Gate driving circuit and driving method therefor, and display apparatus

Abstract

A gate driving circuit and a driving method therefor, and a display apparatus. The gate driving circuit comprises a first gate driving unit and a second gate driving unit, wherein at least one of the first gate driving unit and the second gate driving unit comprises a pull-up node control circuit, an output circuit, a pull-down node control circuit, a first stabilizing circuit and an inductive compensation circuit; the pull-up node control circuit is configured to control an electrical signal of a pull-up node; the output circuit comprises a gate driving output end, and the output circuit is configured to output a composite signal to the gate driving output end under the control of the electrical signal of the pull-up node; the pull-down node control circuit is configured to at least input a first voltage end signal to a pull-down node under the control of the electrical signal of the pull-up node; and the inductive compensation circuit is configured to output an inductive signal under the control of an electrical signal of the pull-down node.

Description

Gate driving circuit and its driving method, display device Cross-references to related applications

[0001] This disclosure claims priority to Chinese patent application No. 202411048537.5, filed on July 31, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to the field of display technology, and to a gate driving circuit, a driving method for the gate driving circuit, and a display device. Background Technology

[0003] In the existing technology, in order to achieve low cost and narrow bezel, most of them adopt GOA (Gate driver on Array) technology, and the gate driver circuit unit is the GOA unit.

[0004] However, in related technologies, some transistors in the gate drive circuit experience characteristic drift such as threshold voltage, making it difficult for the gate drive circuit to accurately output scanning signals. Summary of the Invention

[0005] This disclosure provides a gate driving circuit and its driving method, as well as a display device, through some embodiments, which can solve the problem of difficulty in accurately outputting scanning signals in gate driving circuits in related technologies.

[0006] A first aspect of some embodiments of this disclosure provides a gate driving circuit, including at least one first gate driving unit and a plurality of second gate driving units cascaded with the first gate driving unit. At least one of the first gate driving unit and the second gate driving unit includes a pull-up node control circuit, an output circuit, a pull-down node control circuit, and a first stabilizing circuit. At least one of the first gate driving unit and the second gate driving unit includes an induction compensation circuit. The pull-up node control circuit is configured to control an electrical signal of the pull-up node. The output circuit includes a gate driving output terminal and is configured to output a composite signal to the gate driving output terminal under the control of the electrical signal of the pull-up node. The pull-down node control circuit is configured to input at least a first voltage terminal signal to the pull-down node under the control of the electrical signal of the pull-up node. The induction compensation circuit is configured to output an induction signal under the control of the electrical signal of the pull-down node.

[0007] In some embodiments, both the first gate driving unit and the second gate driving unit include a first stabilizing circuit, and at least one of the first gate driving unit and the second gate driving unit further includes a selection compensation circuit; the selection compensation circuit is at least configured to charge the pull-up control node under the control of a selection compensation control signal and to charge the pull-up node under the control of a first clock signal; the pull-up node control circuit includes a display input sub-circuit, which is configured to input a first power signal to the pull-up node under the control of a charging input signal; the pull-down node control circuit is configured to input a second power signal or the first voltage terminal signal to the pull-down node under the electrical signal control of the pull-up node; the first stabilizing circuit is configured to perform electrical signal control on the pull-up node under the electrical signal control of the pull-down node.

[0008] In some embodiments, the pull-up node control circuit further includes a display protection sub-circuit configured to electrically control the first node under the electrical signal control of the pull-up node; the first node is electrically connected to the first stabilization circuit and the induction compensation circuit; the first stabilization circuit is further configured to electrically control the first node under the electrical signal control of the pull-down node.

[0009] In some embodiments, the inductive compensation circuit includes a first inductive compensation transistor and a second inductive compensation transistor; the gate of the first inductive compensation transistor is electrically connected to the pull-down node, the first terminal of the first inductive compensation transistor outputs the inductive signal, and the second terminal of the first inductive compensation transistor is electrically connected to the first node and the first terminal of the second inductive compensation transistor; the gate of the second inductive compensation transistor is electrically connected to the pull-down node, and the second terminal of the second inductive compensation transistor is connected to a first compensation input signal.

[0010] In some implementations, the first compensation input signal is a first point clock signal or the selected compensation control signal.

[0011] In some embodiments, the inductive compensation circuit further includes a third inductive compensation transistor and a fourth inductive compensation transistor; the gate of the third inductive compensation transistor is connected to a second point clock signal, the first electrode of the third inductive compensation transistor is electrically connected to the pull-down node, and the second electrode of the third inductive compensation transistor is electrically connected to the second electrode of the fourth inductive compensation transistor, the gate of the first inductive compensation transistor, and the gate of the second inductive compensation transistor; the gate of the fourth inductive compensation transistor is connected to the first compensation input signal, and the first electrode of the fourth inductive compensation transistor is connected to a second compensation input signal.

[0012] In some implementations, the first compensation input signal is a first point clock signal or a selection compensation control signal; the second compensation input signal is the second power supply signal or a third point clock signal.

[0013] In some embodiments, the display input sub-circuit includes a first display input transistor, a second display input transistor, and a third display input transistor; the gate of the first display input transistor is connected to the charging input signal, the first terminal of the first display input transistor is connected to the first power supply signal, and the second terminal of the first display input transistor is electrically connected to the first terminal of the second display input transistor and the first terminal of the third display input transistor; the gate of the second display input transistor is connected to the charging input signal, and the second terminal of the second display input transistor is electrically connected to the pull-up node; the gate of the third display input transistor is electrically connected to the pull-down node, and the second terminal of the third display input transistor is connected to the first power supply signal.

[0014] In some embodiments, the pull-down node control circuit includes a first reverse control transistor, a second reverse control transistor, a third reverse control transistor, a fourth reverse control transistor, and a fifth reverse control transistor; the gate of the first reverse control transistor is connected to the second power supply signal, the first terminal of the first reverse control transistor is connected to the second power supply signal, and the second terminal of the first reverse control transistor is electrically connected to the first terminal of the second reverse control transistor; the gate of the second reverse control transistor is connected to the second power supply signal, and the second terminal of the second reverse control transistor is electrically connected to the first terminal of the third reverse control transistor and the gate of the fourth reverse control transistor; the gate of the third reverse control transistor is electrically connected to the pull-up node, and the second terminal of the third reverse control transistor is connected to a second voltage terminal signal; the first terminal of the fourth reverse control transistor is connected to the second power supply signal, and the second terminal of the fourth reverse control transistor is electrically connected to the first terminal of the fifth reverse control transistor and the pull-down node; the gate of the fifth reverse control transistor is electrically connected to the pull-up node, and the second terminal of the fifth reverse control transistor is connected to the first voltage terminal signal.

[0015] In some embodiments, the pull-down node control circuit further includes a sixth inverting control transistor; the gate of the sixth inverting control transistor is connected to a second clock signal, the first terminal of the sixth inverting control transistor is electrically connected to the second terminal of the fourth inverting control transistor and the pull-down node, and the second terminal of the sixth inverting control transistor is electrically connected to the first terminal of the fifth inverting control transistor.

[0016] In some embodiments, the pull-down node control circuit further includes a seventh inverting control transistor; the gate of the seventh inverting control transistor is connected to a second clock signal, the first terminal of the seventh inverting control transistor is electrically connected to the second terminal of the second inverting control transistor, and the second terminal of the seventh inverting control transistor is electrically connected to the first terminal of the third inverting control transistor.

[0017] In some embodiments, the display protection sub-circuit includes a first protection transistor and a second protection transistor; the gate of the first protection transistor is electrically connected to the pull-up node, the first terminal of the first protection transistor is connected to the first power signal, and the second terminal of the first protection transistor is electrically connected to the first terminal of the second protection transistor; the gate of the second protection transistor is electrically connected to the pull-up node, and the second terminal of the second protection transistor is electrically connected to the first node.

[0018] In some embodiments, the pull-up node control circuit further includes a display reset sub-circuit; the display reset sub-circuit is configured to electrically control the pull-up node under the control of a display reset signal.

[0019] In some embodiments, the display reset sub-circuit includes a first display reset transistor and a second display reset transistor; the gate of the first display reset transistor is connected to the display reset signal, the first terminal of the first display reset transistor is electrically connected to the pull-up node, and the second terminal of the first display reset transistor is electrically connected to the first terminal of the second display reset transistor and the first node; the gate of the second display reset transistor is connected to the display reset signal, and the second terminal of the second display reset transistor is electrically connected to the first voltage terminal signal.

[0020] In some embodiments, the selection compensation circuit includes a charging sub-circuit, a storage sub-circuit, and an isolation sub-circuit; the charging sub-circuit is configured to input the charging input signal to the pull-up control node under the control of the selection compensation control signal; the storage sub-circuit is configured to store the charging input signal input by the charging sub-circuit; and the isolation sub-circuit is configured to input the charging input signal to the pull-up node under the control of the electrical signal of the pull-up control node and a first clock signal.

[0021] In some embodiments, the charging sub-circuit includes a first charging transistor, a second charging transistor, a first capacitor, and a third charging transistor; the storage sub-circuit includes a second capacitor; the isolation sub-circuit includes a first isolation transistor and a second isolation transistor; the gate of the first charging transistor is connected to the selection compensation control signal, the gate of the first charging transistor is also electrically connected to the first plate of the first capacitor, the first terminal of the first charging transistor is connected to the charging input signal, and the second terminal of the first charging transistor is electrically connected to the first terminal of the second charging transistor and the first terminal of the third charging transistor; the gate of the second charging transistor is connected to the selection compensation control signal, the gate of the second charging transistor is also electrically connected to the first plate of the first capacitor, and the second terminal of the second charging transistor is electrically connected to the gate of the third charging transistor, the second plate of the first capacitor, the gate of the first isolation transistor, and the second plate of the second capacitor; the second terminal of the third charging transistor is electrically connected to the first plate of the second capacitor and the first terminal of the first isolation transistor, and the second terminal of the third charging transistor is also connected to the first power supply signal; the second terminal of the first isolation transistor is electrically connected to the first terminal of the second isolation transistor; the gate of the second isolation transistor is connected to the first clock signal, and the second terminal of the second isolation transistor is electrically connected to the pull-up node.

[0022] In some embodiments, the first stabilizing circuit includes a first stabilizing transistor and a second stabilizing transistor; the gate of the first stabilizing transistor is electrically connected to the pull-down node, the first electrode of the first stabilizing transistor is electrically connected to the pull-up node, and the second electrode of the first stabilizing transistor is electrically connected to the first node and the first electrode of the second stabilizing transistor; the gate of the second stabilizing transistor is electrically connected to the pull-down node, and the second electrode of the second stabilizing transistor is connected to the first voltage terminal signal.

[0023] In some embodiments, at least one of the first gate driving unit and the second gate driving unit further includes a second stabilizing circuit; the second stabilizing circuit is configured to electrically control the pull-up node under the control of a total reset signal.

[0024] In some embodiments, the second stabilizing circuit includes a third stabilizing transistor and a fourth stabilizing transistor; the gate of the third stabilizing transistor is connected to the total reset signal, the first terminal of the third stabilizing transistor is electrically connected to the pull-up node, and the second terminal of the third stabilizing transistor is electrically connected to the first node and the first terminal of the fourth stabilizing transistor; the gate of the fourth stabilizing transistor is connected to the total reset signal, and the second terminal of the fourth stabilizing transistor is connected to the first voltage terminal signal.

[0025] In some embodiments, at least one of the first gate driving unit and the second gate driving unit further includes a pull-down circuit, the pull-down circuit being configured to control the gate driving output terminal with an electrical signal under the control of the electrical signal of the pull-down node; at least one of the first gate driving unit and the second gate driving unit further includes a pull-down node stabilization circuit, the pull-down node stabilization circuit being configured to control the electrical signal of the pull-down node under the control of a first clock signal, an electrical signal of a pull-up control node, and the charging input signal.

[0026] In some embodiments, the output circuit includes an output transistor and a third capacitor; the pull-down circuit includes a pull-down transistor; the pull-down node stabilization circuit includes a first pull-down node stabilizing transistor, a second pull-down node stabilizing transistor, and a third pull-down node stabilizing transistor; the gate of the output transistor is electrically connected to the pull-up node and the first plate of the third capacitor, the first terminal of the output transistor is connected to an output clock signal, and the second terminal of the output transistor is electrically connected to the second plate of the third capacitor, the gate drive output terminal, and the first terminal of the pull-down transistor; the gate of the pull-down transistor is electrically connected to the pull-down node, and the second terminal of the pull-down transistor is connected to the first voltage terminal signal. The gate of the first pull-down node stabilizing transistor is connected to the first clock signal, the first terminal of the first pull-down node stabilizing transistor is electrically connected to the pull-down node, and the second terminal of the second pull-down node stabilizing transistor is electrically connected to the first terminal of the second pull-down node stabilizing transistor; the gate of the second pull-down node stabilizing transistor is electrically connected to the pull-up control node, and the second terminal of the second pull-down node stabilizing transistor is connected to the first voltage terminal signal; the gate of the third pull-down node stabilizing transistor is connected to the charging input signal, the first terminal of the third pull-down node stabilizing transistor is electrically connected to the pull-down node, and the second terminal of the third pull-down node stabilizing transistor is connected to the first voltage terminal signal.

[0027] A second aspect of some embodiments of this disclosure provides a driving method for a gate driving circuit, applied to the gate driving circuit described in any one of the above embodiments, comprising: acquiring a first sensing signal through a sensing compensation circuit in a blanking stage m, where m is a positive integer; acquiring a second sensing signal through the sensing compensation circuit in a blanking stage m+i, where i is a positive integer; and compensating the difference between the first sensing signal and the second sensing signal to a second power supply signal connected to a pull-down node control circuit.

[0028] A third aspect of some embodiments of this disclosure provides a display device including the gate driving circuit described in any one of the above embodiments.

[0029] In some embodiments of this disclosure, at least one of the first gate driving unit and the second gate driving unit is provided with an induction compensation circuit. The induction compensation circuit is configured to output an induction signal under the control of the electrical signal of the pull-down node. The difference between the induction signals output at different times can be used to obtain the change in the threshold voltage of at least some transistors in the induction compensation circuit, thereby reflecting the change in the threshold voltage (Vth) of at least some other transistors in the first gate driving unit and / or the second gate driving unit. The change in the threshold voltage (Vth) of the transistors is compensated to the first gate driving unit and / or the second gate driving unit, thereby accurately driving at least some other transistors in the first gate driving unit and / or the second gate driving unit. This allows the first gate driving unit and / or the second gate driving unit to output a precise composite signal at the gate driving output terminal. At the same time, it can avoid the different electrodes (gate, first electrode, or second electrode) of at least some other transistors in the first gate driving unit and / or the second gate driving unit from being in a state of non-preset voltage difference for a long time, thereby improving the reliability of transistors such as lifespan, thereby achieving the effect of improving the reliability of the gate driving circuit such as lifespan. For example, at least some transistors in the first gate driving unit and / or the second gate driving unit have the same voltage environment (gate, first electrode, or second electrode voltage) as at least some transistors in the inductive compensation circuit; for example, at least some transistors in the first gate driving unit and / or the second gate driving unit are connected to the same pull-down node as at least some transistors in the inductive compensation circuit, so that the change in the threshold voltage (Vth) of at least some other transistors in the first gate driving unit and / or the second gate driving unit can be reflected by the change in the threshold voltage of at least some transistors in the inductive compensation circuit. By compensating for this change in threshold voltage, the first gate driving unit and / or the second gate driving unit can output a precise composite signal at the gate driving output terminal, thereby improving the reliability of transistors such as lifespan, and thus achieving the effect of improving the reliability of the gate driving circuit such as lifespan. Attached Figure Description

[0030] Figure 1 is a schematic diagram of a first structural block of a gate driving unit of a gate driving circuit provided in some embodiments of this disclosure;

[0031] Figure 2 is a schematic diagram of a second structural block of a gate driving unit of a gate driving circuit provided in some embodiments of this disclosure;

[0032] Figure 3 is a schematic diagram of a third structure of a gate driving unit of a gate driving circuit provided in some embodiments of this disclosure;

[0033] Figure 4 is a schematic diagram of a first type of gate driving unit of a gate driving circuit provided in some embodiments of this disclosure;

[0034] Figure 5 is a second circuit diagram of a gate driving unit of a gate driving circuit provided in some embodiments of this disclosure;

[0035] Figure 6 is a third circuit diagram of a gate driving unit of a gate driving circuit provided in some embodiments of this disclosure;

[0036] Figure 7 is a fourth circuit diagram of a gate driving unit of a gate driving circuit provided in some embodiments of this disclosure;

[0037] Figure 8 is a fifth circuit diagram of a gate driving unit of a gate driving circuit provided in some embodiments of this disclosure;

[0038] Figure 9 is a sixth circuit diagram of a gate driving unit of a gate driving circuit provided in some embodiments of this disclosure;

[0039] Figure 10 is a seventh circuit diagram of a gate driving unit of a gate driving circuit provided in some embodiments of this disclosure;

[0040] Figure 11 is a schematic diagram of the cascade of multiple gate driving units in a first type of gate driving circuit provided in some embodiments of this disclosure;

[0041] Figure 12 is a schematic diagram of the driving timing of a first type of gate driving circuit provided in some embodiments of this disclosure;

[0042] Figure 13 is an eighth circuit diagram of a gate driving unit of a gate driving circuit provided in some embodiments of this disclosure;

[0043] Figure 14 is a ninth circuit diagram of a gate driving unit of a gate driving circuit provided in some embodiments of this disclosure.

[0044] Figure 15 is a tenth circuit diagram of a gate driving unit of a gate driving circuit provided in some embodiments of this disclosure.

[0045] Figure 16 is an eleventh circuit diagram of a gate driving unit of a gate driving circuit provided in some embodiments of this disclosure;

[0046] Figure 17 is a schematic diagram of the twelfth type of gate driving unit of a gate driving circuit provided in some embodiments of the present disclosure;

[0047] Figure 18 is a thirteenth circuit diagram of a gate driving unit of a gate driving circuit provided in some embodiments of this disclosure.

[0048] Figure 19 is a schematic diagram of the cascade of multiple gate driving units in a second type of gate driving circuit provided in some embodiments of this disclosure;

[0049] Figure 20 is a schematic diagram of the driving timing of a second type of gate driving circuit provided in some embodiments of this disclosure;

[0050] Figure 21 is a schematic flowchart of a driving method for a gate driving circuit provided in some embodiments of this disclosure;

[0051] Figure 22 is a schematic diagram of the blanking stage of a gate driving circuit or the compensation process of a pixel driving circuit provided in some embodiments of this disclosure. Detailed Implementation

[0052] To better understand the technical solutions provided in the embodiments of this specification, the technical solutions of the embodiments of this specification will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the embodiments of this specification and the specific features in the embodiments are detailed descriptions of the technical solutions of the embodiments of this specification, rather than limitations on the technical solutions of this specification. In the absence of conflict, the embodiments of this specification and the technical features in the embodiments can be combined with each other.

[0053] In this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, without necessarily requiring or implying any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. The term "two or more" includes two or more cases.

[0054] In related technologies, some transistors in the gate drive circuit experience characteristic drift (change) such as threshold voltage, which makes it difficult for the gate drive circuit to accurately output scanning signals and also leads to a decrease in the reliability of the gate drive circuit, such as its lifespan.

[0055] In related technologies, external compensation via gate drive circuits is commonly used to increase device consistency. However, this compensation method is prone to producing compensation lines or increasing product bezels. For example, the external compensation drive signal consists of a row shift signal and a frame shift signal. The signal during the blanking time of a frame is the frame shift signal. Frame shift is further divided into sequential frame shift and random frame shift. In the sequential frame shift compensation method, the gate drive circuit can output drive signals to pixels row by row to compensate the transistors of the pixel drive circuit. In the random frame shift compensation method, the gate drive circuit can output compensation drive signals to any row of pixels in any frame to compensate the transistors of the pixel drive circuit. However, the sequential frame shift compensation method is prone to producing compensation lines, resulting in poor display.

[0056] In view of the above, this disclosure provides a gate driving circuit and driving method thereof, as well as a display device, which can improve or solve at least one of the above problems.

[0057] This disclosure provides a gate driving circuit, including at least one first gate driving unit and a plurality of second gate driving units cascaded with the first gate driving unit. At least one of the first gate driving unit and the second gate driving units includes a pull-up node control circuit, an output circuit, a pull-down node control circuit and a first stabilizing circuit.

[0058] At least one of the first gate driving unit and the second gate driving unit includes a sensing compensation circuit;

[0059] The pull-up node control circuit is configured to control the electrical signals of the pull-up node;

[0060] The output circuit includes a gate drive output terminal, and the output circuit is configured to output a composite signal to the gate drive output terminal under the electrical signal control of the pull-up node.

[0061] The pull-down node control circuit is configured to input at least a first voltage terminal signal to the pull-down node under the electrical signal control of the pull-up node;

[0062] The induction compensation circuit is configured to output an induction signal under the control of the electrical signal of the pull-down node.

[0063] This disclosure also provides a driving method for a gate driving circuit, applied to the gate driving circuit described above.

[0064] This disclosure also provides a display device including the gate driving circuit described above.

[0065] In the following detailed description, different embodiments are described in order to better illustrate the inventive spirit of this disclosure, but the description of different embodiments is not intended to limit the combination of different implementations or features in this disclosure.

[0066] Please refer to Figures 1 to 3. Figure 1 is a schematic diagram of a first structural block of a gate driving unit of a gate driving circuit provided in some embodiments of the present disclosure; Figure 2 is a schematic diagram of a second structural block of a gate driving unit of a gate driving circuit provided in some embodiments of the present disclosure; and Figure 3 is a schematic diagram of a third structural block of a gate driving unit of a gate driving circuit provided in some embodiments of the present disclosure.

[0067] Please refer to Figures 4 to 10. Figure 4 is a first circuit diagram of a gate driving unit of a gate driving circuit provided in some embodiments of this disclosure; Figure 5 is a second circuit diagram of a gate driving unit of a gate driving circuit provided in some embodiments of this disclosure; Figure 6 is a third circuit diagram of a gate driving unit of a gate driving circuit provided in some embodiments of this disclosure; Figure 7 is a fourth circuit diagram of a gate driving unit of a gate driving circuit provided in some embodiments of this disclosure; Figure 8 is a fifth circuit diagram of a gate driving unit of a gate driving circuit provided in some embodiments of this disclosure; Figure 9 is a sixth circuit diagram of a gate driving unit of a gate driving circuit provided in some embodiments of this disclosure; and Figure 10 is a seventh circuit diagram of a gate driving unit of a gate driving circuit provided in some embodiments of this disclosure.

[0068] Please refer to Figures 11 and 12. Figure 11 is a schematic diagram of the cascade of multiple gate driving units of a first type of gate driving circuit provided in some embodiments of the present disclosure; Figure 12 is a schematic diagram of the driving timing of a first type of gate driving circuit provided in some embodiments of the present disclosure.

[0069] Please refer to Figures 13 to 18. Figure 13 is an eighth circuit diagram of a gate driving unit of a gate driving circuit provided in some embodiments of this disclosure; Figure 14 is a ninth circuit diagram of a gate driving unit of a gate driving circuit provided in some embodiments of this disclosure; Figure 15 is a tenth circuit diagram of a gate driving unit of a gate driving circuit provided in some embodiments of this disclosure; Figure 16 is an eleventh circuit diagram of a gate driving unit of a gate driving circuit provided in some embodiments of this disclosure; Figure 17 is a twelfth circuit diagram of a gate driving unit of a gate driving circuit provided in some embodiments of this disclosure; and Figure 18 is a thirteenth circuit diagram of a gate driving unit of a gate driving circuit provided in some embodiments of this disclosure.

[0070] Please refer to Figures 19 and 20. Figure 19 is a schematic diagram of the cascade of multiple gate driving units in a second type of gate driving circuit provided in some embodiments of this disclosure; Figure 20 is a schematic diagram of the driving timing of a second type of gate driving circuit provided in some embodiments of this disclosure.

[0071] Figures 4, 7, 9, 13, 15, and 17 are detailed circuit diagrams of the circuit block diagram in Figure 1, and Figure 5 is a detailed circuit diagram of the circuit block diagram in Figure 2.

[0072] Figures 6, 8, 10, 14, 16, and 18 are detailed circuit diagrams of the circuit block diagram in Figure 3.

[0073] Figure 11 is a schematic diagram of the cascade of multiple gate driving units in the example circuits of Figures 4 to 10; Figure 12 illustrates a driving timing of the example circuits of Figures 4 to 10 or Figure 11.

[0074] Figure 19 is a schematic diagram of the cascade of multiple gate driving units in the example circuits of Figures 13 to 18; Figure 20 illustrates a driving timing sequence of the example circuits of Figures 13 to 18 or Figure 19.

[0075] This disclosure provides a gate driving circuit 2000, which includes at least one first gate driving unit 1001 and a plurality of second gate driving units 1002 cascaded with the first gate driving unit 1001. At least one of the first gate driving unit 1001 and the second gate driving unit 1002 includes a pull-up node control circuit 200, an output circuit 300, a pull-down node control circuit 400, and a first stabilizing circuit 500. At least one of the first gate driving unit 1001 and the second gate driving unit 1002 includes an induction compensation circuit 900; the pull-up node control circuit 200 is configured to control the electrical signal of the pull-up node Q; the output circuit 300 includes a gate driving output terminal CR, and the output circuit 300 is configured to output a composite signal to the gate driving output terminal CR under the control of the electrical signal of the pull-up node Q; the pull-down node control circuit 400 is configured to input at least a first voltage terminal signal VGL1 to the pull-down node QB under the control of the electrical signal of the pull-up node Q; and the induction compensation circuit 900 is configured to output an induction signal Se under the control of the electrical signal of the pull-down node QB.

[0076] For example, in some embodiments, the gate drive circuit 2000 includes a plurality of gate drive units 1000 (shift registers, GOA units), the plurality of gate drive units 1000 including at least one first gate drive unit 1001 and at least one second gate drive unit 1002, the first gate drive unit 1001 being cascaded with the first gate drive unit 1001.

[0077] For example, in some embodiments, one of the first gate driving unit 1001 and the second gate driving unit 1002 is a dummy gate driving unit (Dummy GOA) and the other is a cascading gate driving unit. In some embodiments of this disclosure, the first gate driving unit 1001 is a dummy gate driving unit and the second gate driving unit 1002 is a cascading gate driving unit as an example, but it is not limited thereto.

[0078] For example, in some embodiments, the display panel or display device includes a display area and a non-display area. The display panel includes a plurality of pixel driving circuits disposed in the display area. The pixel driving circuits can drive the light-emitting units to perform display. The display panel can be an OLED (Organic Light-Emitting Diode) display panel, and the display device can be an OLED (Organic Light-Emitting Diode) display device. In this case, the light-emitting unit is a light-emitting device.

[0079] For example, in some embodiments, the first gate driving unit 1001 may include one or more output circuits 300 (CR in the schematic diagram). <n>The gate drive output terminal CR of the nth gate drive unit (where n or N is an integer greater than 0) is represented. The first gate drive unit 1001 may include one or more gate drive output terminals CR. The second gate drive unit 1002 may include one or more output circuits 300. The second gate drive unit 1002 may include one or more gate drive output terminals CR.

[0080] For example, in some implementations, the signal output by the gate drive output terminal CR of the cascade gate drive unit can be a gate drive signal (scan drive signal), which can be provided to the pixel drive circuit; the signal output by the gate drive output terminal CR of the cascade gate drive unit can also include a cascade signal.

[0081] For example, in some embodiments, the composite signal may include a display output signal and a blanking output signal. During the display phase of a frame, the output circuit 300 outputs the display output signal to the gate drive output terminal CR under the control of the level of the pull-up node Q. In some embodiments, the gate drive output terminal CR may include a shift signal output terminal and a pixel signal output terminal. The display output signal (stage transmission signal) output from the shift signal output terminal can be used for scanning shift of the upper and lower level gate drive units 1000, while the display output signal (gate drive signal, or scan drive signal) output from the pixel signal output terminal can be used to drive the sub-pixels (pixel drive circuits) in the display panel to perform scanning display. In some embodiments, during the blanking phase between two adjacent frames (or the blanking phase of a frame), the output circuit 300 outputs the blanking output signal to the gate drive output terminal CR under the control of the level of the pull-up node Q. This blanking output signal can be used to compensate the pixel drive circuit.

[0082] For example, in some implementations, the signal output by the gate drive output terminal CR of the dummy gate drive unit can be a cascade signal, which can be provided to the next stage, the previous stage, or other cascaded gate drive units 1000.

[0083] For example, in some implementations, the pull-up node control circuit 200 controls the electrical signal of the pull-up node Q, the electrical signal of the pull-up node Q controls the electrical signal of the gate drive output terminal CR through the output circuit 300, the electrical signal of the pull-up node Q controls the electrical signal of the pull-down node QB, and the pull-down node QB controls the induction signal Se output by the induction compensation circuit 900.

[0084] For example, if the pull-down node QB is at a high potential for a long time, the transistor whose gate is electrically connected to the pull-down node QB is in the on state for a long time, and the transistor whose gate is electrically connected to the pull-down node QB is in the bias voltage state for a long time, a significant threshold voltage shift will occur. Therefore, by setting the induction compensation circuit 900 to output an induction signal Se under the control of the electrical signal of the pull-down node QB, the transistor in the gate drive unit 1000 with a significant threshold voltage shift can be detected. Then, this threshold voltage change can be compensated to the gate drive unit 1000, which can efficiently and accurately improve the accuracy of the output voltage of the gate drive unit at the gate drive output terminal CR, and efficiently and accurately improve the reliability of the transistor, such as its lifespan, thereby achieving the effect of improving the reliability of the gate drive circuit.

[0085] In some embodiments of this disclosure, at least one induction compensation circuit 900 is provided in the first gate driving unit 1001 and the second gate driving unit 1002. The induction compensation circuit 900 is configured to output an induction signal Se under the control of the electrical signal of the pull-down node QB. The difference between the induction signals Se output at different times can be used to obtain the change in the threshold voltage of at least some transistors in the induction compensation circuit 900, thereby reflecting the change in the threshold voltage (Vth) of at least some other transistors in the first gate driving unit 1001 or / and the second gate driving unit 1002, and compensating the change in the threshold voltage (Vth) of the transistors to the first gate driving unit 1001 or / and the second gate driving unit 1002. The dual gate driving unit 1002 can precisely drive at least some of the other transistors of the first gate driving unit 1001 or / and the second gate driving unit 1002, thereby enabling the first gate driving unit 1001 or / and the second gate driving unit 1002 to output a precise composite signal at the gate driving output terminal CR. At the same time, it can prevent the different electrodes (gate, first electrode, or second electrode) of at least some of the other transistors of the first gate driving unit 1001 or / and the second gate driving unit 1002 from being in a state of non-preset voltage difference for a long time, thereby improving the reliability of transistors such as lifespan, and thus achieving the effect of improving the reliability of gate driving circuits such as lifespan. For example, at least some transistors in the first gate driving unit 1001 or / and the second gate driving unit 1002 have the same voltage environment (gate, first terminal, or second terminal voltage) as at least some transistors in the induction compensation circuit 900; for example, at least some transistors in the first gate driving unit 1001 or / and the second gate driving unit 1002 and at least some transistors in the induction compensation circuit 900 are electrically connected to the pull-down node QB, so that the change in the threshold voltage of at least some transistors in the first gate driving unit 1001 or / and the second gate driving unit 1002 can reflect the change in the threshold voltage (Vth) of at least some other transistors in the first gate driving unit 1001 or / and the second gate driving unit 1002. By compensating for this change in threshold voltage, the first gate driving unit 1001 or / and the second gate driving unit 1002 can output a precise composite signal at the gate driving output terminal CR, thereby improving the reliability of transistors such as lifespan, and thus achieving the effect of improving the reliability of the gate driving circuit such as lifespan.

[0086] In some embodiments, both the first gate driving unit 1001 and the second gate driving unit 1002 include a first stabilizing circuit 500, and at least one of the first gate driving unit 1001 and the second gate driving unit 1002 further includes a selection compensation circuit 100. The selection compensation circuit 100 is configured to charge the pull-up control node P under the control of the selection compensation control signal OE, and to charge the pull-up node Q under the control of the first clock signal CKA; the pull-up node control circuit 200 includes a display input sub-circuit 201, which is configured to input a first power supply signal GVDD1 to the pull-up node Q under the control of the charging input signal STU; the pull-down node control circuit 400 is configured to input a second power supply signal GVDD2 or a first voltage terminal signal VGL1 to the pull-down node QB under the electrical signal control of the pull-up node Q; the first stabilizing circuit 500 is configured to perform electrical signal control on the pull-up node Q under the electrical signal control of the pull-down node QB.

[0087] For example, in some embodiments, at least one of the first gate driving unit 1001 and the second gate driving unit 1002 is a cascaded gate driving unit, which includes a selection compensation circuit 100.

[0088] For example, in some embodiments, at least one of the first gate driving unit 1001 and the second gate driving unit 1002 is a dummy gate driving unit, which may not include the selection compensation circuit 100.

[0089] For example, in some other embodiments, the dummy gate drive unit may also include a selection compensation circuit 100.

[0090] For example, the induction compensation circuit 900 is configured to output an induction signal Se under the control of the electrical signal of the pull-down node QB, and the pull-down node control circuit 400 is configured to input a second power supply signal GVDD2 or a first voltage terminal signal VGL1 to the pull-down node QB under the control of the electrical signal of the pull-up node Q, so that at least some electrodes of at least some transistors in the pull-down node control circuit 400 and the induction compensation circuit 900 have the same voltage environment (voltage of the gate, the first electrode, or the second electrode). By reflecting the change in the threshold voltage of at least some transistors in the induction compensation circuit 900 through the difference of the induction signal Se output at different times, the change in the threshold voltage of at least some transistors in the pull-down node control circuit 400 can be understood, and signal compensation can be made for the change in threshold voltage.

[0091] For example, the selection compensation control signal OE can be configured to be provided by a control circuit that can provide the selection compensation circuit 100 with an on or off selection compensation control signal OE. For example, in one example, this control circuit can be implemented as an FPGA (Field Programmable Gate Array) device or other signal generation circuit (e.g., a timing controller).

[0092] For example, as shown in Figure 11, in the gate drive circuit 2000, for example, except for the first-stage gate drive unit, the charging input signal STU of the k-th stage gate drive unit is provided by a gate drive output terminal CR of the preceding stage gate drive unit (e.g., the (k-1)-th stage gate drive unit, where k-1 is an integer greater than 0) (the input terminal of the charging input signal of the k-th stage gate drive unit is electrically connected to a gate drive output terminal CR of the preceding stage gate drive unit). For example, except for the first-stage and second-stage gate drive units, the charging input signal STU of the k-th stage gate drive unit is provided by a gate drive output terminal CR of the preceding stage gate drive unit (e.g., the (k-2)-th stage gate drive unit, where k-2 is an integer greater than 0) (the input terminal of the charging input signal of the k-th stage gate drive unit is electrically connected to a gate drive output terminal CR of the preceding stage gate drive unit). For example, Figure 11 illustrates that the charging input signal STU of the first-stage gate drive unit GOA1 is provided by a gate drive output terminal CR of the first dummy gate drive unit DUM1 (the input terminal of the charging input signal of the first-stage gate drive unit GOA1 is electrically connected to the gate drive output terminal CR of the first dummy gate drive unit DUM1). For example, Figure 11 illustrates that the charging input signal STU of the second-stage gate drive unit GOA2 is provided by a gate drive output terminal CR of the second dummy gate drive unit DUM2 (the input terminal of the charging input signal of the second-stage gate drive unit GOA2 is electrically connected to the gate drive output terminal CR of the second dummy gate drive unit DUM2).

[0093] In some embodiments, the pull-up node control circuit 200 further includes a display protection sub-circuit 202, which is configured to control the first node QH with an electrical signal under the control of the pull-up node Q; the first node QH is electrically connected to the first stabilization circuit 500 and the induction compensation circuit 900; the first stabilization circuit 500 is further configured to control the first node QH with an electrical signal under the control of the pull-down node QB.

[0094] For example, the first node QH is electrically connected to the first stabilization circuit 500 and the induction compensation circuit 900, such that at least some electrodes of at least some transistors in the first stabilization circuit 500 and the induction compensation circuit 900 have the same voltage environment (voltage of the gate, the first electrode, or the second electrode). By reflecting the change in the threshold voltage of at least some transistors in the induction compensation circuit 900 through the difference of the induction signal Se output at different times, the change in the threshold voltage of at least some transistors in the first stabilization circuit 500 can be understood, and signal compensation can be made for the change in threshold voltage.

[0095] In some embodiments, as shown in Figures 4 to 10, the induction compensation circuit 900 includes a first induction compensation transistor M1 and a second induction compensation transistor M2; the gate of the first induction compensation transistor M1 is electrically connected to a pull-down node QB, the first terminal of the first induction compensation transistor M1 outputs an induction signal Se, the second terminal of the first induction compensation transistor M1 is electrically connected to a first node QH and the first terminal of the second induction compensation transistor M2; the gate of the second induction compensation transistor M2 is electrically connected to the pull-down node QB, and the second terminal of the second induction compensation transistor M2 is connected to a first compensation input signal.

[0096] It should be noted that, in this disclosure, when the transistor is a thin-film transistor or a field-effect transistor, the transistor includes a gate, a source, and a drain. In the schematic diagram, the upper part is the first terminal of the transistor and the lower part is the second terminal, or the left side is the first terminal and the right side is the second terminal. The first terminal of the transistor is one of the source and drain of the transistor, and the second terminal is the other of the source and drain of the transistor. Moreover, depending on the setting of high and low levels in the specific circuit and the different types and characteristics of the transistors, the source and drain of each transistor can be completely or partially interchanged. This is easily implemented by those skilled in the art according to the specific application scenario, and will not be elaborated here.

[0097] For example, as shown in Figures 4 to 10, the gate of the first inductive compensation transistor M1 is electrically connected to the pull-down node QB, the gate of the second inductive compensation transistor M2 is electrically connected to the pull-down node QB, the second electrode of the first inductive compensation transistor M1 is electrically connected to the first node QH, and the first electrode of the second inductive compensation transistor M2 is electrically connected to the pull-down node QB; the gate of the first stable transistor T20 is electrically connected to the pull-down node QB, the second electrode of the first stable transistor T20 is electrically connected to the first node QH, and the gate of the second stable transistor T21 is electrically connected to the pull-down node QB; this ensures that the first inductive compensation transistor M1 and / or the second inductive compensation transistor M2 have the same voltage environment (gate, first electrode, or second electrode voltage) as the first stable transistor T20 and / or the second stable transistor T21. By detecting the change in the threshold voltage of the first inductive compensation transistor M1 and / or the second inductive compensation transistor M2, the change in the threshold voltage of the first stable transistor T20 and / or the second stable transistor T21 can be accurately reflected, improving the accuracy of threshold voltage detection, thereby enabling precise signal compensation for changes in threshold voltage.

[0098] For example, as shown in Figures 4 to 10, the induction compensation circuit 900 includes a first induction compensation transistor M1 and a second induction compensation transistor M2, which has the advantages of small transistor count, simple structure, and narrow bezel.

[0099] For example, as shown in Figures 4 to 10, in response to the electrical signal of the pull-down node QB, the first inductive compensation transistor M1 and the second inductive compensation transistor M2 can be turned on, transmitting the first compensation input signal as an inductive signal Se. In some embodiments, when the pull-down node QB is a high-level signal, the first inductive compensation transistor M1 and the second inductive compensation transistor M2 are turned on, transmitting the first compensation input signal as an inductive signal Se.

[0100] For example, as shown in Figures 4 to 10, setting the low potential of the first compensation input signal (e.g., the low potential signal of the first point clock signal DCLK1) to be the same as the first voltage terminal signal VGL1 (same voltage) can better ensure that the first sensing compensation transistor M1 or / and the second sensing compensation transistor M2 have the same voltage environment (gate, first electrode, or second electrode voltage) as the first stable transistor T20 or / and the second stable transistor T21. By detecting the change in the threshold voltage of the first sensing compensation transistor M1 or / and the second sensing compensation transistor M2, the change in the threshold voltage of the first stable transistor T20 or / and the second stable transistor T21 can be reflected more accurately, improving the accuracy of threshold voltage detection, thereby enabling precise signal compensation for changes in threshold voltage.

[0101] For example, as shown in Figures 4 to 10, the working principle of the induction compensation circuit 900 is illustrated by the following example: by acquiring the first induction signal and the second induction signal through two detections, the change in the threshold voltage of the first induction compensation transistor M1 and the second induction compensation transistor M2 can be obtained.

[0102] The first detection acquires the first sensing signal, based on the principle of Formula 1 below. Here, Vs1 represents the voltage of the first sensing signal, V_(GVDD2) represents the voltage of the second power supply signal GVDD2, Vth1_T16 represents the threshold voltage of the fourth reverse control transistor T16 during the first detection, Vth1_T13 represents the threshold voltage of the first reverse control transistor T13 during the first detection, and Vthmax1_(M1,M2) represents the maximum threshold voltage between the first sensing compensation transistor M1 and the second sensing compensation transistor M2 during the first detection. For example, Vthmax1_(M1,M2) can be the threshold voltage of the second sensing compensation transistor M2.

[0103] Formula 1, Vs1=V_(GVDD2)-Vth1_T16-Vth1_T13–Vthmax1_(M1,M2).

[0104] The second detection acquires the second sensing signal. The principle is as follows: Formula 2 below. In this formula, Vs2 represents the voltage of the second sensing signal, V_(GVDD2) represents the voltage of the second power supply signal GVDD2, Vth2_T16 represents the threshold voltage of the fourth reverse control transistor T16 during the second detection, Vth2_T13 represents the threshold voltage of the first reverse control transistor T13 during the second detection, and Vthmax2_(M1,M2) represents the maximum threshold voltage between the first sensing compensation transistor M1 and the second sensing compensation transistor M2 during the second detection. For example, Vthmax1_(M1,M2) can be the threshold voltage of the second sensing compensation transistor M2.

[0105] Formula 2, Vs2=V_(GVDD2)-Vth2_T16-Vth2_T13–Vthmax2_(M1,M2).

[0106] For example, since the fourth reverse control transistor T16 is affected by PBTS (positive bias temperature stress, where the gate voltage is greater than the source voltage) most of the time, the threshold voltage of the fourth reverse control transistor T16 can be assumed to be constant. Therefore, the voltage difference between the two detected sensing signals is the change of the second sensing compensation transistor M2, thereby obtaining the change of the threshold voltage of the first sensing compensation transistor M1 or / and the second sensing compensation transistor M2, which can then be compensated in the gate drive unit 1000, for example, by compensating the second power supply signal.

[0107] For example, assuming the threshold voltage of the second inductive compensation transistor M2 is larger (the threshold voltage of the first inductive compensation transistor M1 is smaller), for the first inductive compensation transistor M1, Vgs-Vth>Vds, where Vgs is the gate-source level difference of the transistor, Vth is the threshold voltage of the transistor, and Vds is the drain-source level difference of the transistor. The first inductive compensation transistor M1 operates in the linear region, and the voltage of the first node QH is equal to the voltage of the induced signal Se. In this case, the threshold voltage of the second inductive compensation transistor M2 is used in the above formula. Assuming the threshold voltage of the first inductive compensation transistor M1 is larger (the threshold voltage of the second inductive compensation transistor M2 is smaller), the first compensation input signal will lose part after passing through the second inductive compensation transistor M2, and will continue to lose more after passing through the first inductive compensation transistor M1. In this case, the threshold voltage of the first inductive compensation transistor M1 is used in the above formula.

[0108] For example, by comparing the voltage difference between the first sensing signal and the second sensing signal, the change in the threshold voltage of the first sensing compensation transistor M1 and / or the second sensing compensation transistor M2 during the first detection and the second detection can be obtained.

[0109] In some implementations, as shown in Figures 4 to 10, the first compensation input signal is a first point clock signal DCLK1 or a selection compensation control signal OE.

[0110] For example, in some embodiments, as shown in Figures 4 to 8, the first compensation input signal is a first point clock signal DCLK1. By inputting the first point clock signal DCLK1 or the first point clock signal separately to the induction compensation circuit 900, the accuracy of the induction signal S2 output by the induction compensation circuit 900 can be improved.

[0111] For example, in some implementations, as shown in Figures 9 and 10, the first compensation input signal is a selection compensation control signal OE. By setting the selection compensation control signal OE as the first compensation input signal, the number of traces providing electrical signals in the gate drive circuit can be reduced, the layout area of ​​the gate drive circuit can be reduced, and this contributes to a narrow bezel.

[0112] Referring to Figure 11, in some embodiments, the gate driving circuit 2000 includes a plurality of gate driving units 1000 (shift registers, GOA units), and the gate driving circuit 2000 includes n (n is a positive integer) cascaded gate driving units. Each cascaded gate driving unit may include an output circuit 300 or a gate driving output terminal CR. The gate driving circuit 2000 can drive n rows of pixels. In some embodiments, the gate driving circuit 2000 includes n (n is a positive integer), and each cascaded gate driving unit may include r (r is a positive integer greater than 1, for example, r equals 4) output circuits 300 or r gate driving output terminals CR. The gate driving circuit 2000 can drive n×r rows of pixels. In some embodiments, in a cascaded gate driving unit, one output circuit 300 may include one or more gate driving output terminals CR.

[0113] Referring to Figure 11, in some embodiments, the gate drive circuit 2000 includes a plurality of gate drive units 1000 (shift registers, GOA units), and the gate drive circuit 2000 includes one or more dummy gate drive units. In some embodiments, the gate drive circuit 2000 includes one or more preceding stage dummy gate drive units. Figure 11 illustrates that two preceding stage dummy gate drive units, namely the first dummy gate drive unit DUM1 and the second dummy gate drive unit DUM2, are provided before the first stage gate drive unit GOA1. In some embodiments, the gate drive circuit 2000 includes one or more subsequent stage dummy gate drive units. Figure 11 illustrates that two subsequent stage dummy gate drive units, namely the third dummy gate drive unit DUM3 and the fourth dummy gate drive unit DUM4, are provided after the nth stage gate drive unit GOAn. In some embodiments, the gate drive circuit 2000 includes one or more preceding stage dummy gate drive units and one or more subsequent stage dummy gate drive units. Figure 11 illustrates that two preceding stage dummy gate drive units, namely the first dummy gate drive unit DUM1 and the second dummy gate drive unit DUM2, are provided before the first stage gate drive unit GOA1, and two subsequent stage dummy gate drive units, namely the third dummy gate drive unit DUM3 and the fourth dummy gate drive unit DUM4, are provided after the nth stage gate drive unit GOAn. In some embodiments, the gate drive circuit 2000 may include only one or more preceding stage dummy gate drive units. In some embodiments, the gate drive circuit 2000 may include only one or more subsequent stage dummy gate drive units.

[0114] For example, Figure 11 illustrates a gate drive circuit 2000 including n-stage gate drive units, such as the first-stage gate drive unit GOA1, the second-stage gate drive unit GOA2, and the nth-stage gate drive unit GOAn. Figure 11 also illustrates a gate drive circuit 2000 including four dummy gate drive units, such as the first dummy gate drive unit DUM1, the second dummy gate drive unit DUM2, the third dummy gate drive unit DUM3, and the fourth dummy gate drive unit DUM4.

[0115] For example, Figure 11 illustrates that the first dummy gate drive unit DUM1, the second dummy gate drive unit DUM2, the first stage gate drive unit GOA1, the second stage gate drive unit GOA2 to the nth stage gate drive unit GOAn, the third dummy gate drive unit DUM3 and the fourth dummy gate drive unit DUM4 are arranged or cascaded in sequence, where n is an integer greater than 0.

[0116] For example, Figure 11 illustrates multiple sub-clock signal lines that provide corresponding clock signals and other electrical signals to the gate drive circuit. For instance, Figure 11 illustrates the first sub-clock line CLKE1, the second sub-clock line CLK2, the third sub-clock line CLKE3, the fourth sub-clock line CLKE4, the fifth sub-clock line CLKE5, the sixth sub-clock line CLKE6, the seventh sub-clock line CLKE7, the eighth sub-clock line CLKE8, the ninth sub-clock line CLKE9, the tenth sub-clock line CLKE10, the eleventh sub-clock line CLKE11, and the twelfth sub-clock line CLKE12.

[0117] For example, in some embodiments, FIG11 illustrates that an induction compensation circuit 900 is disposed in at least one dummy gate driving unit. On one hand, the dummy gate driving unit obtains the change in the threshold voltage (Vth) of the transistor in the gate driving unit 1000 through the induction compensation circuit 900, and compensates the gate driving unit 1000 for the change in the threshold voltage (Vth), thereby accurately driving the other transistors in the gate driving unit 1000, enabling the gate driving unit 1000 to output a precise composite signal at the gate driving output terminal CR. On the other hand, it avoids the long-term non-preset voltage difference between different electrodes (gate, first electrode, or second electrode) of the other transistors in the gate driving unit 1000, thereby improving the reliability of the transistors, such as lifespan, and thus achieving the effect of improving the reliability of the gate driving circuit. On the other hand, the dummy gate driving unit obtains the change in the threshold voltage (Vth) of the transistor in the gate driving unit through the induction compensation circuit 900, without interfering with the operation of the cascaded gate driving unit, and without interfering with the precise output of the composite signal at the gate driving output terminal CR of the cascaded gate driving unit.

[0118] For example, in some other embodiments, the induction compensation circuit 900 is disposed in at least one stage gate drive unit.

[0119] For example, in some other embodiments, the induction compensation circuit 900 is disposed in at least one dummy gate driving unit, and at the same time, another induction compensation circuit 900 is disposed in at least one cascade gate driving unit. The induction compensation circuit 900 in the dummy gate driving unit can be selected to operate, or the induction compensation circuit 900 in the cascade gate driving unit can be selected to operate.

[0120] In some embodiments, as shown in Figures 13 to 18, the induction compensation circuit 900 further includes a third induction compensation transistor M3 and a fourth induction compensation transistor M4; the gate of the third induction compensation transistor M3 is connected to the second point clock signal DCLK2, the first electrode of the third induction compensation transistor M3 is electrically connected to the pull-down node QB, and the second electrode of the third induction compensation transistor M3 is electrically connected to the second electrode of the fourth induction compensation transistor M4, the gate of the first induction compensation transistor M1, and the gate of the second induction compensation transistor M2; the gate of the fourth induction compensation transistor M4 is connected to the first compensation input signal, and the first electrode of the fourth induction compensation transistor M4 is connected to the second compensation input signal.

[0121] For example, as shown in Figures 13 to 18, the induction compensation circuit 900 is configured to output an induction signal Se under the control of the electrical signal of the pull-down node QB and the second point clock signal DCLK2.

[0122] For example, as shown in Figures 13 to 18, the induction compensation circuit 900 includes a first induction compensation transistor M1 and a second induction compensation transistor M2, as well as a third induction compensation transistor M3 and a fourth induction compensation transistor M4. The gate of the first induction compensation transistor M1 is electrically connected to a pull-down node QB, and the first terminal of the first induction compensation transistor M1 outputs an induction signal Se. The second terminal of the first induction compensation transistor M1 is electrically connected to the first node QH and the first terminal of the second induction compensation transistor M2. The gate of the second induction compensation transistor M2 is electrically connected to the pull-down node QB, and the second terminal of the second induction compensation transistor M2 is connected to a first compensation input signal. The gate of the third induction compensation transistor M3 is connected to a second clock signal, and the first terminal of the third induction compensation transistor M3 is electrically connected to the pull-down node QB. The second terminal of the third induction compensation transistor M3 is electrically connected to the second terminal of the fourth induction compensation transistor M4, the gate of the first induction compensation transistor M1, and the gate of the second induction compensation transistor M2. The gate of the fourth induction compensation transistor M4 is connected to the first compensation input signal, and the first terminal of the fourth induction compensation transistor M4 is connected to a second compensation input signal.

[0123] For example, the working principle of the induction compensation circuit 900 shown in Figures 13 to 18 (the principle of acquiring threshold voltage change) is the same as that of the circuit shown in Figures 4 to 10. The difference is that when detecting or acquiring the induction signal Se, the gate voltage of the first induction compensation transistor M1 and the second induction compensation transistor M2 is the voltage of the second point clock signal DCLK2, which will not be described in detail here.

[0124] For example, as shown in Figures 13 to 18, during the display phase (e.g., when the gate drive output terminal CR outputs a high-level signal), in response to the electrical signal of the second point clock signal DCLK2, the third inductive compensation transistor M3 is turned on, and the electrical signal of the pull-down node QB acts on (transmitted to) the first inductive compensation transistor M1 and the second inductive compensation transistor M2, such that the first inductive compensation transistor M1 and / or the second inductive compensation transistor M2 have the same or substantially the same voltage environment (gate, first electrode, or second electrode voltage) as the first stable transistor T20 and / or the second stable transistor T21. In some embodiments, during the display phase (e.g., when the gate drive output terminal CR outputs a high-level signal), the second point clock signal DCLK2 is high, the third inductive compensation transistor M3 is turned on, and the electrical signal of the pull-down node QB acts on (transmitted to) the first inductive compensation transistor M1 and the second inductive compensation transistor M2, such that the first inductive compensation transistor M1 and / or the second inductive compensation transistor M2 have the same voltage environment (gate, first electrode, or second electrode voltage) as the first stable transistor T20 and / or the second stable transistor T21.

[0125] For example, as shown in Figures 13 to 18, during the blanking phase (when acquiring the sensing signal Se), in response to the electrical signal of the second clock signal DCLK2, the third sensing compensation transistor M3 is turned off, and in response to the second compensation input signal, the first sensing compensation transistor M1 and the second sensing compensation transistor M2 can be turned on, transmitting the first compensation input signal as the sensing signal Se. In some embodiments, during the blanking phase (when acquiring the sensing signal Se), the second clock signal DCLK2 is a low-level signal, the third sensing compensation transistor M3 is turned off, the second compensation input signal is a high-level signal, and the first sensing compensation transistor M1 and the second sensing compensation transistor M2 are turned on, transmitting the first compensation input signal as the sensing signal Se.

[0126] For example, as shown in Figures 13 to 18, setting the low potential of the first compensation input signal (e.g., the low potential signal of the first point clock signal DCLK1) to be the same as the first voltage terminal signal VGL1 (same voltage) can better ensure that the first sensing compensation transistor M1 or / and the second sensing compensation transistor M2 have the same voltage environment (gate, first electrode, or second electrode voltage) as the first stable transistor T20 or / and the second stable transistor T21. By detecting the change in the threshold voltage of the first sensing compensation transistor M1 or / and the second sensing compensation transistor M2, the change in the threshold voltage of the first stable transistor T20 or / and the second stable transistor T21 can be reflected more accurately, improving the accuracy of threshold voltage detection, thereby enabling precise signal compensation for changes in threshold voltage.

[0127] For example, as shown in Figures 13 to 18, by setting a third inductive compensation transistor M3 and a fourth inductive compensation transistor M4, on the one hand, during the display phase (e.g., when the gate drive output terminal CR outputs a high-level signal), in response to the electrical signal of the second point clock signal DCLK2, the third inductive compensation transistor M3 is turned on, and the electrical signal of the pull-down node QB acts on (transmitted to) the first inductive compensation transistor M1 and the second inductive compensation transistor M2, so that the first inductive compensation transistor M1 and / or the second inductive compensation transistor M2 have the same voltage environment (gate, first electrode, or second electrode voltage) as the first stable transistor T20 and / or the second stable transistor T21; on the other hand, in During the blanking phase (when acquiring the sensing signal Se), in response to the second clock signal DCLK2, the third sensing compensation transistor M3 is turned off. In response to the second compensation input signal, the first sensing compensation transistor M1 and the second sensing compensation transistor M2 can be turned on, transmitting the first compensation input signal as the sensing signal Se. The gates of the first sensing compensation transistor M1 and the second sensing compensation transistor M2 are unaffected by the electrical signal of the pull-down node QB. The first sensing compensation transistor M1 and the second sensing compensation transistor M2 are turned on by the second compensation input signal. For example, even when the electrical signal of the pull-down node QB is unstable, a precise sensing signal Se can still be obtained, improving the accuracy of the sensing signal Se acquisition. Furthermore, the fourth sensing compensation transistor M4 is turned on under the control of the first compensation input signal DCLK1, thereby controlling the second compensation input signal to ensure that the first sensing compensation transistor M1 and the second sensing compensation transistor M2 can be turned on. This avoids the situation where the gates of the first sensing compensation transistor M1 and the second sensing compensation transistor M2 are in a floating state due to the third sensing compensation transistor M3 being turned off, making it difficult to turn on stably.

[0128] For example, as shown in Figures 13 to 18, setting the low potential of the first compensation input signal (e.g., the low potential signal of the first point clock signal DCLK1) to be the same as the first voltage terminal signal (same voltage) can better ensure that the first sensing compensation transistor M1 or / and the second sensing compensation transistor M2 have the same voltage environment (gate, first electrode, or second electrode voltage) as the first stable transistor T20 or / and the second stable transistor T21. By detecting the change in the threshold voltage of the first sensing compensation transistor M1 or / and the second sensing compensation transistor M2, the change in the threshold voltage of the first sensing compensation transistor M1 or / and the second sensing compensation transistor M2 can be reflected more accurately, improving the accuracy of threshold voltage detection, thereby enabling precise signal compensation for changes in threshold voltage.

[0129] In some implementations, as shown in Figures 13 to 20, the first compensation input signal is a first point clock signal DCLK1 or a selection compensation control signal OE; the second compensation input signal is a second power supply signal GVDD2 or a third point clock signal DCLK3.

[0130] For example, in some embodiments, as shown in Figures 13 and 14, 19 and 20, the first compensation input signal is a first point clock signal DCLK1, and the second compensation input signal is a third point clock signal DCLK3. By inputting the first point clock signal DCLK1 and the third point clock signal DCLK3 separately into the induction compensation circuit 900, the accuracy of the induction signal S2 output by the induction compensation circuit 900 can be improved.

[0131] For example, in some implementations, as shown in Figures 15 and 16, and Figures 19 and 20, the first compensation input signal is the selection compensation control signal OE, and the second compensation input signal is the third-point clock signal DCLK3. By setting the selection compensation control signal OE as the first compensation input signal, the number of traces providing electrical signals in the gate drive circuit can be reduced, the layout area of ​​the gate drive circuit can be reduced, and this contributes to a narrow bezel.

[0132] For example, in some embodiments, as shown in Figures 17 and 18, 19 and 20, the first compensation input signal is a selection compensation control signal OE, and the second compensation input signal is a second power supply signal GVDD2. By setting the selection compensation control signal OE as the first compensation input signal and the second power supply signal GVDD2 as the second compensation input signal, the number of traces providing electrical signals in the gate drive circuit can be further reduced, the layout area of ​​the gate drive circuit can be reduced, and this contributes to a narrow bezel.

[0133] It should be noted that the cascading relationship of the multiple gate drive units 1000 in Figure 20, the output signal and number of the gate drive output terminal CR, the selection compensation control signal OE, and the setting of the charging input signal STU are the same as or similar to those in Figure 11, and will not be repeated here.

[0134] It should be noted that, compared to Figure 11, the number of electrical signals connected to the induction compensation circuit 900 in Figure 19 is different. Figure 19 illustrates, for example, that the induction compensation circuit 900 is located in at least one dummy gate drive unit. Figure 19 illustrates, for example, that the first compensation input signal is the first point clock signal DCLK1, the second compensation input signal is the third point clock signal DCLK3, and the induction compensation circuit 900 also connects to a second point clock signal DCLK2. For example, the first compensation input signal is the first point clock signal DCLK1, and the second compensation input signal is the third point clock signal DCLK3. Both can be synchronously high-level, for example, in the XT3 stage of the blanking phase. The second point clock signal DCLK2 is low-level when the first point clock signal DCLK1 is high-level, for example, in the XT3 stage of the blanking phase.

[0135] In some embodiments, the display input sub-circuit 201 includes a first display input transistor T6, a second display input transistor T7, and a third display input transistor T8; the gate of the first display input transistor T6 is connected to a charging input signal STU, the first terminal of the first display input transistor T6 is connected to a first power supply signal GVDD1, and the second terminal of the first display input transistor T6 is electrically connected to the first terminals of the second display input transistor T7 and the third display input transistor T8; the gate of the second display input transistor T7 is connected to the charging input signal STU, and the second terminal of the second display input transistor T7 is electrically connected to a pull-up node Q; the gate of the third display input transistor T8 is electrically connected to a pull-down node QB, and the second terminal of the third display input transistor T8 is connected to the first power supply signal GVDD1.

[0136] For example, the first display input transistor T6 and the second display input transistor T7 are relatively large (the semiconductor layer is relatively large), and the current in the first display input transistor T6 and the second display input transistor T7 is relatively large. The display input sub-circuit 201 adds a third display input transistor T8, which is smaller (the semiconductor layer is relatively small), and the current in the third display input transistor T8 is smaller. Since the first display input transistor T6 and the second display input transistor T7 are larger than the third display input transistor T8, the potential of the pull-down node QB remains high for a longer period. When the third display input transistor T8 is turned on, the first power signal GVDD1 can be transmitted through the third display input transistor T8, reducing the current in the second display input transistor T7 and reducing the threshold voltage drift of the second display input transistor T7. When the second display input transistor T7 is turned off, it can be better shut down and leakage can be prevented.

[0137] For example, in response to the charging input signal STU, the first display input transistor T6 and the second display input transistor T7 can be turned on, thereby transmitting the first power supply signal GVDD1 to the pull-up node Q. In some embodiments, the first display input transistor T6 and the second display input transistor T7 are turned on when the charging input signal STU is high.

[0138] In some embodiments, as shown in Figures 13 and 14, the pull-down node control circuit 400 includes a first inverting control transistor T13, a second inverting control transistor T14, a third inverting control transistor T15, a fourth inverting control transistor T16, and a fifth inverting control transistor T17. The gate of the first inverting control transistor T13 is connected to a second power supply signal GVDD2, the first terminal of the first inverting control transistor T13 is connected to the second power supply signal GVDD2, and the second terminal of the first inverting control transistor T13 is electrically connected to the first terminal of the second inverting control transistor T14. The gate of the second inverting control transistor T14 is connected to the second power supply signal GVDD2, and the second inverting control transistor T15 is electrically connected to the first terminal of the second inverting control transistor T16. The second terminal of transistor T14 is electrically connected to the first terminal of the third reverse control transistor T15 and the gate of the fourth reverse control transistor T16; the gate of the third reverse control transistor T15 is electrically connected to the pull-up node Q, and the second terminal of the third reverse control transistor T15 is connected to the second voltage terminal signal VGL2; the first terminal of the fourth reverse control transistor T16 is connected to the second power supply signal GVDD2, and the second terminal of the fourth reverse control transistor T16 is electrically connected to the first terminal of the fifth reverse control transistor T17 and the pull-down node QB; the gate of the fifth reverse control transistor T17 is electrically connected to the pull-up node Q, and the second terminal of the fifth reverse control transistor T17 is connected to the first voltage terminal signal VGL1.

[0139] For example, the second terminal of the second reverse control transistor T14 and the gate of the fourth reverse control transistor T16 are electrically connected to the first sub-node F1.

[0140] For example, in response to the second power supply signal GVDD2, the first inverting control transistor T13 and the second inverting control transistor T14 can be turned on to transmit the second power supply signal GVDD2 to the first child node F1.

[0141] For example, in response to the electrical signal of the pull-up node Q, the third inverting control transistor T15 can be turned on, transmitting the second voltage terminal signal VGL2 to the first child node F1. In some embodiments, when the pull-up node Q is at a high potential, the third inverting control transistor T15 is turned on, thereby discharging or resetting the first child node F1 to the second voltage terminal signal VGL2.

[0142] For example, in response to the electrical signal of the first child node F1, the fourth inverting control transistor T16 can be turned on, thereby transmitting the second power supply signal GVDD2 to the pull-down node QB. In some embodiments, the fourth inverting control transistor T16 is turned on when the first child node F1 is at a high potential, thereby transmitting the second power supply signal GVDD2 to the pull-down node QB.

[0143] For example, in response to the electrical signal at the pull-up node Q, the fifth inverting control transistor T17 can be turned on, transmitting the first voltage terminal signal VGL1 to the pull-down node QB. In some embodiments, when the pull-up node Q is at a high potential, the fifth inverting control transistor T17 is turned on, thereby discharging or resetting the pull-down node QB to the first voltage terminal signal VGL1.

[0144] For example, in some implementations, the first power signal GVDD1 and the second power signal GVDD2 can be high-level signals, and the potentials of the first power signal GVDD1 and the second power signal GVDD2 can be the same or different; the first voltage terminal signal VGL1 and the second voltage terminal signal VGL2 can be low-level signals, and the potentials of the first voltage terminal signal VGL1 and the second voltage terminal signal VGL2 can be the same or different.

[0145] For example, in some implementations, the voltage of the first power signal GVDD1 is greater than the voltage of the second power signal GVDD2, and the voltage of the first voltage terminal signal VGL1 is greater than the voltage of the second voltage terminal signal VGL2.

[0146] In some implementations, as shown in Figures 4 and 6, the pull-down node control circuit 400 further includes a sixth inverting control transistor T31; the gate of the sixth inverting control transistor T31 is connected to the second point clock signal DCKL2, the first terminal of the sixth inverting control transistor T31 is electrically connected to the second terminal of the fourth inverting control transistor T16 and the pull-down node QB, and the second terminal of the sixth inverting control transistor T31 is electrically connected to the first terminal of the fifth inverting control transistor T17.

[0147] For example, as shown in Figures 4 and 6, the pull-down node control circuit 400 includes a first reverse control transistor T13, a second reverse control transistor T14, a third reverse control transistor T15, a fourth reverse control transistor T16, a fifth reverse control transistor T17, and a sixth reverse control transistor T31.

[0148] For example, in response to the electrical signal at the pull-up node Q, the fifth inverting control transistor T17 can be turned on, and in response to the second clock signal DCKL2, the sixth inverting control transistor T31 can be turned on, transmitting the first voltage terminal signal VGL1 to the pull-down node QB. In some embodiments, when the pull-up node Q is at a high potential and the second clock signal DCKL2 is at a high potential, the fifth inverting control transistor T17 and the sixth inverting control transistor T31 are turned on, thereby discharging or resetting the pull-down node QB to the first voltage terminal signal VGL1.

[0149] For example, referring to Figures 4 and 12, the pull-down node control circuit 400 includes a sixth inverting control transistor T31. When it is necessary to start detecting the threshold voltage of the first sensing compensation transistor M1 and the second sensing compensation transistor M2, since the second power supply signal GVDD2 is transmitted to the first sensing compensation transistor M1 and the second sensing compensation transistor M2, it needs to pass through the fourth inverting control transistor T16 and is also affected by the fifth inverting control transistor T17 (compared to not setting the sixth inverting control transistor T31). At this time, the sixth inverting control transistor T31 is turned off under the control of the low potential signal of the second point clock signal DCKL2 (to prevent the potential of the pull-up node Q from being unstable) and isolates the influence of the fifth inverting control transistor T17 on the electrical signal of the pull-down node QB, thereby improving the accuracy of the sensing compensation circuit 900 in detecting the threshold voltage.

[0150] For example, referring to Figures 4 and 12, the pull-down node control circuit 400 includes a sixth inverting control transistor T31. When the induction compensation circuit 900 is set in the dummy gate driving unit, during the display phase, the second point clock signal DCKL2 is at a high potential, which does not affect the normal potential of the pull-down node QB of the dummy gate driving unit. During the blanking phase, when it is necessary to start detecting the threshold voltage of the first induction compensation transistor M1 and the second induction compensation transistor M2, since the second power supply signal GVDD2 is transmitted to the first induction compensation transistor M1 and the second induction compensation transistor M2, it needs to pass through the fourth inverting control transistor T16 and is also affected by the fifth inverting control transistor T17 (compared to not setting the sixth inverting control transistor T31). At this time, the sixth inverting control transistor T31 is turned off under the control of the low potential signal of the second point clock signal DCKL2 (to prevent the potential of the pull-up node Q from being unstable) and isolates the influence of the fifth inverting control transistor T17 on the electrical signal of the pull-down node QB, thereby improving the accuracy of the induction compensation circuit 900 in detecting the threshold voltage.

[0151] For example, as shown in Figures 4 and 12, when the pull-up node Q is at a low potential for a long time, the threshold voltage of the fifth reverse control transistor T17 is prone to negative drift, making it easy for the fifth reverse control transistor T17 to leak current. By adding the sixth reverse control transistor T31, the threshold voltage of the sixth reverse control transistor T31 is less likely to drift under the control of the second clock signal DCKL2, and the sixth reverse control transistor T31 can be turned off effectively, thereby preventing the fifth reverse control transistor T17 from leaking current.

[0152] In some implementations, as shown in Figures 7 and 8, the pull-down node control circuit 400 further includes a seventh inverting control transistor T32; the gate of the seventh inverting control transistor T32 is connected to the second point clock signal DCKL2, the first terminal of the seventh inverting control transistor T32 is electrically connected to the second terminal of the second inverting control transistor T14, and the second terminal of the seventh inverting control transistor T32 is electrically connected to the first terminal of the third inverting control transistor T15.

[0153] For example, as shown in Figures 7 and 8, the pull-down node control circuit 400 includes a first reverse control transistor T13, a second reverse control transistor T14, a third reverse control transistor T15, a fourth reverse control transistor T16, a fifth reverse control transistor T17, a sixth reverse control transistor T31, and a seventh reverse control transistor T32.

[0154] For example, as shown in Figures 7 and 8, the second terminal of the second reverse control transistor T14 and the gate of the fourth reverse control transistor T16 are electrically connected to the first sub-node F1.

[0155] For example, as shown in Figures 7 and 8, in response to the second power supply signal GVDD2, the first inverting control transistor T13 and the second inverting control transistor T14 can be turned on to transmit the second power supply signal GVDD2 to the first child node F1.

[0156] For example, as shown in Figures 7 and 8, in response to the electrical signal of the pull-up node Q, the third inverting control transistor T15 can be turned on, and in response to the second clock signal DCKL2, the seventh inverting control transistor T32 can be turned on, transmitting the second voltage terminal signal VGL2 to the first child node F1. In some embodiments, when the pull-up node Q is at a high potential and the second voltage terminal signal VGL2 is at a high potential, the third inverting control transistor T15 and the seventh inverting control transistor T32 are turned on, thereby discharging or resetting the first child node F1 to the second voltage terminal signal VGL2.

[0157] For example, as shown in Figures 7 and 8, in response to the electrical signal of the first child node F1, the fourth inverting control transistor T16 can be turned on, thereby transmitting the second power supply signal GVDD2 to the pull-down node QB. In some embodiments, when the first child node F1 is at a high potential, the fourth inverting control transistor T16 is turned on, thereby transmitting the second power supply signal GVDD2 to the pull-down node QB.

[0158] For example, as shown in Figures 7 and 8, in response to the electrical signal of the pull-up node Q, the fifth inverting control transistor T17 can be turned on, and in response to the second clock signal DCKL2, the sixth inverting control transistor T31 can be turned on, transmitting the first voltage terminal signal VGL1 to the pull-down node QB. In some embodiments, when the pull-up node Q is at a high potential and the second clock signal DCKL2 is at a high potential, the fifth inverting control transistor T17 and the sixth inverting control transistor T31 are turned on, thereby discharging or resetting the pull-down node QB to the first voltage terminal signal VGL1.

[0159] For example, referring to Figures 7 and 12, when it is necessary to start detecting the threshold voltage of the first inductive compensation transistor M1 and the second inductive compensation transistor M2, since the second power supply signal GVDD2 is transmitted to the first inductive compensation transistor M1 and the second inductive compensation transistor M2, it needs to pass through the fourth reverse control transistor T16. The gate of the fourth reverse control transistor T16 is easily affected by the third reverse control transistor T15. At this time, the seventh reverse control transistor T32 is turned off under the control of the low potential signal of the second clock signal DCKL2, which isolates the electrical signal influence of the third reverse control transistor T15 on the gate of the fourth reverse control transistor T16, thereby improving the accuracy of the inductive compensation circuit 900 in detecting the threshold voltage.

[0160] For example, if the pull-up node Q is at a low potential for a long time, the threshold voltage of the third reverse control transistor T15 is prone to negative drift, making it easy for the third reverse control transistor T15 to leak current. By adding a seventh reverse control transistor T32, the threshold voltage of the seventh reverse control transistor T32 is less likely to drift under the control of the second clock signal DCKL2, and the seventh reverse control transistor T32 can be turned off effectively, thereby preventing the third reverse control transistor T15 from leaking current.

[0161] For example, referring to Figures 7 and 12, the pull-down node control circuit 400 includes a seventh inverting control transistor T32. When the induction compensation circuit 900 is set in the dummy gate driving unit, during the display phase, the second point clock signal DCKL2 is at a high potential, which does not affect the normal potential of the pull-down node QB of the dummy gate driving unit. During the blanking phase, when it is necessary to start detecting the threshold voltage of the first induction compensation transistor M1 and the second induction compensation transistor M2, since the second power supply signal GVDD2 is transmitted to the first induction compensation transistor M1 and the second induction compensation transistor M2, it needs to pass through the fourth inverting control transistor T16. The gate of the fourth inverting control transistor T16 is easily affected by the third inverting control transistor T15. At this time, the seventh inverting control transistor T32 is turned off under the control of the low potential signal of the second point clock signal DCKL2, which isolates the electrical signal influence of the third inverting control transistor T15 on the gate of the fourth inverting control transistor T16, thereby improving the accuracy of the induction compensation circuit 900 in detecting the threshold voltage.

[0162] For example, referring to Figures 7 and 12, the pull-down node control circuit 400 includes a seventh inverting control transistor T32 and a sixth inverting control transistor T31. When it is necessary to start detecting the threshold voltage of the first sensing compensation transistor M1 and the second sensing compensation transistor M2, since the second power supply signal GVDD2 is transmitted to the first sensing compensation transistor M1 and the second sensing compensation transistor M2, it needs to pass through the fourth inverting control transistor T16. The transmitted electrical signal is easily affected by the fifth inverting control transistor T17 (compared to not having the sixth inverting control transistor T31). The gate of the fourth inverting control transistor T16 is easily affected by... The influence of the third reverse control transistor T15 (compared to not having the seventh reverse control transistor T32) is that the sixth reverse control transistor T31 is turned off under the low potential signal control of the second clock signal DCKL2, isolating the electrical signal influence of the fifth reverse control transistor T17 on the pull-down node QB, and the seventh reverse control transistor T32 is turned off under the low potential signal control of the second clock signal DCKL2, isolating the electrical signal influence of the third reverse control transistor T15 on the gate of the fourth reverse control transistor T16, thereby improving the accuracy of the induction compensation circuit 900 in detecting the threshold voltage.

[0163] For example, as shown in Figures 7 and 12, the pull-down node control circuit 400 includes a seventh inverting control transistor T32 and a sixth inverting control transistor T31. When the induction compensation circuit 900 is set in the dummy gate driving unit, during the display stage, the second point clock signal DCKL2 is at a high potential, which does not affect the normal potential of the pull-down node QB of the dummy gate driving unit.

[0164] In some embodiments, the display protection sub-circuit 202 includes a first protection transistor T11 and a second protection transistor T12; the gate of the first protection transistor T11 is electrically connected to the pull-up node Q, the first terminal of the first protection transistor T11 is connected to the first power supply signal GVDD1, and the second terminal of the first protection transistor T11 is electrically connected to the first terminal of the second protection transistor T12; the gate of the second protection transistor T12 is electrically connected to the pull-up node Q, and the second terminal of the second protection transistor T12 is electrically connected to the first node QH.

[0165] For example, when the pull-up node Q is at a high potential, the first protection transistor T11 and the second protection transistor T12 are turned on, which can transmit the electrical signal of the first power supply signal GVDD1 to the first node QH.

[0166] In some embodiments, the pull-up node control circuit 200 further includes a display reset sub-circuit 203; the display reset sub-circuit 203 is configured to electrically control the pull-up node Q under the control of the display reset signal STD.

[0167] For example, as shown in FIG11, in the gate driving circuit 2000, for example, except for the last stage gate driving unit, the display reset signal STD of the (k-1)th stage gate driving unit (k-1 is an integer greater than 0) is provided by a gate drive output terminal CR of the subsequent stage gate driving unit (e.g., the kth stage gate driving unit) (the input terminal of the display reset signal of the (k-1)th stage gate driving unit is electrically connected to a gate drive output terminal CR of the subsequent stage gate driving unit). For example, except for the last stage gate driving unit and the last two stage gate driving units, the display reset signal STD of the (k-2)th stage gate driving unit (k-2 is an integer greater than 0) is provided by a gate drive output terminal CR of the subsequent stage gate driving unit (e.g., the kth stage gate driving unit) (the input terminal of the display reset signal of the (k-2)th stage gate driving unit is electrically connected to a gate drive output terminal CR of the subsequent stage gate driving unit). For example, Figure 11 illustrates that the display reset signal STD of the first dummy gate drive unit DUM1 is provided by a gate drive output terminal CR of the first stage gate drive unit GOA1 (the input terminal of the display reset signal of the first dummy gate drive unit DUM1 is electrically connected to a gate drive output terminal CR of the first stage gate drive unit GOA1).

[0168] For example, as shown in Figure 11, in the gate drive circuit 2000, the display reset signal STD of at least part of the dummy gate drive unit is provided by the drive chip or control circuit.

[0169] In some embodiments, the display reset sub-circuit 203 includes a first display reset transistor T9 and a second display reset transistor T10; the gate of the first display reset transistor T9 is connected to the display reset signal STD, the first terminal of the first display reset transistor T9 is electrically connected to the pull-up node Q, and the second terminal of the first display reset transistor T9 is electrically connected to the first terminal of the second display reset transistor T10 and the first node QH; the gate of the second display reset transistor T10 is connected to the display reset signal STD, and the second terminal of the second display reset transistor T10 is electrically connected to the first voltage terminal signal VGL1.

[0170] For example, in response to the input of the display reset signal STD, the first display reset transistor T9 and the second display reset transistor T10 can be turned on, discharging the pull-up node Q to the voltage of the first voltage terminal signal VGL1. The discharge of the pull-up node Q to the first voltage terminal signal VGL1 can also be represented as the reset of the pull-up node Q. In some embodiments, when the display reset signal STD is high, the first display reset transistor T9 and the second display reset transistor T10 are turned on, discharging the pull-up node Q to the voltage of the first voltage terminal signal VGL1.

[0171] For example, the second display reset transistor T10 can respond to the input of the display reset signal STD, and the first voltage terminal signal VGL1 can be transmitted to the first node QH. In some embodiments, when the display reset signal STD is high, the second display reset transistor T10 is turned on, and the first voltage terminal signal VGL1 can be transmitted to the first node QH.

[0172] In some embodiments, the selection compensation circuit 100 includes a charging sub-circuit 101, a storage sub-circuit 102, and an isolation sub-circuit 103; the charging sub-circuit 101 is configured to input the charging input signal STU to the pull-up control node P under the control of the selection compensation control signal OE; the storage sub-circuit 102 is configured to store the charging input signal STU input by the charging sub-circuit 101; and the isolation sub-circuit 103 is configured to input the charging input signal STU to the pull-up node Q under the control of the electrical signal of the pull-up control node P and the first clock signal CKA.

[0173] In some embodiments, as shown in FIG6, the charging sub-circuit 101 includes a first charging transistor T1, a second charging transistor T2, a first capacitor C1, and a third charging transistor T3; the storage sub-circuit 102 includes a second capacitor C2; the isolation sub-circuit 103 includes a first isolation transistor T4 and a second isolation transistor T5; the gate of the first charging transistor T1 is connected to the selection compensation control signal OE, the gate of the first charging transistor T1 is also electrically connected to the first plate of the first capacitor C1, the first terminal of the first charging transistor T1 is connected to the charging input signal STU, and the second terminal of the first charging transistor T1 is electrically connected to the first terminal of the second charging transistor T2 and the first terminal of the third charging transistor T3; the gate of the second charging transistor T2 is connected to the selection... The compensation control signal OE is applied. The gate of the second charging transistor T2 is also electrically connected to the first plate of the first capacitor C1. The second terminal of the second charging transistor T2 is electrically connected to the gate of the third charging transistor T3, the second plate of the first capacitor C1, the gate of the first isolation transistor T4, and the second plate of the second capacitor C2. The second terminal of the third charging transistor T3 is electrically connected to the first plate of the second capacitor C2 and the first terminal of the first isolation transistor T4. The second terminal of the third charging transistor T3 is also connected to the first power supply signal GVDD1. The second terminal of the first isolation transistor T4 is electrically connected to the first terminal of the second isolation transistor T5. The gate of the second isolation transistor T5 is connected to the first clock signal CKA. The second terminal of the second isolation transistor T5 is electrically connected to the pull-up node Q.

[0174] For example, in a gate drive unit 1000 including a selection compensation circuit 100, in response to the input of a selection compensation control signal OE, a first charging transistor T1 and a second charging transistor T2 are turned on, a charging input signal STU is input to a pull-up control node P, and an electrical signal is stored in a first capacitor C1 and a second capacitor C2. The pull-up control node P can be charged to a high potential of the charging input signal STU.

[0175] For example, in response to the electrical signal of the pull-up control node P, the third charging transistor T3 can be turned on, and the first power supply signal GVDD1 is input to the pull-up control node P. In some embodiments, when the pull-up control node P is at a high potential, the third charging transistor T3 is turned on, and the first power supply signal GVDD1 is input to the pull-up control node P, further increasing the potential of the pull-up control node P or further improving the stability of the potential of the pull-up control node P, and storing more charge in the first capacitor C1 and the second capacitor C2.

[0176] For example, the first isolation transistor T4 can be turned on in response to a high potential of the pull-up control node P, and the second isolation transistor T5 can be turned on in response to a high potential of the first clock signal CKA. When both the first isolation transistor T4 and the second isolation transistor T5 are turned on, the first power supply signal GVDD1 can be transmitted to the pull-up node Q.

[0177] For example, in the gate drive unit 1000 including the selection compensation circuit 100, the second isolation transistor T5 can be turned off in response to the low potential of the first clock signal CKA, and can maintain the potential of the pull-up node Q.

[0178] In some embodiments, the first stabilizing circuit 500 includes a first stabilizing transistor T20 and a second stabilizing transistor T21; the gate of the first stabilizing transistor T20 is electrically connected to a pull-down node QB, the first electrode of the first stabilizing transistor T20 is electrically connected to a pull-up node Q, the second electrode of the first stabilizing transistor T20 is electrically connected to a first node QH and the first electrode of the second stabilizing transistor T21; the gate of the second stabilizing transistor T21 is electrically connected to the pull-down node QB, and the second electrode of the second stabilizing transistor T21 is connected to a first voltage terminal signal VGL1.

[0179] For example, in response to the electrical signal of the pull-down node QB, the first stabilizing transistor T20 and the second stabilizing transistor T21 can be turned on, transmitting the first voltage terminal signal VGL1 to the pull-up node Q and the first node QH. In some embodiments, when the first voltage terminal signal VGL1 is a low-level signal and the pull-down node QB is a high-level signal, the first stabilizing transistor T20 and the second stabilizing transistor T21 are turned on, discharging or resetting the pull-up node Q and the first node QH to the first voltage terminal signal VGL1.

[0180] In some embodiments, at least one of the first gate driving unit 1001 and the second gate driving unit 1002 further includes a second stabilizing circuit 600; the second stabilizing circuit 600 is configured to electrically control the pull-up node Q under the control of the total reset signal TRS.

[0181] For example, the total reset signal TRS can be configured to be provided by a control circuit or driver chip.

[0182] In some embodiments, the second stabilizing circuit 600 includes a third stabilizing transistor T22 and a fourth stabilizing transistor T23; the gate of the third stabilizing transistor T22 is connected to the total reset signal TRS, the first terminal of the third stabilizing transistor T22 is electrically connected to the pull-up node Q, and the second terminal of the third stabilizing transistor T22 is electrically connected to the first node QH and the first terminal of the fourth stabilizing transistor T23; the gate of the fourth stabilizing transistor T23 is connected to the total reset signal TRS, and the second terminal of the fourth stabilizing transistor T23 is connected to the first voltage terminal signal VGL1.

[0183] For example, in response to the electrical signal of the total reset signal TRS, the third stabilizing transistor T22 and the fourth stabilizing transistor T23 can be turned on, transmitting the first voltage terminal signal VGL1 to the pull-up node Q and the first node QH. In some embodiments, when the total reset signal TRS is a high-level signal, the third stabilizing transistor T22 and the fourth stabilizing transistor T23 are turned on, the first voltage terminal signal VGL1 is transmitted to the pull-up node Q and the first node QH, and the pull-up node Q and the first node QH are discharged or reset to the first voltage terminal signal VGL1.

[0184] In some embodiments, at least one of the first gate driving unit 1001 and the second gate driving unit 1002 further includes a pull-down circuit 700, which is configured to control the gate driving output terminal CR under the control of the electrical signal of the pull-down node QB; at least one of the first gate driving unit 1001 and the second gate driving unit 1002 further includes a pull-down node stabilization circuit 800, which is configured to control the electrical signal of the pull-down node QB under the control of the first clock signal CKA, the electrical signal of the pull-up control node P, and the charging input signal STU.

[0185] For example, in some embodiments, at least one of the first gate driving unit 1001 and the second gate driving unit 1002 further includes a pull-down circuit 700.

[0186] For example, in some embodiments, at least one of the first gate driving unit 1001 and the second gate driving unit 1002 further includes a pull-down node stabilization circuit 800.

[0187] For example, in some embodiments, as shown in Figures 2, 3, 5, 6, 8, 10, 14, 16 and 18, when at least one of the first gate driving unit 1001 and the second gate driving unit 1002 is a cascading gate driving unit, the cascading gate driving unit includes a pull-down node stabilization circuit 800. The pull-down node stabilization circuit 800 is configured to control the electrical signal of the pull-down node QB under the control of the first clock signal CKA, the electrical signal of the pull-up control node P and the charging input signal STU.

[0188] For example, in some embodiments, as shown in Figures 1, 4, 7, 9, 13, 15 and 17, when at least one of the first gate driving unit 1001 and the second gate driving unit 1002 is a dummy gate driving unit, the dummy gate driving unit includes a pull-down node stabilization circuit 800, which is configured to control the electrical signal of the pull-down node QB under the control of the charging input signal STU.

[0189] In some embodiments, the output circuit 300 includes an output transistor T25 and a third capacitor C3; the pull-down circuit 700 includes a pull-down transistor T26; the pull-down node stabilization circuit 800 includes a first pull-down node stabilization transistor T18, a second pull-down node stabilization transistor T19, and a third pull-down node stabilization transistor T24; the gate of the output transistor T25 is electrically connected to the pull-up node Q and the first plate of the third capacitor C3, the first terminal of the output transistor T25 is connected to the output clock signal CLKD1, and the second terminal of the output transistor T25 is electrically connected to the second plate of the third capacitor C3, the gate drive output terminal CR, and the first terminal of the pull-down transistor T26; the gate of the pull-down transistor T26 is electrically connected to the pull-down node QB, and the second terminal of the pull-down transistor T26 is connected to the first plate of the third capacitor C3. The voltage terminal signal is VGL1; the gate of the first pull-down node stabilizing transistor T18 is connected to the first clock signal CKA, the first electrode of the first pull-down node stabilizing transistor T18 is electrically connected to the pull-down node QB, the second electrode of the second pull-down node stabilizing transistor T19 is electrically connected to the first electrode of the second pull-down node stabilizing transistor T19; the gate of the second pull-down node stabilizing transistor T19 is electrically connected to the pull-up control node P, and the second electrode of the second pull-down node stabilizing transistor T19 is connected to the first voltage terminal signal VGL1; the gate of the third pull-down node stabilizing transistor T24 is connected to the charging input signal STU, the first electrode of the third pull-down node stabilizing transistor T24 is electrically connected to the pull-down node QB, and the second electrode of the third pull-down node stabilizing transistor T24 is connected to the first voltage terminal signal VGL1.

[0190] For example, in some embodiments, the induction compensation circuit 900 is disposed in at least one stage gate drive unit. Referring to Figures 2, 3, 5, 6, 8, 10, 14, 16, and 18, the pull-down node stabilization circuit 800 is configured to control the electrical signal of the pull-down node QB under the control of the first clock signal CKA, the electrical signal of the pull-up control node P, and the charging input signal STU. On the one hand, this allows the electrical signal of the pull-down node QB to be controlled more stably and accurately. On the other hand, it makes the electrical signal of the pull-down node QB input to the induction compensation circuit 900 more stable and accurate, improving the stability and accuracy of the composite signal output from the gate drive output terminal CR, and also improving the stability and accuracy of the output induction signal Se under the control of the electrical signal of the pull-down node QB.

[0191] For example, in some embodiments, as shown in conjunction with Figures 2, 3, 5, 6, 8, 10, 14, 16, and 18, and also in conjunction with Figure 11 or 12, when at least one of the first gate driving unit 1001 and the second gate driving unit 1002 is a cascaded gate driving unit, the pull-down node stabilization circuit 800 includes a first pull-down node stabilization transistor T18, a second pull-down node stabilization transistor T19, and a third pull-down node stabilization transistor T24.

[0192] For example, referring to Figures 2, 3, 5, 6, 8, 10, 14, 16, and 18, and also to Figure 11 or 12, in response to the charging input signal STU, the third pull-down node stabilizing transistor T24 can be turned on, transmitting the first voltage terminal signal VGL1 to the pull-down node QB. In response to the first clock signal CKA, the first pull-down node stabilizing transistor T18 can be turned on, and in response to the pull-up control node P, the second pull-down node stabilizing transistor T19 can be turned on, transmitting the first voltage terminal signal VGL1 to the pull-down node QB. In some embodiments, when the charging input signal STU is high, the first voltage terminal signal VGL1 is transmitted to the pull-down node QB. In some embodiments, when the electrical signals of the first clock signal CKA and the pull-up control node P are high, the first pull-down node stabilizing transistor T18 and the second pull-down node stabilizing transistor T19 are turned on, transmitting the first voltage terminal signal VGL1 to the pull-down node QB.

[0193] For example, in some other embodiments, as shown in Figures 1, 4, 7, 9, 13, 15, and 17, and referring to Figure 11 or 19, the induction compensation circuit 900 is disposed in at least one dummy gate driving unit. On one hand, the dummy gate driving unit obtains the change in the threshold voltage (Vth) of the transistor in the gate driving unit 1000 through the induction compensation circuit 900, and compensates the gate driving unit 1000 for the change in the threshold voltage (Vth), thereby accurately driving the other transistors in the gate driving unit 1000, enabling the gate driving unit 1000 to output a precise composite signal at the gate driving output terminal CR. On the other hand, it can prevent the different electrodes (gate, first electrode, or second electrode) of the other transistors in the gate driving unit 1000 from being in a state of non-preset voltage difference for a long time, thereby improving the reliability of the transistors, such as lifespan, and thus achieving the effect of improving the reliability of the gate driving circuit, such as lifespan. In three aspects, the virtual gate drive unit obtains the change of the threshold voltage (Vth) of the transistor in the gate drive unit 1000 through the induction compensation circuit 900, which will not interfere with the operation of the stage-transmitted gate drive unit, nor will it interfere with the accurate composite signal output of the gate drive output terminal CR of the stage-transmitted gate drive unit.

[0194] For example, in some other embodiments, as shown in Figures 1, 4, 7, 9, 13, 15 and 17, when at least one of the first gate driving unit 1001 and the second gate driving unit 1002 is a dummy gate driving unit, the pull-down node stabilization circuit 800 includes a third pull-down node stabilization transistor T24. The gate of the third pull-down node stabilization transistor T24 is connected to the charging input signal STU, the first electrode of the third pull-down node stabilization transistor T24 is electrically connected to the pull-down node QB, and the second electrode of the third pull-down node stabilization transistor T24 is connected to the first voltage terminal signal VGL1.

[0195] For example, in some other embodiments, as shown in Figures 1, 4, 7, 9, 13, 15 and 17, when at least one of the first gate driving unit 1001 and the second gate driving unit 1002 is a dummy gate driving unit, the pull-down node stabilization circuit 800 does not include the first pull-down node stabilization transistor T18 and the second pull-down node stabilization transistor T19.

[0196] For example, in some other embodiments, the induction compensation circuit 900 is disposed in at least one dummy gate driving unit, and at the same time, another induction compensation circuit 900 is disposed in at least one cascade gate driving unit. The induction compensation circuit 900 in the dummy gate driving unit can be selected to operate, or the induction compensation circuit 900 in the cascade gate driving unit can be selected to operate.

[0197] For example, as shown in Figures 1, 4, 7, 9, 13, 15, and 17, and referring to Figure 11 or 19, in response to the charging input signal STU, the third pull-down node stabilizing transistor T24 can be turned on, transmitting the first voltage terminal signal VGL1 to the pull-down node QB. In some embodiments, when the charging input signal STU is at a high level, the first voltage terminal signal VGL1 is transmitted to the pull-down node QB.

[0198] For example, in response to the electrical signal of the pull-up node Q, the output transistor T25 can be turned on, transmitting the output clock signal CLKD1 to the gate drive output terminal CR. In some embodiments, when the electrical signal of the pull-up node Q is at a high potential, the output transistor T25 is turned on, transmitting the output clock signal CLKD1 to the gate drive output terminal CR. At the same time, the high-potential output clock signal CLKD1 is transmitted to the second plate of the third capacitor C3. The third capacitor C3, through the voltage bootstrap effect, can further increase the voltage of the pull-up node Q, causing the gate drive output terminal CR to output a higher potential signal.

[0199] For example, in response to the electrical signal of the pull-down node QB, the pull-down transistor T26 can be turned on, transmitting the first voltage terminal signal VGL1 to the gate drive output terminal CR. In some embodiments, when the pull-down node QB is at a high potential, the pull-down transistor T26 is turned on, transmitting the first voltage terminal signal VGL1 to the gate drive output terminal CR.

[0200] Please refer to Figures 21 and 22. Figure 21 is a schematic flowchart of a driving method for a gate driving circuit according to some embodiments of this disclosure, and Figure 22 is a schematic diagram of a blanking stage or pixel driving circuit compensation process of a gate driving circuit according to some embodiments of this disclosure.

[0201] As shown in Figure 22, external compensation via a gate drive circuit is used to increase device consistency. For example, the external compensation drive signal consists of a row shift signal and a frame shift signal. The signal during the blanking time of a frame is the frame shift signal. Frame shift is further divided into sequential frame shift and random frame shift. In the sequential frame shift compensation method, the gate drive circuit can output drive signals to pixels row by row to compensate the transistors of the pixel drive circuit. In the random frame shift compensation method, the gate drive circuit can output compensation drive signals to any row of pixels in any frame to compensate the transistors of the pixel drive circuit. Figure 22 illustrates, for example, pixel drive circuit compensation is performed on the first row before the first frame, on the second row during the blanking time between the first and second frames, and on the third row during the blanking time between the second and third frames.

[0202] This disclosure also provides a driving method for a gate driving circuit, which can be applied to the gate driving circuit of any of the above-described features, or to a gate driving circuit combining any of the above-described features. The driving method for the gate driving circuit includes steps S100, S200, and S300.

[0203] In step S100, the first sensing signal Se is obtained through the sensing compensation circuit 900 during the m-th blanking stage, where m is a positive integer.

[0204] For example, before the first detection of the sensing signal Se and the acquisition of the first sensing signal, the second power signal GVDD2 is the initial second power signal, the voltage of the initial second power signal is V(GVDD2_1), and the voltage of the acquired first sensing signal Se is V(Se_1).

[0205] In step S200, during the m+i blanking stage, the second sensing signal Se is obtained through the sensing compensation circuit 900, where i is a positive integer.

[0206] For example, the voltage of the second induced signal Se is V(Se_2).

[0207] In step S300, the difference between the first sensing signal Se and the second sensing signal Se is compensated to the second power signal GVDD2 connected to the pull-down node control circuit 400.

[0208] For example, the difference ΔVth (threshold voltage change) between the first and second sensed signals Se is obtained through two detections, ΔVth = V(Se_2) - V(Se_1).

[0209] For example, after the second detection of the sensing signal Se and the acquisition of the second sensing signal, the second power supply signal GVDD2 is compensated. The compensated second power supply signal GVDD2 is the compensated second power supply signal, and the voltage of the compensated second power supply signal is V(GVDD2_2).

[0210] For example, the voltage of the compensated second power supply signal is the sum of the voltage of the initial second power supply signal and ΔVth, that is, V(GVDD2_2)=V(GVDD2_1)+ΔVth.

[0211] For example, in some embodiments, the driving process of the gate driving circuit, or the display process of the display panel, or the display process of the display device includes multiple display stages (display frames) and a blanking stage between two adjacent frames. During the display stage (display frame), the gate driving circuit can output a gate driving signal (scan driving signal), which can be provided to the pixel driving circuit.

[0212] For example, referring to Figures 9 to 12, an example illustrates the operation process of the display stage of a gate driving circuit driving method. The display stage may include a first sub-display stage, a second sub-display stage, and a third sub-display stage.

[0213] During the first sub-display stage, the charging input signal STU is high, the first display input transistor T6 and the second display input transistor T7 are turned on, and the pull-up node Q can be charged to the high potential of the first power supply signal GVDD1. Since the third pull-down node stabilizing transistor T24 of the pull-down node stabilizing circuit 800 is turned on by the high-potential charging input signal STU, the pull-down node QB can be discharged to the voltage (e.g., a low voltage) of the first voltage terminal signal VGL1.

[0214] During the second sub-display phase, the output clock signal CLKD1 is at a high level, and the voltage of the pull-up node Q is bootstrapped by the third capacitor C3 to a first boost voltage potential higher than the first power supply signal GVDD1. Therefore, during this period, the gate drive signal or the stage transmission signal can be output from the gate drive output terminal CR.

[0215] During the third sub-display stage, the output clock signal CLKD1 is at a low level, and the gate drive output terminal CR outputs a low-level signal.

[0216] It should be noted that, in other embodiments, the operation of the display stage of the gate driving circuit driving method may also include other stages besides the first sub-display stage, the second sub-display stage, and the third sub-display stage.

[0217] It should be noted that, in other embodiments, the operation of the display stage of the gate driving circuit driving method may also include other operation processes in the first sub-display stage, the second sub-display stage, and the third sub-display stage.

[0218] For example, during the blanking phase, the voltage magnitude of the induced signal Se can be obtained by detection.

[0219] For example, in some implementations, the induction compensation circuit 900 is provided in the dummy gate driving unit, which can detect and obtain the voltage magnitude of the induction signal Se during the blanking phase. In this case, the cascaded gate driving unit can also compensate the pixel driving circuit during the blanking phase.

[0220] For example, in some other embodiments, the induction compensation circuit 900 is provided in the stage gate drive unit, which can detect and obtain the voltage magnitude of the induction signal Se during the display stage.

[0221] For example, in some implementations, the driving method of the gate driving circuit further includes step S400, compensating at least one row of pixel driving circuits in the m-th blanking stage or the m+i-th blanking stage.

[0222] For example, referring to Figures 9 to 12, the working process of the blanking stage of a gate driving circuit driving method is illustrated. The working stages of the gate driving circuit driving method include a first stage XT1, a second stage XT2, a third stage XT3, a fourth stage XT4, and a fifth stage XT5, that is, the blanking stage includes the first stage XT1, the second stage XT2, the third stage XT3, the fourth stage XT4, and the fifth stage XT5. The following explanation uses the example of an induction compensation circuit 900 being set in a dummy gate driving unit.

[0223] In the first stage XT1, for the gate driving unit (gate driving unit of the compensation row) that performs pixel driving circuit compensation, the first clock signal CKA is a high-level signal, the pull-up control node P is a high-level signal, and the high level of the pull-up control node P is transmitted to the pull-up node Q, so the pull-up node Q is a high-level signal. At the same time, for the dummy gate driving unit including the induction compensation circuit 900 (e.g., the third dummy gate driving unit DUM3 in Figure 11), the pull-up control node P is always a low-level signal, the pull-up node Q of the dummy gate driving unit including the induction compensation circuit 900 is kept at a low level, and the pull-down node QB is kept at a high level.

[0224] In the second stage XT2, for the cascaded gate driving unit (the gate driving unit of the compensation row) that performs pixel driving circuit compensation, the first sub-clock signal CLK1 (the cascaded gate driving unit may include one or more output circuits 300, and the first sub-clock signal CLK1 is used as an example of an output clock signal CLKD1) is at a high potential. The output transistor T25 of one output circuit 300 is turned on, and the gate driving signal of the first row of pixels is output to compensate the pixel driving circuit of that row. At the same time, for the dummy gate driving unit including the induction compensation circuit 900 (such as the third dummy gate driving unit DUM3 in Figure 11), the second point clock signal DCLK2 is at a low potential. Thus, the sixth inverting control transistor T31 and the seventh inverting control transistor T32 are turned off, which can ensure that the output of the pull-down node QB is not affected by the fourth inverting control transistor T16 and the fifth inverting control transistor T17. The first induction compensation transistor M1 and the second induction compensation transistor M2 are turned on, and the induction signal Se is pulled down to a low potential.

[0225] In the third stage XT3: For the gate driving unit (gate driving unit of the compensation row) that performs pixel driving circuit compensation, the compensation control signal OE is selected as high potential, the first charging transistor T1 and the second charging transistor T2 are turned on, the pull-up control node P is pulled to low potential, and the pull-up node Q remains at high potential, and the working state remains unchanged. At the same time, for the dummy gate driving unit including the induction compensation circuit 900 (e.g., the third dummy gate driving unit DUM3 in Figure 11), the compensation control signal OE is selected as high potential, the first induction compensation transistor M1 and the second induction compensation transistor M2 are continuously turned on, and the induction signal Se is pulled high potential.

[0226] In stage 4 (XT4), for the gate driving unit (gate driving unit of the compensation row) that performs pixel driving circuit compensation, the compensation control signal OE is selected as low, the pull-up control node P is kept low, the pull-up node Q is kept high, and the first sub-clock signal CLK1 continues to be output at a high level to compensate the pixel driving circuit of that row. At the same time, for the dummy gate driving unit including the sensing compensation circuit 900 (e.g., the third dummy gate driving unit DUM3 in Figure 11), the sensing signal Se is reset to low, and the first sensing compensation transistor M1 and the second sensing compensation transistor M2 complete one detection.

[0227] In stage 5 (XT5), for the gate driving unit (gate driving unit of the compensation row) that performs pixel driving circuit compensation, the first sub-clock signal CLK1 changes from high to low, disabling the compensation of the pixel driving circuit for that row, and ending the compensation detection for that row. Simultaneously, for dummy gate driving units including the sensing compensation circuit 900 (e.g., the third dummy gate driving unit DUM3 in Figure 11), the operating state of the sensing compensation circuit 900 remains unchanged in this stage. Meanwhile, in stage 5 (XT5), when the total reset signal TRS is high, all gate driving units are reset by the pull-up node Q through the second stabilization circuit 600.

[0228] For example, in some implementations, the driving method of the gate driving circuit includes compensation of one or more rows of pixel driving circuits, and the driving method of the gate driving circuit also includes acquiring the voltage of the sensing signal Se.

[0229] For example, in some embodiments, as shown in Figures 13 to 20, the driving method of the gate driving circuit is the same as or similar to the example in Figures 9 to 12, except that: 1) for a dummy gate driving unit including an induction compensation circuit 900 (e.g., the third dummy gate driving unit DUM3 in Figure 19), during the display phase (e.g., when the gate driving output terminal CR outputs a high potential signal), in response to the electrical signal of the second point clock signal DCLK2, the third induction compensation transistor M3 is turned on, and the electrical signal of the pull-down node QB is applied to (transmitted to) the first induction compensation transistor M1 and the second induction compensation transistor M2, such that the first induction compensation transistor M1 or / and the second induction compensation transistor M2 have the same voltage environment (voltage of the gate, the first electrode, or the second electrode) as the first stable transistor T20 or / and the second stable transistor T21. 2) For a dummy gate driving unit including the induction compensation circuit 900 (e.g., the third dummy gate driving unit DUM3 in FIG19), during the blanking phase (when acquiring the induction signal Se), in response to the electrical signal of the second point clock signal DCLK2, the third induction compensation transistor M3 is turned off, and in response to the second compensation input signal, the first induction compensation transistor M1 and the second induction compensation transistor M2 can be turned on, transmitting the first compensation input signal as the induction signal Se. 3) For a dummy gate driving unit including the induction compensation circuit 900 (e.g., the third dummy gate driving unit DUM3 in FIG19), when detecting or acquiring the induction signal Se, the gate voltages of the first induction compensation transistor M1 and the second induction compensation transistor M2 are the voltages of the second point clock signal DCLK2.

[0230] This disclosure also provides a display device, which includes any of the above-described gate driving circuits, or the display device includes a gate driving circuit that combines any of the above-described features.

[0231] For example, the gate driving circuit includes a gate driving unit 1000 of any one of the above, or the gate driving circuit includes a gate driving unit 1000 of any combination of the above.

[0232] For example, the display device may be a smartphone, laptop, television, tablet computer or other display, and some embodiments of this disclosure are not specifically limited.

[0233] For example, in some implementations, the display device is a display panel.

[0234] It should be noted that the technical features in the above embodiments / examples can be combined with each other to obtain new shift registers.

[0235] It should be noted that the descriptions of each embodiment in the above embodiments have different focuses. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0236] The above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit it. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this disclosure.

[0237] Although preferred embodiments have been described in this specification, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this specification.

[0238] Obviously, those skilled in the art can make various modifications and variations to this specification without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims and their equivalents, this specification is also intended to include such modifications and variations.< / n>

Claims

1. A gate driving circuit, comprising at least one first gate driving unit and a plurality of second gate driving units cascaded with the first gate driving unit, wherein at least one of the first gate driving unit and the second gate driving units includes a pull-up node control circuit, an output circuit, a pull-down node control circuit and a first stabilizing circuit. At least one of the first gate driving unit and the second gate driving unit includes a sensing compensation circuit; The pull-up node control circuit is configured to control the electrical signals of the pull-up node; The output circuit includes a gate drive output terminal, and the output circuit is configured to output a composite signal to the gate drive output terminal under the electrical signal control of the pull-up node. The pull-down node control circuit is configured to input at least a first voltage terminal signal to the pull-down node under the electrical signal control of the pull-up node; The induction compensation circuit is configured to output an induction signal under the control of the electrical signal of the pull-down node.

2. The gate driving circuit according to claim 1, wherein, Both the first gate driving unit and the second gate driving unit include a first stabilizing circuit, and at least one of the first gate driving unit and the second gate driving unit further includes a selection compensation circuit; The selection compensation circuit is configured to charge the pull-up control node under the control of the selection compensation control signal and to charge the pull-up node under the control of the first clock signal. The pull-up node control circuit includes a display input sub-circuit, which is configured to input a first power signal to the pull-up node under the control of a charging input signal. The pull-down node control circuit is configured to input a second power signal or the first voltage terminal signal to the pull-down node under the electrical signal control of the pull-up node; The first stabilizing circuit is configured to electrically control the pull-up node under the control of the electrical signal of the pull-down node.

3. The gate driving circuit according to claim 2, wherein, The pull-up node control circuit further includes a display protection sub-circuit, which is configured to perform electrical signal control on the first node under the electrical signal control of the pull-up node. The first node is electrically connected to the first stabilizing circuit and the inductive compensation circuit; The first stabilizing circuit is also configured to electrically control the first node under the control of the electrical signal of the pull-down node.

4. The gate driving circuit according to claim 3, wherein, The inductive compensation circuit includes a first inductive compensation transistor and a second inductive compensation transistor. The gate of the first sensing compensation transistor is electrically connected to the pull-down node, the first terminal of the first sensing compensation transistor outputs the sensing signal, and the second terminal of the first sensing compensation transistor is electrically connected to the first node and the first terminal of the second sensing compensation transistor. The gate of the second inductive compensation transistor is electrically connected to the pull-down node, and the second terminal of the second inductive compensation transistor is connected to the first compensation input signal.

5. The gate driving circuit according to claim 4, wherein, The first compensation input signal is either the first point clock signal or the selected compensation control signal.

6. The gate driving circuit according to claim 4, wherein, The induction compensation circuit also includes a third induction compensation transistor and a fourth induction compensation transistor. The gate of the third inductive compensation transistor is connected to the second point clock signal, the first electrode of the third inductive compensation transistor is electrically connected to the pull-down node, and the second electrode of the third inductive compensation transistor is electrically connected to the second electrode of the fourth inductive compensation transistor, the gate of the first inductive compensation transistor, and the gate of the second inductive compensation transistor. The gate of the fourth inductive compensation transistor is connected to the first compensation input signal, and the first electrode of the fourth inductive compensation transistor is connected to the second compensation input signal.

7. The gate driving circuit according to claim 6, wherein, The first compensation input signal is a first point clock signal or a selection compensation control signal; The second compensation input signal is either the second power supply signal or the third clock signal.

8. The gate driving circuit according to claim 2, wherein, The display input sub-circuit includes a first display input transistor, a second display input transistor, and a third display input transistor; The gate of the first display input transistor is connected to the charging input signal, the first terminal of the first display input transistor is connected to the first power signal, and the second terminal of the first display input transistor is electrically connected to the first terminal of the second display input transistor and the first terminal of the third display input transistor; The gate of the second display input transistor is connected to the charging input signal, and the second electrode of the second display input transistor is electrically connected to the pull-up node; The gate of the third display input transistor is electrically connected to the pull-down node, and the second terminal of the third display input transistor is connected to the first power signal.

9. The gate driving circuit according to claim 3, wherein, The pull-down node control circuit includes a first reverse control transistor, a second reverse control transistor, a third reverse control transistor, a fourth reverse control transistor, and a fifth reverse control transistor. The gate of the first reverse control transistor is connected to the second power supply signal, the first terminal of the first reverse control transistor is connected to the second power supply signal, and the second terminal of the first reverse control transistor is electrically connected to the first terminal of the second reverse control transistor. The gate of the second reverse control transistor is connected to the second power supply signal, and the second terminal of the second reverse control transistor is electrically connected to the first terminal of the third reverse control transistor and the gate of the fourth reverse control transistor. The gate of the third reverse control transistor is electrically connected to the pull-up node, and the second terminal of the third reverse control transistor is connected to the second voltage terminal signal. The first terminal of the fourth inverting control transistor is connected to the second power supply signal, and the second terminal of the fourth inverting control transistor is electrically connected to the first terminal of the fifth inverting control transistor and the pull-down node; The gate of the fifth reverse control transistor is electrically connected to the pull-up node, and the second terminal of the fifth reverse control transistor is connected to the first voltage terminal signal.

10. The gate driving circuit according to claim 9, wherein, The pull-down node control circuit also includes a sixth inverting control transistor; The gate of the sixth inverting control transistor is connected to the second clock signal, the first terminal of the sixth inverting control transistor is electrically connected to the second terminal of the fourth inverting control transistor and the pull-down node, and the second terminal of the sixth inverting control transistor is electrically connected to the first terminal of the fifth inverting control transistor.

11. The gate driving circuit according to claim 9, wherein, The pull-down node control circuit also includes a seventh inverting control transistor; The gate of the seventh inverting control transistor is connected to the second clock signal, the first terminal of the seventh inverting control transistor is electrically connected to the second terminal of the second inverting control transistor, and the second terminal of the seventh inverting control transistor is electrically connected to the first terminal of the third inverting control transistor.

12. The gate driving circuit according to claim 3, wherein, The display protection sub-circuit includes a first protection transistor and a second protection transistor; The gate of the first protection transistor is electrically connected to the pull-up node, the first terminal of the first protection transistor is connected to the first power supply signal, and the second terminal of the first protection transistor is electrically connected to the first terminal of the second protection transistor. The gate of the second protection transistor is electrically connected to the pull-up node, and the second electrode of the second protection transistor is electrically connected to the first node.

13. The gate driving circuit according to claim 3, wherein, The pull-up node control circuit also includes a display reset sub-circuit; The display reset sub-circuit is configured to electrically control the pull-up node under the control of the display reset signal.

14. The gate drive circuit according to claim 13, wherein, The display reset sub-circuit includes a first display reset transistor and a second display reset transistor; The gate of the first display reset transistor is connected to the display reset signal, the first electrode of the first display reset transistor is electrically connected to the pull-up node, and the second electrode of the first display reset transistor is electrically connected to the first electrode of the second display reset transistor and the first node; The gate of the second display reset transistor is connected to the display reset signal, and the second electrode of the second display reset transistor is connected to the first voltage terminal signal.

15. The gate drive circuit according to claim 2, wherein, The selection compensation circuit includes a charging sub-circuit, a storage sub-circuit, and an isolation sub-circuit; The charging sub-circuit is configured to input the charging input signal to the pull-up control node under the control of the selection compensation control signal; The storage sub-circuit is configured to store the charging input signal input to the charging sub-circuit; The isolation sub-circuit is configured to input the charging input signal to the pull-up node under the control of the electrical signal of the pull-up control node and the first clock signal.

16. The gate drive circuit according to claim 15, wherein, The charging sub-circuit includes a first charging transistor, a second charging transistor, a first capacitor, and a third charging transistor; The storage sub-circuit includes a second capacitor; The isolation sub-circuit includes a first isolation transistor and a second isolation transistor; The gate of the first charging transistor is connected to the selection compensation control signal, the gate of the first charging transistor is also electrically connected to the first plate of the first capacitor, the first terminal of the first charging transistor is connected to the charging input signal, and the second terminal of the first charging transistor is electrically connected to the first terminal of the second charging transistor and the first terminal of the third charging transistor. The gate of the second charging transistor is connected to the selection compensation control signal, and the gate of the second charging transistor is also electrically connected to the first plate of the first capacitor. The second plate of the second charging transistor is electrically connected to the gate of the third charging transistor, the second plate of the first capacitor, the gate of the first isolation transistor, and the second plate of the second capacitor. The second terminal of the third charging transistor is electrically connected to the first plate of the second capacitor and the first terminal of the first isolation transistor. The second terminal of the third charging transistor is also connected to the first power signal. The second terminal of the first isolation transistor is electrically connected to the first terminal of the second isolation transistor; The gate of the second isolation transistor is connected to the first clock signal, and the second terminal of the second isolation transistor is electrically connected to the pull-up node.

17. The gate drive circuit according to claim 3, wherein, The first stabilizing circuit includes a first stabilizing transistor and a second stabilizing transistor; The gate of the first stable transistor is electrically connected to the pull-down node, the first electrode of the first stable transistor is electrically connected to the pull-up node, and the second electrode of the first stable transistor is electrically connected to the first node and the first electrode of the second stable transistor. The gate of the second stabilizing transistor is electrically connected to the pull-down node, and the second terminal of the second stabilizing transistor is connected to the first voltage terminal signal.

18. The gate driving circuit according to claim 3, wherein, At least one of the first gate driving unit and the second gate driving unit further includes a second stabilizing circuit; The second stabilizing circuit is configured to electrically control the pull-up node under the control of the total reset signal.

19. The gate drive circuit according to claim 18, wherein, The second stabilizing circuit includes a third stabilizing transistor and a fourth stabilizing transistor; The gate of the third stable transistor is connected to the total reset signal, the first terminal of the third stable transistor is electrically connected to the pull-up node, and the second terminal of the third stable transistor is electrically connected to the first node and the first terminal of the fourth stable transistor. The gate of the fourth stable transistor is connected to the total reset signal, and the second terminal of the fourth stable transistor is connected to the first voltage terminal signal.

20. The gate driving circuit according to claim 2, wherein, At least one of the first gate driving unit and the second gate driving unit further includes a pull-down circuit, which is configured to control the gate driving output terminal with an electrical signal under the control of the electrical signal of the pull-down node. At least one of the first gate driving unit and the second gate driving unit further includes a pull-down node stabilization circuit, which is configured to control the electrical signal of the pull-down node under the control of a first clock signal, an electrical signal of a pull-up control node, and the charging input signal.

21. The gate driving circuit according to claim 20, wherein, The output circuit includes an output transistor and a third capacitor; The pull-down circuit includes a pull-down transistor; The pull-down node stabilization circuit includes a first pull-down node stabilization transistor, a second pull-down node stabilization transistor, and a third pull-down node stabilization transistor. The gate of the output transistor is electrically connected to the pull-up node and the first plate of the third capacitor. The first plate of the output transistor is connected to the output clock signal. The second plate of the output transistor is electrically connected to the second plate of the third capacitor, the gate drive output terminal, and the first plate of the pull-down transistor. The gate of the pull-down transistor is electrically connected to the pull-down node, and the second terminal of the pull-down transistor is connected to the first voltage terminal signal; The gate of the first pull-down node stabilizing transistor is connected to the first clock signal, the first terminal of the first pull-down node stabilizing transistor is electrically connected to the pull-down node, and the second terminal of the second pull-down node stabilizing transistor is electrically connected to the first terminal of the second pull-down node stabilizing transistor. The gate of the second pull-down node stabilizing transistor is electrically connected to the pull-up control node, and the second terminal of the second pull-down node stabilizing transistor is connected to the first voltage terminal signal; The gate of the third pull-down node stabilizing transistor is connected to the charging input signal, the first electrode of the third pull-down node stabilizing transistor is electrically connected to the pull-down node, and the second electrode of the third pull-down node stabilizing transistor is connected to the first voltage terminal signal.

22. A driving method for a gate driving circuit, applied to the gate driving circuit as described in any one of claims 1 to 21, comprising: The first induced signal is obtained through the induction compensation circuit in the m-th blanking stage, where m is a positive integer; In the (m+i)th blanking stage, the second sensing signal is obtained through the sensing compensation circuit, where i is a positive integer; The difference between the first and second sensing signals is compensated to the second power signal connected to the pull-down node control circuit.

23. A display device comprising a gate driving circuit as claimed in any one of claims 1 to 21.

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