Cache, chip, server, and cluster

Abstract

A cache, a chip, a server, and a cluster. The cache comprises: a tag array memory, comprising a first tag line; and a data array memory, comprising a first data line, wherein the first data line comprises one or more data blocks. In a first mode, the first data line is used for storing first storage data in a memory, the first tag line is used for storing a first high-order address of a first storage address where the first storage data in the memory is located, the first high-order address is bits in the first storage address other than a first low-order address, and the number of bits of the first low-order address is determined on the basis of the number of data lines in the data array memory and the number of data blocks in each data line; and in the second mode, the first tag line is used for storing a first key in a first key-value pair, and the first data line is used for storing a first value in the first key-value pair. The solution can achieve hardware accelerated query of a key-value table by means of a cache.

Description

Cache, chip, server and cluster

[0001] The present application claims priority to the Chinese patent application No. 202411047550.9, filed on July 31, 2024, with the State Intellectual Property Office of China, and entitled "Cache, chip, server and cluster", the whole content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the field of computer, and in particular, to a cache, a chip, a server and a cluster. BACKGROUND

[0003] Key-value query is a process of finding a value according to an input key to find a key-value table. As shown in FIG. 1, the prior art provides a hardware hash query system, which includes a content addressable memory (CAM) 110, an encoder 120, a decoder 130 and a random access memory (RAM) 140. The CAM 110 is used to store keys in the key-value table, and the RAM 140 is used to store values in the key-value table. Moreover, the addresses of the same key-value pair stored in the CAM 110 and the RAM 140 are corresponding.

[0004] The process of inputting a key into the hardware key-value query system to obtain a value can be: inputting the key into the CAM 110 to obtain a first storage address of the key in the CAM 110. The first storage address is output to the encoder 120 for encoding to obtain encoding information. The encoding information is sent to the decoder 130 for decoding to obtain a second storage address in the RAM 140. The second storage address is sent to the RAM 140 to obtain the value stored in the second storage address of the RAM 140.

[0005] Here, the CAM 110 is a special memory that can be addressed according to the stored content, rather than accessing the stored content by the storage address as in the traditional memory. Specifically, when the key is input into the CAM 110, the CAM 110 will compare it with each key stored in the internal in parallel, and if a matching key is found, the CAM 110 will output the storage address of the key in the CAM 110. Since the CAM 110 determines the storage address of the storage content in the CAM 110 according to the storage content at the hardware level, the processing speed is very fast.

[0006] The encoder 120 and the decoder 130 are used to realize the mapping between the first storage address in the CAM 110 and the second storage address in the RAM 140. Since the encoder 120 and the decoder 130 have been pre-configured with the mapping relationship between the storage address in the CAM 110 and the storage address in the RAM 140, the mapping from the first storage address in the CAM 110 to the second storage address in the RAM 140 can be realized.

[0007] The RAM 140 can access the storage content according to the storage address, and can access the storage content at any position in almost the same time. Specifically, when the second storage address is input to the RAM 140, the RAM 140 quickly determines the value of the storage unit corresponding to the second storage address in the RAM 140 according to the second storage address. Since the RAM 140 determines the storage address in the storage content of the RAM 140 at the hardware level, the processing speed is very fast.

[0008] The process of inputting the key into the hardware key-value query system to obtain the value will be described in detail below with specific examples.

[0009] Suppose the key-value table includes the following two items:

[0010] Table 1 Key-value table

[0011] The keys and values in the above key-value table are stored separately, wherein the keys in the key-value table are stored in the CAM 110, and the values in the key-value table are stored in the RAM 140. Then,

[0012] The CAM storage address 1 and the CAM storage address 2 in the CAM 110 respectively store the keys "11" and "22" in the key-value table, as shown in Table 2:

[0013] Table 2 CAM storage

[0014] The RAM storage address 1 and the RAM storage address 2 in the RAM 140 respectively store the values "Name: Zhang San, Score: 98" and "Name: Li Si, Score: 95" in the key-value table, as shown in Table 3:

[0015] Table 3 RAM storage

[0016] Therefore, when the key "22" is input into the CAM 110, the CAM 110 finds the first storage address "CAM storage address 2" of the key "22" in the CAM 110 according to the key "22", and then inputs the "CAM storage address 2" into the encoder 120 to obtain the encoding information, and inputs the encoding information into the decoder 130 to obtain the decoding information. Since the encoder 120 and the decoder 130 are pre-configured with the mapping relationship between the storage addresses in the CAM 110 and the storage addresses in the RAM 140, the obtained decoding information is the second storage address "RAM storage address 2" in the RAM 140. Inputting the "RAM storage address 2" into the RAM 140 can determine the corresponding value as "name: Li Si, score: 95".

[0017] As can be seen from the above statements, the current hardware-accelerated query of the key-value table cannot be implemented without the CAM, and therefore can only be used in a specific circuit based on the CAM. SUMMARY

[0018] The application provides a cache, a chip, a server and a cluster, which can realize hardware-accelerated query of a key-value table through the cache.

[0019] In a first aspect, a cache is provided. The cache comprises a tag array memory and a data array memory. The tag array memory comprises a first tag row, and the first tag row comprises one or more data blocks. The data array memory comprises a first data row, and the first data row comprises one or more data blocks. In a first mode, the first data row is used to store first storage data in a memory, and the first tag row is used to store a first high bit address of a first storage address of the first storage data in the memory. In a second mode, the first tag row is used to store a first key in a first key-value pair, and the first data row is used to store a first value in the first key-value pair. The first high bit address is a bit of the first storage address other than a first low bit address, and the number of bits of the first low bit address is determined according to the number of data rows in the data array memory and the number of data blocks in each data row.

[0020] In the scheme, the redundant resources in the cache can be used to implement hardware accelerated query of the key-value table. For a database application, the application can include one or more key-value tables, and thus, the key-value table needs to be queried, and the query performance of the key-value table has a great influence on the performance of the application. In addition to the query of the key-value table, the application also needs to read and write a large amount of data, and when the data needs to be stored in the cache, the original key-value table stored in the cache will be replaced. Thus, the next time the key-value table is queried, the key-value table cannot be found in the cache, and the key-value table needs to be loaded from the memory to the cache. The query of the key-value table is based on the key to query the value of the key-value table, and the key and the value have a one-to-one correspondence. In the cache, the tag row in the tag array memory and the data row in the data array memory have a one-to-one correspondence. Therefore, the circuit of the cache can be improved to use the resources in the cache to implement hardware accelerated query of the key-value table.

[0021] In some possible designs, in the two different modes, the data array memory can output first stored data and a first value respectively. For example,

[0022] In the first mode, when the processor needs to read the first stored data from the cache, and the data in the corresponding data block of the first data row corresponding to the first low address and the first high address is the same, the data array memory outputs the first stored data in the corresponding data block in the first data row corresponding to the first low address.

[0023] In the second mode, when the processor needs to read the first value from the cache, and the data in the corresponding data block of the first data row corresponding to the first low address and the first high address is the same, the data array memory outputs the first value in the corresponding data block in the first data row corresponding to the first low address.

[0024] In the scheme, in the two different modes, the data array memory can output first stored data and a first value respectively, so as to implement cache read and key-value read.

[0025] In some possible designs, the cache further includes a first multiplexer, a second multiplexer, and a comparator.

[0026] The first multiplexer and the second multiplexer are both configured to receive a first control signal in the first mode and when the processor needs to read the first stored data from the cache.

[0027] The first multiplexing controller is configured to select the first high-bit address to be input to the tag array memory and the comparator under the action of the first control signal;

[0028] The second multiplexing controller is configured to select the first low-bit address to be input to the tag array memory and the data array memory under the action of the first control signal;

[0029] The tag array memory is configured to output data in a corresponding data block in a first tag row corresponding to the first low-bit address to the comparator for comparison;

[0030] The data array memory is configured to output the first stored data in a corresponding data block in a first data row corresponding to the first low-bit address when the comparison result of the comparator is same.

[0031] The first multiplexing controller and the second multiplexing controller are both configured to receive a second control signal when the second mode is used and the processor needs to read the first key-value pair from a first specified address of the cache;

[0032] The first multiplexing controller is configured to select the first key to be input to the tag array memory and the comparator under the action of the second control signal;

[0033] The second multiplexing controller is configured to select the first specified address to be input to the tag array memory and the data array memory under the action of the second control signal;

[0034] The tag array memory is configured to output data in a corresponding data block in a first tag row corresponding to the first specified address to the comparator for comparison;

[0035] The data array memory is configured to output the first value in a corresponding data block in a first data row corresponding to the first specified address when the comparison result of the comparator is same, the first specified address being same as the first low-bit address.

[0036] In the above scheme, through the setting of the first multiplexing controller and the second multiplexing controller, the data array memory can output the first stored data and the first value respectively in two different modes, so as to realize cache reading and key-value reading. Therefore, the scheme of the embodiment can realize cache data caching and key-value table hardware acceleration query in a compatible manner with very few additional devices and very little modification to the original circuit.

[0037] In some possible design, the data array memory can be configured to store second storage data and second value in two different modes respectively.

[0038] The data array memory is configured to, in the first mode, write the second storage data into a corresponding data block of a second data row corresponding to the second low address in the data array memory when the processor needs to write the second storage data into the cache and a second high address in the second storage address and data in a corresponding data block of a second data row corresponding to the second low address in the data array memory are the same.

[0039] The data array memory is configured to, in the second mode, write the second value into a corresponding data block of a second data row corresponding to the second specified address in the data array memory when the processor needs to write a second key-value pair into the cache and a second key in the second key-value pair and data in a corresponding data block of a tag row corresponding to the second specified address in the tag array memory are the same.

[0040] In the above solution, the data array memory can store second storage data and second value in two different modes respectively, so as to implement cache write and key-value write.

[0041] In some possible design, the tag array memory includes a second tag row, and the data array memory includes a second data row.

[0042] The first multiplexer controller and the second multiplexer controller are configured to, in the first mode and when the processor needs to write second storage data into the cache, receive a first control signal.

[0043] The first multiplexer controller is configured to, under the action of the first control signal, select to input a second high address in the second storage address into the tag array memory and the comparator.

[0044] The second multiplexer controller is configured to, under the action of the first control signal, select to input a second low address in the second storage address into the tag array memory and the data array memory.

[0045] The tag array memory is configured to output data in a corresponding data block in a second tag row corresponding to the second low address to the comparator for comparison.

[0046] The data array memory is configured to write the second storage data into a corresponding data block of a second data row corresponding to the second low-bit address in the data array memory when the comparison result of the comparator is same.

[0047] The first multiplexing controller and the second multiplexing controller are configured to receive a second control signal when the second mode is selected and the processor needs to write a second key-value pair to a second specified address of the cache.

[0048] The first multiplexing controller is configured to select the second key in the second key-value pair to be input to the tag array memory and the comparator under the action of the second control signal.

[0049] The second multiplexing controller is configured to select the second specified address to be input to the tag array memory and the data array memory under the action of the second control signal.

[0050] The tag array memory is configured to output data in a corresponding data block in a second tag row corresponding to the second specified address to the comparator for comparison.

[0051] The data array memory is configured to write a second value in the second key-value pair into a corresponding data block of a second data row corresponding to the second specified address in the data array memory when the comparison result of the comparator is same.

[0052] In the above scheme, through the setting of the first multiplexing controller and the second multiplexing controller, the data array memory can store the second storage data and the second value in two different modes respectively, so as to realize cache writing and key-value writing. Therefore, the scheme of the embodiment can realize the hardware acceleration query of the cache and the key-value table in a compatible manner by adding very few devices and modifying the original circuit very little.

[0053] In a second aspect, a chip is provided, including a processing core, a cache, and a power supply circuit, wherein the power supply circuit is configured to supply power to the processing core and the cache, and the cache is the cache according to any one of the first aspect.

[0054] In a third aspect, a server is provided, including a power supply system and a chip, wherein the power supply system is configured to supply power to the chip, and the chip is the chip according to the second aspect.

[0055] In a fourth aspect, a server is provided, including a processor and a cache, wherein the processor and the cache are connected, and the cache is the cache according to any one of the first aspect.

[0056] In a fifth aspect, there is provided a server cluster comprising a plurality of servers, wherein at least one server is a server as described in the fourth aspect. BRIEF DESCRIPTION OF DRAWINGS

[0057] Fig. 1 is a schematic diagram of a hardware-accelerated query system according to the prior art;

[0058] Fig. 2 is a schematic diagram of a memory hierarchy according to the present application;

[0059] Fig. 3 is a schematic diagram of a cache according to the present application;

[0060] Fig. 4 is a schematic diagram of direct mapping between a memory and a data array memory according to the present application;

[0061] Fig. 5 is a schematic diagram of a server according to the present application;

[0062] Fig. 6 is a schematic diagram of another server according to the present application;

[0063] Fig. 7 is a schematic diagram of a server cluster according to the present application. DETAILED DESCRIPTION

[0064] As shown in Fig. 2, the memory hierarchy can include registers, cache, and main memory, etc. The closer to the top of the pyramid, the smaller the capacity, the faster the access speed, and the higher the cost of the device. The closer to the bottom of the pyramid, the larger the capacity, the slower the access speed, and the lower the cost of the device. The processor (CPU) reads data in the register, which only needs one clock cycle. If the data is read in the main memory, it needs about one hundred cycles.

[0065] Because of the great disparity between the processing speed of the processor and the access speed of the main memory, in order to reduce the disparity, a cache is needed to be set between the processor and the main memory to cache data and instructions that the processor frequently accesses recently. When the processor needs to read or write data, it will first check whether the cache has the required data. If the cache has the required data, the processor will read the data from the cache or write the data to the cache directly. If the cache does not have the required data, the processor will read the data from the main memory and load it into the cache, so that the next time the data can be read from the cache quickly or written to the cache, thereby reducing the speed mismatch between the processor and the main memory. Because the capacity of the main memory is greater than the capacity of the cache, therefore, the cache can only save a part of the data of the main memory. If the cache has already stored a part of the data of the main memory, when another part of the data of the main memory needs to be stored in the same position of the cache, the original part of the data of the main memory stored in the cache can only be replaced by the other part of the data of the main memory.

[0066] The performance of the cache can be measured by hit rate and miss rate. The hit rate and the miss rate will be introduced in detail below.

[0067] The hit rate refers to the probability that the data required by the processor is already in the cache when the processor accesses the cache. In other words, it represents the ratio of the number of times the processor successfully finds data when trying to read data from the cache to the total number of accesses. The higher the hit rate, the better the performance of the cache, and the faster the processor accesses data.

[0068] The miss rate is the complement of the hit rate. It represents the probability that the data required by the processor is not in the cache when the processor accesses the cache. In other words, it represents the ratio of the number of times the processor does not find data when trying to read data from the cache to the total number of accesses. The higher the miss rate, the worse the performance of the cache, and the slower the processor accesses data.

[0069] The hit rate and the miss rate are related to each other, and they together determine the performance of the cache. A high hit rate means that the processor can access data faster, while a low miss rate indicates that the cache can effectively cache the data required by the processor.

[0070] With the improvement of modern technology, the capacity of cache can be larger and larger, and the amount of data in the main memory that the cache can load is also larger and larger. Through the performance analysis of the upper application program, it is found that although the capacity of the cache is larger, it helps to improve the performance to a certain extent, but when the capacity of the cache reaches a certain size, the performance improvement of the cache capacity continues to increase, which includes:

[0071] (1) Due to the marginal diminishing effect, at the beginning, the increase of the capacity of the cache can significantly reduce the number of times of accessing the main memory of the processor, thereby improving the overall performance, but when the cache capacity reaches a certain threshold, the effect of increasing the capacity on reducing the frequency of accessing the main memory of the processor becomes limited. For example, when the capacity of the cache increases to a certain extent, the miss rate is already very low, at this time, the effect of increasing the cache capacity on reducing the miss rate is limited.

[0072] (2) Because some upper application programs are not sensitive to the capacity of the cache, even if the cache capacity increases a lot, the performance improvement is not obvious.

[0073] (3) Because the larger the cache is, the more complex the maintenance and management mechanism is required, for example, the more complex the replacement strategy and address mapping mechanism is, which may increase the burden of the processor, thereby offsetting the performance improvement brought by the capacity increase.

[0074] Therefore, the capacity of the cache is larger and larger, and whether the redundant resources in the cache can be used for other things, so as to fully utilize the resources of the cache.

[0075] In order to solve the above problems, the application provides a cache which can be used for data caching and hardware accelerated key-value table query at the same time.

[0076] Referring to FIG. 3, FIG. 3 is a structural schematic diagram of a cache provided by the application, as shown in FIG. 3, the cache provided by the application comprises a key input interface 201, a mode selection interface 202, an address input interface 203, a value input interface 204, a tag read-write interface 205, a tag logic 206, a first multiplexer (MUX) 207, a second MUX 208, a data read-write interface 209, a tag array memory 210, a data array memory 211, and a comparator 212.

[0077] The key input interface 201, the mode selection interface 202, the address input interface 203, the value input interface 204, the tag read-write interface 205, and the data read-write interface 209 are all input-output interfaces, which will not be described here.

[0078] The first MUX 207 and the second MUX 208 are both multiplexers, which are used to output one of multiple input signals to an output terminal under the action of a control signal. The multiplexers can be 2-way selectors, 3-way selectors or even more way selectors. The first MUX 207 and the second MUX 208 can be the same type of multiplexers or completely different types of multiplexers. For example, the first MUX 207 and the second MUX 208 are both 2-way selectors, or the first MUX 207 is a 2-way selector and the second MUX 208 is a 4-way selector, and so on.

[0079] The tag array memory 210 includes multiple tag rows, each of which includes one or more data fields, wherein the data fields are used to store data. Optionally, each tag row further includes a tag valid bit and a tag row number, and so on, wherein the tag valid bit is used to indicate whether the data in the tag row is valid. For example, if the valid bit is set to 1, it indicates that the row data in the corresponding tag row is valid; if it is set to 0, it indicates that the row data of the corresponding tag row is invalid or has been deleted. The tag row number is used to locate a specific tag row in the tag array memory. In addition to the above-mentioned fields, the tag row can also include more fields, which are not limited here.

[0080] The data array memory 211 includes multiple data rows, each of which can include one or more data blocks. Each data block can include one or more byte fields. For example, the size of the data block can be 32 bytes, 64 bytes or 128 bytes, but can also be other sizes. Optionally, each data row further includes a data valid bit and a data row number, and so on, wherein the data valid bit is used to indicate whether the data in the data row is valid. For example, if the valid bit is set to 1, it indicates that the row data in the corresponding data row is valid; if it is set to 0, it indicates that the row data of the corresponding data row is invalid or has been deleted. The data row number is used to locate a specific tag row in the data array memory. In addition to the above-mentioned fields, the data row can also include more fields, which are not limited here.

[0081] The number of tag rows in the tag array memory 210 and the number of data rows in the data array memory 211 are the same, and the tag rows in the tag array memory 210 and the data rows in the data array memory 211 can be one-to-one associated, and the associated tag rows and data rows form a cache line. Specifically, the association between the tag row and the data row can be:

[0082] The first tag row in the tag array memory 210 and the first data row in the data array memory 211 are associated, and both constitute a first cache line;

[0083] The second tag row in the tag array memory 210 and the second data row in the data array memory 211 are associated, and both constitute a second cache line;

[0084] By analogy;

[0085] The last tag row in the tag array memory 210 and the last data row in the data array memory 211 are associated, and both constitute a last cache line.

[0086] It can be understood that the above-mentioned cache only exemplarily illustrates the structure of one cache, and in actual application, a plurality of caches can be included, each of which can be the cache shown in FIG. 2, or a part of the cache shown in FIG. 3 and a part of a conventional cache (which will not be described here).

[0087] The comparator 212 is used to compare two input signals to determine whether the two input signals are the same. The comparator can be an operational amplifier, a dedicated comparator integrated circuit, a digital logic gate, a parallel comparison type analog-to-digital converter, a successive approximation type analog-to-digital converter, and the like. In a specific embodiment, the comparator 212 includes a first input end, a second input end, and an output end. When the input signal at the first input end and the input signal at the second output end are equal, the output end of the comparator 212 outputs a first output signal; when the input signal at the first input end and the input signal at the second output end are not equal, the output end of the comparator 212 outputs a second output signal. It can be understood that the above-mentioned comparator 212 takes two input signals as an example, and in actual application, the comparator 212 can also include more input signals, which is not limited here.

[0088] The cache shown in FIG. 3 can be an L1 level cache, an L2 level cache, or an L3 level cache. When there are a plurality of caches, it can be a mixture of one or more of the above-mentioned various levels of the cache shown in FIG. 3 and the conventional cache. For example, when there are a plurality of caches, a part of them can be the L1 level cache shown in FIG. 3, a part of them can be the L2 level cache shown in FIG. 2, and a part of them can be the L3 level cache shown in FIG. 3.

[0089] After introducing the structure of the cache, the storage mode of the cache will be described in detail. The storage mode of the cache has the following characteristics:

[0090] (1) Since the access of the processor to the data has temporal locality and spatial locality, the processor reads the data from the memory and loads it into the cache in units of lines. That is, the entire line of data in which the data is located in the memory is loaded into the data array memory of the cache. The temporal locality refers to the possibility that if a data is accessed now, it will be accessed later. The spatial locality refers to the possibility that if a data is accessed now, the data around it will be accessed later. Therefore, when the processor loads the data from the memory to the cache, not only the data is loaded from the memory to the cache, but also the entire line of data in which the data is located in the memory is loaded from the memory to the cache. Loading data into the cache in units of lines can effectively reduce the number of times the processor reads data from the memory and loads it into the cache. The memory is an internal storage that directly exchanges data with the processor, and can be read and written at any time (except when it is refreshed), and has a very fast speed, and is usually used as a temporary data storage medium for an operating system or other programs running. The memory can write (store) or read (fetch) information from any specified address at any time. For example, the memory can include memory provided by a host slot, memory embedded in a chip, such as graphics double data rate dynamic random access memory (gddr) used by a graphics card, high bandwidth memory (hbm), or remotely accessed memory space, such as remote memory or a composable memory system (cms) connected through a peripheral component interconnect express (pcie) bus, compute express link (cxl) bus, etc. The cache is a storage between the processor and the memory, but has a faster access speed than the memory. The cache can provide instructions and data to the processor at a high speed, thereby speeding up the execution of the program.

[0091] (2) Since the capacity of the memory is much larger than that of the cache, usually, a plurality of memory lines in the memory are mapped to one data line in the data array memory 211. The specific way in which a plurality of memory lines in the memory are mapped to one data line in the data array memory will be described in detail below by taking direct memory mapping as an example.

[0092] As shown in FIG. 4, it is assumed that the memory includes a continuous storage space from address 0x00000000 to address 0x00111100, and the storage space in the memory is divided into 16 storage rows.

[0093] The first storage row in the memory includes four data blocks with addresses 0x00000000, 0x00000001, 0x00000010 and 0x00000011 respectively.

[0094] The second storage row in the memory includes four data blocks with addresses 0x00000100, 0x00001001, 0x00001010 and 0x00001011 respectively.

[0095] By analogy;

[0096] The sixteenth storage row in the memory includes four data blocks with addresses 0x00111100, 0x00111101, 0x00111110 and 0x00111111 respectively.

[0097] The data array memory includes a continuous storage space from address 0x0000 to address 0x1100, and the storage space in the data array memory is divided into four data rows.

[0098] The first data row in the data array memory includes four data blocks with addresses 0x0000, 0x0001, 0x0010 and 0x0011 respectively.

[0099] The second data row in the data array memory includes four data blocks with addresses 0x0100, 0x0101, 0x0110 and 0x0111 respectively.

[0100] By analogy;

[0101] The fourth data row in the data array memory includes four data blocks with addresses 0x1100, 0x1101, 0x1110 and 0x1111 respectively.

[0102] When mapping, the memory and the data array memory can be mapped in the following manner:

[0103] The four data blocks in the first storage row, the four data blocks in the fifth storage row, the four data blocks in the ninth storage row and the four data blocks in the thirteenth storage row in the memory can be respectively mapped into the four data blocks in the first data row in the data array memory.

[0104] The 4 data blocks of the second memory row, the 4 data blocks of the sixth memory row, the 4 data blocks of the tenth memory row, and the 4 data blocks of the fourteenth memory row in the memory can be mapped into the 4 data blocks of the second data row of the data array memory respectively;

[0105] By analogy;

[0106] The 4 data blocks of the fourth memory row, the 4 data blocks of the eighth memory row, the 4 data blocks of the twelfth memory row, and the 4 data blocks of the sixteenth memory row in the memory can be mapped into the 4 data blocks of the fourth data row of the data array memory respectively.

[0107] Fig. 4 is a diagram illustrating an example in which the memory includes 16 memory rows, the data array memory in the cache includes 4 data rows, each memory row and each data row includes 4 data blocks, and the memory and the data array memory are mapped by direct mapping. In actual applications, the memory can include more or fewer memory rows, the data array memory can include more or fewer data rows, each memory row and each data row can include more or fewer data blocks, and the mapping can include group mapping and full mapping, etc. without specific limitation herein. In addition, the data row number and the data valid bit, etc. are not shown in Fig. 4. In actual applications, the data row number and the data valid bit, etc. can be included without specific limitation herein.

[0108] (3) Since multiple different memory rows in the memory are mapped to the same data row, but the same data row can only be used to store the data of one memory row at the same time, if the data of one memory row has been stored in the data row, when the data of another memory row needs to be read into the data row, the stored data of one memory row in the data row needs to be replaced by the data of another memory row. Of course, the replacement strategy of directly replacing described above is only the most basic replacement strategy. In actual applications, more complex replacement strategies can be used without specific limitation herein.

[0109] (4) Since different memory lines in the memory are mapped to the same data line, and the first low address of the start address of the different memory lines mapped to the same data line is the same, and the first low address is the start address of the data line. Only through the first low address in the storage address, it is not possible to distinguish which memory line in the memory is mapped to the data line. Therefore, the first high address in the start address of the memory line needs to be saved to the tag array memory 210, so as to determine which memory line in the memory is mapped to the data line through the first high address saved in the data array memory. Taking the example of the example shown in FIG. 4, the first memory line, the fifth memory line, the ninth memory line, and the thirteenth memory line in the memory are all mapped to the first data line in the data array memory, the start address of the first memory line is 0x00000000, the start address of the fifth memory line is 0x00010000, the start address of the ninth memory line is 0x00100000, and the start address of the thirteenth memory line is 0x00100000, and the start address of the first data line in the data array memory 211 is 0x0000. It is not difficult to see that the first low address of the last 4 bits of the start address of the different memory lines mapped to the same data line is the same, and the last 4 bits are the start address of the data line in the data array memory. And the first two addresses of each data block in the same data line are the same, and the last two addresses of each data block in the same data line are different, so the first two of the last four bits can be used to distinguish different data lines, and the last two of the last two bits can be used to distinguish different data blocks in the same data line. However, since the first memory line, the fifth memory line, the ninth memory line, and the thirteenth memory line in the memory are all mapped to the first data line in the tag array memory 210, only through the last 4 bits in the start address, it is not possible to distinguish which memory line is mapped to the first data line, so the first high address in the start address of the memory line other than the last 4 bits needs to be stored in the tag line associated with the data line in the tag array memory. The first memory line, the fifth memory line, the ninth memory line, and the thirteenth memory line in the memory are mapped to the first data line in the data array memory, and the first high address in the start address of the memory line other than the last 4 bits is saved in the first tag line in the tag array memory.

[0110] When the first memory line in the memory is mapped to the first data line in the data array memory 211, the part 0x0000 of the first memory line start address 0x00000000 except the last 4 bits can be stored in the first tag line in the tag array memory;

[0111] When the fifth memory line in the memory is mapped to the first data line in the data array memory 211, the first high bit address 0x0001 in the first address 0x00010000 of the fifth memory line can be stored into the first tag line in the tag array memory;

[0112] When the ninth memory line in the memory is mapped to the first data line in the data array memory 211, the first high bit address 0x0010 in the first address 0x00100000 of the ninth memory line can be stored into the first tag line in the tag array memory;

[0113] When the thirteenth memory line in the memory is mapped to the first data line in the data array memory 211, the first high bit address 0x0011 in the first address 0x00110000 of the thirteenth memory line can be stored into the first tag line in the tag array memory.

[0114] From the above examples, it can be seen that when different memory lines are mapped to the same data line, the first high bit address stored in the tag line associated with the data line is obviously different, and thus the first high bit address stored in the tag line can be used to determine which memory line in the memory is mapped to the data line.

[0115] When the cache is used to cache data, cache read and cache write are implemented. The cache read and cache write when the cache is used to cache data will be described in detail below.

[0116] When cache write is performed, the processor writes the storage data to the storage address of the cache. The processor writes the storage data to the storage address of the cache is based on the following principle: if the data corresponding to the storage address has been stored in the cache, the storage data can be directly replaced with the data corresponding to the storage address in the cache; if the data corresponding to the storage address has not been stored in the cache, the data corresponding to the storage address needs to be first read from the memory to the cache, and then the storage data is replaced with the data corresponding to the storage address in the cache. The processor writes the storage data to the storage address of the cache will be described in detail below in combination with the circuit diagram of the cache shown in FIG. 3.

[0117] The processor can input a first control signal to the first MUX 207 and the second MUX 208 through the mode selection interface 202 respectively. Under the action of the first control signal, the first MUX 207 and the second MUX 208 perform the following operations:

[0118] The first MUX 207 selects the input signal of the first path (labeled as "1" in the figure) to output to the output end of the first MUX 207, and does not select the input signal of the second path (labeled as "2" in the figure) to output to the output end of the first MUX 207.

[0119] The second MUX 208 selects the input signal of the first path (labeled as "1" in the figure) to output to the output end of the second MUX 208, and does not select the input signal of the second path (labeled as "2" in the figure) to output to the output end of the second MUX 208.

[0120] When the first MUX 207 and the second MUX 208 are 2-way selectors, the first control signal can be "0" or "1"; when the first MUX 207 and the second MUX 208 are 4-way selectors, the first control signal can be any one of "00", "01", "10" or "11"; and so on, when the first MUX 207 and the second MUX 208 are more-way selectors, the number of bits of the first control signal can be more, which is not limited here.

[0121] The processor outputs a write signal to the tag array memory 210 through the tag read-write interface 205, and the processor can input a storage address to the tag logic 206 through the address input interface 203, and then the tag logic 206 divides the storage address into a first high-bit address and a first low-bit address. The write signal can be a high level or a low level. The first high-bit address is the address of the first few bits of the storage address, and the first low-bit address is the address of the last few bits of the storage address. The first high-bit address and the first low-bit address are spliced together to obtain the complete storage address. For example, assuming that the storage address is 0x00010000, the first high-bit address can be the first 4 bits 0x0001 of the storage address, and the first low-bit address can be the last 4 bits 0x0000 of the storage address. The first 4-bit address 0x0001 and the last 4-bit address 0x0000 are spliced together to obtain the storage address 0x00010000.

[0122] The number of bits of the first low-bit address is determined by the number of data blocks in the data array memory and the number of data rows in the data array memory. The first high-bit address is obtained by subtracting the first low-bit address from the storage address. The relationship between the number of bits of the first low-bit address and the number of data blocks in the data array memory and the number of data rows in the data array memory is that, when the number of data blocks in the data array memory is constant, the more the number of data rows in the data array memory is, the more the number of bits of the first low-bit address is; and when the number of data rows in the data array memory is constant, the more the number of data blocks in the data array memory is, the more the number of bits of the first low-bit address is.

[0123] The first low address can be divided into a first high part and a first low part, the first high part is used to indicate a data row in the data array memory, and the first low part is used to indicate a data block in the data array memory. The first low address can be obtained by splicing the first high part and the first low part. The number of digits of the first high part is determined by the number of data rows in the data array memory. For example, if the number of data rows in the data array memory is 2, 1 digit is needed to indicate; if the number of data rows in the data array memory is 4, 2 digits are needed to indicate; if the number of data rows in the data array memory is 8, 3 digits are needed to indicate, and so on. The number of digits of the first low part is determined by the number of data blocks in the data array memory. For example, if the number of data blocks in the data array memory is 2, 1 digit is needed to indicate; if the number of data blocks in the data array memory is 4, 2 digits are needed to indicate; if the number of data blocks in the data array memory is 8, 3 digits are needed to indicate, and so on. Therefore, if the number of data rows in the data array memory is 4, and the number of data blocks in the data array memory is 8, the first high part of the first low address is 2 digits, and the first low part is 2 digits, so the total number of digits of the first low address is 4 digits.

[0124] The first high part is used to indicate a data row in the data array memory, that is, when the number of digits of the first high part is different, the first high part indicates different data rows respectively. For example, assuming that the number of digits of the first high part is 2, when the value of the first high part is “00”, it is used to indicate the first data row in the data array memory; when the value of the first high part is “01”, it is used to indicate the second data row in the data array memory; when the value of the first high part is “10”, it is used to indicate the third data row in the data array memory; and when the value of the first high part is “11”, it is used to indicate the fourth data row in the data array memory. The above example only illustrates the relationship between each value and data row when the number of digits of the first high part is 2. When the number of digits of the first high part is more, the relationship between each value and data row can be extended by analogy, which is not described here.

[0125] The first low bit part is used to indicate the data block of the data row in the data array memory. When the digits of the first low bit part are different values, the first low bit part respectively indicates different data blocks. For example, assuming that the digits of the first low bit part are 2 bits, when the value of the first low bit part is "00", it is used to indicate the first data block in the data row, when the value of the first low bit part is "01", it is used to indicate the second data block in the data row, when the value of the first low bit part is "10", it is used to indicate the third data block in the data row, and when the value of the first low bit part is "11", it is used to indicate the fourth data block in the data row. The above example only illustrates the relationship between the values of the first low bit part and the data blocks when the digits of the first low bit part are 2 bits, and the relationship between the values of the first low bit part and the data blocks can be analogized when the number of the digits of the first low bit part is more, which will not be described here.

[0126] Therefore, in combination with the first high bit part and the first low bit part of the first low bit address, it can be determined which data row and which data block. For example, when the first high bit part of the first low bit address is "01" and the first low bit part is "10", it is determined that the third data block of the second data row. The above example only illustrates the relationship between the combination of one first low bit part and one first high bit part and the data row and the data block, and the relationship between the combination of other first low bit part and first high bit part and the data row and the data block can be analogized, which will not be described here.

[0127] The number of bits of the first high bit address is determined by the total number of storage addresses and the total number of the first low bit address. When the total number of storage addresses is constant, the more the total number of the first low bit address is, the less the total number of the first high bit address is; when the total number of storage addresses is constant, the less the total number of the first low bit address is, the more the total number of the first high bit address is. When the total number of the first low bit address is constant, the more the total number of storage addresses is, the more the total number of the first high bit address is; when the total number of the first low bit address is constant, the less the total number of storage addresses is, the less the total number of the first high bit address is. For example, assuming that the total number of storage addresses is 8 bits and the number of digits of the first low bit address is 4 bits, then the number of bits of the first high bit address is 4 bits.

[0128] The first high bit address is used to map which storage row to the data row. The following will illustrate how the first high bit address determines which storage row is mapped to the data row by combining specific examples.

[0129] Corresponding to the first data line, when the first high bit address is 0x0000, it indicates that the first storage line is mapped into the first data line; when the first high bit address is 0x0001, it indicates that the fifth storage line is mapped into the first data line; when the first high bit address is 0x0010, it indicates that the ninth storage line is mapped into the first data line; when the first high bit address is 0x0011, it indicates that the thirteenth storage line is mapped into the first data line;

[0130] Corresponding to the second data line, when the first high bit address is 0x0000, it indicates that the second storage line is mapped into the first data line; when the first high bit address is 0x0001, it indicates that the sixth storage line is mapped into the first data line; when the first high bit address is 0x0010, it indicates that the tenth storage line is mapped into the first data line; when the first high bit address is 0x0011, it indicates that the fourteenth storage line is mapped into the first data line;

[0131] Corresponding to the second data line, when the first high bit address is 0x0000, it indicates that the second storage line is mapped into the first data line; when the first high bit address is 0x0001, it indicates that the sixth storage line is mapped into the first data line; when the first high bit address is 0x0010, it indicates that the tenth storage line is mapped into the first data line; when the first high bit address is 0x0011, it indicates that the fourteenth storage line is mapped into the first data line;

[0132] Corresponding to the second data line, when the first high bit address is 0x0000, it indicates that the second storage line is mapped into the first data line; when the first high bit address is 0x0001, it indicates that the sixth storage line is mapped into the first data line; when the first high bit address is 0x0010, it indicates that the tenth storage line is mapped into the first data line; when the first high bit address is 0x0011, it indicates that the fourteenth storage line is mapped into the first data line;

[0133] It can be understood that, in the above example, the number of data lines is four, the number of storage lines is sixteen, and the number of bits of the first high bit address is four, which are taken as examples for description. In actual application, the number of data lines can be less or more, the number of storage lines can be less or more, and the number of bits of the first high bit address can be less or more, which are not limited herein.

[0134] The processor outputs a write signal to the data array memory 211 through the data read-write interface. The tag logic 206 outputs the first high-bit address to the first MUX 207. Since the first MUX 207 selects the input signal of the first path (marked as "1" in the figure) to output to the output end of the first MUX 207 under the action of the first control signal, the first MUX 207 inputs the first high-bit address into the comparator 212. The first low-bit address is input into the first path of the second MUX 208. Since the second MUX 208 selects the input signal of the first path to output to the output end of the second MUX 208 under the action of the first control signal, the second MUX 208 outputs the first low-bit address to the tag array memory 210 and the data array memory 211. The tag array memory 210 reads the data from the data field of the tag row corresponding to the first low-bit address in the tag array memory 210 according to the first low-bit address, and outputs the read data to the comparator 212. As mentioned in the fourth point in the above-mentioned storage mode of the cache, the data row in the data array memory 211 can be any one of the plurality of memory rows loaded from the memory. Therefore, it cannot be determined which row of the plurality of memory rows in the memory is loaded into the data row in the data array memory 211. Therefore, the comparator 212 compares the data found by the tag array memory 210 according to the first low-bit address with the first high-bit address output by the tag logic 206, and performs two different processing modes according to the comparison result. The two different processing modes are:

[0135] The first mode: if the comparison result is the same, it means a hit. That is, the data corresponding to the storage address has been stored in the cache. Therefore, the data array memory 211 stores the storage data input from the value input interface 204 into the data block of the data row found according to the first low-bit address.

[0136] The second mode: if the comparison result is different, it means a miss, that is, the data corresponding to the storage address is not stored in the cache. Therefore, the processor first reads the memory data corresponding to the storage address from the memory into the cache (the specific implementation can be referred to the cache read below), and then the data array memory 211 re-executes the writing of the storage data to the storage address of the cache.

[0137] When a cache read is performed, the processor reads the storage data from the storage address of the cache. The processor reads the storage data from the storage address of the cache based on the following principle: if the data corresponding to the storage address has been stored in the cache, the storage data in the storage address can be directly read from the cache; if the storage data corresponding to the storage address has not been stored in the cache, the storage data corresponding to the storage address needs to be first read from the memory to the cache, and then the storage data in the storage address of the cache is read. The processor reads the storage data from the storage address of the cache will be described in detail below in combination with the circuit diagram of the cache shown in FIG. 3.

[0138] The processor can input a first control signal to the first MUX 207 and the second MUX 208 respectively through the mode selection interface 202. Under the action of the first control signal, the first MUX 207 and the second MUX 208 perform the following operations:

[0139] The first MUX 207 selects the input signal of the first path (marked as "1" in the figure) to output to the output end of the first MUX 207, and does not select the input signal of the second path (marked as "2" in the figure) to output to the output end of the first MUX 207.

[0140] The second MUX 208 selects the input signal of the first path (marked as "1" in the figure) to output to the output end of the second MUX 208, and does not select the input signal of the second path (marked as "2" in the figure) to output to the output end of the second MUX 208.

[0141] The processor outputs a read signal to the tag array memory through the tag read-write interface 205, and the processor can input a storage address to the tag logic 206 through the address input interface 203, then the tag logic 206 will divide the storage address into a first high-bit address and a first low-bit address. The first high-bit address and the first low-bit address can be referred to the description of the cache write above, and will not be described here.

[0142] The processor outputs a read signal to the data array memory 211 through the value input interface 204. The tag logic 206 outputs the first high bit address to the first MUX 207. Since the first MUX 207 selects the input signal of the first path (marked as "1" in the figure) to output to the output terminal of the first MUX 207 under the action of the first control signal, the first MUX 207 inputs the first high bit address to the comparator 212. The first low bit address is input to the first path of the second MUX 208. Since the second MUX 208 selects the input signal of the first path to output to the output terminal of the second MUX 208 under the action of the first control signal, the second MUX 208 outputs the first low bit address to the tag array memory 210 and the data array memory 211. The tag array memory 210 reads the data from the data field of the tag row corresponding to the first low bit address in the tag array memory 210 according to the first low bit address, and outputs the read data to the comparator 212. As mentioned in the fourth point in the above storage mode of the cache, the data row in the data array memory 211 can be any one of the plurality of memory rows loaded from the memory. Therefore, it cannot be determined which row of the plurality of memory rows is loaded into the data row in the data array memory 211 at this time. Therefore, the comparator 212 compares the data found by the tag array memory 210 according to the first low bit address with the first high bit address of the storage address, and performs two different processing modes according to the comparison result. The two different processing modes are:

[0143] The first mode: if the comparison result is the same, it means a hit. That is, the data corresponding to the storage address has been stored in the cache. Therefore, the data array memory 211 reads the corresponding storage data from the low bit address.

[0144] The second mode: if the comparison result is different, it means a miss, that is, the data corresponding to the storage address is not stored in the cache. Therefore, the processor first reads the memory data corresponding to the storage address from the memory to the cache, and then the data array memory 211 re-executes reading the storage data from the storage address of the cache.

[0145] When the cache is used for caching key values, key value reading and key value writing need to be implemented. The key value reading and key value writing of the cache when used for caching key values will be introduced in detail below.

[0146] When the key-value write is performed, the processor writes the key-value to the specified address of the cache. The processor finds the corresponding storage space according to the specified address input by the cache, and writes the key and the value in the storage space. The processor writing the key-value to the storage address of the cache will be described in detail below in combination with the circuit diagram of the cache shown in FIG. 3.

[0147] The processor can input the second control signal to the first MUX 207 and the second MUX 208 respectively through the mode selection interface 202. Under the action of the second control signal, the first MUX 207 and the second MUX 208 perform the following operations:

[0148] The first MUX 207 selects the input signal of the second path (marked as "2" in the figure) to output to the output end of the first MUX 207, and does not select the input signal of the first path (marked as "1" in the figure) to output to the output end of the first MUX 207.

[0149] The second MUX 208 selects the input signal of the second path (marked as "2" in the figure) to output to the output end of the second MUX 208, and does not select the input signal of the first path (marked as "1" in the figure) to output to the output end of the second MUX 208.

[0150] When the first MUX 207 and the second MUX 208 are 2-way selectors, the second control signal can be "1" or "0"; when the first MUX 207 and the second MUX 208 are 4-way selectors, the second control signal can be any one of "00", "01", "10" or "11" except the first control signal; and so on, when the first MUX 207 and the second MUX 208 are more-way selectors, the number of bits of the second control signal can be more, which is not limited here.

[0151] The processor outputs a write signal to the tag array memory through the tag read-write interface 205, and the processor can input the specified address to the second MUX 208 through the address input interface 203.

[0152] The number of bits of the specified address is determined by the number of data blocks in the data array memory and the number of data rows in the data array memory. The relationship between the number of bits of the specified address and the number of data blocks in the data array memory and the number of data rows in the data array memory is: when the number of data blocks in the data array memory is constant, the more the number of data rows in the data array memory, the more the number of bits of the specified address; when the number of data rows in the data array memory is constant, the more the number of data blocks in the data array memory, the more the number of bits of the specified address.

[0153] The specified address can be divided into a second high bit part and a second low bit part, the second high bit part is used to indicate a data row in the data array memory, and the second low bit part is used to indicate a data block in the data array memory. The second high bit part and the second low bit part are spliced to obtain the specified address. The number of digits of the second high bit part is determined by the number of data rows in the data array memory. For example, if the number of data rows in the data array memory is 2 rows, 1 digit is needed to indicate; if the number of data rows in the data array memory is 4 rows, 2 digits are needed to indicate; if the number of data rows in the data array memory is 8 rows, 3 digits are needed to indicate, and so on. The number of digits of the second low bit part is determined by the number of data blocks in the data array memory. For example, if the number of data blocks in the data array memory is 2 rows, 1 digit is needed to indicate; if the number of data blocks in the data array memory is 4 rows, 2 digits are needed to indicate; if the number of data blocks in the data array memory is 8 rows, 3 digits are needed to indicate, and so on. Therefore, if the number of data rows in the data array memory is 4 rows, and the number of data blocks in the data array memory is 8 blocks, the first high bit part in the specified address is 2 bits, and the first low bit part is 2 bits, so the total number of digits of the specified address is 4 bits.

[0154] The second high bit part is used to indicate a data row in the data array memory, that is, when the number of digits of the second high bit part is different, the second high bit part respectively indicates different data rows. For example, assuming that the number of digits of the second high bit part is 2 bits, when the value of the second high bit part is “00”, it is used to indicate the first data row in the data array memory; when the value of the second high bit part is “01”, it is used to indicate the second data row in the data array memory; when the value of the second high bit part is “10”, it is used to indicate the third data row in the data array memory; and when the value of the second high bit part is “11”, it is used to indicate the fourth data row in the data array memory. The above example only illustrates the relationship between each value and the data row when the number of digits of the second high bit part is 2 bits. When the number of digits of the second high bit part is more, the relationship between each value and the data row can be extended by analogy, which is not described here.

[0155] The second low bit part is used to indicate the data block of the data row in the data array memory. When the digits of the second low bit part are different values, the second low bit part respectively indicates different data blocks. For example, assuming that the digits of the second low bit part are 2 bits, when the value of the second low bit part is "00", it is used to indicate the first data block in the data row, when the value of the second low bit part is "01", it is used to indicate the second data block in the data row; when the value of the first low bit part is "10", it is used to indicate the third data block in the data row, and when the value of the second low bit part is "11", it is used to indicate the fourth data block in the data row. The above example only illustrates the relationship between the values of the second low bit part and the data blocks when the digits of the second low bit part are 2 bits, and the relationship between the values of the second low bit part and the data blocks can be analogized when the number of the digits of the second low bit part is more, which will not be described here.

[0156] Therefore, in combination with the second high bit part and the second low bit part of the specified address, it can be determined which data row and which data block. For example, when the second high bit part of the first low bit address is "01" and the second low bit part is "10", it is determined that the third data block of the second data row. The above example only illustrates the relationship between the combination of the second low bit part and the second high bit part and the data row and the data block, and the relationship between the combination of other second low bit parts and second high bit parts and the data row and the data block can be analogized, which will not be described here.

[0157] It can be understood that because the number of bits of the specified address is often the same as the number of bits of the first low bit address of the storage address, when the cache is used to cache the storage data, the number of bits of the storage address is often more than the number of bits of the specified address when the cache is used to cache the key value. In order to be compatible between the two, the same number of bits as the first high bit address can be added before the specified address, so as to obtain the extended specified address, for example, a plurality of "0" or "1" with the same number of bits as the first high bit address can be supplemented before the specified address, so as to obtain the extended specified address.

[0158] The processor outputs a write signal to the data array memory 211 through the data read-write interface 209. Since the processor inputs a specified address to the second MUX 208 through the address input interface 203, and the second MUX 208 selects the input signal of the second path (labeled as "2" in the figure) to output to the output end of the second MUX 208 under the action of the second control signal, the specified address is output to the tag array memory 210 and the data array memory 211. The tag array memory 210 and the data array memory 211 respectively search the data block of the data row found according to the specified address. Similarly, since the first MUX 207 selects the input signal of the second path (labeled as "2" in the figure) to output to the output end of the first MUX 207 under the action of the second level, the key is written into the data block corresponding to the specified address in the tag array memory 210. Then, the data array memory 211 stores the value input from the value input interface 204 into the data block of the data row found according to the specified address. Therefore, the key and the value of the same group are respectively input to the corresponding data blocks of the same data row (tag row or data row) corresponding to the specified address.

[0159] It can be understood that if the processor inputs an extended specified address to the tag logic 206 through the address input interface 203, the tag logic 206 divides the extended specified address into a discarded address and a specified address. The number of bits of the discarded address is equal to the number of bits of the extended specified address minus the number of bits of the specified address. At this time, the first control signal needs to be input to the second MUX 208 to select the signal input from the first path of the second MUX 208 to output to the output end, and then output the specified address to the tag array memory 210 and the data array memory 211. The other contents are similar to those of the specified address, which will not be described here.

[0160] When reading the key value, the processor reads the key value from the specified address of the cache. The processor finds the corresponding storage space according to the specified address input by the cache, and reads the key and the value from the storage space. The processor will be described in detail below in combination with the circuit diagram of the cache shown in FIG. 3.

[0161] The processor can input the second control signal to the first MUX 207 and the second MUX 208 through the mode selection interface 202, respectively. Under the action of the second control signal, the first MUX 207 and the second MUX 208 perform the following operations:

[0162] The first MUX 207 selects the input signal of the second path (labeled as "2" in the figure) to output to the output end of the first MUX 207, and does not select the input signal of the first path (labeled as "1" in the figure) to output to the output end of the first MUX 207.

[0163] The second MUX 208 selects the input signal of the second path (labeled as "2" in the figure) to output to the output end of the second MUX 208, and does not select the input signal of the first path (labeled as "1" in the figure) to output to the output end of the second MUX 208.

[0164] When the first MUX 207 and the second MUX 208 are 2-way selectors, the second control signal can be "1" or "0"; when the first MUX 207 and the second MUX 208 are 4-way selectors, the second control signal can be any one of "00", "01", "10" or "11" except the first control signal; and so on, when the first MUX 207 and the second MUX 208 are more-way selectors, the number of bits of the second control signal can be more, which is not limited here.

[0165] The processor outputs a read signal to the tag array memory 210 through the tag read-write interface 205, and the processor can input a specified address to the tag logic 206 through the address input interface 203. The specific introduction of the specified address can be referred to the key value read in the above, which is not expanded here.

[0166] The processor outputs a read signal to the data array memory 211 through the data read-write interface 209. The processor inputs a specified address to the second MUX 208 through the address input interface 203, and then, under the action of the second control signal, the second MUX 208 selects the input signal of the second path (labeled as "2" in the figure) to output to the output end of the second MUX 208, so that the specified address is output to the tag array memory 210 and the data array memory 211. The tag array memory 210 and the data array memory 211 respectively find the corresponding data row and the corresponding data block according to the specified address. The tag array memory 210 outputs the data found according to the specified address to the comparator 212. Similarly, under the action of the second control signal, the first MUX 207 selects the input signal of the second path (labeled as "2" in the figure) to output to the output end of the first MUX 207, so that the key is output to the comparator 212. Therefore, the comparator 212 compares the data found by the tag array memory 210 according to the specified address with the key, and performs two different processing modes according to the comparison result. The two different processing modes are:

[0167] The first mode: if the comparison result is the same, it means a hit. That is, the value corresponding to the key has been stored in the cache. Therefore, the data array memory 211 reads the value corresponding to the specified address from the data array memory 211.

[0168] The second way: if the comparison result is not the same, it means that there is no hit, that is, the value corresponding to the key is not stored in the cache. Therefore, the data array memory 211 will discard the value found according to the specified address.

[0169] In the above-mentioned way, it is taken as an example that the tag row in the tag array memory and the data row in the data array memory each include a plurality of data blocks. In actual application, the tag row can only include one data block, and the data row in the data array memory includes a plurality of data blocks. At this time, since each tag row can only be used to store one key, although the data row in the data array memory includes a plurality of data blocks, it can only be used to store one value, so as to ensure that the key and the value are one-to-one corresponding. Of course, if one key can correspond to multiple values, for example, the key-value table is a hash table, and a hash collision can occur, multiple values can be stored in the plurality of data blocks of the data row in the data array memory.

[0170] It can be understood that the cache shown in FIG. 3 is only a specific example, and in actual application, it can include more or fewer components, and some parts thereof can be replaced by other components, which are not limited specifically herein. The cache can be arranged in a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DPU), a field-programmable gate array (FPGA), a system on chip (SoC), a solid state disk controller, a memory controller, an embedded processor, etc., and can also be arranged outside the central processing unit (CPU), for example, the cache can be a last level cache (LLC), etc.

[0171] In the above scheme, the excess resources in the cache can be used to implement hardware-accelerated queries on the key-value table. For database applications, the application may include one or more key-value tables, thus requiring queries on these tables. The query performance of the key-value table has a significant impact on the application's performance. Besides querying the key-value table, the application also needs to read and write a large amount of data. When this data needs to be stored in the cache, the key-value table previously stored in the cache will be replaced. Therefore, the next time the key-value table is queried, it cannot be looked up in the cache again; instead, it needs to be loaded from memory into the cache. Since key-value table queries retrieve values ​​based on keys, and there is a one-to-one correspondence between keys and values, and there is also a one-to-one correspondence between the tag rows in the tag array memory and the data rows in the data array memory in the cache, it is possible to consider improving the cache circuitry to utilize the excess resources in the cache for hardware-accelerated queries on the key-value table.

[0172] To better utilize the excess resources of the cache for hardware-accelerated lookups of the key-value table, this can be achieved by adding instructions to the instruction set or by sending data packets to the cache driver.

[0173] (1) One or more of the following instructions can be added to the instruction set:

[0174] A. Key Storage Instruction. A key storage instruction is used to store a key into a tag array memory at a specified address. The key storage instruction may include a key storage instruction name, a specified address, and a key. The key storage instruction name is a constant indicating that the instruction is a key storage instruction; the specified address is a variable indicating the address of the storage space in the tag array memory where the key is stored; and the key is a variable indicating the data stored in the tag array memory. In a specific embodiment, the key storage instruction may be: HsST.key, addr, KEY

[0175] Here, HsST.key is the name of the key storage instruction, addr is the specified address, and KEY is the key. When the processor issues a key storage instruction, it will store the key in the tag array memory at the specified address through the part of writing the key to the tag array memory 210 in the key-value write above.

[0176] B. Value store instruction. The value store instruction is used to store a value into the data array storage at a specified address. The value store instruction can include a value store instruction name, a specified address, and a value. The value store instruction name is a constant indicating that the instruction is a value store instruction. The specified address is a variable indicating the address of the storage space in the data array storage where the value is to be stored. The value is a variable indicating the data to be stored into the data array storage. In one embodiment, the value store instruction can be: HsST.value, addr, VALUE

[0177] where HsST.value is the value store instruction name, addr is the specified address, and VALUE is the value. When the processor issues the value store instruction, the value will be stored into the data array storage at the specified address through the part of the key-value write above.

[0178] C. Key-value store instruction. The key-value store instruction is used to store a key and a value into the data array storage at a specified address. The key-value store instruction can include a key-value store instruction name, a specified address, a key, and a value. The key-value store instruction name is a constant indicating that the instruction is a key-value store instruction. The specified address is a variable indicating the address of the storage space in the tag array storage where the key is to be stored, and the address of the storage space in the data array storage where the value is to be stored. The key is a variable indicating the data to be stored into the tag array storage. The value is a variable indicating the data to be stored into the data array storage. In one embodiment, the key-value store instruction can be: HsST.keyvalue, addr, KEY, VALUE

[0179] where HsST.keyvalue is the key-value store instruction name, addr is the specified address, KEY is the key, and VALUE is the value. When the processor issues the key-value store instruction, the key will be stored into the tag array storage at the specified address, and the value will be stored into the data array storage at the specified address through the key-value write above.

[0180] D. Value lookup instruction. The value lookup instruction is used to look up a value corresponding to a key according to the key. The value lookup instruction can include a value lookup instruction name, a register, and a key. The value lookup instruction name is a constant indicating that the instruction is a value lookup instruction. The key is a variable indicating the key to be looked up. The register is a variable indicating the register where the value looked up according to the key is to be stored. In one embodiment, the value lookup instruction can be: HsLU reg, KEY

[0181] Wherein, HsLU reg is the value query instruction name, reg is the register, and KEY is the key. When the processor issues the value storage instruction, the key-value read above is used to query the value corresponding to the key according to the key.

[0182] (2) Sending a data packet to the key-value address of the driver. The data includes a load field, an address field, and an operation field. The load field is used to transmit the key / value. The address field is used to indicate the address of the tag array memory or the address of the data array memory. The operation field can be any one of the key storage operation, the value storage operation, the value query operation, and the invalid operation.

[0183] When the operation field is the key storage operation, the address field is the address of the tag array memory 210, and the load field is the key. After receiving the data packet, the driver writes the key in the data field into the tag array memory 210.

[0184] When the operation field is the value storage operation, the address field is the address of the data array memory 211, and the load field is the value. After receiving the data packet, the driver writes the value in the data field into the data array memory 211.

[0185] When the operation field is the value query operation, the address field is not used, and the load field is the key. The key-value read is used to query the value corresponding to the key according to the key, the queried value is written back to the load field, and the driver returns the data packet to the sending end.

[0186] It can be understood that the above-mentioned way of increasing instructions in the instruction set or sending data packets to the driver of the cache to use the excess resources of the cache to realize the hardware accelerated query of the key-value table can also be used in other ways in actual applications, which is not limited here.

[0187] The application further provides a server 300. As shown in FIG. 5, the server 300 includes a processor 301, a memory 303, and a communication interface 304. The processor 301 includes a cache 302. The processor 301, the memory 303, and the communication interface 304 communicate through a bus 305. It should be understood that the number of processors and memories in the server 300 is not limited in the application.

[0188] The processor 301 can include one or more of a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor (MP), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a programmable logic device (PLD), and so on. The PLD can be any one or more of a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), a data processing unit (DPU), a neural network processing unit (NPU), a system on chip (SoC), an offload card, an acceleration card, and so on.

[0189] The memory 303 is generally used to store various running software in the operating system, input and output data, and information exchanged with the external storage, and the like. In order to improve the access speed of the processor 301, the memory 303 needs to have the advantage of fast access speed. In the traditional computer system architecture, dynamic random access memory (DRAM) is usually used as the memory 303. The processor 301 can access the memory 303 at high speed through the memory controller, and perform read and write operations on any storage unit in the memory 303.

[0190] In some possible designs, the memory 303 can include one or more dual-inline-memory-modules (DIMMs). Generally, a DIMM can be used as a memory bank entity, and a memory bank can have two sides. High-end memory banks have memory particles on both sides. We call each side a Rank, that is, a memory bank has a Rank0 and a Rank1. A DIMM can include one or more Ranks. Each Rank can include a plurality of memory chips.

[0191] Data is stored in the memory 303, specifically, in the memory cells in the memory chip. In the embodiments of the present application, the memory cell refers to the smallest unit of memory for storing data. Generally, one memory cell can store 1 bit of data. Of course, some memory cells can also implement multi-value storage. When the DRAM is used as the memory 303, the memory cells (which can also be referred to as DRAM cells) in the DRAM are arranged and distributed in a matrix, which is referred to as a memory bank or a DRAM bank. According to this manner, the memory cells in one memory chip can be logically divided into a plurality of memory banks, and each memory bank can be regarded as a memory array composed of a plurality of memory cells. Each memory cell in the memory bank is identified by the row address and the column address where it is located, and the memory controller can locate any memory cell in the memory bank through the corresponding row and column decoders. In the embodiments of the present application, the memory bank can also be referred to as the bank.

[0192] The communication interface 304 uses a transceiving module such as but not limited to a network interface card and a transceiver to implement the communication between the server and other devices or communication networks.

[0193] The bus 305 can be a peripheral component interconnect Express (PCIe) bus or an extended industry standard architecture (EISA) bus, a unified bus (Ubus or UB), a compute express link (CXL), a cache coherent interconnect for accelerators (CCIX), etc. The unified bus can also be referred to as a coherent bus. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, only one line is used in FIG. 5, but it does not mean that there is only one bus or only one type of bus. The bus 305 can include a path for transmitting information between various components (for example, the processor 301, the memory 303, and the communication interface 304) of the server 300. The unified bus can also be referred to as a coherent bus.

[0194] As a possible implementation manner, the server 300 can further include a chip including a processing core, a cache and a power supply circuit for performing power supply on the processing core and the cache, and the cache can be the cache shown in FIG. 3. For brevity, details are not described herein. The chip can be implemented by a GPU, or can be implemented by a DPU, a NPU, an XPU, a SoC, an offload card, an acceleration card or an AI chip.

[0195] As a possible implementation manner, the processor 301 can be provided with the cache 302 as shown in FIG. 3. Alternatively, as shown in FIG. 6, the cache shown in FIG. 3 can not be provided in the processor 301, but provided outside the processor 301. Alternatively, the cache 302 as shown in FIG. 3 can be provided in the processor 301 and outside the processor 301.

[0196] The embodiments of the present application further provide a server cluster. As shown in FIG. 7, the server cluster includes at least one server as shown in FIG. 5 or FIG. 6. The server can be a central server, an edge server, or a local server in a local data center, etc.

[0197] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, but not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand: they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the protection scope of the technical solutions of the embodiments of the present application.

Claims

1. A cache, characterized by The cache comprises: a tag array memory comprising a first tag row, the first tag row comprising one or more data blocks; a data array memory comprising a first data row, the first data row comprising one or more data blocks; in a first mode, the first data row is used to store first stored data in the memory, and the first tag row is used to store a first high bit address of a first stored address of the first stored data in the memory, wherein the first high bit address is a bit of the first stored address other than a first low bit address, and the number of bits of the first low bit address is determined according to the number of data rows in the data array memory and the number of data blocks in each data row; in a second mode, the first tag row is used to store a first key in a first key-value pair, and the first data row is used to store a first value in the first key-value pair.

2. The cache of claim 1, wherein the data array memory is configured to, in the first mode, output the first stored data in a corresponding data block in a first data row corresponding to the first low bit address, when the processor needs to read the first stored data from the cache, and data in the corresponding data block in the first data row corresponding to the first low bit address is the same as data in a corresponding data block in the first data row corresponding to the first high bit address.

3. The cache of claim 2, wherein, The cache further comprises a first multiplexer, a second multiplexer, and a comparator. The first multiplexer and the second multiplexer are both configured to, in the first mode and when the processor needs to read the first stored data from the cache, receive a first control signal. The first multiplexer is configured to, under the action of the first control signal, select to input the first high bit address to the tag array memory and the comparator. The second multiplexer is configured to, under the action of the first control signal, select to input the first low bit address to the tag array memory and the data array memory. The tag array memory is configured to output data in a corresponding data block in a first tag row corresponding to the first low bit address to the comparator for comparison. The data array memory is configured to, in the case that the comparison result of the comparator is the same, output the first stored data in the corresponding data block in the first data row corresponding to the first low bit address.

4. The cache of claim 3, wherein the data array memory is configured to, in the second mode, output the first value in a corresponding data block in a first data row corresponding to the first low bit address, when the processor needs to read the first value from the cache, and data in the corresponding data block in the first data row corresponding to the first low bit address is the same as data in a corresponding data block in the first data row corresponding to the first high bit address.

5. The cache of claim 4, wherein The first multiplexing controller and the second multiplexing controller are used in the second mode, and a second control signal is received in a case where the processor needs to read the first key-value pair from a first designated address of the cache; The first multiplexing controller is used to select the first key to be input to the tag array memory and the comparator under the action of the second control signal; The second multiplexing controller is used to select the first designated address to be input to the tag array memory and the data array memory under the action of the second control signal; The tag array memory is used to output data in a corresponding data block of a first tag row corresponding to the first designated address to the comparator for comparison; The data array memory is used to output the first value in a corresponding data block of a first data row corresponding to the first designated address in a case where the comparison result of the comparator is same, the first designated address and the first low address being same.

6. The cache according to claim 2, wherein, The data array memory is used to write the second storage data into a corresponding data block of a second data row corresponding to the second low address in the data array memory in a case where the second storage address in the second mode, the processor needs to write second storage data to the cache to the memory, and data in a corresponding data block of a second data row corresponding to a second high address in the second storage address and a second low address in the second storage address of the tag array memory are same.

7. The cache of claim 6, wherein, The tag array memory includes a second tag row, and the data array memory includes a second data row, The first multiplexing controller and the second multiplexing controller are used in the first mode, and a first control signal is received in a case where the processor needs to write second storage data to the cache; The first multiplexing controller is used to select a second high address in the second storage address to be input to the tag array memory and the comparator under the action of the first control signal; The second multiplexing controller is used to select a second low address in the second storage address to be input to the tag array memory and the data array memory under the action of the first control signal; The tag array memory is used to output data in a corresponding data block of a second tag row corresponding to the second low address to the comparator for comparison; The data array memory is used to write the second storage data into a corresponding data block of a second data row corresponding to the second low address in the data array memory in a case where the comparison result of the comparator is same.

8. The cache according to claim 7, wherein, The data array memory is configured to, in the second mode, write the second value into a corresponding data block of a second data row corresponding to the second specified address in the data array memory, when the processor needs to write a second key-value pair into a second specified address of the cache, and a second key in the second key-value pair is the same as data in a corresponding data block of a second tag row corresponding to the second specified address of the tag array memory.

9. The cache according to claim 8, wherein, The first multiplexer and the second multiplexer are configured to, in the second mode, receive a second control signal when the processor needs to write a second key-value pair into a second specified address of the cache. The first multiplexer is configured to, under the action of the second control signal, select to input a second key in the second key-value pair into the tag array memory and the comparator. The second multiplexer is configured to, under the action of the second control signal, select to input the second specified address into the tag array memory and the data array memory. The tag array memory is configured to output data in a corresponding data block of a second tag row corresponding to the second specified address into the comparator for comparison. The data array memory is configured to, in the second mode, write the second value into a corresponding data block of a second data row corresponding to the second specified address in the data array memory, when the processor needs to write a second key-value pair into a second specified address of the cache, and a second key in the second key-value pair is the same as data in a corresponding data block of a second tag row corresponding to the second specified address of the tag array memory.

10. A chip, characterized by A chip includes a processing core, a cache, and a power supply circuit, wherein the power supply circuit is configured to supply power to the processing core and the cache, and the cache is the cache according to any one of claims 1 to 9.

11. A server, characterized by A chip includes a power supply system and a chip, wherein the power supply system is configured to supply power to the chip, and the chip is the chip according to claim 10.

12. A server, characterized by A chip includes a processing core, a cache, and a power supply circuit, wherein the power supply circuit is configured to supply power to the processing core and the cache, and the cache is the cache according to any one of claims 1 to 9.

13. A server cluster, characterized by A plurality of servers include at least one server according to claim 12.

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