Communication method and communication apparatus based on LDPC code

Abstract

A communication method and communication apparatus based on an LDPC code. The method comprises: acquiring a first codeword sequence, wherein the first codeword sequence is obtained on the basis of an LDPC matrix, N1 columns among core check columns in the LDPC matrix are truncated columns for rate matching, the N1 columns are columns having the greatest column weights in a core check region of an LDPC base matrix corresponding to the LDPC matrix, and N1 is a positive integer; and performing rate matching on the first codeword sequence. In the method, during rate matching, N1 columns among columns having the greatest weights in a core check region can be selected for truncation, so as to avoid the situation where rate matching can only be implemented by means of puncturing in the core check region, thereby achieving greater flexibility. In addition, since information of the truncated columns are known information at a receiving end, the receiving end can perform decoding more quickly, such that the receiving end can achieve a good decoding performance with a small number of iterations, thereby facilitating an improvement in performance.

Description

A communication method and a communication device based on LDPC code

[0001] The present application claims priority to the Chinese patent application No. 202411030571.X, filed on July 29, 2024, and entitled "A communication method and a communication device based on LDPC code", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the field of channel coding, and more particularly, to a communication method and a communication device based on low-density parity check (LDPC) code. BACKGROUND

[0003] In the field of channel coding, LDPC code is one of the most mature and widely used channel coding schemes. Quasi-cyclic low density parity check (QC-LDPC) code is a structured LDPC code. Due to the unique structure of the check matrix, it can be implemented by using a simple feedback shift register during encoding, which reduces the encoding complexity of LDPC code.

[0004] To implement an LDPC coding scheme with variable code length, rate matching can be performed on the LDPC code. However, in the current rate matching scheme of LDPC code, the puncturing positions of the check matrix are relatively fixed, which makes the rate matching mode less flexible. SUMMARY

[0005] Embodiments of the present application provide a communication method and a communication device based on LDPC code, which can support a more flexible rate matching mode.

[0006] In a first aspect, a communication method based on LDPC code is provided. The method can be performed by a sending end device. In the absence of special description, the "sending end device" in the present application can refer to the sending end device itself (e.g., a network device, a terminal device), a component (e.g., a processor, a chip, or a chip system, etc.) in the sending end device, or a logic module or software capable of realizing all or part of the functions of the sending end device.

[0007] The method includes: obtaining a first codeword sequence, the first codeword sequence being obtained according to an LDPC check matrix, wherein N1 columns in a core check column in the LDPC check matrix are truncated columns in rate matching, the N1 columns belong to columns with the maximum column weight in a core check region of an LDPC base matrix corresponding to the LDPC check matrix, and N1 is a positive integer; and performing rate matching on the first codeword sequence.

[0008] Based on the above scheme, the N1 columns in the column with the largest column weight in the core check region can be selected for truncation during rate matching, thus avoiding rate matching only through puncturing of the core check region, and having stronger flexibility.

[0009] In addition, since the information of the truncated column is known information at the receiving end, the receiving end can decode faster, so that the receiving end can achieve higher decoding performance at a lower number of iterations, which helps to improve performance.

[0010] Exemplarily, the column with the largest column weight in the core check region corresponds to the Z c column in the LDPC check matrix, Z c is the lifting value of the LDPC base matrix, and N1 is less than or equal to Z c , Z c is a positive integer.

[0011] In some implementations, in combination with the first aspect, the N1 rows in the core rows in the LDPC check matrix are truncated rows in rate matching, and the rows to which the N1 rows belong in the LDPC base matrix are the same as the row with the largest row weight in the first matrix, and the first matrix is a matrix composed of the core rows of the LDPC base matrix and the punctured columns in rate matching.

[0012] Based on the above scheme, the truncated row can be located in the row with the largest row weight in the first matrix, so that the row with fewer punctured elements can be retained, facilitating the receiving end to recover the punctured information and improving decoding efficiency.

[0013] In some implementations, in combination with the first aspect, the N1 rows in the core rows in the LDPC check matrix are truncated rows in rate matching, and the rows to which the N1 rows belong in the LDPC base matrix are the same as one of at least two rows with the same check relationship in the first matrix, and the first matrix is a matrix composed of the core rows of the LDPC base matrix and the punctured columns in rate matching.

[0014] Based on the above scheme, since the rows with the same check relationship play the same role in recovering the punctured information, the truncated row is located in one of at least two rows with the same check relationship in the first matrix, which helps the receiving end to recover the punctured information and improve decoding efficiency.

[0015] In some implementations, in combination with the first aspect, the N1 rows in the core rows in the LDPC check matrix are truncated rows in rate matching, and the N1 rows belong to the row with the largest row weight in the core check region of the LDPC base matrix.

[0016] As a possible implementation, the relationship between the N1 rows and the N1 columns is: Ri = mod(Ci + Z c – S, Z c ).

[0017] Where i represents the i-th column in column N1 and the i-th row in row N1, and Ci represents the position of the i-th column in column Z. c In the column, it is located in column Ci, and Ri indicates that the i-th row is in column Z. c Located in row Ri, Z c Let S represent the lift value of the LDPC basis matrix, where S represents the shift value of the LDPC basis matrix at row y and column x. Row y is the row containing row N1 in the LDPC basis matrix, and column x is the column with the largest column weight in the core verification region. x and y are both integers greater than or equal to 0, i is an integer greater than or equal to 0 and less than N1, and Ci and Ri are both greater than or equal to 0 and less than Z. c Integers.

[0018] For example, truncated rows are rows in the LDPC check matrix that are not checked.

[0019] Based on the above scheme, since the LDCP verification matrix contains truncated columns and has N1 columns, by selecting the same number of rows (i.e., N1 rows) as rows not to be verified, the verification process can proceed normally and abnormal verification relationships can be avoided.

[0020] In conjunction with the first aspect, in some implementations, the method further includes: determining a truncated column from the core check column based on the target bitrate, and then determining a punched column from the core check column, wherein the punched column and the truncated column do not overlap, and the punched column is at least one of the core check columns.

[0021] Based on the above scheme, the rate matching scheme of this application includes punching and truncation. While taking into account the limit of the number of columns of punching, truncation can also be used, so it can support higher bit rates, for example, the bit rate can exceed 22 / 23.

[0022] Furthermore, when punctured columns are present, the first few iterations in the decoding process are primarily used for recovering the punctured columns. Since the above scheme determines the truncated columns before determining the punctured columns, the receiver does not need to recover the truncated column information when recovering data; it only needs to recover the punctured columns. Therefore, the receiver can achieve high decoding performance with a lower number of iterations, exhibiting superior performance in high-throughput scenarios.

[0023] In conjunction with the first aspect, in some implementations, the method includes: determining a punch column from the core check column based on the target bitrate, and then determining a truncation column from the core check column, wherein the punch column and the truncation column do not overlap, and the punch column is at least one of the core check columns.

[0024] Based on the above scheme, the rate matching scheme of this application includes punching and truncation. After reaching the limit number of punched columns, it can continue to be shortened, thus supporting higher bit rates, for example, bit rates can exceed 22 / 23.

[0025] In addition, since the puncturing columns are determined first and then the shortening columns are determined, when the receiving end recovers data, the information of the puncturing columns can be recovered first, and the information of the shortening columns does not need to be recovered, so that the receiving end can achieve higher decoding performance at a higher iteration number, and the convergence performance is better.

[0026] Exemplarily, the rate matching on the first codeword sequence includes: not sending information corresponding to the shortening columns and the puncturing columns in the LDPC check matrix.

[0027] In a second aspect, a communication method based on an LDPC code is provided, which can be executed by a receiving end device. In the absence of special instructions, the receiving end device in the present application can refer to the receiving end device itself (for example, a network device or a terminal device), a component (for example, a processor, a chip, or a chip system) in the receiving end device, or a logic module or software capable of realizing all or part of the functions of the receiving end device.

[0028] The method includes: obtaining a second received value sequence; and performing de-rate matching on the second received value sequence according to positions of shortening columns in rate matching, wherein the shortening columns are N1 columns in core check columns of an LDPC check matrix, the N1 columns belong to columns with the maximum column weight in a core check region of an LDPC base matrix corresponding to the LDPC check matrix, and N1 is a positive integer.

[0029] Based on the above scheme, when rate matching, the N1 columns in the columns with the maximum column weight in the core check region can be selected for shortening, so that rate matching can be realized only by puncturing in the core check region, and stronger flexibility is achieved.

[0030] In addition, since the information of the shortening columns is known information at the receiving end, the receiving end can decode faster, so that the receiving end can achieve higher decoding performance at a lower iteration number, which helps to improve performance.

[0031] Exemplarily, the columns with the maximum column weight in the core check region correspond to Z c columns in the LDPC check matrix, Z c is a lifting value of the LDPC base matrix, N1 is less than or equal to Z c , and Z c is a positive integer.

[0032] In some implementations, in the core rows of the LDPC check matrix, the N1 rows are shortening rows in rate matching, the rows to which the N1 rows belong in the LDPC base matrix are the same as the rows with the maximum row weight in the first matrix, and the first matrix is a matrix composed of the core rows of the LDPC base matrix and the puncturing columns in rate matching.

[0033] In some implementations, in the core rows of the LDPC check matrix, the N1th row is a shortened row in rate matching, the N1th row is identical to one of at least two rows in the LDPC base matrix to which the N1th row belongs, and the at least two rows have the same check relationship in the first matrix, the first matrix being a matrix composed of the core rows of the LDPC base matrix and punctured columns in rate matching.

[0034] In some implementations, in the core rows of the LDPC check matrix, the N1th row is a shortened row in rate matching, the N1th row belongs to a row with the largest row weight in the core check region of the LDPC base matrix.

[0035] As a possible implementation, the relationship between the N1th row and the N1th column is: Ri = mod(Ci + Z c -S, Z c ).

[0036] wherein i represents the ith column in the N1 columns and the ith row in the N1 rows, Ci represents the position of the ith column in the Z c th column, Ri represents the position of the ith row in the Z c th row, Z c represents a lifting value of the LDPC base matrix, S represents a shift value of the LDPC base matrix corresponding to the yth row and the xth column, the yth row being a row to which the N1th row belongs in the LDPC base matrix, the xth column being a column with the largest column weight in the core check region, x and y each being an integer greater than or equal to 0, i being an integer greater than or equal to 0 and less than N1, and Ci and Ri each being an integer greater than or equal to 0 and less than Z c .

[0037] Exemplarily, the shortened row in the present application is a row that is not checked in the LDPC check matrix.

[0038] Exemplarily, the rate dematching of the second received value sequence according to the shortened column in rate matching comprises: rate dematching the second received value sequence according to the position of the shortened column and the position of the shortened row.

[0039] In some implementations, the method further comprises: determining the punctured column from the core check column according to the target code rate, and then determining the shortened column from the core check column, the punctured column and the shortened column being non-overlapping, and the punctured column being at least one column of the core check column.

[0040] In some implementations, the method further comprises: determining the shortened column from the core check column according to the target code rate, and then determining the punctured column from the core check column, the punctured column and the shortened column being non-overlapping, and the punctured column being at least one column of the core check column.

[0041] Exemplarily, the second received value sequence is de-rate matched according to the truncated column and the punctured column in the rate matching, including: de-rate matching the second received value sequence according to the position of the truncated column and the position of the punctured column.

[0042] Optionally, the second received value sequence is de-rate matched according to the position of the truncated column and the position of the punctured column, including: setting different log-likelihood ratios at the truncated column and the punctured column.

[0043] In a third aspect, a communication method based on an LDPC code is provided, which can be executed by a sending end device. In the absence of special instructions, the sending end device in the present application can refer to the sending end device itself (for example, a network device or a terminal device), a component (for example, a processor, a chip, or a chip system) in the sending end device, or a logic module or software capable of realizing all or part of the functions of the sending end device.

[0044] The method comprises: encoding an information bit sequence according to an LDPC check matrix to obtain a first codeword sequence, wherein N1 columns in a core check column in the LDPC check matrix are truncated columns in rate matching, the N1 columns belong to columns with the largest column weight in a core check region of an LDPC base matrix corresponding to the LDPC check matrix, and N1 is a positive integer; performing rate matching on the first codeword sequence to obtain a second codeword sequence; and outputting the second codeword sequence.

[0045] Based on the above scheme, the N1 columns with the largest column weight in the core check region can be selected for truncation during rate matching, which avoids rate matching through puncturing of the core check region only, and has stronger flexibility.

[0046] In addition, since the information of the truncated column is known information at the receiving end, the receiving end can decode faster, so that the receiving end can achieve higher decoding performance at a lower iteration number, which helps to improve performance.

[0047] Exemplarily, the column with the largest column weight in the core check region corresponds to a Z c column in the LDPC check matrix, Z c is a lifting value of the LDPC base matrix, N1 is less than or equal to Z c , and Z c is a positive integer.

[0048] In combination with the third aspect, in some implementations, N1 rows in the core row in the LDPC check matrix are truncated rows in rate matching, the row to which the N1 rows belong in the LDPC base matrix is the same as the row with the largest row weight in a first matrix, and the first matrix is a matrix composed of the core row of the LDPC base matrix and the punctured column in rate matching.

[0049] In some implementations, in the third aspect, the N1 rows in the core rows in the LDPC check matrix are shorted rows in rate matching, and the N1 rows belong to one of at least two rows in the LDPC base matrix which have the same check relationship as the first matrix, the first matrix being a matrix composed of the core rows in the LDPC base matrix and the punctured columns in the rate matching.

[0050] In some implementations, in the third aspect, the N1 rows in the core rows in the LDPC check matrix are shorted rows in rate matching, and the N1 rows belong to a row with the largest row weight in the core check region in the LDPC base matrix.

[0051] As a possible implementation, the relationship between the N1 rows and the N1 columns is: Ri = mod(Ci + Z c -S, Z c ).

[0052] wherein i represents the ith column in the N1 columns and the ith row in the N1 rows, Ci represents the position of the ith column in the Z c columns, Ri represents the position of the ith row in the Z c rows, Z c represents the lifting value of the LDPC base matrix, S represents the shift value of the LDPC base matrix corresponding to the yth row and the xth column, the yth row being the row to which the N1 rows belong in the LDPC base matrix, the xth column being the column with the largest column weight in the core check region, x and y being integers greater than or equal to 0, i being an integer greater than or equal to 0 and less than N1, Ci and Ri being integers greater than or equal to 0 and less than Z c .

[0053] Exemplarily, the shorted rows are rows that are not checked in the LDPC check matrix.

[0054] In some implementations, in the third aspect, the method further comprises: determining the punctured columns from the core check columns according to the target code rate before determining the shorted columns from the core check columns, the punctured columns and the shorted columns being non-overlapped, and the punctured columns being at least one of the core check columns.

[0055] In some implementations, in the third aspect, the method comprises: determining the punctured columns from the core check columns according to the target code rate before determining the shorted columns from the core check columns, the punctured columns and the shorted columns being non-overlapped, and the punctured columns being at least one of the core check columns.

[0056] Exemplarily, the rate matching on the first codeword sequence comprises: not sending information corresponding to the shorted columns and the punctured columns in the LDPC check matrix.

[0057] In a fourth aspect, a communication method based on an LDPC code is provided, which can be performed by a receiving end device. In the present application, the "receiving end device" can refer to the receiving end device itself (e.g., a network device or a terminal device), a component (e.g., a processor, a chip, or a chip system) in the receiving end device, or a logic module or software capable of realizing all or part of the functions of the receiving end device.

[0058] The method comprises: obtaining a second received value sequence; performing de-rate matching on the second received value sequence according to the positions of the truncated columns in the rate matching to obtain a first received value sequence, wherein the truncated columns are N1 columns in a core check column in the LDPC check matrix, the N1 columns belong to the column with the maximum column weight in a core check region of an LDPC base matrix corresponding to the LDPC check matrix, and N1 is a positive integer; and performing decoding on the first received value sequence according to the LDPC check matrix to obtain a decoded information bit sequence.

[0059] Exemplarily, the column with the maximum column weight in the core check region corresponds to Z c columns in the LDPC check matrix, Z c is a lifting value of the LDPC base matrix, and N1 is less than or equal to Z c , and Z c is a positive integer.

[0060] Based on the above scheme, when rate matching, N1 columns in the column with the maximum column weight in the core check region can be selected for truncation, which avoids that rate matching can only be realized through puncturing of the core check region, and has stronger flexibility.

[0061] In addition, since the information of the truncated columns is known information at the receiving end, the receiving end can decode faster, so that the receiving end can achieve higher decoding performance at a lower number of iterations, which helps to improve performance.

[0062] In combination with the fourth aspect, in some implementations, N1 rows in the core rows in the LDPC check matrix are truncated rows in the rate matching, and the row to which the N1 row belongs in the LDPC base matrix is the same as the row with the maximum row weight in the first matrix, and the first matrix is a matrix composed of the core rows of the LDPC base matrix and the punctured columns in the rate matching.

[0063] In combination with the fourth aspect, in some implementations, N1 rows in the core rows in the LDPC check matrix are truncated rows in the rate matching, and the row to which the N1 row belongs in the LDPC base matrix is the same as one of at least two rows with the same check relationship in the first matrix, and the first matrix is a matrix composed of the core rows of the LDPC base matrix and the punctured columns in the rate matching.

[0064] In some implementations, in the core rows of the LDPC check matrix, the N1th row is a shortened row in rate matching, and the N1th row is a row with the largest row weight in the core check region of the LDPC base matrix.

[0065] As a possible implementation, the relationship between the N1th row and the N1th column is: Ri = mod(Ci + Z c -S, Z c ).

[0066] wherein i represents the ith column in the N1 columns and the ith row in the N1 rows, Ci represents the column located at the Ci-th column in the Z c columns, and Ri represents the row located at the Ri-th row in the Z c rows, Z c represents a lifting value of the LDPC base matrix, S represents a shift value of the LDPC base matrix corresponding to the y-th row and the x-th column, the y-th row is a row to which the N1 rows belong in the LDPC base matrix, the x-th column is a column with the largest column weight in the core check region, x and y are integers greater than or equal to 0, i is an integer greater than or equal to 0 and less than N1, and Ci and Ri are integers greater than or equal to 0 and less than Z c .

[0067] Exemplarily, the shortened row in the present application is a row that is not checked in the LDPC check matrix.

[0068] Exemplarily, the rate matching of the second received value sequence according to the shortened column in the rate matching includes: rate matching the second received value sequence according to the position of the shortened column and the position of the shortened row.

[0069] In some implementations, the method further includes: determining the punctured column from the core check column first and then determining the shortened column from the core check column according to the target code rate, the punctured column and the shortened column are not overlapped, and the punctured column is at least one column of the core check column.

[0070] In some implementations, the method further includes: determining the shortened column from the core check column first and then determining the punctured column from the core check column according to the target code rate, the punctured column and the shortened column are not overlapped, and the punctured column is at least one column of the core check column.

[0071] Exemplarily, the rate matching of the second received value sequence according to the shortened column in the rate matching includes: rate matching the second received value sequence according to the position of the shortened column and the position of the punctured column.

[0072] Optionally, the rate matching of the second received value sequence according to the position of the shortened column and the position of the punctured column includes: setting different log-likelihood ratios for the shortened column and the punctured column.

[0073] In a fifth aspect, a communication apparatus is provided. The apparatus is configured to perform the method in the first aspect or its implementation forms. Specifically, the apparatus can include units and / or modules configured to perform the method in the first aspect or its implementation forms, such as a processing unit and / or a transceiving unit.

[0074] In an implementation form, the apparatus is a transmitting device. When the apparatus is a transmitting device, the transceiving unit can be a transceiver, or an input / output interface, or a communication interface; the processing unit can be at least one processor. Optionally, the transceiver is a transceiving circuit. Optionally, the input / output interface is an input / output circuit.

[0075] In another implementation form, the apparatus is a chip, chip system or circuit for use in a transmitting device. When the apparatus is a chip, chip system or circuit for use in a transmitting device, the transceiving unit can be an input / output interface, interface circuit, output circuit, input circuit, pin or related circuitry, etc. on the chip, chip system or circuit; the processing unit can be at least one processor, processing circuit or logic circuit, etc.

[0076] Exemplarily, the processing unit is configured to obtain a first codeword sequence, the first codeword sequence being obtained according to an LDPC check matrix, wherein N1 columns in a core check column in the LDPC check matrix are shortened columns in rate matching, the N1 columns belong to columns with maximum column weight in a core check region of an LDPC base matrix corresponding to the LDPC check matrix, and N1 is a positive integer; and the processing unit is further configured to perform rate matching on the first codeword sequence.

[0077] In a possible implementation form, the processing unit is further configured to determine the shortened columns from the core check columns and then determine the punctured columns from the core check columns according to the target code rate, the punctured columns being non-overlapped with the shortened columns, and the punctured columns being at least one column of the core check columns.

[0078] In a possible implementation form, the processing unit is further configured to determine the punctured columns from the core check columns and then determine the shortened columns from the core check columns according to the target code rate, the punctured columns being non-overlapped with the shortened columns, and the punctured columns being at least one column of the core check columns.

[0079] Exemplarily, the processing unit is specifically configured to not send information of the shortened columns and the punctured columns.

[0080] In a sixth aspect, a communication apparatus is provided. The apparatus is configured to perform the method in the second aspect or its implementation forms. Specifically, the apparatus can include units and / or modules configured to perform the method in the second aspect or its implementation forms, such as a processing unit and / or a transceiving unit.

[0081] In an implementation, the apparatus is a receiving end device. When the apparatus is a receiving end device, the transceiver unit can be a transceiver, or an input / output interface, or a communication interface; the processing unit can be at least one processor. Optionally, the transceiver is a transceiver circuit. Optionally, the input / output interface is an input / output circuit.

[0082] In another implementation, the apparatus is a chip, chip system or circuit for a receiving end device. When the apparatus is a chip, chip system or circuit for a receiving end device, the transceiver unit can be an input / output interface, interface circuit, output circuit, input circuit, pin or related circuitry, etc. on the chip, chip system or circuit; the processing unit can be at least one processor, processing circuit or logic circuit, etc.

[0083] Exemplarily, the transceiver unit is configured to obtain the second received value sequence; and the processing unit is configured to perform de-rate matching on the second received value sequence according to the shortened columns in the rate matching, wherein the shortened columns are N1 columns in the core check columns of the LDPC check matrix, the N1 columns belong to the column weight maximum columns in the core check region of the LDPC base matrix corresponding to the LDPC check matrix, and N1 is a positive integer.

[0084] In a possible implementation, the processing unit is specifically configured to perform de-rate matching on the second received value sequence according to the positions of the shortened columns and the positions of the punctured columns.

[0085] In a possible implementation, the processing unit is further configured to determine the punctured columns from the core check columns before determining the shortened columns from the core check columns according to the target code rate, the punctured columns and the shortened columns are non-overlapped, and the punctured columns are at least one column of the core check columns.

[0086] In a possible implementation, the processing unit is further configured to determine the punctured columns from the core check columns before determining the shortened columns from the core check columns according to the target code rate, the punctured columns and the shortened columns are non-overlapped, and the punctured columns are at least one column of the core check columns.

[0087] Exemplarily, the processing unit is specifically configured to perform de-rate matching on the second received value sequence according to the positions of the shortened columns and the positions of the punctured columns.

[0088] Exemplarily, the processing unit is specifically configured to set different log-likelihood ratios for the shortened columns and the punctured columns.

[0089] In a seventh aspect, a communication apparatus is provided, which is configured to perform the method in the third aspect or its implementation. Specifically, the apparatus can include units and / or modules for performing the method in the third aspect or its implementation, such as a processing unit and / or a transceiver unit.

[0090] In one implementation, the device is a transmitting device. When the device is a transmitting device, the transceiver unit can be a transceiver, an input / output interface, or a communication interface; the processing unit can be at least one processor. Optionally, the transceiver is a transceiver circuit. Optionally, the input / output interface is an input / output circuit.

[0091] In another implementation, the device is a chip, chip system, or circuit used in a transmitting device. When the device is a chip, chip system, or circuit used in a transmitting device, the transceiver unit can be an input / output interface, interface circuit, output circuit, input circuit, pin, or related circuit on the chip, chip system, or circuit; the processing unit can be at least one processor, processing circuit, or logic circuit.

[0092] For example, the processing unit is configured to: encode the information bit sequence according to the LDPC parity check matrix to obtain a first codeword sequence, wherein the N1 column in the core parity column of the LDPC parity check matrix is ​​a truncated column in rate matching, the N1 column belongs to the column with the largest column weight in the core parity region of the LDPC base matrix corresponding to the LDPC parity check matrix, and N1 is a positive integer; the processing unit is further configured to: perform rate matching on the first codeword sequence to obtain a second codeword sequence; the transceiver unit is configured to: output the second codeword sequence.

[0093] In one possible implementation, the processing unit is further configured to: determine a truncated column from the core check column based on the target bitrate, and then determine a punched column from the core check column, wherein the punched column does not overlap with the truncated column, and the punched column is at least one of the core check columns.

[0094] In one possible implementation, the processing unit is further configured to: determine a punch column from the core check column based on the target bit rate, and then determine a truncation column from the core check column, wherein the punch column and the truncation column do not overlap, and the punch column is at least one of the core check columns.

[0095] For example, the processing unit is specifically configured to: not send information about the truncated column and the punched column.

[0096] Eighthly, a communication apparatus is provided for performing the method provided in the fourth aspect or its implementation thereof. Specifically, the apparatus may include units and / or modules for performing the method provided in the fourth aspect or its implementation thereof, such as processing units and / or transceiver units.

[0097] In one implementation, the device is a receiving device. When the device is a receiving device, the transceiver unit can be a transceiver, an input / output interface, or a communication interface; the processing unit can be at least one processor. Optionally, the transceiver is a transceiver circuit. Optionally, the input / output interface is an input / output circuit.

[0098] In another implementation, the apparatus is a chip, a chip system or a circuit for use in a receiving end device. When the apparatus is a chip, a chip system or a circuit for use in a receiving end device, the transceiving unit can be an input / output interface, an interface circuit, an output circuit, an input circuit, a pin or related circuitry, etc. on the chip, the chip system or the circuit; and the processing unit can be at least one processor, a processing circuit or a logic circuit, etc.

[0099] Exemplarily, the transceiving unit is configured to obtain the second received value sequence; and the processing unit is configured to perform de-rate matching on the second received value sequence according to the positions of the shortened columns in the rate matching to obtain the first received value sequence, wherein the shortened columns are N1 columns in the core check columns of the LDPC check matrix, the N1 columns belong to the columns with the largest column weight in the core check region of the LDPC base matrix corresponding to the LDPC check matrix, and N1 is a positive integer; and the processing unit is further configured to perform decoding on the first received value sequence according to the LDPC check matrix to obtain the decoded information bit sequence.

[0100] In a possible implementation, the processing unit is specifically configured to perform de-rate matching on the second received value sequence according to the positions of the shortened columns and the positions of the punctured columns.

[0101] In a possible implementation, the processing unit is further configured to determine the punctured columns from the core check columns first and then determine the shortened columns from the core check columns according to the target code rate, the punctured columns and the shortened columns are non-overlapping, and the punctured columns are at least one column of the core check columns.

[0102] In a possible implementation, the processing unit is further configured to determine the shortened columns from the core check columns first and then determine the punctured columns from the core check columns according to the target code rate, the punctured columns and the shortened columns are non-overlapping, and the punctured columns are at least one column of the core check columns.

[0103] Exemplarily, the processing unit is specifically configured to perform de-rate matching on the second received value sequence according to the positions of the shortened columns and the positions of the punctured columns.

[0104] Exemplarily, the processing unit is specifically configured to set different log-likelihood ratios for the shortened columns and the punctured columns.

[0105] It should be understood that the detailed description of the third aspect, the fifth aspect and the seventh aspect can refer to the first aspect, and the detailed description of the fourth aspect, the sixth aspect and the eighth aspect can refer to the second aspect.

[0106] In a ninth aspect, a communication apparatus is provided, which comprises a memory configured to store a program; and at least one processor configured to execute the computer program or instructions stored in the memory to perform the method provided by any of the above aspects or implementation manners thereof.

[0107] In an implementation manner, the apparatus is a sending-end device or a receiving-end device.

[0108] In another implementation manner, the apparatus is a chip, a chip system or a circuit used in the sending-end device or the receiving-end device.

[0109] In a tenth aspect, a communication apparatus is provided, which includes at least one processor and a communication interface, the at least one processor being configured to acquire a computer program or instructions stored in a memory through the communication interface, so as to execute the method provided in any one of the aspects or the implementation manners thereof. The communication interface can be implemented by hardware or software.

[0110] In an implementation manner, the apparatus further includes the memory.

[0111] In an eleventh aspect, a processor is provided, which is configured to execute the method provided in the aspects.

[0112] For the sending and acquiring / receiving operations of the processor, if no special description is made, or if it is not contrary to the actual role or inherent logic in the related description, it can be understood as the output and receiving, input operations of the processor, or the sending and receiving operations performed by the radio frequency circuit and the antenna, which are not limited in the present application.

[0113] In an eleventh aspect, a computer readable storage medium is provided, which stores program codes for execution by a device, and the program codes include codes for executing the method provided in any one of the aspects or the implementation manners thereof.

[0114] In a twelfth aspect, a computer program product including instructions is provided, which, when executed on a computer, causes the computer to execute the method provided in any one of the aspects or the implementation manners thereof.

[0115] In a thirteenth aspect, a chip is provided, which includes a processor and a communication interface, the processor being configured to read instructions stored in a memory through the communication interface, and execute the method provided in any one of the aspects or the implementation manners thereof. The communication interface can be implemented by hardware or software.

[0116] Optionally, as an implementation manner, the chip further includes the memory, the memory storing the computer program or instructions, and the processor being configured to execute the computer program or instructions stored in the memory, and when the computer program or instructions are executed, the processor is configured to execute the method provided in any one of the aspects or the implementation manners thereof.

[0117] When the method provided in the present application is executed by a chip, the present application does not limit the number of chips for implementing the method of the present application, for example, the method of the present application can be executed by one chip, or two or more chips. When the number of chips for implementing the method of the present application is two or more, the chip manufacturers are not limited, and can be the same manufacturer or different manufacturers.

[0118] In a fourteenth aspect, a communication system is provided, which includes at least one of the transmitter device or the receiver device described above. BRIEF DESCRIPTION OF DRAWINGS

[0119] FIG. 1 is a schematic diagram of a network architecture to which embodiments of the present application can be applied.

[0120] FIG. 2 is a schematic diagram of a check matrix H of an LDPC.

[0121] FIG. 3 is a Tanner graph of a check matrix H of an LDPC.

[0122] FIG. 4 is a schematic diagram of a structure of a check matrix.

[0123] FIG. 5 is a schematic diagram of an information transmission process.

[0124] FIG. 6 is a schematic diagram of a base matrix.

[0125] FIG. 7 is a schematic flowchart of a communication method 700 provided by the present application.

[0126] FIG. 8 is a schematic diagram of a matrix after expansion of a B matrix according to an embodiment of the present application.

[0127] FIG. 9 is a schematic diagram for comparing effects of scheme 1 and scheme 2 provided by the present application.

[0128] FIG. 10 is a schematic flowchart of a communication method 800 provided by the present application.

[0129] FIG. 11 is a schematic block diagram of a communication apparatus 1000 provided by an embodiment of the present application.

[0130] FIG. 12 is a schematic block diagram of a communication apparatus 1100 provided by an embodiment of the present application. DETAILED DESCRIPTION

[0131] To facilitate understanding of the embodiments of the present application, the following explanations are made before the embodiments of the present application are introduced.

[0132] “For indicating” or “indicating” can include for directly indicating and for indirectly indicating, or in other words, “for indicating” or “indicating” can explicitly and / or implicitly indicate.

[0133] The first, second, and the like various numerical numbers are only distinguished for convenience of description, and are not intended to limit the scope of the embodiments of the present application, for example, to distinguish different messages, different information, and the like.

[0134] The "predefined" can be implemented by pre-storing corresponding codes, tables or other means available for indicating related information in the device, and the specific implementation manner is not limited in the present application.

[0135] The "protocol" referred to can refer to a standard protocol in the communication field, for example, can include a long term evolution (LTE) protocol, a new radio (NR) protocol, and a related protocol applied in a future communication system, and the present application is not limited thereto.

[0136] The words "example", "for example", "e.g.", "as an example", and the like are used to indicate that the example is an example, illustration, or description. Any embodiment or design scheme described as "example" in the present application should not be interpreted as more preferred or more advantageous than other embodiments or design schemes.

[0137] The terms "comprise", "include", "have", and their variants mean "including but not limited to", unless otherwise specifically emphasized.

[0138] "at least one" refers to one or more, and "multiple" refers to two or more. "At most one" refers to one or 0.

[0139] "and / or" describes the association relationship of the associated objects, which means that there can be three kinds of relationships, for example, A and / or B can represent: A exists alone, A and B exist together, and B exists alone, where A and B can be singular or plural. The character " / " before and after the word generally means that the associated objects before and after the " / " are in an "or" relationship. The character " / " in the formula generally means division (÷) operation.

[0140] "at least one of (one / column)" or the like refers to any combination of these items, including any combination of single item or multiple items. For example, at least one of a, b and c (one / column) can represent: a, or b, or c, or a and b, or a and c, or b and c, or a, b and c. Where a, b and c can be single or multiple.

[0141] The description related to the sending of messages, information or data by network element A to network element B, and the receiving of messages, information or data from network element A by network element B is intended to indicate which network element the messages, information or data are intended to send to, and does not limit whether they are directly sent or indirectly sent via other network elements.

[0142] The terms "when", "in the event that", "if", and "whether" are all used to indicate that the device will perform corresponding processing under certain objective conditions, and are not limited in time, and do not require the device to have a judgment action when implemented, nor does it mean that there are other limitations.

[0143] In addition, the network architecture and service scenarios described in the embodiments of the present application are used to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application. Those skilled in the art can know that, with the evolution of network architecture and the emergence of new service scenarios, the technical solutions provided by the embodiments of the present application are also applicable to similar technical problems.

[0144] The communication system to which the embodiments of the present application can be applied will be described below.

[0145] The embodiments of the present application can be applied to various communication systems, including but not limited to: a 5th generation (5G) system, an LTE system, a long term evolution-advanced (LTE-A) system, an LTE frequency division duplex (FDD) system, an LTE time division duplex (TDD) system, etc., and can also be applied to future communication systems. In addition, it can also be applied to device to device (D2D) communication, vehicle-to-everything (V2X) communication, machine to machine (M2M) communication, machine type communication (MTC), internet of things (IoT) communication system, narrow band-internet of things (NB-IoT) or other communication systems. In addition, it can also be extended to similar wireless communication systems, such as wireless-fidelity (WiFi), worldwide interoperability for microwave access (WIMAX), and 3rd generation partnership project (3GPP) related communication systems, etc., without limitation.

[0146] The communication system applicable to the embodiments of the present application can include one or more transmitting end devices and one or more receiving end devices. Optionally, one of the transmitting end device and the receiving end device can be a terminal device, and the other can be a network device. Optionally, both the transmitting end device and the receiving end device can be terminal devices. Optionally, both the transmitting end device and the receiving end device can be network devices.

[0147] FIG. 1 is a schematic diagram of a network architecture applicable to the embodiments of the present application. As shown in FIG. 1, the embodiments of the present application can be applicable to both uplink data transmission and downlink data transmission. In FIG. 1, only uplink data transmission or downlink data transmission between one network device and two terminal devices (e.g., terminal device 1 and terminal device 2) is taken as an example. In uplink data transmission, the transmitting end device herein is a terminal device, and the receiving end device is a network device; conversely, in downlink data transmission, the transmitting end device is a network device, and the receiving end device is a terminal device. In addition, the embodiments of the present application are not limited in their applicability to other communication scenarios, for example, they can also be applied to Sidelink communication.

[0148] The terminal device of the present application can also be referred to as a user equipment (UE), an access terminal, a user unit, a user station, a mobile station, a mobile station, a mobile terminal (MT), a remote station, a remote terminal, a mobile device, a user terminal, a terminal, a drone, a wireless communication device, a user agent or a user apparatus, etc. The terminal device in the embodiments of the present application can refer to a device that provides voice and / or data connectivity to users, and can be used to connect people, things and machines, such as handheld devices with wireless connection function, vehicle-mounted devices, etc. The terminal device in the embodiments of the present application can be a mobile phone, a pad, a notebook computer, a palm computer, a mobile internet device (MID), a wearable device, a virtual reality (VR) device, an augmented reality (AR) device, a wireless terminal in industrial control, a wireless terminal in self driving, a wireless terminal in remote medical surgery, a wireless terminal in smart grid, a wireless terminal in transportation safety, a wireless terminal in smart city, a wireless terminal in smart home, etc.

[0149] The network device of the present application can be a device with wireless transceiving function, which can be a device providing wireless communication function service, usually located at the network side, including but not limited to next generation base station (gNodeB, gNB) in 5G system, base station in future mobile communication system, or access node in wireless fidelity (WiFi) system, evolved node B (eNB) in long term evolution (LTE) system, radio network controller (RNC), node B (NB), base station controller (BSC), home base station (such as home evolved NodeB or home Node B, HNB), base band unit (BBU), transmission reception point (TRP), transmitting point (TP), base transceiver station (BTS), satellite, unmanned aerial vehicle, etc. In one network structure, the network device can include a centralized unit (CU) node, or include a distributed unit (DU) node, or be a RAN device including CU node and DU node, or be a RAN device including control plane CU node and user plane CU node, and DU node, or the network device can also be a wireless controller in cloud radio access network (CRAN) scenario, relay station, vehicle-mounted device, wearable device, etc. In addition, the base station can be a macro base station, micro base station, relay node, donor node or combination thereof. The base station can also refer to a communication module, modem or chip for setting in the foregoing device or apparatus. The base station can also be a mobile switching center, and a device assuming base station function in D2D, V2X, M2M communication, network side device in future communication network, device assuming base station function in future communication system, etc. The base station can support networks of the same or different access technologies, without limitation.

[0150] Unless otherwise defined, the apparatuses used in the embodiments of the present application to realize the functions of the terminal device or the network device can refer to the terminal device or the network device itself, or can refer to an apparatus capable of supporting the terminal device or the network device to realize the functions, such as a chip system or a chip, specifically, a system on a chip (SoC) or a Modem. The apparatus can be installed in the terminal device or the network device. In the embodiments of the present application, the chip system can be composed of a chip, or can include a chip and other discrete devices.

[0151] It should also be noted that some embodiments in the present document take the 5G system as an example to introduce specific scheme details. It can be understood that when the scheme is used in other communication systems, for example, the LTE system, or future communication systems, the messages, channels or information in the scheme can be replaced by messages, channels or information capable of realizing corresponding functions in other communication systems, and the present application does not limit this.

[0152] In addition, the embodiments of the present application can be applied to various application scenarios, such as a high throughput scenario, a high reliability scenario, a low latency scenario, a high reliability low latency scenario, or a low power consumption scenario. Among them, the high throughput scenario can be, for example, an enhanced mobile broadband (eMBB) scenario, and the high reliability low latency scenario can be, for example, an ultra reliable low latency communication (URLLC) scenario.

[0153] In order to facilitate understanding of the embodiments of the present application, several concepts or terms related to the embodiments of the present application are briefly described. The concepts or terms described below are described based on the concepts or terms defined in the protocol, but it does not mean that the embodiments of the present application can only be applied to the existing system, and the concepts or terms related to the embodiments of the present application can be applied to future systems. And the specific name of the concept or term (for example, the concept or term related to the functional description) can be adjusted with the development of future systems.

[0154] 1. LDPC code

[0155] The LDPC code is a kind of linear block code. The linear block code is to divide the information sequence to be coded into groups in units of q (q is an integer greater than 0), and then linearly operate the q information bits by an encoder to obtain m (m is an integer greater than or equal to 0) check bits, and then combine the q information bits and the m check bits to obtain a code word with a length n = q + m. The mapping relationship from the q-bit information bits to the n-bit code word is usually represented by a corresponding check matrix H. According to the check matrix H, a code word sequence can be generated to complete the coding process. After the code word sequence is transmitted through a channel, the received signal is decoded by a receiving end device to determine the original information bits. The code rate is R = q / n.

[0156] The check matrix H of the LDPC is a sparse matrix. The number of zero elements in the check matrix H is much larger than the number of non-zero elements, or in other words, the row weight (or column weight) of the check matrix is much smaller than the number of elements in each row (or each column) of the LDPC matrix. The LDPC code with the information bit sequence length equal to q and the code length equal to n can be uniquely determined by the check matrix H thereof.

[0157] Tanner represented the check matrix H in the form of a graph in 1981. This graph is now called a Tanner graph, and the Tanner graph and the check matrix correspond to each other. The Tanner graph is composed of two types of vertices. One type of vertex represents a code word bit and is called a variable node. The other type of vertex is a check node and represents a check constraint relationship. Each check node represents a check constraint relationship. The following will be described in combination with FIG. 2 and FIG. 3.

[0158] FIG. 2 is a schematic diagram of a check matrix H of an LDPC. In FIG. 2, {V i} represents a variable node (VN) set, and {C i} represents a check node (CN) set. Each row of the check matrix H represents a check equation, each check equation corresponds to a check node, each column represents a code word bit, and each code word bit corresponds to a variable node. In FIG. 2, there are 8 variable nodes and 4 check nodes. If a code word bit is included in the corresponding check equation, a line is used to connect the variable node and the check node involved to obtain a Tanner graph.

[0159] FIG. 3 is a Tanner graph of a check matrix H of an LDPC. As shown in FIG. 3, the Tanner graph represents the check matrix of the LDPC. For example, for a check matrix H of size m rows by n columns, the Tanner graph contains two types of nodes, n variable nodes and m check nodes. The n variable nodes correspond to the n columns of the check matrix H, and the m check nodes correspond to the m rows of the check matrix H. A cycle in the Tanner graph is a group of vertices connected to each other, a loop is a cycle that has one vertex in common as a starting point and an ending point, and passes through each node only once. The length of a loop is defined as the number of edges it contains, and the girth of a graph can also be referred to as the perimeter of the graph, which is defined as the minimum cycle length in the graph. In FIG. 3, the girth is 4, as shown by the black line. The variable nodes in the Tanner graph correspond to each column of the check matrix H, i.e., each code bit of the LDPC. The check nodes in the Tanner graph correspond to each row of the check matrix H, i.e., each check bit of the LDPC. The connection between the two types of nodes corresponds to the value of the element in the H matrix. If there is a connection between the i th check node and the j th variable node, it means that the value of the element (i, j) in the H matrix is 1, and if there is no connection, the corresponding element is 0. The connection between the variable nodes and the check nodes can also be referred to as an edge. The connection between the check nodes and the variable nodes can also be described as: the check nodes and the variable nodes have a connection or an edge. The edge relationship between the check nodes and the variable nodes can include the existence of an edge or the non-existence of an edge. In addition, in the Tanner graph, a cycle refers to a closed loop formed by variable nodes, check nodes, and edges connected end to end.

[0160] 2. QC-LDPC code

[0161] The QC-LDPC code is a structured LDPC code. Due to the unique structure of the check matrix, it can be implemented using a simple feedback shift register during encoding, reducing the encoding complexity of the LDPC code. The QC-LDPC code actually used is represented by a base graph (BG). The elements in the BG are 0 or 1. The 1 and 0 in the BG are expanded, and after the expansion is completed, the check matrix H obtained can be used for encoding or decoding. In the embodiments of the present application, the BG can be written in the form of a matrix, which can be referred to as a base matrix H BG BG ​The middle element is 0, indicating that there is no edge in the base graph, and is 1, indicating that there is an edge in the base graph (or indicating that the corresponding check is associated with the corresponding variable). The NR LDPC code involves multiple base graph selection, and the current standard stores two base graphs BG1 and BG2. When the information length is less than or equal to 292, or the information length is less than or equal to 3824 and the code rate is less than or equal to 2 / 3, or the code rate is less than or equal to 0.25, BG2 is used, otherwise BG1 is used. The following describes the extension process of the base matrix.

[0162] Based on the base matrix and the lifting value Z c (lifting size), the base matrix can be extended to a complete check matrix for encoding or decoding. In this application, Z c may also be referred to as an extension factor, a lifting factor, an extension value, an extension coefficient, a lifting size, etc. The extension process is to lift all elements in the base matrix to a Z c ×Z c square matrix, wherein the 0 element is lifted to a Z c ×Z c 0 matrix, and the 1 element is lifted to a unit matrix and cyclically shifted based on the shifting value (SV) corresponding to the 1 element. The cyclic shift can be to the left or to the right, which is not limited in this application. It can be understood that each 1 element in the base matrix corresponds to a shifting value. Taking a 4*4 unit matrix as an example, if the shifting values are 0, 1 and 3, respectively, the cyclic shift matrix after right cyclic shift is as follows:

[0163] (1) When the shifting value is 0 (i.e. remains unchanged), the corresponding matrix after cyclic shift is

[0164] (2) When the shifting value is 1, the corresponding matrix after cyclic shift is

[0165] (3) When the shifting value is 3, the corresponding matrix after cyclic shift is

[0166] It can also be understood that the complete check matrix H can be represented by an exponential matrix H b , each element in H b corresponds to a Z c ×Z c submatrix, and each element identifies the number of times of cyclic shift of the corresponding submatrix from the unit matrix. Thus, the storage space required by the complete check matrix H is greatly reduced. The elements in the exponential matrix H b may also be referred to as QC blocks.

[0167] For example, the QC-LDPC code with code length of 1944 and code rate of 5 / 6 has an exponent matrix H b As shown below:

[0168] As can be seen, the exponent matrix H b has a size of 4 rows and 24 columns, and each element i in the exponent matrix H b represents a Z c order matrix represents a circulant shift matrix, i represents a circulant shift value of the circulant shift matrix, and i is an integer. In addition, “-1” in the exponent matrix H b represents an all-zero matrix, and “0” represents an identity matrix.

[0169] For example, As shown below:

[0170] Alternatively, the zero element in the exponent matrix H b may be represented in other forms in addition to “-1”, such as using “-” or a null value to represent an all-zero matrix.

[0171] It can be understood that the matrix corresponding to the change of the positions greater than and equal to 0 in the above exponent matrix H b to 1 and the positions of -1 to 0 is a base matrix. The 1 in the base matrix is extended to a circulant shift matrix based on the element in the corresponding position of the exponent matrix, and the 0 is extended to a 0 matrix of the corresponding size. After the extension is completed, the check matrix is obtained.

[0172] 3, lifting size Z c (lifting size, LS) and shifting value (SV)

[0173] The storage content of the 5G LDPC code with respect to the shifting value includes: (1) a lifting size list; and (2) a shifting value list corresponding to each row of the lifting size list. In this application, the shifting value can also be referred to as an offset value, a shift value, etc.

[0174] The current data channel supports information bit ranges from 1 to 8448, and the standard describes two check matrices, BG1 and BG2. For a BG, different Z c are needed to adapt to rate matching of different code lengths. Therefore, the storage of the Z c list and the shifting value list is needed, and then rate matching can be performed based on the Z c list and the shifting value list.

[0175] It can be understood that the elements in the base matrix H BG include 0 and 1, i.e. all elements are either 0 or 1. When performing LDPC encoding, it is necessary to determine the lifting value first, and then determine the corresponding shift value based on the selected lifting value to construct the parity check matrix.

[0176] 4. Column weight and row weight

[0177] For a column of the matrix, the column weight can refer to the number of non-zero elements contained in the column. For a row of the matrix, the row weight can refer to the number of non-zero elements contained in the row. It can be understood that the matrix involved in the description of the row weight and the column weight is the parity check matrix H.

[0178] The present application does not limit the specific forms of zero elements and non-zero elements. For example, as shown in the parity check matrix H in FIG. 2, "0" is used to represent zero elements and "1" is used to represent non-zero elements. For another example, as described above, "-1" is used to represent zero elements and non-negative values (including 0, 1, 13, 48, etc.) are used to represent non-zero elements in the exponent matrix H b .

[0179] 5. Structure of the parity check matrix

[0180] FIG. 4 is a schematic diagram of the structure of the parity check matrix.

[0181] As shown in (a) of FIG. 4, the parity check matrix can include a high rate region, an all-zero region, an incremental redundancy region, and a raptor-like region. The high rate region can include the A part and the B part shown in (b) of FIG. 4, where the A part corresponds to information bits (or information bits, system bits, etc.), and the B part is a square matrix and corresponds to core check bits (or core check region, core check matrix, or core check bits), where the core check can be the check corresponding to the highest code rate, or can be the check with a degree greater than or equal to 2, or can be the check node corresponding to the row set with the maximum row weight (the row weight is significantly / higher than other rows). The all-zero region can correspond to the C part of (b) of FIG. 4, which is an all-zero matrix. The incremental redundancy region can correspond to the D part of (b) of FIG. 4. The raptor-like region can correspond to the E part of (b) of FIG. 4, which can be a unit matrix and corresponds to the check bits for low code rate extension.

[0182] Wherein the matrix corresponding to the B part can be referred to as the B matrix. Exemplarily, the B matrix in BG1 is as follows:

[0183] The B matrix of BG2 is as follows:

[0184] where "0" represents a zero matrix of Z c x Z c , "1" represents a non-zero matrix of Z c x Z c , and Z c is a positive integer. It can also be said that "0" represents a zero element and "1" represents a non-zero element.

[0185] The check matrix of the LDPC code shown in FIG. 4 adopts a "raptor-like" structure and can be gradually expanded to a low code rate from a high code rate by a core matrix. In actual use, as shown in (a) of FIG. 4, the first X rows and the first Y columns of the check matrix can be intercepted, and as the code rate gradually decreases from high to low, X and Y gradually increase, and the area of the matrix used also gradually expands. The black dotted line in the figure represents the matrix area intercepted at different code rates.

[0186] It should be noted that the check matrix can be represented by an LDPC base matrix (or simply a base matrix), and therefore the structure of the LDPC base matrix is similar to that of the check matrix, which will not be described in detail here.

[0187] 6, Information column and check column

[0188] The columns of the LDPC base matrix are composed of information columns and check columns.

[0189] Information column: corresponding to information bits (or information bits, system bits, etc.), the column corresponding to part A.

[0190] Check column: corresponding to check bits (or check bits, etc.), which can include core check columns and extended check columns, wherein the core check columns are the columns corresponding to part B, and the extended check columns are the columns corresponding to part C or part E. The extended check column can also be referred to as a raptor-like column.

[0191] 7, Core row, core column, core matrix and core check column

[0192] Core row: the row of the core check area corresponding to the LDPC base matrix. In other words, the core row is the row corresponding to the high code rate area, or the row corresponding to part A, part B or part C.

[0193] Core column: can include all information columns and all core check columns. In other words, the core column is the column corresponding to the high code rate area, or the column corresponding to part A + part B.

[0194] Kernel Matrix: A matrix region composed of all kernel rows and all kernel columns of the LDPC base matrix. In other words, the kernel matrix is a high code rate region of the LDPC base matrix, or a portion composed of the A portion and the B portion.

[0195] Kernel Check Column: N columns of the base matrix of the LDPC after the information columns, N being equal to the number of rows corresponding to the kernel rows. For example, if the information columns are 1 to K b , the kernel check columns are K b +1 to K b +N columns.

[0196] 8. Information length, code length, and code rate

[0197] The information length is the length (i.e., the number of bits) of the information bit sequence to be transmitted. The length can be the length of the payload information bits, or the length of the payload information bits after adding cyclic redundancy check (CRC) bits, and the present application does not make a specific limitation.

[0198] The code length refers to the length of the bit sequence to be transmitted, which can be the bit sequence corresponding to the modulated symbols.

[0199] The code rate refers to the ratio of the length of the information bit sequence to be transmitted to the code length.

[0200] Optionally, the above three values can be pre-configured by high layer signaling, medium access control (MAC) layer, or downlink physical layer signal, and can also be obtained or calculated directly by the transceiver. For example, the code length can be determined by the coding and the frame structure, the number of layers, and the modulation scheme of the information bit sequence to be transmitted; the code rate can be indicated in the above manner, or given in the modulation and coding scheme (MCS).

[0201] 9. Rate matching (RM)

[0202] After encoding the bit to be transmitted, the length of the mother code is obtained. However, the channel resources allocated in the communication system do not necessarily match the length of the mother code, so rate matching is needed. Specifically, rate matching refers to processing the bits on the transmission channel to match the carrying capacity of the physical channel, so that the bit rate required by the transmission format is achieved when the channel is mapped. The transmitting device can perform rate matching on the information to be transmitted before transmitting the information, and correspondingly, the receiving device can perform de-rate matching processing on the received information after receiving the information.

[0203] FIG. 5 is a schematic diagram of an information transmission process applicable to the present application. As shown in FIG. 5, information is transmitted from a source, processed by source encoding, channel encoding, modulation, air interface transmission, demodulation, channel decoding, source recovery (or source decoding), and reaches a destination, completing the transmission of information from the source to the destination. The upper layer processes shown in FIG. 5 (including source encoding, channel encoding, and modulation, etc.) are performed at the sending end device, and the lower layer processes shown in FIG. 5 (including demodulation, channel decoding, source recovery, etc.) are performed at the receiving end device. Embodiments of the present application mainly relate to source encoding, channel encoding, channel decoding, and source recovery shown in FIG. 5.

[0204] Taking the information transmission process in FIG. 5 as an example, rate matching can be performed between channel encoding and modulation, and correspondingly, de-rate matching can be performed between demodulation and channel decoding, as shown in FIG. 5. Alternatively, rate matching can also be performed after modulation, and de-rate matching can also be performed before demodulation, without limitation.

[0205] The rate matching method includes puncturing and shortening. Puncturing means that the sending end does not send part of the encoding result, and the receiving end does not know the encoding value and does not have the received value of the channel, so the receiving end obtains a log likelihood ratio (LLR) of 0 at this position, that is, no information is received. Then, the received result is decoded together with other received results, and the information at this position is recovered. The position of puncturing can continue to be sent in the case of unsuccessful decoding of the initial transmission, to obtain the effect of incremental redundancy retransmission. Shortening can also be referred to as shortening. The original intention of shortening is to shorten the mother code, so the part of shortening cannot be retransmitted by incremental redundancy. Specifically, shortening means that the sending end forcibly sets part of the input bits to 0 during encoding, and does not send the content in this part of the encoding result during transmission. However, this part of the bits is a known value at the sending end and the receiving end, so the receiving end can set the LLR of these positions to an infinite value (since the prior probability is 1, the result is infinite after taking the logarithm of the likelihood ratio), and then the received result is decoded together with other received results.

[0206] It should be understood that puncturing and shortening both do not send information at the corresponding positions, but puncturing does not affect the encoding process, that is, the position of puncturing is normally encoded during the encoding process. However, shortening affects the encoding process, that is, the position of shortening is set to 0 during the encoding process.

[0207] The rate matching method provided in the application can be considered as a channel coding scheme, which can be applied to various network devices (e.g., base station devices) as described above, and can also be applied to various terminal devices as described above. Illustratively, the channel coding scheme can be implemented by a channel coding unit in the devices. Correspondingly, the rate dematching method provided in the application can be considered as a channel decoding scheme, which can be applied to various network devices (e.g., base station devices) as described above, and can also be applied to various terminal devices as described above. Illustratively, the channel decoding scheme can be implemented by a channel decoding unit in the devices.

[0208] In the current rate matching scheme, the first two columns of the check matrix of BG1 and BG2 are puncturing columns. From the perspective of the matrix, the column weight of the two columns is very large, and from the perspective of transmitting information, the bits corresponding to the two columns are not transmitted, and the receiving end has no reception information about this part. The receiving end sets the LLR of the two columns to 0 and recovers through decoding.

[0209] For example, the number of columns of the A part of BG1 is 22, the number of columns of the B part is 4, and the number of puncturing columns is 2. The code rate it can support is: 22 / (22+4-2) = 11 / 12 ≈ 0.917. If a code rate higher than this is required, additional puncturing of the check bits is needed.

[0210] FIG. 6 is a schematic diagram of a base matrix of BG1. As shown in FIG. 6, the first 22 columns of the base matrix correspond to the A part, and the last 4 columns of the base matrix correspond to the B part. The dashed box represents the puncturing column. When only the first two columns of the base matrix are punctured, a code rate of 0.917 can be supported. If a code rate higher than this is required, the last column of the base matrix can be punctured, so that a code rate of 22 / (22+4-3) = 0.956 can be achieved.

[0211] However, the above scheme uses a single base graph and a fixed number of information columns, which results in a fixed number of puncturing bits, and thus cannot allocate the number of puncturing bits according to the code rate, making the rate matching method not flexible enough.

[0212] Therefore, the application provides a communication method based on an LDPC code, which can support a more flexible rate matching scheme.

[0213] FIG. 7 is a schematic flowchart of a communication method 700 based on an LDPC code provided in the application. The method includes at least one of the following steps.

[0214] S710, the sending end device acquires a first codeword sequence.

[0215] In the application, the first codeword sequence is obtained according to an LDPC check matrix, that is, the first codeword sequence is an LDPC codeword sequence.

[0216] Exemplarily, S710, the sending device acquires the first codeword sequence, which can mean that the sending device encodes the information bit sequence according to the LDPC check matrix to obtain the first codeword sequence; or can only mean that the sending device knows the specific content of the first codeword sequence. That is, S710 can or can not include the process of encoding, and is not limited.

[0217] It can be understood that if the sending device needs to communicate with the receiving device, that is, the sending device needs to send a signal to the receiving device, the sending device needs to first acquire the information bit sequence corresponding to the signal to be sent to the receiving device.

[0218] Optionally, before S710, the method further includes: the sending device acquires the information bit sequence. Wherein, the sending device acquires the information bit sequence, which can mean that the sending device source encodes the source symbol to generate the information bit sequence, or the sending device acquires the information bit sequence, which can also mean that the sending device receives the information bit sequence from other communication devices, and the application does not limit the way of acquiring the information bit sequence.

[0219] Wherein, the N1 columns in the LDPC check matrix are truncated columns.

[0220] In this application, the truncated column refers to a column that needs to be truncated in the rate matching process, or a column that is not transmitted, or a column that needs to be forced to be set to 0 in the encoding process. In other words, when determining the LDPC check matrix required for encoding, the sending device can set the value of the N1 column to 0, so that in the encoding process, the value of the N1 column is 0, and in the rate matching process, the N1 column is the position that needs to be truncated.

[0221] It should be understood that before encoding, the sending device can determine the position of the column that needs to be rate matched, which includes the position of the truncated column, so that when determining the LDPC check matrix for encoding, the sending device can set the value of the truncated column to 0.

[0222] Wherein, the N1 column belongs to the column with the largest column weight in the core check area of the LDPC base matrix corresponding to the LDPC check matrix, or the N1 column belongs to the same column as the column with the largest column weight in the core check area of the base matrix, and N1 is a positive integer. Or, the N1 column belongs to the xth column in the LDPC base matrix, the xth column represents the column with the largest column weight in the core check area of the base matrix, and x is an integer greater than or equal to 0.

[0223] Specifically, taking Figure 4(b) as an example, the core parity region of the base matrix, also known as the core parity bit, core parity matrix, or core parity unit, refers to the region corresponding to part B of the base matrix. Therefore, it can be understood that column N1 belongs to the column with the largest column weight in part B.

[0224] It should be understood that the N1 column in this application refers to the complete N1 column in the LDPC check matrix. In the case where the LDPC check matrix includes part D as shown in Figure 4(b), each column in the N1 column is composed of columns from part B and columns from part D.

[0225] In this application, the column with the largest column weight in the core verification region corresponds to Z in the LDPC verification matrix. c Z c Z is the lifting value of the LDPC basis matrix. c A column refers to all columns obtained after lifting one column in the base matrix. Therefore, column N1 is the column with the largest column weight in part B, which can be understood as column N1 being Z. c One or more columns in the column, or in other words, column N1, is one or more sub-columns of the column with the largest column weight in part B. Therefore, N1 is less than or equal to Z. c Where N1 is less than Z c This can be understood as the truncated column being a sub-column of the column with the largest column weight in part B, where N1 equals Z. c This can be understood as the truncated column being all sub-columns of the column with the largest column weight in part B.

[0226] For example, taking Figure 6 as an example, the column with the largest column weight in part B is column 0 of part B. Let Z be an example. c If the value is 6, then after the expansion of column 0 of part B, there are a total of 6 columns in the parity check matrix. That is, column 0 of part B of the base matrix consists of 6 sub-columns in the parity check matrix, and column N1 can be at least one of these 6 sub-columns.

[0227] It should be understood that in this application, the row or column numbering can start from 0 and increment by 1 each time, i.e., the numbering can be 0, 1, 2, 3, 4... Alternatively, the row or column numbering can start from 1 and increment by 1 each time, i.e., the numbering can be 1, 2, 3, 4, 5... This application does not limit the numbering. For ease of explanation, unless otherwise specified, the numbering starts from 0.

[0228] Optionally, in this application, the core verification region of the base matrix is ​​an irregular repeat accumulate (IRA) structure.

[0229] It can be understood that the method 700 can be performed by a sending device, and the "sending device" can refer to the sending device itself or a device capable of supporting the sending device to implement the function, and for the convenience of description, the sending device is used to describe below. The sending device can be a terminal device or a network device.

[0230] S720, the sending device rate matches the first codeword sequence to obtain a second codeword sequence.

[0231] In this application, the second codeword is also an LDPC codeword sequence.

[0232] Specifically, the rate matching of the first codeword sequence includes not sending the information of the truncated column.

[0233] Based on the above scheme, when rate matching, the N1 columns in the column with the maximum column weight in the core check region can be selected for truncation, so as to avoid that rate matching can only be realized by puncturing the core check region, and therefore, a more flexible rate matching scheme can be supported.

[0234] In addition, since the information of the truncated column is known information at the receiving end, the receiving end can decode faster, so that the receiving end can achieve higher decoding performance at a lower iteration number, and therefore, the performance can be improved.

[0235] It should be understood that in the 5G peak throughput scenario, the code length is long, and the information number of different scenarios is large (such as 1k-2k, or more than 8k). At present, such a scenario is completely realized by BG1, and if a higher code rate is pursued, the maximum can only be 22 / 23=0.956. If the channel condition is super good and there is no noise at all, the LDPC code cannot achieve a code rate greater than this. Because the number of punctured columns exceeds three columns, the current matrix cannot recover all the encoded values. In addition, this way needs to puncture the core check region additionally, which will cause too many punctured columns, poor decoding threshold, and slow convergence speed, and the performance loss is very large in the high throughput scenario. Through the scheme of the present application, a flexible rate matching scheme can be supported, so that various code rates can be achieved, and the iteration number and high performance advantages are possessed in the high throughput scenario.

[0236] Optionally, the method 700 further includes: S730, the sending device outputs the second codeword sequence.

[0237] The subsequent sending device can map the second codeword sequence to an air interface signal and send the air interface signal to the receiving device.

[0238] Specifically, when the sending device is a chip, it can output the second codeword sequence to other modules (such as a radio frequency module or an antenna) connected to the sending device, and send it to the receiving device by these modules.

[0239] Optionally, the N1 rows in the LDPC check matrix are further included in the core rows, and the number of the truncated columns in the LDPC check matrix is the same as the number of the truncated rows.

[0240] Similar to the truncated columns, the sending device can also set the values of the truncated rows to 0 when determining the LDPC check matrix, so that the values of the N1 rows are all 0 in the encoding process. Further, the sending device performs rate matching on the first codeword sequence, including not sending the information of the truncated rows.

[0241] The position of the truncated row is in the core rows in the LDPC check matrix. In this application, the core row refers to the row corresponding to the core check region. In other words, the core row is the row corresponding to the high code rate region, or the row corresponding to the A part, the B part or the C part in the region shown in (b) of FIG. 4.

[0242] In this application, the truncated row can be understood as a row that is not checked in the LDPC check matrix.

[0243] Specifically, the LDPC check matrix is used to define the check relationship of the codeword. Each row of the check matrix represents an independent check equation, which is used to check whether the bits in the codeword satisfy a specific parity check condition. In the process of encoding and decoding, if a row of the check matrix is all "0", the bits corresponding to the row will not be constrained by any check relationship in the check process.

[0244] It should be understood that, since the rate matching method of this application includes column truncation, which will affect the check relationship, the influence can be eliminated by setting the truncated row to meet the check relationship of the check matrix. That is, the truncated row is mainly set in a way that can still meet the check matrix after introducing the truncated column.

[0245] In this application, the N1 rows in the LDPC check matrix belong to the yth row in the LDPC base matrix, or in other words, the yth row is the position of the N1 rows in the LDPC check matrix in the LDPC base matrix, or in other words, the yth row is the row to which the N1 rows belong in the LDPC base matrix, and y is an integer greater than or equal to 0.

[0246] Wherein, N1 is less than Z c The case that N1 is equal to Z c The case that N1 is equal to Z

[0247] Assuming Z cWhen y is 6, there are 6 rows in the check matrix after the yth row is extended, that is, the yth row of the base matrix is composed of 6 sub-rows in the check matrix, and the N1 rows can be at least one of the 6 sub-rows.

[0248] It should be understood that the N1 rows in the present application refer to the complete N1 rows in the LDPC check matrix, and in the case that the LDPC check matrix includes the C part as shown in (b) of FIG. 4, each row in the N1 rows is composed of a row in the A part, a row in the B part, and a row in the C part.

[0249] Based on the above scheme, since there are truncated columns in the LDPC check matrix and the number of columns is N1 columns, by selecting the same number of rows (i.e., N1 rows) as the rows that are not checked, the check process can be normally performed, and abnormal check relationship can be avoided.

[0250] The possible positions of the yth row are described below.

[0251] As an example, in the case that the rate matching further includes puncturing, the yth row is the same as, or corresponds to, the row with the largest row weight in the first matrix. The first matrix is a matrix composed of the core rows of the LDPC base matrix and the punctured columns of the rate matching.

[0252] Since the first matrix is a matrix composed of the core rows of the LDPC base matrix and the punctured columns of the rate matching, the first matrix represents the content that is punctured, and the row weight of the first matrix represents the number of elements that are punctured. Therefore, the row with the largest row weight in the first matrix can be understood as the row in the core row that is most affected by puncturing, or the row in the core row that has the most punctured elements.

[0253] It should be understood that the punctured columns of the rate matching mentioned in the present application mainly refer to puncturing of the columns corresponding to the A part and / or the B part of the LDPC check matrix. In other words, in the present application, whether the rate matching includes puncturing refers to whether there is at least one column that needs to be punctured in the area composed of the A part and the B part.

[0254] For example, continue to take FIG. 6 as an example for description, FIG. 6 shows the A part and the B part, and therefore the 4 rows are all core rows, and the punctured columns are the first two columns and the last column. Therefore, the first matrix is a matrix composed of the first two columns and the last column in FIG. 6, that is, the first matrix is:

[0255] Among them, the row with the largest row weight in the first matrix is the last two rows, and therefore the yth row can be any one of the two rows. It can also be understood that from the 0th row to the 3rd row, the row weights are 2, 1, 3, and 3 respectively, and therefore the row weights of the last two rows are both the largest, that is, the last two rows both have the most punctured elements.

[0256] Based on the above scheme, the truncated row can be located in the row with the largest row weight in the first matrix, so that the row with fewer punctured elements can be retained, facilitating the receiving end to recover the punctured information and improving the decoding efficiency.

[0257] As another example, in the case where the rate matching further includes puncturing, the y-th row is identical to one of the at least two rows in the first matrix that have the same check relationship, or in other words, the y-th row corresponds to one of the at least two rows in the first matrix that have the same check relationship. The meaning of the first matrix is the same as before.

[0258] In this application, the at least two rows with the same check relationship can be understood as the positions of the 1 elements and / or 0 elements in these rows corresponding to each other, or in other words, these rows are identical. For example, a row has a total of 3 elements, and the 0th, 1st and 2nd elements are 1, 1 and 0 in turn. The row with the same check relationship as this row refers to a row whose 0th, 1st and 2nd elements are 1, 1 and 0 in turn.

[0259] It should be understood that in this application, the rows with the same check relationship refer to the base matrix, not the extended check matrix.

[0260] It should be understood that in this example, the at least two rows in the first matrix with the same check relationship can be the rows with the largest row weight in the first matrix, or can not be the rows with the largest row weight in the first matrix, which is not limited.

[0261] For example, continuing with FIG. 6, the first matrix is shown above, and the elements of the last two rows are all 1, 1 and 1, so the last two rows are not only the rows with the largest row weight in the first matrix, but also the two rows with the same check relationship, that is, in this example, the y-th row can be any one of the last two rows.

[0262] For another example, the first matrix is:

[0263] Among them, the 0th and 2nd rows are both 1, 0 and 1, and the 0th and 2nd rows are both the two rows with the same check relationship, so the y-th row can be any one of the 0th and 2nd rows.

[0264] Based on the above scheme, since the rows with the same check relationship have the same effect when recovering the punctured information, locating the truncated row in one of the at least two rows with the same check relationship in the first matrix helps the receiving end to recover the punctured information and improves the decoding efficiency.

[0265] As another example, in the case where the rate matching does not include puncturing, the y-th row can be the row with the largest row weight in the core check region of the base matrix.

[0266] That is, in the case that the rate matching does not include puncturing columns, N1 subrows in the row with the largest row weight in the core check region of the base matrix can be selected as the shortened rows.

[0267] Specifically, taking (b) of FIG. 4 as an example, the core check region of the base matrix refers to the region corresponding to the B part. Therefore, it can be understood that, in the case that the rate matching does not include puncturing, the yth row is the row with the largest row weight in the B part.

[0268] In an implementation manner, the relationship between the N1 rows and the N1 columns in the present application is: Ri = mod(Ci + Z c -S, Z c ).

[0269] Wherein, i represents the ith column in the N1 columns and the ith row in the N1 rows, Ci represents the column located at the Ci column in the Z c column, Ri represents the row located at the Ri row in the Z c row, S represents the shift value of the LDPC base matrix corresponding to the yth row and the xth column, i is an integer greater than or equal to 0 and less than or equal to N1, Ci and Ri are integers greater than or equal to 0 and less than or equal to Z c , and mod() represents the modulo operation.

[0270] It should be understood that, in the case that the numbering starts from 0, the value range of i is an integer greater than or equal to 0 and less than N1, that is, i = 0, 1, 2, …, (N1-1). The value range of Ci and Ri is an integer greater than or equal to 0 and less than Z c , that is, Ci = 0, 1, 2, …, (Z c -1), and Ri = 0, 1, 2, …, (Z c -1). In the case that the numbering starts from 1, the value range of i is an integer greater than 0 and less than or equal to N1, that is, i = 1, 2, …, N1. The value range of Ci and Ri is an integer greater than 0 and less than or equal to Z c , that is, Ci = 1, 2, …, Z c , and Ri = 1, 2, …, Z c .

[0271] For example, assuming that Z c = 4, S = 1, and N1 = 2, the value of i is 0 and 1. Assuming that C0 = 0 and C1 = 3, that is, the shortened columns are the 2nd and 3rd columns in the 4 columns, and the two columns are the 0th and 3rd columns in the 4 columns after lifting, then:

[0272] (1) When C0 = 0, R0 = mod(3, 4) = 3, indicating that when the shortened column is the 0th column in the 4 columns, the shortened row is the 3rd row in the 4 rows.

[0273] (2) When C1=3, R1=mod(6,4)=2, indicating that when the truncated column is the 3rd column in the 4 columns, the truncated behavior is the 2nd row in the 4 rows.

[0274] The row truncation is described below in combination with FIG. 8.

[0275] FIG. 8 takes BG1 as an example, assuming that Z c =4, the B matrix in BG1 is expanded as shown in FIG. 8, where X0, X1, …, X15 represent 16 rows obtained after the B matrix is expanded, Y0, Y1, …, Y15 represent 16 columns obtained after the B matrix is expanded, and the elements in the positions other than "1" in the figure, i.e., the positions of the blank small boxes in the figure, are all 0. Among them, the column with the largest column weight in the B matrix is the 0th column, and the 0th column in the B matrix includes the 0th column to the 3rd column after expansion, i.e., Y0, Y1, Y2, Y3 in FIG. 8.

[0276] Assuming that N1=1, the value of i is 0. Assuming that C0=0, i.e., the truncated column is the 1st column in the 4 columns, and the 1st column is the 0th column in the 4 columns after promotion, i.e., Y0 in FIG. 8 is set to 0.

[0277] Each row of the system matrix is subjected to an XOR operation to obtain X0, X1, …, X15, and Y0, Y1, …, Y15 can be obtained by encoding X0, X1, …, X15, specifically:

[0278] By performing XOR operations on the 0th row, the 4th row, the 8th row, and the 12th row, formula (1) is obtained: X0^X4^X8^X12=Y0^Y0^Y1^Y4^Y4^Y8^Y8^Y12^Y12=Y1 (1)

[0279] Where "^" represents an XOR operation. Specifically, the XOR operation means that when the two inputs are different, the output is 1; when the two inputs are the same, the output is 0.

[0280] By performing XOR operations on the 1st row, the 5th row, the 9th row, and the 13th row, formula (2) is obtained: X1^X5^X9^X13=Y1^Y1^Y2^Y5^Y5^Y9^Y9^Y13^Y13=Y2 (2)

[0281] By performing XOR operations on the 2nd row, the 6th row, the 10th row, and the 14th row, formula (3) is obtained: X2^X6^X10^X14=Y2^Y2^Y3^Y6^Y6^Y10^Y10^Y14^Y14=Y3 (3)

[0282] By performing XOR operation on the 3rd row, the 7th row, the 11th row and the 15th row, formula (4) is obtained: X3^X7^X11^X15=Y3^Y3^Y0^Y7^Y7^Y11^Y11^Y15^Y15=Y0 (4)

[0283] After Y0-Y3 are obtained, Y4-Y15 can be obtained by performing the XOR operation as described above.

[0284] Since Y0 has been set to 0, formula (4) is not established, and thus formula (4) can not pass the check, and the corresponding row check can be cancelled.

[0285] The row on which the row check is cancelled specifically can be determined by Ri=mod(Ci+Z c -S, Z c ), where Ci=C0, Z c =4. With reference to the examples above, when determining Ri, the yth row can be determined according to the puncturing column first, so that the value of S can be determined, and then the value of Ri can be determined.

[0286] Optionally, in the case where the rate matching includes puncturing, before S710, the method further includes: the sending end device first determines the puncturing column from the core check columns according to the target code rate, and then determines the shortened column from the core check columns, the puncturing column and the shortened column do not overlap, and the puncturing column is at least one column of the core check columns.

[0287] In this application, the code rate refers to the ratio of the length of the information bit sequence to be sent to the code length. The target code rate refers to the code rate expected to be achieved in the encoding process. In the process of rate matching, the coded codeword sequence will also be punctured and / or shortened according to the requirements of the target code rate.

[0288] Specifically, when determining the shortened column, the sending end can first determine the xth column from the base matrix according to the target code rate, and then select at least one sub-column in the xth column from the check matrix obtained by expanding the base matrix, so as to obtain N1 columns. Similarly, when determining the puncturing column, one or more columns are first determined from the base matrix as the positions of puncturing, and then sub-columns in the one or more columns are selected from the check matrix obtained by expanding the base matrix as the puncturing column.

[0289] For example, taking BG1 as an example, as shown in FIG. 6, the number of columns of part A of BG1 is 22, and the number of columns of part B is 4, wherein the 22nd column (numbered from 0) is the column with the maximum number of columns, when the target code rate is between 22 / 23 and 1, all sub-columns of the 22nd column of the base matrix can be selected as the truncated column, and then all sub-columns of the 0th column and the 1st column and part of the sub-columns of the 25th column can be selected as the punctured column. When the target code rate is between 22 / 24 and 22 / 23, part of the sub-columns of the 22nd column of the base matrix can be selected as the truncated column, and then all sub-columns of the 0th column and the 1st column can be selected as the punctured column.

[0290] Based on the above scheme, the rate matching scheme of the present application includes puncturing and truncation, which can support a higher code rate while taking into account the limit of the number of punctured columns, for example, the code rate can exceed 22 / 23.

[0291] In addition, in the presence of punctured columns, the first few rounds of iterations in the decoding process are mainly used for the recovery of the punctured columns. Since the above scheme first determines the truncated column and then determines the punctured column, when recovering the data, the information of the truncated column does not need to be recovered, only the punctured column needs to be recovered, so the receiving end can achieve higher decoding performance at a lower number of iterations, and has better performance in high throughput scenarios.

[0292] The following is an example combined with FIG. 9, when the target code rate is 22 / 23, the scheme shown in FIG. 6 is to puncture the first two columns and the last column of the base matrix, that is, to send the 2nd to 24th columns (denoted as scheme 1), and the scheme of method 700 is to puncture the first two columns of the base matrix and truncate the 22nd column, that is, to send the 2nd to 21st columns and the 23rd to 25th columns (denoted as scheme 2). FIG. 9 is a comparison diagram of the effects of the above two schemes.

[0293] In FIG. 9, the vertical coordinate represents the symbol signal-to-noise ratio (EsN0) required when the block error rate (BLER) reaches 0.01, and the horizontal coordinate represents the number of iterations (iteration). The solid line and the dashed line respectively represent the symbol signal-to-noise ratio required by scheme 1 and scheme 2 when the code rate is 22 / 23, and the number of iterations. As can be seen from FIG. 9, when the number of iterations is less than or equal to 6, scheme 2 has obvious gain compared with scheme 1, especially when the number of iterations is less than 5, the gain is very significant, wherein when the number of iterations is 3, scheme 2 has a gain of more than 1 dB compared with scheme 1.

[0294] Optionally, in the case where the rate matching includes puncturing, before S710, the method further includes: the sending end device first determines the punctured column from the core check column according to the target code rate, and then determines the truncated column from the core check column, the punctured column and the truncated column do not overlap, and the punctured column is at least one column of the core check column.

[0295] For example, taking BG1 as an example, as shown in FIG. 6, the A part of BG1 has 22 columns and the B part has 4 columns, wherein the 22nd column (numbered from 0) is the column with the maximum column weight, when the target code rate is between 22 / 23 and 1, the 0th column and the 1st column and the 25th column can be selected as the puncturing column, and then part of the 22nd column of the base matrix can be selected as the shortening column. When the target code rate is between 22 / 24 and 22 / 23, the 0th column and the 1st column can be selected as the puncturing column, and whether the 25th column needs to be punctured can be determined according to the code rate.

[0296] Based on the above scheme, the rate matching scheme of the present application includes puncturing and shortening, and after reaching the limit number of puncturing columns, shortening can continue, so that a higher code rate can be supported, for example, the code rate can exceed 22 / 23.

[0297] In addition, since the puncturing column is determined first and then the shortening column is determined, when the receiving end recovers data, the information of the puncturing column can be recovered first, and the information of the shortening column does not need to be recovered, so that the receiving end can achieve higher decoding performance at a higher iteration number, and the convergence performance is better.

[0298] FIG. 10 is a schematic flowchart of a communication method 800 based on an LDPC code provided by the present application, which includes at least one of the following steps

[0299] S810, the receiving end device acquires a second received value sequence.

[0300] Since the code word sequence may introduce channel noise signals in the transmission process, the second code word sequence output or sent by the sending end device will reach the receiving end device through the air interface, and the information input or received by the receiving end device is referred to as the second received value sequence in the present application. Specifically, the second received value sequence can be the same as or different from the second code word sequence, and is not limited.

[0301] It can be understood that the method 800 can be executed by the receiving end device, and under the condition that there is no special description, the "receiving end device" can refer to the receiving end device itself, or can refer to a device capable of supporting the receiving end device to realize its functions. For the convenience of description, the receiving end device is used for description hereinafter. The receiving end device can be a terminal device or a network device.

[0302] S820, the receiving end device performs de-rate matching on the second received value sequence according to the position of the shortening column in the rate matching, to obtain a first received value sequence.

[0303] The de-rate matching refers to an inverse process of the rate matching. Specifically, the rate matching is used to align the coded data stream with the actual available number of transmission resources, and usually includes steps such as bit selection and bit interleaving to ensure that the data can adapt to the current channel condition and transmission resource. In the process of de-rate matching, the receiving end device will perform corresponding inverse operations such as de-interleaving and de-bit selection according to the received data to recover the data stream before the rate matching of the sending end device.

[0304] Specifically, the first received value sequence refers to the data stream obtained by the receiving end device after de-rate matching, which can be the same as or different from the first codeword sequence before the rate matching of the sending end device, and is not limited.

[0305] The truncated column is an N1 column in the LDPC check matrix, and the N1 column is a column with the maximum column weight in the core check area of the LDPC base matrix corresponding to the LDPC check matrix.

[0306] Based on the above scheme, the N1 column in the column with the maximum column weight in the core check area can be selected for truncation during rate matching, which avoids the rate matching being realized only by puncturing the core check area, and thus a more flexible rate matching scheme can be supported.

[0307] In addition, since the information of the truncated column is known information at the receiving end, the receiving end can decode faster, so that the receiving end can achieve higher decoding performance at a lower number of iterations, and thus the performance can be improved.

[0308] Optionally, the core row in the LDPC check matrix further includes an N1 row, and the N1 row is a truncated row in the rate matching. In this case, S820 specifically includes: the receiving end device performs de-rate matching on the second received value sequence according to the position of the truncated column in the rate matching and the position of the truncated row to obtain the first received value sequence.

[0309] Optionally, the core check column in the LDPC check matrix further includes a punctured column in the rate matching. In this case, S820 specifically includes: the receiving end device performs de-rate matching on the second received value sequence according to the position of the truncated column in the rate matching, the position of the truncated row, and the position of the punctured column to obtain the first received value sequence.

[0310] For specific introduction of the truncated column, the truncated row, and the punctured column, refer to the method 700, which is not described here.

[0311] Specifically, the receiving end device inserts LLR = positive infinity at the positions of the punctured columns in the process of de-rate matching, and the check results of the punctured columns are not added to the column variables in the process of decoding. If there are punctured columns, the receiving end device inserts LLR = 0 at the positions of the punctured columns in the process of de-rate matching.

[0312] It should be understood that the receiving end device can determine the positions of the columns that need to be de-rate matched before de-rate matching, which includes the positions of the punctured columns. If there are punctured columns, it also includes the positions of the punctured columns.

[0313] Optionally, the method 800 further includes: S830, the receiving end device decodes the first received value sequence according to the LDPC check matrix to obtain a decoded information bit sequence.

[0314] Specifically, when determining the LDPC check matrix required for decoding, the N1 columns have LLR values of infinity, so that in the process of decoding, the values of the N1 columns are all known values. Optionally, when there is puncturing in rate matching, the receiving end determines the LDPC check matrix required for decoding when the LLR values of the punctured columns are 0. The receiving end device uses these LLR values to perform an iterative decoding process, and finally outputs a decoded information bit sequence by constantly updating and exchanging information about bit reliability. The specific decoding method is not limited in the present application.

[0315] It should be understood that, according to the performance of the receiving end device and other factors, the information bit sequence obtained after decoding may be the same as or different from the information bit sequence used when encoding (i.e., in S710).

[0316] Optionally, before S820, the method 800 further includes: the receiving end device determines the punctured columns from the core check columns according to the target code rate, and then determines the punctured columns from the core check columns, the punctured columns and the punctured columns are not overlapped, and the punctured columns are at least one column of the core check columns.

[0317] Specifically, the receiving end device can determine the positions of the punctured columns before de-rate matching, and then determine the positions of the punctured columns, and perform de-rate matching according to the corresponding positions, the same as the sending end device.

[0318] It should be understood that in the process of de-rate matching, the receiving end can also consider factors such as the target code rate to restore the information before the receiving end device rate matches.

[0319] Optionally, before S820, the method 800 further includes: the receiving end device determines the punctured columns from the core check columns according to the target code rate, and then determines the punctured columns from the core check columns, the punctured columns and the punctured columns are not overlapped, and the punctured columns are at least one column of the core check columns.

[0320] Specifically, like the sending device, the receiving device can determine the positions of the punctured columns and the positions of the shortened columns before rate matching, and then perform rate matching according to the corresponding positions.

[0321] It should be understood that the method 800 is not described in detail in the description, and reference can be made to the method 700.

[0322] It can be understood that the steps in the above-described figures are only exemplary and are not strictly limited. In addition, the size of the serial number of the above-described processes does not mean the order of execution, and the execution order of the processes should be determined according to their functions and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0323] It can also be understood that some optional features in the embodiments of the present application can not depend on other features in some scenarios, or can be combined with other features in some scenarios, without limitation.

[0324] It can also be understood that the methods and operations implemented by the device (sending device or receiving device) in the above-described various method embodiments can also be implemented by components (such as chips or circuits) of the device, without limitation.

[0325] The method embodiments provided by the present application are described in detail above in combination with FIGS. 1 to 10. The device embodiments of the present application will be described below in combination with FIGS. 11 and 12. It can be understood that, in order to realize the functions in the above-described embodiments, the device in FIGS. 11 and 12 includes corresponding hardware structures and / or software modules for executing various functions. Those skilled in the art should easily realize that, in combination with the units and method steps of the examples described in the embodiments disclosed in the present application, the present application can be realized in the form of hardware or a combination of hardware and computer software. It can be understood that the technical features described in the above-described method embodiments are also applicable to the following device embodiments.

[0326] FIGS. 11 and 12 are structural schematic diagrams of possible devices provided by the embodiments of the present application. These devices can be used to realize the functions of the sending device or the receiving device in the above-described method embodiments, and thus can also realize the beneficial effects possessed by the above-described method embodiments.

[0327] FIG. 11 is a schematic block diagram of a communication device 1000 provided by the embodiments of the present application. As shown in FIG. 11, the device 1000 can include a communication unit 1010 and a processing unit 1020. The communication unit 1010 can communicate with the outside, and the processing unit 1020 is used for data processing. The communication unit 1010 can also be referred to as a communication interface or a transceiver unit.

[0328] In one possible design, the apparatus 1000 can implement steps or procedures corresponding to those performed by a transmitting-end device in the above-described method embodiments, where the processing unit 1020 is configured to perform processing-related operations of the transmitting-end device in the above-described method embodiments, and the communication unit 1010 is configured to perform transmission-related operations of the transmitting-end device in the above-described method embodiments.

[0329] In another possible design, the apparatus 1000 can implement steps or procedures corresponding to those performed by a receiving-end device in the above-described method embodiments, where the communication unit 1010 is configured to perform receiving-related operations of the receiving-end device in the above-described method embodiments, and the processing unit 1020 is configured to perform processing-related operations of the receiving-end device in the above-described method embodiments.

[0330] It is to be understood that the apparatus 1000 herein is embodied in the form of a functional unit. The term "unit" herein can refer to an application specific integrated circuit (ASIC), an electronic circuit, a processor (shared, dedicated or group) and memory that execute one or more software or firmware programs, a combinational logic circuit, and / or other suitable components that provide the described functionality. In one possible design, the apparatus 1000 can be embodied as the transmitting-end device in the above-described embodiments, and can be configured to perform the procedures and / or steps corresponding to the transmitting-end device in the above-described method embodiments. Alternatively, the apparatus 1000 can be embodied as the receiving-end device in the above-described embodiments, and can be configured to perform the procedures and / or steps corresponding to the receiving-end device in the above-described method embodiments. To avoid redundancy, details are not repeated herein.

[0331] The apparatus 1000 in each of the above-described designs has the functionality to implement the corresponding steps performed by the transmitting-end device in the above-described method embodiments, or has the functionality to implement the corresponding steps performed by the receiving-end device in the above-described method embodiments. The functionality can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above-described functionality; for example, the communication unit can be replaced by a transceiver (e.g., a transmitter in the communication unit can be replaced by a transmitter, and a receiver in the communication unit can be replaced by a receiver), and other units, such as the processing unit, can be replaced by a processor, which performs the corresponding transmission and processing operations in the above-described method embodiments.

[0332] In addition, the communication unit can also be a transceiver (e.g., can include a receiving circuit and a transmitting circuit), and the processing unit can be a processing circuit. In embodiments of the present application, the apparatus in FIG. 11 can be a receiving end device or a transmitting end device in the foregoing embodiments, or can be a chip or a chip system, for example, a system on chip (SoC). Wherein, the communication unit can be an input / output circuit, a communication interface; and the processing unit is a processor or a microprocessor integrated on the chip or an integrated circuit. Herein, no limitation is made.

[0333] FIG. 12 is a schematic block diagram of a communication apparatus 1100 provided by embodiments of the present application. The apparatus 1100 includes a processor 1110 and a transceiver 1120. Wherein, the processor 1110 and the transceiver 1120 communicate with each other through an internal connection path, and the processor 1110 is configured to execute instructions to control the transceiver 1120 to transmit and / or receive signals.

[0334] Optionally, the apparatus 1100 can further include a memory 1130, which communicates with the processor 1110 and the transceiver 1120 through an internal connection path. The memory 1130 is configured to store instructions, and the processor 1110 can execute the instructions stored in the memory 1130. In a possible implementation manner, the apparatus 1100 is configured to implement each process and step corresponding to the transmitting end device in the method embodiments. In another possible implementation manner, the apparatus 1100 is configured to implement each process and step corresponding to the receiving end device in the method embodiments.

[0335] Optionally, the memory 1130 can be integrated in the processor 1110.

[0336] In a possible scenario, the apparatus 1100 includes at least one processor integrated with a memory, and other memories in addition to the memory integrated on the processor.

[0337] It can be understood that the apparatus 1100 can be specifically the transmitting end device or the receiving end device in the foregoing embodiments, or can be a chip or a chip system. Correspondingly, the transceiver 1120 can be a transceiver circuit of the chip, and no limitation is made herein. Specifically, the apparatus 1100 can be configured to execute each step and / or process corresponding to the transmitting end device or the receiving end device in the method embodiments.

[0338] Optionally, the memory 1130 can include read-only memory and random access memory, and provide instructions and data to the processor. The memory can include non-volatile random access memory. For example, the memory can also store device type information. The processor 1110 can be used to execute the instructions stored in the memory, and when the processor 1110 executes the instructions stored in the memory, the processor 1110 is used to perform the steps and / or processes of the above-mentioned method embodiments corresponding to the sending end device or the receiving end device.

[0339] In the implementation process, the steps of the above method can be completed by the integrated logic circuit of the hardware in the processor or the instructions in the form of software. The steps of the method disclosed in combination with the embodiments of the present application can be directly embodied as hardware processor execution completion, or executed by a combination of hardware and software modules in the processor. The software module can be located in a random access memory, a flash memory, a read-only memory, a programmable read-only memory, an electrically erasable programmable memory, a register, and other mature storage media in the art. The storage medium is located in the memory, and the processor reads the information in the memory, and combines the hardware to complete the steps of the above method. To avoid repetition, it will not be described in detail here.

[0340] It should be noted that the processor in the embodiments of the present application can be an integrated circuit chip with signal processing capability. In the implementation process, the steps of the above method embodiments can be completed by the integrated logic circuit of the hardware in the processor or the instructions in the form of software. The above processor can be a general processor, a digital signal processing (digital signal processing, DSP), an ASIC, a field-programmable gate array (field-programmable gate array, FPGA) or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component. The processor in the embodiments of the present application can implement or execute the disclosed methods, steps and logic block diagrams in the embodiments of the present application. The general processor can be a microprocessor or the processor can also be any conventional processor. The steps of the method disclosed in combination with the embodiments of the present application can be directly embodied as hardware decoding processor execution completion, or executed by a combination of hardware and software modules in the decoding processor. The software module can be located in a random access memory, a flash memory, a read-only memory, a programmable read-only memory, an electrically erasable programmable memory, a register, and other mature storage media in the art. The storage medium is located in the memory, and the processor reads the information in the memory, and combines the hardware to complete the steps of the above method.

[0341] It is to be appreciated that the memory in the embodiments of the application can be a volatile memory or a nonvolatile memory, or can include both volatile and nonvolatile memory. Where the nonvolatile memory is, for example, read-only memory (ROM), programmable ROM (PROM), erasable PROM (EPROM), electrically EPROM (EEPROM), or flash memory. The volatile memory, which can be used as external cache, can be, for example, random access memory (RAM), static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), or direct rambus RAM (DR RAM). It is to be appreciated that the memory described herein is intended to include, among other things, these and any other memory suitable for storing or providing program code or instructions to a processor or other system.

[0342] Optionally, the memory (e.g., 1130) in the embodiments of the application can be integrated in the processor (e.g., 1110).

[0343] In addition, the application also provides a computer readable storage medium, the computer readable storage medium stores computer instructions, when the computer instructions run on the computer, the operations and / or processes performed by the sending end device or the receiving end device in the method embodiments of the application are executed.

[0344] The application also provides a computer program product, the computer program product includes computer program code or instructions, when the computer program code or instructions run on the computer, the operations and / or processes performed by the sending end device or the receiving end device in the method embodiments of the application are executed.

[0345] Further, the application provides a chip including a processor. A memory for storing a computer program is arranged independently of the chip, and the processor is configured to execute the computer program stored in the memory, so that the operations and / or processes performed by the sending device or the receiving device in any one of the method embodiments are performed.

[0346] Further, the chip can further include a communication interface. The communication interface can be an input / output interface, an interface circuit, or the like. Further, the chip can further include a memory.

[0347] Further, the application provides a communication system including the sending device and the receiving device in the embodiments of the application.

[0348] It should be further noted that the memory described herein is intended to include, but not limited to, these and any other suitable types of memory.

[0349] Those skilled in the art can appreciate that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether the functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. A person skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the application. Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described system, device and unit can refer to the corresponding processes in the foregoing method embodiments, which will not be described here. In several embodiments provided in the application, it should be understood that the disclosed system, device and method can be implemented in other ways. For example, the above-described device embodiments are only schematic, for example, the division of the units is only a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some interface, device or unit, which can be electrical, mechanical or other form. The units described as separate components can be or can not be physically separate, and the components shown as units can be or can not be physical units, i.e., they can be located in one place, or can be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment. In addition, the functional units in each embodiment of the application can be integrated in one processing unit, or each unit can be physically present, or two or more units can be integrated in one unit.

[0350] If the functions are implemented in the form of software function units and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application essentially or the parts that contribute to the prior art or parts of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes various media that can store program codes, such as a U disk, a mobile hard disk, a ROM, a RAM, a magnetic disk, or an optical disk.

[0351] It can be understood that the "embodiments" mentioned throughout the specification mean that the specific features, structures or characteristics related to the embodiments are included in at least one embodiment of the present application. Therefore, the various embodiments throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner.

[0352] It can also be understood that in the various embodiments of the present application, "A corresponds to B" means that B is associated with A and can be determined according to A. However, it can also be understood that determining B according to A does not mean that B is determined only according to A, but B can also be determined according to A and / or other information.

Claims

1. A communication method based on a low-density parity-check (LDPC) code, characterized by, The method comprises: obtaining a first codeword sequence, the first codeword sequence being obtained according to an LDPC check matrix, wherein N1 columns in a core check column in the LDPC check matrix are shortened columns in rate matching, the N1 columns belong to columns with the largest column weight in a core check region of an LDPC base matrix corresponding to the LDPC check matrix, and N1 is a positive integer; performing rate matching on the first codeword sequence.

2. A communication method based on an LDPC code, characterized by, The method comprises: obtaining a second received value sequence; performing de-rate matching on the second received value sequence according to positions of shortened columns in rate matching, wherein the shortened columns are N1 columns in a core check column in an LDPC check matrix, the N1 columns belong to columns with the largest column weight in a core check region of an LDPC base matrix corresponding to the LDPC check matrix, and N1 is a positive integer.

3. The method according to claim 1 or 2, characterized in that, The column pair with the maximum column weight in the core check region corresponds to Z in the LDPC check matrix c The column pair with the maximum column weight in the core check region corresponds to Z in the LDPC check matrix c Z is the lifting value of the LDPC base matrix, N1 is less than or equal to Z c Z c is a positive integer.

4. The method according to any one of claims 1 to 3, characterized in that, N1 rows in core rows in the LDPC check matrix are shortened rows in the rate matching, the N1 rows belong to the same row as at least one row with the same check relationship in a first matrix in a row to which the N1 rows belong in the LDPC base matrix, and the first matrix is a matrix composed of core rows of the LDPC base matrix and punctured columns in the rate matching.

5. The method according to any one of claims 1 to 3, characterized in that, N1 rows in core rows in the LDPC check matrix are shortened rows in the rate matching, the N1 rows belong to the same row as at least one row with the same check relationship in a first matrix in a row to which the N1 rows belong in the LDPC base matrix, and the first matrix is a matrix composed of core rows of the LDPC base matrix and punctured columns in the rate matching.

6. The method according to any one of claims 1 to 3, characterized in that, The N1 rows belong to rows with the largest column weight in a core check region of the LDPC base matrix.

7. The method according to any one of claims 4 to 6, characterized in that, A relationship between the N1 rows and the N1 columns is: Ri = mod(Ci + Z c - S, Z c ); wherein i represents the ith column in the N1 columns and the ith row in the N1 rows, Ci represents the position of the ith column in the Z c columns, Ri represents the position of the ith row in the Z c rows, Z c represents the lifting value of the LDPC base matrix, S represents the shift value corresponding to the yth row and the xth column of the LDPC base matrix, the yth row is the row to which the N1 rows belong in the LDPC base matrix, the xth column is the column with the maximum column weight in the core check region, x and y are both integers greater than or equal to 0, i is an integer greater than or equal to 0 and less than N1, and Ci and Ri are both integers greater than or equal to 0 and less than Z c .

8. The method according to any one of claims 4 to 7, characterized in that, The shortened rows are rows that are not checked in the LDPC check matrix.

9. The method according to any one of claims 4 to 8, characterized in that, The de-rate matching on the second received value sequence according to the shortened columns in the rate matching comprises: performing de-rate matching on the second received value sequence according to positions of the shortened columns and positions of the shortened rows.

10. The method according to any one of claims 1 to 9, characterized in that, The method further comprises: determining the shortened columns from the core check columns and determining punctured columns in the rate matching from the core check columns according to a target code rate, the punctured columns do not overlap with the shortened columns, and the punctured columns are at least one column of the core check columns.

11. The method according to any one of claims 1 to 9, characterized in that, The method further comprises: determining punctured columns in the rate matching from the core check columns and determining the shortened columns from the core check columns according to a target code rate, the punctured columns do not overlap with the shortened columns, and the punctured columns are at least one column of the core check columns.

12. The method according to claim 10 or 11, characterized in that, The de-rate matching on the second received value sequence according to the shortened columns in the rate matching comprises: performing de-rate matching on the second received value sequence according to positions of the shortened columns and positions of the punctured columns.

13. A communication method based on an LDPC code, characterized by, The method comprises: The information bit sequence is encoded according to an LDPC check matrix to obtain a first codeword sequence, wherein N1 columns in a core check column in the LDPC check matrix are truncated columns in rate matching, the N1 columns belong to columns with the largest column weight in a core check region of an LDPC base matrix corresponding to the LDPC check matrix, and N1 is a positive integer; The first codeword sequence is subjected to rate matching to obtain a second codeword sequence; The second codeword sequence is output.

14. A communication method based on an LDPC code, characterized by, The method comprises: A second received value sequence is obtained; The second received value sequence is subjected to de-rate matching according to positions of truncated columns in rate matching to obtain a first received value sequence, wherein the truncated columns are N1 rows in core rows in an LDPC check matrix, the N1 rows belong to rows with the largest column weight in a core check region of an LDPC base matrix corresponding to the LDPC check matrix, and N1 is a positive integer; The first received value sequence is decoded according to the LDPC check matrix to obtain a decoded information bit sequence.

15. The method according to claim 13 or 14, characterized in that, The column pair with the maximum column weight in the core check region corresponds to Z in the LDPC check matrix c The column pair with the maximum column weight in the core check region corresponds to Z in the LDPC check matrix c Z is the lifting value of the LDPC base matrix, and N1 is less than or equal to Z c Z c is a positive integer.

16. The method according to any one of claims 13 to 15, characterized in that, N1 rows in core rows in the LDPC check matrix are truncated rows in rate matching, the N1 rows belong to the same row as a row with the largest column weight in a first matrix in a row to which the N1 rows belong in the LDPC base matrix, and the first matrix is a matrix composed of core rows of the LDPC base matrix and punctured columns in the rate matching.

17. The method according to any one of claims 13 to 15, characterized in that, N1 rows in core rows in the LDPC check matrix are truncated rows in rate matching, the N1 rows belong to the same row as at least one row with the same check relationship in a first matrix in a row to which the N1 rows belong in the LDPC base matrix, and the first matrix is a matrix composed of core rows of the LDPC base matrix and punctured columns in the rate matching.

18. The method of any one of claims 13-15, wherein, N1 rows in core rows in the LDPC check matrix are truncated rows in rate matching, and the N1 rows belong to rows with the largest column weight in a core check region of the LDPC base matrix.

19. The method of any one of claims 16-18, wherein, The relationship between the N1 rows and the N1 columns is: Ri = mod(Ci + Z c – S, Z c ); wherein i represents the ith column in the N1 columns and the ith row in the N1 rows, Ci represents the position of the ith column in the Z c columns, Ri represents the position of the ith row in the Z c rows, Z c represents the lifting value of the LDPC base matrix, S represents the shift value corresponding to the yth row and the xth column of the LDPC base matrix, the yth row is the row to which the N1 rows belong in the LDPC base matrix, the xth column is the column with the maximum column weight in the core check region, x and y are both integers greater than or equal to 0, i is an integer greater than or equal to 0 and less than N1, and Ci and Ri are both integers greater than or equal to 0 and less than Z c .

20. The method of any one of claims 16-19, wherein, The truncated rows are rows that are not checked in the LDPC check matrix.

21. The method according to any one of claims 13 to 20, characterized in that, The method further comprises: According to a target code rate, the truncated columns are determined from the core check columns, and the punctured columns in the rate matching are determined from the core check columns, the punctured columns do not overlap with the truncated columns, and the punctured columns are at least one column of the core check columns.

22. The method of any one of claims 13-20, wherein, The method comprises: According to a target code rate, the punctured columns in the rate matching are determined from the core check columns, and the truncated columns are determined from the core check columns, the punctured columns do not overlap with the truncated columns, and the punctured columns are at least one column of the core check columns.

23. The method of claim 21 or 22, wherein, The de-rate matching of the second received value sequence according to positions of the truncated columns in the rate matching comprises: The second received value sequence is subjected to de-rate matching according to positions of the truncated columns and positions of the punctured columns.

24. A communications device, characterized by The method comprises: The processing unit is configured to obtain a first codeword sequence, the first codeword sequence being obtained according to an LDPC check matrix, wherein N1 columns in a core check column in the LDPC check matrix are truncated columns in rate matching, the N1 columns belong to columns with the largest column weight in a core check region of an LDPC base matrix corresponding to the LDPC check matrix, and N1 is a positive integer. The processing unit is further configured to perform rate matching on the first codeword sequence.

25. A communications device, characterized by The processing unit comprises: The transceiving unit is configured to obtain a second received value sequence. The processing unit is configured to perform de-rate matching on the second received value sequence according to truncated columns in rate matching, wherein the truncated columns are N1 columns in a core check column in an LDPC check matrix, the N1 columns belong to columns with the largest column weight in a core check region of an LDPC base matrix corresponding to the LDPC check matrix, and N1 is a positive integer.

26. The apparatus of claim 24 or 25, wherein, The column pair with the maximum column weight in the core check region corresponds to Z in the LDPC check matrix c The column pair with the maximum column weight in the core check region corresponds to Z in the LDPC check matrix c Z is the lifting value of the LDPC base matrix, and N1 is less than or equal to Z c Z c is a positive integer.

27. The apparatus of any one of claims 24-26, wherein, N1 rows in a core row in the LDPC check matrix are truncated rows in the rate matching, the N1 rows belong to the same row as at least one row with the same check relationship in a first matrix, and the first matrix is a matrix composed of core rows of the LDPC base matrix and punctured columns in the rate matching.

28. The apparatus of any one of claims 24-26, wherein, N1 rows in a core row in the LDPC check matrix are truncated rows in the rate matching, the N1 rows belong to the same row as at least one row with the same check relationship in a first matrix, and the first matrix is a matrix composed of core rows of the LDPC base matrix and punctured columns in the rate matching.

29. The apparatus of any one of claims 24-26, wherein, N1 rows in a core row in the LDPC check matrix are truncated rows in the rate matching, the N1 rows belong to the same row as at least one row with the same check relationship in a first matrix, and the first matrix is a matrix composed of core rows of the LDPC base matrix and punctured columns in the rate matching.

30. The apparatus of any one of claims 27-29, wherein, The relationship between the N1 rows and the N1 columns is: Ri = mod(Ci + Z c – S, Z c ); wherein i represents the ith column in the N1 columns and the ith row in the N1 rows, Ci represents the position of the ith column in the Z c columns, Ri represents the position of the ith row in the Z c rows, Z c represents the lifting value of the LDPC base matrix, S represents the shift value corresponding to the yth row and the xth column of the LDPC base matrix, the yth row is the row to which the N1 rows belong in the LDPC base matrix, the xth column is the column with the maximum column weight in the core check region, x and y are both integers greater than or equal to 0, i is an integer greater than or equal to 0 and less than N1, and Ci and Ri are both integers greater than or equal to 0 and less than Z c .

31. The apparatus of any one of claims 27-30, wherein, The truncated rows are rows that are not checked in the LDPC check matrix.

32. The apparatus of any one of claims 27-31, wherein, The processing unit is specifically configured to: perform de-rate matching on the second received value sequence according to positions of the truncated columns and positions of the truncated rows.

33. The apparatus of any one of claims 24-32, wherein, The processing unit is further configured to: determine the truncated columns from the core check columns and determine punctured columns in the rate matching from the core check columns according to a target code rate, the punctured columns do not overlap with the truncated columns, and the punctured columns are at least one column of the core check columns.

34. The apparatus of any one of claims 24-32, wherein, The processing unit is further configured to: determine punctured columns in the rate matching from the core check columns and determine the truncated columns from the core check columns according to a target code rate, the punctured columns do not overlap with the truncated columns, and the punctured columns are at least one column of the core check columns.

35. The apparatus of claim 33 or 34, wherein, The processing unit is specifically configured to: perform de-rate matching on the second received value sequence according to positions of the truncated columns and positions of the punctured columns.

36. A communications device, characterized by The processing unit comprises: The processing unit is configured to encode an information bit sequence according to an LDPC check matrix to obtain a first codeword sequence, wherein N1 columns in a core check column in the LDPC check matrix are truncated columns in rate matching, the N1 columns belong to columns with the largest column weight in a core check region of an LDPC base matrix corresponding to the LDPC check matrix, and N1 is a positive integer. The processing unit is further configured to perform rate matching on the first codeword sequence to obtain a second codeword sequence. The transceiver is configured to output the second codeword sequence.

37. A communications device, characterized by The transceiver is configured to obtain a second received value sequence. The processing unit is configured to perform de-rate matching on the second received value sequence according to positions of truncated columns in the rate matching to obtain a first received value sequence, wherein the truncated columns are N1 columns in core check columns in an LDPC check matrix, and the N1 columns are columns with the largest column weight in a core check region of an LDPC base matrix corresponding to the LDPC check matrix, and N1 is a positive integer. The processing unit is further configured to decode the first received value sequence according to the LDPC check matrix to obtain a decoded information bit sequence. N1 rows in core rows in the LDPC check matrix are truncated rows in the rate matching, and the N1 rows are in the same row as rows with the largest row weight in a first matrix in the LDPC base matrix, and the first matrix is a matrix composed of core rows of the LDPC base matrix and punctured columns in the rate matching.

38. The apparatus of claim 36 or 37, wherein, The column pair with the maximum column weight in the core check region corresponds to Z in the LDPC check matrix c The column pair with the maximum column weight in the core check region corresponds to Z in the LDPC check matrix c Z is the lifting value of the LDPC base matrix, and N1 is less than or equal to Z c Z is the lifting value of the LDPC base matrix, and N1 is less than or equal to Z c Z is a positive integer.

39. The apparatus of any one of claims 36-38, wherein, N1 rows in core rows in the LDPC check matrix are truncated rows in the rate matching, and the N1 rows are in the same row as at least one row with the same check relationship in a first matrix in the LDPC base matrix, and the first matrix is a matrix composed of core rows of the LDPC base matrix and punctured columns in the rate matching.

40. The apparatus of any one of claims 36-38, wherein, N1 rows in core rows in the LDPC check matrix are truncated rows in the rate matching, and the N1 rows are rows with the largest column weight in a core check region of the LDPC base matrix.

41. The apparatus of any one of claims 36-38, wherein, The truncated rows are rows that are not checked in the LDPC check matrix.

42. The apparatus of any one of claims 39-41, wherein, The relationship between the N1 rows and the N1 columns is: Ri = mod(Ci + Z c – S, Z c ); wherein i represents the ith column in the N1 columns and the ith row in the N1 rows, Ci represents the position of the ith column in the Z c columns, Ri represents the position of the ith row in the Z c rows, Z c represents the lifting value of the LDPC base matrix, S represents the shift value corresponding to the yth row and the xth column of the LDPC base matrix, the yth row is the row to which the N1 rows belong in the LDPC base matrix, the xth column is the column with the maximum column weight in the core check region, x and y are both integers greater than or equal to 0, i is an integer greater than or equal to 0 and less than N1, and Ci and Ri are both integers greater than or equal to 0 and less than Z c .

43. The apparatus of any one of claims 39-42, wherein, The processing unit is further configured to:

44. The apparatus of any one of claims 36-43, wherein, determine the truncated columns from the core check columns and determine the punctured columns in the rate matching from the core check columns according to a target code rate, the punctured columns are not overlapped with the truncated columns, and the punctured columns are at least one column of the core check columns. The processing unit is further configured to:

45. The apparatus of any one of claims 36-43, wherein, determine the punctured columns in the rate matching from the core check columns and determine the truncated columns from the core check columns according to a target code rate, the punctured columns are not overlapped with the truncated columns, and the punctured columns are at least one column of the core check columns. The processing unit is specifically configured to:

46. The device of claim 44 or 45, wherein, perform de-rate matching on the second received value sequence according to positions of the truncated columns and positions of the punctured columns. The communication device includes at least one processor and interface circuitry, the interface circuitry is configured to receive signals from other communication devices outside the communication device and transmit the signals to the processor or send signals from the processor to other communication devices outside the communication device, and the processor is configured to implement the method in any one of claims 1 to 12 through logic circuitry or code instructions, or to implement the method in any one of claims 13 to 23.

47. A communications device, characterized by The communication device is a chip or a chip system.

48. The communication apparatus of claim 47, wherein ​ 49. A computer-readable storage medium, characterized in that, The storage medium has stored therein a computer program or instructions which, when executed, cause the method of any one of claims 1 to 12 to be implemented; or cause the method of any one of claims 13 to 23 to be implemented.

50. A computer program product, characterised in that, The computer program, when executed, causes the method of any one of claims 1 to 12 to be implemented; or causes the method of any one of claims 13 to 23 to be implemented.

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