Display device and electronic apparatus

Abstract

The present invention corrects the luminance in real time without a frame memory.　This display device comprises light-emitting elements, pixel circuits, a pixel array, a detection circuit, and an address generation circuit. The pixel circuit drives the light-emitting elements. In the pixel array, the light-emitting elements and the pixel circuits are arranged in a two-dimensional array. The detection circuit detects a current flowing through the light-emitting elements. The address generation circuit acquires, on the basis of the current detected by the detection circuit, a timing at which the light-emitting elements quench.

Description

Display devices and electronic devices

[0001] The present disclosure relates to a display device and an electronic device.

[0002] In display devices, IR drop occurs due to the resistance of the current path within the light-emitting pixel. This IR drop can cause a decrease in the brightness of the emitted light. The degree of brightness decrease varies depending on the amount of IR drop, but this IR drop varies depending on the total amount of current flowing through the current path, so there is a problem in that the amount of brightness decrease varies depending on the path.

[0003] For example, when Warp conversion or similar is applied to image or video information, the area in the display region where that image or video information is displayed changes. This change in display area significantly changes the current flowing through the pixels, which can change the amount of IR drop and potentially cause brightness flicker. Correcting the amount of brightness change requires detecting the display pattern, but adding a frame memory for this detection poses challenges such as an increase in panel size and power consumption.

[0004] Japanese Patent Application Laid-Open No. 2007-293264

[0005] Therefore, one non-limiting problem to be solved by the embodiments of the present disclosure is to realize real-time luminance correction without a frame memory. As some further non-limiting examples, the problem to be solved by the embodiments of the present disclosure may be a problem corresponding to the effects described in the embodiments. In other words, a problem corresponding to at least one of the effects described in the description of the embodiments of the present disclosure may be a problem to be solved by the present disclosure.

[0006] According to one embodiment, a display device includes a light-emitting element, a pixel circuit, a pixel array, a detection circuit, and an address generation circuit. The pixel circuit drives the light-emitting element. The pixel array has the light-emitting elements and the pixel circuits arranged in a two-dimensional array. The detection circuit detects a current flowing through the light-emitting element. The address generation circuit determines the timing at which the light-emitting element should turn off based on the current detected by the detection circuit.

[0007] The display device may further include a drive circuit that outputs a drive control signal for the light-emitting element to the pixel circuit, and outputs a signal that independently controls the light-emission timing and the extinction timing acquired by the address generation circuit.

[0008] The address generation circuit can perform control such that the greater the current value detected by the detection circuit, the earlier the extinction timing becomes.

[0009] The address generation circuit may obtain the extinction timing after the light emitting elements in the display area of ​​the pixel array emit light.

[0010] The drive circuit may output a control signal for turning off the light-emitting element at the light-off timing in a frame in which the address generation circuit acquires the light-off timing.

[0011] The address generation circuit may obtain the extinction timing by obtaining a difference between a current value of a previous frame and a current value of a current frame.

[0012] The address generation circuit may obtain the extinction timing by obtaining a difference between a predetermined current value and a current value of the current frame.

[0013] The address generation circuit may obtain the extinction timing after the light emitting elements in the entire display area of ​​the pixel array have emitted light.

[0014] The address generation circuit may divide a display area of ​​the pixel array and obtain the extinction timing for each divided area, and the drive circuit may control the extinction for each divided display area.

[0015] The light-emitting element may emit light of one of a plurality of colors, and the pixel array may display a mixture of the plurality of colors, the address generation circuit may obtain the extinction timing for each of the plurality of colors, and the drive circuit may control the timing of extinguishing the light-emitting element for each of the plurality of colors.

[0016] When the brightness control throughout a frame in the display area of ​​the pixel array is controlled by a duty ratio, the address generation circuit may obtain the extinction timing in each light emitting period in the frame.

[0017] The sensing circuit may sense current in a line belonging to a predetermined region of the pixel array.

[0018] When a display in a partial region of the pixel array is changed, the detection circuit may detect a current related to the display in a region other than the partial region.

[0019] The address generation circuit may include a shift register.

[0020] According to one embodiment, an electronic device includes a light-emitting element, a pixel circuit, a pixel array, a detection circuit, an address generation circuit, and a drive circuit. The pixel circuit drives the light-emitting element. The pixel array has the light-emitting elements and the pixel circuits arranged in a two-dimensional array. The detection circuit detects a current flowing through the light-emitting element. The address generation circuit obtains, as address information, a timing at which the light-emitting element will turn off based on the current detected by the detection circuit. The drive circuit outputs a signal that controls the drive of the light-emitting element in each of the pixel circuits.

[0021] The electronic device may further include an acceleration sensor; and an image processing circuit that generates warp-converted data of image data to be displayed when the display area of ​​the pixel array is tilted in the acceleration sensor, and the drive circuit may output a signal to drive the light-emitting element based on the output from the image processing circuit.

[0022] Furthermore, the light-emitting element, the pixel circuit, the pixel array, the detection circuit, the address generation circuit, the drive circuit, or the drive circuit may have any of the features of the display device described above.

[0023] 1 is a block diagram schematically showing an example of a display device according to an embodiment. A block diagram schematically showing an example of a display device according to an embodiment. A diagram showing an example of a display according to an embodiment. A diagram showing an example of a display according to an embodiment. A timing chart showing an example of the timing of light emission and extinction according to an embodiment. A timing chart showing an example of the timing of light emission and extinction according to an embodiment. A timing chart showing an example of the light emission intensity of a pixel according to an embodiment. A timing chart showing an example of the timing of light emission and extinction ... diagram showing an example of a pixel arrangement according to an embodiment. A diagram showing an example of an LDO according to an embodiment. A diagram showing an example of an LDO according to an embodiment. A circuit diagram showing an example of a pixel circuit according to an embodiment. A circuit diagram showing an example of a pixel circuit according to an embodiment. A circuit diagram showing an example of a pixel circuit according to an embodiment. A circuit diagram showing an example of a pixel circuit according to an embodiment. A circuit diagram showing an example of a pixel circuit according to an embodiment. 1 is a circuit diagram showing an example of a schematic of a pixel circuit according to an embodiment. FIG. 2 is an external view of an HMD which is a third application example of the electronic device. FIG. 3 is an external view of smart glasses. FIG. 4 is a front view of a digital camera which is a second application example of the electronic device. FIG. 5 is a rear view of a digital camera. FIG. 6 is an external view of a TV which is an application example of the electronic device. FIG. 7 is an external view of a smartphone which is an application example of the electronic device. FIG. 8 is a view showing the interior of a vehicle from the rear to the front of the vehicle. FIG. 9 is a view showing the interior of a vehicle from diagonally rear to diagonally front of the vehicle.

[0024] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. The drawings are used for explanation purposes, and the shape, size, and size ratio of each component in an actual device do not necessarily have to be the same as those shown in the drawings. Furthermore, since the drawings are simplified, components necessary for implementation other than those shown in the drawings are also assumed to be appropriately provided.

[0025] The present disclosure will be described in the following order: 1. Configuration example of a display device 2. Operation example of a display device 3. Configuration example of a detection circuit 4. Configuration example of a pixel circuit 5. Application example of a display device

[0026] <1. Example of display device configuration>

[0027] 1 is a block diagram showing a schematic example of the configuration of a display device according to one embodiment. The display device 1 includes, for example, a pixel array 10, a control circuit 11, a first drive circuit 12, a second drive circuit 13, a detection circuit 14, a comparison circuit 15, and an address generation circuit 16. The display device 1 is not limited to the above configuration, and may include other components necessary for the display device to function, such as a power supply circuit and an interface for acquiring information to be displayed.

[0028] It should be noted that the above configurations do not need to be configured as separate circuits, and circuits that perform multiple operations may execute the processing in each circuit as appropriate.

[0029] The display device 1 displays image information and video information (hereinafter referred to as image information, etc.) while suppressing fluctuations in brightness values ​​for each frame due to IR drop. For example, the display device 1 displays image information, etc. while suppressing flickering of overall brightness values ​​when Warp conversion, etc. is performed on the image information, etc.

[0030] The pixel array 10 is an area in which pixels 100 are arranged in a two-dimensional array along a first direction (e.g., a line direction) and a second direction (e.g., a column direction) intersecting the first direction. Each pixel 100 has a light-emitting element, and emits light with an appropriate brightness to form image information, etc.

[0031] The control circuit 11 is a circuit that transmits signals to the driver to control the brightness and timing of light emission of the pixels 100 in the pixel array 10. The control circuit 11 may also perform other controls to ensure that the display device 1 operates appropriately.

[0032] The first driving circuit 12 is a circuit (driver) that selects the pixels 100 arranged along the first direction in the pixel array 10 to be in a drivable state. A signal line 120 connects, for example, each of the pixels 100 belonging to the same line to the first driving circuit 12. Based on a signal input from the control circuit 11, the first driving circuit 12 selects a line via the signal line 120 and drives the light-emitting elements of the pixels belonging to this line.

[0033] The second drive circuit 13 is a circuit that outputs a signal to cause the light-emitting elements of the pixels 100 positioned along the second direction in the pixel array 10 and enabled by the first drive circuit 12 to emit light at an appropriate brightness. A signal line 130 connects, for example, each of the pixels 100 belonging to the same column to the second drive circuit 13. Based on a signal input from the control circuit 11, the second drive circuit 13 outputs a drive signal via the signal line 130 to the pixels 100 selected by the first drive circuit 12 and enabled to emit light at an appropriate brightness value.

[0034] Each pixel 100 emits light at an appropriate brightness (including the case where no light is emitted, i.e., the brightness is 0) based on a signal input from the first drive circuit 12 and a signal input from the second drive circuit 13. When the pixels 100 in the pixel array 10 emit light at an appropriate brightness, the display device 1 can display desired image information, etc.

[0035] The detection circuit 14 is a circuit that detects current. More specifically, the detection circuit 14 is a circuit that detects current flowing through the light-emitting element of the pixel 100 that belongs to the display area of ​​the pixel array 10. When an IR drop occurs in the pixel 100 in the display area, the detection circuit 14 is a circuit that detects current in order to obtain a current value that changes due to the occurrence of this IR drop.

[0036] The comparison circuit 15 is a circuit that compares the current value detected by the detection circuit 14 with a current value for correcting an image or the like, and outputs the result.

[0037] The address generation circuit 16 is a circuit that acquires the timing to extinguish the light-emitting elements of the pixels 100 that belong to the display area of ​​the pixel array 10, based on the comparison value of the current output by the comparison circuit 15. The address generation circuit 16 can output a signal that controls the extinguishing timing by generating address information that corresponds to the extinguishing timing.

[0038] The address generation circuit 16 outputs address information indicating this extinction timing to the control circuit 11. The control circuit 11 transmits the address information indicating the extinction timing to the first drive circuit 12 and the second drive circuit 13. The first drive circuit 12 and the second drive circuit 13 drive each pixel 100 based on the address information obtained from the control circuit 11, thereby extinguishing the pixel 100 at the appropriate timing.

[0039] That is, the first drive circuit 12 and the second drive circuit 13 cause the pixel 100 to emit light at an appropriate timing, for example, at a predetermined timing in a frame, and extinguish the pixel 100 at a required timing. In this way, the first drive circuit 12 and the second drive circuit 13 can drive the light emission and extinguishing independently.

[0040] The address generation circuit 16 may perform control such that the timing of extinction is brought forward as the current value detected by the detection circuit 14 is greater as a result of comparison by the comparison circuit 15. Since the display becomes brighter as the current value flowing through the light-emitting element of the pixel 100, i.e., the IR drop current, is greater, the brightness is stabilized by shortening the time until extinction as the detected current value is greater.

[0041] In this way, the address generation circuit 16 generates address information indicating the timing of extinction after the timing of emission of the pixel 100. Then, in the same frame in which the detection circuit 14 detects the current value, the address generation circuit 16 transmits the generated address information to the control circuit 11, and the control circuit 11 controls the extinction drive of the light-emitting element of the pixel 100 via the first drive circuit 12 and the second drive circuit 13 so that extinction control can be performed in real time.

[0042] The comparison circuit 15, for example, compares a predetermined current value with the current value detected by the detection circuit 14, and outputs the difference between these current values ​​to the address generation circuit 16. The address generation circuit 16 sets an address based on this difference in current values ​​so that the greater the current flowing through the light-emitting element in the pixel 100 detected by the detection circuit 14, the earlier the extinction timing, and outputs the address to the control circuit 11.

[0043] 2 is a block diagram schematically illustrating another example of the display device 1 according to an embodiment. The display device 1 may further include a memory 17. The memory 17 temporarily stores the current value acquired by the detection circuit 14. The memory 17 may have, for example, a configuration of a general memory circuit, or may use a short-term memory area such as a register.

[0044] The memory 17 temporarily stores the current value acquired by the detection circuit 14. In the next frame, the comparison circuit 15 compares the current value output by the light-emitting element of the pixel 100 in the current frame detected by the detection circuit 14 with the current value output by the light-emitting element of the pixel 100 in the previous frame stored in the memory 17. The address generation circuit 16 acquires the extinction timing using the comparison result of the comparison circuit 15. As described above, this extinction timing may be generated so that the higher the current value detected in the current frame, the earlier the timing.

[0045] In this way, as another embodiment, the display device 1 can also generate the extinction timing in the current frame based on the difference in current flowing through the light emitting element between the previous frame and the current frame.

[0046] As described above, according to this embodiment, it is possible to suppress flickering of images, etc. across the entire display area due to IR drop caused by the number of pixels 100 actually used for display in the display area of ​​the pixel array 10, i.e., the size of the area in which images, etc. are actually displayed.

[0047] For example, as shown in Figure 3, a case where an image or the like is displayed over the entire display area of ​​the pixel array 10 is taken as a reference. The shaded area represents an area in the pixel array 10 where no image or the like is displayed. With the above configuration, the display device 1 operates in such a way that flickering of the display due to changes in luminance value does not occur from the state where an image or the like is displayed over the entire area.

[0048] Figure 4 is a diagram showing an example in which the image displayed in Figure 3 has been transformed by Warp transformation or the like. When such a transformation is performed, the area in which the image transformed by Warp or the like is output becomes, for example, an area tilted with respect to the pixel array 10, and the area in which no luminance value data is set, i.e., the shaded area in which no display is performed, increases. As a result, a larger current flows in the area in which the image is actually displayed due to IR drop compared to the case of Figure 3, and the overall luminance of the image increases.

[0049] According to the display device 1, when the brightness value becomes high in this way, the extinction timing can be set earlier than the basic frame or the previous frame, thereby lowering the duty ratio of the area used for display, thereby lowering the apparent brightness value and suppressing flickering in the display area.

[0050] As will be described later, the above configuration can be used in electronic devices such as VR devices and AR devices. For example, a VR device can acquire the angle of the user's head using an acceleration sensor, an inertial sensor, etc., and deform the image displayed in accordance with the head angle. This deformation can be expressed by a Warp transformation that includes a simple rotation.

[0051] In such a conversion, the area in which an image or the like is displayed may increase or decrease as shown in Figures 3 and 4. Even in such a case, by controlling the duty ratio in the same frame from the current value output by the light-emitting element, it is possible to realize a display in which flickering of the overall brightness of the image or the like is suppressed.

[0052] As another configuration, the address generation circuit 16 can be replaced with a shift register. When using a shift register, the pulses of each line are managed by shifting the signal line by line in the shift register. The shift register can output the input signal with a delay time according to the number of bits that can be stored in the shift register.

[0053] The shift register, which may function as the address generation circuit 16, acquires the comparison value of the current output by the comparison circuit 15 as a pulse, shifts the acquired pulse at a timing according to the clock signal, and outputs it. The shift register stores, for example, data when the comparison circuit 15 detects an IR drop, such as the timing when the output of the comparison circuit 15 transitions from low to high, and outputs this timing after a predetermined delay.

[0054] For example, the control circuit 11 may control the light emission of the pixel 100 via the first drive circuit 12 and the second drive circuit 13 so that the light is extinguished based on the timing of a signal transition output from the shift register after controlling the light emission. Alternatively, when no signal transition is output from the shift register, the control circuit 11 may control the extinguishing of the pixel 100 at a set standard extinguishing timing.

[0055] In this way, a shift register can also be used as the address generating circuit 16.

[0056] <2. Example of display device operation>

[0057] The configuration of the display device 1 has been described above. Next, several examples of the operation of the display device 1 will be described.

[0058] (First embodiment)

[0059] 5 is a timing chart for one frame showing an example of the timing of light emission and extinction according to one embodiment. The time indicated by the diagonal lines indicates the period during which data is written to the pixel 100. The time indicated by the dashed lines indicates the period during which the light is emitted in the frame, which is the standard for not advancing the extinction timing.

[0060] In particular, the address generation circuit 16 may obtain the extinction timing after the light emitting elements of all the pixels 100 belonging to the entire display area of ​​the pixel array 10 have emitted light. Obtaining the extinction timing at this timing makes it possible to minimize the influence of IR drop that occurs due to the narrowing of the display area.

[0061] During the writing period, the second driving circuit 13 writes the intensity at which each pixel 100 emits light to the pixels 100. After this, the pixels 100 belonging to the pixel array 10 start emitting light when the light emission start address is reached.

[0062] After the pixel array 10 starts emitting light, the detection circuit 14 detects the currents flowing through the light-emitting elements of all lines of the pixels 100. The comparison circuit 15 compares the detected current values ​​with an appropriate value, for example, a predetermined current value or the current value of the previous frame in the above example, and outputs the result to the address generation circuit 16.

[0063] The address generation circuit 16 generates address information indicating the timing of extinction based on the output result from the comparison circuit 15. The address generation circuit 16 transmits the generated address information to the control circuit 11, which then controls the timing of extinction of the light-emitting element of the pixel 100 in the pixel array 10.

[0064] Under the control of the control circuit 11, for example, if the current value detected by the detection circuit 14 is greater than a predetermined value or the current value of the previous frame, the address indicating the extinction timing is set earlier than the address indicating the reference extinction timing, as shown in the figure, and the extinction timing is changed as shown by the arrow.

[0065] As a result, the light emission duty cycle can be reduced across the pixel array 10, making it possible to suppress flickering between the overall brightness of the reference frame and the brightness of the current frame. The display device 1 can perform processes from current detection by the detection circuit 14 to acquisition of the extinction address by the address generation circuit 16 within the same frame, making it possible to prevent display flickering caused by IR drop in real time.

[0066] (Second embodiment)

[0067] In the above-described embodiment, for example, a case where the display area itself changes due to a conversion such as Warp has been described, but the process from current detection to extinction timing control in the present disclosure can also be applied to other uses. In this embodiment, an example will be described in which the extinction timing is obtained from the current value in each cycle in a configuration in which brightness is controlled by the duty ratio.

[0068] In the following, as a variation, an example in which light is emitted from a line on which writing has been completed will be described, but this does not exclude an example in which all pixels emit light simultaneously after writing is completed, as in Figure 5. That is, the following example can also be applied to a case in which all pixels emit light simultaneously. Similarly, it is also possible to apply a form in which the timing of pixel emission is staggered, for example, an example in which several pixels emit light sequentially with a certain delay from pixels on which writing has been completed. Of course, the example in Figure 5 in which light is emitted from a line on which writing has been completed can also be applied.

[0069] 6 is a timing chart for one frame showing an example of the timing of light emission and extinction according to an embodiment. The above configuration of the present disclosure can be used to suppress a drop in luminance due to spontaneous discharge of written data within a frame.

[0070] In this embodiment, the display device 1 executes a process of setting a duty ratio so as to suppress the phenomenon in which the brightness of the data (brightness value) written to the pixel 100 decreases over time, and to bring the brightness closer to a constant value within the frame.

[0071] Hereinafter, one period within a frame driven with a duty ratio that starts with the emission of light on the first line after the completion of the writing period for each line will be referred to as a "subframe." In each subframe, an emission start address is set, and the pixel array 10 is controlled to emit light for each line according to this emission start address.

[0072] The detection circuit 14 detects the current to obtain the reference current value in the first subframe. In this embodiment, since the luminance values ​​of the pixels 100 belonging to the pixel array 10 do not change within a frame, it is not necessary to detect the current in all lines, and it is sufficient to detect the current in some of the lines.

[0073] In the first subframe, a reference extinction address is set, and the extinction drive control of the pixels 100 in each line is performed based on this reference extinction address. In the subsequent subframes, the extinction timing corresponding to this reference extinction address is also indicated by a dashed line.

[0074] After emitting light at a predetermined duty ratio, in the next subframe, the pixels 100 are similarly controlled to emit light by the control circuit 11. In the subframe, the detection circuit 14 similarly detects current from at least some of the lines.

[0075] The comparison circuit 15 compares the current value in the first subframe, which serves as a reference, with the current value in the subframe in question.

[0076] Based on the comparison result, the address generation circuit 16 obtains an address indicating the extinction timing for the subframe and notifies the control circuit 11. The control circuit 11 then performs drive control of the extinction timing of the pixel 100 based on this extinction address via the first drive circuit 12 and the second drive circuit 13.

[0077] The same applies to the subsequent subframes, and the extinction timing for each subframe is controlled based on the current value detected in the first subframe of the frame.

[0078] 7 is a timing chart showing an example of the emission intensity of a pixel 100 according to one embodiment. Data (emission intensity based on a brightness value) in the pixel circuit of the pixel 100 is generally stored in a capacitor. When writing such data, as shown in the data at the top, the value gradually decreases over time due to natural discharge of the capacitor.

[0079] By obtaining the extinction timing taking into consideration the extinction delay in each subframe due to the extinction timing in FIG. 6, it is possible to perform processing to stabilize the luminance by the duty ratio in each subframe.

[0080] The second row of Fig. 7 shows the timing of light emission and extinction of the pixels 100 in a certain line. As shown in this diagram, the extinction timing of each pixel 100 is set by the extinction address obtained based on the detected current value. The detection circuit 14 detects the current value flowing through the light-emitting element, which has decreased due to a decrease in voltage value caused by natural discharge, as shown in the first row.

[0081] The current value flowing through the light-emitting element in the first subframe of a frame is used as a reference, and the extinction timing is obtained from the difference between this and the current values ​​in subsequent subframes. The address generation circuit 16 calculates the extinction timing based on the current value detected by the detection circuit 14, for example, so that the time integral value of the luminance value in each subframe becomes a constant value (ideally) throughout the frame, and generates an extinction address.

[0082] The third row shows the change in light emission intensity over time in pixel 100, taking into account the written data. As shown in the third row, as the voltage stored in the capacitor as data decreases, the light emission period in each subframe becomes longer, and the apparent luminance value in each subframe becomes constant.

[0083] As described above, according to this embodiment, by using a configuration similar to that described above, it is possible to suppress flickering of brightness values ​​within a frame by controlling the light emission of light-emitting elements that are controlled by a duty ratio.

[0084] (Third embodiment)

[0085] The configuration of the present disclosure can also be used for other purposes. For example, even when partial lighting is used by dividing the display area, flickering can be prevented in each divided area by using the above configuration.

[0086] As an example, an example of partially writing only a part of an image in foveated rendering in a VR device will be described. Of course, this example can be applied not only to foveated rendering but also to partial updating of an image.

[0087] The detection circuit 14 detects the current for each divided area, and the address generation circuit 16 can obtain the extinction timing for each divided area of ​​the divided display area. Using the extinction address obtained by the address generation circuit 16, the control circuit 11 can drive and control the extinction timing for each area according to the extinction address.

[0088] 8 is a timing chart showing an example of the timing of light emission and extinction according to one embodiment. As shown in the frame on the left, the detection circuit 14 can detect current for each divided region. Note that although the diagram shows division along the line direction, this is for the sake of explanation; division along the column direction is also possible, or division in both the line and column directions is also possible.

[0089] For example, the current value detected in the left frame may be used as a reference current value for comparison with subsequent frames. Consider a case in which data is written to a certain area of ​​an image, etc., in the next frame, as shown in the figure. In this case, the detection circuit 14 detects the current in a divided area including this area, and the comparison circuit 15 compares the reference current value with the current value in the divided area, and the address generation circuit 16 obtains an extinction address based on the comparison result.

[0090] As shown in the figure, the address generation circuit 16 can generate an extinction address that advances the extinction timing due to the increase in the current value in the divided area where the new data is written, so as to suppress the variation in brightness values ​​within the frame.

[0091] 9 is a timing chart showing an example of the timing of light emission and extinction according to one embodiment. Unlike FIG. 8, the detection circuit 14 may detect the current value in an area that does not include a divided area in which new data has been written. In this case, the comparison circuit 15 obtains the current value of the current frame, which has a lower current value than the previous frame serving as a reference, and the address generation circuit 16 can generate an extinction address for the area in which new data has been written.

[0092] 8 and 9 may be combined. That is, the display device 1 may generate addresses by acquiring current values ​​in an area where new data is written and an area where new data is not written, and comparing the current values ​​with the current values ​​in the previous frame.

[0093] As another example, regardless of the previous frame, the display device 1 may be configured such that the address generation circuit 16 generates an extinction address based on the difference between the current value in an area in which new data has not been written within a frame and the current value in an area in which new data has been written, using the current value as a reference current value. According to this example, an extinction address can be generated for partial data writing within the same frame.

[0094] In each of the above examples, the timing of extinguishing a partially written area is advanced, but in this process, for example, the luminance value of a divided area with a high frame rate is reduced based on the luminance of the entire display area with a low frame rate. While this process makes it possible to reduce power consumption, there is a possibility that flicker may be perceived when data is written to the display area with a low frame rate.

[0095] To solve this problem, instead of lowering the brightness value of the partial area where data has been written, a process of raising the brightness value of other areas may be performed.

[0096] 10 is a timing chart showing an example of the timing of light emission and extinction according to an embodiment. The detection circuit 14 detects the current at the timing when data is written to the previous display area as a reference current.

[0097] When partial writing is performed in the next frame, the detection circuit 14 detects the current in each of the areas other than the written area, and may also detect the current in the area including the written area.

[0098] The comparator circuit 15 compares the current value acquired in each divided region with a reference current value, and the address generator circuit 16 generates an extinction address for each divided region based on the comparison result. As a result, as shown in the right frame, it is possible to generate an extinction address that delays the extinction timing in regions other than the region where data has been written.

[0099] As in the case of FIG. 6, in areas other than the area where data has been written, the voltage value indicating the data decreases over time, but this decrease can also be considered to be the same across the entire display area.

[0100] 11 is a timing chart showing an example of the timing of light emission and extinction according to one embodiment. As shown in the previous paragraph, when data is written in a certain area, the decrease in the signal value indicating the luminance value in the other area can be assumed to be at approximately the same rate.

[0101] Therefore, as shown in FIG. 11, the display device 1 may detect the current in a part of the area where no data has been written, and compare this current with, for example, a predetermined current value or the current value of the previous frame to generate an extinction address indicating the timing of extinction.

[0102] As described above, when the display area of ​​an image or the like is divided, various processes can be realized for each divided area.

[0103] (Fourth embodiment)

[0104] In each of the above-described embodiments, particularly in the case where light is emitted as soon as writing is completed for each line, there may not be a sufficient period during which all lines emit light simultaneously. In such cases, as shown in this embodiment, the extinction addresses may be generated sequentially for each divided line.

[0105] 12 is a timing chart showing an example of the timing of light emission and extinction according to one embodiment. As shown in this figure, current detection may be performed for each divided region. The divided regions are respectively designated (1), (2), (3), (4), .... Each region may include overlapping regions.

[0106] The extinction address can be generated using the current value detected in each divided region. As shown on the right, in region (1), the extinction address is generated using the current value detected in region (1).

[0107] In the overlapping region of (2) and (3), the current values ​​of (1) and (2) that can be detected before the current detection timing of (3) are used to generate the extinction address by taking the current value of (2) minus the current value of (1).

[0108] In the overlapping region of (3) and (4), the current values ​​of (1) to (3) that can be detected before the current detection timing of (4) are used to generate the extinction address by using the current value of (3) - (current value of (2) - current value of (1)).

[0109] In this way, the current value already detected may be used to sequentially generate an extinction address taking into account the overlapping region.

[0110] As described above, according to this embodiment, in cases where it is difficult to detect the current in the entire display area, or where detecting the current in the entire display area makes it difficult to obtain the extinction timing, the extinction timing for each divided area can be appropriately controlled by detecting the current for each divided area.

[0111] (Fifth embodiment)

[0112] Although the above description has focused on brightness, the display device 1 generally emits light of three colors, for example, RGB, in the pixel array 10 and displays images etc. by additive color mixing of these colors. The following describes the case where the three colors of RGB are used.

[0113] Note that RGB is given as a non-limiting example and does not exclude other additive colors. For example, other colors such as white, magenta, yellow, cyan, and emerald may be included. Also, although the color arrangement is assumed to be a Bayer array, this arrangement is not limited to this arrangement either.

[0114] 13 is a diagram showing the arrangement of pixels 100 in a portion of a pixel array 10 according to one embodiment, and the relationship with power supply voltage lines that supply power. In this diagram, signal lines other than the power supply lines are omitted, but the pixels 100 are properly connected to the first drive circuit 12, the second drive circuit 13, etc.

[0115] The pixels 100 emit light of the colors R, G, and B, respectively. These colors can be emitted by, for example, a light-emitting diode (LED) equipped with a color filter, an organic photoelectric conversion film, or the like. By emitting light of the three colors at each pixel, it is possible to display a mixed color.

[0116] In one embodiment, current sensing, comparison, and generation of extinction addresses are performed for each pixel 100 of each color, and drive control is performed according to the extinction timing for each color.

[0117] An LDO (Low Drop Out) may be provided as at least one of the positive power supplies of each pixel 100. The configuration of the LDO will be described in detail in the embodiments described later. In the present disclosure, for example, an LDO is provided for each color, and the LDO corresponding to each color supplies power to the pixels 100 that emit light of that color.

[0118] The pixel 100 that emits R is applied with a positive voltage Vccpr from the R LDO 20R via the power supply line VDDPR. The pixel 100 that emits G is applied with a positive voltage Vccpg from the G LDO 20G via the power supply line VDDPG. The pixel 100 that emits B is applied with a positive voltage Vccpb from the B LDO 20B via the power supply line VDDPB.

[0119] Each pixel 100 may be connected to a ground potential line VSS as a negative power supply for the light emitting element, and the negative potential may be set to voltage Vss.

[0120] This configuration is for a configuration in which a detection circuit 14 is provided within an LDO. In this configuration, the detection circuit 14 provided in each LDO performs AD conversion on a current that mirrors the load current, outputs the current, and inputs it to a comparison circuit 15 corresponding to each color. The comparison circuit 15 corresponding to each color outputs the comparison result to an address generation circuit 16 corresponding to each color, and the address generation circuit 16 corresponding to each color generates an extinction address corresponding to each color.

[0121] It is not essential that the comparator circuit 15 and the address generator circuit 16 are provided for each color. For example, the comparator circuit 15 and the address generator circuit 16 may compare the detected currents output from the respective LDOs and generate quench addresses at different timings.

[0122] Based on the generated extinction addresses, the control circuit 11 controls the appropriate extinction timing for each of the pixels 100. As can be understood from the above, in the pixel array 10, it is also possible to output drive signals to the pixels 100 corresponding to each color from the first drive circuit 12 and the second drive circuit 13 using signal lines 120 and 130 corresponding to each color.

[0123] It is desirable that the first drive circuit 12 at least have signal lines 120 corresponding to the respective colors in order to control driving corresponding to the respective colors. That is, the signal line 120 for R light emission / extinction control from the first drive circuit 12 is connected to the pixels 100 that emit R light and belong to the same line, the signal line 120 for G light emission / extinction control from the first drive circuit 12 is connected to the pixels 100 that emit G light and belong to the same line, and the signal line 120 for B light emission / extinction control from the first drive circuit 12 is connected to the pixels 100 that emit B light and belong to the same line.

[0124] When forming an image or the like to be displayed using additive color mixing according to the above, it is desirable to minimize the deviation of additive color mixing. The deviation of additive color mixing can be expressed as follows, for example, using the maximum value of white (white raster) in a frame (or a subframe in the above-described embodiment) and the maximum value of the luminance of each color: The address generation circuit 16 may calculate the maximum value of the monochromatic luminance of each color from the extinction address, and use that value to calculate the extinction address so that the additive color mixture deviation approaches 0. By performing this processing, it is possible to achieve more faithful color reproduction of images, etc.

[0125] As described above, according to this embodiment, by calculating the extinction address for each color, it is possible to reproduce colors more faithfully and suppress flickering in the display.

[0126] <3. Example of detection circuit configuration>

[0127] Next, several configuration examples of the detection circuit will be described. The detection circuit 14 is a circuit that acquires the value of a current flowing through a light-emitting element. The detection circuit 14 acquires the value of a current flowing through a light-emitting element, for example, the anode or cathode of an LED. The detection circuit 14 may detect the total current value of pixels across the entire display area, or may detect the total current value of monitor pixels that have been thinned out across the entire display area. The detection circuit 14 may detect the current flowing through the light-emitting element during the period when the light-emitting element is emitting light.

[0128] Simply put, the detection circuit 14 may be configured as a current mirror connected to the anode of the light-emitting element in the pixel circuit of the pixel 100. Alternatively, the detection circuit 14 may be configured as a current mirror connected to the cathode of the light-emitting element in the pixel circuit of the pixel 100. Alternatively, the detection circuit 14 may be configured as a current mirror connected to the node between the anode or cathode of the light-emitting element and the initialization transistor of the light-emitting element in the pixel circuit of the pixel 100.

[0129] When configured as a current mirror for the current at a predetermined position within the pixel circuit, the detection circuit 14 can obtain the current obtained by combining these outputs across the entire display area, or by combining these outputs across each divided area of ​​the display area, thereby obtaining the current value across the entire display area or each divided area.

[0130] (Sixth embodiment)

[0131] As yet another alternative, the detection circuit 14 may be provided in a power supply circuit, more specifically, an LDO circuit, that uses the pixel circuit of the pixel 100 as a load. In this embodiment, a case where the detection circuit 14 is provided in this LDO will be described.

[0132] FIG. 14 is a circuit diagram showing an example of an LDO configuration according to an embodiment. The detection circuit 14 may be a circuit included in an LDO power supply. The LDO 20, for example, is configured by adding a current mirror that mirrors the drain current of the output transistor to a typical LDO configuration. The output of this current mirror is output to a comparison circuit 15 via an AD converter.

[0133] VCCP is a signal line that supplies power to the pixels 100. The LDO 20 is connected to the pixels 100 that belong to the entire display area or to each divided area of ​​the display area via VCCP as a load. As a result, a load current flows from the signal line VCCP to the LDO 20, with the pixels 100 acting as a load. This load current is mainly a current that flows between the anode and cathode of the light-emitting element. Therefore, by monitoring this load current, it is possible to detect an increase or decrease in current due to IR drop.

[0134] The detection circuit 14 detects this load current using a current mirror. As in the above-described embodiments, the current detected by the detection circuit 14 is output to the comparison circuit 15, and the extinction timing is generated in the address generation circuit 16.

[0135] 15 is a diagram showing another example of an LDO according to an embodiment. As shown in this diagram, the current value may be acquired from either the drain side or the source side of the transistors that make up the current mirror.

[0136] Although the transistors in the LDO are shown as p-type MOSFETs in the drawings, they are not limited to this and may be n-type MOSFETs.

[0137] In the case of the fifth embodiment described above, an LDO 20 may be provided for each color. By providing an LDO for each color, it becomes possible to detect the current flowing through the light-emitting element of the pixel 100 as the load current in the entire display area or a part of the display area for each color.

[0138] As described above, the detection circuit 14 in the present disclosure may be configured to be provided inside an LDO power supply. By providing the detection circuit 14 inside an LDO circuit, the detection circuit 14 can detect the current flowing through the light-emitting element of the pixel 100 as the load current.

[0139] By detecting the current on the anode side, cathode side, or initialization transistor side of the light-emitting element using the configuration according to this embodiment, it is possible to control the timing of extinction in real time within a frame or subframe.

[0140] <4. Example of pixel circuit configuration>

[0141] In the following, the expressions "first voltage" and "second voltage" are used, but when the expressions "first voltage" and "second voltage" are used in the above-mentioned embodiments, etc., they are not necessarily limited to being the same voltage. Note that in the following, pixel 100 is referred to as pixel PIX.

[0142] (Seventh embodiment)

[0143] 16 shows an example of the configuration of a pixel PIX. The pixel PIX has a capacitor C01, transistors MN02 and MN03, and a light-emitting element EL. The transistors MN02 and MN03 are, for example, N-type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors).

[0144] The transistor MN02 has a gate connected to the control line WSL, the other of the source or drain connected to the signal line SGL, and one of the source or drain connected to the gate of the transistor MN03 and one end of the capacitor C01.

[0145] One end of the capacitor C01 is connected to one of the source / drain of the transistor MN02 and the gate of the transistor MN03, and the other end is connected to one of the source / drain of the transistor MN03 and the anode of the light-emitting element EL.

[0146] The transistor MN03 has a gate connected to one of the source / drain of the transistor MN02 and one end of the capacitor C01, the other of the source / drain connected to the power supply line VCCP, and one of the source / drain connected to the other end of the capacitor C01 and the anode of the light-emitting element EL.

[0147] The light-emitting element EL has an anode connected to one of the source and drain of the transistor MN03 and the other end of the capacitor C01, and a cathode connected to the power supply line Vcath.

[0148] The voltage of the power supply line VCCP is switched appropriately between a first voltage and a second voltage lower than the first voltage.

[0149] With this configuration, in pixel PIX, when transistor MN02 is turned on, the voltage across capacitor C01 is set based on the pixel signal supplied from signal line SGL. While the voltage of power supply line VCCP is at the first voltage, transistor MN03 passes a current corresponding to the voltage across capacitor C01 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor MN03.

[0150] In this way, the pixel PIX emits light at a luminance corresponding to the pixel signal. Note that, during the period in which the voltage of the power supply line VCCP is the second voltage, the light-emitting element EL is extinguished.

[0151] As described above, the detection circuit 14 may be incorporated into an LDO circuit connected to the power supply line VCCP, or may be connected to the anode or cathode of the light-emitting element EL to detect current.

[0152] (Eighth embodiment)

[0153] 17 shows another example of the configuration of pixel PIX. This pixel PIX has capacitors C11 and C12, transistors MP12 to MP15, and a light-emitting element EL. Transistors MP12 to MP15 are, for example, P-type MOSFETs.

[0154] The transistor MP12 has a gate connected to the control line WSL, one of the source / drain connected to the signal line SGL, and the other of the source / drain connected to the gate of the transistor MP14 and the other end of the capacitor C12.

[0155] One end of the capacitor C11 is connected to the power supply line VCCP, and the other end is connected to one end of the capacitor C12, the other of the source / drain of the transistor MP13, and one of the source / drain of the transistor MP14.

[0156] One end of the capacitor C12 is connected to the other end of the capacitor C11, the other of the source / drain of the transistor MP13, and one of the source / drain of the transistor MP14, and the other end is connected to the other of the source / drain of the transistor MP12 and the gate of the transistor MP14.

[0157] The transistor MP13 has a gate connected to the control line DSL, one of the source / drain connected to the power supply line VCCP, and the other of the source / drain connected to one of the source / drain of the transistor MP14, the other end of the capacitor C11, and one end of the capacitor C12.

[0158] The gate of transistor MP14 is connected to the other of the source and drain of transistor MP12 and the other end of capacitor C12, one of the source and drain is connected to the other of the source and drain of transistor MP13, the other end of capacitor C11, and one end of capacitor C12, and the other of the source and drain is connected to the anode of light-emitting element EL and one of the source and drain of transistor MP15.

[0159] The transistor MP15 has a gate connected to the control line AZSL, one of the source / drain connected to the other of the source / drain of the transistor MP14 and the anode of the light-emitting element EL, and the other of the source / drain connected to the power supply line VSS.

[0160] With this configuration, in pixel PIX, when transistor MP12 is turned on, the voltage across capacitor C12 is set based on the pixel signal supplied from signal line SGL. Transistor MP13 turns on / off based on the signal on control line DSL. While transistor MP13 is on, transistor MP14 passes a current corresponding to the voltage across capacitor C12 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor MP14.

[0161] In this way, the pixel PIX emits light with a luminance according to the pixel signal.

[0162] The transistor MP15 is turned on / off based on a signal on the control line AZSL. While the transistor MP15 is in the on state, the light-emitting element EL is initialized by setting the anode voltage to the voltage of the power supply line VSS.

[0163] The transistors MP12 to MP15 may be transistors using low temperature polysilicon (LTPS), and at least one of the transistors MP12 and MP15 may be a transistor using an oxide semiconductor.

[0164] As described above, the detection circuit 14 may be incorporated into an LDO circuit connected to the power supply line VCCP, or may be connected to the anode or cathode of the light-emitting element EL or the ground side of the transistor MP15 to detect current.

[0165] (Ninth embodiment)

[0166] 18 shows another example of the configuration of the pixel PIX. This pixel PIX has a capacitor C21, transistors MN22 to MN25, and a light-emitting element EL. The transistors MN22 to MN25 are, for example, N-type MOSFETs.

[0167] The transistor MN22 has a gate connected to the control line WSL, the other of the source or drain connected to the signal line SGL, and one of the source or drain connected to the gate of the transistor MN24 and one end of the capacitor C21.

[0168] One end of capacitor C21 is connected to one of the source / drain of transistor MN22 and the gate of transistor MN24, and the other end is connected to one of the source / drain of transistor MN24, the other of the source / drain of transistor MN25, and the anode of light-emitting element EL.

[0169] The transistor MN23 has a gate connected to the control line DSL, the other of the source / drain connected to the power supply line VCCP, and one of the source / drain connected to the other of the source / drain of the transistor MN24.

[0170] The gate of transistor MN24 is connected to one of the source / drain of transistor MN22 and one end of capacitor C21, the other of the source / drain is connected to one of the source / drain of transistor MN23, and one of the source / drain is connected to the other end of capacitor C21, the other of the source / drain of transistor MN25, and the anode of light-emitting element EL.

[0171] The gate of transistor MN25 is connected to control line AZSL, the other of the source / drain is connected to one of the source / drain of transistor MN24, the other end of capacitor C21, and the anode of light-emitting element EL, and one of the source / drain is connected to power supply line VSS.

[0172] With this configuration, in pixel PIX, when transistor MN22 is turned on, the voltage across capacitor C21 is set based on the pixel signal supplied from signal line SGL. Transistor MN23 turns on / off based on the signal on control line DSL. While transistor MN23 is on, transistor MN24 passes a current corresponding to the voltage across capacitor C21 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor MN24.

[0173] In this way, the pixel PIX emits light with a luminance according to the pixel signal.

[0174] The transistor MN25 is turned on / off based on the signal on the control line AZSL. While the transistor MN25 is in the on state, the light-emitting element EL is initialized by setting the anode voltage to the voltage of the power supply line VSS.

[0175] Note that the transistors MN22 to MN25 may be transistors using low temperature polysilicon (LTPS), and at least one of the transistors MN22 and MN25 may be a transistor using an oxide semiconductor.

[0176] As described above, the detection circuit 14 may be incorporated into an LDO circuit connected to the power supply line VCCP, or may be connected to the anode or cathode of the light-emitting element EL or the ground side of the transistor MP25 to detect current.

[0177] (Tenth embodiment)

[0178] 19 shows another example of the configuration of pixel PIX. This pixel PIX has a capacitor C31, transistors MP32 to MP36, and a light-emitting element EL. The transistors MP32 to MP36 are, for example, P-type MOSFETs.

[0179] The transistor MP32 has a gate connected to the control line WSL, one of the source and drain connected to the signal line SGL, and the other of the source and drain connected to the gate of the transistor MP33, the other of the source and drain of the transistor MP34, and the other end of the capacitor C31.

[0180] The capacitor C31 has one end connected to the power supply line VCCP, and the other end connected to the other of the source and drain of the transistor MP32, the gate of the transistor MP33, and the other of the source and drain of the transistor MP34.

[0181] The gate of transistor MP34 is connected to control line AZSL1, one of the source / drain is connected to the other of the source / drain of transistor MP33 and one of the source / drain of transistor MP35, and the other of the source / drain is connected to the other of the source / drain of transistor MP32, the gate of transistor MP33, and the other end of capacitor C31.

[0182] The transistor MP35 has a gate connected to the control line DSL, one of its source / drain connected to the other of the source / drain of the transistor MP33 and one of the source / drain of the transistor MP34, and the other of its source / drain connected to one of the source / drain of the transistor MP36 and the anode of the light-emitting element EL.

[0183] The transistor MP36 has a gate connected to the control line AZSL2, one of the source / drain connected to the other of the source / drain of the transistor MP35 and the anode of the light-emitting element EL, and the other of the source / drain connected to the power supply line VSS.

[0184] With this configuration, in pixel PIX, when transistor MP32 is turned on, the voltage across capacitor C31 is set based on the pixel signal supplied from signal line SGL. Transistor MP35 turns on / off based on the signal on control line DSL. While transistor MP35 is on, transistor MP33 passes a current corresponding to the voltage across capacitor C31 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor MP33.

[0185] In this way, the pixel PIX emits light with a luminance according to the pixel signal.

[0186] The transistor MP34 is turned on / off based on a signal on the control line AZSL1. While the transistor MP34 is in the on state, the other of the source and drain of the transistor MP33 and the gate are connected to each other.

[0187] The transistor MP36 is turned on / off based on the signal on the control line AZSL2. During the period when the transistor MP36 is in the on state, the anode voltage of the light-emitting element EL is initialized by being set to the voltage of the power supply line VSS.

[0188] Note that the transistors MP32 to MP36 may be transistors using low temperature polysilicon (LTPS), and at least one of the transistors MP32, MP34, and MP36 may be a transistor using an oxide semiconductor.

[0189] As described above, the detection circuit 14 may be incorporated into an LDO circuit connected to the power supply line VCCP, or may be connected to the anode or cathode of the light-emitting element EL or the ground side of the transistor MP36 to detect current.

[0190] (Eleventh embodiment)

[0191] FIG. 20 shows another example of the configuration of the pixel PIX.

[0192] The capacitor C48 has one end connected to the signal line SGL1 and the other end connected to the power supply line VSS.

[0193] The capacitor C49 has one end connected to the signal line SGL1 and the other end connected to the signal line SGL2.

[0194] The transistor MP49 is, for example, a P-type MOSFET, with its gate connected to the control line WSL2, one of its source / drain connected to the signal line SGL1, and the other of its source / drain connected to the signal line SGL2.

[0195] The pixel PIX includes a capacitor C41, transistors MP42 to MP46, and a light-emitting element EL. The transistors MP42 to MP46 are, for example, P-type MOSFETs.

[0196] The transistor MP42 has a gate connected to the control line WSL1, one of the source / drain connected to the signal line SGL2, and the other of the source / drain connected to the gate of the transistor MP43 and the other end of the capacitor C41.

[0197] The capacitor C41 has one end connected to the power supply line VCCP and the other end connected to the other of the source and drain of the transistor MP42 and the gate of the transistor MP43.

[0198] The gate of transistor MP43 is connected to the other of the source / drain of transistor MP42 and the other end of capacitor C41, one of the source / drain is connected to the power supply line VCCP, and the other of the source / drain is connected to one of the source / drain of transistors MP44 and MP45.

[0199] The transistor MP44 has a gate connected to the control line AZSL1, one of its source / drain connected to the other of the source / drain of the transistor MP43 and one of the source / drain of the transistor MP45, and the other of its source / drain connected to the signal line SGL2.

[0200] The transistor MP45 has a gate connected to the control line DSL, one of its source / drain connected to the other of the source / drain of the transistor MP43 and one of the source / drain of the transistor MP44, and the other of its source / drain connected to one of the source / drain of the transistor MP46 and the anode of the light-emitting element EL.

[0201] The transistor MP46 has a gate connected to the control line AZSL2, one of the source / drain connected to the other of the source / drain of the transistor MP45 and the anode of the light-emitting element EL, and the other of the source / drain connected to the power supply line VSS.

[0202] With this configuration, in pixel PIX, when transistor MP42 is turned on, the voltage across capacitor C41 is set based on the pixel signal supplied from signal line SGL1 via capacitor C49. Transistor MP45 turns on / off based on the signal on control line DSL. While transistor MP45 is on, transistor MP43 passes a current corresponding to the voltage across capacitor C41 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor MP43.

[0203] In this way, the pixel PIX emits light with a luminance according to the pixel signal.

[0204] The transistor MP44 is turned on / off based on the signal on the control line AZSL1. While the transistor MP44 is in the on state, the other of the source and drain of the transistor MP43 and the signal line SGL2 are connected to each other.

[0205] The transistor MP46 is turned on / off based on a signal on the control line AZSL2. During the period when the transistor MP46 is in the on state, the light-emitting element EL is initialized by setting the anode voltage to the voltage of the power supply line VSS.

[0206] Note that the transistors MP42 to MP46 and MP49 may be transistors using low temperature polysilicon (LTPS), and at least one of the transistors MP42, MP46 and MP49 may be a transistor using an oxide semiconductor.

[0207] As described above, the detection circuit 14 may be incorporated into an LDO circuit connected to the power supply line VCCP, or may be connected to the anode or cathode of the light-emitting element EL or the ground side of the transistor MP46 to detect current.

[0208] (Twelfth embodiment)

[0209] 21 shows another example of the configuration of the pixel PIX. A plurality of pixels PIX are arranged in a matrix in a display area 1000, and the display area 1000 is arranged between a first control unit 40 and a second control unit 70.

[0210] The first control unit 40 has transmission gates TG45 and TG46, transistors MP56 and MP57, and a capacitor C61. The transistors MP56 and MP57 are, for example, P-type MOSFETs.

[0211] The transmission gate TG45 has one end to which a pixel signal is supplied and the other end connected to one end of the signal line 14a.

[0212] The transmission gate TG46 has one end connected to the signal line 14b and the other end connected to the power supply line Vorst.

[0213] The capacitor C61 has one end connected to the signal line 14a and the other end connected to the power supply line VSS1.

[0214] The transistor MP56 has a gate connected to the control line INIL, one of the source / drain connected to the power supply line Vini, and the other of the source / drain connected to the signal line 14b.

[0215] The transistor MP57 has a gate connected to the control line ELL, one of the source / drain connected to the power supply line Vel, and the other of the source / drain connected to the signal line 14b.

[0216] The second control unit 70 includes a transmission gate TG72, a transistor MP73, and a capacitor C82. The transistor MP73 is, for example, a P-type MOSFET.

[0217] The transmission gate TG72 has one end connected to the signal line 14a and the other end connected to the other of the source and drain of the transistor MP73 and one end of the capacitor C82.

[0218] The transistor MP73 has a gate connected to the control line REFL, one of the source / drain connected to the power supply line Vref, and the other of the source / drain connected to the other end of the transmission gate TG72 and one end of the capacitor C82.

[0219] The capacitor C82 has one end connected to the other end of the transmission gate TG72 and the other of the source and drain of the transistor MP73, and the other end connected to one end of the signal line 14b.

[0220] The pixel PIX has a capacitor C132, transistors MP121 to MP125, and a light-emitting element EL. The transistors MP121 to MP125 are, for example, P-type MOSFETs.

[0221] The transistor MP122 has a gate connected to the control line WSL, one of the source / drain connected to the signal line 14b, and the other of the source / drain connected to the gate of the transistor MP121 and the other end of the capacitor C132.

[0222] The capacitor C132 has one end connected to the power supply line Vel and the other end connected to the other of the source and drain of the transistor MP122 and the gate of the transistor MP121.

[0223] The gate of transistor MP121 is connected to the other of the source and drain of transistor MP122 and the other end of capacitor C132, one of the source and drain is connected to the power supply line Vel, and the other of the source and drain is connected to one of the source and drain of transistors MP123 and MP124.

[0224] The transistor MP123 has a gate connected to the control line AZSL, one of its source / drain connected to the other of the source / drain of the transistor MP121 and one of the source / drain of the transistor MP124, and the other of its source / drain connected to the signal line 14b.

[0225] The transistor MP124 has a gate connected to the control line DSL, one of its source / drain connected to the other of the source / drain of the transistor MP121 and one of the source / drain of the transistor MP123, and the other of its source / drain connected to the other of the source / drain of the transistor MP125 and the anode of the light-emitting element EL.

[0226] The transistor MP125 has a gate connected to the control line AZSL, one of the source / drain connected to the power supply line Vorst, and the other of the source / drain connected to the other of the source / drain of the transistor MP124 and the anode of the light-emitting element EL.

[0227] With this configuration, in pixel PIX, when transistor MP122 is turned on, the voltage across capacitor C132 is set based on the pixel signal supplied via transmission gate TG45, signal line 14a, transmission gate TG72, capacitor C82, and signal line 14b. Transistor MP124 turns on / off based on the signal on control line DSL. While transistor MP124 is on, transistor MP121 passes a current corresponding to the voltage across capacitor C132 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor MP121.

[0228] In this way, the pixel PIX emits light with a luminance according to the pixel signal.

[0229] The transistors MP123 and MP125 are turned on / off based on a signal on the control line AZSL. While the transistor MP123 is on, the other of the source and drain of the transistor MP121 and one of the source and drain of the transistor MP124 are connected to the signal line 14b. While the transistor MP125 is on, the light-emitting element EL is initialized by setting the anode voltage to the voltage on the power supply line Vorst.

[0230] Furthermore, transistor MP56 turns on / off based on the signal on control line INIL, transistor MP57 turns on / off based on the signal on control line ELL, and transistor MP73 turns on / off based on the signal on control line REFL. When transistor MP56 is turned on, signal line 14b is set to the voltage of power supply line Vini, and when transistor MP57 is turned on, signal line 14b is set to the voltage of power supply line Vel. When transistor MP73 is turned on, one end of capacitor C82 is initialized by being set to the voltage of power supply line Vref.

[0231] The transistors MP121 to MP125, MP56, and MP57 may be transistors using low temperature polysilicon (LTPS), and at least one of the transistors MP122 and MP125 may be a transistor using an oxide semiconductor.

[0232] As described above, the detection circuit 14 may be incorporated into an LDO circuit connected to the power supply line VCCP, or may be connected to the anode or cathode of the light-emitting element EL to detect current.

[0233] (Thirteenth embodiment)

[0234] 22 shows another example of the configuration of pixel PIX. This pixel PIX has a capacitor C51, transistors MP52 to MP60, and a light-emitting element EL. The transistors MP52 to MP60 are, for example, P-type MOSFETs.

[0235] The transistor MP52 has a gate connected to the control line WSL, one of the source / drain connected to the signal line SGL, and the other of the source / drain connected to the other of the source / drain of the transistor MP53 and one of the source / drain of the transistor MP54.

[0236] The transistor MP53 has a gate connected to the control line DSL, one of the source / drain connected to the power supply line VCCP, and the other of the source / drain connected to the other of the source / drain of the transistor MP52 and one of the source / drain of the transistor MP54.

[0237] The gate of transistor MP54 is connected to one of the sources or drains of transistor MP55, the other of the sources or drains of transistor MP57, and the other end of capacitor C51, one of the sources or drains is connected to the other of the sources or drains of transistors MP52 and MP53, and the other of the source or drain is connected to one of the sources or drains of transistors MP58 and MP59.

[0238] Capacitor C51 has one end connected to the power supply line VCCP and the other end connected to the gate of transistor MP54, one of the source / drain of transistor MP55, and the other of the source / drain of transistor MP57. Capacitor C51 may include two capacitors connected in parallel.

[0239] The gate of transistor MP55 is connected to control line AZSL1, one of the source / drain is connected to the gate of transistor MP54, the other of the source / drain of transistor MP57 and the other end of capacitor C51, and the other of the source / drain is connected to one of the source / drain of transistor MP56.

[0240] The transistor MP56 has a gate connected to the control line AZSL1, one of the source / drain connected to the other of the source / drain of the transistor MP55, and the other of the source / drain connected to the power supply line VSS.

[0241] The gate of transistor MP57 is connected to the control line WSL, the other of the source and drain is connected to the gate of transistor MP54, one of the source and drain of transistor MP55 and the other end of capacitor C51, and one of the source and drain is connected to the other of the source and drain of transistor MP58.

[0242] The transistor MP58 has a gate connected to the control line WSL, the other of its source / drain connected to one of the source / drain of the transistor MP57, and one of its source / drain connected to the other of the source / drain of the transistor MP54 and one of the source / drain of the transistor MP59.

[0243] The transistor M59 has a gate connected to the control line DSL, one of its source / drain connected to the other of the source / drain of the transistor MP54 and one of the source / drain of the transistor MP58, and the other of its source / drain connected to one of the source / drain of the transistor MP60 and the anode of the light-emitting element EL.

[0244] The transistor MP60 has a gate connected to the control line AZSL2, one of the source / drain connected to the other of the source / drain of the transistor MP59 and the anode of the light-emitting element EL, and the other of the source / drain connected to the power supply line VSS.

[0245] With this configuration, in pixel PIX, transistors MP52, MP54, MP58, and MP57 are turned on, setting the voltage across capacitor C51 based on the pixel signal supplied from signal line SGL. Transistors MP53 and MP59 are turned on and off based on the signal on control line DSL. While transistor MP53 and MP59 are on, transistor MP54 passes a current corresponding to the voltage across capacitor C51 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor MP54.

[0246] In this way, the pixel PIX emits light with a luminance according to the pixel signal.

[0247] The transistors MP55 and MP56 are turned on / off based on the signal on the control line AZSL1. While the transistors MP55 and MP56 are in the on state, the transistor MP54 is initialized by setting the gate voltage to the voltage of the power supply line VSS.

[0248] The transistor MP60 is turned on / off based on the signal on the control line AZSL2. While the transistor MP60 is in the on state, the light-emitting element EL is initialized by setting the anode voltage to the voltage of the power supply line VSS.

[0249] Note that the transistors MP52 to MP60 may be transistors using low temperature polysilicon (LTPS), and at least one of the transistors MP55 to MP58 and MP60 may be a transistor using an oxide semiconductor.

[0250] As described above, the detection circuit 14 may be incorporated into an LDO circuit connected to the power supply line VCCP, or may be connected to the anode or cathode of the light-emitting element EL or the ground side of the transistor MP60 to detect current.

[0251] (Fourteenth embodiment)

[0252] 23 shows another example of the configuration of the pixel PIX. The signal on the control line WSNL and the signal on the control line WSPL are mutually inverted signals.

[0253] The pixel PIX has capacitors C61 and C62, transistors MN63, MP64, MN65 to MN67, and a light-emitting element EL. The transistors MN63, MN65 to MN67 are, for example, N-type MOSFETs, and the transistor MP64 is, for example, a P-type MOSFET.

[0254] The gate of transistor MN63 is connected to control line WSNL, the other of its source / drain is connected to signal line SGL and one of the source / drain of transistor MP64, and one of its source / drain is connected to the other of the source / drain of transistor MP64, capacitors C61 and C62, and the gate of transistor MN65.

[0255] The gate of transistor MP64 is connected to control line WSPL, one of the source / drain is connected to signal line SGL and the other of the source / drain of transistor MN63, and the other of the source / drain is connected to one of the source / drain of transistor MN63, one end of capacitor C61, one end of capacitor C62, and the gate of transistor MN65.

[0256] Capacitor C61 is configured using, for example, a MOM (Metal Oxide Metal) capacitor, one end of which is connected to one of the source and drain of transistor MN63, the other of the source and drain of transistor MP64, one end of capacitor C62, and the gate of transistor MN65, and the other end of which is connected to power supply line VSS2. Capacitor C61 may also be configured using, for example, a MOS capacitor or an MIM (Metal Insulator Metal) capacitor.

[0257] Capacitor C62 is configured using, for example, a MOS capacitor, with one end connected to one of the source and drain of transistor MN63, the other of the source and drain of transistor MP64, one end of capacitor C61, and the gate of transistor MN65, and the other end connected to power supply line VSS2. Capacitor C62 may also be configured using, for example, a MOM capacitor or an MIM capacitor. Capacitor C62 may also have the other end connected to power supply line VSS3 (not shown).

[0258] The gate of transistor MN65 is connected to one of the source / drain of transistor MN63, the other of the source / drain of transistor MP64, one end of capacitor C61, and one end of capacitor C62, the other of the source / drain is connected to power supply line VCCP, and one of the source / drain is connected to the other of the source / drain of transistors MN66 and MN67.

[0259] The gate of transistor MN66 is connected to control line AZL, the other of the source / drain is connected to one of the source / drain of transistor MN65 and the other of the source / drain of transistor MN67, and one of the source / drain is connected to power supply line VSS1.

[0260] The gate of transistor MN67 is connected to control line DSL, the other of the source and drain is connected to one of the source and drain of transistor MN65 and the other of the source and drain of transistor MN66, and one of the source and drain is connected to the anode of light-emitting element EL. Note that a configuration may be adopted in which transistor MN67 and control line DSL are not provided, and one of the source and drain of transistor MN65 is connected to the other of the source and drain of transistor MN66 and the anode of light-emitting element EL.

[0261] With this configuration, in pixel PIX, when at least one of transistors MN63 and MP64 is turned on, the voltage across capacitors C61 and C62 is set based on the pixel signal supplied from signal line SGL. Transistor MN67 turns on and off based on the signal on control line DSL. While transistor MN67 is on, transistor MN65 passes a current corresponding to the voltage across capacitors C61 and C62 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor MP65.

[0262] In this way, the pixel PIX emits light with a luminance according to the pixel signal.

[0263] Transistor MN66 may be turned on / off based on the signal on control line AZL. Alternatively, transistor MN66 may function as a resistive element having a resistance value according to the signal on control line AZL. In this case, transistors MN65 and MN66 form a so-called source follower circuit.

[0264] Note that the transistors MN63, MP64, and MN65 to MN67 may be transistors using low temperature polysilicon (LTPS), and at least one of the transistors MN63, MP64, and MN66 may be a transistor using an oxide semiconductor.

[0265] As described above, the detection circuit 14 may be incorporated into an LDO circuit connected to the power supply line VCCP, or may be connected to the anode or cathode of the light-emitting element EL or the ground side of the transistor MP66 to detect current.

[0266] (Fifteenth embodiment)

[0267] 24 shows another example of the configuration of pixel PIX. This pixel PIX has a capacitor C71, transistors MN72 to MN77, and a light-emitting element EL. The transistors MN72 to MN77 are, for example, N-type MOSFETs.

[0268] The gate of transistor MN72 is connected to control line WSL, the other of the source / drain is connected to signal line SGL, and one of the source / drain is connected to one of the source / drain of transistor MN74 and the other of the source / drain of transistor MN75.

[0269] One end of capacitor C71 is connected to the gate of transistor MN74 and one of the source and drain of transistor MN76, and the other end is connected to the other of the source and drain of transistor MN77, one of the source and drain of transistor MN75, and the anode of light-emitting element EL.

[0270] The gate of transistor MN73 is connected to control line DSL1, the other of the source / drain is connected to power supply line VCCP, and one of the source / drain is connected to the other of the source / drain of transistor MN74 and the other of the source / drain of transistor MN76.

[0271] The gate of transistor MN74 is connected to one of the source / drain of transistor MN76 and one end of capacitor C71, the other of the source / drain is connected to one of the source / drain of transistor MN73 and the other of the source / drain of transistor MN76, and one of the source / drain is connected to one of the source / drain of transistor MN72 and the other of the source / drain of transistor MN75.

[0272] The gate of transistor MN75 is connected to control line DSL2, the other of the source / drain is connected to one of the source / drain of transistor MN72 and one of the source / drain of transistor MN74, and one of the source / drain is connected to the other end of capacitor C71, the other of the source / drain of transistor MN77, and the anode of light-emitting element EL.

[0273] Transistor MN76 has a gate connected to control line AZSL, the other of its source / drain connected to one of the source / drain of transistor MN73 and the other of the source / drain of transistor MN74, and one of its source / drain connected to the gate of transistor MN74 and one end of capacitor C71.

[0274] The gate of transistor MN77 is connected to control line AZSL, the other of the source and drain is connected to the other end of capacitor C71, one of the source and drain of transistor MN75 and the anode of light-emitting element EL, and one of the source and drain is connected to power supply line VSS.

[0275] With this configuration, in pixel PIX, transistors MN72, MN74, and MN76 are turned on, and the voltage across capacitor C71 is set based on the pixel signal supplied from signal line SGL. Transistor MN73 turns on / off based on the signal on control line DSL1, and transistor MN75 turns on / off based on the signal on control line DSL2. While transistors MN73 and MN75 are on, transistor MN74 passes a current corresponding to the voltage across capacitor C71 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor MN74.

[0276] In this way, the pixel PIX emits light with a luminance according to the pixel signal.

[0277] The transistor MN77 is turned on / off based on the signal on the control line AZSL. While the transistor MN77 is in the on state, the light-emitting element EL is initialized by setting the anode voltage to the voltage of the power supply line VSS.

[0278] The transistors MN72 to MN77 may be transistors using low temperature polysilicon (LTPS), and the transistor MN76 may be a transistor using an oxide semiconductor.

[0279] As described above, the detection circuit 14 may be incorporated into an LDO circuit connected to the power supply line VCCP, or may be connected to the anode or cathode of the light-emitting element EL to detect current.

[0280] <5. Examples of display device applications>

[0281] The display device 1 according to the present disclosure can be applied to various electronic devices, typically VR devices, AR devices, etc. However, these examples do not exclude other applications.

[0282] (16th embodiment)

[0283] The electronic device may include, for example, an acceleration sensor and an inertial sensor (hereinafter simply referred to as a sensor), as well as a signal processing circuit and an image processing circuit.

[0284] The sensor acquires tilt information of the electronic device, which may be tilt information within an image plane. The signal processing circuit acquires a linear transformation matrix for rotating the image, etc., based on the tilt information, and converts the image, etc., into tilted data within the image plane.

[0285] A display module having a configuration corresponding to the display device 1 in the electronic device can suppress flickering of images and the like caused by an IR drop that can occur due to this tilt.

[0286] The sensor may also acquire information on the tilt of the electronic device not only within the image plane but also in a direction perpendicular to the image plane. The signal processing circuit can acquire a function (matrix) for Warp transforming the image, etc., based on the tilt within the image plane and the direction perpendicular to the image plane, and convert the image, etc., into Warp-transformed data within the image plane.

[0287] Similarly to the above, the display module having a configuration corresponding to the display device 1 in the electronic device can suppress flickering of images etc. caused by IR drop that can occur due to this orientation.

[0288] Next, application examples of the display device / display system / display module described in the above embodiments will be described.

[0289] (First application example)

[0290] The display device 1 according to the present disclosure can also be applied to a head-mounted display (HMD). The HMD can be used for virtual reality (VR), augmented reality (AR), mixed reality (MR), substitutional reality (SR), etc.

[0291] FIG. 25 is an external view of an HMD 320 which is a first application example of the display device / system.

[0292] 25 has a wearing member 322 for wearing over a person's eyes. This wearing member 322 is fixed by hooking it onto a person's ear, for example.

[0293] A display device 321 is provided inside the HMD 320, and a person wearing the HMD 320 can view a stereoscopic image or the like on this display device 321. The HMD 320 is equipped with, for example, a wireless communication function and an acceleration sensor, and can switch the stereoscopic image or the like displayed on the display device 321 according to the posture, gestures, or the like of the wearer.

[0294] Alternatively, a camera may be provided in the HMD 320 to capture an image of the wearer's surroundings, and an image obtained by combining the image captured by the camera with an image generated by a computer may be displayed on the display device 321.

[0295] For example, by placing a camera on the back side of the display device 321 that is visible to the wearer of the HMD 320, and using this camera to capture an image of the area around the wearer's eyes, and then displaying the captured image on another display attached to the outer surface of the HMD 320, people around the wearer can grasp the wearer's facial expressions and eye movements in real time.

[0296] (Second application example)

[0297] Note that various types of HMD 320 are possible. For example, as shown in Figure 26, the display device / display system according to the present disclosure can also be applied to smart glasses 340 that display various information on glasses 344.

[0298] The smart glasses 340 in FIG. 26 have a main body 341 , an arm 342 , and a lens barrel 343 .

[0299] The main body 341 is connected to the arm 342. The main body 341 is detachable from the glasses 344. The main body 341 incorporates a control board for controlling the operation of the smart glasses 340 and a display unit.

[0300] The main body 341 and the lens barrel are connected to each other via an arm 342. The lens barrel 343 outputs image light emitted from the main body 341 via the arm 342 to the lens 345 side of the glasses 344. This image light passes through the lens 345 and enters the human eye.

[0301] A wearer of the smart glasses 340 in FIG. 26 can see not only the surrounding situation but also various pieces of information emitted from the lens barrel 343, just like with regular glasses.

[0302] (Third application example)

[0303] The display device / display system according to the present disclosure is applicable not only to various displays used in vehicles but also to displays mounted on various electronic devices.

[0304] Fig. 27A is a front view of a digital camera 310, which is a third application example of the display device / display system, and Fig. 27B is a rear view of the digital camera 310. The digital camera 310 in Figs. 27A and 27B shows an example of a single-lens reflex camera with an interchangeable lens 312, but the present invention is also applicable to cameras in which the lens 312 cannot be interchangeable.

[0305] In the camera of Figures 27A and 27B, the photographer holds the grip 313 of the camera body 311, looks through the electronic viewfinder 315, decides on the composition of the shot, adjusts the focus, and then presses the shutter, and the photographed data is saved in the memory within the camera.

[0306] 27B, the rear side of the camera is provided with a monitor screen 314 that displays shooting data, live images, etc., and an electronic viewfinder 315. In addition, the top of the camera may be provided with a sub-screen that displays setting information such as shutter speed and exposure value.

[0307] By arranging a sensor on the back side of a monitor screen 314, an electronic viewfinder 315, a sub-screen, etc. used in a camera, it can be used as a display device / display system according to the present disclosure.

[0308] (Fourth Application Example)

[0309] 28 shows an example of the appearance of a television device 330. The television device 330 has a video display screen unit 331 including a front panel 332 and a filter glass 333.

[0310] The techniques according to the above-described embodiments can be applied to this video display screen unit 331 .

[0311] 29 shows an example of the appearance of a smartphone 350. The smartphone 350 has a display unit 351 that displays various information, and an operation unit 352 that includes buttons and the like that accept operation inputs by the user.

[0312] The techniques according to the above-described embodiments can be applied to this display unit 351 .

[0313] (Example 6)

[0314] The display device / display system according to the present disclosure can be used for various purposes. Figures 30A and 30B are diagrams showing the internal configuration of a vehicle 360, which is a sixth application example of a display device / display system according to the present disclosure. Figure 30A is a diagram showing the internal configuration of the vehicle 360 ​​from the rear to the front of the vehicle 360, and Figure 30B is a diagram showing the internal configuration of the vehicle 360 ​​from diagonally rear to diagonally front of the vehicle 360.

[0315] The vehicle 360 ​​of Figures 30A and 30B has a center display 361, a console display 362, a head-up display 363, a digital rearview mirror 364, a steering wheel display 365, and a rear entertainment display 366.

[0316] Center display 361 is arranged on dashboard 367 in a position facing driver's seat 368 and passenger seat 369. Although Fig. 30A and Fig. 30B show an example of horizontally elongated center display 361 extending from driver's seat 368 side to passenger seat 369 side, the screen size and arrangement location of center display 361 are arbitrary.

[0317] The center display 361 can display information detected by various sensors. As a specific example, the center display 361 can display an image captured by an image sensor, an image showing the distance to obstacles in front of or beside the vehicle measured by a Time of Flight (ToF) sensor, the body temperature of a passenger detected by an infrared sensor, etc. The center display 361 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information.

[0318] Safety-related information includes information such as detection of drowsiness, distraction, mischief by children in the vehicle, whether seat belts are fastened, and whether passengers have been abandoned, and is information detected, for example, by a sensor placed on top of the back side of the center display 361.

[0319] The operation-related information is obtained by detecting gestures related to the operation of the occupant using a sensor. The detected gestures may include operations of various facilities in the vehicle 360. For example, operations of the air conditioning system, navigation system, AV system, lighting system, etc. are detected.

[0320] The life log includes the life logs of all occupants. For example, the life log includes a record of each occupant's actions while on board. By acquiring and saving the life log, it is possible to confirm the state of the occupants at the time of an accident.

[0321] The health-related information may be acquired by detecting the body temperature of the occupant using a temperature sensor and inferring the occupant's health condition based on the detected body temperature. Alternatively, the occupant's face may be captured using an image sensor and the occupant's health condition may be inferred from the facial expression in the captured image. Furthermore, the occupant may be spoken to by an automated voice and the occupant's health condition may be inferred based on the occupant's responses.

[0322] The authentication / identification-related information includes a keyless entry function that uses a sensor to perform facial recognition, and a function that automatically adjusts seat height and position using facial recognition.

[0323] The entertainment-related information includes functions such as using a sensor to detect operation information of the AV device by the occupant, and using a sensor to recognize the occupant's face and provide content suitable for the occupant via the AV device.

[0324] The console display 362 can be used to display, for example, life log information. The console display 362 is disposed near a shift lever 371 on a center console 370 between a driver's seat 368 and a passenger seat 369. The console display 362 can also display information detected by various sensors. The console display 362 may also display an image of the vehicle's surroundings captured by an image sensor, or an image showing the distance to an obstacle around the vehicle.

[0325] The head-up display 363 is virtually displayed behind the windshield 372 in front of the driver's seat 368. The head-up display 363 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information. Because the head-up display 363 is often virtually located in front of the driver's seat 368, it is suitable for displaying information directly related to the operation of the vehicle 360, such as the speed of the vehicle 360 ​​and the remaining fuel (battery) level.

[0326] The digital rearview mirror 364 can not only display the rear of the vehicle 360 ​​but also display the state of passengers in the rear seats. Therefore, by placing a sensor on the back side of the digital rearview mirror 364, it can be used to display, for example, life log information.

[0327] The steering wheel display 365 is disposed near the center of the steering wheel 373 of the vehicle 360. The steering wheel display 365 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information. In particular, because the steering wheel display 365 is located near the driver's hands, it is suitable for displaying life log information such as the driver's body temperature, and information related to the operation of AV equipment, air conditioning equipment, etc.

[0328] The rear entertainment display 366 is attached to the back of the driver's seat 368 and the passenger seat 369 and is intended for viewing by rear seat passengers. The rear entertainment display 366 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information. In particular, since the rear entertainment display 366 is located in front of the rear seat passengers, information related to the rear seat passengers is displayed on the rear entertainment display 366. For example, the rear entertainment display 366 may display information related to the operation of the AV equipment or air conditioning equipment, or the results of measuring the body temperature of the rear seat passengers using a temperature sensor.

[0329] As mentioned above, by placing a sensor on the back side of a display device / display system, it is possible to measure the distance to surrounding objects. Optical distance measurement methods can be broadly divided into passive and active types.

[0330] Passive distance measurement is performed by receiving light from an object without projecting light from the sensor onto the object. Passive distance measurement methods include the lens focusing method, the stereo method, and the monocular method.

[0331] Active types measure distance by projecting light onto an object and receiving the light reflected from the object with a sensor. Active types include optical radar, active stereo, photometric stereo, moire topography, and interferometry.

[0332] The display device 1 according to the present disclosure can be applied to any of these distance measurement methods. By using a sensor disposed on the back side of the display device 1 according to the present disclosure, the above-mentioned passive or active distance measurement can be performed.

[0333] The above-described embodiment may be modified as follows.

[0334] (1) A display device comprising: a light-emitting element; a pixel circuit that drives the light-emitting element; a pixel array in which the light-emitting elements and the pixel circuits are arranged in a two-dimensional array; a detection circuit that detects a current flowing through the light-emitting element; and an address generation circuit that obtains a timing at which the light-emitting element is to be turned off based on the current detected by the detection circuit.

[0335] (2) The display device according to (1), further comprising: a drive circuit that outputs a drive control signal for the light-emitting element to the pixel circuit, the drive circuit outputting a signal that independently controls the light-emission timing and the light-off timing acquired by the address generation circuit.

[0336] (3) The display device according to (2), wherein the address generating circuit controls the extinction timing to be earlier as the current value detected by the detection circuit increases.

[0337] (4) The display device according to (2) or (3), wherein the address generation circuit acquires the extinction timing after the light emitting elements in the display region of the pixel array emit light.

[0338] (5) The display device according to (4), wherein the drive circuit outputs a control signal for turning off the light-emitting element at the light-off timing in a frame in which the address generation circuit acquires the light-off timing.

[0339] (6) The display device according to (5), wherein the address generation circuit obtains the extinction timing by obtaining a difference between a current value of a previous frame and a current value of a current frame.

[0340] (7) The display device according to (5), wherein the address generation circuit obtains the extinction timing by obtaining a difference between a predetermined current value and a current value of a current frame.

[0341] (8) The display device according to any one of (4) to (7), wherein the address generation circuit acquires the extinction timing after the light emitting elements in the entire display area of ​​the pixel array have emitted light.

[0342] (9) The display device according to any one of (4) to (7), wherein the address generation circuit divides a display area of ​​the pixel array and obtains the extinction timing for each divided area, and the drive circuit controls the extinction for each divided display area.

[0343] (10) A display device according to any one of (4) to (7), wherein the light-emitting element emits light of one of a plurality of colors, and displays a mixture of the plurality of colors in the pixel array; the address generation circuit acquires the extinction timing for each of the plurality of colors; and the drive circuit controls the timing for extinguishing the light-emitting element for each of the plurality of colors.

[0344] (11) The display device according to any one of (4) to (10), wherein, when the brightness control throughout the frame in the display area of ​​the pixel array is controlled by a duty ratio, the address generation circuit acquires the extinction timing in each light emission period in the frame.

[0345] (12) The display device according to (11), wherein the detection circuit detects a current in a line that belongs to a predetermined region in the pixel array.

[0346] (13) The display device according to any one of (4) to (12), wherein when a display in a partial region of the pixel array is changed, the detection circuit detects a current related to a display in a region other than the partial region.

[0347] (14) The display device according to any one of (1) to (13), wherein the address generating circuit includes a shift register.

[0348] (15) An electronic device comprising: a light-emitting element; a pixel circuit that drives the light-emitting element; a pixel array in which the light-emitting elements and the pixel circuits are arranged in a two-dimensional array; a detection circuit that detects a current flowing through the light-emitting element; an address generation circuit that obtains, as address information, the timing at which the light-emitting element turns off based on the current detected by the detection circuit; and a drive circuit that outputs a signal that controls the drive of the light-emitting element in each of the pixel circuits.

[0349] (16) The electronic device described in (15) further includes an acceleration sensor; and an image processing circuit that generates data by warping image data to be displayed when the display area of ​​the pixel array in the acceleration sensor is tilted, wherein the drive circuit outputs a signal to drive the light-emitting element based on an output from the image processing circuit.

[0350] The aspects of the present disclosure are not limited to the above-described embodiments and include various conceivable modifications, and the effects of the present disclosure are not limited to the above-described contents. The components in each embodiment may be appropriately combined and applied. In other words, various additions, modifications, and partial deletions are possible within the scope of the conceptual idea and intent of the present disclosure, which is derived from the content defined in the claims and their equivalents.

[0351] 1: display device, 10: pixel array, 100: pixel, PIX: pixel, 11: control circuit, 12: first drive circuit, 120: signal line, 13: second drive circuit, 130: signal line, 14: detection circuit, 15: comparison circuit, 16: address generation circuit, 17: memory, 20: LDO, 20R, 20G, 20B: LDO 310: digital camera, 311: camera body, 312: lens, 313: grip, 314: monitor screen, 315: electronic viewfinder, 320: HMD, 321: display device, 322: mounting member, 330: television device, 331: video display screen unit, 332: front panel, 333: filter glass, 340: Smart glasses, 341: Main body, 342: Arm, 343: Lens barrel, 344: Glasses, 345: Lens, 350: Smartphone, 351: Display, 352: Operation unit, 360: Vehicle, 361: Center display, 362: Console display, 363: Head-up display, 364: Digital rearview mirror, 365: Steering wheel display, 366: Rear entertainment display, 367: Dashboard, 368: Driver's seat, 369: Passenger seat, 370: Center console, 371: Shift lever, 372: Windshield, 373: Steering wheel

Claims

1. A display device comprising: a light-emitting element; a pixel circuit that drives the light-emitting element; a pixel array in which the light-emitting elements and the pixel circuits are arranged in a two-dimensional array; a detection circuit that detects a current flowing through the light-emitting element; and an address generation circuit that obtains a timing at which the light-emitting element should turn off based on the current detected by the detection circuit.

2. The display device according to claim 1, further comprising: a drive circuit that outputs a drive control signal for the light-emitting element to the pixel circuit, the drive circuit outputting a signal that independently controls the light-emitting timing and the light-extinction timing acquired by the address generation circuit.

3. The display device according to claim 2, wherein the address generation circuit controls the extinction timing to be earlier as the current value detected by the detection circuit increases.

4. The display device according to claim 2, wherein the address generation circuit acquires the extinction timing after the light emitting elements in the display region of the pixel array emit light.

5. The display device according to claim 4, wherein the drive circuit outputs a control signal for turning off the light-emitting element at the light-off timing in a frame in which the address generation circuit acquires the light-off timing.

6. The display device according to claim 5, wherein the address generation circuit obtains the extinction timing by obtaining a difference between a current value in a previous frame and a current value in a current frame.

7. The display device according to claim 5, wherein the address generation circuit obtains the extinction timing by obtaining a difference between a predetermined current value and a current value of a current frame.

8. The display device according to claim 4, wherein the address generation circuit acquires the extinction timing after the light emitting elements in the entire display area of ​​the pixel array have emitted light.

9. The display device according to claim 4, wherein the address generation circuit divides the display area of ​​the pixel array and obtains the extinction timing for each divided area, and the drive circuit controls the extinction for each divided display area.

10. The display device according to claim 4, wherein the light-emitting element emits light of one of a plurality of colors, and displays a mixture of the plurality of colors in the pixel array; the address generation circuit obtains the extinction timing for each of the plurality of colors; and the drive circuit controls the extinction timing of the light-emitting element for each of the plurality of colors.

11. The display device according to claim 4, wherein when brightness control throughout a frame in the display area of ​​the pixel array is controlled by a duty ratio, the address generation circuit obtains the extinction timing in each light emission period in the frame.

12. The display device according to claim 11, wherein the detection circuit detects a current in a line belonging to a predetermined region in the pixel array.

13. The display device according to claim 4, wherein when a display in a partial region of the pixel array is changed, the detection circuit detects a current related to a display in a region other than the partial region.

14. The display device according to claim 1, wherein the address generation circuit comprises a shift register.

15. An electronic device comprising: a light-emitting element; a pixel circuit that drives the light-emitting element; a pixel array in which the light-emitting elements and the pixel circuits are arranged in a two-dimensional array; a detection circuit that detects a current flowing through the light-emitting element; an address generation circuit that obtains the timing at which the light-emitting element is to be turned off based on the current detected by the detection circuit; and a drive circuit that outputs a signal that controls the drive of the light-emitting element in each of the pixel circuits.

16. The electronic device according to claim 15, further comprising: an acceleration sensor; and an image processing circuit that generates data by warping image data to be displayed when the display area of ​​the pixel array in the acceleration sensor is tilted; wherein the drive circuit outputs a signal to drive the light-emitting element based on an output from the image processing circuit.

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