Method and apparatus for predicting device characteristics based on artificial intelligence

Abstract

According to an embodiment of the present disclosure, a method for predicting characteristics of a device by receiving design parameters and bias conditions of the device as an input, performed by a computing apparatus, comprises the steps of: pre-training a neural network model having an encoder-decoder structure on the basis of pre-input data comprising device data of a plurality of technology nodes; generating a device vector in an encoder on the basis of first input data comprising device data of a target technology node; and predicting characteristics of a target device in a decoder on the basis of the device vector, and design parameters and bias conditions of the target device.

Description

Method and device for predicting device characteristics based on artificial intelligence

[0001] The present disclosure relates to deep learning technology in the semiconductor field, and more particularly, to a method and apparatus for predicting characteristics of semiconductor devices using limited measurement data of a new technology node.

[0002] As transistor semiconductor devices continue to shrink, the accuracy of integrated circuit design and compact modeling techniques are becoming increasingly important. Compact modeling techniques primarily develop analytical model equations, such as the Berkeley Short-channel IGFET Model (BSIM), and extract hundreds of model parameters to describe the electrical characteristics of MOSFETs. However, device miniaturization has led to complex physical phenomena, necessitating more sophisticated model equations. This has made it increasingly difficult to improve modeling accuracy or shorten turnaround times.

[0003] To address these issues, learning-based models have recently been proposed. However, these AI-based models still have limitations, relying on large amounts of training data for accurate performance. In real-world device modeling situations, measurement data is often limited, and this dependency hinders the model's utilization.

[0004] Therefore, a new approach to compact modeling technology is required that can easily adapt to new technology nodes and enable accurate device simulation even with limited measurement data.

[0005] The present disclosure is conceived in response to the aforementioned background technology, and aims to provide a neural network model capable of accurate device simulation even with limited measurement data at a specific technology node.

[0006] The present disclosure can improve prediction performance by learning general characteristics and relationships of elements through large-scale dictionary learning.

[0007] The present disclosure can provide a neural network model with flexibility that can be easily adapted to new technology nodes.

[0008] However, the problems to be solved in this disclosure are not limited to the problems mentioned above, and other problems not mentioned can be clearly understood based on the description below.

[0009] According to one embodiment of the present disclosure for realizing the task as described above, a method for predicting characteristics of a device by receiving design parameters and bias conditions of the device, which is performed by a computing device, includes the steps of pre-training a neural network model of an encoder-decoder structure based on preliminary input data including device data of a plurality of technology nodes, the step of generating a device vector in the encoder based on first input data including device data of a target technology node, and the step of predicting characteristics of the target device in the decoder based on the device vector and the design parameters and bias conditions of the target device.

[0010] Alternatively, the design parameters include one or more of a channel width (W), a channel length (L), or an operating temperature (T) of the device, and the bias conditions include one or more of a drain-source voltage, a gate-source voltage, or a bulk-source voltage of the device.

[0011] Alternatively, the step of pre-training the neural network model is characterized by including a first preprocessing step of normalizing design parameters and bias conditions included in the pre-input data.

[0012] Alternatively, the first preprocessing step includes normalizing the reciprocal of the channel width (W) and the reciprocal of the channel length (L) based on the target technology node, and normalizing the bias condition based on the supply voltage.

[0013] Alternatively, the first input data is characterized in that it includes design parameters of the device of the target technology node and characteristics of the device measured under bias conditions.

[0014] Alternatively, the encoder is characterized by comprising: one or more fully connected layers for processing input data, one or more self-attention layers for processing outputs of the fully connected layers, and an aggregation layer for aggregating outputs of the self-attention layers to generate a component vector, which is a fixed-length latent vector.

[0015] Alternatively, the decoder is characterized by including an input layer that receives the element vector and design parameters and bias conditions of the element to be predicted as inputs, one or more fully connected layers, one or more residual blocks including skip connections that directly connect the input and output of the fully connected layers, and an output layer that outputs electrical characteristics of the element to be predicted.

[0016] Alternatively, the characteristics of the device include capacitance data, characterized in that the capacitance data includes one or more of a total gate capacitance (Cgg), a gate source capacitance (Cgs), a gate drain capacitance (Cgd), a gate bulk capacitance (Cgb) or capacitance components of the device.

[0017] Alternatively, the method for predicting the device characteristics is characterized by including a step of normalizing the capacitance data based on a value obtained by dividing the capacitance data by a channel width (W)*channel length (L) and then dividing the result by an oxide capacitance (Cox).

[0018] Alternatively, the neural network model is characterized in that it outputs at least one of a gate charge (Qg), a drain charge (Qd), a source charge (Qs), and a bulk charge (Qb), and generates capacitance data based on the following mathematical expression 1 that differentiates any one of the gate charge (Qg), the drain charge (Qd), the source charge (Qs), and the bulk charge (Qb) into a voltage, and includes a first loss function for minimizing a difference between the capacitance data and the measured capacitance.

[0019] [Mathematical Formula 1]

[0020] Cij = dQi / dVj

[0021] i, j are gate (g), drain (d), source (s), and bulk (b)

[0022] Alternatively, the characteristics of the device are characterized by including a drain current (Id).

[0023] Alternatively, the step of pre-training the neural network model is characterized by including a step of normalizing the drain current (Id) based on a value obtained by dividing the drain current (Id) by the channel width (W) / channel length (L) and taking the natural logarithm.

[0024] Alternatively, the neural network model includes a second loss function that minimizes an error between a predicted value and a measured value of the drain current (Id), characterized in that the second loss function includes a first term obtained by log-transforming the predicted value and the measured value to handle an error in an exponentially increasing region of the drain current (Id), and a second term obtained by exponentially transforming the predicted value to handle an error in a linearly increasing region of the drain current (Id).

[0025] According to one embodiment of the present disclosure for realizing the task described above, a computing device for receiving design parameters and bias conditions of a device and predicting characteristics of the device includes a processor including at least one core, a memory including program codes executable in the processor, and a network unit. The processor is characterized in that it pre-trains a neural network model of an encoder-decoder structure based on pre-input data including device data of a plurality of technology nodes, generates a device vector in the encoder based on first input data including device data of a target technology node, and predicts the characteristics of the target device in the decoder based on the device vector and the design parameters and bias conditions of the target device.

[0026] Alternatively, the design parameters include one or more of a channel width (W), a channel length (L), or an operating temperature (T) of the device, and the bias conditions include one or more of a drain-source voltage, a gate-source voltage, or a bulk-source voltage of the device.

[0027] Alternatively, the first input data is characterized in that it includes design parameters of the device of the target technology node and characteristics of the device measured under bias conditions.

[0028] This disclosure enables high-accuracy device simulations even with limited measurement data and allows rapid adaptation to new technology nodes, thereby reducing modeling costs and time.

[0029] In particular, since both IV and CV characteristics can be accurately predicted, it can be utilized in various circuit designs and simulations.

[0030] FIG. 1 is a block diagram of a computing device according to one embodiment of the present disclosure.

[0031] FIG. 2 is a block diagram illustrating the structure of a device characteristic prediction device according to one embodiment of the present disclosure.

[0032] FIG. 3 is a drawing illustrating a device for predicting device characteristics including a neural network model for predicting device characteristics by inputting design parameters and bias conditions of a device according to one embodiment of the present disclosure.

[0033] FIG. 4 is a flowchart illustrating a method for predicting device characteristics according to one embodiment of the present disclosure.

[0034] Below, embodiments of the present disclosure are described in detail with reference to the attached drawings so that those skilled in the art can easily implement the present disclosure. The embodiments presented in this disclosure are provided to enable those skilled in the art to utilize or implement the contents of the present disclosure. Accordingly, various modifications to the embodiments of the present disclosure will be apparent to those skilled in the art. That is, the present disclosure may be implemented in various different forms and is not limited to the embodiments described below.

[0035] Throughout the specification of this disclosure, identical or similar drawing numbers refer to identical or similar components. Furthermore, for the purpose of clearly describing the disclosure, drawing numbers for parts in the drawings that are not relevant to the description of the disclosure may be omitted.

[0036] The term "or" as used herein is intended to mean an inclusive "or" rather than an exclusive "or." That is, unless otherwise specified herein or clear from context, "X employs A or B" should be understood to mean either of the natural inclusive permutations. For example, unless otherwise specified herein or clear from context, "X employs A or B" can be interpreted to mean either X employs A, X employs B, or X employs both A and B.

[0037] The term "and / or" as used herein should be understood to refer to and include all possible combinations of one or more of the related concepts listed.

[0038] The terms "comprises" and / or "comprising" as used herein should be understood to mean the presence of certain features and / or components. However, it should be understood that the terms "comprises" and / or "comprising" do not exclude the presence or addition of one or more other features, other components, and / or combinations thereof.

[0039] Unless otherwise specified in this disclosure or unless the context makes it clear that the singular form is intended to be referred to, the singular should generally be construed to include “one or more.”

[0040] The term "Nth (N is a natural number)" used in the present disclosure can be understood as an expression used to mutually distinguish components of the present disclosure based on a predetermined standard such as a functional perspective, a structural perspective, or convenience of explanation. For example, components performing different functional roles in the present disclosure can be distinguished as a first component or a second component. However, components that are substantially the same within the technical spirit of the present disclosure but must be distinguished for convenience of explanation may also be distinguished as a first component or a second component.

[0041] The term "acquisition" as used in this disclosure may be understood to mean not only receiving data through a wired or wireless communication network with an external device or system, but also generating data in an on-device form.

[0042] Meanwhile, the term "module" or "unit" used in the present disclosure can be understood as a term referring to an independent functional unit that processes computing resources, such as a computer-related entity, firmware, software or a part thereof, hardware or a part thereof, or a combination of software and hardware. At this time, the "module" or "unit" may be a unit composed of a single element, or a unit expressed as a combination or set of multiple elements. For example, as a narrow concept, a "module" or "unit" may refer to a hardware element of a computing device or a set thereof, an application program that performs a specific function of software, a processing process implemented through software execution, or a set of instructions for program execution, etc. In addition, as a broad concept, a "module" or "unit" may refer to the computing device itself that constitutes the system, or an application running on the computing device, etc. However, since the above-described concept is only an example, the concept of “module” or “part” may be defined in various ways within a range understandable to those skilled in the art based on the contents of the present disclosure.

[0043] The term "model" as used herein may be understood as a system implemented using mathematical concepts and language to solve a specific problem, a set of software units to solve a specific problem, or an abstract model of a processing process to solve a specific problem. For example, a neural network "model" may refer to the entire system implemented as a neural network that has problem-solving capabilities through learning. In this case, the neural network can have problem-solving capabilities by optimizing the parameters connecting nodes or neurons through learning. A neural network "model" may include a single neural network or a set of neural networks that are a combination of multiple neural networks.

[0044] The term "data" used in this disclosure may include "images," signals, and the like. The term "image" used in this disclosure may refer to multidimensional data composed of discrete image elements. In other words, "image" may be understood as a term referring to a digital representation of an object visible to the human eye. For example, "image" may refer to multidimensional data composed of elements corresponding to pixels in a two-dimensional image. "Image" may refer to multidimensional data composed of elements corresponding to voxels in a three-dimensional image.

[0045] The term "block" used in this disclosure can be understood as a set of configurations categorized based on various criteria, such as type and function. Therefore, the configurations classified as a single "block" can vary depending on the criteria. For example, a neural network "block" can be understood as a set of neural networks including at least one neural network. In this case, the neural networks included in the neural network "block" can be assumed to perform specific operations identically.

[0046] The term "functional data" used in this disclosure can be understood as multivariate data having infinite dimensional values. For example, "functional data" may be data that includes a continuously changing curve, such as a curve relating to device characteristics that represents changes in voltage with respect to current.

[0047] The term "device" as used in the present disclosure may mean a semiconductor device or a transistor. For example, the device may be a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) and may include an n-channel MOSFET or a p-channel MOSFET.

[0048] The term "electrical parameter" as used in the present disclosure can be understood as a measurable characteristic that defines the operation and performance of an electrical component, device, or system under various conditions. For example, an "electrical parameter" with respect to the characteristics of a metal-oxide-semiconductor field-effect transistor (MOSFET) is V, which represents the voltage difference between the drain and the source. DS , V represents the voltage difference between the gate and the source. GS , the current flowing through the drain, I D It may include:

[0049] The term "technology node" used in this disclosure may be an indicator of a generation of a semiconductor manufacturing process. A technology node may be expressed in nanometers (nm), such as 45 nm, 32 nm, 14 nm, and 7 nm. In the past, it referred to the gate length of a transistor, but is currently used as a symbolic number indicating a generation. The smaller the technology node, the smaller the transistor size and the higher the integration level. Parameters related to the technology node include gate length (L), gate width (W), and device operating temperature (T).

[0050] The explanation of the above terms is intended to aid understanding of the present disclosure. Therefore, unless explicitly stated as limiting the contents of the present disclosure, it should be noted that the above terms are not intended to limit the technical ideas of the present disclosure.

[0051] FIG. 1 is a block diagram of a computing device according to one embodiment of the present disclosure.

[0052] A computing device (100) according to one embodiment of the present disclosure may be a hardware device or a part of a hardware device that performs comprehensive processing and calculation of data, or may be a software-based computing environment connected to a communication network. For example, the computing device (100) may be a server that performs intensive data processing functions and shares resources, or may be a client that shares resources through interaction with a server. In addition, the computing device (100) may be a cloud system in which multiple servers and clients interact to comprehensively process data. Since the above description is only one example related to the type of computing device (100), the type of computing device (100) may be configured in various ways within a range understandable to those skilled in the art based on the contents of the present disclosure.

[0053] Referring to FIG. 1, a computing device (100) according to one embodiment of the present disclosure may include a processor (110), a memory (120), and a network unit (130). However, FIG. 1 is merely an example, and the computing device (100) may include other components for implementing a computing environment. In addition, only some of the disclosed components may be included in the computing device (100).

[0054] The processor (110) according to one embodiment of the present disclosure may be understood as a configuration unit including hardware and / or software for performing computing operations. For example, the processor (110) may read a computer program to perform data processing for machine learning. The processor (110) may process computational processes such as processing input data for machine learning, feature extraction for machine learning, and error calculation based on backpropagation. The processor (110) for performing such data processing may include a central processing unit (CPU), a general purpose graphics processing unit (GPGPU), a tensor processing unit (TPU), an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). The above-described type of the processor (110) is only one example, and thus, the type of the processor (110) may be configured in various ways within a range understandable to those skilled in the art based on the contents of the present disclosure.

[0055] The processor (110) can receive design parameters and bias conditions of a semiconductor device for simulation and train a neural network model to predict the characteristics of the device.

[0056] For example, the processor (110) can pre-train a neural network model of an encoder-decoder structure using a large-scale dataset corresponding to multiple technology nodes. The large-scale dataset can use data from various technology nodes ranging from 45 nm to 180 nm, and can include up to 35 different MOSFET device types for each node. The large-scale dataset can consider three process variations: Typical, Fast, and Slow for each device type.

[0057] As described above, the processor (110) can fine-tune the neural network model with limited data for a new technology node (32 nm) using a pre-trained neural network model. This allows the processor (110) to easily adapt the neural network model to new nodes by learning about various technology nodes and device types.

[0058] For convenience of explanation, the pre-learning target technology node is set from 45 nm to 180 nm, and the new technology node is set at 32 nm, but this is exemplary, and the present invention can be adapted to various technology nodes and device types for which data is not secured after learning a neural network model based on a technology node for which a large amount of data is secured.

[0059] The memory (120) according to one embodiment of the present disclosure may be understood as a configuration unit including hardware and / or software for storing and managing data processed in the computing device (100). That is, the memory (120) may store any type of data generated or determined by the processor (110) and any type of data received by the network unit (130). For example, the memory (120) may include at least one type of storage medium among a flash memory type, a hard disk type, a multimedia card micro type, a card type memory, a random access memory (RAM), a static random access memory (SRAM), a read-only memory (ROM), an electrically erasable programmable read-only memory (EEPROM), a programmable read-only memory (PROM), a magnetic memory, a magnetic disk, and an optical disk. In addition, the memory (120) may also include a database system that controls and manages data in a predetermined system. The type of memory (120) described above is only one example, and thus the type of memory (120) can be configured in various ways within a range understandable to those skilled in the art based on the contents of the present disclosure.

[0060] The memory (120) can structure and organize and manage data, combinations of data, and program codes executable by the processor (110) required for the processor (110) to perform operations. For example, the memory (120) can store data regarding semiconductor device characteristics received through the network unit (130) described below. The memory (120) can store program codes that operate a neural network model for predicting device characteristics to perform learning, program codes that operate a neural network model to receive data corresponding to various technology nodes and perform inference according to the purpose of use of the computing device (100), and processed data generated as the program codes are executed.

[0061] The network unit (130) according to one embodiment of the present disclosure may be understood as a component that transmits and receives data through any type of known wired or wireless communication system. For example, the network unit (130) may perform data transmission and reception using a wired or wireless communication system such as a local area network (LAN), wideband code division multiple access (WCDMA), long term evolution (LTE), wireless broadband internet (WiBro), fifth generation mobile communication (5G), ultra wide-band, ZigBee, radio frequency (RF) communication, wireless LAN, wireless fidelity, near field communication (NFC), or Bluetooth. Since the above-described communication systems are only examples, the wired and wireless communication system for data transmission and reception of the network unit (130) may be applied in various ways other than the above-described examples.

[0062] The network unit (130) can receive data necessary for the processor (110) to perform calculations through wired or wireless communication with any system or any client, etc. In addition, the network unit (130) can transmit data generated through calculations of the processor (110) through wired or wireless communication with any system or any client, etc. For example, the network unit (130) can receive data regarding characteristics of semiconductor devices through communication with a database, a cloud server, a client, etc. The network unit (130) can transmit output data of a neural network model, intermediate data derived from the calculation process of the processor (110), processed data, etc. through communication with the aforementioned database, server, or client, etc.

[0063]

[0064] FIG. 2 is a block diagram illustrating the structure of a device characteristic prediction device according to one embodiment of the present disclosure.

[0065] The device characteristic prediction device (200) may include a preprocessing module (210) and a neural network model (220).

[0066] The preprocessing module (210) can perform preprocessing on data used in the device characteristic prediction device (200) or the neural network model (220). The preprocessing module (210) can include a first preprocessing unit (212) that performs preprocessing on input data and a second preprocessing unit (214) that performs preprocessing on output data.

[0067] The first preprocessing unit (212) can preprocess design parameters (or design parameters) including a channel width (W), a channel length (L), or an operating temperature (T). For example, the first preprocessing unit (212) can take the reciprocal of the channel width (W) and the channel length (L), and normalize 1 / W and 1 / L to the minimum length of the corresponding technology node. Through this normalization, the device characteristic prediction device (200) can perform more sophisticated modeling in a small range of channel widths (W) and channel lengths (L).

[0068] The first preprocessing unit (212) can preprocess a bias condition (or bias voltage) including a drain-source voltage, a gate-source voltage, or a bulk-source voltage of the device. The first preprocessing unit (212) can normalize the bias condition including a drain-source voltage, a gate-source voltage, or a bulk-source voltage of the device by dividing it by a maximum voltage (VDD).

[0069] The second preprocessing unit (214) can preprocess the capacitance when predicting the capacitance-voltage (CV) characteristics. The second preprocessing unit (214) can divide the capacitance by the channel width (W) * channel length (L), take the logarithm, and then normalize. The second preprocessing unit (214) can normalize the capacitance by dividing it by the oxide capacitance (Cox).

[0070] The second preprocessing unit (214) can preprocess the drain current (Ids) when predicting the current-voltage (IV) characteristics. The second preprocessing unit (214) can divide the drain current (Ids) by W / L by taking advantage of the fact that the drain current (Ids) is proportional to the channel width (W) / channel length (L). The second preprocessing unit (214) can divide the drain current (Ids) by W / L, take the logarithm, and then normalize.

[0071] The device characteristic prediction device (200) can improve the learning efficiency of a neural network model (220) through a preprocessing module (210) and provide consistent performance for devices of various sizes and bias conditions.

[0072] The neural network model (220) can utilize various types of neural network models with an encoder-decoder structure, such as a recurrent neural network-based model, a convolutional neural network-based model, a transformer-based model, and an autoencoder.

[0073] The neural network model (220) may include an encoder (222) and a decoder (224). The encoder (222) may convert input data into a compressed latent vector (or element vector). The decoder (224) may convert the latent vector (or element vector) into a desired output format. For example, in a device characteristic prediction device (200), the encoder (222) may process limited measurement data, and the decoder (224) may be used to predict device characteristics such as capacitance and drain current under new conditions.

[0074] The neural network model (220) may include fully connected layers. Fully connected layers can learn complex relationships by performing nonlinear transformations of input data.

[0075] The neural network model (220) may include a self-attention layer. Self-attention layers are primarily used in encoders and can learn global context by capturing relationships between various input data points. The neural network model (220) can analyze data from multiple perspectives through multi-head attention (MHA).

[0076] The neural network model (220) may include skip connections. Skip connections directly connect the output of the encoder to the corresponding layer of the decoder, enabling a direct flow of information, thereby alleviating the gradient vanishing problem.

[0077] The neural network model (220) may include residual blocks. Residual blocks are primarily used in decoders, and can stabilize learning and improve performance by directly adding input to output.

[0078] The neural network model (220) may include a convolutional layer and can effectively learn and process spatial features of input data.

[0079] The neural network model (220) may include an activation function. The neural network model (220) may use a smooth function such as Swish to generate a differentiable and smooth capacitance curve.

[0080] The neural network model (220) may include a loss function. The device characteristic prediction device may train the neural network model to minimize the loss function. For example, the loss function may include the following mathematical expression 1 for a neural network model for predicting capacitance.

[0081] [Mathematical Formula 1]

[0082]

[0083] N: total number of data points

[0084] C_ij: Capacitance value predicted by the model

[0085] data_ij is the actual measured capacitance value

[0086] l: order of distance measurement (usually 1 or 2)

[0087] i, j: gate (g), drain (d), source (s), bulk (b) respectively

[0088]

[0089] For example, a loss function such as the following mathematical expression 2 can be utilized to increase the accuracy of the linear increasing region in a neural network model for predicting drain current.

[0090] [Equation 2]

[0091]

[0092] N: total number of data points

[0093] model_output_i: the i-th log-transformed output predicted by the model

[0094] data_i: i-th actual measurement value

[0095] alpha, beta: Hyperparameters that adjust the weights of each term

[0096]

[0097] FIG. 3 is a drawing illustrating a device for predicting device characteristics including a neural network model for predicting device characteristics by inputting design parameters and bias conditions of a device according to one embodiment of the present disclosure.

[0098] Referring to FIG. 3, the device characteristic prediction device (300) may include an encoder (310) and a decoder (320).

[0099] The encoder (310) can generate an element vector (OVT), which is a latent vector, based on input data (EID).

[0100] In the process of the device characteristic prediction device (300) pre-learning a large amount of data, the input data (EID) may include device data of multiple technology nodes. In the pre-learning, the input data (EID) may include pre-input data. The input data (EID) or the pre-input data may include design parameters (G1) including a channel width (W), a channel length (L), or an operating temperature (T) for multiple technology nodes or various devices. The input data (EID) or the pre-input data may include bias conditions (G2) including a drain-source voltage (Vds), a gate-source voltage (Vgs), or a bulk-source voltage (Vbs). The input data (EID) or the pre-input data may include device characteristics (G3) corresponding to the design parameters (G1) and the bias conditions (G2). The device characteristics (G3) may include capacitance data such as Cgg, Cgb, and Cgc. The device characteristics (G3) may include IV characteristic curve data related to a drain current (Id).

[0101] In pre-training, pre-input data can include data for various technology nodes, from 45 nm to 180 nm. The pre-input data can include different MOSFET device types. For each device type, the pre-input data can consider three process variations: typical, fast, and slow. The pre-input data can include multiple bias conditions (G2) for combinations of channel width (W), channel length (L), and operating temperature (T).

[0102] The device characteristic prediction device (300) can additionally learn device data of a target technology node. The input data (EID) may include first input data including device data of the target technology node. For example, the first input data may be limited data compared to the pre-input data used in the pre-learning. The first input data may include design parameters (G1) including a channel width (W), a channel length (L), or an operating temperature (T) for the device of the target technology node. The first input data may include bias conditions (G2) including a drain-source voltage (Vds), a gate-source voltage (Vgs), or a bulk-source voltage (Vbs) for the device of the target technology node. The first input data may include characteristics (G3) of the device measured under the design parameters (G1) and the bias conditions (G2). In the first input data, the characteristics of the device (G3) may include a very limited number of Cgg-Vgs curves in a specific voltage range, or a very limited number of Cgb-Vgs curves in the same voltage range, or electrical parameters (Eps) representing the IV curve characteristics, particularly the threshold voltage (Vth).

[0103] The decoder (320) can generate output data (DOD) based on the element vector (OVT) and target element data (IP). The target element data (IP) can include design parameters and bias conditions of the target element of the technology node to be predicted. The target element data (IP) can include a channel width (W), a channel length (L), or an operating temperature (T). The target element data (IP) can include a drain-source voltage (Vds), a gate-source voltage (Vgs), or a bulk-source voltage (Vbs).

[0104] A concatenation unit (330) can concatenate an element vector (OVT) and target element data (IP) to generate a decoder input (DID). The decoder input (DID) can be a vector.

[0105] The output data (DOD) may be a result of predicting the characteristics of the target element. For example, the output data (DOD) may include second output data (OD2) including a gate charge (Qg), a drain charge (Qd), a source charge (Qs), or a bulk charge (Qb) corresponding to the target element data (IP). The output data (DOD) may include first output data (OD1) including a drain current (Id).

[0106]

[0107] FIG. 4 is a flowchart illustrating a method for predicting device characteristics according to one embodiment of the present disclosure.

[0108] Referring to FIG. 4, the device characteristic prediction device can perform preprocessing on device data to generate input data (S110).

[0109] The device characteristic prediction device can preprocess design parameters (or design parameters) including channel width (W), channel length (L), or operating temperature (T). For example, the device characteristic prediction device can take the reciprocal of the channel width (W) and channel length (L) and normalize 1 / W and 1 / L to the minimum length of the corresponding technology node. This normalization allows the device characteristic prediction device to perform more sophisticated modeling in a small range of channel widths (W) and channel lengths (L).

[0110] The device characteristic prediction device can preprocess bias conditions (or bias voltages) including the drain-source voltage, gate-source voltage, or bulk-source voltage of the device. The device characteristic prediction device can normalize the bias conditions including the drain-source voltage, gate-source voltage, or bulk-source voltage of the device by dividing them by the maximum voltage (VDD).

[0111] The device characteristic prediction device can preprocess the capacitance when predicting the capacitance-voltage (CV) characteristics. The device characteristic prediction device can normalize the capacitance by dividing it by the channel width (W) * channel length (L). The device characteristic prediction device can normalize the capacitance by dividing it by the oxide capacitance (Cox). The device characteristic prediction device can normalize the capacitance by dividing it by the channel width (W) * channel length (L) and by the oxide capacitance (Cox).

[0112] A device characteristic prediction device can preprocess the drain current (Ids) when predicting current-voltage (IV) characteristics. The device characteristic prediction device can divide the drain current (Ids) by W / L, taking advantage of the fact that the drain current (Ids) is proportional to the channel width (W) / channel length (L). The device characteristic prediction device can divide the drain current (Ids) by W / L, take the logarithm, and then normalize. Through preprocessing, the device characteristic prediction device can improve the learning efficiency of the neural network model and provide consistent performance for devices of various sizes and bias conditions.

[0113] A device for predicting device characteristics can pre-train a neural network model of an encoder-decoder structure based on pre-input data (S120). The pre-input data can include design parameters including a channel width (W), a channel length (L), or an operating temperature (T) for multiple technology nodes or various devices. The pre-input data can include bias conditions including a drain-source voltage (Vds), a gate-source voltage (Vgs), or a bulk-source voltage (Vbs). The pre-input data can include device characteristics corresponding to the design parameters and bias conditions. The device characteristics can include capacitance data such as Cgg, Cgb, and Cgc. The device characteristics can include IV characteristic curve data related to a drain current (Id).

[0114] In pre-training, pre-input data can include data for various technology nodes, from 45 nm to 180 nm. The pre-input data can include different MOSFET device types. For each device type, the pre-input data can consider three process variations: typical, fast, and slow. The pre-input data can include multiple bias conditions for combinations of channel width (W), channel length (L), and operating temperature (T).

[0115] The device for predicting device characteristics can generate a device vector from an encoder based on first input data (S130).

[0116] The first input data may include device data of a target technology node. The target technology node may be the most recent technology and may have relatively little device data. The first input data may be limited data compared to the pre-input data used in pre-learning. The first input data may include design parameters (G1) including a channel width (W), a channel length (L), or an operating temperature (T) for the device of the target technology node. The first input data may include bias conditions (G2) including a drain-source voltage (Vds), a gate-source voltage (Vgs), or a bulk-source voltage (Vbs) for the device of the target technology node. The first input data may include device characteristics (G3) measured under the design parameters (G1) and the bias conditions (G2). In the first input data, the characteristics (G3) of the device may include a very limited number of Cgg-Vgs curves in a specific voltage range, or a very limited number of Cgb-Vgs curves in the same voltage range, or electrical parameters (EPs) representing IV curve characteristics, particularly threshold voltage (Vth). An encoder trained based on the pre-input data can generate a device vector, which is a latent vector, by taking the first input data as input.

[0117] The device characteristic prediction device can generate output data from the decoder based on the device vector and target parameters (S140).

[0118] The target parameter may be the target device data (IP) described in FIG. 3. The target parameter may include design parameters and bias conditions of the target device to be predicted at the target technology node. The device characteristic prediction device may combine the device vector and the target parameter to generate a decoder input. The decoder may predict the characteristics of the target device based on the decoder input and generate output data.

[0119] The output data may include gate charge (Qg), drain charge (Qd), source charge (Qs), or bulk charge (Qb) under design parameters and bias conditions of the target device. The output data may include drain current (Id) under design parameters and bias conditions of the target device.

[0120] The device for predicting device characteristics may include a first neural network model capable of receiving three voltage (V) components (Vds, Vgs, Vbs) as input and outputting 16 capacitance components (Cgg, Cgd, Cgb, Cgs, ...) (i.e., C_ij where i, j = g, d, b, s). The output capacitance must satisfy C_ij = dQi / dVj or Curl C = 0 for the charge quantity Q (Qg, Qd, Qb, Qs).

[0121] The device characteristic prediction device may include a small number of Cgg-Vgs curves for a limited number of specific design parameter pairs (W = width, L = length, T = temperature) of a target technology node. The device characteristic prediction device may include a small number of Cgb-Vgs curves or electrical parameters (EP) representing the IV characteristics of the corresponding design parameters. The device characteristic prediction device or the first neural network model may be capable of predicting 16 capacitance components over a full range of voltages (Vds, Vgs, Vbs) for a full range of design parameter pairs (WLT) of the target technology node.

[0122] The output of the first neural network model can be the charge amounts (Qg, Qd, Qb) corresponding to W / L / T / Vds / Vgs / Vbs of the decoder input. The charge amount Qs can be obtained using the relationship (Qs = -Qg-Qd-Qb) where sum Q = 0.

[0123] The activation function of the decoder of the first neural network model can use a smooth function such as Swish. Each capacitance component can be obtained by differentiating the charge Q (Qg, Qd, Qb, Qs), which is the output of the first neural network model (C_ij = dQi / dVj), as shown below.

[0124] In the process of learning the first neural network model, the loss function can be defined as in the following mathematical equation 3. The device characteristic prediction device learns the first neural network model in a direction that minimizes the loss function.

[0125] [Equation 3]

[0126]

[0127] N: total number of data points

[0128] C_ij: Capacitance value predicted by the model

[0129] data_ij is the actual measured capacitance value

[0130] l: order of distance measurement (usually 1 or 2)

[0131] i, j: gate (g), drain (d), source (s), bulk (b) respectively

[0132] The loss function of the first neural network model uses the derivative (C_ij = dQi / dVj) value of the output charge Q (Qg, Qd, Qb, Qs), and through this, the first neural network model can be trained to satisfy specific physical conditions (e.g., C_ij = dQi / dVj or Curl C = 0).

[0133] The device characteristic prediction device can train a second neural network model that can input three voltage components (Vds, Vgs, Vbs) and output a drain current (Id). The device characteristic prediction device can include an IV curve (I-VVV) that well represents the curve characteristics in a limited number of specific design parameter pairs (W = width, L = length, T = temperature) of the target technology node.

[0134] The device characteristic prediction device can divide the IV curve into an exponential increase region and a linear increase region as the voltage increases during the process of modeling IV data.

[0135] In order to increase the accuracy of the linear increase region, the device characteristic prediction device can utilize a loss function such as the following mathematical expression 4 when learning the second neural network model.

[0136] [Equation 4]

[0137]

[0138] N: total number of data points

[0139] model_output_i: the i-th log-transformed output predicted by the model

[0140] data_i: i-th actual measurement value

[0141] alpha, beta: Hyperparameters that adjust the weights of each term

[0142]

[0143] The various embodiments of the present disclosure described above can be combined with additional embodiments and modified within the scope understood by those skilled in the art in light of the detailed description above. It should be understood that the embodiments of the present disclosure are illustrative in all respects and not restrictive. For example, each component described as a single component may be implemented in a distributed manner, and likewise, components described as distributed may be implemented in a combined manner. Accordingly, all changes or modifications derived from the meaning, scope, and equivalent concepts of the claims of the present disclosure should be construed as being included within the scope of the present disclosure.

Claims

1. A method for predicting characteristics of a device using a neural network model including an encoder and a decoder, the method being performed by a computing device including at least one processor, A step of generating an element vector in the encoder based on first input data including element data of a target technology node; and A step of predicting the characteristics of the target element in the decoder based on the element vector and the design parameters and bias conditions of the target element; Method for predicting device characteristics.

2. In paragraph 1, The above design parameters include one or more of the channel width (W), channel length (L), or operating temperature (T) of the device, wherein the bias condition comprises at least one of a drain-source voltage, a gate-source voltage, or a bulk-source voltage of the device. Method for predicting device characteristics.

3. In paragraph 2, characterized in that it includes a first preprocessing step for normalizing design parameters and bias conditions included in the first input data. Method for predicting device characteristics.

4. In paragraph 3, The above first preprocessing step is, Based on the target technology node, the reciprocal of the channel width (W) and the reciprocal of the channel length (L) are normalized, comprising a step of normalizing the bias condition based on the supply voltage; Method for predicting device characteristics.

5. In paragraph 1, wherein the first input data includes design parameters of the device of the target technology node and characteristics of the device measured under bias conditions. Method for predicting device characteristics.

6. In paragraph 1, The above encoder, One or more fully connected layers that process input data; One or more self-attention layers that process the output of the fully connected layer; and An aggregation layer that aggregates the outputs of the self-attention layer to generate a component vector, which is a latent vector of a fixed length; characterized in that it includes; Method for predicting device characteristics.

7. In paragraph 6, The above decoder, An input layer that receives as input the above element vector and the design parameters and bias conditions of the element to be predicted; One or more fully connected layers; One or more residual blocks including skip connections that directly connect the input and output of the fully connected layer; and characterized in that it includes an output layer that outputs the electrical characteristics of the predicted target element; Method for predicting device characteristics.

8. In paragraph 1, A step of pre-training a neural network model based on pre-input data including element data of multiple technology nodes; further comprising; Method for predicting device characteristics.

9. In paragraph 4, The characteristics of the above device include capacitance data, The above capacitance data is characterized in that it includes one or more of the total gate capacitance (Cgg), the gate source capacitance (Cgs), the gate drain capacitance (Cgd), the gate bulk capacitance (Cgb) or the capacitance components of the device. Method for predicting device characteristics.

10. In paragraph 9, It is characterized by including a step of normalizing based on a value obtained by dividing the above capacitance data by channel width (W) * channel length (L) and then dividing it by oxide capacitance (Cox). Method for predicting device characteristics.

11. In paragraph 10, The above neural network model outputs one or more of the gate charge (Qg), the drain charge (Qd), the source charge (Qs), and the bulk charge (Qb), Generate capacitance data based on the following mathematical expression 1, which differentiates one of the gate charge (Qg), drain charge (Qd), source charge (Qs), and bulk charge (Qb) by voltage, characterized in that it includes a first loss function for minimizing the difference between the above capacitance data and the measured capacitance. Method for predicting device characteristics. [Mathematical Formula 1] Cij = dQi / dVj i, j are gate (g), drain (d), source (s), and bulk (b) 12. In paragraph 4, The characteristics of the above device are characterized by including a drain current (Id). Method for predicting device characteristics.

13. In paragraph 12, The step of pre-training the neural network model is characterized in that it includes a step of normalizing based on a value obtained by dividing the drain current (Id) by the channel width (W) / channel length (L) and taking the natural logarithm. Method for predicting device characteristics.

14. In paragraph 13, The above neural network model includes a second loss function that minimizes the error between the predicted value and the measured value of the drain current (Id), The second loss function is characterized in that it includes a first term obtained by log-transforming the predicted value and the measured value to handle errors in an exponential increase region of the drain current (Id) and a second term obtained by exponentially transforming the predicted value to handle errors in a linear increase region of the drain current (Id). Method for predicting device characteristics.

15. A computing device for predicting the characteristics of a device by inputting design parameters and bias conditions of the device, A processor comprising at least one core; A memory containing program codes executable by the processor; and network unit; Including, The above processor, A neural network model of an encoder-decoder structure is pre-trained based on pre-input data including element data of multiple technology nodes, an element vector is generated in the encoder based on first input data including element data of a target technology node, and a characteristic of the target element is predicted in the decoder based on the element vector and design parameters and bias conditions of the target element. Device characteristic prediction device.

16. In paragraph 15, The above design parameters include one or more of the channel width (W), channel length (L), or operating temperature (T) of the device, wherein the bias condition comprises at least one of a drain-source voltage, a gate-source voltage, or a bulk-source voltage of the device. Device characteristic prediction device.

17. In paragraph 16, wherein the first input data includes design parameters of the device of the target technology node and characteristics of the device measured under bias conditions. Device characteristic prediction device.

Images