Pixel circuit unit and display device

Abstract

A pixel circuit unit and a display device. The pixel circuit unit comprises a drive unit (102), a light-emitting unit (104), a first pulse width modulation unit (105) and a second pulse width modulation unit (106), wherein the drive unit (102) generates a drive current; the light-emitting unit (104) is connected to the drive unit (102) and emits light under the action of the drive current generated by the drive unit (102); the first pulse width modulation unit (105) is connected between the drive unit (102) and the light-emitting unit (104), and is turned on or turned off on the basis of a received light emission control signal (EM); and the second pulse width modulation unit (106) is separately connected to the drive unit (102) and the light-emitting unit (104), controls, on the basis of a received control signal (RS), the turning-on and turning-off of the drive unit (102), and cooperates with the first pulse width modulation unit (105) to regulate the light emission duration of the light-emitting unit (104). Therefore, the area consumed by a pixel circuit is reduced, the pixel density is increased, and the visual effect is improved.

Description

Pixel circuit unit and display device

[0001] The present application claims priority to the Chinese patent application No. 202411074810.1, filed on August 6, 2024, entitled “Pixel circuit unit and display device”, the whole content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the field of display, more particularly, to a pixel circuit unit and display device. BACKGROUND

[0003] In the circuit design of micro light emitting diode display (Micro LED), analog signal is used to modulate output current, and currently, digital-analog hybrid modulation method is mainly used.

[0004] Since low-voltage digital signal is difficult to control medium-voltage or high-voltage analog circuit, it is necessary to widen the voltage range to the required analog voltage through level conversion and the like, so that more transistors need to be introduced. For example, at least 4 medium-high voltage CMOS transistors are introduced in the level converter.

[0005] The introduction of more transistors leads to more area consumption of the pixel circuit, making it difficult to achieve the target pixels per inch (PPI), and affecting the picture effect. SUMMARY

[0006] The present application aims to provide a pixel circuit unit and display device to reduce the area consumption of the pixel circuit, improve the pixels per inch (PPI), and thus improve the picture effect.

[0007] In a first aspect, the present application provides a pixel circuit unit, comprising:

[0008] a driving unit for generating a driving current;

[0009] a light emitting unit connected to the driving unit and emitting light under the driving of the driving unit;

[0010] a first pulse width modulation unit connected between the driving unit and the light emitting unit and capable of conducting or not conducting according to a received light emitting control signal;

[0011] a second pulse width modulation unit connected to the driving unit, the second pulse width modulation unit controlling the driving unit to conduct or not conduct according to a received control signal, and cooperating with the first pulse width modulation unit to regulate the light emitting duration of the light emitting unit.

[0012] Optionally, the second pulse width modulation unit comprises a first end, a second end, a third end and a control end, the control end of the second pulse width modulation unit is configured to receive the control signal, the first end of the second pulse width modulation unit is configured to receive a reset signal, and the second end and the third end of the second pulse width modulation unit are electrically connected to the driving unit respectively;

[0013] When the first pulse width modulation unit is in the on state under the control of the light emission control signal, the second pulse width modulation unit can be turned on under the control of the control signal, and the driving unit can be initialized through the reset signal via the second end and the third end to control the on-off of the driving unit, thereby controlling the light emission duration of the light emitting unit.

[0014] Optionally, the second end is also connected to the light emitting unit to simultaneously initialize the driving unit and the light emitting unit, thereby realizing multiplexing of the second end.

[0015] Optionally, the second pulse width modulation unit comprises a first pulse width modulation sub-unit and a second pulse width modulation sub-unit, the control signal comprises a first control signal and a second control signal, and the reset signal comprises a first reset signal and a second reset signal.

[0016] The first pulse width modulation sub-unit comprises a control end, a first end and the second end, the control end of the first pulse width modulation sub-unit is configured to receive the first control signal, the first end of the first pulse width modulation sub-unit is configured to receive the first reset signal, and the second end of the first pulse width modulation sub-unit is electrically connected to the second end of the driving unit.

[0017] The second pulse width modulation sub-unit comprises a control end, a first end and the third end, the control end of the second pulse width modulation sub-unit is configured to receive the second control signal, the first end of the second pulse width modulation sub-unit is configured to receive the second reset signal, and the third end of the second pulse width modulation sub-unit is connected to the control end of the driving unit.

[0018] When the first pulse width modulation unit is in the on state under the control of the light emission control signal, the first pulse width modulation sub-unit is turned on under the control of the first control signal, the driving unit is initialized through the first reset signal via the second end, the second pulse width modulation sub-unit is turned on under the control of the second control signal, and the driving unit is initialized through the second reset signal via the third end, so as to control the on-off of the driving unit through the action of the two pulse width modulation sub-units to regulate the light emission duration of the light emitting unit.

[0019] Optionally, the second end of the first pulse width modulation sub-unit is connected to the second end of the driving unit via the first pulse width modulation unit.

[0020] The second end of the first pulse width modulation sub-unit is connected with the first end of the light emitting unit, and is connected with the second end of the driving unit through the first pulse width modulation unit, so as to simultaneously initialize the driving unit and the light emitting unit, and realize multiplexing of the second end.

[0021] Optionally, the reset signals of the first pulse width modulation sub-unit and the second pulse width modulation sub-unit are simultaneously received by the first pulse width modulation sub-unit and the second pulse width modulation sub-unit respectively when determining the on-off of the driving unit.

[0022] Optionally, the pixel circuit unit comprises a data writing unit and an energy storage unit.

[0023] The data writing unit comprises a control end, a first end and a second end, the control end of the data writing unit is used for receiving a scanning signal, the first end of the data writing unit is used for receiving a data signal, and the second end of the data writing unit is connected with the control end of the driving unit and the first end of the energy storage unit.

[0024] When the data writing unit is in a conduction state under the control of the scanning signal, the data signal is written into the energy storage unit.

[0025] Optionally, the light emitting control signal is a global signal or a local signal.

[0026] And / or, the control signal is a global signal or a local signal.

[0027] The global signal is shared by all sub-pixels in a pixel array, and the local signal is shared by part of the sub-pixels in the pixel array.

[0028] Optionally, in the initialization stage, the data writing unit is in a conduction state under the control of the scanning signal, so as to write a reference signal received by the first end of the data writing unit into the energy storage unit; the first pulse width modulation unit is in a conduction state under the control of the light emitting control signal, and the first pulse width modulation sub-unit is in a conduction state under the control of the first control signal, so as to initialize the first end of the light emitting unit and the second end of the driving unit through the first reset signal.

[0029] In the data writing stage, the data writing unit is in a conduction state under the control of the scanning signal, so as to write a data signal received by the first end of the data writing unit into the energy storage unit.

[0030] In the light emitting stage, the voltage difference between the two ends of the energy storage unit controls the driving unit to be in a conduction state, and the first pulse width modulation unit is in a conduction state under the control of the light emitting control signal, so as to control the light emitting unit to be in a working state.

[0031] In the waiting stage, the first pulse width modulation unit is in the on state under the control of the light emitting control signal, and the first pulse width modulation sub-unit is in the on state under the control of the first control signal, so as to initialize the first end of the light emitting unit and the second end of the driving unit through the first reset signal, and the second pulse width modulation sub-unit is in the on state under the control of the second control signal, so as to turn off the driving unit through the second reset signal.

[0032] Optionally, the data writing unit comprises a first NMOS transistor; a gate of the first NMOS transistor is used as a control end of the data writing unit, a drain of the first NMOS transistor is used as a first end of the data writing unit, and a source of the first NMOS transistor is used as a second end of the data writing unit.

[0033] The driving unit comprises a second NMOS transistor; a gate of the second NMOS transistor is used as a control end of the driving unit, a drain of the second NMOS transistor is used as a first end of the driving unit, and a source of the second NMOS transistor is used as a second end of the driving unit.

[0034] The first pulse width modulation unit comprises a third NMOS transistor; a gate of the third NMOS transistor is used as a control end of the first pulse width modulation unit, a drain of the third NMOS transistor is used as a first end of the first pulse width modulation unit, and a source of the third NMOS transistor is used as a second end of the first pulse width modulation unit.

[0035] Optionally, the first pulse width modulation sub-unit comprises a fourth NMOS transistor; a gate of the fourth NMOS transistor is used as a control end of the first pulse width modulation sub-unit, a drain of the fourth NMOS transistor is used as a first end of the first pulse width modulation sub-unit, and a source of the fourth NMOS transistor is used as a second end of the first pulse width modulation sub-unit.

[0036] The second pulse width modulation sub-unit comprises a fifth NMOS transistor; a gate of the fifth NMOS transistor is used as a control end of the second pulse width modulation sub-unit, a drain of the fifth NMOS transistor is used as a first end of the second pulse width modulation sub-unit, and a source of the fifth NMOS transistor is used as a second end of the second pulse width modulation sub-unit.

[0037] Optionally, the data writing unit comprises a first PMOS transistor; a gate of the first PMOS transistor is used as a control terminal of the data writing unit, a source of the first PMOS transistor is used as a first terminal of the data writing unit, and a drain of the first PMOS transistor is used as a second terminal of the data writing unit.

[0038] The driving unit comprises a second PMOS transistor; a gate of the second PMOS transistor is used as a control terminal of the driving unit, a source of the second PMOS transistor is used as a first terminal of the driving unit, and a drain of the second PMOS transistor is used as a second terminal of the driving unit.

[0039] The first pulse width modulation unit comprises a third PMOS transistor; a gate of the third PMOS transistor is used as a control terminal of the first pulse width modulation unit, a source of the third PMOS transistor is used as a first terminal of the first pulse width modulation unit, and a drain of the third PMOS transistor is used as a second terminal of the first pulse width modulation unit.

[0040] Optionally, the first pulse width modulation sub-unit comprises a fourth PMOS transistor; a gate of the fourth PMOS transistor is used as a control terminal of the first pulse width modulation sub-unit, a source of the fourth PMOS transistor is used as a first terminal of the first pulse width modulation sub-unit, and a drain of the fourth PMOS transistor is used as a second terminal of the first pulse width modulation sub-unit.

[0041] The second pulse width modulation sub-unit comprises a fifth PMOS transistor; a gate of the fifth PMOS transistor is used as a control terminal of the second pulse width modulation sub-unit, a source of the fifth PMOS transistor is used as a first terminal of the second pulse width modulation sub-unit, and a drain of the fifth PMOS transistor is used as a second terminal of the second pulse width modulation sub-unit.

[0042] Optionally, the data writing unit comprises a first CMOS transistor; a control terminal of the first CMOS transistor is used as a control terminal of the data writing unit, a high-level input terminal of the first CMOS transistor is used as a first terminal of the data writing unit, and an output terminal of the first CMOS transistor is used as a second terminal of the data writing unit.

[0043] The driving unit comprises a second CMOS transistor; a control terminal of the second CMOS transistor is used as a control terminal of the driving unit, a high-level input terminal of the second CMOS transistor is used as a first terminal of the driving unit, and an output terminal of the second CMOS transistor is used as a second terminal of the driving unit.

[0044] The first pulse width modulation unit comprises a third CMOS transistor, a control end of the third CMOS transistor serving as a control end of the first pulse width modulation unit, a high-level input end of the third CMOS transistor serving as a first end of the first pulse width modulation unit, and an output end of the third CMOS transistor serving as a second end of the first pulse width modulation unit.

[0045] Optionally, the first pulse width modulation sub-unit comprises a first NMOS transistor or a first PMOS transistor, and the second pulse width modulation sub-unit comprises a second NMOS transistor or a second PMOS transistor.

[0046] When the first pulse width modulation sub-unit comprises a first NMOS transistor, a gate of the first NMOS transistor serves as a control end of the first pulse width modulation sub-unit, a drain of the first NMOS transistor serves as a first end of the first pulse width modulation sub-unit, and a source of the first NMOS transistor serves as a second end of the first pulse width modulation sub-unit.

[0047] When the first pulse width modulation sub-unit comprises a first PMOS transistor, a gate of the first PMOS transistor serves as a control end of the first pulse width modulation sub-unit, a source of the first PMOS transistor serves as a first end of the first pulse width modulation sub-unit, and a drain of the first PMOS transistor serves as a second end of the first pulse width modulation sub-unit.

[0048] When the second pulse width modulation sub-unit comprises a second NMOS transistor, a gate of the second NMOS transistor serves as a control end of the second pulse width modulation sub-unit, a drain of the second NMOS transistor serves as a first end of the second pulse width modulation sub-unit, and a source of the second NMOS transistor serves as a second end of the second pulse width modulation sub-unit.

[0049] When the second pulse width modulation sub-unit comprises a second PMOS transistor, a gate of the second PMOS transistor serves as a control end of the second pulse width modulation sub-unit, a source of the second PMOS transistor serves as a first end of the second pulse width modulation sub-unit, and a drain of the second PMOS transistor serves as a second end of the second pulse width modulation sub-unit.

[0050] In a second aspect, the present application provides a display device comprising the pixel circuit unit.

[0051] The pixel circuit unit and the display device provided by the application comprise a driving unit, a light-emitting unit, a first pulse width modulation unit and a second pulse width modulation unit. The driving unit generates a driving current; the light-emitting unit is connected to the driving unit and emits light under the action of the driving current generated by the driving unit; the first pulse width modulation unit is connected between the driving unit and the light-emitting unit and can be turned on and off according to a received light-emitting control signal; the second pulse width modulation unit is connected to the driving unit and controls the driving unit to be turned on and off according to a received control signal, and cooperates with the first pulse width modulation unit to regulate the light-emitting duration of the light-emitting unit. The scheme of the application does not need to introduce more transistors, reduces the area consumed by the pixel circuit, improves the pixel density unit, and further improves the picture effect. BRIEF DESCRIPTION OF DRAWINGS

[0052] In order to more clearly illustrate the technical solutions of the application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are some embodiments of the application, and other drawings can also be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0053] Fig. 1 is a circuit schematic diagram of a pixel circuit provided by an embodiment;

[0054] Fig. 2 is a circuit schematic diagram of a pixel circuit provided by another embodiment;

[0055] Fig. 3 is a circuit schematic diagram of a pixel circuit provided by still another embodiment;

[0056] Fig. 4 is a circuit schematic diagram of a pixel circuit unit provided by an embodiment of the application;

[0057] Fig. 5 is a circuit schematic diagram of a pixel circuit unit provided by an embodiment of the application;

[0058] Fig. 6 is a circuit schematic diagram of a pixel circuit unit provided by another embodiment of the application;

[0059] Fig. 7 is a connection schematic diagram of a digital module and an analog part inside a sub-pixel provided by an embodiment of the application;

[0060] Fig. 8 is a sub-pixel signal equivalent schematic diagram provided by an embodiment of the application;

[0061] Fig. 9 is a pixel schematic diagram of 2x2 arrangement provided by an embodiment of the application;

[0062] Fig. 10 is a sub-pixel signal equivalent schematic diagram of 2x2 array provided by an embodiment of the application;

[0063] Fig. 11 is a circuit schematic diagram of a pixel circuit unit provided by still another embodiment of the application;

[0064] FIG. 12 is a timing diagram of a pixel circuit unit according to an embodiment of the present application;

[0065] FIG. 13 is a timing diagram of a pixel circuit unit according to another embodiment of the present application;

[0066] FIG. 14 is a circuit schematic diagram of another pixel circuit unit according to an embodiment of the present application;

[0067] FIG. 15 is a timing diagram of another pixel circuit unit according to an embodiment of the present application. DETAILED DESCRIPTION

[0068] In order to make the objects, technical solutions and advantages of the present application clearer, the technical solutions in the present application will be described clearly and completely below with reference to the drawings in the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0069] FIG. 1 shows a circuit schematic diagram of a 2T1C pixel circuit, as shown in FIG. 1, the 2T1C pixel circuit includes two transistors, one capacitor and a light emitting element, for example, including a first NMOS transistor T1, a second NMOS transistor T2, a capacitor Cst and a micro light emitting diode Micro LED.

[0070] The gate of the first NMOS transistor T1 receives a scan signal SC, the drain of the first NMOS transistor T1 receives a data signal Data, and the source of the first NMOS transistor T1 is connected to the gate of the second NMOS transistor T2 and the first end of the capacitor Cst; the drain of the second NMOS transistor T2 receives a power supply voltage VDD, the source of the second NMOS transistor T2 is connected to the second end of the capacitor Cst and the anode of the micro light emitting diode Micro LED, and the cathode of the micro light emitting diode Micro LED receives a ground voltage VSS.

[0071] When displaying, the first NMOS transistor T1 is turned on under the control of the scanning signal SC, and the data signal Data received by the drain of the first NMOS transistor T1 passes through the first NMOS transistor T1 and enters the gate of the second NMOS transistor T2 and the storage capacitor Cst. Then, the first NMOS transistor T1 is turned off under the control of the scanning signal SC, and due to the storage effect of the storage capacitor Cst, the gate voltage of the second NMOS transistor T2 can still continue to maintain the data signal voltage, so that the second NMOS transistor T2 is in a turned-on state, thereby enabling the power supply voltage VDD received by the drain of the second NMOS transistor T2 to continuously provide a driving current to the micro light emitting diode Micro LED.

[0072] In some examples, when the display panel is in operation, the pulse width of the driving current of the light emitting element can be adjusted by a pulse-width modulation (PWM) mode, so that each light emitting element exhibits different color steps to display different pictures.

[0073] Correspondingly, in the micro light emitting diode circuit design, a digital-analog hybrid modulation mode can be used to adjust the pulse width of the driving current of the micro light emitting diode. For example, an analog pixel circuit and a digital pixel circuit are adopted, the analog pixel circuit has the same circuit structure as the pixel circuit, the analog pixel circuit mainly generates a required current value, and the digital pixel circuit controls the current width of the analog pixel circuit according to the gray scale requirement. The digital pixel circuit generally controls the branch in which the analog pixel circuit generates the required current, for example, by adding a tube, multiple tubes or other ways in the analog pixel circuit, to control the on-off of the current.

[0074] As shown in FIG. 2, a third NMOS transistor T3 is added in the analog pixel circuit, the gate of the third NMOS transistor T3 receives a light emitting control signal EM, the drain of the third NMOS transistor T3 is connected to the source of the second NMOS transistor T2, and the source of the third NMOS transistor T3 is connected to the anode of the micro light emitting diode Micro LED. When the third NMOS transistor T3 is turned on under the control of the light emitting control signal EM, the power supply voltage VDD received by the drain of the second NMOS transistor T2 can provide a driving current to the micro light emitting diode Micro LED.

[0075] However, since the analog pixel circuit is a medium-high voltage process, the driving voltage required by the first NMOS transistor and the third NMOS transistor is greater than 1V, and the low-voltage digital signal 1 / 0 cannot directly drive the third NMOS transistor T3. For example, if the cross-voltage required by the third NMOS transistor T3 to output the target driving current is greater than 1V, and the digital signal received by the gate of the third NMOS transistor T3 changes at a rate of 0V-1V, the third NMOS transistor T3 cannot be controlled to turn on and output the target driving current (for example, a current in the order of nanoamperes to microamperes). For another example, the pixel circuit needs to achieve a voltage of 0-1.2V to achieve the target driving current in the anode part of the micro light emitting diode. At this time, if the light emitting control signal is 1 / 0, the anode voltage of the micro light emitting diode is less than 1V-Vth (threshold voltage of the third NMOS transistor), so the anode voltage cannot be maximized to 1.2V.

[0076] In some examples, the digital signal can be expanded to the required cross-voltage by a level conversion circuit or the like. As shown in FIG. 3, when the digital module outputs the digital signal 1 / 0, the digital signal is converted into a medium-high voltage signal by a level converter to control the third NMOS transistor T3 to turn on.

[0077] However, a large number of transistors will be introduced in the level converter, for example, at least four medium-high voltage CMOS transistors will be introduced. This will cause the pixel circuit to occupy more area, and it is impossible to achieve a high pixel density unit, which affects the picture effect.

[0078] In addition, if the transistors in the analog pixel circuit are NMOS transistors, if PMOS transistors are introduced in the level converter, the voltage domains of the level converter and the analog pixel circuit are inconsistent, and at least two deep N-well (DNW) voltage domains will be introduced. The spacing between the two deep N-wells is at least in the order of microns in the existing process, which also limits the area.

[0079] To solve the above problems, the present application provides a pixel circuit unit, which comprises a second pulse width modulation unit. The second pulse width modulation unit controls the on-off of the driving unit according to the received control signal, and cooperates with the first pulse width modulation unit to regulate the light emitting time length of the light emitting unit. Without introducing a large number of transistors, the area consumed by the pixel circuit is reduced, the pixel unit density is improved, and the picture effect is improved.

[0080] The technical solutions of the present application will be described in detail below with specific examples. The following specific examples can be combined with each other, and the same or similar concepts or processes may not be described in detail in some examples.

[0081] Figure 4 shows a circuit schematic of a pixel circuit unit according to an embodiment of the present application. As shown in Figure 4, the pixel circuit unit according to the embodiment of the present application comprises a driving unit 102, a light emitting unit 104, a first pulse width modulation unit 105, and a second pulse width modulation unit 106.

[0082] The driving unit 102 generates a driving current.

[0083] The light emitting unit 104 is connected to the driving unit 102 and emits light under the driving of the driving unit 102.

[0084] The first pulse width modulation unit 105 is connected between the driving unit 102 and the light emitting unit 104, and can be turned on and off according to a received light emitting control signal EM.

[0085] The second pulse width modulation unit 106 is connected to the driving unit 102, and controls the driving unit 102 to be turned on and off according to a received control signal RS, and cooperates with the first pulse width modulation unit 105 to regulate the light emitting time of the light emitting unit 104.

[0086] The driving current refers to the current of the branch in which the driving unit 102, the first pulse width modulation unit 105, and the light emitting unit 104 are located, and can also be understood as the current that drives the light emitting unit 104 to be in a working state (light emitting).

[0087] It can be understood that, in a frame of picture, the start of the pulse width is the start time when the first pulse width modulation unit 105 is in a conductive state under the control of the light emitting control signal EM. The end of the pulse width is the start time when the second pulse width modulation unit 106 is in a conductive state under the control of the control signal RS. Therefore, different pulse widths can be formed by controlling the conduction time of the second pulse width modulation unit 106, so as to realize different gray scales. For example, after the first pulse width modulation unit 105 is in a conductive state for a preset time under the control of the light emitting control signal EM, the second pulse width modulation unit 106 is turned on under the control of the control signal RS, and then the pulse width is the preset time.

[0088] In some embodiments, as shown in FIG. 4, the second pulse width modulation unit 106 includes a first end, a second end, a third end, and a control end. The control end of the second pulse width modulation unit 106 is configured to receive a control signal RS, the first end of the second pulse width modulation unit 106 is configured to receive a reset signal, and the second end and the third end of the second pulse width modulation unit 106 are electrically connected to the driving unit 102. When the first pulse width modulation unit 105 is in the on state under the control of the light emission control signal EM, the second pulse width modulation unit 106 can be turned on under the control of the control signal RS, and the driving unit 102 can be initialized through the second end and the third end by the reset signal Reset, so as to control the on-off of the driving unit 102, and further control the light emission duration of the light emitting unit 104.

[0089] For example, the driving unit 102 includes a first end, a second end, and a control end, the second end of the second pulse width modulation unit 106 is connected to the second end of the driving unit 102, and the third end of the second pulse width modulation unit 106 is connected to the control end of the driving unit 102. Therefore, when the second pulse width modulation unit 106 is turned on under the control of the control signal RS, the driving unit 102 can be initialized by the reset signal Reset, so as to control the on-off of the driving unit 102, and further control the light emission duration of the light emitting unit 104. The first end of the driving unit 102 is configured to receive a power supply voltage VDD, so as to provide the required driving current for the light emitting unit 104.

[0090] Correspondingly, the first pulse width modulation unit 105 includes a first end, a second end, and a control end. The control end of the first pulse width modulation unit 105 is configured to receive a light emission control signal EM, the first end of the first pulse width modulation unit 105 is connected to the second end of the driving unit 102, and the second end of the light emitting unit 104 can receive a ground voltage VSS. The first pulse width modulation unit 105 can be in the on state under the control of the light emission control signal EM.

[0091] In some embodiments, the second end of the second pulse width modulation unit 106 is further connected to the light emitting unit 104, so as to simultaneously initialize the driving unit 102 and the light emitting unit 104, and realize the multiplexing of the second end of the second pulse width modulation unit 105. When the second pulse width modulation unit 106 is turned on under the control of the control signal RS, the driving unit 102 and the light emitting unit 104 can be initialized by the reset signal Reset, so as to accelerate the turn-off speed of the light emitting unit 104, thereby being able to quickly turn off the main branch current, and further realizing the high contrast of each frame of picture. For example, the second end of the second pulse width modulation unit 106 is further connected to the first end of the light emitting unit 104.

[0092] In some examples, as shown in FIG. 6, the second pulse width modulation unit 106 includes a first pulse width modulation sub-unit 1061 and a second pulse width modulation sub-unit 1062, the control signal RS includes a first control signal RS1 and a second control signal RS2, and the reset signal Reset includes a first reset signal Reset1 and a second reset signal Reset2.

[0093] The first pulse width modulation sub-unit 1061 includes a control terminal, a first terminal, and a second terminal of the second pulse width modulation unit 106. The control terminal of the first pulse width modulation sub-unit 1061 is configured to receive the first control signal RS1, the first terminal of the first pulse width modulation sub-unit 1061 is configured to receive the first reset signal Reset1, and the second terminal of the first pulse width modulation sub-unit 1061 is electrically connected to the second terminal of the driving unit 102. The second pulse width modulation sub-unit 1062 includes a control terminal, a first terminal, and a second pulse width modulation unit 106. The control terminal of the second pulse width modulation sub-unit 1062 is configured to receive the second control signal RS2, the first terminal of the second pulse width modulation sub-unit 1062 is configured to receive the second reset signal Reset2, and the third terminal of the second pulse width modulation sub-unit 1062 is electrically connected to the control terminal of the driving unit 102.

[0094] Therefore, when the first pulse width modulation unit 105 is in the on state under the control of the light-emitting control signal EM, the first pulse width modulation sub-unit 1061 can be turned on under the control of the first control signal RS1 and initialize the driving unit 102 through the first reset signal Reset1 via the second terminal of the first pulse width modulation unit 106, and the second pulse width modulation sub-unit 1062 can be turned on under the control of the second control signal RS2 and initialize the driving unit 102 through the second reset signal Reset2 via the third terminal of the second pulse width modulation unit 106, so as to control the driving unit 102 to be turned off through the actions of the two pulse width modulation sub-units, thereby regulating the light-emitting duration of the light-emitting unit 104.

[0095] Specifically, the first pulse width modulation subunit 1061 comprises a control end, a first end and a second end. The control end of the first pulse width modulation subunit 1061 serves as the control end of the second pulse width modulation unit 106, and is configured to receive the first control signal RS1. The first end of the first pulse width modulation subunit 1061 serves as the first end of the second pulse width modulation unit 106, and is configured to receive the first reset signal Reset1. The second end of the first pulse width modulation subunit 1061 serves as the second end of the second pulse width modulation unit 106, and is electrically connected to the second end of the driving unit 102. The second pulse width modulation subunit 1062 comprises a control end, a first end and a second end. The control end of the second pulse width modulation subunit 1062 serves as the control end of the second pulse width modulation unit 106, and is configured to receive the second control signal RS2. The first end of the second pulse width modulation subunit 1062 serves as the first end of the second pulse width modulation unit 106, and is configured to receive the second reset signal Reset2. The second end of the second pulse width modulation subunit 1062 serves as the third end of the second pulse width modulation unit 106, and is connected to the control end of the driving unit 102.

[0096] In some examples, the second end of the first pulse width modulation subunit 1061 is connected to the second end of the driving unit 102 through the first pulse width modulation unit 105. For example, the second end of the first pulse width modulation subunit 1061 is connected to the first end of the first pulse width modulation unit 105.

[0097] In other examples, the second end of the first pulse width modulation subunit 1061 is connected to the first end of the light emitting unit 104, and is connected to the second end of the driving unit 102 through the first pulse width modulation unit 105, so as to simultaneously initialize the driving unit 102 and the light emitting unit 104, and realize multiplexing of the second end.

[0098] It should be noted that when the driving unit 102 is turned off, the light emitting unit 104 is theoretically also turned off. In order to improve the turn-off speed of the light emitting unit 104, the second end of the first pulse width modulation subunit 1061 is connected to the first end of the light emitting unit 104, so as to initialize the first end of the light emitting unit 104 through the first reset signal Reset1, thereby accelerating the turn-off speed of the light emitting unit 104.

[0099] In yet other examples, the reset signals of the first pulse width modulation subunit 1061 and the second pulse width modulation subunit 1062 are used to determine the on-off of the driving unit 102. The first pulse width modulation subunit 1061 and the second pulse width modulation subunit 1062 simultaneously receive the first control signal RS1 and the second control signal RS2 respectively, so that the first reset signal Reset1 and the second reset signal Reset2 simultaneously act on the driving unit 102 and the light emitting unit 104 respectively, and thus the driving unit 102 and the light emitting unit 104 can be simultaneously turned off.

[0100] In other examples, the first pulse width modulation subunit 1061 and the second pulse width modulation subunit 1062 can also receive the first control signal RS1 and the second control signal RS2 respectively in time division. For example, the first pulse width modulation subunit 1061 can receive the first control signal RS1 first, and the second pulse width modulation subunit 1062 can receive the second control signal RS2 later. For another example, the second pulse width modulation subunit 1062 can receive the second control signal RS2 first, and the first pulse width modulation subunit 1061 can receive the first control signal RS1 later.

[0101] In some embodiments, as shown in FIGS. 5 and 6, the pixel circuit unit further includes a data writing unit 101 and an energy storage unit 103. The control end of the data writing unit 101 receives a scanning signal SC, the first end of the data writing unit 101 receives a data signal Data, and the second end of the data writing unit 101 is connected to the control end of the driving unit 102 and the first end of the energy storage unit 103. The data writing unit 101 writes the data signal Data into the energy storage unit 103 when it is in a conductive state under the control of the scanning signal SC.

[0102] In some embodiments, as shown in FIGS. 7 and 8, FIG. 7 is a schematic diagram of the connection between the digital module and the analog part inside the sub-pixel, and FIG. 8 is a schematic diagram of the signal equivalence of the sub-pixel, the pixel circuit unit further includes a digital control module 201, and the output end of the digital control module 201 is used to output a control signal RS. For example, the digital control module 201 includes an input end, a control end, a first output end, and a second output end. The input end of the digital control module 201 is used to receive a digital signal R, the control end of the digital control module 201 is used to receive a digital enable signal C, and the digital control module 201 generates a first control signal RS1 and a second control signal RS2 according to the digital signal R under the control of the digital enable signal C, and outputs the first control signal RS1 through the first output end and outputs the second control signal RS2 through the second output end. The first output end of the digital control module 201 can be connected to the control end of the first pulse width modulation subunit 1061, and the second output end of the digital control module 201 can be connected to the control end of the second pulse width modulation subunit 1062.

[0103] In addition, the data writing unit 101, the driving unit 102, the energy storage unit 103, the first pulse width modulation unit 105, and the second pulse width modulation unit 106 can be equivalent to an analog module 202. The first end of the analog module 202 is used to receive an analog input signal, such as a power supply voltage VDD; the second end of the analog module 202 is connected to the first end of the light emitting unit 104, and the control end of the analog module 202 is used to receive an analog opening signal, such as a light emitting control signal EM. In practical applications, the light emitting control signal EM and the control signal RS can be global or local. Global means that all pixels in the array share, and local means that part of the pixels share.

[0104] For example, as shown in FIG. 9, FIG. 9 shows a pixel schematic diagram of a 2x2 array, the first pulse width modulation unit 105 in each sub-pixel receives the same light-emitting control signal EM and control signal RS (for example, the first control signal RS1 and the second control signal RS2). In addition, each sub-pixel can have a corresponding digital control module 201, the digital control modules 201 in the same column receive the same digital enable signal, the digital control modules 201 in the same row receive the same digital signal, for example, the digital control modules 201 in the first column receive the digital enable signal C_1, the digital control modules 201 in the second column receive the digital enable signal C_2, the digital control modules 201 in the first row receive the digital signal R_1, and the digital control modules 201 in the second row receive the digital signal R_2. As shown in FIG. 10, FIG. 10 shows a sub-pixel signal equivalent schematic diagram of a 2x2 array, each sub-pixel has a corresponding digital control module 201 and analog module 202, each analog module 202 has a corresponding analog enable signal, for example, the analog module 202 of the sub-pixel in the first row and the first column receives the analog enable signal EM1, the analog module 202 of the sub-pixel in the first row and the second column receives the analog enable signal EM2, the analog module 202 of the sub-pixel in the second row and the first column receives the analog enable signal EM3, and the analog module 202 of the sub-pixel in the second row and the second column receives the analog enable signal EM4. In the case of receiving the same light-emitting control signal EM and control signal RS at each sub-pixel, the local sub-pixel operation can be controlled by the analog enable signal.

[0105] The working state of the pixel circuit unit provided by the embodiment in a frame of picture can include four stages, an initialization stage, a data writing stage, a light-emitting stage, and a waiting stage.

[0106] In the initialization stage, the data writing unit 101 is in a conductive state under the control of the scanning signal SC, so as to write the reference signal received by the first end of the data writing unit 101 into the energy storage unit 103; the first pulse width modulation unit 105 is in a conductive state under the control of the light-emitting control signal EM, and the first pulse width modulation sub-unit 1061 is in a conductive state under the control of the first control signal RS1, so that the first reset signal Reset1 received by the first end of the first pulse width modulation sub-unit 1061 can be transmitted to the first end of the light-emitting unit 104 through the first pulse width modulation sub-unit 1061, and then transmitted to the second end of the driving unit 102 through the first pulse width modulation unit 105, thereby enabling the first end of the light-emitting unit 104 and the second end of the driving unit 102 to be initialized.

[0107] In the data writing stage, the data writing unit 101 is in a conductive state under the control of the scanning signal SC, so as to write the data signal received by the first end of the data writing unit 101 into the energy storage unit 103.

[0108] In the light-emitting stage, the voltage difference across the energy storage unit 103 controls the driving unit 102 to be in the on state, and the first pulse width modulation unit 105 is controlled by the light-emitting control signal EM to be in the on state, so that the power supply voltage VDD received by the first end of the driving unit 102 can provide a driving current for the light-emitting unit 104, so that the light-emitting unit 104 is in the working state.

[0109] In the waiting stage, the first pulse width modulation unit 105 is controlled by the light-emitting control signal EM to be in the on state, and the second pulse width modulation sub-unit 1062 is controlled by the second control signal RS2 to be in the on state, so that the second reset signal Reset2 received by the first end of the second pulse width modulation sub-unit 1062 is transmitted to the control end of the driving unit 102 through the second pulse width modulation sub-unit 1062, thereby turning off the driving unit 102 through the second reset signal Reset2. At the same time, the first pulse width modulation sub-unit 1061 is controlled by the first control signal RS1 to be in the on state, and the first reset signal Reset1 received by the first end of the first pulse width modulation sub-unit 1061 is transmitted to the first end of the light-emitting unit 104 through the first pulse width modulation sub-unit 1061, and is transmitted to the second end of the driving unit 102 through the first pulse width modulation unit 105, thereby initializing the first end of the light-emitting unit 104 and the second end of the driving unit 102 through the first reset signal, thereby quickly turning off the light-emitting unit 104. At this time, the pulse width of the driving current can be controlled.

[0110] In actual application, the energy storage unit 103 includes a capacitor Cst, the first end of the capacitor Cst is the first end of the energy storage unit 103, and the second end of the capacitor Cst is the second end of the energy storage unit 103. The light-emitting unit 104 includes a micro light-emitting diode Micro LED, the anode of the micro light-emitting diode Micro LED is the anode of the light-emitting unit 104, the cathode of the micro light-emitting diode Micro LED is the cathode of the light-emitting unit 104, and the number of the micro light-emitting diode Micro LED can be multiple.

[0111] In some examples, as shown in FIGS. 5-7, the second end of the energy storage unit 103 is connected to the second end of the driving unit 102, and the data writing unit 101 includes a first NMOS transistor T1, the driving unit 102 includes a second NMOS transistor T2, and the first pulse width modulation unit 105 includes a third NMOS transistor T3, so that when the first NMOS transistor T1 is turned off, the second NMOS transistor T2 can be controlled to be turned on by the energy storage unit 103, thereby ensuring that the power supply voltage VDD can provide a driving current for the light-emitting unit 104.

[0112] The gate of the first NMOS transistor T1 is the control terminal of the data writing unit 101, and receives a scanning signal SC; the drain of the first NMOS transistor T1 is the first terminal of the data writing unit 101, and receives a data signal Data; and the source of the first NMOS transistor T1 is the second terminal of the data writing unit 101, and is connected to the control terminal of the driving unit 102.

[0113] The gate of the second NMOS transistor T2 is the control terminal of the driving unit 102, and is connected to the second terminal of the data writing unit 101, the first terminal of the energy storage unit 103, and the second terminal of the second pulse width modulation sub-unit 1062; the drain of the second NMOS transistor T2 is the first terminal of the driving unit 102, and receives a power supply voltage VDD; and the source of the second NMOS transistor T2 is the second terminal of the driving unit 102, and is connected to the second terminal of the energy storage unit 103 and the first terminal of the first pulse width modulation unit 105.

[0114] The gate of the third NMOS transistor T3 is the control terminal of the first pulse width modulation unit 105, and receives a light-emitting control signal EM; the drain of the third NMOS transistor T3 is the first terminal of the first pulse width modulation unit 105, and is connected to the second terminal of the energy storage unit 103 and the second terminal of the driving unit 102; and the source of the third NMOS transistor T3 is the second terminal of the first pulse width modulation unit 105, and is connected to the second terminal of the first pulse width modulation sub-unit 1061 and the first terminal of the light-emitting unit 104.

[0115] In consideration of the fact that, when the pixel circuit is a pure NMOS transistor circuit, the introduction of a PMOS transistor will introduce a deep N-well (DNW) voltage domain, resulting in a large area occupied by the pixel circuit, in the present embodiment, the first pulse width modulation sub-unit 1061 and the second pulse width modulation sub-unit 1062 are NMOS transistors, so as to reduce the area occupied by the pixel circuit.

[0116] Specifically, as shown in FIG. 6 and FIG. 11, the first pulse width modulation sub-unit 1061 includes a fourth NMOS transistor T4, the gate of the fourth NMOS transistor T4 is the control terminal of the first pulse width modulation sub-unit 1061, and receives a first control signal RS1; the drain of the fourth NMOS transistor T4 is the first terminal of the first pulse width modulation sub-unit 1061, and receives a first reset signal Reset1; and the source of the fourth NMOS transistor T4 is the second terminal of the first pulse width modulation sub-unit 1061, and is connected to the first terminal of the light-emitting unit 104 and the second terminal of the first pulse width modulation unit 105.

[0117] The second pulse width modulation subunit 1062 comprises a fifth NMOS transistor T5, a gate of the fifth NMOS transistor T5 serving as a control terminal of the second pulse width modulation subunit 1062 and receiving a second control signal RS2; a drain of the fifth NMOS transistor T5 serving as a first terminal of the second pulse width modulation subunit 1062 and receiving a second reset signal Reset2; and a source of the fifth NMOS transistor T5 serving as a second terminal of the second pulse width modulation subunit 1062 and being connected to a control terminal of the driving unit 102, a second terminal of the data writing unit 101 and a first terminal of the energy storage unit 103.

[0118] FIG. 12 shows a timing diagram when the transistors included in the pixel circuit unit are pure NMOS transistors. As shown in FIG. 12, the working state of the pixel circuit unit in each frame can include an initialization phase, a data writing phase, an emitting phase and a waiting phase.

[0119] In the initialization phase, the first control signal RS1 is a high-level signal, the fourth NMOS transistor T4 is turned on under the control of the first control signal RS1, and the emitting control signal EM is a high-level signal, the third NMOS transistor T3 is turned on under the control of the emitting control signal EM, so that the first terminal of the emitting unit 104, the second terminal of the energy storage unit 103 and the second terminal of the driving unit 102 can be initialized by the first reset signal Reset1. At the same time, the second control signal RS2 is a low-level signal, the fifth NMOS transistor T5 is turned off under the control of the second control signal RS2, the scanning signal SC is a high-level signal, the first NMOS transistor T1 is turned on under the control of the scanning signal SC, and at this time the drain of the first NMOS transistor T1 receives the reference signal, so that the reference signal is written into the energy storage unit 103, and the initialization of the energy storage unit 103 is realized. It should be noted that the voltage difference between the two terminals of the energy storage unit 103 is the voltage difference between the reference signal and the first reset signal Reset1, which cannot control the second NMOS transistor T2 to be turned on, so that the initialization of the two terminals of the energy storage unit 103 and the first terminal of the emitting unit 104 is realized.

[0120] In the data writing phase, the first control signal RS1 is a low-level signal, the fourth NMOS transistor T4 is turned off under the control of the first control signal RS1, the second control signal RS2 is a low-level signal, the fifth NMOS transistor T5 is turned off under the control of the second control signal RS2, and the emitting control signal EM is also a low-level signal, the third NMOS transistor T3 is turned off under the control of the emitting control signal EM. At the same time, the scanning signal SC is a high-level signal, the first NMOS transistor T1 is turned on under the control of the scanning signal SC, and at this time the drain of the first NMOS transistor T1 receives the data signal Data, so that the data signal Data is written into the energy storage unit 103.

[0121] In the light emitting stage, the first control signal RS1 is a low level signal, the fourth NMOS transistor T4 is turned off under the control of the first control signal RS1, the second control signal RS2 is a low level signal, the fifth NMOS transistor T5 is turned off under the control of the second control signal RS2, the scanning signal SC is a low level signal, and the first NMOS transistor T1 is turned off under the control of the scanning signal SC. At the same time, the light emitting control signal EM is a high level signal, the third NMOS transistor T3 is turned on under the control of the light emitting control signal EM, and the second NMOS transistor T2 is turned on due to the voltage difference between the energy storage unit 103 being the voltage difference between the data signal Data and the first reset signal Reset1, so that the driving current I_Micro_LED for the light emitting unit 104 is provided by the power supply voltage received by the drain of the second NMOS transistor T2, so that the light emitting unit 104 is in a working state.

[0122] In the waiting stage, the light emitting control signal EM continues to be a high level signal, the third NMOS transistor T3 is turned on under the control of the light emitting control signal EM, the first control signal RS1 is a high level signal, and the fourth NMOS transistor T4 is turned on under the control of the first control signal RS1, so that the first end of the light emitting unit 104 and the source of the second NMOS transistor T2 are initialized by the first reset signal Reset1 received by the drain of the fourth NMOS transistor T4. And the second control signal RS2 is a high level signal, and the fifth NMOS transistor T5 is turned on under the control of the second control signal RS2, so that the gate of the second NMOS transistor T2 is initialized by the second reset signal Reset2 received by the drain of the fifth NMOS transistor T5 to turn off the second NMOS transistor T2. In addition, since the third NMOS transistor T3 and the fourth NMOS transistor T4 are in the on state, the discharge part of the energy storage unit 103 can be led away through the third NMOS transistor T3 and the fourth NMOS transistor T4.

[0123] It can be understood that the pulse width of the driving current can be controlled by the third NMOS transistor T3, the fourth NMOS transistor T4 and the fifth NMOS transistor T5. As shown in FIG. 7, a pixel circuit can have different pulse widths in different frames. Specifically, by controlling the conduction time of the fourth NMOS transistor T4 and the fifth NMOS transistor T5, different pulse widths can be achieved in different frames to realize different gray scales.

[0124] In the above embodiment, the first control signal RS1, the second control signal RS2 and the light-emitting control signal EM can be digital signals of 1 / 0V, the high-level signals corresponding to the first control signal RS1, the second control signal RS2 and the light-emitting control signal EM can be digital signals of 1V, and the low-level signals corresponding to the first control signal RS1, the second control signal RS2 and the light-emitting control signal EM can be digital signals of 0V. The high-level signal corresponding to the scanning signal SC can be a signal greater than 1V. Correspondingly, the first reset signal Reset1 can be 0V-(1-Vth_T4), Vth_T4 being the threshold voltage of the fourth NMOS transistor T4, and the second reset signal Reset2 can be less than the sum of the first reset signal Reset1 and the threshold voltage Vth_T5 of the fifth NMOS transistor T5, i.e., Reset2<Reset1+Vth_T5, so as to turn off the fifth NMOS transistor T5.

[0125] For the pixel circuits of the same frame or the same pixel circuit in different frames, the conduction time of the fourth NMOS transistor T4 and the fifth NMOS transistor T5 can be controlled, so that different frames have different pulse widths, and different gray scales are achieved. FIG. 13 shows a timing diagram of the pixel circuits of two rows of pixels in two frames. As shown in FIG. 13, the driving current I_Micro_LED_1 of the first pixel circuit in the first frame has a pulse width L1, the driving current I_Micro_LED_1 of the first pixel circuit in the second frame has a pulse width L2, the driving current I_Micro_LED_2 of the second pixel circuit in the first frame has a pulse width L3, and the driving current I_Micro_LED_2 of the second pixel circuit in the second frame has a pulse width L4.

[0126] In other examples, as shown in FIG. 14, the second end of the energy storage unit 103 is connected to the first end of the driving unit 102, the data writing unit 101 includes a first PMOS transistor T10, the driving unit 102 includes a second PMOS transistor T20, and the first pulse width modulation unit 105 includes a third PMOS transistor T30, so that when the first PMOS transistor is turned off, the second PMOS transistor T20 is controlled to be turned on by the energy storage unit 103, and the power supply voltage VDD can provide a driving current for the light-emitting unit 104.

[0127] The gate of the first PMOS transistor T10 serves as the control end of the data writing unit 101 and receives the scanning signal SC; the source of the first PMOS transistor T10 serves as the first end of the data writing unit 101 and receives the data signal Data; and the drain of the first PMOS transistor T10 serves as the second end of the data writing unit 101 and is connected to the control end of the driving unit 102.

[0128] The gate of the second PMOS transistor T20 is connected to the second end of the data writing unit 101, the first end of the energy storage unit 103 and the second end of the second pulse width modulation subunit 1062 as the control end of the driving unit 102; the source of the second PMOS transistor T20 is connected to the second end of the energy storage unit 103 and receives a power supply voltage as the first end of the driving unit 102; and the drain of the second PMOS transistor T20 is connected to the first end of the first pulse width modulation unit 105 as the second end of the driving unit 102.

[0129] The gate of the third PMOS transistor T30 receives a light-emitting control signal EM as the control end of the first pulse width modulation unit 105; the source of the third PMOS transistor T30 is connected to the second end of the driving unit 102 as the first end of the first pulse width modulation unit 105; and the drain of the third PMOS transistor T30 is connected to the first end of the light-emitting unit 104 as the second end of the first pulse width modulation unit 105.

[0130] In consideration of the fact that the pixel circuit is a pure PMOS transistor circuit, if a CMOS transistor is introduced, the potential of the PMOS substrate is different from the potential of the P substrate of the CMOS, which will introduce a deep N well voltage domain, occupying a large area of the pixel circuit. Therefore, in the embodiment, the first pulse width modulation subunit 1061 and the second pulse width modulation subunit 1062 are PMOS transistors, so as to reduce the area occupied by the pixel circuit.

[0131] Specifically, as shown in FIG. 14, the first pulse width modulation subunit 1061 includes a fourth PMOS transistor T40, the gate of the fourth PMOS transistor T40 receives a first control signal RS1 as the control end of the first pulse width modulation subunit 1061; the source of the fourth PMOS transistor T40 receives a first reset signal Reset1 as the first end of the first pulse width modulation subunit 1061; and the drain of the fourth PMOS transistor T40 is connected to the first end of the light-emitting unit 104 and the second end of the first pulse width modulation unit 105 as the second end of the first pulse width modulation subunit 1061.

[0132] The second pulse width modulation subunit 1062 includes a fifth PMOS transistor T50, the gate of the fifth PMOS transistor T50 receives a second control signal RS2 as the control end of the second pulse width modulation subunit 1062; the source of the fifth PMOS transistor T50 receives a second reset signal Reset2 as the first end of the second pulse width modulation subunit 1062; and the drain of the fifth PMOS transistor T50 is connected to the control end of the driving unit 102, the second end of the data writing unit 101 and the first end of the energy storage unit 103 as the second end of the second pulse width modulation subunit 1062.

[0133] Fig. 15 shows a timing diagram when the transistors included in the pixel circuit unit are pure PMOS transistors. As shown in Fig. 15, the working state of the pixel circuit unit in each frame can include an initialization phase, a data writing phase, an emitting phase and a waiting phase.

[0134] In the initialization phase, the first control signal RS1 is a low-level signal, the fourth PMOS transistor T40 is turned on under the control of the first control signal RS1, and the emitting control signal EM is a low-level signal, the third PMOS transistor T30 is turned on under the control of the emitting control signal EM, so that the first end of the emitting unit 104 and the second end of the driving unit 102 can be initialized by the first reset signal Reset1. At the same time, the second control signal RS2 is a high-level signal, the fifth PMOS transistor T50 is turned off under the control of the second control signal RS2, the scanning signal SC is a low-level signal, the first PMOS transistor T10 is turned on under the control of the scanning signal SC, and at this time the source of the first PMOS transistor T10 receives the reference signal, so as to write the reference signal into the energy storage unit 103 and realize the initialization of the energy storage unit 103. It should be noted that the voltage difference between the two ends of the energy storage unit 103 is the voltage difference between the power supply voltage VDD and the reference signal, and the second PMOS transistor T20 cannot be turned on.

[0135] In the data writing phase, the first control signal RS1 is a high-level signal, the fourth PMOS transistor T40 is turned off under the control of the first control signal RS1, the second control signal RS2 is a high-level signal, the fifth PMOS transistor T50 is turned off under the control of the second control signal RS2, and the emitting control signal EM is also a high-level signal, the third PMOS transistor T30 is turned off under the control of the emitting control signal EM. At the same time, the scanning signal SC is a low-level signal, the first PMOS transistor T10 is turned on under the control of the scanning signal SC, and at this time the source of the first PMOS transistor T10 receives the data signal Data, so as to write the data signal Data into the energy storage unit 103.

[0136] In the light emitting stage, the first control signal RS1 is a high level signal, the fourth PMOS transistor T40 is turned off under the control of the first control signal RS1, the second control signal RS2 is a high level signal, the fifth PMOS transistor T50 is turned off under the control of the second control signal RS2, the scanning signal SC is a high level signal, and the first PMOS transistor T10 is turned off under the control of the scanning signal SC. At the same time, the light emitting control signal EM is a low level signal, the third PMOS transistor T30 is turned on under the control of the light emitting control signal EM, and the second PMOS transistor T20 is turned on due to the voltage difference between the energy storage unit 103 being the voltage difference between the power supply voltage VDD and the second data signal Data, so that the power supply voltage VDD received by the source of the second PMOS transistor T20 can be used to provide a driving current I_Micro_LED for the light emitting unit 104, so that the light emitting unit 104 is in a working state.

[0137] In the waiting stage, the light emitting control signal EM continues to be a low level signal, the third PMOS transistor T30 is turned on under the control of the light emitting control signal EM, and the first control signal RS1 is a low level signal, the fourth PMOS transistor T40 is turned on under the control of the first control signal RS1, so that the first reset signal Reset1 received by the source of the fourth PMOS transistor T40 can initialize the first end of the light emitting unit 104 and the drain of the second PMOS transistor T20. And the scanning signal SC is a high level signal, the first PMOS transistor T10 is turned off under the control of the scanning signal SC, the second control signal RS2 is a low level signal, and the fifth PMOS transistor T50 is turned on under the control of the second control signal RS2, so that the second reset signal Reset2 received by the source of the fifth PMOS transistor T50 can initialize the gate of the second PMOS transistor T20, at this time the voltage difference between the energy storage unit 103 is the voltage difference between the power supply voltage VDD and the voltage of the second reset signal Reset2, so that the second PMOS transistor T20 can be turned off.

[0138] It can be understood that the pulse width of the driving current can be controlled by the third PMOS transistor T30, the fourth PMOS transistor T40 and the fifth PMOS transistor T50. As shown in FIG. 10, a pixel circuit can have different pulse widths in different frames. Specifically, by controlling the conduction time of the fourth PMOS transistor T40 and the fifth PMOS transistor T50, different pulse widths can be achieved in different frames to realize different gray scales.

[0139] In the above embodiment, the first control signal RS1, the second control signal RS2 and the light-emitting control signal EM can be digital signals of 1 / 0V, the high-level signals corresponding to the first control signal RS1, the second control signal RS2 and the light-emitting control signal EM can be digital signals of 1V, and the low-level signals corresponding to the first control signal RS1, the second control signal RS2 and the light-emitting control signal EM can be digital signals of 0V. The high-level signal corresponding to the scanning signal SC can be a signal greater than 1V. Accordingly, the voltage of the first reset signal Reset1 can be greater than the threshold voltage Vth_T40 of the fourth PMOS transistor T40 and less than the sum of the high-level digital signal and the threshold voltage, i.e., Vth_T40 < Reset1 < 1+Vth_T40. The voltage of the second reset signal Reset2 is greater than the threshold voltage Vth_T50 of the fifth PMOS transistor T50 and less than the sum of the high-level digital signal and the threshold voltage, i.e., Vth_T50 < Reset2 < 1+Vth_T50. Moreover, the voltage of the second reset signal Reset2 is greater than the difference between the power supply voltage and the threshold voltage, i.e., Reset2 > VDD-Vth_T50.

[0140] In yet some examples, the second end of the energy storage unit 103 is connected to the first end of the driving unit 102, and the data writing unit 101 includes a first CMOS transistor, the driving unit 102 includes a second CMOS transistor, and the first pulse width modulation unit 105 includes a third CMOS transistor.

[0141] The control end of the first CMOS transistor serves as the control end of the data writing unit 101 and receives the scanning signal SC; the high-level input end of the first CMOS transistor serves as the first end of the data writing unit 101 and receives the data signal; and the output end of the first CMOS transistor serves as the second end of the data writing unit 101 and is connected to the control end of the driving unit 102, the second end of the second pulse width modulation sub-unit 1062 and the first end of the energy storage unit 103.

[0142] The control end of the second CMOS transistor serves as the control end of the driving unit 102 and is connected to the first end of the energy storage unit 103, the second end of the data writing unit 101 and the second end of the second pulse width modulation sub-unit 1062; the high-level input end of the second CMOS transistor serves as the first end of the driving unit 102 and is connected to the second end of the energy storage unit 103 and receives the power supply voltage VDD; and the output end of the second CMOS transistor serves as the second end of the driving unit 102 and is connected to the first end of the first pulse width modulation unit 105.

[0143] The control end of the third CMOS transistor is used as the control end of the first pulse width modulation unit 105, and receives the light emitting control signal EM. The high level input end of the third CMOS transistor is used as the first end of the first pulse width modulation unit 105, and is connected to the second end of the driving unit 102. The output end of the third CMOS transistor is used as the second end of the first pulse width modulation unit 105, and is connected to the first end of the light emitting unit 104.

[0144] Correspondingly, if the transistors in the pixel circuit are CMOS transistors, the first pulse width modulation sub-unit 161 can include a first NMOS transistor or a first PMOS transistor, and the second pulse width modulation sub-unit 162 can include a second NMOS transistor or a second PMOS transistor.

[0145] In some examples, the first pulse width modulation sub-unit includes a first NMOS transistor, the gate of the first NMOS transistor is used as the control end of the first pulse width modulation sub-unit, and receives the first control signal. The drain of the first NMOS transistor is used as the first end of the first pulse width modulation sub-unit, and receives the first reset signal. The source of the first NMOS transistor is used as the second end of the first pulse width modulation sub-unit, and is connected to the first end of the light emitting unit and the second end of the first pulse width modulation unit. The second pulse width modulation sub-unit includes a second NMOS transistor, the gate of the second NMOS transistor is used as the control end of the second pulse width modulation sub-unit, and receives the second control signal. The drain of the second NMOS transistor is used as the first end of the second pulse width modulation sub-unit, and receives the second reset signal. The source of the second NMOS transistor is used as the second end of the second pulse width modulation sub-unit, and is connected to the first end of the light emitting unit.

[0146] In other examples, the first pulse width modulation sub-unit includes a first PMOS transistor, the gate of the first PMOS transistor is used as the control end of the first pulse width modulation sub-unit, and receives the first control signal. The source of the first PMOS transistor is used as the first end of the first pulse width modulation sub-unit, and receives the first reset signal. The drain of the first PMOS transistor is used as the second end of the first pulse width modulation sub-unit, and is connected to the first end of the light emitting unit. The second pulse width modulation sub-unit includes a second PMOS transistor, the gate of the second PMOS transistor is used as the control end of the second pulse width modulation sub-unit, and receives the second control signal. The source of the second PMOS transistor is used as the first end of the second pulse width modulation sub-unit, and receives the second reset signal. The drain of the second PMOS transistor is used as the second end of the second pulse width modulation sub-unit, and is connected to the first end of the light emitting unit.

[0147] In still some examples, the first pulse width modulation subunit includes a first NMOS transistor, a gate of the first NMOS transistor serving as a control terminal of the first pulse width modulation subunit and receiving the first control signal, a drain of the first NMOS transistor serving as a first terminal of the first pulse width modulation subunit and receiving the first reset signal, and a source of the first NMOS transistor serving as a second terminal of the first pulse width modulation subunit and connected to the first terminal of the light emitting unit. The second pulse width modulation subunit includes a first PMOS transistor, a gate of the first PMOS transistor serving as a control terminal of the second pulse width modulation subunit and receiving the second control signal, a source of the first PMOS transistor serving as a first terminal of the second pulse width modulation subunit and receiving the second reset signal, and a drain of the first PMOS transistor serving as a second terminal of the second pulse width modulation subunit and connected to the first terminal of the light emitting unit.

[0148] In still some examples, the first pulse width modulation subunit includes a first PMOS transistor, a gate of the first PMOS transistor serving as a control terminal of the first pulse width modulation subunit and receiving the first control signal, a source of the first PMOS transistor serving as a first terminal of the first pulse width modulation subunit and receiving the first reset signal, and a drain of the first PMOS transistor serving as a second terminal of the first pulse width modulation subunit and connected to the first terminal of the light emitting unit. The second pulse width modulation subunit includes a first NMOS transistor, a gate of the first NMOS transistor serving as a control terminal of the second pulse width modulation subunit and receiving the second control signal, a source of the first PMOS transistor serving as a first terminal of the second pulse width modulation subunit and receiving the second reset signal, and a drain of the first PMOS transistor serving as a second terminal of the second pulse width modulation subunit and connected to the first terminal of the light emitting unit.

[0149] The pixel circuit unit provided by the present application is described above, and the pixel circuit unit provided by the present application has the following advantages. The second pulse width modulation unit controls the driving unit to be turned off according to the received control signal, and cooperates with the first pulse width modulation unit to modulate the light emitting duration of the light emitting unit, without introducing more transistors, reducing the area consumed by the pixel circuit, improving the pixel density unit, and further improving the picture effect.

[0150] The display device provided by the embodiment of the present application includes the pixel circuit unit described above.

[0151] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, but not to limit them. Although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacements to some or all of the technical features. These modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A pixel circuit unit, wherein, The pixel circuit unit comprises: a driving unit for generating a driving current; a light-emitting unit connected to the driving unit and emitting light under the driving of the driving unit; a first pulse width modulation unit connected between the driving unit and the light-emitting unit and capable of being turned on and off according to a received light-emitting control signal; a second pulse width modulation unit connected to the driving unit, the second pulse width modulation unit controlling the driving unit to be turned on and off according to a received control signal and cooperating with the first pulse width modulation unit to regulate the light-emitting duration of the light-emitting unit.

2. The pixel circuit unit according to claim 1, wherein, The second pulse width modulation unit comprises a first end, a second end, a third end and a control end, the control end of the second pulse width modulation unit being used for receiving the control signal, the first end of the second pulse width modulation unit being used for receiving a reset signal, and the second end and the third end of the second pulse width modulation unit being electrically connected to the driving unit respectively. When the first pulse width modulation unit is in a conductive state under the control of the light-emitting control signal, the second pulse width modulation unit can be turned on under the control of the control signal and can initialize the driving unit through the reset signal via the second end and the third end to control the driving unit to be turned on and off and further control the light-emitting duration of the light-emitting unit.

3. The pixel circuit unit according to claim 2, wherein, The second end is also connected to the light-emitting unit to simultaneously initialize the driving unit and the light-emitting unit and realize multiplexing of the second end.

4. The pixel circuit unit according to claim 2 or 3, wherein The second pulse width modulation unit comprises a first pulse width modulation subunit and a second pulse width modulation subunit, the control signal comprises a first control signal and a second control signal, and the reset signal comprises a first reset signal and a second reset signal. The first pulse width modulation subunit comprises a control end, a first end and the second end, the control end of the first pulse width modulation subunit being used for receiving the first control signal, the first end of the first pulse width modulation subunit being used for receiving the first reset signal, and the second end of the first pulse width modulation subunit being electrically connected to the second end of the driving unit. The second pulse width modulation subunit comprises a control end, a first end and the third end, the control end of the second pulse width modulation subunit being used for receiving the second control signal, the first end of the second pulse width modulation subunit being used for receiving the second reset signal, and the third end of the second pulse width modulation subunit being connected to the control end of the driving unit. When the first pulse width modulation unit is in a conductive state under the control of the light-emitting control signal, the first pulse width modulation subunit is turned on under the control of the first control signal and initializes the driving unit through the first reset signal via the second end, and the second pulse width modulation subunit is turned on under the control of the second control signal and initializes the driving unit through the second reset signal via the third end to control the driving unit to be turned on and off through the action of the two pulse width modulation subunits and regulate the light-emitting duration of the light-emitting unit.

5. The pixel circuit unit according to claim 4, wherein, The second end of the first pulse width modulation subunit is connected to the second end of the driving unit through the first pulse width modulation unit.

6. The pixel circuit unit according to claim 4 or 5, wherein The second end of the first pulse width modulation sub-unit is connected with the first end of the light emitting unit, and is connected with the second end of the driving unit through the first pulse width modulation unit, so as to simultaneously initialize the driving unit and the light emitting unit, and realize multiplexing of the second end.

7. The pixel circuit unit according to any one of claims 4 to 6, wherein The reset signals of the first pulse width modulation sub-unit and the second pulse width modulation sub-unit are simultaneously received by the first pulse width modulation sub-unit and the second pulse width modulation sub-unit respectively when determining the on-off of the driving unit.

8. The pixel circuit unit according to any one of claims 1 to 7, wherein, The light emitting control signal is a global signal or a local signal. The control signal is a global signal or a local signal. The global signal is shared by all sub-pixels in a pixel array, and the local signal is shared by part of the sub-pixels in the pixel array.

9. The pixel circuit unit according to any one of claims 4 to 7, wherein The pixel circuit unit comprises a data writing unit and an energy storage unit. The data writing unit comprises a control end, a first end and a second end, the control end of the data writing unit is used for receiving a scanning signal, the first end of the data writing unit is used for receiving a data signal, and the second end of the data writing unit is connected with the control end of the driving unit and the first end of the energy storage unit. The data writing unit writes the data signal into the energy storage unit when the data writing unit is in a conductive state under the control of the scanning signal.

10. The pixel circuit unit according to claim 9, wherein, in the initialization stage, the data writing unit is in a conductive state under the control of the scanning signal, so as to write a reference signal received by the first end of the data writing unit into the energy storage unit; the first pulse width modulation unit is in a conductive state under the control of the light emitting control signal, and the first pulse width modulation sub-unit is in a conductive state under the control of the first control signal, so as to initialize the first end of the light emitting unit and the second end of the driving unit through the first reset signal; in the data writing stage, the data writing unit is in a conductive state under the control of the scanning signal, so as to write a data signal received by the first end of the data writing unit into the energy storage unit; in the light emitting stage, the voltage difference between the two ends of the energy storage unit controls the driving unit to be in a conductive state, and the first pulse width modulation unit is in a conductive state under the control of the light emitting control signal, so as to control the light emitting unit to be in a working state; in the waiting stage, the first pulse width modulation unit is in a conductive state under the control of the light emitting control signal, the first pulse width modulation sub-unit is in a conductive state under the control of the first control signal, so as to initialize the first end of the light emitting unit and the second end of the driving unit through the first reset signal, and the second pulse width modulation sub-unit is in a conductive state under the control of the second control signal, so as to turn off the driving unit through the second reset signal.

11. The pixel circuit unit according to claim 9 or 10, wherein The data writing unit comprises a first NMOS transistor, the gate of the first NMOS transistor is used as the control end of the data writing unit, the drain of the first NMOS transistor is used as the first end of the data writing unit, and the source of the first NMOS transistor is used as the second end of the data writing unit. The driving unit comprises a second NMOS transistor; a gate of the second NMOS transistor is used as a control end of the driving unit, a drain of the second NMOS transistor is used as a first end of the driving unit, and a source of the second NMOS transistor is used as a second end of the driving unit. The first pulse width modulation unit comprises a third NMOS transistor; a gate of the third NMOS transistor is used as a control end of the first pulse width modulation unit, a drain of the third NMOS transistor is used as a first end of the first pulse width modulation unit, and a source of the third NMOS transistor is used as a second end of the first pulse width modulation unit.

12. The pixel circuit unit according to claim 11, wherein, The first pulse width modulation subunit comprises a fourth NMOS transistor; a gate of the fourth NMOS transistor is used as a control end of the first pulse width modulation subunit, a drain of the fourth NMOS transistor is used as a first end of the first pulse width modulation subunit, and a source of the fourth NMOS transistor is used as a second end of the first pulse width modulation subunit. The second pulse width modulation subunit comprises a fifth NMOS transistor; a gate of the fifth NMOS transistor is used as a control end of the second pulse width modulation subunit, a drain of the fifth NMOS transistor is used as a first end of the second pulse width modulation subunit, and a source of the fifth NMOS transistor is used as a second end of the second pulse width modulation subunit.

13. The pixel circuit unit according to any one of claims 9 to 12, wherein, The data writing unit comprises a first PMOS transistor; a gate of the first PMOS transistor is used as a control end of the data writing unit, a source of the first PMOS transistor is used as a first end of the data writing unit, and a drain of the first PMOS transistor is used as a second end of the data writing unit. The driving unit comprises a second PMOS transistor; a gate of the second PMOS transistor is used as a control end of the driving unit, a source of the second PMOS transistor is used as a first end of the driving unit, and a drain of the second PMOS transistor is used as a second end of the driving unit. The first pulse width modulation unit comprises a third PMOS transistor; a gate of the third PMOS transistor is used as a control end of the first pulse width modulation unit, a source of the third PMOS transistor is used as a first end of the first pulse width modulation unit, and a drain of the third PMOS transistor is used as a second end of the first pulse width modulation unit.

14. The pixel circuit unit according to claim 13, wherein, The first pulse width modulation subunit comprises a fourth PMOS transistor; a gate of the fourth PMOS transistor is used as a control end of the first pulse width modulation subunit, a source of the fourth PMOS transistor is used as a first end of the first pulse width modulation subunit, and a drain of the fourth PMOS transistor is used as a second end of the first pulse width modulation subunit. The second pulse width modulation subunit comprises a fifth PMOS transistor; a gate of the fifth PMOS transistor is used as a control end of the second pulse width modulation subunit, a source of the fifth PMOS transistor is used as a first end of the second pulse width modulation subunit, and a drain of the fifth PMOS transistor is used as a second end of the second pulse width modulation subunit. The second pulse width modulation subunit comprises a fifth PMOS transistor; a gate of the fifth PMOS transistor is a control end of the second pulse width modulation subunit, a source of the fifth PMOS transistor is a first end of the second pulse width modulation subunit, and a drain of the fifth PMOS transistor is a second end of the second pulse width modulation subunit.

15. The pixel circuit unit according to any one of claims 9 to 12, wherein, The data writing unit comprises a first CMOS transistor; a control end of the first CMOS transistor is a control end of the data writing unit, a high-level input end of the first CMOS transistor is a first end of the data writing unit, and an output end of the first CMOS transistor is a second end of the data writing unit. The driving unit comprises a second CMOS transistor; a control end of the second CMOS transistor is a control end of the driving unit, a high-level input end of the second CMOS transistor is a first end of the driving unit, and an output end of the second CMOS transistor is a second end of the driving unit. The first pulse width modulation unit comprises a third CMOS transistor; a control end of the third CMOS transistor is a control end of the first pulse width modulation unit, a high-level input end of the third CMOS transistor is a first end of the first pulse width modulation unit, and an output end of the third CMOS transistor is a second end of the first pulse width modulation unit.

16. The pixel circuit unit according to claim 15, wherein, The first pulse width modulation subunit comprises a first NMOS transistor or a first PMOS transistor; and the second pulse width modulation subunit comprises a second NMOS transistor or a second PMOS transistor. When the first pulse width modulation subunit comprises the first NMOS transistor, a gate of the first NMOS transistor is a control end of the first pulse width modulation subunit, a drain of the first NMOS transistor is a first end of the first pulse width modulation subunit, and a source of the first NMOS transistor is a second end of the first pulse width modulation subunit. When the first pulse width modulation subunit comprises the first PMOS transistor, a gate of the first PMOS transistor is a control end of the first pulse width modulation subunit, a source of the first PMOS transistor is a first end of the first pulse width modulation subunit, and a drain of the first PMOS transistor is a second end of the first pulse width modulation subunit. When the second pulse width modulation subunit comprises the second NMOS transistor, a gate of the second NMOS transistor is a control end of the second pulse width modulation subunit, a drain of the second NMOS transistor is a first end of the second pulse width modulation subunit, and a source of the second NMOS transistor is a second end of the second pulse width modulation subunit. When the second pulse width modulation subunit comprises the second PMOS transistor, a gate of the second PMOS transistor is a control end of the second pulse width modulation subunit, a source of the second PMOS transistor is a first end of the second pulse width modulation subunit, and a drain of the second PMOS transistor is a second end of the second pulse width modulation subunit.

17. A display device, wherein, The pixel circuit unit comprises the pixel circuit unit of any one of claims 1-16.

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