Array substrate, display panel and display device

Abstract

The application provides an array substrate, a display panel and a display device. The array substrate comprises a substrate, an active layer and a multilayer conductor layer which are arranged in a stack on one side of the substrate, the active layer and the multilayer conductor layer form at least one pixel circuit, the pixel circuit comprises a first capacitor and a second capacitor, the first capacitor and the second capacitor are formed between two layers of the conductor layer, and a projection of the first capacitor on the substrate and a projection of the second capacitor on the substrate at least partially overlap. By at least partially overlapping the projection of the first capacitor on the substrate and the projection of the second capacitor on the substrate, the total space occupied by the first capacitor and the second capacitor can be reduced, so that the pixel density is improved, and high-PPI display is realized. Meanwhile, the first capacitor and the second capacitor can be designed to be larger, the pixel circuit can meet a higher refresh rate, and the display effect is improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Technology

[0002] Organic light-emitting diode (OLED) display technology is considered one of the most promising next-generation display technologies. Compared to liquid crystal displays, OLED technology offers advantages such as lower energy consumption, lower cost, self-emissive properties, wide viewing angles, and faster response times.

[0003] However, the performance of current OLED display products needs to be improved. Summary of the Invention

[0004] Based on this, this application provides an array substrate, a display panel, and a display device, which can effectively improve the performance of display products.

[0005] In a first aspect, this application provides an array substrate, comprising: Substrate; An active layer and multiple conductor layers are stacked on one side of the substrate. The active layer and the multiple conductor layers form at least one pixel circuit. The pixel circuit includes a first capacitor and a second capacitor, which are formed between the two conductor layers. Wherein, the orthographic projection of the first capacitor on the substrate and the orthographic projection of the second capacitor on the substrate at least partially overlap.

[0006] In one embodiment, the multilayer conductor layer includes at least a first conductor layer, a fifth conductor layer, and a second conductor layer sequentially stacked in a direction away from the substrate; Wherein, the first plate of the first capacitor is located in the first conductor layer, and the second plate of the first capacitor is located in the fifth conductor layer; the second capacitor is connected in series with the first capacitor, and the first plate of the second capacitor is located in the fifth conductor layer, and the second plate of the second capacitor is located in the second conductor layer. The second plate of the first capacitor is reused as the first plate of the second capacitor; Preferably, the orthographic projection of the first electrode plate of the first capacitor on the substrate at least partially overlaps with the orthographic projection of the second electrode plate of the first capacitor on the substrate; the orthographic projection of the first electrode plate of the second capacitor on the substrate at least partially overlaps with the orthographic projection of the second electrode plate of the second capacitor on the substrate.

[0007] In one embodiment, the pixel circuit includes a plurality of transistors, at least some of which are dual-gate transistors, and at least some of the dual-gate transistors have an intermediate node capacitor disposed between the two gates; Preferably, the dual-gate transistor includes one or more of a data write transistor, a threshold compensation transistor, a reference voltage write transistor, and a gate reset transistor. The intermediate node of the two gates of the dual-gate transistor forms the intermediate node capacitance with the second conductor layer; Alternatively, the intermediate node capacitance is formed between the middle node of the two gates of a portion of the dual-gate transistor and the second conductor layer, and the intermediate node capacitance is formed between the middle node of the two gates of a portion of the dual-gate transistor and the fifth conductor layer. Preferably, the plurality of transistors include a data writing transistor, a threshold compensation transistor, a reference voltage writing transistor, a gate reset transistor, a driving transistor, a light-emitting control transistor, and an anode reset transistor, wherein the driving transistor, the light-emitting control transistor, and the anode reset transistor are single-gate transistors, and the data writing transistor, the threshold compensation transistor, the reference voltage writing transistor, and the gate reset transistor are dual-gate transistors.

[0008] In one embodiment, at least a portion of the dual-gate transistor includes a first gate branch and a second gate branch, the first gate branch and the second gate branch being located in the first conductor layer, and the orthogonal projections of the first gate branch and the second gate branch on the substrate overlapping once with the orthogonal projections of the active layer on the substrate to form a dual-gate structure; Alternatively, at least a portion of the dual-gate transistor includes a gate branch whose orthogonal projection on the substrate overlaps twice with the orthogonal projection of the active layer on the substrate to form a dual-gate structure.

[0009] In one embodiment, the multilayer conductor further includes: A third conductor layer is disposed on the side of the second conductor layer away from the substrate; A fourth conductor layer is disposed on the side of the third conductor layer away from the substrate.

[0010] In one embodiment, the array substrate further includes: The fan-out trace is partially located in the third conductor layer and partially located in the fourth conductor layer. The fan-out trace in the third conductor layer is connected to the fan-out trace in the fourth conductor layer. Preferably, the fan-out trace in the third conductor layer extends along a first direction, and the fan-out trace in the fourth conductor layer extends along a second direction; wherein the first direction and the second direction intersect.

[0011] In one embodiment, the array substrate further includes: The first reset signal line is partially located in the third conductor layer and partially located in the fourth conductor layer. The first reset signal line in the third conductor layer is connected to the first reset signal line in the fourth conductor layer to form a mesh structure. The second reset signal line is partially located in the second conductor layer and partially located in the fourth conductor layer. The second reset signal line in the second conductor layer is connected to the second reset signal line in the fourth conductor layer to form a mesh structure. Preferably, the first reset signal line in the third conductor layer and the second reset signal line in the second conductor layer extend along a first direction, and the first reset signal line and the second reset signal line in the fourth conductor layer extend along a second direction; wherein the first direction and the second direction intersect.

[0012] In one embodiment, the multilayer conductor further includes: A sixth conductor layer is disposed between the third conductor layer and the fourth conductor layer; The fan-out trace is partially located in the sixth conductor layer and partially located in the fourth conductor layer. The fan-out trace in the sixth conductor layer is connected to the fan-out trace in the fourth conductor layer. Preferably, the fan-out trace in the sixth conductor layer extends along a first direction, and the fan-out trace in the fourth conductor layer extends along a second direction; wherein the first direction and the second direction intersect. Preferably, the array substrate further includes: The first reset signal line is at least partially located in the sixth conductor layer; The second reset signal line is at least partially located in the sixth conductor layer; Preferably, the array substrate further includes a first interlayer dielectric layer, the third conductor layer is connected to the second conductor layer through a via of the first interlayer dielectric layer, the third conductor layer is connected to the fifth conductor layer through a via of the first interlayer dielectric layer, the third conductor layer is connected to the first conductor layer through a via of the first interlayer dielectric layer, and the third conductor layer is connected to the active layer through a via of the first interlayer dielectric layer.

[0013] On the other hand, this application also discloses a display panel comprising the array substrate described in any of the above claims.

[0014] Furthermore, this application also discloses a display device that includes the aforementioned display panel.

[0015] The array substrate provided in this application, by at least partially overlapping the orthographic projections of the first capacitor and the second capacitor on the substrate, helps to reduce the overall space occupied by the first and second capacitors, thereby increasing pixel density and achieving high PPI display. Simultaneously, it facilitates the design of larger first and second capacitors, enabling the pixel circuitry to meet higher refresh rates and improve display performance. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in this application or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a circuit diagram of a pixel circuit in a related array substrate; Figure 2 It is a layout of a related array substrate; Figure 3 This is a schematic diagram of the layer structure of the array substrate in one embodiment of this application; Figure 4 This is a schematic diagram of a portion of the layer structure of the array substrate in another embodiment of this application; Figure 5 This is a schematic diagram of the layer structure of the array substrate in another embodiment of this application; Figure 6 This is a schematic diagram of the layer structure of the array substrate in another embodiment of this application; Figure 7 This is a schematic diagram of the layer structure of the array substrate in another embodiment of this application; Figure 8 This is a schematic diagram of the layer structure of the array substrate in another embodiment of this application; Figure 9 This is a partial layout schematic diagram of the array substrate in another embodiment of this application; Figure 10 This is a partial layout schematic diagram of the array substrate in another embodiment of this application; Figure 11 This is a partial layout schematic diagram of the array substrate in another embodiment of this application; Figure 12 This is a partial layout schematic diagram of the array substrate in another embodiment of this application; Figure 13 This is a partial layout schematic diagram of the array substrate in another embodiment of this application; Figure 14 This is a partial layout schematic diagram of the array substrate in another embodiment of this application; Figure 15 This is a partial layout schematic diagram of the array substrate in another embodiment of this application; Figure 16 This is a partial layout schematic diagram of the array substrate in another embodiment of this application; Figure 17 This is a partial layout schematic diagram of the array substrate in another embodiment of this application; Figure 18 This is a partial layout schematic diagram of the array substrate in another embodiment of this application; Figure 19 This is a partial layout schematic diagram of the array substrate in another embodiment of this application; Figure 20 This is a partial layout schematic diagram of the array substrate in another embodiment of this application; Figure 21 This is a partial layout schematic diagram of the array substrate in another embodiment of this application; Figure 22 This is a partial layout schematic diagram of the array substrate in another embodiment of this application; Figure 23 This is a partial layout schematic diagram of the array substrate in another embodiment of this application; Figure 24 This is a partial layout schematic diagram of the array substrate in another embodiment of this application; Figure 25 This is a partial layout schematic diagram of the array substrate in another embodiment of this application; Figure 26 This is a partial layout schematic diagram of the array substrate in another embodiment of this application; Figure 27 This is a partial layout schematic diagram of the array substrate in another embodiment of this application.

[0018] Marker explanation: 100. Array substrate; 110. Pixel circuit; C1. First capacitor; C2. Second capacitor; 1. Gate; 11. First gate branch; 12. Second gate branch; 13. Gate branch; 2. Source; 3. Drain; 10. Substrate; 20. Active layer; 30. Conductor layer; 31. First conductor layer; 32. Second conductor layer; 33. Third conductor layer; 34. Fourth conductor layer; 35. Fifth conductor layer; 36. Sixth conductor layer; 41. Fan-out trace; 81. Anode layer; 91. Pixel definition layer; 92. Spacer layer. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0020] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in the embodiments of this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0021] Reference Figure 1 The diagram shown illustrates a pixel circuit capable of achieving a high refresh rate in a related technology. This pixel circuit comprises seven P-type LTPS TFTs (Low Temperature Poly-Silicon Thin Film Transistors) (T1, T2, T3, T4, T5, T6, and T7) and two capacitors (C1 and C2), hence the abbreviation 7T2C pixel circuit. T2, T3, T4, and T5 are all dual-gate TFTs; for example, T2 is composed of T2-1 and T2-2 forming a dual-gate TFT.

[0022] The inventors discovered that connecting capacitors C1 and C2 in series reduces the overall capacitance. Therefore, to enable the pixel circuit to achieve a high refresh rate, both capacitors need to be designed to be as large as possible. For example, if C1 and C2 are designed to be 100fF, the resulting series capacitance is 50fF. Multiple dual-gate TFTs and two large capacitors require significantly more design space for the overall circuit structure (compared to 7T1C or 8T1C), making high PPI design extremely difficult.

[0023] Reference Figure 2 The diagram shows a layout of a pixel circuit in a related technology, in which capacitors C1 and C2 are formed using the same two metal layers, resulting in a large overall footprint and making it difficult to achieve a high PPI display.

[0024] Based on this, this application provides an array substrate solution to solve the above-mentioned technical problems.

[0025] Reference Figure 3-4 As shown, an array substrate 100 is disclosed in one embodiment of this application, which includes: a substrate 10; an active layer 20 and a multilayer conductor layer 30 stacked on one side of the substrate 10, wherein the active layer 20 and the multilayer conductor layer 30 form at least one pixel circuit, the pixel circuit including a first capacitor C1 and a second capacitor C2, the first capacitor C2 and the second capacitor C2 being formed between the two conductor layers; wherein the orthographic projection of the first capacitor C1 on the substrate 10 and the orthographic projection of the second capacitor C2 on the substrate 10 at least partially overlap.

[0026] The array substrate 100 provided in this embodiment, by at least partially overlapping the orthographic projections of the first capacitor C1 and the second capacitor C2 on the substrate 10, helps to reduce the overall space occupied by the first capacitor C1 and the second capacitor C2, thereby increasing the pixel density and achieving a high PPI display. Simultaneously, it facilitates the design of larger first capacitor C1 and second capacitor C2, enabling the pixel circuit to meet higher refresh rates and improve display performance.

[0027] Wherein, the orthographic projection of the first capacitor C1 on the substrate 10 and the orthographic projection of the second capacitor C2 on the substrate 10 at least partially overlap, which can be understood as the orthographic projection of the first capacitor C1 on the substrate 10 and the orthographic projection of the second capacitor C2 on the substrate 10 partially overlapping or completely overlapping.

[0028] Optionally, the first capacitor C1 and the second capacitor C2 can be connected in series or in parallel.

[0029] The substrate 10 has the functions of support, protection and buffer. The substrate 10 can be a flexible substrate, such as a polyimide (PI) substrate, or a rigid substrate, such as a glass substrate. No limitation is made here.

[0030] Optionally, the transistor T formed in this embodiment is a P-type thin-film transistor or an N-type thin-film transistor.

[0031] Optionally, the pixel circuit 110 can be a 5T2C pixel circuit, a 6T2C pixel circuit, a 7T2C pixel circuit, an 8T2C pixel circuit, etc.

[0032] In this capacitor, one of the first capacitor C1 and the second capacitor C2 is a storage capacitor, and the other is a compensation capacitor. Optionally, the ratio of the storage capacitor to the compensation capacitor is from 1:1 to 5:1.

[0033] Among them, the storage capacitor is used to sample and maintain the grayscale data voltage from the data line, providing a stable potential input to the gate node of the driving transistor within a frame cycle, ensuring that the driving current of the pixel circuit is constant and accurately corresponds to the input grayscale, thereby achieving a stable output of pixel brightness. It is the core energy storage component that determines the grayscale and color information of the image.

[0034] The compensation capacitor is used to sample and store the threshold voltage information of the driving transistor. It can offset the threshold voltage deviation of the driving transistor itself, the unevenness of the process, and the threshold drift during operation through charge coupling and potential coupling. This can effectively improve the uniformity of panel brightness, suppress flicker and afterimages, and improve the working stability of the pixel circuit under high refresh rate and high PPI conditions.

[0035] Reference Figure 4 As shown, in one embodiment, the multilayer conductor layer 30 includes at least a first conductor layer 31, a fifth conductor layer 35, and a second conductor layer 32 sequentially stacked along a direction away from the substrate 10. The first electrode C11 of the first capacitor C1 is located on the first conductor layer 31, and the second electrode C12 of the first capacitor C1 is located on the fifth conductor layer 35. The second capacitor C2 is connected in series with the first capacitor C1, and the first electrode C21 of the second capacitor C2 is located on the fifth conductor layer 35, while the second electrode C22 of the second capacitor C2 is located on the second conductor layer 32. The second electrode C12 of the first capacitor C1 is reused as the first electrode C21 of the second capacitor C2. That is, the second electrode C12 of the first capacitor C1 is also the first electrode C21 of the second capacitor C2, which helps to further reduce space occupation, reduce the area of ​​the fifth conductor layer 35, and reduce the impact of the fifth conductor layer 35 on the wiring between other film layers.

[0036] Optionally, the orthographic projection of the first plate C11 of the first capacitor C1 on the substrate 10 at least partially overlaps with the orthographic projection of the second plate C12 of the first capacitor C1 on the substrate 10; the orthographic projection of the first plate C21 of the second capacitor C2 on the substrate 10 at least partially overlaps with the orthographic projection of the second plate C22 of the second capacitor C2 on the substrate 10; this is beneficial for further reducing space occupation.

[0037] In one embodiment, the pixel circuit includes a plurality of transistors, at least some of which are dual-gate transistors. An intermediate node capacitor C3 is disposed between the two gates of the dual-gate transistor. (Refer to...) Figure 1 As shown in the diagram. The intermediate node capacitor C3 is used to ensure the stable voltage state of the node when the dual-gate transistor is off, preventing it from being affected by parasitic capacitance.

[0038] Optionally, the ratio of intermediate node capacitor C3 to storage capacitor is 1:100 to 1:20.

[0039] Optionally, the dual-gate transistor includes one or more of the following: a data write transistor T2, a threshold compensation transistor T3, a reference voltage write transistor T4, and a gate reset transistor T5. The intermediate node of the two gates of the dual-gate transistor forms an intermediate node capacitance C3 with the second conductor layer 32. Alternatively, the intermediate node capacitance C3 is formed by the intermediate nodes of the two gates of some dual-gate transistors with the second conductor layer 32, and by the intermediate nodes of the two gates of some dual-gate transistors with the fifth conductor layer 35. This ensures stable node voltage states while meeting high refresh rates. The intermediate node of the two gates of the dual-gate transistor is located in the active layer 20.

[0040] In one embodiment, the intermediate nodes of the two gates of the data writing transistor T2, the threshold compensation transistor T3, the reference voltage writing transistor T4, and the gate reset transistor T5 all form an intermediate node capacitor C3 between themselves and the second conductor layer 32.

[0041] For example, the intermediate nodes of the two gates of the data writing transistor T2 and the gate reset transistor T5 respectively form intermediate node capacitance C3 between the high-level power supply signal line VDD and the node in the second conductor layer 32; the intermediate nodes of the two gates of the threshold compensation transistor T3 and the reference voltage writing transistor T4 respectively form intermediate node capacitance C3 between the two gates of the second reset signal line Vref2 in the second conductor layer 32.

[0042] In another embodiment, an intermediate node capacitor C3 is formed between the middle node of the two gates of the gate reset transistor T5 and the fifth conductor layer 35. Similarly, intermediate node capacitors are formed between the middle nodes of the two gates of the data write transistor T2, the threshold compensation transistor T3, and the reference voltage write transistor T4 and the second conductor layer 32. Exemplarily, an intermediate node capacitor C3 is formed between the middle nodes of the two gates of the gate reset transistor T5 and the first reset signal line Vref1 in the fifth conductor layer 35. Similarly, intermediate node capacitors C3 are formed between the middle nodes of the two gates of the data write transistor T2, the threshold compensation transistor T3, and the reference voltage write transistor T4 and the second reset signal line Vref2 in the second conductor layer 32.

[0043] Optionally, the plurality of transistors includes a data write transistor T2, a threshold compensation transistor T3, a reference voltage write transistor T4, a gate reset transistor T5, a drive transistor T1, a light-emitting control transistor T6, and an anode reset transistor T7. The drive transistor T1, light-emitting control transistor T6, and anode reset transistor T7 are single-gate transistors. The data write transistor T2, threshold compensation transistor T3, reference voltage write transistor T4, and gate reset transistor T5 are reference... Figure 1The 7T2C pixel circuit consists of a data writing transistor T2, a threshold compensation transistor T3, a reference voltage writing transistor T4, a gate reset transistor T5, a driving transistor T1, a light emission control transistor T6, an anode reset transistor T7, a first capacitor C1, and a second capacitor C2.

[0044] In one embodiment, at least a portion of the dual-gate transistor includes a first gate branch and a second gate branch, the first gate branch and the second gate branch being located on the first conductor layer 31, and the orthogonal projections of the first gate branch and the second gate branch on the substrate 10 overlapping once with the orthogonal projections of the active layer 20 on the substrate 10 to form a dual-gate structure.

[0045] In another embodiment, at least a portion of the dual-gate transistor includes a gate branch whose orthographic projection on the substrate 10 overlaps twice with the orthographic projection of the active layer 20 on the substrate 10 to form a dual-gate structure. Since the intermediate node of the two gates of the dual-gate transistor is located in the active layer 20, compared to the above embodiment, the area of ​​the active layer 20 between the two overlaps can be designed to be larger in this embodiment; therefore, the resulting intermediate node capacitance C3 can be designed to be larger.

[0046] Reference Figure 5 As shown, in one embodiment, the multilayer conductor layer 30 further includes a third conductor layer 33 and a fourth conductor layer 34. The third conductor layer 33 is disposed on the side of the second conductor layer 32 away from the substrate 10, and the fourth conductor layer 34 is disposed on the side of the third conductor layer 33 away from the substrate 10. The third conductor layer 33 is used to form the source 2 and drain 3 of the transistor, and the fourth conductor layer 34 is used to form the high-level power signal line VDD.

[0047] Optionally, the second conductor layer 32 is used to form the gate 1 of the transistor. The gate 1 is used to apply a control signal, and the source 2 and drain 3 respectively form ohmic contacts with the corresponding regions of the active layer 20. The carrier transport capability in the active layer 20 can be adjusted by the control voltage applied to the gate 1, thereby realizing the turn-on and turn-off control between the source 2 and the drain 3.

[0048] Reference Figure 5 As shown, in one embodiment, the array substrate 100 further includes fan-out traces 41, partially located in the third conductor layer 33 and partially located in the fourth conductor layer 34. The fan-out traces 41 in the third conductor layer 33 are connected to the fan-out traces 41 in the fourth conductor layer 34. By distributing the fan-out traces 41 in the third conductor layer 33 and the fourth conductor layer 34, it is convenient to implement FIAA (Fanout In AA) design, thereby achieving a narrow bezel for the display product.

[0049] Preferably, the fan-out trace 41 in the third conductor layer 33 extends along a first direction, and the fan-out trace 41 in the fourth conductor layer 34 extends along a second direction; wherein the first direction and the second direction intersect.

[0050] Optionally, the first direction and the second direction are at an angle of 45 degrees, 50 degrees, 55 degrees, 60 degrees, 65 degrees, 70 degrees, 75 degrees, 80 degrees, 85 degrees, 90 degrees, etc.

[0051] Reference Figure 6 As shown, in one embodiment, the array substrate 100 further includes a first reset signal line Vref1 and a second reset signal line Vref2. The first reset signal line Vref1 is partially located in the third conductor layer 33 and partially located in the fourth conductor layer 34. The first reset signal line Vref1 in the third conductor layer 33 is connected to the first reset signal line Vref1 in the fourth conductor layer 34 to form a mesh structure. The second reset signal line Vref2 is partially located in the second conductor layer 32 and partially located in the fourth conductor layer 34. The second reset signal line Vref2 in the second conductor layer 32 is connected to the second reset signal line Vref2 in the fourth conductor layer 34 to form a mesh structure. This improves the uniformity of the display in the display product.

[0052] Optionally, the first reset signal line Vref1 in the third conductor layer 33 and the second reset signal line Vref2 in the second conductor layer 32 extend along a first direction, and the first reset signal line Vref1 and the second reset signal line Vref2 in the fourth conductor layer 34 extend along a second direction.

[0053] Reference Figure 7 As shown, in another embodiment, the multilayer conductor layer 30 further includes a sixth conductor layer 36 and fan-out traces 41. The sixth conductor layer 36 is disposed between the third conductor layer 33 and the fourth conductor layer 34. Part of the fan-out traces 41 are located in the sixth conductor layer 36, and part are located in the fourth conductor layer 34. The fan-out traces 41 in the sixth conductor layer 36 are connected to the fan-out traces 41 in the fourth conductor layer 34. Compared to the above embodiment, in this embodiment, by disposing of the sixth conductor layer 36 between the third conductor layer 33 and the fourth conductor layer 34, and moving the fan-out traces 41 in the third conductor layer 33 to the sixth conductor layer 36, the parasitic capacitance between the conductor layer and the lower conductor layer can be effectively reduced, which is more conducive to achieving a high PPI design.

[0054] Optionally, the fan-out trace 41 in the sixth conductor layer 36 extends along a first direction, and the fan-out trace 41 in the fourth conductor layer 34 extends along a second direction; wherein the first direction and the second direction intersect.

[0055] Optionally, the array substrate 100 further includes a first reset signal line Vref1 and a second reset signal line Vref2, wherein the first reset signal line Vref1 is at least partially located in the sixth conductor layer 36 and the second reset signal line Vref2 is at least partially located in the sixth conductor layer 36, thereby reducing the routing pressure on other conductor layers.

[0056] Optionally, the first reset signal line Vref1 is partially located in the fourth conductor layer 34 and partially located in the sixth conductor layer 36. The first reset signal line Vref1 in the fourth conductor layer 34 is connected to the first reset signal line Vref1 in the sixth conductor layer 36 to form a mesh structure. The second reset signal line Vref2 is partially located in the fourth conductor layer 34 and partially located in the sixth conductor layer 36. The second reset signal line Vref2 in the fourth conductor layer 34 is connected to the second reset signal line Vref2 in the sixth conductor layer 36 to form a mesh structure.

[0057] Optionally, the first reset signal line Vref1 and the second reset signal line Vref2 in the sixth conductor layer 36 extend along a first direction, and the first reset signal line Vref1 and the second reset signal line Vref2 in the fourth conductor layer 34 extend along a second direction.

[0058] Reference Figure 8 As shown, in one embodiment, the array substrate 100 further includes a first interlayer dielectric layer ILD1, a third conductor layer 33 connected to a second conductor layer 32 through a via of the first interlayer dielectric layer ILD1, a third conductor layer 33 connected to a fifth conductor layer 35 through a via of the first interlayer dielectric layer ILD1, a third conductor layer 33 connected to a first conductor layer 31 through a via of the first interlayer dielectric layer ILD1, and a third conductor layer 33 connected to an active layer 20 through a via of the first interlayer dielectric layer ILD1.

[0059] Optionally, the array substrate 100 further includes a first planarization layer PLN1, and the fourth conductor layer 34 is connected to the third conductor layer 33 through a via of the first planarization layer PLN1.

[0060] Optionally, the array substrate 100 further includes an anode layer 81 and a second planarization layer PLN2, wherein the anode layer 81 is connected to the fourth conductor layer 34 through a via of the second planarization layer PLN2.

[0061] Furthermore, the array substrate 100 is also provided with a pixel definition layer 91 and a spacer layer 92. The pixel definition layer 91 is used to form pixel openings that expose the anode layer 81, and the spacer layer 92 is used to support the mask during subsequent evaporation.

[0062] Reference Figure 9-20 The diagram shown is a layout of the array substrate 100 in another embodiment of this application, and is combined with... Figure 1 and8 The fabrication process of the array substrate 100 is as follows: (101) First, an active layer 20 is formed on the substrate 10.

[0063] (102) A first conductor layer 31 is formed on the side of the active layer 20 away from the substrate 10, as shown in the figure. Figure 9-10 As shown in the diagram, the space within the dashed box represents the area occupied by one pixel circuit 110. Adjacent pixel circuits 110 are mirror images of each other, forming a "back-to-back" structure, which is beneficial for achieving a high PPI. The first conductor layer 31 includes the first electrode C11 of the first capacitor C1. The first conductor layer 31 also includes the gate of a transistor, and scan signal lines S1, S1', S2, S3, and the light emission control signal line EM connected to each gate, as well as nodes g in the pixel circuit 110.

[0064] Among them, the data writing transistor T2, the threshold compensation transistor T3, the reference voltage writing transistor T4, and the gate reset transistor T5 are all dual-gate transistors. The intermediate node capacitor C3 is formed between the intermediate nodes of the two gates T2-1 and T2-2 of T2 and the second conductor layer 32. The intermediate node capacitor C3 is formed between the intermediate nodes of the two gates T3-1 and T3-2 of T3 and the second conductor layer 32. The intermediate node capacitor C3 is formed between the intermediate nodes of the two gates T4-1 and T4-2 of T4 and the second conductor layer 32. The intermediate node capacitor C3 is formed between the intermediate nodes of the two gates T5-1 and T5-2 of T5 and the second conductor layer 32.

[0065] T2 and T5 both include a first gate branch 11 and a second gate branch 12. The first gate branch 11 and the second gate branch 12 are located in the first conductor layer 31. The orthogonal projections of the first gate branch 11 and the second gate branch 12 on the substrate 10 overlap once with the orthogonal projections of the active layer 20 on the substrate 10 to form a dual gate structure.

[0066] (103) A fifth conductor layer 35 is formed on the side of the first conductor layer 31 away from the substrate 10, as shown in the figure. Figure 11 As shown. Within the space occupied by a pixel circuit 110, the fifth conductor layer 35 is a single piece of metal. The fifth conductor layer 35 serves as the second electrode C12 of the first capacitor C1 and the first electrode C21 of the second capacitor C2. The fifth conductor layer 35 includes node n in the pixel circuit 110. The orthographic projection of the first electrode C11 of the first capacitor C1 onto the substrate 10 at least partially overlaps with the orthographic projection of the second electrode C12 of the first capacitor C1 onto the substrate 10.

[0067] (104) A second conductor layer 32 is formed on the side of the fifth conductor layer 35 away from the substrate 10, as shown in the figure. Figure 12As shown. The second conductor layer 32 includes the second plate C22 of the second capacitor C2, the high-level power supply signal node VDD, and the second reset signal line Vref2.

[0068] Among them, the intermediate node T23 of the two gates T2-1 and T2-2 of T2, the intermediate node T33 of the two gates T3-1 and T3-2 of T3, the intermediate node T43 of the two gates T4-1 and T4-2 of T4, and the intermediate node T53 of the two gates T5-1 and T5-2 of T5 are referenced. Figure 13 As shown.

[0069] Among them, intermediate nodes T23 and T53 form intermediate node capacitor C3 with node VDD in the second conductor layer 32; intermediate nodes T33 and T43 form intermediate node capacitor C3 with the second reset signal line Vref2 in the second conductor layer 32.

[0070] (105) A first interlayer dielectric layer ILD1 is formed on the side of the second conductor layer 32 away from the substrate 10, as shown in the figure. Figure 14 As shown.

[0071] Within the space occupied by a pixel circuit 110, the holes of the first interlayer dielectric layer ILD1 include holes ILD1-1, ILD1-2, ILD1-3, ILD1-4, ILD1-5, ILD1-6, ILD1-7, ILD1-8, ILD1-9, ILD1-10, ILD1-11, ILD1-12, ILD1-13, and ILD1-14, wherein ILD1-1, ILD1-2, and ILD1-4... Holes ILD1-5, ILD1-8, ILD1-11, ILD1-13, and ILD1-14 are holes connecting the third conductor layer 33 to the active layer 20; holes ILD1-7, ILD1-9, and ILD1-12 are holes connecting the third conductor layer 33 to the first conductor layer 31; hole ILD1-10 is a hole connecting the third conductor layer 33 to the fifth conductor layer 35; and holes ILD1-3, ILD1-6, and ILD1-15 are holes connecting the third conductor layer 33 to the second conductor layer 32.

[0072] (106) A third conductor layer 33 is formed on the side of the first interlayer dielectric layer ILD1 away from the substrate 10, as shown in the figure. Figure 15 As shown.

[0073] The third conductor layer 33 includes nodes g, n, VDD (high-level power signal node), anode node a, scan signal line S3, EM (light emission control signal line), Data signal node Data, Vref1 (first reset signal line), and fan-out trace 41 in the pixel circuit 110.

[0074] The first reset signal line Vref1 and the fan-out trace 41 extend along the first direction (X direction in the figure).

[0075] (107) A first planarization layer PLN1 is formed on the side of the third conductor layer 33 away from the substrate 10, as shown in the figure. Figure 16 As shown.

[0076] The first planarization layer PLN1 includes three holes: PLN1-1, PLN1-2, and PLN1-3. Hole PLN1-1 is connected to the high-level power signal line VDD, hole PLN1-2 is connected to the data signal line Data, and hole PLN1-3 is connected to the anode point a.

[0077] (108) A fourth conductor layer 34 is formed on the side of the first planarization layer PLN1 away from the substrate 10, as shown in the figure. Figure 17-18 As shown.

[0078] Among them, the fan-out trace 41, the high-level power signal line VDD, and the data signal line Data extend along the second direction (Y direction in the figure). The second reset signal line Vref2 in the second conductor layer 32 and the second reset signal line Vref2 in the fourth conductor layer 34 are connected by vias at position PLN1-b to form a mesh structure. The first reset signal line Vref1 in the third conductor layer 33 and the first reset signal line Vref1 in the fourth conductor layer 34 are connected by vias at position PLN1-a to form a mesh structure. (Refer to...) Figure 18 As shown.

[0079] Specifically, the fan-out trace 41 in the fourth conductor layer 34 is connected to the fan-out trace 41 in the third conductor layer 33 via a via at position PLN1-c, and then connected to the data traces at other positions, as shown in the reference. Figure 19 As shown. The pixel circuits 110 are arranged in an array in the first and second directions, and adjacent pixel circuits 110 are mirror images of each other, forming a "back-to-back" structure.

[0080] (109) A second planarization layer PLN2 is formed on the side of the fourth conductor layer 34 away from the substrate 10.

[0081] (110) An anode layer 81 is formed on the side of the second planarization layer PLN2 away from the substrate 10, as shown in the figure. Figure 20 As shown.

[0082] Reference Figure 21-27 The diagram shown is a layout of the array substrate 100 in another embodiment of this application, and is combined with... Figure 1 and 8 The fabrication process of the array substrate 100 is as follows: (201) First, an active layer 20 is formed on the substrate 10.

[0083] (202) A first conductor layer 31 is formed on the side of the active layer 20 away from the substrate 10, as shown in the figure. Figure 21-22 As shown in the diagram, the space within the dashed box represents the area occupied by one pixel circuit 110. Adjacent pixel circuits 110 are mirror images of each other, forming a "back-to-back" structure, which is beneficial for achieving a high PPI. The first conductor layer 31 includes the first electrode C11 of the first capacitor C1. The first conductor layer 31 also includes the gate of a transistor, and scan signal lines S1, S1', S2, S3, and the light emission control signal line EM connected to each gate, as well as nodes g in the pixel circuit 110.

[0084] Among them, the data writing transistor T2, the threshold compensation transistor T3, the reference voltage writing transistor T4, and the gate reset transistor T5 are all dual-gate transistors. The intermediate node capacitor C3 is formed between the intermediate nodes of the two gates T2-1 and T2-2 of T2 and the second conductor layer 32. The intermediate node capacitor C3 is formed between the intermediate nodes of the two gates T3-1 and T3-2 of T3 and the second conductor layer 32. The intermediate node capacitor C3 is formed between the intermediate nodes of the two gates T4-1 and T4-2 of T4 and the second conductor layer 32. The intermediate node capacitor C3 is formed between the intermediate nodes of the two gates T5-1 and T5-2 of T5 and the fifth conductor layer 35.

[0085] T2 and T5 each include a gate branch 13, and the orthogonal projection of the gate branch 13 on the substrate 10 overlaps twice with the orthogonal projection of the active layer 20 on the substrate 10 to form a dual-gate structure.

[0086] (203) A fifth conductor layer 35 is formed on the side of the first conductor layer 31 away from the substrate 10, as shown in the figure. Figure 23 As shown. The fifth conductor layer 35 includes the second electrode C12 of the first capacitor C1 and the first electrode C21 of the second capacitor C2. The fifth conductor layer 35 also includes node n and the first reset signal line Vref1 in the pixel circuit 110. The orthographic projection of the first electrode C11 of the first capacitor C1 onto the substrate 10 at least partially overlaps with the orthographic projection of the second electrode C12 of the first capacitor C1 onto the substrate 10.

[0087] (204) A second conductor layer 32 is formed on the side of the fifth conductor layer 35 away from the substrate 10, as shown in the figure. Figure 24 As shown. The second conductor layer 32 includes the second plate C22 of the second capacitor C2, the high-level power supply signal node VDD, and the second reset signal line Vref2.

[0088] Among them, the intermediate node T23 of the two gates T2-1 and T2-2 of T2, the intermediate node T33 of the two gates T3-1 and T3-2 of T3, the intermediate node T43 of the two gates T4-1 and T4-2 of T4, and the intermediate node T53 of the two gates T5-1 and T5-2 of T5 are referenced. Figure 25 As shown.

[0089] Among them, intermediate node T53 and the first reset signal line Vref1 in the fifth conductor layer 35 form intermediate node capacitor C3; intermediate node T23, intermediate node T33 and intermediate node T43 and the second reset signal line Vref2 in the second conductor layer 32 form intermediate node capacitor C3.

[0090] (205) A first interlayer dielectric layer ILD1 is formed on the side of the second conductor layer 32 away from the substrate 10, as shown in the figure. Figure 26 As shown.

[0091] Within the space occupied by a pixel circuit 110, the holes of the first interlayer dielectric layer ILD1 include holes ILD1-1, ILD1-2, ILD1-3, ILD1-4, ILD1-5, ILD1-6, ILD1-7, ILD1-8, ILD1-9, ILD1-10, ILD1-11, ILD1-12, ILD1-13, and ILD1-14, wherein ILD1-1, ILD1-3, and ILD1-4 are... D1-4, ILD1-7, ILD1-8, ILD1-11, ILD1-13, and ILD1-14 are holes connecting the third conductor layer 33 to the active layer 20; ILD1-6, ILD1-10, and ILD1-11 are holes connecting the third conductor layer 33 to the first conductor layer 31; ILD1-9 is a hole connecting the third conductor layer 33 to the fifth conductor layer 35; and ILD1-5 and ILD1-14 are holes connecting the third conductor layer 33 to the second conductor layer 32.

[0092] (206) A third conductor layer 33 is formed on the side of the first interlayer dielectric layer ILD1 away from the substrate 10, as shown in the figure. Figure 27 As shown.

[0093] The third conductor layer 33 includes nodes g, n, VDD (high-level power signal node), anode node a, scan signal line S3, EM (light emission control signal line), Data signal node Data, Vref1 (first reset signal line), and fan-out trace 41 in the pixel circuit 110.

[0094] The first reset signal line Vref1 and the fan-out trace 41 extend along the first direction (X direction in the figure).

[0095] (207) A first planarization layer PLN1 is formed on the side of the third conductor layer 33 away from the substrate 10, as shown in the figure. Figure 16 As shown.

[0096] The first planarization layer PLN1 includes three holes: PLN1-1, PLN1-2, and PLN1-3. Hole PLN1-1 is connected to the high-level power signal line VDD, hole PLN1-2 is connected to the data signal line Data, and hole PLN1-3 is connected to the anode point a.

[0097] (208) A fourth conductor layer 34 is formed on the side of the first planarization layer PLN1 away from the substrate 10, as shown in the figure. Figure 17 and 18 As shown.

[0098] Among them, the fan-out trace 41, the high-level power signal line VDD, and the data signal line Data extend along the second direction (Y direction in the figure). The second reset signal line Vref2 in the second conductor layer 32 and the second reset signal line Vref2 in the fourth conductor layer 34 are connected by vias at position PLN1-b to form a mesh structure. The first reset signal line Vref1 in the third conductor layer 33 and the first reset signal line Vref1 in the fourth conductor layer 34 are connected by vias at position PLN1-a to form a mesh structure. (Refer to...) Figure 18 .

[0099] (209) A second planarization layer PLN2 is formed on the side of the fourth conductor layer 34 away from the substrate 10.

[0100] (210) An anode layer 81 is formed on the side of the second planarization layer PLN2 away from the substrate 10, as shown in the figure. Figure 20 As shown.

[0101] Based on the same inventive concept, another embodiment of this application discloses a display panel, which includes the array substrate 100 of any of the above-mentioned embodiments. The display panel may further include a light-emitting device (OLED), and the pixel circuit in the array substrate 100 is connected to the light-emitting device OLED to drive the light-emitting device OLED to emit light. The display panel includes the array substrate 100 provided in any embodiment of the present invention, and therefore has the same beneficial effects as the array substrate provided in any embodiment of the present application, which will not be described again here. The display panel can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, etc.

[0102] Based on the same inventive concept, another embodiment of this application discloses a display device that includes the aforementioned display panel. This display device may include devices with image processing capabilities, such as mobile phones, desktop computers, laptops, tablets, in-vehicle displays, wearable devices, etc. Because this display device includes the display panel described in this application, the reliability of this electronic device is higher.

[0103] It should be noted that the above description describes some embodiments of this application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in a different order than that shown in the above embodiments and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0104] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the technical concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. An array substrate, characterized in that, include: Substrate; An active layer and multiple conductor layers are stacked on one side of the substrate. The active layer and the multiple conductor layers form at least one pixel circuit. The pixel circuit includes a first capacitor and a second capacitor, which are formed between the two conductor layers. Wherein, the orthographic projection of the first capacitor on the substrate and the orthographic projection of the second capacitor on the substrate at least partially overlap.

2. The array substrate according to claim 1, characterized in that, The multilayer conductor layer includes at least a first conductor layer, a fifth conductor layer, and a second conductor layer sequentially stacked along a direction away from the substrate; Wherein, the first plate of the first capacitor is located in the first conductor layer, and the second plate of the first capacitor is located in the fifth conductor layer; the second capacitor is connected in series with the first capacitor, and the first plate of the second capacitor is located in the fifth conductor layer, and the second plate of the second capacitor is located in the second conductor layer. The second plate of the first capacitor is reused as the first plate of the second capacitor; Preferably, the orthographic projection of the first electrode plate of the first capacitor on the substrate at least partially overlaps with the orthographic projection of the second electrode plate of the first capacitor on the substrate; the orthographic projection of the first electrode plate of the second capacitor on the substrate at least partially overlaps with the orthographic projection of the second electrode plate of the second capacitor on the substrate.

3. The array substrate according to claim 2, characterized in that, The pixel circuit includes a plurality of transistors, at least some of which are dual-gate transistors, and at least some of the dual-gate transistors have an intermediate node capacitor disposed between the two gates; Preferably, the dual-gate transistor includes one or more of a data write transistor, a threshold compensation transistor, a reference voltage write transistor, and a gate reset transistor. The intermediate node of the two gates of the dual-gate transistor forms the intermediate node capacitance with the second conductor layer. Alternatively, the intermediate node capacitance is formed between the middle node of the two gates of a portion of the dual-gate transistor and the second conductor layer, and the intermediate node capacitance is formed between the middle node of the two gates of a portion of the dual-gate transistor and the fifth conductor layer. Preferably, the plurality of transistors include a data write transistor, a threshold compensation transistor, a reference voltage write transistor, a gate reset transistor, a driving transistor, a light-emitting control transistor, and an anode reset transistor, wherein the driving transistor, the light-emitting control transistor, and the anode reset transistor are single-gate transistors, and the data write transistor, the threshold compensation transistor, the reference voltage write transistor, and the gate reset transistor are dual-gate transistors.

4. The array substrate according to claim 3, characterized in that, At least a portion of the dual-gate transistor includes a first gate branch and a second gate branch, the first gate branch and the second gate branch being located in the first conductor layer, and the orthogonal projections of the first gate branch and the second gate branch on the substrate overlapping once with the orthogonal projections of the active layer on the substrate to form a dual-gate structure; Alternatively, at least a portion of the dual-gate transistor includes a gate branch whose orthogonal projection on the substrate overlaps twice with the orthogonal projection of the active layer on the substrate to form a dual-gate structure.

5. The array substrate according to claim 2, characterized in that, The multilayer conductor layer further includes: A third conductor layer is disposed on the side of the second conductor layer away from the substrate; A fourth conductor layer is disposed on the side of the third conductor layer away from the substrate.

6. The array substrate according to claim 5, characterized in that, The array substrate further includes: The fan-out trace is partially located in the third conductor layer and partially located in the fourth conductor layer. The fan-out trace in the third conductor layer is connected to the fan-out trace in the fourth conductor layer. Preferably, the fan-out trace in the third conductor layer extends along a first direction, and the fan-out trace in the fourth conductor layer extends along a second direction; wherein the first direction and the second direction intersect.

7. The array substrate according to claim 5, characterized in that, The array substrate further includes: The first reset signal line is partially located in the third conductor layer and partially located in the fourth conductor layer. The first reset signal line in the third conductor layer is connected to the first reset signal line in the fourth conductor layer to form a mesh structure. The second reset signal line is partially located in the second conductor layer and partially located in the fourth conductor layer. The second reset signal line in the second conductor layer is connected to the second reset signal line in the fourth conductor layer to form a mesh structure. Preferably, the first reset signal line in the third conductor layer and the second reset signal line in the second conductor layer extend along a first direction, and the first reset signal line and the second reset signal line in the fourth conductor layer extend along a second direction; wherein the first direction and the second direction intersect.

8. The array substrate according to claim 5, characterized in that, The multilayer conductor layer further includes: A sixth conductor layer is disposed between the third conductor layer and the fourth conductor layer; The fan-out trace is partially located in the sixth conductor layer and partially located in the fourth conductor layer. The fan-out trace in the sixth conductor layer is connected to the fan-out trace in the fourth conductor layer. Preferably, the fan-out trace in the sixth conductor layer extends along a first direction, and the fan-out trace in the fourth conductor layer extends along a second direction; wherein the first direction and the second direction intersect. Preferably, the array substrate further includes: The first reset signal line is at least partially located in the sixth conductor layer; The second reset signal line is at least partially located in the sixth conductor layer; Preferably, the array substrate further includes a first interlayer dielectric layer, the third conductor layer is connected to the second conductor layer through a via of the first interlayer dielectric layer, the third conductor layer is connected to the fifth conductor layer through a via of the first interlayer dielectric layer, the third conductor layer is connected to the first conductor layer through a via of the first interlayer dielectric layer, and the third conductor layer is connected to the active layer through a via of the first interlayer dielectric layer.

9. A display panel, characterized in that, include: The array substrate as described in any one of claims 1-8.

10. A display device, characterized in that, include: The display panel as described in claim 9.

Images