Semiconductor device

Abstract

Provided is a novel semiconductor device. This semiconductor device comprises a first element layer, a second element layer located on the first element layer, and a third element layer located on the second element layer, wherein: the first element layer has a first transistor that has silicon in a channel formation region; the second element layer has a second transistor that has indium oxide in a channel formation region; the third element layer has a third transistor that has IGZO in a channel formation region; a CMOS circuit is formed by the first transistor and the second transistor; a circuit formed by the third element layer is driven at a higher voltage than the CMOS circuit; and an insulation layer that has barrier properties against hydrogen is provided between the second element layer and the third element layer.

Description

Semiconductor Devices

[0001] 1. Field of the Invention The present invention relates to a semiconductor device. The term "semiconductor device" refers to any device that can function by utilizing semiconductor characteristics.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. Therefore, more specifically, examples of the technical field of one embodiment of the present invention disclosed in this specification include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, a driving method thereof, or a manufacturing method thereof.

[0003] In recent years, semiconductor devices have been developed, and a CPU (Central Processing Unit), a memory, or other LSIs (Large Scale Integrations) are mainly used in semiconductor devices. A CPU is an assembly of semiconductor elements that have semiconductor integrated circuits (at least transistors and memories) formed into chips by processing a semiconductor wafer and on which electrodes serving as connection terminals are formed.

[0004] 2. Description of the Related Art A CPU, a memory, or other LSI semiconductor circuit (IC chip) is mounted on a circuit board, such as a printed wiring board, and is used as one of the components of various electronic devices.

[0005] Furthermore, a technique for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. Such transistors are widely applied to electronic devices such as integrated circuits and image display devices (also simply referred to as display devices). While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors containing In, Ga, and Zn have also attracted attention as other materials.

[0006] Furthermore, it is known that a transistor using an oxide semiconductor for a channel formation region (hereinafter referred to as an OS transistor) has an extremely small leakage current (also referred to as an off-state leakage current) in a non-conducting state compared to a transistor using crystalline silicon for a channel formation region (hereinafter referred to as a Si transistor). On the other hand, a Si transistor can achieve higher mobility than an OS transistor. Therefore, technological development of a semiconductor device combining an OS transistor and a Si transistor has been progressing. For example, Patent Document 1 discloses a low-power CPU that utilizes the low leakage current characteristic of an OS transistor. Furthermore, Patent Document 2 discloses a memory device that can retain stored data for a long period of time. Furthermore, a complementary metal oxide semiconductor (CMOS) circuit can be configured using an OS transistor as an n-channel transistor and a Si transistor as a p-channel transistor. By using an OS transistor and a Si transistor in combination, a semiconductor device with low power consumption and high operating speed can be realized.

[0007] JP 2012-257187 A JP 2011-151383 A

[0008] Takashi Koida, "High Mobility Transparent Conductive Film," National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Report 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0009] Semiconductor devices are being required to be smaller, consume less power, and have more functions. A semiconductor device in which a CMOS circuit is configured using a p-type Si transistor and an n-type OS transistor, and in which the Si transistor and the OS transistor are stacked, can occupy a smaller area than a semiconductor device in which the CMOS circuit is configured using only Si transistors. Because Si transistors have high field-effect mobility and a low threshold voltage (Vth), a CMOS circuit configured using only Si transistors can achieve low driving voltage and high-speed driving. However, because OS transistors have lower field-effect mobility than Si transistors, the characteristics of the Si transistors and the OS transistors are likely to be unbalanced. An OS transistor optimized for a circuit requiring a low off-leakage current has a higher threshold voltage than a Si transistor, and a CMOS circuit configured using such an OS transistor and a Si transistor may not be able to operate at high speed. Conversely, an OS transistor whose threshold voltage is lowered to balance with that of a Si transistor has a high off-leakage current, making it unsuitable for a circuit requiring a low off-leakage current.

[0010] An object of one embodiment of the present invention is to provide a novel semiconductor device or the like.An object of one embodiment of the present invention is to provide a semiconductor device or the like having a novel structure and an area occupied by the semiconductor device being reduced.An object of one embodiment of the present invention is to provide a semiconductor device or the like having a novel structure and excellent low power consumption.

[0011] Note that the description of the above-mentioned problems does not preclude the existence of other problems. Those skilled in the art will naturally find the other problems from the description of the specification, drawings, claims, etc., and can extract the other problems from the description of the specification, drawings, claims, etc. Note that one embodiment of the present invention does not necessarily solve all of these problems (the above-mentioned problems and other problems).

[0012] (1) One embodiment of the present invention is a semiconductor device including a first element layer, a second element layer over the first element layer, a first insulating layer over the second element layer that has a barrier property against hydrogen, and a third element layer over the second element layer, in which the first element layer includes a first transistor having silicon in a channel formation region, the second element layer includes a second transistor having a first oxide semiconductor in a channel formation region, and the third element layer includes a third transistor having a second oxide semiconductor in a channel formation region, in which the first oxide semiconductor includes indium oxide and the second oxide semiconductor includes indium, gallium, and zinc.

[0013] (2) In one embodiment of the present invention, the first insulating layer preferably has a higher barrier property against hydrogen than insulating layers provided in the first element layer and the second element layer.

[0014] (3) One embodiment of the present invention is a semiconductor device including a first element layer, a second element layer over the first element layer, and a third element layer over the second element layer. The first element layer includes a first semiconductor having a channel formation region of a first transistor. The second element layer includes a first oxide semiconductor having a channel formation region of a second transistor and a first insulating layer having a region over the first oxide semiconductor and having a barrier property against hydrogen. The third element layer includes a second oxide semiconductor having a channel formation region of the third transistor. The first semiconductor includes silicon, the first oxide semiconductor includes indium oxide, and the second oxide semiconductor includes indium, gallium, and zinc.

[0015] (4) In one embodiment of the present invention, the first insulating layer preferably has a higher barrier property against hydrogen than an insulating layer provided between the first semiconductor and the first oxide semiconductor.

[0016] (5) In one aspect of the present invention, the first insulating layer is preferably an insulating layer having lower hydrogen permeability than silicon oxide.

[0017] (6) In one aspect of the present invention, the first insulating layer is preferably made of aluminum oxide, hafnium oxide, or silicon nitride.

[0018] (7) In one embodiment of the present invention, it is preferable that the thickness of the gate insulating layer of the second transistor be larger than the thickness of the gate insulating layer of the first transistor, and the thickness of the gate insulating layer of the third transistor be larger than the thickness of the gate insulating layer of the second transistor.

[0019] One embodiment of the present invention can provide a novel semiconductor device or the like. Alternatively, one embodiment of the present invention can provide a semiconductor device or the like having a novel structure and a reduced area. Alternatively, one embodiment of the present invention can provide a semiconductor device or the like having a novel structure and excellent low power consumption.

[0020] Note that the description of the above effects does not preclude the existence of other effects. Those skilled in the art will naturally find the other effects from the description in the specification, drawings, claims, etc., and can extract the other effects from the description in the specification, drawings, claims, etc. Note that one embodiment of the present invention does not necessarily have all of these effects (the above effects and other effects).

[0021] FIGS. 1A and 1B are perspective views illustrating an example of a configuration of a semiconductor device. FIGS. 2A and 2B are block diagrams illustrating an example of a circuit configuration of a semiconductor device. FIGS. 3A and 3B are block diagrams illustrating an example of a circuit configuration of a semiconductor device. FIG. 4A is a perspective view illustrating an example of a configuration of a semiconductor device. FIG. 4B is a block diagram illustrating an example of a circuit configuration of a semiconductor device. FIG. 5A is a diagram illustrating an example of a circuit configuration of a CMOS circuit. FIGS. 5B and 5C are diagrams illustrating an example of a circuit configuration of a pixel circuit. FIGS. 6A, 6B, and 6C are diagrams illustrating the configuration of a transistor. FIGS. 7A, 7B, and 7C are diagrams illustrating the configuration of a transistor. FIGS. 8A and 8B are diagrams illustrating the configuration of a transistor. FIGS. 9A and 9B are diagrams illustrating the configuration of a transistor. FIGS. 10A, 10B, and 10C are diagrams illustrating the configuration of a transistor. FIGS. 11A, 11B, and 11C are diagrams illustrating the configuration of a transistor. FIGS. 12A, 12B, 12C, 12D, and 12E are diagrams illustrating example configurations of transistors. FIGS. 13A and 13B are diagrams illustrating an example of the configuration of a transistor. FIGS. 14A, 14B, 14C, 14D, and 14E are diagrams illustrating an example of the configuration of a transistor. FIG. 15 is a diagram illustrating an example of the configuration of a transistor. FIGS. 16A, 16B, 16C, 16D, and 16E are diagrams illustrating an example of the configuration of a transistor. FIGS. 17A and 17B are diagrams illustrating the carrier concentration dependence of Hall mobility. FIG. 17C is a cross-sectional view illustrating an indium oxide film. FIGS. 18A and 18B are diagrams illustrating an example of electronic equipment. FIGS. 19A and 19B are diagrams illustrating an example of electronic equipment, and FIGS. 19C, 19D, and 19E are diagrams illustrating an example of a mainframe computer. FIG. 20 is a diagram illustrating an example of space equipment. FIG. 21 is a diagram illustrating an example of a storage system applicable to a data center.

[0022] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0023] In this specification, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a semiconductor element (transistor, diode, photodiode, etc.), a circuit including a semiconductor element, a device having such a circuit, etc. It also refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component that houses a chip in a package are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, electronic devices, etc. may themselves be semiconductor devices and may also include semiconductor devices.

[0024] In the drawings and the like relating to this specification, the size, thickness, or area may be exaggerated for clarity. Therefore, the size, aspect ratio, etc. are not necessarily limited to the size, aspect ratio, etc. The drawings are merely schematic illustrations of ideal examples, and the shapes, values, etc. shown in the drawings are not limited to the shapes, values, etc.

[0025] In the configuration of the invention of the embodiment, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations may be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned. Furthermore, to make the drawings easier to understand, the illustration of some components may be omitted in perspective views, plan views, etc.

[0026] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion between components. Therefore, they do not limit the number of components or the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be referred to as "second" in another embodiment or in the claims. For example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims. Even if a term does not have an ordinal number in this specification, an ordinal number may be added in the claims to avoid confusion between components. Even if a term has an ordinal number in this specification, a different ordinal number may be added in the claims. Even if a term has an ordinal number in this specification, the ordinal number may be omitted in the claims.

[0027] In this specification, terms indicating position, such as "above," "below," "upward," or "belowward," may be used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each configuration is depicted. Therefore, the terms are not limited to those used in the specification, and can be rephrased appropriately. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing 180 degrees.

[0028] Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed on insulating layer A in direct contact with it, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0029] In this specification, terms such as "overlap" do not limit the state of the stacking order of components, etc. For example, the expression "electrode B overlapping insulating layer A" is not limited to a state in which electrode B is formed on insulating layer A, but does not exclude a state in which electrode B is formed under insulating layer A or a state in which electrode B is formed on the right (or left) side of insulating layer A, etc.

[0030] In this specification and the like, terms such as "film" and "layer" for conductors, semiconductors, and insulators can be interchangeable. For example, the term "conductive layer" can be changed to the term "conductive film" in some cases. Furthermore, terms such as "film" and "layer" can be replaced with other terms without using them. For example, the term "conductive layer" or "conductive film" can be changed to the term "conductor" in some cases, and the term "conductor" can be changed to the term "conductive layer" or "conductive film" in some cases. Furthermore, multiple conductors may be collectively referred to as a "conductive layer" or "conductive film." The same applies to semiconductors and insulators.

[0031] As used herein, "A and B are the same layer" means "A and B were formed in the same process" or "A and B were formed from the same material." For example, "A and B were formed in the same process" or "A and B were formed from the same material" means that a predetermined film (starting film) was patterned to form A and B. Patterning means, for example, forming a mask on the predetermined film (starting film), processing the predetermined film (starting film) into a predetermined shape using the mask, and then removing the mask. Therefore, the concept of "A and B were formed in the same process" or "A and B were formed from the same material" includes the concept of "A and B were formed using the same starting film." As another example, when A and B are formed using a printing method (such as an inkjet method or a letterpress printing method), "A and B were formed in the same process" or "A and B were formed from the same material" means that printing was performed so that both A and B were patterned.

[0032] In addition, in this specification, a special example of "A and B are in the same layer" will be described below. When A and B are made of different materials, and patterned A and patterned B are not in a vertically overlapping state and are provided in contact with a film in the same layer, this is also considered to be "A and B are in the same layer."

[0033] In this specification, the term "layer" when expressed as an "element layer" or the like has a different meaning from the "layer" of the above-mentioned conductor, semiconductor, or insulator. That is, the "element layer" is a structure provided with at least one or more "elements," and the structure may include multiple "insulating layers" and / or multiple "semiconductor layers" and / or multiple "conductive layers." Note that the "element" when expressed as an "element layer" or the like refers to a circuit element (e.g., a transistor, a switch, a diode, a capacitive element (also called a capacitor), a display element, a light-emitting element, a liquid crystal element, a light-receiving element, etc.) and may be composed of a part of an "insulating layer," a "semiconductor layer," or a "conductive layer" included in the structure. When the "element layer" includes multiple "elements," the multiple "elements" may be stacked, or may be composed of a part of an "insulating layer" and / or a part of a "semiconductor layer" and / or a part of a "conductive layer" of the same layer instead of being stacked. The multiple "elements" may be the same type of circuit element or different types of circuit elements. When only wiring and / or plugs are included, the layer is not called an "element layer."

[0034] In this specification and the like, a barrier insulating layer refers to an insulating layer having barrier properties. In this specification and the like, having barrier properties refers to having a property of preventing the permeation of a corresponding substance (also referred to as low permeability). For example, an insulating layer having barrier properties has a property that makes it difficult for a corresponding substance to diffuse into the insulating layer. Furthermore, for example, an insulating layer having barrier properties has a function of capturing or fixing (also referred to as gettering) a corresponding substance inside the insulating layer. Furthermore, an insulating layer having barrier properties has a function of not releasing a corresponding substance when heated.

[0035] In this specification, terms such as "electrode," "wiring," and "terminal" do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where multiple "electrodes" or "wirings" are integrally formed. Furthermore, for example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where multiple "electrodes," "wirings," "terminals," and the like are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal," and a "terminal" can be part of a "wiring" or "electrode." Furthermore, terms such as "electrode," "wiring," and "terminal" may be replaced with terms such as "region," "conductive layer," and the like, depending on the circumstances.

[0036] In this specification and the like, terms such as "wiring," "signal line," and "power line" can be interchanged. For example, the term "wiring" can be changed to the term "signal line." Also, for example, the term "wiring" can be changed to the term "power line." Also, vice versa, terms such as "signal line" and "power line" can be changed to the term "wiring." A term such as "power line" can be changed to the term "signal line." Also, vice versa, terms such as "signal line" can be changed to the term "power line." Also, a term such as "potential" applied to a wiring can be changed to the term "signal." Also, vice versa, terms such as "signal" can be changed to the term "potential."

[0037] In this specification, the term "source" refers to a source region, a source electrode, or a source wiring. The source region refers to one of two regions of a semiconductor layer that are adjacent to a channel formation region. The source electrode refers to a conductive layer that includes a portion connected to the source region.

[0038] In this specification, the term "drain" refers to a drain region, a drain electrode, or a drain wiring. The drain region refers to the other of two regions of a semiconductor layer that are adjacent to a channel formation region. The drain electrode refers to a conductive layer that includes a portion connected to the drain region.

[0039] In this specification, the term "gate" refers to a gate electrode or a gate wiring. The gate electrode is an electrode that overlaps with a semiconductor layer of a transistor and has a function of controlling the resistance between the source and drain of the transistor depending on a supplied voltage.

[0040] In this specification, one of the source and the drain of a transistor may be referred to as a "first terminal", and the other of the source and the drain of a transistor may be referred to as a "second terminal".

[0041] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes cases where the angle is -5° or more and 5° or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -15° or more and 15° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is 85° or more and 95° or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0042] Furthermore, voltage often refers to the potential difference between a certain potential and a reference potential (for example, ground potential or source potential). Therefore, voltage and potential can often be interchanged. In this specification and the like, unless otherwise specified, voltage and potential can be interchanged.

[0043] In this specification and the like, a high power supply potential VDD (hereinafter also simply referred to as "VDD") refers to a power supply potential that is higher than a low power supply potential VSS. A low power supply potential VSS (hereinafter also simply referred to as "VSS") refers to a power supply potential that is lower than a high power supply potential VDD. A ground potential GND (hereinafter also simply referred to as "GND") can also be used as VDD or VSS. For example, when VDD is GND, VSS is a lower potential than GND, and when VSS is GND, VDD is a higher potential than GND.

[0044] In this specification, the "on state" of a transistor means that the source and drain of the transistor are in a conductive state (a state in which electricity can pass), and the "off state" of a transistor means that the source and drain of the transistor are in a non-conductive state (a state that can be considered as cut off).

[0045] In this specification, the term "on-state current" refers to a current that flows between a source and a drain when a transistor is on, and the term "off-state current" refers to a current that flows between a source and a drain when a transistor is off.

[0046] In this specification and the like, potential H is a potential that turns on an n-channel field effect transistor (also referred to as an "n-type transistor") and turns off a p-channel field effect transistor (also referred to as a "p-type transistor"). Potential L is a potential that turns off an n-type transistor and turns on a p-type transistor. Therefore, potential H is a potential higher than potential L. Potential H may be equal to VDD. Potential L may be equal to VSS. Unless otherwise specified, the transistors described in this specification are enhancement-type (normally-off) transistors.

[0047] In addition, in drawings and the like, to clearly show the potential of wirings, electrodes, etc., "H" indicating a potential H or "L" indicating a potential L may be added next to the wirings, electrodes, etc. Furthermore, "H" or "L" may be enclosed in letters around wirings, electrodes, etc. in which a potential change has occurred. Furthermore, when a transistor is in an off state, an "x" symbol may be added over the transistor. Furthermore, an arrow may be added to indicate the direction of current flow.

[0048] In this specification, when referring to counting values ​​and measurement values, terms such as "identical," "same," "equal," or "uniform" (including synonyms thereof) are used, this includes an error of plus or minus 10%, unless otherwise specified.

[0049] In addition, in the drawings and the like relating to this specification, arrows indicating the X direction, Y direction, and Z direction may be used. In this specification and the like, the "X direction" refers to the direction along the X axis, and the forward direction and the reverse direction may not be distinguished unless explicitly stated. The same applies to the "Y direction" and the "Z direction." The X direction, Y direction, and Z direction are directions that intersect with each other. For example, the X direction, Y direction, and Z direction are directions that are perpendicular to each other. In this specification and the like, one of the X direction, Y direction, and Z direction may be referred to as the "first direction" or "first direction." The other may be referred to as the "second direction" or "second direction." The remaining one may be referred to as the "third direction" or "third direction." In the drawings and the like relating to this specification, the X direction and Y direction are parallel to the surface of the substrate, and the Z direction is perpendicular to the surface of the substrate.

[0050] Generally, a "capacitance" has a configuration in which two electrodes face each other with an insulator (dielectric) interposed therebetween. In this specification, etc., the term "capacitance element" includes the above-mentioned "capacitance." That is, in this specification, etc., the term "capacitance element" includes a configuration in which two electrodes face each other with an insulator interposed therebetween, a configuration in which two wires face each other with an insulator interposed therebetween, or a configuration in which two wires are arranged with an insulator interposed therebetween. Note that in this specification, one of the two electrodes may be referred to as a first electrode or a first terminal, and the other may be referred to as a second electrode or a second terminal.

[0051] In this specification, when the same symbol is used for multiple elements, and particularly when it is necessary to distinguish between them, an identifying symbol such as “A”, “b”, “_1”, "[n]”, or "[m, n]” may be added to the symbol.

[0052] In this specification, "connection" includes, as an example, "electrical connection." Note that the term "electrical connection" is sometimes used to define the connection relationship between circuit elements as an object. Furthermore, "electrical connection" includes "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the intervention of a circuit element (e.g., a transistor, a switch, etc.; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected via one or more circuit elements.

[0053] For example, assuming that a circuit including A and B is operating, if there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B, then it can be defined that "A and B are indirectly connected" as objects. Note that even if there is a time during the operation of the circuit when no electrical signal is exchanged or an interaction of electrical potential occurs between A and B, it can still be defined that "A and B are indirectly connected" as long as there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B.

[0054] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where it cannot be said that "A and B are indirectly connected" is when an insulator is present in the path from A to B. Specifically, there are cases where a capacitive element is connected between A and B, and cases where a gate insulating layer of a transistor is present between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of the transistor are indirectly connected."

[0055] Another example of a case where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between one transistor and another transistor from a power supply, GND, etc.

[0056] Embodiment 1 A semiconductor device 100A according to one embodiment of the present invention will be described with reference to the drawings.

[0057] 1A and 1B are perspective views of a semiconductor device 100A according to one embodiment of the present invention. The semiconductor device 100A includes an element layer 10, an element layer 20 over the element layer 10, and an element layer 30 over the element layer 20. FIG. 1A illustrates a case where a barrier insulating layer 50 is provided between the element layer 20 and the element layer 30. FIG. 1B illustrates a case where the barrier insulating layer 50 is included in the element layer 20 or the element layer 30. The barrier insulating layer 50 is an insulating layer that has a barrier property against hydrogen.

[0058] The element layer 10 is a structure including a transistor M1 having silicon in a channel formation region. The element layer 10 may include a substrate. If the substrate is a semiconductor substrate, the channel formation region of the transistor M1 may be formed on the surface of the semiconductor substrate. If the substrate is other than a semiconductor substrate, the channel formation region of the transistor M1 may be formed in a semiconductor film. The transistor M1 is preferably a p-type transistor. The element layer 10 may include wiring and / or plugs.

[0059] The element layer 20 is a structure including a transistor M2 having an oxide semiconductor in a channel formation region. The oxide semiconductor used in the transistor M2 is, in particular, crystalline indium oxide (InO Ｘ) is preferable. Details of indium oxide will be described later in embodiment 4. The element layer 20 may include wirings and / or plugs. In FIG. 1A, the barrier insulating layer 50 is provided between the element layer 20 and the element layer 30. However, as shown in FIG. 1B, the barrier insulating layer 50 may be included in the element layer 20. In that case, the barrier insulating layer 50 is provided above the indium oxide included in the transistor M2. The transistor M2 is preferably an n-channel transistor.

[0060] The element layer 30 is a structure including a transistor M3 having an oxide semiconductor in a channel formation region. The oxide semiconductor used in the transistor M3 is preferably a crystalline oxide semiconductor. The oxide semiconductor used in the transistor M3 is preferably a metal oxide having a band gap wider than that of indium oxide. By using a metal oxide having a band gap wider than that of indium oxide for the semiconductor layer, the off-state current of the transistor M3 can be reduced more than that of the transistor M2. Details of the crystalline oxide semiconductor will be described later in Embodiment 3. The element layer 30 may include wirings and / or plugs. Although the barrier insulating layer 50 is provided between the element layer 20 and the element layer 30 in FIG. 1A , the barrier insulating layer 50 may be included in the element layer 30 as shown in FIG. 1B . In this case, the barrier insulating layer 50 is provided below the oxide semiconductor included in the transistor M3. The transistor M3 is preferably an n-channel transistor.

[0061] Because the transistor M1 has silicon in the channel formation region, it needs to be subjected to a process (also called hydrogenation) in which dangling bonds of silicon are terminated with hydrogen. The hydrogenation process allows hydrogen to diffuse into silicon, terminating the dangling bonds in the silicon, thereby improving the reliability of the transistor M1. The hydrogenation process involves heat treatment of the insulating layer containing hydrogen in the element layer 10, so that some of the hydrogen in the insulating layer is released and supplied to the transistor M1.

[0062] Hydrogen and water can cause fluctuations in the electrical characteristics of the oxide semiconductor of the transistor M3. That is, hydrogen is thought to be absorbed into oxygen vacancies (Vo) in the oxide semiconductor, which generates carriers. Therefore, it is preferable not to provide an insulating layer that releases hydrogen by heat treatment around the transistor M3.

[0063] On the other hand, as described in Embodiment 4, the indium oxide of the transistor M2 is likely to have reduced oxygen vacancies, and therefore hydrogen and water are unlikely to be factors that cause fluctuations in electrical characteristics. Therefore, the barrier insulating layer 50, which is an insulating film having barrier properties against hydrogen, is provided between the element layer 20 and the element layer 30, but does not necessarily need to be provided between the element layer 10 and the element layer 20. Alternatively, the barrier insulating layer 50 is provided between the indium oxide of the transistor M2 and the oxide semiconductor of the transistor M3, but does not necessarily need to be provided between the semiconductor layer of the transistor M1 and the indium oxide of the transistor M2. Because the barrier insulating layer 50 does not necessarily need to be provided between the element layer 10 and the element layer 20 or between the semiconductor layer of the transistor M1 and the indium oxide of the transistor M2, the manufacturing process of the semiconductor device 100A can be simplified. In other words, the barrier insulating layer 50 is an insulating layer with higher barrier properties against hydrogen than the insulating layer provided between the element layer 10 and the element layer 20, or between the semiconductor layer of the transistor M1 and the indium oxide of the transistor M2.

[0064] The barrier insulating layer 50 may be made of an insulating material that has the function of suppressing the diffusion or permeation of impurities such as water or hydrogen. The barrier insulating layer 50 may be made of a film that has lower permeability to water or hydrogen than a silicon oxide film or a silicon oxynitride film. Alternatively, the barrier insulating layer 50 may be made of an insulating material that does not release impurities such as water or hydrogen when heated. The barrier insulating layer 50 may be made of a film that has lower water or hydrogen release properties when heated than a silicon oxide film or a silicon oxynitride film. For example, aluminum oxide, hafnium oxide, silicon nitride, or the like may be used as the barrier insulating layer 50. This can suppress the diffusion of impurities such as water or hydrogen from the element layer 10 and / or the element layer 20 to the transistor M3 included in the element layer 30. The barrier insulating layer 50 is provided on the entire surface of the element layer 20 or the element layer 30 except for the portions where wiring and / or plugs are provided.

[0065] FIG. 2A is a block diagram illustrating the configuration of a semiconductor device 100A. As shown in FIG. 2A, the semiconductor device 100A includes a first circuit 110 and a second circuit 120. The first circuit 110 includes a p-type transistor M1 and an n-type transistor M2, forming a CMOS circuit. The second circuit 120 includes a transistor M3, and is driven at a higher drive voltage than the first circuit 110. The drive voltage of the first circuit 110 is preferably 1.5 V or less. The drive voltage of the second circuit 120 is preferably greater than 1.5 V and less than 3.3 V. A register 310 is formed by a portion of the first circuit 110 and a portion of the second circuit 120.

[0066] 5A shows an example of a CMOS circuit applicable to the first circuit 110. FIG. 5A shows an inverter circuit. The inverter circuit is a CMOS circuit configured with a p-type transistor M1 and an n-type transistor M2. One of the source or drain of the transistor M1 is electrically connected to VDD, and one of the source or drain of the transistor M2 is electrically connected to VSS. The gates of the transistors M1 and M2 are electrically connected to VIN, and the other of the source or drain of the transistor M1 and M2 is electrically connected to VOUT.

[0067] Since the transistor M2 and the transistor M1 constitute a CMOS circuit, they are required to have a high on-state current and a low threshold voltage. Therefore, the thickness of the gate insulating layer of the transistor M2 is preferably formed to be approximately the same as the thickness of the gate insulating layer of the transistor M1. Specifically, the thickness of the gate insulating layer of the transistor M2 is preferably 50% or more, preferably 80% or more, more preferably 90% or more, and 600% or less, preferably 300% or less, and more preferably 150% or less of the thickness of the gate insulating layer of the transistor M1. By setting the gate insulating layer of the transistor M2 to such a thickness, the withstand voltages of the transistors M1 and M2 become close to each other, which makes it easier to balance the electrical characteristics of the transistors M1 and M2. This allows the drive voltage of the first circuit 110 to be lowered, enabling the first circuit 110 to operate at high speed. In this specification, the film thickness of the gate insulating layer refers to the equivalent oxide thickness (EOT) of an insulator that functions as a gate insulating film.

[0068] Because the n-channel transistor M2 and the p-channel transistor M1 form a CMOS circuit, the threshold voltage of the transistor M2 is preferably balanced with the threshold voltage of the transistor M1. Specifically, assuming that the threshold voltage of the transistor M1 is Vth_M1 and the threshold voltage of the transistor M2 is Vth_M2, Vth_M2 is preferably 60% or more, preferably 80% or more, more preferably 90% or more, and 140% or less, preferably 120% or less, and more preferably 110% or less of |Vth_M1| (the absolute value of Vth_M1). Here, Vth_M1 is a negative value, and Vth_M2 is a positive value. Note that the threshold voltage of the transistor M2 is preferably adjusted with an emphasis on the balance of electrical characteristics with the transistor M1, even if the off-state current (also called cutoff current) when the voltage between the gate electrode and the source electrode is 0 V is somewhat high. This allows the drive voltage of the first circuit to be lowered, enabling the first circuit to operate at high speed.

[0069] Furthermore, because the first circuit 110 is driven at a lower drive voltage than the second circuit 120, the gate insulating layer of transistor M2 is preferably formed thinner than the gate insulating layer of transistor M3. Because the second circuit 120 is driven at a higher drive voltage than the first circuit 110, transistor M3 is required to have a higher breakdown voltage than transistor M2. Therefore, the gate insulating layer of transistor M3 is preferably formed thicker than the gate insulating layer of transistor M2. By forming the gate insulating layer of transistor M3 thicker than the gate insulating layer of transistor M2, the drive voltage of the second circuit 120 can be increased. Because the drive voltage of the second circuit 120 is high, the threshold voltage Vth_M3 of transistor M3 may be adjusted to be higher than the threshold voltage Vth_M2 of transistor M2. Therefore, the cutoff current of transistor M3 can be adjusted to a value sufficiently lower than the cutoff current of transistor M2. As a result, the second circuit 120 can be a circuit requiring a low off-leakage current.

[0070] 2B is a diagram showing an example of a circuit configuration of the register 310. The register 310 is configured by part of the first circuit 110 and part of the second circuit 120. The register 310 includes a scan flip-flop 320 (volatile register), a data retention circuit 330, and a transistor 332. The scan flip-flop 320 and the transistor 332 are provided in the first circuit 110, and the data retention circuit 330 is provided in the second circuit 120. The scan flip-flop 320 includes a selector 321 and a flip-flop 322. The data retention circuit 330 includes a memory circuit 331.

[0071] Each of the memory circuits 331 includes a transistor 333, a transistor 334, and a capacitor 335. The transistor 333 is provided between the capacitor 335 and a terminal Q. The transistor 334 is provided between the capacitor 335 and a terminal SD. In each of the memory circuits 331, one electrode of the capacitor 335 is illustrated as one of nodes SN[1] to SN[k]. The other electrode of the capacitor 335 is connected to a wiring CL. Each of the memory circuits 331 is connected to the terminal Q and the terminal SD. In the memory circuits 331, a terminal (wiring) connected to the terminal Q is referred to as an input terminal, and a terminal (wiring) connected to the terminal SD is referred to as an output terminal.

[0072] Output terminal Q of flip-flop 322 Ｆ is connected to the input terminal of the data holding circuit 330 (memory circuit 331) and the input terminal D of the flip-flop 322. Ｆ are connected to the output terminals of the data holding circuit 330 (memory circuit 331).

[0073] The signal BK[k:1] is a signal that controls saving (also referred to as saving, storing, or backing up) data held in the flip-flop 322 in the scan flip-flop 320. By saving the data, the data held in the flip-flop 322 is held in one of the multiple memory circuits 331 in the data holding circuit 330. Note that the signal BK[k:1] may be expressed as signals BK[1] to BK[k].

[0074] The signal RE is a circuit that controls loading (also referred to as restoration, restore, or recovery) of data held in one of the plurality of memory circuits 331 in the data holding circuit 330. By loading the data, the data held in one of the plurality of memory circuits 331 in the data holding circuit 330 is held in the flip-flop 322 in the scan flip-flop 320. Note that the signal RE[k:1] may be expressed as signals RE[1] to RE[k].

[0075] The signal SE is a switching signal for the selector 321. The clock signal is a signal for operating the flip-flop 322.

[0076] The register 310 holds data input from terminal D or data input from terminal SD in the scan flip-flop 320 and outputs the data from terminal Q in response to the clock signal CLK. The data of the scan flip-flop 320 output from terminal Q is saved in one of a plurality of memory circuits 331 included in the data holding circuit 330 under the control of a signal BK[k:1]. The data of one of the plurality of memory circuits 331 included in the data holding circuit 330 is loaded into terminal SD of the scan flip-flop 320 under the control of a signal RE[k:1].

[0077] The selector 321 has a function of transmitting the signal of the terminal D or the terminal SD to the flip-flop 322 in response to the signal SE. The terminal D is a terminal that supplies data input from outside the register 310. The terminal SD is a terminal that supplies data input from the data holding circuit 330 or data input from the terminal SD_IN that supplies scan test data. The data input from the terminal SD_IN is supplied via a transistor 332 whose conductive state or non-conductive state is controlled by the signal BK[0].

[0078] In the memory circuit 331, one of signals BK[1] to BK[k] is applied to the gate of the transistor 333, and one of signals RE[1] to RE[k] is applied to the gate of the transistor 334. The signals BK[1] to BK[k] are signals for saving data held in the flip-flop 322 in one of the plurality of memory circuits 331. The signals RE[1] to RE[k] are signals for loading data held in one of the plurality of memory circuits 331 into the flip-flop 322.

[0079] 2B illustrates a D flip-flop as the flip-flop 322, but is not limited to this. Flip-flops available in a standard circuit library can be applied. The flip-flop 322 outputs a D flip-flop at its input terminal in response to the clock signal CLK. Ｆ The data is stored and output to the output terminal Q Ｆ The signal is output to terminal Q.

[0080] 2B , a circuit such as the scan flip-flop 320 includes a p-type transistor M1 and an n-type transistor M2, forming a CMOS circuit. The transistor 332 may be formed of the transistor M2, i.e., a transistor having indium oxide in its channel formation region. A circuit using the transistors M1 and M2 can be driven at a low drive voltage and can achieve high-speed operation.

[0081] The data retention circuit 330 is formed of a transistor having an oxide semiconductor in its channel formation region. A transistor having an oxide semiconductor in its channel formation region has a characteristic of extremely low off-state current. Therefore, when a transistor having an oxide semiconductor in its channel formation region is used as the transistor provided in the data retention circuit 330, a potential corresponding to data written to the scan flip-flop 320 can be retained for a long period of time. Since data is rewritten by charging and discharging the capacitor 335, the memory circuit 331 is theoretically free from restrictions on the number of rewrites and can write and read data with low energy. By configuring the data retention circuit 330 as a circuit including a transistor having an oxide semiconductor in its channel formation region, the data retention circuit 330 can be provided overlapped with circuits other than the data retention circuit 330, such as the scan flip-flop 320.

[0082] <Modification 1> Next, a modification of the semiconductor device 100A will be described with reference to Fig. 3. To reduce repetition in the description, the following mainly describes matters that are different from the semiconductor device 100A shown in Fig. 2. For explanations not described below, the explanation of the semiconductor device 100A shown in Fig. 2 can be referred to.

[0083] FIG. 3A is a block diagram illustrating the configuration of a semiconductor device 100A. As shown in FIG. 3A, the semiconductor device 100A includes a first circuit 110 and a third circuit 130. The first circuit 110 includes a p-type transistor M1 and an n-type transistor M2, forming a CMOS circuit. The third circuit 130 includes a transistor M2 and a transistor M3. In the third circuit 130, the drive voltage (gate voltage) supplied to the transistor M3 is higher than the drive voltage supplied to the transistor M2, and the drive voltage supplied to the transistor M2 may be the same as that of the first circuit 110. The drive voltage supplied to the transistor M3 is preferably greater than 1.5 V and less than or equal to 3.3 V. A memory device 410 is configured by a portion of the first circuit 110 and a portion of the third circuit 130.

[0084] 3B is a diagram showing an example of a circuit configuration of the memory device 410. The first circuit 110 includes a read circuit 311, and the third circuit 130 includes a memory cell 300 (a memory element).

[0085] 3B includes a source line SL, a bit line BL, a first signal line S1, a second signal line S2, a word line WL, a transistor 301, a transistor 302, a transistor 303, and a capacitor 305. The transistors 301 and 303 are transistors M2 whose channel formation regions are formed using indium oxide, and the transistor 302 is transistor M3 whose channel formation region is formed using an oxide semiconductor. The memory cell 300 may be a multi-valued type.

[0086] Here, the gate electrode of the transistor 301 is connected to one of the source electrode or drain electrode of the transistor 302. The source electrode of the transistor 301 is connected to a source line SL, and the drain electrode of the transistor 301 is connected to a source electrode of the transistor 303. The bit line BL is connected to the drain electrode of the transistor 303. The first signal line S1 is connected to the other of the source electrode or drain electrode of the transistor 302. The second signal line S2 is connected to the gate electrode of the transistor 302. The word line WL is connected to the gate electrode of the transistor 303. One electrode of the capacitor 305 is connected to the gate electrode of the transistor 301 and to one of the source electrode or drain electrode of the transistor 302. A predetermined potential is applied to the other electrode of the capacitor 305. The predetermined potential is, for example, GND. The node connected to the gate electrode of the transistor 301 is referred to as node A.

[0087] 3B will be described. Note that the operation of the memory cell 300 will be described here using a quaternary type as an example of the operation of the memory cell 300. The four states of the quaternary type of the memory cell 300 are assumed to be data "00b", "01b", "10b", and "11b", and the potentials of node A at that time are assumed to be V00, V01, V10, and V11 (V00<V01<V10<V11), respectively.

[0088] When writing to the memory cell 300, the source line SL is set to 0 [V], the word line WL is set to 0 [V], the bit line BL is set to 0 [V], and the second signal line S2 is set to V2 [V] (V2 > V11). When writing data "00b", the first signal line S1 is set to V00 [V]. When writing data "01b", the first signal line S1 is set to V01 [V]. When writing data "10b", the first signal line S1 is set to V10 [V]. When writing data "11b", the first signal line S1 is set to V11 [V]. At this time, the transistor 303 is in an off state, and the transistor 302 is in an on state. The transistor 302 is a transistor M3, and a potential (V2) higher than V11 [V] can be applied to the gate electrode. Therefore, the on-state current of the transistor 302 becomes high, high-speed writing can be realized, and the potential of the node A can be set to the potential of the first signal line S1. Note that, when writing is completed, before the potential of the first signal line S1 changes, the second signal line S2 is set to 0 V, and the transistor 302 is turned off.

[0089] As a result, after writing the data "00b", "01b", "10b", and "11b", the potentials of the node A become V00 [V], V01 [V], V10 [V], and V11 [V], respectively. Charge corresponding to the potential of the first signal line S1 is accumulated in the node A. However, because the off-state current of the transistor 302 is extremely small or substantially zero, the potential of the gate electrode of the transistor 301 is held for a long time.

[0090] When reading the memory cell 300, first, the bit line BL is precharged to Vpc [V]. Then, the source line SL is set to Vs_read [V], the word line WL is set to VW [V], the second signal line S2 is set to 0 [V], and the first signal line S1 is set to 0 [V]. At this time, the transistor 303 is in an on state and the transistor 302 is in an off state.

[0091] As a result, a current flows from the source line SL to the bit line BL, and the bit line BL is charged to a potential expressed as (potential of node A) - (threshold voltage Vth of transistor 301). As a result, the bit line BL potential becomes V00 - Vth, V01 - Vth, V10 - Vth, and V11 - Vth for data "00b", "01b", "10b", and "11b", respectively. A read circuit connected to the bit line BL can read out data "00b", "01b", "10b", and "11b" from the difference in these potentials.

[0092] 3B, the readout circuit 311 includes a p-type transistor M1 and an n-type transistor M2, forming a CMOS circuit. A circuit using the transistors M1 and M2 can be driven at a low drive voltage and can achieve high-speed operation.

[0093] The memory cell 300 includes a transistor M2 (a transistor having indium oxide in a channel formation region) and a transistor M3 (a transistor having an oxide semiconductor in a channel formation region).

[0094] A circuit using the transistor M2 can be driven at a low driving voltage and can achieve high-speed reading. The transistor M3 can handle a high driving voltage (gate voltage) and can perform high-speed reading and writing. The transistor M3 also has a characteristic of having a very low off-state current. Therefore, when the transistor M3 is used as the transistor 302 in the memory cell 300, the potential of the node A can be maintained for a long period of time. Since data is rewritten by charging and discharging the capacitor 305, the memory cell 300 is theoretically capable of writing and reading data with low energy and has no limit on the number of times it can be rewritten.

[0095] <Modification 2> Next, another modification of the semiconductor device 100A will be described with reference to Fig. 4. To reduce repetition in the description, the following mainly describes matters different from the semiconductor device 100A shown in Fig. 1 and Fig. 2. For explanations not described below, the explanation of the semiconductor device 100A shown in Fig. 2 can be referred to.

[0096] 4A and 4B illustrate a semiconductor device 100B, which is a modification of the semiconductor device 100A. Fig. 4A is a perspective view of the semiconductor device 100B according to one embodiment of the present invention. Fig. 4B is a block diagram illustrating the configuration of the semiconductor device 100B.

[0097] The semiconductor device 100B shown in FIG. 4A further includes an element layer 40 in addition to the semiconductor device 100A shown in FIG. 1A. The element layer 40 is a structure including a transistor M4 having an oxide semiconductor in a channel formation region. The oxide semiconductor used in the transistor M4 is preferably an oxide semiconductor having crystallinity. Details of the oxide semiconductor having crystallinity will be described later in embodiment 3. The element layer 40 may include wiring and / or plugs. The element layer 40 may further include a barrier insulating layer 50.

[0098] As shown in FIG. 4B , the semiconductor device 100B further includes a fourth circuit 140 in addition to the semiconductor device 100A. The semiconductor device 100B also includes a second circuit 120 and / or a third circuit. Because the fourth circuit 140 is driven at a higher drive voltage than the second circuit 120 and the third circuit 130, the transistor M4 is required to have a higher breakdown voltage than the transistor M3. Therefore, the gate insulating layer of the transistor M4 is formed thicker than the gate insulating layer of the transistor M3. By forming the gate insulating layer of the transistor M4 thicker than the gate insulating layer of the transistor M3, the drive voltage of the fourth circuit 140 can be made higher than the drive voltages of the second circuit 120 and the third circuit 130. Because the drive voltage of the fourth circuit 140 is high, the threshold voltage Vth_M4 of the transistor M4 may be adjusted to be higher than the threshold voltage Vth_M3 of the transistor M3. Therefore, the cutoff current of the transistor M4 can be adjusted to a value sufficiently lower than the cutoff current of the transistor M3. As a result, the fourth circuit 140 can be used with a higher drive voltage and requires a lower off-leakage current than the second circuit 120 and the third circuit 130. The drive voltage supplied to the fourth circuit 140 is preferably 10 V or higher.

[0099] The semiconductor device 100B can be a display device. The fourth circuit 140 includes a pixel circuit 510, and the pixel circuit 510 includes a display element. The display element can be a liquid crystal element or a light-emitting element. The light-emitting element can be a self-luminous display element such as an organic EL element, a micro LED, or a quantum-dot light-emitting diode (QLED).

[0100] 5B and 5C are diagrams showing an example of a circuit configuration of a pixel circuit 510. A pixel circuit 510A shown in FIG. 5B includes a transistor 501, a transistor 502, and a capacitor 503. FIG. 5B also shows a light-emitting element 601 connected to the pixel circuit 510A. A wiring DL, a wiring GL, a wiring ANO, and a wiring VCOM are electrically connected to the pixel circuit 510A. A pixel circuit 510B shown in FIG. 5C includes a transistor 504 in addition to the pixel circuit 510A. A wiring VO is electrically connected to the pixel circuit 510B. Although FIGS. 5B and 5C show an example of the pixel circuit 510 including two or three transistors, one embodiment of the present invention is not limited thereto. The transistor 501, the transistor 502, and the transistor 504 can be formed using a transistor M4.

[0101] The second circuit 120 may include a data retention circuit 330. The third circuit 130 may include a memory cell 300. The first circuit 110 may include a scan flip-flop 320 and / or a read circuit 311. The first circuit 110 may include a driver circuit and / or a CPU, etc.

[0102] In the semiconductor device 100B, the first circuit 110 includes a p-type transistor M1 and an n-type transistor M2, forming a CMOS circuit. A circuit using the transistors M1 and M2 can be driven at a low drive voltage and can achieve high-speed operation.

[0103] The semiconductor device 100B includes a data retention circuit 330 and / or a memory cell 300. The data retention circuit 330 and the memory cell 300 each include a transistor M3 (a transistor having an oxide semiconductor in a channel formation region) and can retain data for a long period of time.

[0104] The fourth circuit 140 needs to withstand the drive voltage for driving the display element, so the thickness of the gate insulating layer of the transistor M4 is set to a value that can withstand the drive voltage of the display element.

[0105] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiment modes and examples.

[0106] Embodiment 2 In this embodiment, a transistor that can be used for a semiconductor device according to one embodiment of the present invention will be described.

[0107] Note that the structural example of the transistor described in this embodiment is an example in which the transistor is provided over a substrate as an example in the case where the transistor is provided in the element layer 10. When the transistor described in this embodiment is provided in the element layer 20 or the element layer 30, the substrate is included in the element layer 10.

[0108] 6A is a plan view of a transistor 200A that can be used for a semiconductor device according to one embodiment of the present invention. The transistor 200A is an example of a planar transistor. In this specification, a planar transistor refers to a transistor in which a source electrode and a drain electrode are located at the same height or approximately the same height and a current flowing through a semiconductor has a lateral component.

[0109] Fig. 6B is a cross-sectional view taken along the line A1-A2 indicated by the dashed dotted line in Fig. 6A. Fig. 6C is a cross-sectional view taken along the line A3-A4 indicated by the dashed dotted line in Fig. 6A. Note that some elements are omitted from the plan view of Fig. 6A for clarity. Some elements may also be omitted from other plan views.

[0110] The transistor 200A has an insulating layer 202 over a substrate 201 and a semiconductor layer 203 over the insulating layer 202. The transistor 200A also has an insulating layer 204 over the insulating layer 202 and the semiconductor layer 203. The transistor 200A also has a conductive layer 205 over the insulating layer 204. The semiconductor layer 203 and the conductive layer 205 have regions that overlap with each other with the insulating layer 204 interposed therebetween.

[0111] The semiconductor layer 203 has a region 203a, a channel formation region 203b, and a region 203c. The region 203a functions as either a source region or a drain region. The region 203c functions as the other of the source region and the drain region. In the semiconductor layer 203, a region overlapping with the conductive layer 205 functions as the channel formation region 203b. Therefore, the conductive layer 205 functions as the gate electrode of the transistor 200A. The insulating layer 204 functions as a gate insulating layer of the transistor 200A.

[0112] The length of the channel formation region 203b in the X direction is the channel length L of the transistor 200A (see FIG. 6B), and the length of the channel formation region 203b in the Y direction is the channel width W of the transistor 200A (see FIG. 6C).

[0113] An insulating layer 206 is provided over the insulating layer 204 and the conductive layer 205. An opening 207a is provided in the insulating layer 204 and the insulating layer 206 in a region overlapping with a region 203a of the semiconductor layer 203. An opening 207b is provided in the insulating layer 204 and the insulating layer 206 in a region overlapping with a region 203c of the semiconductor layer 203.

[0114] A conductive layer 208a is provided over the insulating layer 206 and the opening 207a, and a conductive layer 208b is provided over the insulating layer 206 and the opening 207b. The conductive layer 208a is connected to the region 203a of the semiconductor layer 203 at the bottom of the opening 207a. The conductive layer 208b is connected to the region 203c of the semiconductor layer 203 at the bottom of the opening 207b. Thus, the conductive layer 208a functions as one of the source and drain electrodes of the transistor 200A, and the conductive layer 208b functions as the other of the source and drain electrodes of the transistor 200A.

[0115] In addition, an insulating layer 209 is provided over the insulating layer 206 and the conductive layer 208 (the conductive layer 208a and the conductive layer 208b).

[0116] 7A is a plan view of a transistor 200B that can be used for a semiconductor device of one embodiment of the present invention. The transistor 200B is a variation of the transistor 200A. To avoid repetition of description, differences between the transistor 200B and the transistor 200A will be mainly described.

[0117] Fig. 7B is a cross-sectional view taken along the line A1-A2 indicated by the dashed dotted line in Fig. 7A. Fig. 7C is a cross-sectional view taken along the line A3-A4 indicated by the dashed dotted line in Fig. 7A.

[0118] The transistor 200B differs from the transistor 200A in that a conductive layer 219 is provided between the substrate 201 and the insulating layer 202. The conductive layer 219 functions as a backgate electrode of the transistor 200B. Therefore, the conductive layer 219 overlaps with the channel formation region 203b. The conductive layer 219 preferably extends beyond the end of the channel formation region 203b. That is, the conductive layer 219 preferably covers the channel formation region 203b. Covering the channel formation region 203b with the conductive layer 219 can enhance the electric field shielding effect described in the above embodiment.

[0119] 8A is a plan view of a transistor 200C that can be used in a semiconductor device according to one embodiment of the present invention, and FIG. 8B is a cross-sectional view taken along the line A1-A2 indicated by a dashed dotted line in FIG. 8A.

[0120] The transistor 200C includes an insulating layer 202 over a substrate 201 and a conductive layer 255 over the insulating layer 202. The transistor 200C also includes an insulating layer 257 over the conductive layer 255, an insulating layer 258 over the insulating layer 257, and an insulating layer 259 over the insulating layer 258. Note that in this specification, the insulating layer 257, the insulating layer 258, and the insulating layer 259 may be collectively referred to as an insulating layer 256 or a spacer layer. The transistor 200C also includes a conductive layer 261 over the insulating layer 259.

[0121] An opening 262 penetrating the conductive layer 261, the insulating layer 259, the insulating layer 258, and the insulating layer 257 is provided in a region overlapping with part of the conductive layer 255. A semiconductor layer 263 is provided to cover the inner wall of the opening 262.

[0122] The semiconductor layer 263 has a region overlapping with the bottom of the opening 262 and a region overlapping with the side surface of the opening 262. That is, the semiconductor layer 263 has a region in contact with the insulating layer 256 inside the opening 262. The semiconductor layer 263 also has a region in contact with the conductive layer 255 and a region in contact with the conductive layer 261 inside the opening 262.

[0123] An insulating layer 264 is provided over the insulating layer 259, the conductive layer 261, and the semiconductor layer 263. A conductive layer 265 is provided over the insulating layer 264. The conductive layer 265 has a region overlapping with the semiconductor layer 263. The conductive layer 265 has a region overlapping with the semiconductor layer 263 with the insulating layer 264 interposed therebetween.

[0124] The insulating layer 264 and the conductive layer 265 each have a region overlapping with the opening 262. The insulating layer 264 and the conductive layer 265 each have a region overlapping with the inside of the opening 262. Inside the opening 262, the semiconductor layer 263 has a region overlapping with the conductive layer 265 with the insulating layer 264 interposed therebetween and a region overlapping with a side surface of the opening 262 (a side surface of the insulating layer 256).

[0125] Furthermore, an insulating layer 266 is provided on the insulating layer 264. Note that the upper surface of the insulating layer 266 is preferably flat. Alternatively, it is preferable that the heights (positions in the Z direction) of the upper surfaces of the insulating layer 266 and the conductive layer 265 are the same or approximately the same. For example, the flatness of the upper surface of the insulating layer 266 can be improved by performing chemical mechanical polishing (CMP) processing or the like. Furthermore, by performing CMP processing, the positions of the upper surfaces of the insulating layer 266 and the conductive layer 265 can be made to be the same or approximately the same. By performing CMP processing, unevenness on the sample surface can be reduced, and the coverage of the insulating layer and conductive layer to be formed subsequently can be improved.

[0126] When an oxide semiconductor is used for the semiconductor layer 263, the conductive layer 255 in contact with the semiconductor layer 263 and the conductive layer 261 in contact with the semiconductor layer 263 are preferably formed using a conductive material that makes the oxide semiconductor n-type. For example, a conductive material containing nitrogen may be used. For example, a conductive material containing titanium or tantalum and nitrogen may be used. Alternatively, another conductive material may be provided over the conductive material containing nitrogen.

[0127] When an oxide semiconductor is used for the semiconductor layer 263, it is preferable to use a material containing oxygen and in which hydrogen is reduced for the insulating layer 258. For example, a material containing silicon and oxygen may be used. Specifically, silicon oxide, silicon oxynitride, or the like may be used. Since hydrogen is an impurity element in an oxide semiconductor, contact between the semiconductor layer 263, which is an oxide semiconductor, and the insulating layer 258 in which hydrogen is reduced makes it difficult for the semiconductor layer 263 to become n-type. Furthermore, contact between the semiconductor layer 263, which is an oxide semiconductor, and the insulating layer 258 containing oxygen reduces oxygen vacancies in the semiconductor layer 263, thereby stabilizing the characteristics of the transistor and improving its reliability.

[0128] In the case where an oxide semiconductor is used for the semiconductor layer 263, the insulating layer 258 preferably contains excess oxygen. In this specification, excess oxygen refers to oxygen that is released by heating. A material that releases oxygen by heating is a material that releases oxygen in an amount of 1.0×10 converted into oxygen atoms as determined by thermal desorption spectroscopy (TDS) analysis. １８ atoms / cm ３ or more, preferably 1.0 × 10 １９ atoms / cm ３ More preferably, 2.0 × 10 １９ atoms / cm ３ or more or 3.0 x 10 ２０ atoms / cm ３ The surface temperature of the film during the TDS analysis is preferably in the range of 100°C to 700°C or 100°C to 400°C.

[0129] Furthermore, when a material containing excess oxygen is used for the insulating layer 258, it is preferable to use a material that is impermeable to oxygen for the insulating layers 257 and 259. Examples of materials that are impermeable to oxygen include an oxide containing one or both of aluminum and hafnium, a silicon nitride, and the like. By using a material that is impermeable to oxygen for the insulating layers 257 and 259, the excess oxygen contained in the insulating layer 258 is less likely to be released into the lower or upper layer. Therefore, sufficient oxygen can be supplied to the oxide semiconductor. For example, a structure in which an insulating layer containing silicon and oxygen (insulating layer 258) is provided between two insulating layers containing silicon and nitrogen (insulating layer 257 and insulating layer 259) is preferable. Silicon nitride, silicon nitride oxide, or the like can be used as the insulating layer containing silicon and oxygen. Silicon oxide, silicon oxynitride, or the like can be used as the insulating layer containing silicon and oxygen.

[0130] When an oxide semiconductor is used for the semiconductor layer 263, by using a material containing hydrogen for the insulating layers 257 and 259, hydrogen is supplied to a region of the semiconductor layer 263 in contact with the insulating layer 257 and a region of the semiconductor layer 263 in contact with the insulating layer 259, and each region of the semiconductor layer 263 becomes n-type. Therefore, the region of the semiconductor layer 263 in contact with the conductive layer 261 and the region of the semiconductor layer 263 in contact with the insulating layer 259 function as one of the source region and the drain region. The region of the semiconductor layer 263 in contact with the conductive layer 255 and the region of the semiconductor layer 263 in contact with the insulating layer 257 function as the other of the source region and the drain region.

[0131] The conductive layer 261 functions as one of the source electrode and the drain electrode of the transistor 200C. The conductive layer 255 functions as the other of the source electrode and the drain electrode of the transistor 200C. The transistor 200C is a transistor in which the source electrode and the drain electrode are arranged in the Z direction. That is, the source and the drain of the transistor 200C are arranged at different heights. In other words, the source and the drain of the transistor 200C are arranged at different positions in the Z direction. Such a transistor is also called a "vertical channel transistor," "vertical channel transistor," "vertical transistor," or "VFET (Vertical Field Effect Transistor)."

[0132] In the above configuration, in the transistor 200C, which is a VFET, the length of the side surface of the insulating layer 158 as viewed from the X direction or the Y direction is the channel length L (channel length L1) (see FIG. 8B). Therefore, the channel length L of the transistor 200C is determined depending on the thickness t1 of the insulating layer 258.

[0133] Furthermore, it is preferable to use a material that does not contain hydrogen or that contains very little hydrogen for the insulating layers 257 and 259. For example, silicon nitride or silicon nitride oxide containing very little hydrogen can be used. In this case, the region of the semiconductor layer 263 in contact with the insulating layer 257 and the region of the semiconductor layer 263 in contact with the insulating layer 259 are not made n-type. Therefore, the region of the semiconductor layer 263 in contact with the conductive layer 261 functions as one of the source region and the drain region. The region of the semiconductor layer 263 in contact with the conductive layer 255 functions as the other of the source region and the drain region. The region of the semiconductor layer 263 in contact with the insulating layer 257, the region of the semiconductor layer 263 in contact with the insulating layer 258, and the region of the semiconductor layer 263 in contact with the insulating layer 259 function as channel formation regions.

[0134] In this case, the sum of the lengths of the side surfaces of the insulating layers 257, 258, and 259 as viewed from the X direction or the Y direction is the channel length L (channel length L2). Therefore, the channel length L of the transistor 200C is determined according to the total thickness t2 of the insulating layers 257, 258, and 259. In this manner, the transistor 200C has a channel formation region that extends along the side surface of the insulating layer 256.

[0135] Furthermore, because the semiconductor layer 263 is provided in the opening 262, the perimeter of the opening 262 as viewed from the Z direction is the channel width W of the transistor 200C (see FIG. 8A ). The perimeter may be determined, for example, at a position halfway through the thickness t1 or halfway through the thickness t2 of the insulating layer 258. Note that the perimeter of any position on the opening 262 may be used as the channel width W as needed. For example, the perimeter of the bottom of the opening 262 may be used as the channel width W, or the perimeter of the top of the opening 262 may be used as the channel width W. Although FIG. 8A shows the outline (planar shape) of the opening 262 as viewed from the Z direction as a circle, this is not limiting. For example, the outline of the opening 262 as viewed from the Z direction may be an ellipse, a rectangle, or the like.

[0136] In the memory device of one embodiment of the present invention, the channel length L is preferably smaller than at least the channel width W. In one embodiment of the present invention, the channel length L is 0.1 to 0.99 times, preferably 0.5 to 0.8 times, the channel width W.

[0137] Furthermore, in order to improve the coverage of the semiconductor layer 263, the insulating layer 264, and the conductive layer 265 formed inside the opening 262, the taper angle θ of the side surface of the opening 262, i.e., the taper angle θ of each of the side surfaces of the insulating layer 257, the insulating layer 258, and the insulating layer 259, is set to 45° or more and less than 90°, preferably 50° or more and 75° or less. The taper angles θ of the side surfaces of the insulating layer 257, the insulating layer 258, and the insulating layer 259 may be the same or different from each other. Note that the taper angle θ of the side surface of a layer (insulating layer, conductive layer, or semiconductor layer) refers to the angle formed between the bottom surface and the side surface of the layer (see FIG. 8B ).

[0138] A vertical transistor can occupy a smaller area than a transistor in which a channel formation region, a source region, and a drain region are separately provided on the XY plane (also called a "horizontal transistor"). Therefore, by using a vertical channel transistor in a semiconductor device, the area occupied by the semiconductor device can be reduced. Furthermore, by using a vertical channel transistor in a semiconductor device, high integration of the semiconductor device can be achieved.

[0139] Furthermore, in a lateral transistor, the channel length is limited by the exposure limit of photolithography. In a vertical channel transistor according to one embodiment of the present invention, the channel length can be set by the thickness of the insulating layer 256 or 258. Therefore, the channel length of the transistor can be made into an extremely fine structure that is equal to or less than the exposure limit of photolithography (for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 1 nm or more or 5 nm or more). This increases the on-state current of the transistor 200C, thereby improving frequency characteristics. By using a vertical channel transistor, a semiconductor device with high operating speed can be provided.

[0140] 9A is a plan view of a transistor 200D that can be used for a semiconductor device of one embodiment of the present invention. The transistor 200D is a variation of the transistor 200C. To avoid repetition of description, differences between the transistor 200D and the transistor 200C will be mainly described.

[0141] FIG. 9B is a cross-sectional view taken along the dashed line A1-A2 in FIG. 9A.

[0142] The transistor 200D includes an insulating layer 258a and an insulating layer 258b between the insulating layer 257 and the insulating layer 259, and a conductive layer 267 between the insulating layer 258a and the insulating layer 258b. The insulating layer 258a and the insulating layer 258b can be formed using a material and a method similar to those of the insulating layer 258. The opening 262 of the transistor 200D is provided to penetrate the conductive layer 261, the insulating layer 259, the insulating layer 258b, the conductive layer 267, the insulating layer 258a, and the insulating layer 257 in a region overlapping with part of the conductive layer 255.

[0143] In the transistor 200D, an insulating layer 268 is provided along the side surface of the opening 262. Inside the opening 262, the insulating layer 268 has a region overlapping with a side surface of the conductive layer 261, a region overlapping with a side surface of the insulating layer 259, a region overlapping with a side surface of the insulating layer 258b, a region overlapping with a side surface of the conductive layer 267, a region overlapping with a side surface of the insulating layer 258a, and a region overlapping with a side surface of the insulating layer 257.

[0144] Furthermore, inside the opening 262, the semiconductor layer 263 in the transistor 200D has a region that overlaps with a side surface of the conductive layer 261 via the insulating layer 268, a region that overlaps with a side surface of the insulating layer 259 via the insulating layer 268, a region that overlaps with a side surface of the insulating layer 258b via the insulating layer 268, a region that overlaps with a side surface of the conductive layer 267 via the insulating layer 268, a region that overlaps with a side surface of the insulating layer 258a via the insulating layer 268, and a region that overlaps with a side surface of the insulating layer 257 via the insulating layer 268.

[0145] When the conductive layer 265 is used as a gate electrode, the conductive layer 267 functions as a back gate electrode. When the conductive layer 267 is used as a gate electrode, the conductive layer 265 functions as a back gate electrode. One of the insulating layer 264 and the insulating layer 268 functions as a gate insulating layer, and the other functions as a back gate insulating layer. The insulating layer 268 can be formed using a material and a method similar to those of the insulating layer 264.

[0146] <Transistor Structure Example 5> Fig. 10A is a plan view of a transistor 200E that can be used for a semiconductor device of one embodiment of the present invention. Fig. 10B is a cross-sectional view taken along the line A1-A2 indicated by a dashed dotted line in Fig. 10A. Fig. 10C is a cross-sectional view taken along the line A3-A4 indicated by a dashed dotted line in Fig. 10A. Note that Fig. 10A is a cross-sectional view of the transistor 200E in the channel length direction, and Fig. 10C is a cross-sectional view of the transistor 200E in the channel width direction.

[0147] 10A to 10C , the transistor 200E includes a semiconductor layer 520a disposed on the substrate 201, a semiconductor layer 520b disposed on the semiconductor layer 520a, conductive layers 542a and 542b disposed spaced apart from each other on the semiconductor layer 520b, an insulating layer 580 disposed on the conductive layers 542a and 542b and having an opening formed between the conductive layers 542a and 542b, a conductive layer 560 disposed in the opening, an insulating layer 550 disposed among the semiconductor layer 520b, the conductive layers 542a, 542b, and the insulating layer 580, and the conductive layer 560, and a semiconductor layer 520c disposed among the semiconductor layer 520b, the conductive layers 542a, 542b, the insulating layer 580, and the insulating layer 550. 10B and 10C , the top surface of the conductive layer 560 is substantially aligned with the top ends (the highest positions as viewed from the substrate surface) of the insulating layer 550, the semiconductor layer 520c, and the insulating layer 580. Note that hereinafter, the semiconductor layers 520a, 520b, and 520c may be collectively referred to as semiconductor layers 520. The conductive layers 542a and 542b may be collectively referred to as conductive layers 542.

[0148] 10A to 10C , an insulating layer 554 is disposed between the insulating layer 524, the semiconductor layer 520a, the semiconductor layer 520b, the conductive layer 542a, the conductive layer 542b, and the semiconductor layer 520c and the insulating layer 580. The insulating layer 554 is in contact with the side surfaces of the semiconductor layer 520c, the top and side surfaces of the conductive layer 542a, the top and side surfaces of the conductive layer 542b, the side surfaces of the semiconductor layer 520a and the semiconductor layer 520b, and the top surface of the insulating layer 524.

[0149] Although the transistor 200E has a three-layer structure including the semiconductor layer 520a, the semiconductor layer 520b, and the semiconductor layer 520c in the channel formation region and its vicinity, the present invention is not limited to this. For example, a two-layer structure including the semiconductor layer 520b and the semiconductor layer 520c or a stacked structure of four or more layers may be used. Furthermore, each of the semiconductor layer 520a, the semiconductor layer 520b, and the semiconductor layer 520c may have a stacked structure of two or more layers.

[0150] For example, when an oxide semiconductor, which is a type of metal oxide, is used as the semiconductor layer 520, and the semiconductor layer 520c has a stacked structure consisting of a first metal oxide and a second metal oxide on the first metal oxide, it is preferable that the first metal oxide has a composition similar to that of the semiconductor layer 520b, and the second metal oxide has a composition similar to that of the semiconductor layer 520a.

[0151] Here, the conductive layer 560 functions as the gate electrode of the transistor, and the conductive layers 542a and 542b function as source and drain electrodes, respectively. As described above, the conductive layer 560 is formed so as to fill the opening of the insulating layer 580 and the region sandwiched between the conductive layers 542a and 542b. Here, the conductive layers 560, 542a, and 542b are arranged in a self-aligned manner with respect to the opening of the insulating layer 580. That is, in the transistor 200E, the gate electrode can be arranged between the source and drain electrodes in a self-aligned manner. Therefore, the conductive layer 560 can be formed without providing a margin for alignment, thereby reducing the area occupied by the transistor 200E. This reduces the area occupied by the semiconductor device. Furthermore, the integration degree of the semiconductor device can be increased.

[0152] 10A to 10C , the conductive layer 560 includes a conductive layer 560a provided inside the insulating layer 550 and a conductive layer 560b provided so as to be embedded inside the conductive layer 560a. Although the conductive layer 560 in the transistor 200E has a two-layer stacked structure, the present invention is not limited to this. For example, the conductive layer 560 may have a single-layer structure or a stacked structure of three or more layers.

[0153] The transistor 200E includes an insulating layer 202 disposed on the substrate 201, an insulating layer 514 disposed on the insulating layer 202, an insulating layer 516 disposed on the insulating layer 514, a conductive layer 505 disposed so as to be embedded in the insulating layer 516, an insulating layer 522 disposed on the insulating layer 516 and the conductive layer 505, and an insulating layer 524 disposed on the insulating layer 522. In addition, a semiconductor layer 520a is disposed on the insulating layer 524.

[0154] Further, insulating layers 574 and 581 functioning as interlayer films are provided over the transistor 200E. The insulating layer 574 is provided in contact with top surfaces of the conductive layer 560, the insulating layer 550, the semiconductor layer 520c, and the insulating layer 580.

[0155] When an oxide semiconductor is used for the semiconductor layer 520, an insulating layer having a function of suppressing diffusion of hydrogen (for example, at least one of hydrogen atoms, hydrogen molecules, and the like) may be used for the insulating layer 522, the insulating layer 554, and the insulating layer 574. For example, an insulating layer having lower hydrogen permeability than the insulating layer 524, the insulating layer 550, and the insulating layer 580 may be used for the insulating layer 522, the insulating layer 554, and the insulating layer 574. For example, aluminum oxide, hafnium oxide, silicon nitride, silicon nitride oxide, or the like may be used.

[0156] Furthermore, an insulating layer having a function of suppressing diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, and the like) may be used as the insulating layer 522 and the insulating layer 554. For example, an insulating layer having lower oxygen permeability than the insulating layer 524, the insulating layer 550, and the insulating layer 580 may be used as the insulating layer 522 and the insulating layer 554. For example, aluminum oxide, hafnium oxide, silicon nitride, silicon nitride oxide, or the like may be used.

[0157] Here, the insulating layer 524, the semiconductor layer 520, and the insulating layer 550 are sandwiched between the insulating layer 522 and the insulating layer 574. Therefore, impurities such as hydrogen and excess oxygen contained in layers above the insulating layer 574 and below the insulating layer 522 can be prevented from being mixed into the insulating layer 524, the semiconductor layer 520, and the insulating layer 550.

[0158] 10B illustrates an example in which a conductive layer 545 (conductive layer 545a and conductive layer 545b) that is connected to the transistor 200E and functions as a plug is provided. Note that an example is illustrated in which an insulating layer 541 (insulating layer 541a and insulating layer 541b) is provided in contact with the side surface of the conductive layer 545 that functions as a plug. That is, the insulating layer 541 is provided in contact with the inner walls of the openings of the insulating layer 554, the insulating layer 580, the insulating layer 574, and the insulating layer 581. In addition, in FIG. 10B, a first conductive layer of the conductive layer 545 is provided in contact with the side surface of the insulating layer 541, and a second conductive layer of the conductive layer 545 is provided further inside.

[0159] Here, the height of the top surface of the conductive layer 545 and the height of the top surface of the insulating layer 581 can be approximately the same. Note that although the transistor 200E shows a structure in which the first conductive layer of the conductive layer 545 and the second conductive layer of the conductive layer 545 are stacked, the present invention is not limited to this. For example, the conductive layer 545 can be provided as a single layer or a stacked structure of three or more layers. When the structure has a stacked structure, the structures may be distinguished by assigning ordinal numbers to the order of formation.

[0160] Furthermore, the thickness of the semiconductor layer 520b in a region that does not overlap with the conductive layer 542 may be thinner than the thickness of the region that overlaps with the conductive layer 542. This is achieved by removing part of the top surface of the semiconductor layer 520b when forming the conductive layers 542a and 542b. When a conductive film that will become the conductive layer 542 is formed on the top surface of the semiconductor layer 520b, a low-resistance region may be formed near the interface with the conductive film. In this way, by removing the low-resistance region of the semiconductor layer 520b that is located between the conductive layer 542a and the conductive layer 542b in a plan view, it is possible to prevent a channel from being formed in that region.

[0161] Next, the detailed structure of the transistor 200E that can be used in the semiconductor device of one embodiment of the present invention will be described.

[0162] The conductive layer 505 is arranged to have a region overlapping with the conductive layer 560 with the semiconductor layer 520 interposed therebetween. By providing the conductive layer 505 so as to be embedded in the insulating layer 516, unevenness on the top surfaces of the conductive layer 505 and the insulating layer 516 can be reduced, and coverage with layers formed in later steps can be improved.

[0163] The conductive layer 505 includes a conductive layer 505a, a conductive layer 505b, and a conductive layer 505c. The conductive layer 505a is provided in contact with the bottom surface and sidewall of an opening provided in the insulating layer 516. The conductive layer 505b is provided so as to fill a recess formed in the conductive layer 505a. The top surface of the conductive layer 505b is lower than the top end of the conductive layer 505a and the top surface of the insulating layer 516. The conductive layer 505c is provided in contact with the top surface of the conductive layer 505b and the side surface of the conductive layer 505a. The height of the top surface of the conductive layer 505c is equal to or approximately equal to the height of the top end of the conductive layer 505a and the height of the top surface of the insulating layer 516. In other words, the conductive layer 505b is surrounded by the conductive layers 505a and 505c.

[0164] In the case where an oxide semiconductor is used for the semiconductor layer 520, the conductive layer 505a and the conductive layer 505c can be formed of a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, or a nitrogen oxide molecule (N ２ O, NO, NO ２ A conductive material having a function of suppressing the diffusion of impurities such as copper atoms, etc., or a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) is used.

[0165] By using a conductive material that has a function of reducing hydrogen diffusion for the conductive layers 505a and 505c, it is possible to prevent impurities such as hydrogen contained in the conductive layer 505b from diffusing into the semiconductor layer 520 through the insulating layer 524 or the like. Furthermore, by using a conductive material that has a function of suppressing oxygen diffusion for the conductive layers 505a and 505c, it is possible to prevent the conductive layer 505b from being oxidized and its conductivity from decreasing. Examples of conductive materials that have a function of suppressing oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Therefore, the conductive layer 505a can be formed as a single layer or a stack of any of the above conductive materials. For example, titanium nitride can be used for the conductive layer 505a.

[0166] The conductive layer 505b may be formed using a conductive material containing tungsten, copper, or aluminum as a main component. For example, the conductive layer 505b may be formed using tungsten. When the conductive layer 560 is used as a gate electrode, the conductive layer 505 functions as a back gate electrode.

[0167] The conductive layer 505 is preferably provided to be larger than the channel formation region in the semiconductor layer 520. In particular, as shown in Fig. 10C, the conductive layer 505 preferably extends to a region outside the end portion intersecting with the channel width direction of the semiconductor layer 520. In other words, the conductive layer 505 and the conductive layer 560 preferably overlap with each other with an insulating layer interposed therebetween on the outside of the side surface of the semiconductor layer 520 in the channel width direction.

[0168] With the above structure, the channel formation region of the semiconductor layer 520 can be surrounded by the electric field of the conductive layer 560 functioning as a gate electrode and the electric field of the conductive layer 505 functioning as a back gate electrode.

[0169] The conductive layer 505 can be used as a wiring by extending it beyond the end of the semiconductor layer 520. However, the present invention is not limited to this, and a structure in which a conductive layer functioning as a wiring is provided under the conductive layer 505 is also possible.

[0170] The insulating layer 514 is preferably formed using an insulating material that functions as a barrier insulating layer that prevents impurities such as water or hydrogen from entering the transistor 200E from the substrate side. Therefore, the insulating layer 514 is preferably formed using an insulating material that functions as a barrier insulating layer that prevents impurities such as water or hydrogen from entering the transistor 200E from the substrate side. ２ O, NO, NO ２ The insulating layer 514 may be formed as the barrier insulating layer 50. Alternatively, an insulating material having a function of suppressing diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, and the like) (through which the oxygen is less likely to permeate) may be used.

[0171] For example, aluminum oxide, hafnium oxide, silicon nitride, or the like is used for the insulating layer 514. This can prevent impurities such as water or hydrogen from diffusing from the substrate side of the insulating layer 514 to the transistor 200E side. Alternatively, it can prevent oxygen contained in the insulating layer 524 or the like from diffusing toward the substrate side of the insulating layer 514.

[0172] The insulating layer 516, the insulating layer 580, and the insulating layer 581, which function as interlayer films, may be formed using an insulating material having a lower dielectric constant than the insulating layer 514. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance generated between wirings can be reduced. For example, the insulating layer 516, the insulating layer 580, and the insulating layer 581 may be formed using silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having vacancies, or the like, as appropriate.

[0173] When the conductive layer 505 is used as a gate electrode, the insulating layers 522 and 524 function as gate insulating layers.

[0174] Here, the insulating layer 524 in contact with the semiconductor layer 520 preferably contains excess oxygen. For example, silicon oxide, silicon oxynitride, or the like may be used as appropriate for the insulating layer 524. By providing an insulating layer containing oxygen in contact with the semiconductor layer 520, oxygen vacancies in the semiconductor layer 520 are reduced, and the reliability of the transistor 200E is improved.

[0175] 10C , the insulating layer 524 may have a thinner film thickness in a region that does not overlap with the insulating layer 554 and the semiconductor layer 520b than in other regions. The insulating layer 524 preferably has a film thickness in the region that does not overlap with the insulating layer 554 and the semiconductor layer 520b that allows sufficient diffusion of the oxygen.

[0176] The insulating layer 522 is formed using a material that functions as a barrier insulating layer that prevents impurities such as water or hydrogen from entering the transistor 200E from the substrate side, similar to the insulating layer 514. For example, the insulating layer 522 is formed using a material that has lower hydrogen permeability than the insulating layer 524. The insulating layer 522, the insulating layer 554, and the insulating layer 574 surround the insulating layer 524, the semiconductor layer 520, the insulating layer 550, and the like, thereby preventing impurities such as water or hydrogen from entering the transistor 200E from the outside. The insulating layer 522 may also be formed as the barrier insulating layer 50.

[0177] Furthermore, the insulating layer 522 is preferably made of a material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, and the like) (i.e., the oxygen is less likely to permeate). For example, the insulating layer 522 is made of a material that has lower oxygen permeability than the insulating layer 524. The insulating layer 522 has a function of suppressing the diffusion of oxygen and impurities, so that oxygen diffusing from the semiconductor layer 520 toward the substrate can be reduced. Furthermore, the conductive layer 505 can be prevented from reacting with oxygen contained in the insulating layer 524 or the semiconductor layer 520.

[0178] The insulating layer 522 may be an insulating layer containing an oxide of one or both of aluminum and hafnium, which are insulating materials. For example, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) may be used as the insulating layer containing an oxide of one or both of aluminum and hafnium. Alternatively, silicon nitride or silicon nitride oxide may be used as the insulating layer 522. When the insulating layer 522 is formed using such a material, the insulating layer 522 functions as a layer that suppresses oxygen release from the semiconductor layer 520 and the intrusion of impurities such as hydrogen into the semiconductor layer 520 from the periphery of the transistor 200E.

[0179] Alternatively, for example, a material to which aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide is added can be used for the insulating layer 522. Alternatively, the insulating layer 522 can be subjected to nitriding treatment. Alternatively, the insulating layer 522 can be formed by stacking silicon oxide, silicon oxynitride, or silicon nitride. For example, the insulating layer 522 can have a three-layer structure in which silicon nitride, silicon oxide, and aluminum oxide are stacked in this order.

[0180] The insulating layer 522 may be made of, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), or strontium titanate (SrTiO ３ ) or (Ba,Sr)TiO ３ It is possible to use an insulating layer containing a so-called high-k material such as BST in a single layer or a laminated layer. As transistors become smaller and more highly integrated, problems such as leakage current may occur due to the thinning of the gate insulating layer. By using a high-k material for the insulating layer that functions as the gate insulating layer, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0181] Note that each of the insulating layer 522 and the insulating layer 524 can have a stacked structure of two or more layers. In this case, the insulating layer 522 and the insulating layer 524 are not limited to a stacked structure made of the same material, and can have a stacked structure made of different materials.

[0182] The semiconductor layer 520 includes a semiconductor layer 520a, a semiconductor layer 520b on the semiconductor layer 520a, and a semiconductor layer 520c on the semiconductor layer 520b. By providing the semiconductor layer 520a below the semiconductor layer 520b, it is possible to suppress the diffusion of impurities from structures formed below the semiconductor layer 520a to the semiconductor layer 520b. Furthermore, by providing the semiconductor layer 520c on the semiconductor layer 520b, it is possible to suppress the diffusion of impurities from structures formed above the semiconductor layer 520c to the semiconductor layer 520b.

[0183] When an oxide semiconductor is used for the semiconductor layer 520, the semiconductor layer 520 preferably has a stacked structure of multiple oxide layers with different atomic ratios of metal atoms. For example, when the semiconductor layer 520 includes at least indium (In) and the element M, the ratio of the number of atoms of the element M contained in the semiconductor layer 520a to the number of atoms of all elements constituting the semiconductor layer 520a is made higher than the ratio of the number of atoms of the element M contained in the semiconductor layer 520b to the number of atoms of all elements constituting the semiconductor layer 520b. Furthermore, the atomic ratio of the element M contained in the semiconductor layer 520a to In is made higher than the atomic ratio of the element M contained in the semiconductor layer 520b to In. Here, the semiconductor layer 520c can use the metal oxide used for the semiconductor layer 520a or the semiconductor layer 520b.

[0184] The energy of the conduction band minimum of the semiconductor layer 520a and the semiconductor layer 520c is preferably higher than the energy of the conduction band minimum of the semiconductor layer 520b. In other words, the electron affinity of the semiconductor layer 520a and the semiconductor layer 520c is preferably lower than the electron affinity of the semiconductor layer 520b. In this case, the semiconductor layer 520c may be made of a metal oxide that can be used for the semiconductor layer 520a. Specifically, the ratio of the number of atoms of the element M contained in the semiconductor layer 520c to the number of atoms of all elements constituting the semiconductor layer 520c is preferably higher than the ratio of the number of atoms of the element M contained in the semiconductor layer 520b to the number of atoms of all elements constituting the semiconductor layer 520b. Furthermore, the atomic ratio of the element M contained in the semiconductor layer 520c to In is preferably higher than the atomic ratio of the element M contained in the semiconductor layer 520b to In.

[0185] Here, the energy level of the conduction band minimum changes gradually at the junction between the semiconductor layer 520a, the semiconductor layer 520b, and the semiconductor layer 520c. In other words, the energy level of the conduction band minimum at the junction between the semiconductor layer 520a, the semiconductor layer 520b, and the semiconductor layer 520c changes continuously or can be said to be a continuous junction. To achieve this, it is preferable that the defect level density of the mixed layer formed at the interface between the semiconductor layer 520a and the semiconductor layer 520b and the interface between the semiconductor layer 520b and the semiconductor layer 520c is low.

[0186] Specifically, the semiconductor layers 520a and 520b, and the semiconductor layers 520b and 520c, may have a common element other than oxygen (as a main component), thereby forming a mixed layer with a low defect level density. For example, when the semiconductor layer 520b is an In—Ga—Zn oxide, the semiconductor layers 520a and 520c may be made of In—Ga—Zn oxide, Ga—Zn oxide, gallium oxide, or the like. The semiconductor layer 520c may also have a stacked structure. For example, a stacked structure of In—Ga—Zn oxide and Ga—Zn oxide on the In—Ga—Zn oxide, or a stacked structure of In—Ga—Zn oxide and gallium oxide on the In—Ga—Zn oxide, may be used. In other words, a stacked structure of In—Ga—Zn oxide and an oxide not containing In may be used as the semiconductor layer 520c.

[0187] Specifically, the semiconductor layer 520a may be made of a metal oxide having an atomic ratio of In:Ga:Zn=1:3:4 or thereabouts, or an atomic ratio of 1:1:0.5 or thereabouts. The semiconductor layer 520b may be made of a metal oxide having an atomic ratio of In:Ga:Zn=4:2:3 or thereabouts, or an atomic ratio of 3:1:2 or thereabouts, or an atomic ratio of 1:1:1 or thereabouts. The semiconductor layer 520c may be made of a metal oxide having an atomic ratio of In:Ga:Zn=1:3:4 or thereabouts, or an atomic ratio of In:Ga:Zn=4:2:3 or thereabouts, or an atomic ratio of Ga:Zn=2:1 or thereabouts, or an atomic ratio of Ga:Zn=2:5 or thereabouts. Specific examples of the semiconductor layer 520c having a stacked structure include a stacked structure of In:Ga:Zn=4:2:3 [atomic ratio] or the vicinity thereof and Ga:Zn=2:1 [atomic ratio] or the vicinity thereof, a stacked structure of In:Ga:Zn=4:2:3 [atomic ratio] or the vicinity thereof and Ga:Zn=2:5 [atomic ratio] or the vicinity thereof, and a stacked structure of In:Ga:Zn=4:2:3 [atomic ratio] or the vicinity thereof and gallium oxide.

[0188] In this case, the main carrier path is the semiconductor layer 520b. By configuring the semiconductor layers 520a and 520c as described above, the defect state density at the interface between the semiconductor layers 520a and 520b and the interface between the semiconductor layers 520b and 520c can be reduced. This reduces the effect of interface scattering on carrier conduction, allowing the transistor 200E to achieve high on-state current and high frequency characteristics. Note that when the semiconductor layer 520c has a stacked structure, in addition to the effect of reducing the defect state density at the interface between the semiconductor layers 520b and 520c, the diffusion of constituent elements of the semiconductor layer 520c toward the insulating layer 550 can be suppressed. More specifically, the semiconductor layer 520c has a stacked structure, and an oxide not containing In is positioned above the stacked structure, thereby suppressing In diffusion toward the insulating layer 550. The insulating layer 550 functions as a gate insulating layer, and diffusion of In can result in poor transistor characteristics. Therefore, by forming the semiconductor layer 520c into a stacked structure, a highly reliable semiconductor device can be provided.

[0189] A conductive layer 542 (a conductive layer 542a and a conductive layer 542b) functioning as a source electrode and a drain electrode is provided over the semiconductor layer 520b. When an oxide semiconductor is used for the semiconductor layer 520b, the conductive layer 542 is preferably made of a conductive material that is not easily oxidized or that maintains its conductivity even when it absorbs oxygen.

[0190] A region of the semiconductor layer 520 in contact with the conductive layer 542 functions as a source region or a drain region of the transistor 200E. Here, the region between the conductive layer 542a and the conductive layer 542b is formed to overlap with the opening of the insulating layer 580. This allows the conductive layer 560 to be disposed in a self-aligned manner between the conductive layer 542a and the conductive layer 542b.

[0191] The insulating layer 550 functions as a gate insulating layer. The insulating layer 550 is disposed in contact with the top surface of the semiconductor layer 520c. The insulating layer 550 can be formed using silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, or silicon oxide having vacancies. For example, silicon oxide or silicon oxynitride is used as the insulating layer 550.

[0192] The insulating layer 550 is formed using an insulating material in which the concentration of impurities such as water or hydrogen is reduced, similarly to the insulating layer 524. The thickness of the insulating layer 550 is 1 nm to 20 nm.

[0193] A metal oxide may be provided between the insulating layer 550 and the conductive layer 560. The metal oxide suppresses oxygen diffusion from the insulating layer 550 to the conductive layer 560. This can suppress oxidation of the conductive layer 560 due to oxygen contained in the insulating layer 550.

[0194] Although the conductive layer 560 is shown as a two-layer structure in FIGS. 10A to 10C, a single-layer structure or a stacked structure of three or more layers can also be used.

[0195] The conductive layer 560a is formed of the above-mentioned hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ It is preferable to use a conductive material that has a function of suppressing the diffusion of impurities such as copper atoms, etc. Alternatively, it is preferable to use a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0196] The conductive layer 560a has a function of suppressing oxygen diffusion, which can suppress a decrease in conductivity due to oxidation of the conductive layer 560b caused by oxygen contained in the insulating layer 550. Examples of conductive materials that can suppress oxygen diffusion include tantalum, tantalum nitride, ruthenium, and ruthenium oxide.

[0197] The conductive layer 560b may be formed using a conductive material containing tungsten, copper, or aluminum as a main component. Furthermore, since the conductive layer 560 also functions as a wiring, a conductive layer with high conductivity may be used. For example, a conductive material containing tungsten, copper, or aluminum as a main component may be used. Furthermore, the conductive layer 560b may have a layered structure, for example, a layered structure of titanium or titanium nitride and the above-mentioned conductive material.

[0198] 10B and 10C , in a region of the semiconductor layer 520b that does not overlap with the conductive layer 542, in other words, in the channel formation region of the semiconductor layer 520, the side surface of the semiconductor layer 520 is arranged to be covered with the conductive layer 560. This makes it easier for the electric field of the conductive layer 560, which functions as the gate electrode of the transistor 200E, to act on the side surface of the semiconductor layer 520. This increases the on-state current of the transistor 200E, and improves its frequency characteristics.

[0199] The insulating layer 554, like the insulating layer 514, is made of an insulating material that prevents impurities such as water or hydrogen from entering the transistor 200E from the insulating layer 580 side. For example, the insulating layer 554 is made of an insulating material that has lower hydrogen permeability than the insulating layer 524. Furthermore, as shown in FIGS. 10B and 10C , the insulating layer 554 is provided in contact with the side surfaces of the semiconductor layer 520c, the top and side surfaces of the conductive layer 542a, the top and side surfaces of the conductive layer 542b, the side surfaces of the semiconductor layer 520a and the semiconductor layer 520b, and the top surface of the insulating layer 524. This structure can prevent hydrogen contained in the insulating layer 580 from entering the semiconductor layer 520 from the top surfaces or side surfaces of the conductive layer 542a, the conductive layer 542b, the semiconductor layer 520a, the semiconductor layer 520b, and the insulating layer 524.

[0200] Furthermore, an insulating material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, and the like) (i.e., oxygen is less likely to permeate) is used for the insulating layer 554. For example, an insulating material that has lower oxygen permeability than the insulating layer 580 or the insulating layer 524 is used for the insulating layer 554.

[0201] When an oxide semiconductor is used for the semiconductor layer 520, the insulating layer 554 can be formed by a sputtering method. By forming the insulating layer 554 by a sputtering method in an oxygen-containing atmosphere, oxygen can be added to the insulating layer 524 near a region in contact with the insulating layer 554. This allows oxygen to be supplied from this region into the semiconductor layer 520 through the insulating layer 524. The insulating layer 554 has a function of suppressing upward diffusion of oxygen, thereby preventing oxygen from diffusing from the semiconductor layer 520 to the insulating layer 580. The insulating layer 522 has a function of suppressing downward diffusion of oxygen, thereby preventing oxygen from diffusing from the semiconductor layer 520 toward the substrate. In this manner, oxygen is supplied to the channel formation region of the semiconductor layer 520. This reduces oxygen vacancies in the semiconductor layer 520, thereby preventing the transistor from becoming normally on.

[0202] For example, an insulating layer containing an oxide of one or both of aluminum and hafnium is formed as the insulating layer 554. Note that as the insulating layer containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like can be used.

[0203] The insulating layer 580 is provided over the insulating layer 524, the semiconductor layer 520, and the conductive layer 542 with the insulating layer 554 interposed therebetween. For example, the insulating layer 580 can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, or silicon oxide having vacancies. Silicon oxide and silicon oxynitride are particularly suitable because they are thermally stable. Materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are particularly suitable because they can easily form a region containing oxygen that is released by heating.

[0204] For the insulating layer 574, similar to the insulating layer 514, an insulating material that functions as a barrier insulating layer that suppresses impurities such as water or hydrogen from entering the insulating layer 580 from above is used. For the insulating layer 574, for example, an insulating material that can be used for the insulating layer 514, the insulating layer 554, and the like is used. The insulating layer 574 may also be used as the barrier insulating layer 50.

[0205] 10A to 10C show an example in which an insulating layer 581 functioning as an interlayer film is provided over the insulating layer 574. As the insulating layer 581, an insulating material in which the concentration of impurities such as water or hydrogen is reduced is used, similar to the insulating layer 524 and the like.

[0206] The conductive layers 545a and 545b are disposed in openings formed in the insulating layer 581, the insulating layer 574, the insulating layer 580, and the insulating layer 554. The conductive layers 545a and 545b are provided opposite each other with the conductive layer 560 interposed therebetween. Note that the positions of the top surfaces of the conductive layers 545a and 545b preferably coincide or substantially coincide with the top surface of the insulating layer 581.

[0207] Note that an insulating layer 541a is provided in contact with the inner walls of the openings of the insulating layer 581, the insulating layer 574, the insulating layer 580, and the insulating layer 554, and a first conductive layer of the conductive layer 545a is formed in contact with the side surface of the insulating layer 541a. A conductive layer 542a is located in at least a part of the bottom of the opening, and the conductive layer 545a is in contact with the conductive layer 542a. Similarly, an insulating layer 541b is provided in contact with the inner walls of the openings of the insulating layer 581, the insulating layer 574, the insulating layer 580, and the insulating layer 554, and a first conductive layer of the conductive layer 545b is formed in contact with the side surface of the insulating layer 541b. A conductive layer 542b is located in at least a part of the bottom of the opening, and the conductive layer 545b is in contact with the conductive layer 542b.

[0208] The conductive layers 545a and 545b may be formed using a conductive material containing tungsten, copper, or aluminum as a main component. Each of the conductive layers 545a and 545b can have a stacked structure of two or more layers.

[0209] When the conductive layer 545 has a stacked-layer structure, a conductive material that has a function of suppressing diffusion of impurities such as water or hydrogen may be used for conductive layers in contact with the semiconductor layer 520a, the semiconductor layer 520b, the conductive layer 542, the insulating layer 554, the insulating layer 580, the insulating layer 574, and the insulating layer 581. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like is used. The use of such a conductive material can suppress absorption of oxygen contained in the insulating layer 580 by the conductive layer 545a and the conductive layer 545b. Furthermore, impurities such as water or hydrogen from above the insulating layer 581 can be suppressed from entering the semiconductor layer 520 through the conductive layer 545a and the conductive layer 545b.

[0210] The insulating layers 541a and 541b may be, for example, insulating layers that can be used for the insulating layer 554. The insulating layers 541a and 541b are provided in contact with the insulating layer 554, and therefore can prevent impurities such as water or hydrogen from the insulating layer 580 or the like from entering the semiconductor layer 520 through the conductive layers 545a and 545b. Furthermore, oxygen contained in the insulating layer 580 can be prevented from being absorbed by the conductive layers 545a and 545b.

[0211] <Transistor Configuration Example 6> A modification of the transistor 200E shown in FIG. 10 is shown in FIG. 11A. FIG. 11A is a plan view of a transistor F which is a modification of the transistor 200E. FIG. 11B is a cross-sectional view taken along the line A1-A2 indicated by the dashed dotted line in FIG. 11A. FIG. 11C is a cross-sectional view taken along the line A3-A4 indicated by the dashed dotted line in FIG. 11A. Since the transistor F is a modification of the transistor 200E, differences between the transistor F and the transistor 200E will be mainly described.

[0212] The transistor F has a structure in which the semiconductor layer 520c and the conductive layer 505c are removed from the structure of the transistor 200E. Reducing the number of components of the transistor reduces production costs. Furthermore, reducing the number of components of the transistor shortens the manufacturing process, improving manufacturing yield.

[0213] Furthermore, the transistor F has a region where the insulating layer 554 and the insulating layer 522 are in contact with each other outside the semiconductor layer 520, and the side surface of the insulating layer 524 is covered with the insulating layer 554. When an oxide semiconductor is used for the semiconductor layer 520, covering the side surface of the insulating layer 524 with the insulating layer 554 not only prevents oxygen from diffusing to the outside through the insulating layer 524 but also prevents excessive oxygen from being supplied to the semiconductor layer 520 from the insulating layer 524 side.

[0214] Note that an insulating layer is preferably provided between the insulating layer 580, the insulating layer 554, the conductive layer 542, and the semiconductor layer 520b and the insulating layer 550. Aluminum oxide, hafnium oxide, or the like is preferably used for the insulating layer. By providing the insulating layer, it is possible to suppress desorption of oxygen from the semiconductor layer 520 to the insulating layer 550, excessive supply of oxygen from the insulating layer 550 to the semiconductor layer 520, oxidation of the conductive layer 542, and the like.

[0215] <Transistor Configuration Example 7> FIG. 12A is a plan view of a transistor 200G that can be used in a semiconductor device according to one embodiment of the present invention. FIG. 12B is a schematic perspective view of the transistor 200G. FIGS. 12C to 12E are cross-sectional views of the transistor 200G. FIG. 12C is a cross-sectional view of a portion indicated by a dashed-dotted line A1-A2 in FIG. 12A and is also a cross-sectional view of the transistor 200G in the channel width direction (Y direction). FIG. 12D is a cross-sectional view of a portion indicated by a dashed-dotted line A3-A4 in FIG. 12A and is also a cross-sectional view of the transistor 200G in the channel width direction. FIG. 12E is a cross-sectional view of a portion indicated by a dashed-dotted line A5-A6 in FIG. 12A and is also a cross-sectional view of the transistor 200G in the channel length direction (X direction). Here, the dashed-dotted line A5-A6 is perpendicular to the dashed-dotted line A1-A2 and the dashed-dotted line A3-A4, and the dashed-dotted line A1-A2 and the dashed-dotted line A3-A4 are parallel to each other. Note that some components are omitted from the plan view of FIG. 12A and the perspective schematic view of FIG. 12B. Also, FIG. 13A shows an enlarged view of the vicinity of the conductive layer 260 in FIG. 12E. Also, FIG. 13B shows an enlarged view of the vicinity of the semiconductor layer 230 in FIG. 12C.

[0216] The transistor 200G according to this embodiment includes an insulating layer 295 on a substrate (not shown), an insulating layer 296 on the insulating layer 295, an insulating layer 291 on the insulating layer 296, an insulating layer 292 on the insulating layer 291, a semiconductor layer 230 on the insulating layer 292, conductive layers 242a and 242b on the semiconductor layer 230 and the insulating layer 292, an insulating layer 250 on the semiconductor layer 230, and a conductive layer 260 (conductive layer 260a and conductive layer 260b) on the insulating layer 250. Note that in this specification, the conductive layer 242a and the conductive layer 242b may be collectively referred to as the conductive layer 242.

[0217] An insulating layer 235 is provided on the conductive layer 242, and an insulating layer 280 is provided on the insulating layer 235. The insulating layer 250 and the conductive layer 260 are provided inside a first opening that penetrates the insulating layer 280 and the insulating layer 235 and reaches the semiconductor layer 230. In a plan view, the first opening has a region overlapping with the semiconductor layer 230 and a region extending in the Y direction beyond the edge of the semiconductor layer 230. Therefore, in a plan view, the insulating layer 250 and the conductive layer 260 provided inside the first opening also have a region overlapping with the semiconductor layer 230 and a region extending in the Y direction beyond the edge of the semiconductor layer 230. The conductive layer 260 also functions as wiring. The insulating layer 250 has a region in contact with the semiconductor layer 230 within the first opening. Furthermore, an insulating layer 297 is provided on the insulating layer 280 and the conductive layer 260. Furthermore, an insulating layer 298 is provided on the insulating layer 297.

[0218] The insulating layers 295, 297, and 298 preferably have a barrier property against hydrogen, which can prevent impurities such as water or hydrogen from entering the transistor 200G from the outside. Any of the insulating layers 295, 297, and 298 may be used as the barrier insulating layer 50.

[0219] Furthermore, insulating layer 241a is provided in contact with the inner wall of the second opening, which penetrates insulating layer 298, insulating layer 297, insulating layer 280, and insulating layer 235 and reaches conductive layer 242a, and conductive layer 245a is provided in contact with insulating layer 241a. Conductive layer 245a has a region in contact with conductive layer 242a at the bottom of the first opening.

[0220] Furthermore, insulating layer 241b is provided in contact with the inner wall of the third opening, which penetrates insulating layer 298, insulating layer 297, insulating layer 280, and insulating layer 235 to reach conductive layer 242b, and conductive layer 245b is provided in contact with insulating layer 241b. Conductive layer 245b has a region in contact with conductive layer 242b at the bottom of the second opening.

[0221] In this specification, the conductive layers 245a and 245b may be collectively referred to as conductive layers 245. The insulating layers 241a and 241b may be collectively referred to as insulating layers 241.

[0222] The semiconductor layer 230 includes a channel formation region of the transistor 200G. The conductive layer 260 has a region that functions as a gate electrode of the transistor 200G. The insulating layer 250 has a region that functions as a gate insulating layer of the transistor 200G. In the transistor 200G, a region of the semiconductor layer 230 that overlaps with the conductive layer 260 functions as a channel formation region. A region of the conductive layer 260 that overlaps with the semiconductor layer 230 functions as a gate electrode. A region of the insulating layer 250 where the insulating layer 250 and the semiconductor layer 230 overlap and where the insulating layer 250 and the conductive layer 260 overlap functions as a gate insulating layer.

[0223] The conductive layer 242a has a region functioning as one of the source electrode and the drain electrode of the transistor 200G. The conductive layer 245a functions as a plug connected to the conductive layer 242a. The conductive layer 242b has a region functioning as the other of the source electrode and the drain electrode of the transistor 200G. The conductive layer 245b functions as a plug connected to the conductive layer 242b.

[0224] The semiconductor layer 230 is formed on the insulating layer 292. As shown in FIG. 13B , the semiconductor layer 230 has a shape with a high aspect ratio in a cross-sectional view in the channel width direction. Therefore, the semiconductor layer 230 can also be said to have a fin-like shape. A transistor whose semiconductor layer is fin-shaped is also called a "fin transistor," "fin transistor," or "fin transistor," etc.

[0225] Specifically, a Fin-type transistor is a transistor in which, in a cross-sectional view in the channel width direction (Y direction), the channel formation region of the semiconductor layer has two regions (two surfaces) extending in the Z direction, and has a shape in which a length H (described later) is greater than a length Lx (described later). In a cross-sectional view in the channel width direction, a shape in which the length H is greater than the length Lx is preferable because it allows the channel width per unit area to be increased.

[0226] In this specification, the maximum length of the semiconductor layer 230 in the Y direction in the channel formation region is defined as length Lx, and the maximum length of the semiconductor layer 230 in the channel formation region in a direction perpendicular to the surface on which it is formed (e.g., the top surface of the insulating layer 292) is defined as length H.

[0227] The length Lx can also be considered to be the maximum width of the semiconductor layer 230 in the channel formation region. Therefore, "length Lx" can be read as "width Lx." The length H can also be considered to be the maximum height of the semiconductor layer 230 in the channel formation region. Therefore, "length H" can be read as "height H."

[0228] The ratio of the length H to the length Lx is referred to as the aspect ratio of the semiconductor layer 230. The aspect ratio of the semiconductor layer 230 is preferably as large as possible without causing the semiconductor layer 230 to collapse during the manufacturing process of the transistor 200G. The aspect ratio of the semiconductor layer 230 is preferably greater than 1 and less than 400, more preferably greater than 2 and less than 100, more preferably greater than 5 and less than 40, and even more preferably greater than 10 and less than 20. That is, in the channel formation region of the semiconductor layer 230, the height H of the semiconductor layer 230 is preferably at least longer than the length Lx of the semiconductor layer 230. The height H of the semiconductor layer 230 is preferably greater than 1 and less than 400 times the length Lx of the semiconductor layer 230, more preferably greater than 2 and less than 100 times, more preferably greater than 5 and less than 40 times, and even more preferably greater than 10 and less than 20 times. Alternatively, for example, the height H may be greater than 2 and less than 10 times the length Lx. For example, the length Lx is preferably 5 nm or more and 100 nm or less, more preferably 5 nm or more and 50 nm or less, and even more preferably 10 nm or more and 30 nm or less. Also, for example, the height H is preferably 50 nm or more and 2000 nm or less, and more preferably 100 nm or more and 1000 nm or less. Also, for example, the height H can be 50 nm or more and 100 nm or less.

[0229] 13B , in a cross-sectional view in the channel width direction, the angle θ between the formation surface of the semiconductor layer 230 on the insulating layer 292 and the side surface of the semiconductor layer 230 is preferably perpendicular or approximately perpendicular. For example, the angle θ is preferably 80° to 100°, more preferably 85° to 95°.

[0230] An insulating layer 250, a conductive layer 260, and a conductive layer 242 are provided to cover the semiconductor layer 230 having such an aspect ratio. In the transistor 200G, as shown in FIG. 13B , a portion of the insulating layer 250 and a portion of the conductive layer 260 are provided so as to sandwich the semiconductor layer 230 in two. As a result, in a cross-sectional view in the channel width direction, the semiconductor layer 230 and the conductive layer 260 are provided facing each other with the insulating layer 250 sandwiched between the upper portion, the side surface on the A1 side, and the side surface on the A2 side of the semiconductor layer 230. In other words, the upper portion, the side surface on the A1 side, and the side surface on the A2 side of the semiconductor layer 230 each function as a channel formation region. Therefore, compared to when the semiconductor layer 230 is formed in a planar shape, the channel width of the transistor 200G is larger by the amount of the side surface on the A1 side and the side surface on the A2 side of the semiconductor layer 230.

[0231] By increasing the channel width as described above, the on-state current, transconductance, frequency characteristics, and the like of the transistor 200G can be improved. This makes it possible to provide a semiconductor device with high operating speed. Furthermore, in the above structure, by providing the semiconductor layer 230, the channel width can be increased without increasing the area occupied by the transistor 200G. This allows for miniaturization or high integration of the semiconductor device.

[0232] Furthermore, as shown in FIG. 13B and other figures, it is preferable that the upper portion of the semiconductor layer 230 has a curved shape. Such a curved shape can prevent defects such as voids from being formed in the insulating layer 250 and the conductive layer 242 near the upper portion of the semiconductor layer 230. Note that in FIG. 13B and other figures, a symmetrical structure is shown in which curved shapes are provided on both the A1 side (A3 side) and the A2 side (A4 side) of the upper portion of the semiconductor layer 230, but the present invention is not limited to this. For example, an asymmetrical structure may also be used in which a curved shape is provided on either the A1 side (A3 side) or the A2 side (A4 side) of the upper portion of the semiconductor layer 230.

[0233] When an oxide semiconductor is used as the semiconductor layer 230, as shown in FIGS. 13A and 13B, a structure including the semiconductor layer 230a, the semiconductor layer 230b, and the semiconductor layer 230c disclosed in the third embodiment can be applied.

[0234] 13A and 13B , when an oxide semiconductor is used for the semiconductor layer 230, the insulating layer 250 preferably has a stacked structure of an insulating layer 250a in contact with the semiconductor layer 230, an insulating layer 250b over the insulating layer 250a, an insulating layer 250c over the insulating layer 250b, and an insulating layer 250d over the insulating layer 250c. In this case, the insulating layer 250a and the insulating layer 250c preferably have a function of capturing hydrogen or fixing hydrogen.

[0235] Examples of insulating layers having the function of capturing or fixing hydrogen include metal oxides having an amorphous structure. For example, it is preferable to use a metal oxide such as magnesium oxide or an oxide containing one or both of aluminum and hafnium as the insulating layer 250a and the insulating layer 250c. In such metal oxides having an amorphous structure, oxygen atoms have dangling bonds, and the dangling bonds may have the property of capturing or fixing hydrogen. In other words, metal oxides having an amorphous structure can be said to have a high ability to capture or fix hydrogen.

[0236] Furthermore, it is preferable to use a high-dielectric constant (high-k) material for the insulating layer 250a and the insulating layer 250c. An example of a high-k material is an oxide containing one or both of aluminum and hafnium. Using a high-k material for the insulating layer 250a and the insulating layer 250c makes it possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulating layer. Furthermore, it is possible to reduce the equivalent oxide thickness (EOT) of the insulating layer that functions as the gate insulating layer.

[0237] For the insulating layer 250a and the insulating layer 250c, an oxide containing one or both of aluminum and hafnium is preferably used, and an oxide having an amorphous structure and containing one or both of aluminum and hafnium is more preferably used.

[0238] In this embodiment, aluminum oxide is used as the insulating layer 250a. The aluminum oxide preferably has an amorphous structure. By providing the insulating layer 250a in contact with the semiconductor layer 230, hydrogen contained in the semiconductor layer 230 and the like can be more effectively captured and fixed to the insulating layer 250a.

[0239] In this embodiment, hafnium oxide is used as the insulating layer 250c. Here, by providing the insulating layer 250c between the insulating layer 250b and the insulating layer 250d, hydrogen contained in the insulating layer 250b and the like can be more effectively captured and fixed.

[0240] Next, the insulating layer 250b is preferably an insulating layer that is stable to heat, such as silicon oxide or silicon oxynitride. The silicon oxide film used as the insulating layer 250b is preferably formed by a PEALD method.

[0241] In order to suppress oxidation of the conductive layer 242a, the conductive layer 242b, and the conductive layer 260, a barrier insulating layer against oxygen is preferably provided near each of the conductive layer 242a, the conductive layer 242b, and the conductive layer 260. A film having lower oxygen permeability than a silicon oxide film or a silicon oxynitride film may be used as the barrier insulating layer against oxygen. In the semiconductor device described in this embodiment, the insulating layer is, for example, the insulating layer 250a, the insulating layer 250d, the insulating layer 250c, and the insulating layer 235.

[0242] The insulating layer 250a preferably has a barrier property against oxygen. The insulating layer 250a is preferably at least less permeable to oxygen than the insulating layer 280. The insulating layer 250a has a region in contact with the side surface of the conductive layer 242a and the side surface of the conductive layer 242b. The insulating layer 250a has a barrier property against oxygen, which can prevent the side surfaces of the conductive layer 242a and the conductive layer 242b from being oxidized and forming an oxide film on the side surface. This can prevent a decrease in the on-state current or the field-effect mobility of the transistor 200G.

[0243] The insulating layer 250a is provided in contact with the top surface and side surfaces of the semiconductor layer 230 and the top surface of the insulating layer 292. The insulating layer 250a has a barrier property against oxygen, which can suppress oxygen from being released from the channel formation region of the semiconductor layer 230 when heat treatment or the like is performed. Therefore, oxygen vacancies can be reduced in the semiconductor layer 230.

[0244] Furthermore, by providing the insulating layer 250a, it is possible to suppress the supply of an excessive amount of oxygen from the insulating layer 280 to the semiconductor layer 230, and to supply an appropriate amount of oxygen to the semiconductor layer 230. Therefore, it is possible to suppress the source region and the drain region from being excessively oxidized, which would result in a decrease in the on-state current or a decrease in the field-effect mobility of the transistor 200G.

[0245] The insulating layer 250d also preferably has a barrier property against oxygen. The insulating layer 250d is provided between the channel formation region of the semiconductor layer 230 and the conductive layer 260 and between the insulating layer 280 and the conductive layer 260. This structure can prevent oxygen contained in the channel formation region of the semiconductor layer 230 from diffusing into the conductive layer 260 and forming oxygen vacancies in the channel formation region of the semiconductor layer 230. Furthermore, it can prevent oxygen contained in the semiconductor layer 230 and oxygen contained in the insulating layer 280 from diffusing into the conductive layer 260 and oxidizing the conductive layer 260. The insulating layer 250d is preferably at least less permeable to oxygen than the insulating layer 280. For example, a silicon nitride film is preferably used as the insulating layer 250d. In this case, the insulating layer 250d is an insulating layer containing at least nitrogen and silicon.

[0246] Examples of the barrier insulating layer against oxygen include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate).

[0247] The insulating layer 250d preferably has a barrier property against hydrogen, thereby preventing impurities such as hydrogen contained in the conductive layer 260 from diffusing into the semiconductor layer 230. The insulating layer 250d may also serve as a barrier insulating layer 50.

[0248] The insulating layer 235 also preferably has a barrier property against oxygen. The insulating layer 235 is provided between the insulating layer 280 and the conductive layer 242a and between the insulating layer 280 and the conductive layer 242b. The insulating layer 235 is provided in contact with the side surface of the conductive layer 242, the side surface of the semiconductor layer 230, and the top surface of the insulating layer 292. This configuration can prevent oxygen contained in the insulating layer 280 from diffusing into the conductive layer 242. Therefore, it is possible to prevent the conductive layer 242 from being oxidized by the oxygen contained in the insulating layer 280 and its resistivity from increasing. The insulating layer 235 is preferably at least less permeable to oxygen than the insulating layer 280. For example, it is preferable to use silicon nitride as the insulating layer 235. In this case, the insulating layer 235 is an insulating layer containing at least nitrogen and silicon.

[0249] In order to suppress a decrease in the hydrogen concentrations in the source region and the drain region in the semiconductor layer 230, it is preferable to provide a barrier insulating layer against hydrogen near each of the source region and the drain region. In the semiconductor device described in this embodiment, the barrier insulating layer against hydrogen is, for example, the insulating layer 235. The insulating layer 235 may be the barrier insulating layer 50.

[0250] Examples of the barrier insulating layer against hydrogen include oxides such as aluminum oxide, hafnium oxide, and tantalum oxide, and nitrides such as silicon nitride. For example, the insulating layer 235 preferably has a single-layer structure or a stacked-layer structure of the above-mentioned barrier insulating layers against hydrogen.

[0251] By providing the insulating layer 235 as described above, it is possible to reduce the diffusion of hydrogen in the source and drain regions to the outside, thereby suppressing a decrease in the hydrogen concentration in the source and drain regions, thereby making the source and drain regions n-type.

[0252] With the above structure, the channel formation region can be made i-type or substantially i-type, and the source region and drain region can be made n-type, thereby providing a semiconductor device with excellent electrical characteristics. Furthermore, with the above structure, the semiconductor device can have excellent electrical characteristics even when miniaturized or highly integrated. Furthermore, miniaturizing the transistor 200G can improve high-frequency characteristics. Specifically, the cutoff frequency can be improved.

[0253] The insulating layers 250a to 250d function as part of a gate insulating layer. The insulating layers 250a to 250d, together with the conductive layer 260, are provided in an opening formed in the insulating layer 280. To miniaturize the transistor 200G, the insulating layers 250a to 250d are preferably thin. The thicknesses of the insulating layers 250a to 250d are preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5.0 nm, more preferably 0.5 nm to 5.0 nm, still more preferably 1.0 nm to less than 5.0 nm, and still more preferably 1.0 nm to 3.0 nm. Note that each of the insulating layers 250a to 250d may have a region with the above-described thickness at least in part.

[0254] The thickness of the silicon oxide film used as the insulating layer 250 is preferably 0.7 nm or more and 3 nm or less.

[0255] In order to thin the insulating layers 250a to 250d as described above, it is preferable to form the insulating layers 250a to 250d by using the ALD method. Furthermore, it is preferable to form the insulating layers 250a to 250d in openings in the insulating layer 280, etc., by using the ALD method. By forming the insulating layer 250 by using the ALD method, it is possible to form the insulating layer 250 with good coverage on the side surfaces of the first openings formed in the insulating layer 280, the side edges of the conductive layer 242a, and the side edges of the conductive layer 242b, etc.

[0256] Although the insulating layer 250 has been described above as having a four-layer structure of the insulating layers 250a to 250d, the present invention is not limited to this. The insulating layer 250 can have a structure including at least one of the insulating layers 250a to 250d. By forming the insulating layer 250 using one, two, or three of the insulating layers 250a to 250d, the manufacturing process of the transistor 200G can be simplified and the productivity of a semiconductor device including the transistor 200G can be improved.

[0257] As shown in FIG. 12A , the shape of the semiconductor layer 230 in a planar view is preferably a circumferential shape (which can also be referred to as a frame shape, an annular shape, a doughnut shape, or a closed curve shape) with both ends coinciding. That is, it is preferable that the semiconductor layer 230 has a structure including a plurality of portions extending in the channel width direction (A1-A2 direction) and a plurality of portions extending in the channel length direction (A5-A6 direction). This can prevent the semiconductor layer 230 from collapsing during the transistor fabrication process when the aspect ratio of the semiconductor layer 230 is increased. Note that the semiconductor layer 230 shown in FIG. 12A can also be described as having a shape with an opening in the center. In FIG. 12A , the shape of the semiconductor layer 230 in a planar view is line-symmetrical about the A1-A2 axis, but the present invention is not limited to this. For example, the shape of the semiconductor layer 230 in a planar view may be asymmetrical.

[0258] 12A is a structure in which two circumferential semiconductor layers 230 are formed in the Y direction. As shown in Fig. 12A, the semiconductor layer 230 preferably overlaps with the conductive layer 260 at two or more locations in a plan view. Therefore, the conductive layer 260 preferably has two or more regions that overlap with the semiconductor layer 230. In other words, it is preferable that the semiconductor layer 230 and the conductive layer 260 have two or more regions where they overlap with each other.

[0259] With this structure, as shown in FIG. 12B , multiple fin-shaped semiconductor layers 230 are formed in a cross-sectional view in the channel width direction. Each of the multiple fin-shaped semiconductor layers 230 includes a channel formation region. That is, the transistor 200G functions as a multi-channel transistor. Therefore, the channel width of the transistor 200G can be further increased, thereby increasing the on-state current. Therefore, the operating speed of a semiconductor device including the transistor 200G can be increased.

[0260] Although the above description has been given of a configuration in which two circumferential semiconductor layers 230 are provided, the present invention is not limited to this. For example, a configuration in which one or three or more circumferential semiconductor layers 230 are provided is also possible. It is also possible to combine circumferential semiconductor layers 230 to form a semiconductor layer 230 having a shape with a plurality of openings. It is also possible to use a semiconductor layer 230 in a lattice shape in plan view.

[0261] <Transistor Configuration Example 8> Next, a transistor 200H, which is a variation of the transistor 200G, will be described. FIG. 14A is a plan view of the transistor 200H that can be used in a semiconductor device according to one embodiment of the present invention. FIG. 14B is a schematic perspective view of the transistor 200H. FIGS. 14C to 14E are cross-sectional views of the transistor 200H. FIG. 14C is a cross-sectional view of a portion indicated by a dashed-dotted line A1-A2 in FIG. 14A and is also a cross-sectional view of the transistor 200H in the channel width direction (Y direction). FIG. 14D is a cross-sectional view of a portion indicated by a dashed-dotted line A3-A4 in FIG. 14A and is also a cross-sectional view of the transistor 200H in the channel width direction. FIG. 14E is a cross-sectional view of a portion indicated by a dashed-dotted line A5-A6 in FIG. 14A and is also a cross-sectional view of the transistor 200H in the channel length direction (X direction). Here, the dashed-dotted line A5-A6 is perpendicular to the dashed-dotted line A1-A2 and the dashed-dotted line A3-A4, and the dashed-dotted line A1-A2 and the dashed-dotted line A3-A4 are parallel to each other. Note that in the plan view of Figure 14A and the schematic perspective view of (B), some components are omitted. Also, Figure 15 shows an enlarged view of the semiconductor layer 230 of Figure 14C.

[0262] 14B to 14E , a configuration in which an insulating layer 294 is provided under the semiconductor layer 230 is also possible. The planar shape of the insulating layer 294 (the shape when viewed from the Z direction) is the same as that of the semiconductor layer 230. Therefore, in a planar view, the insulating layer 294 overlaps with the semiconductor layer 230. The lower surface of the insulating layer 294 is in contact with the insulating layer 292, the side surface of the insulating layer 294 is in contact with the insulating layer 250 and the conductive layer 242a, and the upper surface of the insulating layer 294 is in contact with the lower surface of the semiconductor layer 230. The insulating layer 294 may be made of an insulating material that can be used for the insulating layer 250b. For example, silicon oxide may be used for the insulating layer 294.

[0263] 14A to 14E correspond to Fig. 12A to 12E. Also, Fig. 15 corresponds to Fig. 13B. Therefore, matters not explained below regarding the configurations according to Fig. 14A to 14E and Fig. 15 can be understood by referring to the explanations given above regarding Fig. 12A to 12E and Fig. 13B.

[0264] 15 , it is preferable that the thickness t2 of the insulating layer 250 at the bottom of the first opening be thinner than the thickness t1 (the length of the insulating layer 294 in the direction perpendicular to the surface on which it is formed) of the insulating layer 294. With this configuration, the lower surface of the conductive layer 260 (conductive layer 260 a) located in the first opening can be positioned lower than the lower surface of the semiconductor layer 230 by the difference (t1 − t2) between the thickness t1 and the thickness t2.

[0265] By positioning the lower surface of the conductive layer 260 below the lower surface of the semiconductor layer 230, a sufficient gate electric field can be applied from the upper end to the lower end of the semiconductor layer 230. In other words, within the opening of the insulating layer 280 or the like, the entire semiconductor layer 230 is electrically surrounded by the electric field of the conductive layer 260, allowing it to function as a channel formation region. This configuration prevents the lower end of the semiconductor layer 230 from functioning as a parasitic channel, thereby reducing leakage current between the source electrode and the drain electrode. Furthermore, it is possible to suppress poor characteristics, such as normally-on of the transistor, that are caused by the parasitic channel. In other words, it is possible to improve the electrical characteristics of the transistor 200H.

[0266] Furthermore, as described above, the channel width can be increased by making the semiconductor layer 230 function as a channel formation region from the top end to the bottom end, which can improve the on-state current, transconductance, frequency characteristics, and the like of the transistor 200H.

[0267] In this specification and the like, a transistor structure in which the electric field of the gate electrode electrically surrounds the channel formation region as described above is referred to as a surrounded channel (S-channel) structure. In the S-channel structure, the gate electrode is arranged so as to surround at least two or more sides of the channel (specifically, two, three, or four sides, etc.). By adopting the S-channel structure, it is possible to improve resistance to the short channel effect, in other words, to provide a transistor in which the short channel effect is less likely to occur.

[0268] Note that the S-channel structure electrically surrounds the channel formation region, and therefore can be said to be substantially equivalent to a Gate All Around (GAA) structure or a Lateral Gate All Around (LGAA) structure. By forming the transistor 200H in the S-channel, GAA, or LGAA structure, the channel formation region formed at or near the interface between the semiconductor layer 230 and the insulating layer 250, which functions as a gate insulating layer, can be the entire bulk. Therefore, the current density flowing through the transistor can be improved, thereby increasing the on-state current or the field-effect mobility of the transistor. In one embodiment of the present invention, the semiconductor layer 230 has a CAAC structure and a fin-like structure. With this structure, the current paths flowing to the source and drain of the transistor can be parallel to the a-b plane of the crystal axis. In other words, an oxide semiconductor having a CAAC structure and a fin-like structure has a conduction path equivalent to that of a two-dimensional semiconductor material, and by using such an oxide semiconductor, a device having two-dimensional conduction can be fabricated.

[0269] <Transistor Configuration Example 9> A transistor 200I, which is a variation of the transistor 200G, is shown in FIGS. 16A to 16E. The transistor 200I differs from the transistor 200G in that a conductive layer 205 is provided under an insulating layer 291. Note that FIGS. 16A to 16E correspond to FIGS. 12A to 12E. Matters not described below regarding the configurations in FIGS. 16A to 16E can be understood with reference to the description of FIGS. 12A to 12E.

[0270] The conductive layer 205 has a region overlapping with the channel formation region of the semiconductor layer 230. Thus, the conductive layer 205 has a region that functions as a gate electrode, similar to the conductive layer 260. The conductive layer 260 may be referred to as a first gate electrode (upper gate electrode) of the transistor 200I, and the conductive layer 205 may be referred to as a second gate electrode (lower gate electrode) of the transistor 200I. When the conductive layer 260 is referred to as a gate electrode of the transistor 200I, the conductive layer 205 may be referred to as a backgate electrode of the transistor 200I.

[0271] When the conductive layer 205 is provided under the insulating layer 291 as in the transistor 200I, each of the insulating layers 292 and 291 has a region that functions as a gate insulating layer, similar to the insulating layer 250. Specifically, a region of each of the insulating layers 292 and 291 that overlaps with the conductive layer 205 functions as a gate insulating layer. The insulating layer 250 may be referred to as a first gate insulating layer (upper gate insulating layer), and the insulating layer 292 and the insulating layer 291 may be referred to as a second gate insulating layer (lower gate insulating layer).

[0272] In the transistor 200I, the conductive layer 205 is disposed so as to overlap with the semiconductor layer 230 and the conductive layer 260. In FIGS. 16C and 16E , the conductive layer 205 is provided inside a fourth opening that penetrates the insulating layer 296 and reaches the insulating layer 295. The fourth opening has, in a plan view, a region that overlaps with the semiconductor layer 230 and a region that extends in the Y direction beyond the end of the semiconductor layer 230. Therefore, the conductive layer 205 provided inside the fourth opening also has, in a plan view, a region that overlaps with the semiconductor layer 230 and a region that extends in the Y direction beyond the end of the semiconductor layer 230. The conductive layer 205 also functions as a wiring.

[0273] 16C and 16E , the conductive layer 205 preferably includes a conductive layer 205a and a conductive layer 205b. The conductive layer 205a is provided in contact with the bottom and sidewalls of the fourth opening. The conductive layer 205b is provided so as to fill a recess in the conductive layer 205a formed along the bottom and sidewalls of the fourth opening. Here, it is preferable that the top surface of the conductive layer 205 coincides or substantially coincides with the top surface of the insulating layer 296. That is, when viewed from the Y direction, it is preferable that the shortest distance from the top surface of the substrate (not shown) to the top surface of the insulating layer 296 coincides or substantially coincides with the shortest distance from the top surface of the substrate to the top surface of the conductive layer 205.

[0274] Here, the conductive layer 205a contains hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ It is preferable to have a conductive material that has a function of suppressing the diffusion of impurities such as copper atoms, etc., or a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules, etc.).

[0275] By using a conductive material that has a function of reducing hydrogen diffusion for the conductive layer 205a, impurities such as hydrogen contained in the conductive layer 205b can be prevented from diffusing into the semiconductor layer 230 via the insulating layer 296 or the like. Furthermore, by using a conductive material that has a function of suppressing oxygen diffusion for the conductive layer 205a, it is possible to suppress oxidation of the conductive layer 205b and a decrease in conductivity. Examples of conductive materials that have a function of suppressing oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. The conductive layer 205a can have a single-layer structure or a stacked-layer structure of the above conductive materials. For example, the conductive layer 205a preferably contains titanium nitride.

[0276] The conductive layer 205b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component, for example, tungsten.

[0277] As described above, the conductive layer 205 can function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 200I can be controlled by changing the potential applied to the conductive layer 205 independently of the potential applied to the conductive layer 260. In particular, applying a negative potential to the conductive layer 205 can increase the Vth of the transistor 200I and reduce its off-state current. Therefore, applying a negative potential to the conductive layer 205 can reduce the drain current when the potential of the conductive layer 260 is 0 V compared to not applying a negative potential to the conductive layer 205.

[0278] The electrical resistivity of the conductive layer 205 is designed taking into consideration the potential applied to the conductive layer 205, and the film thickness of the conductive layer 205 is set to match the electrical resistivity. The film thickness of the insulating layer 296 is approximately the same as that of the conductive layer 205. Here, it is preferable to make the film thicknesses of the conductive layer 205 and the insulating layer 296 thin within the range permitted by the design of the conductive layer 205. By making the film thickness of the insulating layer 296 thin, the absolute amount of impurities such as hydrogen contained in the insulating layer 296 can be reduced, and therefore, the diffusion of the impurities into the semiconductor layer 230 can be suppressed.

[0279] Although the above describes a stacked structure of the conductive layer 205a and the conductive layer 205b, the present invention is not limited to this, and the conductive layer 205 may have a single-layer structure or a stacked structure of three or more layers. For example, when the conductive layer 205 has a three-layer stacked structure, a structure can be adopted in which a conductive layer made of the same material as the conductive layer 205a is further provided on the conductive layer 205b in the stacked structure of the conductive layer 205a and the conductive layer 205b. In this case, the conductive layer can be formed so that the top surface of the conductive layer 205b is lower than the top of the conductive layer 205a, and so as to fill the recess formed by the conductive layer 205a and the conductive layer 205b.

[0280] In addition to the materials disclosed in this embodiment, the materials for conductive layers shown in other embodiments can be used as materials for conductive layer 205, conductive layer 242, conductive layer 245, and conductive layer 260. In addition to the materials disclosed in this embodiment, the materials for insulating layer shown in other embodiments can be used as materials for insulating layer 295, insulating layer 296, insulating layer 291, insulating layer 292, insulating layer 241, insulating layer 250, insulating layer 235, insulating layer 280, insulating layer 297, and insulating layer 298.

[0281] The transistor 200I described in this embodiment can be used as a transistor included in the semiconductor device 100A or 100B. The transistor 200I can have a large on-state current without increasing the occupation area.

[0282] <Constituent Materials of Transistor> Next, constituent materials that can be used for the transistor 200 (transistor 200A, transistor 200B, transistor 200C, transistor 200D, transistor 200E, transistor 200F, transistor 200G, transistor 200H, and transistor 200I) will be described.

[0283] [Substrate] When a transistor is provided on a substrate, the material used for the substrate is not particularly limited. The material used for the substrate is determined depending on the purpose, taking into consideration the presence or absence of light transparency and heat resistance sufficient to withstand heat treatment. For example, an insulating substrate, a semiconductor substrate, or a conductive substrate can be used as the substrate. Examples of insulating substrates that can be used include glass substrates such as barium borosilicate glass and aluminoborosilicate glass, ceramic substrates, quartz substrates, sapphire substrates, and stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates). Furthermore, semiconductor substrates, flexible substrates, resin substrates, and the like can also be used as the substrate.

[0284] Examples of the semiconductor substrate include a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, there is also a semiconductor substrate having an insulator region inside the semiconductor substrate, such as an SOI (Silicon On Insulator) substrate. The semiconductor substrate may be a single-crystal semiconductor or a polycrystalline semiconductor.

[0285] Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Other examples include substrates containing metal nitrides and substrates containing metal oxides. Furthermore, examples include substrates in which a conductive layer or a semiconductor layer is provided on an insulator substrate, substrates in which a conductive layer or an insulating layer is provided on a semiconductor substrate, and substrates in which a semiconductor layer or an insulating layer is provided on a conductive substrate.

[0286] Examples of materials that can be used for the flexible substrate or resin substrate include polyesters such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), polyacrylonitrile, acrylic resin, polyimide, polymethyl methacrylate, polycarbonate (PC), polyethersulfone (PES), polyamide (nylon, aramid, etc.), polysiloxane, cycloolefin resin, polystyrene, polyamideimide, polyurethane, polyvinyl chloride, polyvinylidene chloride, polypropylene, polytetrafluoroethylene (PTFE), ABS resin, and cellulose nanofiber.

[0287] By using the above materials for the substrate, a lightweight semiconductor device can be provided. Furthermore, by using the above materials for the substrate, a semiconductor device that is resistant to impact can be provided. Furthermore, by using the above materials for the substrate, a semiconductor device that is less likely to break can be provided. Furthermore, it is also possible to use a substrate on which elements are provided. Elements that can be provided on the substrate include capacitance elements, resistance elements, switch elements, light-emitting elements, memory elements, etc.

[0288] [Insulating Layer] An inorganic insulating film is used for each of the insulating layers (insulating layer 202, insulating layer 204, insulating layer 206, insulating layer 209, insulating layer 295, insulating layer 296, insulating layer 291, insulating layer 292, insulating layer 294, insulating layer 241, insulating layer 257, insulating layer 250, insulating layer 258, insulating layer 258a, insulating layer 258b, insulating layer 259, insulating layer 264, insulating layer 266, insulating layer 268, insulating layer 514, insulating layer 516, insulating layer 235, insulating layer 280, insulating layer 297, insulating layer 298, insulating layer 522, insulating layer 524, insulating layer 541, insulating layer 554, insulating layer 580, insulating layer 574, insulating layer 581, etc.). Examples of inorganic insulating films include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. Examples of oxide insulating films include silicon oxide films, aluminum oxide films, magnesium oxide films, gallium oxide films, germanium oxide films, yttrium oxide films, zirconium oxide films, lanthanum oxide films, neodymium oxide films, hafnium oxide films, tantalum oxide films, cerium oxide films, gallium zinc oxide films, and hafnium aluminate films. Examples of nitride insulating films include silicon nitride films and aluminum nitride films. Examples of oxynitride insulating films include silicon oxynitride films, aluminum oxynitride films, gallium oxynitride films, yttrium oxynitride films, and hafnium oxynitride films. Examples of nitride oxide insulating films include silicon nitride oxide films and aluminum nitride oxide films. Furthermore, organic insulating films can also be used for insulating layers included in semiconductor devices.

[0289] In this specification and the like, an oxynitride refers to a material whose composition contains more oxygen than nitrogen, and a nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0290] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulating layers. Using high-k materials for insulating layers that function as gate insulating layers, such as insulating layer 204 and insulating layer 264, enables lower voltages during transistor operation while maintaining the physical film thickness. It also enables thinner equivalent oxide thickness (EOT) for the gate insulating layer. On the other hand, using a material with a low dielectric constant for an insulating layer that functions as an interlayer film can reduce the parasitic capacitance that occurs between wiring. Therefore, it is important to select materials according to the function of the insulating layer. Note that materials with a low dielectric constant also have high dielectric strength.

[0291] Examples of materials with a high relative dielectric constant (high-k) include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0292] Examples of materials with a low relative dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Other inorganic insulating materials with a low relative dielectric constant include silicon oxide doped with fluorine, silicon oxide doped with carbon, and silicon oxide doped with carbon and nitrogen. Another example is silicon oxide having vacancies. These silicon oxides may contain nitrogen.

[0293] [Conductive Layer] For the conductive layers (conductive layer 205, conductive layer 208, conductive layer 219, conductive layer 242, conductive layer 245, conductive layer 255, conductive layer 260, conductive layer 267, conductive layer 261, conductive layer 265, conductive layer 505, conductive layer 545, conductive layer 560, etc.) used in the transistor 200, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., an alloy containing any of the above metal elements, or an alloy combining any of the above metal elements. As the alloy containing any of the above metal elements, a nitride of the alloy or an oxide of the alloy can also be used. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, semiconductors with high electrical conductivity, typified by polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide can also be used.

[0294] In addition, conductive materials containing nitrogen, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum; conductive materials containing oxygen, such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel; and materials containing metal elements, such as titanium, tantalum, or ruthenium, are preferred because they are conductive materials that are resistant to oxidation, have the function of suppressing oxygen diffusion, or maintain conductivity even after absorbing oxygen. Examples of conductive materials containing oxygen include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide (also referred to as ITO), indium tin oxide containing titanium oxide, indium tin oxide with added silicon (also referred to as ITSO), indium zinc oxide (also referred to as IZO (registered trademark)), and indium zinc oxide containing tungsten oxide. In this specification and the like, a conductive layer formed using a conductive material containing oxygen may be referred to as an oxide conductive layer.

[0295] Conductive materials containing tungsten, copper or aluminum as a main component are preferred because they have high conductivity.

[0296] In addition, it is possible to use a plurality of conductive layers formed from the above materials in a stacked state. For example, it is possible to use a stacked structure in which the above-mentioned material containing a metal element and a conductive material containing oxygen are combined. It is also possible to use a stacked structure in which the above-mentioned material containing a metal element and a conductive material containing nitrogen are combined. It is also possible to use a stacked structure in which the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen are combined.

[0297] For example, when an oxide semiconductor, which is a type of metal oxide, is used for the semiconductor layer 203 of the transistor 200A or 200B, a conductive layer functioning as a gate electrode, such as the conductive layer 205 or the conductive layer 219, may have a stacked structure in which a material containing the metal element described above and a conductive material containing oxygen are combined. In this case, the conductive material containing oxygen is preferably provided on the semiconductor layer 203 side. By providing the conductive material containing oxygen on the semiconductor layer 203 side, oxygen desorbed from the conductive material is easily supplied to a channel formation region of the semiconductor layer 203.

[0298] When an oxide semiconductor, which is a type of metal oxide, is used for the semiconductor layer 203, the semiconductor layer 263, or the semiconductor layer 520, the conductive layers 208a, 208b, 255, 261, 542a, and 542b are conductive layers in contact with the semiconductor layer 203, the semiconductor layer 263, or the semiconductor layer 520, respectively. Therefore, a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, a metal oxide having conductivity (also referred to as an oxide conductor), or a conductive material that has a function of suppressing oxygen diffusion may be used for each of the conductive layers. Examples of the conductive material include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layers 208a, 208b, 255, 261, 542a, and 542b.

[0299] By using a conductive material containing oxygen for the conductive layers 208a, 208b, 255, 261, 542a, and 542b, the conductive layers 208a, 208b, 255, 261, 542a, and 542b, the conductivity can be maintained even if the conductive layers 208a, 208b, 255, 261, 542a, and 542b absorb oxygen. For example, even when an insulating layer containing excess oxygen is used as an insulating layer in contact with the conductive layers 208a, 208b, 255, 261, 542a, and 542b, the conductivity of the conductive layers 208a, 208b, 255, 261, 542a, and 542b can be maintained, which is preferable. For each of the conductive layer 208a, the conductive layer 208b, the conductive layer 255, the conductive layer 261, the conductive layer 542a, and the conductive layer 542b, for example, ITO, ITSO, IZO (registered trademark), or the like can be used.

[0300] [Semiconductor Layer] As the semiconductor layer (semiconductor layer 203, semiconductor layer 230, semiconductor layer 263, semiconductor layer 520, etc.), a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like can be used alone or in combination. Examples of the semiconductor material include silicon and germanium. Compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, and nitride semiconductors can also be used. Examples of the compound semiconductor include an organic material having semiconductor properties or a metal oxide (also referred to as an oxide semiconductor) having semiconductor properties. Note that these semiconductor materials may contain impurities as dopants.

[0301] It is possible to use a semiconductor made of a single element or a compound semiconductor as the semiconductor layer. Examples of semiconductors made of a single element include silicon and germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. Other examples of compound semiconductors include organic semiconductors and nitride semiconductors. Note that oxide semiconductors are also a type of compound semiconductor. Note that these semiconductor materials may contain impurities as dopants.

[0302] When silicon is used for the semiconductor layer, examples of silicon that can be used for the semiconductor layer include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low temperature polysilicon (LTPS).

[0303] For example, the transistor 200A or 200B can function as a p-type transistor by using silicon for the semiconductor layer 203 and including boron as a p-type dopant in the regions 203a and 203c of the semiconductor layer 203. Note that when the regions 203a and 203c of the semiconductor layer 203 include both an n-type dopant (phosphorus, arsenic, or the like) and a p-type dopant, the conductivity type with a higher dopant concentration is likely to be realized.

[0304] Two-dimensional materials that function as semiconductors can be used as the semiconductor layer of a transistor. Two-dimensional materials, also known as layered materials, are a general term for a group of materials that have a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds weaker than covalent or ionic bonds, such as van der Waals bonds. Layered materials have high electrical conductivity within a unit layer, i.e., high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity for the semiconductor layer, a transistor with a large on-state current can be provided.

[0305] Examples of the layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen (an element belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used as the semiconductor layer of a transistor include molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ ) etc.

[0306] When an oxide semiconductor, which is a type of metal oxide, is used for the semiconductor layer, the band gap of the metal oxide is preferably 2.0 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a wide band gap for the semiconductor layer, the off-state current of the transistor can be significantly reduced. A transistor having an oxide semiconductor in a channel formation region has a low off-state current, and therefore, the power consumption of the semiconductor device can be reduced. Note that an oxide semiconductor will be described in detail in Embodiment 3, and indium oxide will be described in detail in Embodiment 4.

[0307] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiment modes and examples.

[0308] Embodiment 3 In this embodiment, an oxide semiconductor layer that can be used as a semiconductor layer of the transistor M3 and the transistor M4 will be described.

[0309] [Oxide Semiconductor Layer] An oxide semiconductor layer that can be used as a semiconductor layer of the transistor M3 or the transistor M4 preferably contains a crystalline metal oxide. Among oxide semiconductors, indium oxide will be described later in Embodiment 4. Examples of the structure of a crystalline metal oxide include a c-axis aligned crystal (CAAC) structure, a polycrystalline (poly-crystal) structure, and a nanocrystalline (nc) structure. The use of a crystalline metal oxide for the oxide semiconductor layer can reduce the density of defect states in the oxide semiconductor layer. Therefore, the reliability of a transistor including the oxide semiconductor layer of one embodiment of the present invention can be improved, and the reliability of a memory device including the transistor can be improved.

[0310] The oxide semiconductor layer of one embodiment of the present invention preferably includes a metal oxide having a CAAC structure. The CAAC structure is a crystal structure in which a plurality of microcrystals (typically, a plurality of microcrystals having a hexagonal crystal structure) have c-axis orientation and are connected without being oriented in the a-b plane. Furthermore, when a cross section of an oxide semiconductor layer having a CAAC structure is observed using a high-resolution transmission electron microscope (TEM) image, it can be confirmed that metal atoms are arranged in a layered manner in the crystal parts. Therefore, an oxide semiconductor layer having a CAAC structure can also be said to have a structure having layered crystal parts.

[0311] The crystallinity of the oxide semiconductor layer can be analyzed by, for example, X-ray diffraction (XRD), TEM, or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0312] Note that the crystallinity of the semiconductor material included in the oxide semiconductor layer is not particularly limited. For example, the oxide semiconductor layer may include one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single-crystal semiconductor (a semiconductor having a single-crystal structure), or a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part). When the oxide semiconductor layer has crystallinity, deterioration of transistor characteristics can be suppressed in some cases.

[0313] Examples of metal oxides contained in the oxide semiconductor layer of one embodiment of the present invention include gallium oxide (GaOx, where X is an arbitrary number) and zinc oxide (ZnOx, where X is an arbitrary number). The metal oxide according to one embodiment of the present invention preferably contains at least indium (In) and zinc (Zn). The metal oxide preferably contains two or three elements selected from indium, an element M, and zinc. The element M is a metal element or a metalloid element having a high bond energy with oxygen, for example, a metal element or a metalloid element having a bond energy with oxygen higher than that of indium. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium. When the element M contained in the metal oxide is gallium, the metal oxide according to one embodiment of the present invention preferably contains one or more selected from indium, gallium, and zinc. Note that in this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal element" described in this specification and the like may also include metalloid elements.

[0314] Examples of metal oxides according to one embodiment of the present invention include indium zinc oxide (In—Zn oxide), indium tin oxide (In—Sn oxide), indium titanium oxide (In—Ti oxide), indium gallium oxide (In—Ga oxide), indium gallium aluminum oxide (In—Ga—Al oxide), indium gallium tin oxide (In—Ga—Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga—Zn oxide, also referred to as GZO), aluminum zinc oxide (Al—Zn oxide, also referred to as AZO), and indium gallium tin oxide (In—Ga—Sn oxide, also referred to as IGTO). Examples of the usable oxide include indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO). Alternatively, examples of the usable oxide include indium tin oxide containing silicon (also referred to as ITSO), gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide).

[0315] By increasing the ratio of the number of indium atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide (In content), the transistor can obtain high field-effect mobility, large on-state current, and high frequency characteristics. Note that in this specification, a metal oxide in which the ratio of the number of indium atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide is 97.5 atomic % or more is referred to as indium oxide.

[0316] The metal oxide may contain one or more metal elements having a higher period number in the periodic table instead of indium. Alternatively, the metal oxide may contain one or more metal elements having a higher period number in the periodic table in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, including a metal element having a higher period number in the periodic table may improve the field-effect mobility of a transistor. Examples of metal elements having a higher period number in the periodic table include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0317] The metal oxide may contain one or more nonmetallic elements, which may increase the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0318] Furthermore, by increasing the ratio of the number of zinc atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the metal oxide can be made highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0319] Furthermore, by increasing the ratio of the number of atoms of element M to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-state current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, thereby improving reliability.

[0320] In the present embodiment, an In—Ga—Zn oxide may be used as an example of the metal oxide.

[0321] The oxide semiconductor layer of one embodiment of the present invention has crystallinity and preferably has a CAAC structure.

[0322] The oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide using at least two kinds of film formation methods. For example, the oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide using a first film formation method and a second film formation method. Note that an oxide semiconductor layer formed using at least two kinds of film formation methods may be referred to as a hybrid OS.

[0323] The oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide as a first layer by a first deposition method and then forming a metal oxide as a second layer on the first layer by a second deposition method. In this case, it is preferable to use a deposition method that causes less damage to a surface on which the oxide semiconductor layer is to be formed compared to the second deposition method as the first deposition method. By using a deposition method that causes less damage to a surface on which the oxide semiconductor layer is to be formed as the first deposition method, formation of a mixed layer at the interface between the oxide semiconductor layer and a layer on which the oxide semiconductor layer is to be formed can be suppressed. Furthermore, impurities such as silicon can be prevented from being mixed into the second layer, thereby increasing the crystallinity of the oxide semiconductor layer.

[0324] Examples of the first film formation method include atomic layer deposition (ALD), chemical vapor deposition (CVD), molecular beam epitaxy (MBE), and wet methods. Examples of CVD methods include plasma enhanced CVD (PECVD), thermal CVD, photo-assisted CVD, and metal organic CVD (MOCVD). Examples of wet methods include spray coating. The ALD and CVD methods are suitable as the first film formation method because they can reduce damage to the surface to be formed compared to the sputtering method described below.

[0325] Examples of the ALD method include a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, and a plasma enhanced ALD (PEALD) method in which a plasma-excited reactant is used.

[0326] The ALD method can deposit atoms layer by layer, and therefore has the advantages of enabling ultrathin film formation, film formation on high aspect ratio structures or surfaces with large steps, film formation with fewer defects such as pinholes, film formation with excellent coverage, and film formation at low temperatures. Furthermore, the PEALD method may be preferable in some cases because it utilizes plasma, allowing film formation at lower temperatures. Note that some precursors used in the ALD method contain elements such as carbon or chlorine. Therefore, films formed by the ALD method may contain larger amounts of elements such as carbon or chlorine than films formed by other film formation methods. The amounts of these elements can be quantified using X-ray photoelectron spectroscopy (XPS) or secondary ion mass spectrometry (SIMS). In the method for forming a metal oxide film according to one embodiment of the present invention, an ALD method is used. However, since the ALD method employs one or both of a high substrate temperature condition during film formation and an impurity removal treatment, the amount of carbon and chlorine contained in the film may be smaller than that in the case of using an ALD method without employing these conditions.

[0327] Unlike film formation methods in which particles emitted from a target or the like are deposited, the ALD method is a film formation method in which a film is formed by a reaction on the surface of a workpiece. Therefore, it is a film formation method that is less affected by the shape of the workpiece and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio.

[0328] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, the thermal CVD method is a film formation method that can minimize plasma damage to the workpiece because it does not use plasma. Furthermore, the thermal CVD method produces films with fewer defects because no plasma damage occurs during film formation.

[0329] Examples of the second film formation method include sputtering, pulsed laser deposition (PLD), etc. Metal oxides formed using the second film formation method tend to have a CAAC structure.

[0330] Note that the first layer may be, for example, a metal oxide having a microcrystalline structure or an amorphous structure with lower crystallinity than a CAAC structure. By forming a second layer with high crystallinity on the first layer with low crystallinity, or by forming the second layer and then performing heat treatment, the crystallinity of the first layer may be increased using the second layer as a nucleus. This can increase the crystallinity of the entire oxide semiconductor layer, including the vicinity of the interface with the surface on which it is formed.

[0331] Furthermore, a third layer can be further formed on the second layer. Because the second layer has high crystallinity, the third layer can grow crystals using the crystals of the second layer as nuclei or seeds. Therefore, even if a film formation method that easily imparts crystallinity is not used as a film formation method for the third layer, the third layer can be crystallized. Here, for example, by forming the third layer using a film formation method that has higher coverage than the second layer, the oxide semiconductor layer can have both high crystallinity and high coverage throughout the layer.

[0332] For example, the oxide semiconductor layer of one embodiment of the present invention can be fabricated by forming a metal oxide as a first layer by a first deposition method, forming a metal oxide as a second layer by a second deposition method, and forming a metal oxide as a third layer by the first deposition method. Specifically, an ALD method can be used as the first deposition method, and a sputtering method can be used as the second deposition method. The ALD method has better coverage than the sputtering method, and the use of the ALD method as the deposition method for the first layer and the third layer can improve the coverage of the oxide semiconductor layer. Therefore, the oxide semiconductor layer can be well covered over steps, openings, and the like with a high aspect ratio.

[0333] [Method for Manufacturing Oxide Semiconductor Layer] The semiconductor layer 230, which is an oxide semiconductor layer, can be manufactured by, for example, forming a semiconductor layer 230a on the insulating layer 292, which is a surface to be formed, by an ALD method, forming a semiconductor layer 230b, which is an oxide semiconductor layer, on the semiconductor layer 230a, which is an oxide semiconductor layer, by a sputtering method, and forming a semiconductor layer 230c, which is an oxide semiconductor layer, on the semiconductor layer 230b, by an ALD method. Furthermore, after forming the semiconductor layer 230, which is an oxide semiconductor layer, it is preferable to perform heat treatment. The heat treatment can improve the crystallinity of the semiconductor layer 230. The heat treatment here is not limited to heating treatment. For example, it may be heat applied during the manufacturing process.

[0334] The insulating layer 292 corresponds to the insulating layer 202, the insulating layer 256, the insulating layer 258, or the like described in the above embodiments. The insulating layer 292 does not need to be crystalline. When the insulating layer 292 has crystallinity, it may have a crystal structure with low lattice matching with the metal oxide of the semiconductor layer 230.

[0335] As described above, the use of a metal oxide with a high In content in a transistor can increase the field-effect mobility of the transistor. On the other hand, an oxide semiconductor with a high In content tends to become polycrystalline with random crystal axes. The use of a metal oxide with a polycrystalline structure in a transistor adversely affects the initial characteristics or reliability of the transistor. Therefore, by using an oxide semiconductor with a high In content in one or both of the semiconductor layer 230a and the semiconductor layer 230c, crystals that reflect the crystal orientation of the semiconductor layer 230b are formed, thereby suppressing polycrystallization.

[0336] Furthermore, it is preferable that the lattice mismatch between the crystals of the semiconductor layer 230b and the crystals of the semiconductor layer 230a or the semiconductor layer 230c is small. This allows the semiconductor layer 230a or the semiconductor layer 230c to form crystals that reflect the orientation of the crystals of the semiconductor layer 230b. In this case, for example, in cross-sectional observation of the semiconductor layer 230 using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the formation surface are confirmed in the semiconductor layer 230a or the semiconductor layer 230c.

[0337] As long as the lattice mismatch between the crystals of the semiconductor layer 230b and the crystals of the semiconductor layer 230a or 230c is small, the crystal structure of the semiconductor layer 230a or 230c is not particularly limited. The crystal structure of the semiconductor layer 230a or 230c may be any of cubic, tetragonal, orthorhombic, hexagonal, monoclinic, and trigonal.

[0338] [Composition of Oxide Semiconductor Layer] As described above, the semiconductor layer 230b preferably has a composition suitable for forming a CAAC structure. The semiconductor layer 230b can be formed by, for example, a sputtering method. The semiconductor layer 230b preferably contains, for example, zinc. By containing zinc, the semiconductor layer 230b becomes a metal oxide with high crystallinity. Furthermore, the semiconductor layer 230b preferably contains an element M in addition to zinc. By containing the element M in the semiconductor layer 230b, for example, it is possible to suppress the formation of oxygen vacancies in the metal oxide. Therefore, the reliability of a transistor using an oxide semiconductor layer can be improved. Specifically, the semiconductor layer 230b may be made of a metal oxide having an In:M:Zn = 1:1:1 atomic ratio or a composition thereof, an In:M:Zn = 1:1:1.2 atomic ratio or a composition thereof, an In:M:Zn = 1:1:0.5 atomic ratio or a composition thereof, an In:M:Zn = 1:1:2 atomic ratio or a composition thereof, an In:M:Zn = 4:2:3 atomic ratio or a composition thereof, an In:M:Zn = 1:3:2 atomic ratio or a composition thereof, or an In:M:Zn = 1:3:4 atomic ratio or a composition thereof. Note that a composition thereof may be in the range of -30% to 30% of the desired atomic ratio. Furthermore, it is preferable to use one or more of gallium, aluminum, and tin as the element M.

[0339] The semiconductor layer 230b can be configured without containing the element M. For example, an In—Zn oxide can be used. Specifically, the semiconductor layer 230b can have a composition of In:Zn=1:1 (atomic ratio) or a composition thereabout, an In:Zn=2:1 (atomic ratio) or a composition thereabout, or an In:Zn=4:1 (atomic ratio) or a composition thereabout. It can also be configured to contain a trace amount of the element M. For example, the semiconductor layer 230b can have a composition of In:Ga:Zn=4:0.1:1 (atomic ratio) or a composition thereabout, or an In:Ga:Zn=2:0.1:1 (atomic ratio) or a composition thereabout. Furthermore, the semiconductor layer 230b can have a composition of In:Sn:Zn=4:0.1:1 (atomic ratio) or a composition thereabout, or an In:Sn:Zn=2:0.1:1 (atomic ratio) or a composition thereabout.

[0340] The semiconductor layer 230a and the semiconductor layer 230c can be made of a metal oxide having a high proportion of In. The semiconductor layer 230a and the semiconductor layer 230c can be formed by, for example, an ALD method. In particular, it is preferable to use a metal oxide having a higher proportion of In than the element M. By using a metal oxide having a high proportion of In, when the oxide semiconductor layer is used in a transistor, the on-state current can be increased and the frequency characteristics can be improved.

[0341] The semiconductor layers 230a and 230c may be configured to not contain the element M. For example, an In—Zn oxide may be used. Specifically, the composition may be an In:Zn=1:1 atomic ratio or a composition thereabout, an In:Zn=2:1 atomic ratio or a composition thereabout, or an In:Zn=4:1 atomic ratio or a composition thereabout. The semiconductor layers 230a and 230c may be configured to contain a trace amount of the element M. Specifically, the composition may be an In:Ga:Zn=4:0.1:1 atomic ratio or a composition thereabout, an In:Ga:Zn=2:0.1:1 atomic ratio or a composition thereabout, an In:Sn:Zn=4:0.1:1 atomic ratio or a composition thereabout, or an In:Sn:Zn=2:0.1:1 atomic ratio or a composition thereabout.

[0342] Increasing the zinc content of the oxide semiconductor can improve the crystallinity of the oxide semiconductor. It is particularly preferable that the semiconductor layer 230a contains zinc. For example, when the semiconductor layer 230a is formed by an ALD method and the semiconductor layer 230b is formed by a sputtering method, zinc contained in the semiconductor layer 230a may diffuse into the semiconductor layer 230b. This diffusion may occur during sputtering or subsequent heat treatment. The diffusion of zinc from the semiconductor layer 230a to the semiconductor layer 230b improves the crystallinity. Alternatively, the diffusion of zinc from the semiconductor layer 230a to the semiconductor layer 230b promotes the lateral growth of crystal parts having c-axis orientation, thereby accelerating the formation of CAAC.

[0343] The semiconductor layer 230a and the semiconductor layer 230c can be made of a metal oxide having a higher proportion of In than the semiconductor layer 230b.

[0344] Alternatively, for example, a metal oxide having a higher Ga content than the semiconductor layer 230b can be used for the semiconductor layer 230a and the semiconductor layer 230c. For example, it is preferable to use a metal oxide having an In:Ga:Zn=1:1:1 atomic ratio or a composition thereabout, a metal oxide having an In:Ga:Zn=1:3:2 atomic ratio or a composition thereabout, or a metal oxide having an In:Ga:Zn=1:3:4 atomic ratio or a composition thereabout for the semiconductor layer 230a and the semiconductor layer 230c, respectively. Increasing the Ga content may result in the band gaps of the semiconductor layer 230a and the semiconductor layer 230c being larger than those of the semiconductor layer 230b. As a result, the semiconductor layer 230b is sandwiched between the semiconductor layer 230a and the semiconductor layer 230c, which have larger band gaps, and the semiconductor layer 230b functions primarily as a current path (channel). By sandwiching the semiconductor layer 230b between the semiconductor layers 230a and 230c, it is possible to reduce trap levels at the interface of the semiconductor layer 230b and in the vicinity thereof, thereby realizing a buried channel transistor in which the channel is kept away from the insulating layer interface, and thus increasing the field-effect mobility.

[0345] In the oxide semiconductor layer of one embodiment of the present invention, even when the semiconductor layers 230a and 230c are formed using compositions that make it difficult to form a CAAC structure when a single layer is formed, crystal growth occurs using the semiconductor layer 230b as a nucleus, so that the entire oxide semiconductor layer including the semiconductor layers 230a and 230c can have the CAAC structure. Alternatively, the CAAC structure can be formed in a region including at least a part of the semiconductor layer 230a and the semiconductor layer 230c and the semiconductor layer 230b.

[0346] In particular, even when the semiconductor layers 230 a and 230 c have a high In content, the semiconductor layers can have suitable crystallinity for use as semiconductor layers of a transistor. In the oxide semiconductor layer of one embodiment of the present invention, the increase in the In content can improve the on-state characteristics of the transistor, and the improvement in reliability can be achieved by using a CAAC structure with high crystallinity.

[0347] The semiconductor layer 230a and the semiconductor layer 230c may have different compositions.

[0348] The semiconductor layers 230a and 230c preferably use a metal oxide having the same composition as that of the semiconductor layer 230b.

[0349] By using an oxide semiconductor layer having a CAAC structure formed by using the above two types of film formation methods for a channel formation region of a transistor, a transistor with excellent characteristics (e.g., a transistor with high on-state current, a transistor with high field-effect mobility, a transistor with a small S value, a transistor with high frequency characteristics (also referred to as f characteristics), a highly reliable transistor, etc.) can be realized.

[0350] The composition of the metal oxide used in the semiconductor layer 230 can be analyzed using, for example, EDX, XPS, inductively coupled plasma-mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES). Alternatively, the analysis may be performed using a combination of these techniques. Note that for elements with low content, the actual content and the content obtained by analysis may differ due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.

[0351] [C-Axis Orientation Rate] The oxide semiconductor layer of one embodiment of the present invention has a CAAC structure. The crystallinity of the oxide semiconductor layer of one embodiment of the present invention can be evaluated using, for example, crystal orientation.

[0352] The crystal orientation can be obtained from a Fast Fourier Transform (FFT) pattern obtained by performing FFT processing on a TEM image. Specifically, the direction of the crystal axis can be obtained using the FFT pattern. The FFT pattern obtained by FFT processing reflects reciprocal lattice space information similar to that of an electron diffraction pattern.

[0353] By performing FFT processing on each region in a TEM image of an oxide semiconductor layer, the crystal orientation of each region can be obtained. For example, by obtaining the crystal orientation for each region within a certain area, a map showing the crystal orientation can be formed. Specifically, two spots with high intensity are observed in the FFT pattern of a region having a layered crystalline portion. The direction of the crystal axis of the region can be obtained from the angle of the line segment connecting the two spots.

[0354] The c-axis orientation rate can be calculated by calculating the proportion of c-axis oriented regions in a map showing crystal orientation. Here, the c-axis oriented regions are defined as regions whose orientation coincides with the c-axis and regions whose orientation differs from the c-axis by 20° or less.

[0355] In the oxide semiconductor layer of one embodiment of the present invention, the c-axis orientation ratio can be calculated, for example, by TEM observation of a cross section or a plan view of the oxide semiconductor layer. The region where FFT is performed (also referred to as an FFT window) can be a circle with a diameter of 1.0 nm, for example. Note that the region where FFT is performed is not limited to a circle.

[0356] In the oxide semiconductor layer of one embodiment of the present invention, the c-axis orientation rate is 60% or more, preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and still more preferably 95% or more.

[0357] The c-axis orientation rates of the region formed as semiconductor layer 230a, the region formed as semiconductor layer 230b, and the region formed as semiconductor layer 230c are defined as Rc1, Rc2, and Rc3, respectively. Rc2 and Rc3 are each 60% or more, preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more. Rc3 / Rc1 is preferably greater than 1. Rc2 / Rc1 is preferably greater than 1.

[0358] After the semiconductor layer 230 is fabricated, the boundaries between the semiconductor layers 230a, 230b, and 230c may not be clearly observed.

[0359] The semiconductor layer 230 of one embodiment of the present invention can be divided into three regions, a first region, a second region, and a third region, in this order from above the insulating layer 292. Each region is a layer-like region.

[0360] The first region, the second region, and the third region each have a CAAC structure. The c-axis orientation rate of the third region is preferably higher than that of the first region. The c-axis orientation rate of the second region is preferably higher than that of the first region. The c-axis orientation rates of the second region and the third region are each 80% or higher, more preferably 90% or higher, and even more preferably 95% or higher.

[0361] The first region is located at a distance of 0 nm to 3 nm from the top surface of the insulating layer 292 , and the third region is located at a distance of 0 nm to 3 nm from the top surface of the semiconductor layer 230 .

[0362] Alternatively, the layer thickness in each region may be approximately the same, for example.

[0363] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiment modes and examples.

[0364] In this embodiment, an indium oxide film that can be used for a semiconductor layer of the transistor M2 included in a semiconductor device of one embodiment of the present invention will be described. Note that in this specification, a metal oxide in which the ratio of the number of indium atoms to the total number of atoms of all metal elements contained therein is 97.5 atomic % or more is referred to as indium oxide.

[0365] In this specification and the like, indium oxide having at least a crystalline portion or a crystalline region in a film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystalline IO or crystalline IO include single-crystalline indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0366] Indium oxide is a semiconductor material having physical properties that are completely different from those of oxide semiconductors such as In—Ga—Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0367] The carrier concentration dependence of the Hall mobility of indium oxide, silicon, and IGZO will be explained. FIG. 17A shows the carrier concentration dependence of the Hall mobility of silicon (Si) and indium oxide (InO Ｘ ) and FIG. 17B is a schematic diagram showing the carrier concentration dependence of the hole mobility for IGZO.

[0368] First, IGZO tends to exhibit higher hole mobility as the carrier concentration increases, as shown by the arrows in Figure 17B. On the other hand, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases, as shown by the arrows in Figure 17A (see Non-Patent Document 1). This trend is similar to that of silicon; the lower the dopant (impurity) concentration in the material, the less impurity scattering there is and the higher the hole mobility. In other words, the higher the purity and intrinsic indium oxide, the higher the hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to those of silicon. Note that the characteristics of indium oxide shown in Figure 17A are assumed to be single crystal. Therefore, when indium oxide is non-single crystal (e.g., polycrystalline), the characteristics may differ from those shown in Figure 17A.

[0369] 17A, the range R1 of low carrier concentration has extremely high hole mobility, and therefore can be said to be a range of carrier concentration suitable for, for example, a channel formation region of a transistor. For example, in the case of indium oxide, the range R1 is a range where the carrier concentration value is 1×10 １５ cm −３ The range includes, for example, 1×10 １４ cm −３ That's it, 1 x 10 １８ cm −３ By sufficiently reducing the carrier concentration, the Hall mobility value can be increased to 270 cm ２ It is expected that the resistance can be increased to about / (V·s).

[0370] In addition, in indium oxide, the region where the carrier concentration is in the range R1 may contain an element that lowers the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Examples of elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0371] On the other hand, the range R2 with a high carrier concentration has a low electrical resistance, and can be said to be a range of carrier concentrations suitable for, for example, the source and drain regions of a transistor, a resistor, or a transparent conductive film. ２０ cm −３ The range includes, for example, 1×10 １９ cm −３ That's it, 1 x 10 ２２ cm −３ By increasing the carrier concentration sufficiently, the resistivity can be reduced to 1×10 −４ It is expected that the resistivity can be reduced to Ω·cm or less.

[0372] In the indium oxide, the region having a carrier concentration in the range R2 may contain an element that increases the carrier concentration. For example, it is preferable that the indium oxide contains an element that is common to the source electrode and the drain electrode of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use an element whose oxide has conductive or semiconductive properties.

[0373] In this way, indium oxide uses a region with a low carrier concentration as the channel formation region of a transistor, and a region with a high carrier concentration as the source and drain regions of the transistor. In other words, indium oxide can be said to be an oxide capable of valence electron control. Note that IGZO may experience strain in the source and drain regions due to stress from electrodes in contact with the IGZO, resulting in the formation of n-type regions. On the other hand, unlike IGZO, indium oxide is capable of valence electron control, and therefore does not require strain to be formed in the film as with IGZO. Less strain in the film is expected to improve reliability. For example, by separately creating a region with a carrier concentration in the range R1 shown in FIG. 17A and a region with a carrier concentration in the range R2 in the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Note that valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technical concept that would not normally be conceived.

[0374] By using the above technical concept, the transistor having indium oxide in this specification and the like has two or more, preferably three or more, more preferably four or more, and most preferably five of the following characteristics (1) to (5): (1) high on-state current (in other words, high mobility); (2) low off-state current; (3) normally-off operation; (4) high reliability; and (5) high cutoff frequency (fT). For example, the transistor having indium oxide in this specification and the like has high mobility, low off-state current, and is normally-off operation. The transistor has high mobility and is different from a normally-on transistor.

[0375] Next, an indium oxide film applied to a transistor will be described. The indium oxide film preferably has crystallinity (i.e., has crystal grains). Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains (also called microcrystalline films). In particular, the indium oxide film is preferably a polycrystalline film, and more preferably a single-crystal film. A single-crystal film does not have grain boundaries. Impurities (typically, insulating impurities, insulating oxides, etc.) that hinder carrier flow tend to segregate at grain boundaries. The use of a single-crystal film can suppress carrier scattering at grain boundaries, thereby realizing a transistor exhibiting high field-effect mobility. Furthermore, the use of a single-crystal film has the excellent effect of suppressing variations in transistor characteristics due to the grain boundaries.

[0376] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using a polycrystalline film, it is preferable to use a film with as large a crystal grain size as possible and with few crystal grain boundaries. Note that in a transistor using an indium oxide polycrystalline film, if there is no crystal grain boundary in the channel formation region or no crystal grain boundary is observed, the channel formation region is located within a single crystal region included in the polycrystalline film, and therefore the transistor can be considered to be using single-crystal indium oxide.

[0377] The crystallinity of indium oxide can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0378] In this specification and the like, a semiconductor layer in which no crystal grain boundary is observed in the channel formation region, a semiconductor layer in which the channel formation region is included in one crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions in the channel formation region can be called a single crystal film. Also, a semiconductor layer in which, in the channel formation region, within one crystal grain, the direction of another crystal axis continuously changes around a certain crystal axis or a certain crystal orientation as the axis of rotation can be called a single crystal film.

[0379] The channel formation region refers to a region of the semiconductor layer that overlaps (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, crystal grain boundaries, crystal axes, crystal orientation, etc. in the channel formation region can be confirmed by observing a cross section including the semiconductor layer, the source electrode, and the drain electrode.

[0380] The indium oxide film in the channel formation region preferably has a lower impurity concentration. Impurities in the indium oxide film in the channel formation region can be a scattering source of carriers, which can lead to a decrease in field-effect mobility. These impurities can also hinder the crystal growth of the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The indium oxide film preferably contains these impurities at concentrations of 0.1% or less, and more preferably 0.01% (100 ppm) or less. Carbon, hydrogen, and other elements may be contained in the film-forming gas or precursor during film formation, and may remain in the indium oxide film in greater amounts than the above-mentioned impurities.

[0381] The indium oxide film in the channel formation region may contain an element that can become the same trivalent cation as indium, as long as the crystal maintains a cubic crystal structure (bixbyite type). Examples of such an element include Group 13 elements of the periodic table, such as gallium and aluminum, and Group 3 elements of the periodic table. These elements exist mainly as trivalent cations in oxides, and therefore the carrier concentration of indium oxide can be maintained low.

[0382] By using such an indium oxide film in a transistor, the field effect mobility of the transistor can be increased to 50 cm ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ / (V·s) or more.

[0383] One of the features of an indium oxide film is that it has higher oxygen permeability (diffusibility) than an IGZO film. As shown in FIG. 17C, Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and becomes oxygen molecules (O ２ ) and is released as water molecules (H ２ O) may be released in the film. Ｏ In the case where an indium oxide film is present, oxygen atoms diffuse to compensate for the oxygen vacancies. Since oxygen diffuses easily in the indium oxide film, it can be said that oxygen vacancies are more easily compensated for in the indium oxide film than in the IGZO film.

[0384] As described above, an indium oxide film can more easily reduce oxygen vacancies in the film than an IGZO film. Therefore, by using such an indium oxide film in a transistor, a transistor with extremely high reliability can be realized.

[0385] 17C, the indium oxide film diffuses hydrogen. Hydrogen that diffuses into the indium oxide film from the outside passes through the indium oxide film and becomes hydrogen molecules (H ２ ) or reacts with oxygen contained in the membrane and is released as water molecules.

[0386] A transistor using an indium oxide film is an accumulation-type transistor that uses electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of the electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, for a transistor, the on-state current or field-effect mobility of the transistor can be increased.

[0387] Table 1 shows the results of single crystal indium oxide (here, In ２ O ３ ) and single-crystal silicon (Si). As shown in Table 1, indium oxide is characterized by a small effective mass of electrons and a large effective mass of holes. Indium oxide also has the characteristic that the effective mass of electrons is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in a transistor, a transistor with high field-effect mobility and high frequency characteristics (also called f characteristics) can be realized. Furthermore, since the effective mass of holes is large, a transistor with extremely small off-current can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width can be reduced to 1 fA (1×10) in an environment of 125° C. −１５ A) or less, or 1aA (1 x 10 −１８ A) or less, and under room temperature (25°C) conditions, −１８ A) or less, or 1zA (1 x 10 −２１ Furthermore, as shown in Table 1, indium oxide has a smaller effective mass of electrons and a larger effective mass of holes than silicon, and therefore may be able to realize a transistor with higher field-effect mobility and lower off-state current than a Si transistor.

[0388]

[0389] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. The seed layer is preferably made of a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with indium oxide. This can improve the crystallinity of the indium oxide film. Note that a substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0390] One method for evaluating the degree of lattice mismatch is to use the value of the lattice mismatch shown below. The lattice mismatch Δa [%] of the crystals of the formed film (here, the indium oxide film) with respect to the crystals of the seed layer is expressed as Δa=(L １ -L ２ ) / L ２ ) × 100, where L １ is the length or lattice constant of the unit lattice vector of the crystal of the formed film, and L ２ is the length of the unit cell vector or the lattice constant of the crystal of the seed layer.

[0391] The smaller the absolute value of the lattice mismatch Δa between the seed layer and the indium oxide film, the more preferable, and it is most preferably 0. For example, Δa can be set to −5% or more and 5% or less, preferably −4% or more and 4% or less, more preferably −3% or more and 3% or less, and even more preferably −2% or more and 2% or less.

[0392] Here, the indium oxide crystal has a cubic crystal structure (bixbyite type). For example, the crystal of yttria-stabilized zirconia (YSZ) can have a cubic crystal structure (fluorite type). The lattice mismatch of the indium oxide crystal with the cubic YSZ crystal is in the range of −2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on the YSZ substrate.

[0393] It should be noted that the crystal structure of the seed layer and the crystal structure of the indium oxide film may not necessarily have the same crystal system or crystal orientation. For example, a film having crystals of a hexagonal or trigonal structure may be used under an indium oxide film having crystals of a cubic structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to the crystal orientation necessary for epitaxial growth can be satisfied. Examples of hexagonal or trigonal crystals include wurtzite structure, YbFe ２ O ４ Type structure, Yb ２ Fe ３ O ７ YbFeFe alloys have the following structures: ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a ZnO-type structure is IGZO.

[0394] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0395] In this embodiment, electronic components, electronic devices, mainframes, space equipment, and data centers (also referred to as data centers (DCs)) that can use the semiconductor device described in the above embodiment will be described. The electronic components, electronic devices, mainframes, space equipment, and data centers that use the semiconductor device of one embodiment of the present invention are effective in achieving high performance, such as low power consumption.

[0396] [Electronic Component] FIG. 18A shows a perspective view of a substrate (mounting substrate 704) on which electronic component 700 is mounted. Electronic component 700 shown in FIG. 18A has semiconductor device 710 inside mold 711. FIG. 18A omits some parts to show the interior of electronic component 700. Electronic component 700 has lands 712 on the outside of mold 711. Lands 712 are electrically connected to electrode pads 713, and electrode pads 713 are electrically connected to semiconductor device 710 via wires 714. Electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on printed circuit board 702 to complete mounting substrate 704.

[0397] The semiconductor device 710 also includes a drive circuit layer 715 and a memory layer 716. The memory layer 716 has a configuration in which multiple memory cell arrays are stacked. The stacked configuration of the drive circuit layer 715 and the memory layer 716 can be a monolithic stacked configuration. In a monolithic stacked configuration, the layers can be connected without using through-electrode technology such as a TSV (Through Silicon Via) or a bonding technology such as Cu-Cu direct bonding. By configuring the drive circuit layer 715 and the memory layer 716 as a monolithic stacked configuration, for example, a so-called on-chip memory configuration can be achieved in which the memory is formed directly on the processor. The on-chip memory configuration enables the operation of the interface between the processor and the memory to be faster.

[0398] Furthermore, by configuring an on-chip memory, it is possible to reduce the size of connection wiring, etc., compared to technologies that use through electrodes such as TSVs, and therefore it is possible to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).

[0399] Furthermore, it is preferable that the memory cell arrays included in the memory layer 716 are formed using OS transistors and the memory cell arrays are monolithically stacked. By forming the memory cell arrays in a monolithic stacked structure, it is possible to improve either or both of the memory bandwidth and the memory access latency. Note that the bandwidth is the amount of data transferred per unit time, and the access latency is the time from access to the start of data exchange. Note that when Si transistors are used for the memory layer 716, it is more difficult to form a monolithic stacked structure than when OS transistors are used. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stacked structure.

[0400] The semiconductor device 710 may also be referred to as a die. In this specification, a die refers to a chip piece obtained by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and dicing it into cubes during the semiconductor chip manufacturing process. Examples of semiconductor materials that can be used for the die include silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0401] 18B shows a perspective view of an electronic component 730. The electronic component 730 is an example of a SiP (System in Package) or an MCM (Multi-Chip Module). The electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 710 provided on the interposer 731.

[0402] The electronic component 730 shows an example in which the semiconductor device 710 is used as a high bandwidth memory (HBM). The semiconductor device 735 can be used in an integrated circuit such as a central processing unit (CPU), a graphics processing unit (GPU), or a field programmable gate array (FPGA).

[0403] For example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used as the package substrate 732. For example, a silicon interposer or a resin interposer can be used as the interposer 731.

[0404] The interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to electrically connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In addition, through electrodes may be provided in the interposer 731, and the integrated circuits and the package substrate 732 may be electrically connected using the through electrodes. In addition, with a silicon interposer, a TSV may also be used as the through electrode.

[0405] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0406] Furthermore, in SiP and MCM using silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, since the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on the interposer.

[0407] On the other hand, when a silicon interposer and TSVs are used to electrically connect multiple integrated circuits with different terminal pitches, a space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 730, the width of the terminal pitch becomes an issue, and it may be difficult to provide the many wirings required to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferable. A composite structure may be formed by combining a memory cell array stacked using TSVs and a monolithically stacked memory cell array.

[0408] A heat sink (heat dissipation plate) may be provided overlapping the electronic component 730. When a heat sink is provided, it is preferable to align the height of an integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the height of the semiconductor device 710 and the height of the semiconductor device 735.

[0409] Electrodes 733 may be provided on the bottom of package substrate 732 in order to mount electronic component 730 on another substrate. FIG. 18B shows an example in which electrodes 733 are formed with solder balls. By providing solder balls in a matrix on the bottom of package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, electrodes 733 may be formed with conductive pins. By providing conductive pins in a matrix on the bottom of package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0410] The electronic component 730 can be mounted on other substrates using various mounting methods, including, but not limited to, BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), and a quad flat non-leaded package (QFN).

[0411] [Electronic Device] Next, a perspective view of an electronic device 6500 is shown in FIG. 19A . The electronic device 6500 shown in FIG. 19A is a portable information terminal that can be used as a smartphone. The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and a control device 6509. Note that the control device 6509 includes, for example, one or more selected from a CPU, a GPU, and a memory device. The semiconductor device of one embodiment of the present invention can be applied to the display portion 6502, the control device 6509, and the like.

[0412] 19B is an information terminal that can be used as a laptop personal computer. The electronic device 6600 includes a housing 6611, a keyboard 6612, a pointing device 6613, an external connection port 6614, a display portion 6615, and a control device 6616. Note that the control device 6616 includes, for example, one or more selected from a CPU, a GPU, and a memory device. The semiconductor device of one embodiment of the present invention can be applied to the display portion 6615, the control device 6616, and the like. Note that the use of the semiconductor device of one embodiment of the present invention in the control device 6509 and the control device 6616 is preferable because power consumption can be reduced.

[0413] 19C shows a perspective view of a mainframe computer 5600. The mainframe computer 5600 shown in Fig. 19C has a rack 5610 housing a plurality of rack-mounted computers 5620. The mainframe computer 5600 may also be called a supercomputer.

[0414] The computer 5620 can have the configuration shown in the perspective view in Fig. 19D, for example. In Fig. 19D, the computer 5620 has a motherboard 5630, which has a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0415] A PC card 5621 shown in Figure 19E is an example of a processing board equipped with a CPU, a GPU, a storage device, etc. The PC card 5621 includes a board 5622. The board 5622 also includes a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629. Note that Figure 19E illustrates semiconductor devices other than the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628, but for these semiconductor devices, the following description of the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 may be referred to.

[0416] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0417] The connection terminals 5623, 5624, and 5625 can be, for example, interfaces for supplying power to the PC card 5621, inputting signals, and the like. They can also be, for example, interfaces for outputting signals calculated by the PC card 5621. Examples of the standards for the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). When a video signal is output from the connection terminals 5623, 5624, and 5625, the respective standards include HDMI (registered trademark).

[0418] The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.

[0419] The semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 can be electrically connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5627 include an FPGA, a GPU, and a CPU. For example, the electronic component 730 can be used for the semiconductor device 5627.

[0420] The semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 and the board 5622 can be electrically connected by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5628 include a memory device. For example, the electronic component 700 can be used as the semiconductor device 5628.

[0421] The mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations necessary for learning and inference in artificial intelligence, for example.

[0422] [Space Equipment] The semiconductor device of one embodiment of the present invention can be suitably used in space equipment (for example, equipment having a function of processing and storing information).

[0423] The semiconductor device of one embodiment of the present invention can include an OS transistor. The OS transistor exhibits small changes in electrical characteristics due to radiation exposure. That is, the OS transistor has high radiation resistance and can be suitably used in an environment where radiation may be incident. For example, the OS transistor can be suitably used in outer space.

[0424] Fig. 20 shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. In Fig. 20, a planet 6804 is shown in outer space. Note that outer space refers to an altitude of 100 km or higher, for example, but the outer space described in this specification may also include the thermosphere, mesosphere, and stratosphere.

[0425] 20 , a battery management system (also referred to as a BMS) or a battery control circuit may be provided for the secondary battery 6805. The use of an OS transistor in the battery management system or the battery control circuit is preferable because it consumes low power and has high reliability even in space.

[0426] Furthermore, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0427] When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where sunlight is not irradiated onto the solar panel or where the amount of sunlight irradiating the solar panel is small, the generated power is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is preferable to provide a secondary battery 6805 on the satellite 6800. Note that the solar panel may be called a solar cell module.

[0428] The satellite 6800 can generate a signal. The signal is transmitted via an antenna 6803, and can be received by, for example, a receiver installed on the ground or another satellite. By receiving the signal transmitted by the satellite 6800, the position of the receiver that received the signal can be determined. As described above, the satellite 6800 can constitute a satellite positioning system.

[0429] The control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device. Note that the semiconductor device of one embodiment of the present invention is preferably used for the control device 6807. An OS transistor has smaller fluctuations in electrical characteristics due to radiation exposure than a Si transistor. That is, an OS transistor has high reliability even in an environment where radiation may be incident, and can be preferably used.

[0430] The artificial satellite 6800 can also be configured to include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected from an object on the ground. Alternatively, by including a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 6800 can function as, for example, an earth observation satellite.

[0431] Although an artificial satellite is described as an example of space equipment in this embodiment, the present invention is not limited thereto. For example, the semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.

[0432] As described above, OS transistors have excellent advantages over Si transistors, such as the ability to achieve a wide memory bandwidth and high radiation resistance.

[0433] [Data Center] The semiconductor device of one embodiment of the present invention can be suitably used in a storage system applied to, for example, a data center. The data center is required to perform long-term management of data, such as ensuring data immutability. Managing long-term data requires a large-scale building, such as installing storage and servers for storing a huge amount of data, ensuring a stable power supply for maintaining the data, or ensuring cooling equipment required for maintaining the data.

[0434] By using a storage device according to one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and to miniaturize the storage device that stores the data. This makes it possible to miniaturize the storage system, the power supply for storing data, and the cooling equipment. This allows for space saving in the data center.

[0435] Furthermore, the storage device of one embodiment of the present invention consumes less power, which reduces heat generation from the circuit. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the storage device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0436] Fig. 21 shows a storage system applicable to a data center. The storage system 7000 shown in Fig. 21 has a plurality of servers 7001sb as hosts 7001 (illustrated as Host computers). It also has a plurality of storage devices 7003md as storage 7003 (illustrated as Storage). The host 7001 and storage 7003 are shown connected via a storage area network 7004 (illustrated as SAN: Storage Area Network) and a storage control circuit 7002 (illustrated as Storage Controller).

[0437] The host 7001 corresponds to a computer that accesses data stored in the storage 7003. The hosts 7001 may be connected to each other via a network.

[0438] Although the storage 7003 uses flash memory to reduce the data access speed, i.e., the time required to store and output data, this time is significantly longer than the time required for DRAM (Dynamic Random Access Memory), which can be used as cache memory within the storage. In order to solve the problem of the long access speed of the storage 7003, a storage system typically provides cache memory within the storage to reduce the time required to store and output data.

[0439] The above-mentioned cache memory is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003, and then output to the host 7001 or the storage 7003.

[0440] By using OS transistors as transistors for storing data in the cache memory and holding a potential corresponding to the data, the frequency of refresh operations can be reduced, and power consumption can be reduced.

[0441] Note that by applying the semiconductor device of one embodiment of the present invention to any one or more selected from electronic components, electronic devices, mainframe computers, space equipment, and data centers, the effect of reducing power consumption can be achieved. Therefore, while energy demand is expected to increase with the improvement in performance or high integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention can reduce carbon dioxide (CO ２ Furthermore, the semiconductor device of one embodiment of the present invention is effective as a countermeasure against global warming because it consumes low power.

[0442] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. For example, the configuration, structure, method, and the like described in this embodiment mode can be appropriately combined with the configuration, structure, method, and the like described in other embodiment modes.

[0443] 10: element layer, 20: element layer, 30: element layer, 40: element layer, 50: barrier insulating layer, 100A: semiconductor device, 100B: semiconductor device, 110: first circuit, 120: second circuit, 130: third circuit, 140: fourth circuit, 200: transistor, 200A: transistor, 200B: transistor, 200C: transistor, 200D: transistor, 200E: transistor, 200F: transistor, 200G: transistor, 200H: transistor, 200I: transistor , 300: memory cell, 301: transistor, 302: transistor, 303: transistor, 305: capacitor, 310: register, 311: read circuit, 320: scan flip-flop, 321: selector, 322: flip-flop, 330: data holding circuit, 331: memory circuit, 332: transistor, 333: transistor, 334: transistor, 335: capacitor, 410: storage device, 501: transistor, 502: transistor, 504: transistor

Claims

1. A semiconductor device comprising: a first element layer; a second element layer on the first element layer; a first insulating layer on the second element layer that has a barrier property against hydrogen; and a third element layer on the second element layer, wherein the first element layer comprises a first transistor having silicon in a channel formation region; the second element layer comprises a second transistor having a first oxide semiconductor in a channel formation region; the third element layer comprises a third transistor having a second oxide semiconductor in a channel formation region; the first oxide semiconductor comprises indium oxide; and the second oxide semiconductor comprises indium, gallium, and zinc.

2. A semiconductor device according to claim 1, wherein the first insulating layer is an insulating layer having a higher barrier property against hydrogen than the insulating layers provided on the first element layer and the second element layer.

3. A semiconductor device comprising: a first element layer; a second element layer on the first element layer; and a third element layer on the second element layer, wherein the first element layer comprises a first semiconductor having a channel formation region of a first transistor; the second element layer comprises a first oxide semiconductor having a channel formation region of a second transistor and a first insulating layer having a region on the first oxide semiconductor and having a barrier property against hydrogen; the third element layer comprises a second oxide semiconductor having a channel formation region of a third transistor; the first semiconductor comprises silicon; the first oxide semiconductor comprises indium oxide; and the second oxide semiconductor comprises indium, gallium, and zinc.

4. A semiconductor device according to claim 3, wherein the first insulating layer is an insulating layer having a higher barrier property against hydrogen than an insulating layer provided between the first semiconductor and the first oxide semiconductor.

5. A semiconductor device according to any one of claims 1 to 4, wherein the first insulating layer is an insulating layer having a lower hydrogen permeability than silicon oxide.

6. A semiconductor device according to claim 5, wherein the first insulating layer comprises aluminum oxide, hafnium oxide or silicon nitride.

7. A semiconductor device according to any one of claims 1 to 4, wherein the thickness of the gate insulating layer of the second transistor is greater than the thickness of the gate insulating layer of the first transistor, and the thickness of the gate insulating layer of the third transistor is greater than the thickness of the gate insulating layer of the second transistor.

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