Electronic device and method for partially changing display on display panel

Abstract

An electronic device is provided. The electronic device may comprise: at least one processor including a processing circuit; a display driving circuit including a graphic random access memory (GRAM); and a display panel.

Description

Electronic device and method for partially changing the display on a display panel

[0001] The descriptions below relate to electronic devices and methods for partially changing displays on a display panel.

[0002] An electronic device may include a display. The display may be used to display an image. The display may include a display panel and a display driving circuit. The display driving circuit may be configured to display the image acquired from a processor of the electronic device on the display panel. For example, the display driving circuit may be configured to control a source driver (or data driver) of the electronic device and a gate driver (or scan driver) of the electronic device to display the image on the display panel.

[0003] The above information may be provided as background art to aid in understanding the present disclosure. No claim or determination is made as to whether any of the above is applicable as prior art related to the present disclosure.

[0004] An electronic device is provided. The electronic device may include at least one processor including a processing circuit. The electronic device may include a display panel. The electronic device may include a display driving circuit including a memory. The display driving circuit may be configured to receive first image data from the at least one processor within a first portion of a time interval corresponding to one frame, and display a first image through a first portion of the display panel based on the first image data received from the at least one processor. The display driving circuit may be configured to obtain, within a second portion of the time interval, second image data stored in the memory before the time interval from the memory, and display a second image through a second portion of the display panel based on the second image data obtained from the memory.

[0005] A method is provided. The method can be executed in an electronic device including at least one processor, a display driving circuit including a memory, and a display panel. The method can include an operation of receiving first image data from the at least one processor within a first portion of a time interval corresponding to one frame, and displaying a first image through a first portion of the display panel based on the first image data received from the at least one processor. The method can include an operation of acquiring, within a second portion of the time interval, second image data stored in the memory before the time interval from the memory, and displaying a second image through a second portion of the display panel based on the second image data acquired from the memory.

[0006] An electronic device is provided. The electronic device may include at least one processor including a processing circuit. The electronic device may include a display panel. The electronic device may include a display driving circuit including a memory. The display driving circuit may be configured to receive first image data from the at least one processor within a first portion of a time interval corresponding to one frame, store the first image data received from the at least one processor in a first area of ​​the memory, and display a first image through a first portion of the display panel based on the first image data received from the at least one processor. The display driving circuit may be configured to receive second image data from the at least one processor within a second portion of the time interval, refrain from storing the second image data received from the at least one processor in the memory, and display a second image through a second portion of the display panel based on the second image data.

[0007] A method is provided. The method can be executed in an electronic device including at least one processor, a display driving circuit including a memory, and a display panel. The method can include, within a first portion of a time interval corresponding to one frame, receiving first image data from the at least one processor, storing the first image data received from the at least one processor in a first area of ​​the memory, and displaying a first image through a first portion of the display panel based on the first image data received from the at least one processor. The method can include, within a second portion of the time interval, receiving second image data from the at least one processor, refraining from storing the second image data received from the at least one processor in the memory, and displaying a second image through a second portion of the display panel based on the second image data.

[0008] An electronic device is provided. The electronic device may include at least one processor including a processing circuit. The electronic device may include a display driving circuit including a graphic random access memory (GRAM). The electronic device may include a display panel. The display driving circuit may be configured to receive, from the at least one processor, a first image to be displayed through a first portion of the display panel via a vertical synchronization signal. The display driving circuit may be configured to scan the first image received from the at least one processor to display the first image through the first portion of the display panel within a first portion of a time interval corresponding to the vertical synchronization signal, and to store the first image received from the at least one processor in a first area of ​​the GRAM. The display driving circuit may be configured to, within a second portion of the time interval, obtain a second image stored in a second area of ​​the GRAM before receiving the first image, from the GRAM, and scan the second image obtained from the GRAM to display the second image through the second portion of the display panel.

[0009] A method is provided. The method can be executed in an electronic device including at least one processor, a display driving circuit including a graphic random access memory (GRAM), and a display panel. The method can include an operation in which the display driving circuit receives, from the at least one processor, a first image to be displayed through a first portion of the display panel via a vertical synchronization signal. The method can include an operation in which the display driving circuit scans, within a first portion of a time interval corresponding to the vertical synchronization signal, the first image received from the at least one processor to display the first image through the first portion of the display panel, and stores, in a first area of ​​the GRAM, the first image received from the at least one processor. The method may include, within a second portion of the time interval, an operation in which the display driving circuit acquires, from the GRAM, a second image stored in a second area of ​​the GRAM before receiving the first image, and the display driving circuit scans, to display the second image acquired from the GRAM, the second image through the second portion of the display panel.

[0010] An electronic device is provided. The electronic device may include at least one processor including a processing circuit. The electronic device may include a display driving circuit including a graphic random access memory (GRAM). The electronic device may include a display panel. The display driving circuit may be configured to receive, from the at least one processor, a first image to be displayed through a first portion of the display panel via a vertical synchronization signal. The display driving circuit may be configured to scan the first image received from the at least one processor to display the first image through the first portion of the display panel within a first portion of a time interval corresponding to the vertical synchronization signal, and to refrain from storing the first image received from the at least one processor in a first area of ​​the GRAM. The display driving circuit may be configured to, within a second portion of the time interval, obtain a second image stored in a second area of ​​the GRAM before receiving the first image, from the GRAM, and scan the second image obtained from the GRAM to display the second image through a second portion of the display panel.

[0011] A method is provided. The method can be executed in an electronic device including at least one processor, a display driving circuit including a graphic random access memory (GRAM), and a display panel. The method can include an operation in which the display driving circuit receives, from the at least one processor, a first image to be displayed through a first portion of the display panel via a vertical synchronization signal. The method can include an operation in which the display driving circuit scans, within a first portion of a time interval corresponding to the vertical synchronization signal, the first image received from the at least one processor to display the first image through the first portion of the display panel, and the display driving circuit refrains from storing, in a first area of ​​the GRAM, the first image received from the at least one processor. The method may include, within a second portion of the time interval, obtaining a second image stored in a second area of ​​the GRAM from the GRAM before receiving the first image, and scanning the second image obtained from the GRAM to display the second image through a second portion of the display panel.

[0012] An electronic device is provided. The electronic device may include at least one processor including a processing circuit. The electronic device may include a display driving circuit including a graphic random access memory (GRAM). The electronic device may include a display panel. The display driving circuit may be configured to receive, from the at least one processor, a first image to be displayed through a first portion of the display panel and a second image to be displayed through a second portion of the display panel via a vertical synchronization signal. The display driving circuit may be configured to scan the first image received from the at least one processor to display the first image through the first portion of the display panel within a first portion of a time interval corresponding to the vertical synchronization signal, and to store the first image received from the at least one processor in a first area of ​​the GRAM. The display driving circuit may be configured to scan the second image received from the at least one processor to display the second image through the second portion of the display panel within the second portion of the time interval, and to refrain from storing the second image received from the at least one processor in the second area of ​​the GRAM while scanning the second image.

[0013] A method is provided. The method can be executed in an electronic device including at least one processor, a display driving circuit including a graphic random access memory (GRAM), and a display panel. The method can include an operation in which the display driving circuit receives, from the at least one processor, a first image to be displayed through a first portion of the display panel and a second image to be displayed through a second portion of the display panel via a vertical synchronization signal. The method can include an operation in which the display driving circuit scans, within a first portion of a time interval corresponding to the vertical synchronization signal, the first image received from the at least one processor to display the first image through the first portion of the display panel, and stores, by the display driving circuit, the first image received from the at least one processor in a first area of ​​the GRAM. The method may include, within a second portion of the time interval, an operation in which the display driving circuit scans the second image received from the at least one processor to display the second image through the second portion of the display panel, and refraining from storing the second image received from the at least one processor in a second area of ​​the GRAM while scanning the second image.

[0014] Figure 1 is a simplified block diagram of an exemplary electronic device.

[0015] Figure 2 illustrates a method of scanning performed by a display driving circuit to display an image on a display panel.

[0016] FIG. 3 illustrates the operation of a display driving circuit performed based on reception of an image to be displayed on a portion of a display panel.

[0017] Figure 4 illustrates an example of multi-frequency driving.

[0018] FIG. 5 illustrates the operation of a display driving circuit performed based on reception of an image to be displayed on a portion of a display panel within a display supporting multi-frequency driving.

[0019] Figures 6 to 8 illustrate a method for identifying location information.

[0020] FIG. 9 is a block diagram of an electronic device within a network environment according to various embodiments.

[0021] FIG. 10 is a block diagram of a display module according to various embodiments.

[0022] Figure 1 is a simplified block diagram of an exemplary electronic device.

[0023] Referring to FIG. 1, an electronic device (100) may include at least one processor (110), memory (115), and display (120).

[0024] At least one processor (110) may be a hardware component of the electronic device (100) that is available to execute (or perform) at least a portion of the operations exemplified in the description below. The at least one processor (110) may include processing circuitry or processing integrated circuitry. For example, the at least one processor (110) may include a central processing unit (CPU) (e.g., including processing circuitry), a graphics processing unit (GPU) (e.g., including processing circuitry), and / or a display processing unit (DPU) (e.g., including processing circuitry). The at least one processor (110) may be implemented as a system on chip (SoC). The at least one processor (110) may comprise a processor assembly. The at least one processor (110) may include at least a portion of the processor (920) of FIG. 9 or may correspond to at least a portion of the processor (920) of FIG. 9.

[0025] The memory (115) may include one or more storage media (or one or more storage devices). The memory (115) may comprise a memory assembly comprising one or more storage media. The one or more storage media may include a hard drive, flash memory, permanent memory such as read-only memory (ROM), semi-permanent memory such as random access memory (RAM), any other suitable type of storage (or storage assembly), or any combination thereof. The memory (115) may include a cache memory, which is one or more different types of memory used to temporarily store data for a function or feature of the electronic device (100). As a non-limiting example, the cache memory may be included within at least one processor (110).

[0026] The memory (115) may be fixedly embedded within the electronic device (100) or incorporated into one or more suitably types of components (e.g., a subscriber identity module (SIM) card and / or a secure digital (SD) card) that can be repeatedly inserted into and removed from the electronic device (100).

[0027] The memory (115) may store one or more software applications, such as an operating system (or system software application), a firmware software application, a driver software application, a plug-in (e.g., add-in, add-on, and / or applet) software application, and / or any other suitable software applications. The one or more software applications may include instructions executable by at least one processor (110). The memory (115) may store instructions callable by an application programming interface (API). The memory (115) may store instructions within a library.

[0028] The memory (115) may include at least a portion of the memory (930) of FIG. 9 or correspond to at least a portion of the memory (930) of FIG. 9.

[0029] At least one processor (110) and memory (115) may be described as a host processor.

[0030] The display (120) may be a hardware component of the electronic device (100) that is available to perform at least some of the operations exemplified in the description below. The display (120) may include at least a portion of the display module (960) of FIGS. 9 and 10 or may correspond to at least a portion of the display module (960) of FIGS. 9 and 10. The display (120) may include a display driver circuit (121) (e.g., including at least a portion of the display driver IC (1030) of FIG. 10 or corresponding to at least a portion of the display driver IC (1030) of FIG. 10) and a display panel (122) (e.g., including at least a portion of the display (1010) of FIG. 10 or corresponding to at least a portion of the display (1010) of FIG. 10).

[0031] The display driving circuit (121) may be a hardware component of an electronic device (100) that can be used to display a screen (or one or more images) through a display panel (122) (or through a display area of ​​the display panel (122)). The display driving circuit (121) may be configured to receive data (e.g., frame data) from at least one processor (110) and control the display panel (122) to display the screen (or one or more images) using the data. The display driving circuit (121) may be described as a display peripheral (121).

[0032] The display panel (122) may be a hardware component of an electronic device (100) that is available to display a screen (or one or more images). For example, the display panel (122) may be configured to display the screen (or one or more images) under the control of a display driving circuit (121).

[0033] The electronic device (100) may include one or more interfaces (or one or more paths) that electrically and / or physically connect the display driving circuit (121) to at least one processor (110).

[0034] The one or more interfaces (or the one or more paths) may include an interface (130) (or path (130)). The interface (130) may be a hardware component of the electronic device (100) that is available for data (e.g., frame data) transmitted from at least one processor (110) to the display driver circuit (121). The interface (130) may include a mobile industry processor interface (MIPI). The interface (130) may be operated (or driven) for (or according to) a video hybrid mode (VHM) of the MIPI display serial interface (DSI). The display driver circuit (121) connected to the interface (130) used for the video hybrid mode may include a memory (124), which may be described as a graphic random access memory (GRAM) (124), a frame memory (124), or a frame buffer (124). The memory (124) can (at least temporarily) store an image from at least one processor (110) according to a command from at least one processor (110).

[0035] At least one processor (110) may include a transmission interface (111) (e.g., including a transmission circuit). The transmission interface (111) may be connected to an interface (130). The at least one processor (110) may control (or cause) the transmission interface (111) to transmit an image to the display driving circuit (121) via the interface (130). The transmission interface (111) may be included within the DPU.

[0036] The display driving circuit (121) may include a receiving interface (123) (e.g., including a receiving circuit). The receiving interface (123) may be connected to an interface (130). The display driving circuit (121) may control (or cause) the receiving interface (124) to receive an image from at least one processor (110) via the interface (130).

[0037] The display driving circuit (121) may include a path (126), a path (127), and a path (128).

[0038] Path (126) may be described as a path to the display panel (122) that bypasses the memory (124). Path (126) may be described as a path by which an image from at least one processor (110) received using the receiving interface (123) is provided to the display panel (122). Path (126) may be described as a path of an image that bypasses the memory (124). Path (126) may be available for scanning an image received from at least one processor (110) by bypassing the memory (124). Path (126) used for the video hybrid mode may be the same as or similar to a path within the display used for the video mode of MIPI DSI.

[0039] Path (126) may be activated based on receiving an image from at least one processor (110). Activating path (126) may be described as scanning an image received from at least one processor (110) to display the image received from at least one processor (110) through the display panel (122). Activating path (126) may be described as electrically connecting the display panel (122) to the receiving interface (123). Path (126) may be activated by controlling switch (133) to electrically connect the display panel (122) to the receiving interface (123). The control of switch (133) may be performed by display driving circuit (121) based on receiving an image from at least one processor (110).

[0040] Path (126) may be deactivated based on not receiving an image from at least one processor (110) (or on the condition that an image is not received from at least one processor (110). Deactivating path (126) may be explained as not performing scanning of an image received from at least one processor (110). Deactivating path (126) may be explained as not triggering a change in the display on the display panel (122) by at least one processor (110). Deactivating path (126) may be explained as triggering a change in the display on the display panel (122) by the display driver circuit (121). Deactivating path (126) may be explained as electrically disconnecting the display panel (122) from the receiving interface (123). The path (126) can be deactivated by controlling the switch (133) to electrically disconnect the display panel (122) from the receiving interface (123). The control of the switch (133) can be performed by the display driving circuit (121) based on not receiving an image from at least one processor (110).

[0041] Path (127) may be described as a path to memory (124) (or to an input terminal of memory (124)). Path (127) may be described as a path along which an image from at least one processor (110) received using the receiving interface (123) is stored (or written) in memory (124). Path (127) may be available for storing an image received from at least one processor (110) in memory (124) while scanning the image received from at least one processor (110). Path (127) may be available for storing an image received from at least one processor (110) in memory (124) while scanning the image received from at least one processor (110) using path (126) for displaying the image through the display panel (122).

[0042] Path (127) may be activated based on receiving a first command from at least one processor (110) to store an image received from at least one processor (110) in memory (124). The first command may be described as a still indication. The still indication may include a sticky flag indication (or sticky flag) and / or an on-the-fly indication (or on-the-fly). Activating path (127) may be described as storing an image received from at least one processor (110) in memory (124). Activating path (127) may be described as electrically connecting memory (124) to receiving interface (123). Path (127) may be activated by controlling switch (131) to electrically connect memory (124) to receiving interface (123). The above control of the switch (131) can be performed by the display driving circuit (121) based on the first command.

[0043] Path (127) may be deactivated based on receiving a second command from at least one processor (110) to refrain from storing an image received from at least one processor (110) in memory (124). The second command may indicate bypassing storing an image received from at least one processor (110) in memory (124). Deactivating path (127) may be described as not storing an image received from at least one processor (110) in memory (124). Deactivating path (127) may be described as electrically disconnecting memory (12) from receiving interface (123). Path (127) may be deactivated by controlling switch (131) to electrically disconnect memory (124) from receiving interface (123). The above control of the switch (131) can be performed by the display driving circuit (121) based on the second command.

[0044] Path (128) may be described as a path from memory (124) (or from an output terminal of memory (124)). Path (128) may be described as a path from the output terminal of memory (124) to the display panel (122). Path (128) may be described as a path available for scanning an image stored in memory (124). Path (128) may be described as a path available for reading an image from memory (124). Path (128) may be available for scanning an image without receiving an image from at least one processor (110).

[0045] Path (128) may be activated based on a command from at least one processor (110) and / or a decision of the display driving circuit (121). Activating path (128) may be described as scanning an image stored in memory (124). Activating path (128) may be described as electrically connecting the display panel (122) to the memory (124). Path (128) may be activated by controlling switch (132) to electrically connect the display panel (122) to the memory (124). The control of switch (132) may be performed by the display driving circuit (121).

[0046] Path (128) may be deactivated based on a command from at least one processor (110) and / or a decision of the display driver circuit (121). Deactivating path (128) may be described as bypassing (or refraining from) scanning an image stored in memory (124). Deactivating path (128) may be described as electrically disconnecting the display panel (122) from the memory (124). Path (128) may be deactivated by controlling switch (132) to electrically disconnect the display panel (122) from the memory (124). The control of switch (132) may be performed by the display driver circuit (121).

[0047] The manner (or method) of scanning performed by the display driving circuit (121) to display an image on the display panel (122) may include a first manner, a second manner, and a third manner. The first manner may be related to a path (126), the second manner may be related to a path (126) and a path (127), and the third manner may be related to a path (128). The first manner, the second manner, and the third manner are described with reference to FIG. 2.

[0048] Figure 2 illustrates a method of scanning performed by a display driving circuit to display an image on a display panel.

[0049] Referring to FIG. 2, the display driving circuit (121) may perform a scan to display an image through the display panel (122) according to (or for) the video hybrid mode, in a first manner (201). The scan performed in the first manner (201) may include scanning the image received from at least one processor (110) while not storing the image received from at least one processor (110) in the memory (124). The image received from at least one processor (110) may be described as frame data or image data. The scan performed in the first manner (201) may include providing the image received from at least one processor (110) to the display panel (122) via a path (126). Providing the image to the display panel (122) may include providing a data voltage corresponding to the image to the display panel (122). The scan performed in the first manner (201) may include refraining from storing the image received from at least one processor (110) in the memory (124) via the path (127). The scan performed in the first manner (201) may be related to the second command. The scan within the first manner (201) may be performed while not storing the image received from at least one processor (110) in the memory (124) via the path (127). The scan within the first manner (201) may be described as a scan performed while activating the path (126) and deactivating the paths (127) and (128).

[0050] The display driving circuit (121) may perform a scan to display an image through the display panel (122) according to (or for) the video hybrid mode in a second manner (202). The scan performed in the second manner (202) may include scanning the image received from the at least one processor (110) while storing the image received from the at least one processor (110) in the memory (124). The scan performed in the second manner (202) may include providing the image received from the at least one processor (110) to the display panel (122) via a path (126) and providing the image received from the at least one processor (110) to the memory (124) via a path (127). The scan within the second method (202) may further include providing, relative to the scan within the first method (201), an image received from at least one processor (110) to the memory (124) via the path (127). The scan performed within the second method (202) may be related to the first command. The scan within the second method (202) may be performed while storing, via the path (127), the image received from at least one processor (110), in the memory (124). The scan within the second method (202) may be described as a scan performed while activating the paths (126) and (127), and deactivating the path (128).

[0051] The display driving circuit (121) may perform a scan to display an image through the display panel (122) according to (or for) the video hybrid mode in a third manner (203). The scan performed in the third manner (203) may include scanning an image stored in the memory (124) while not receiving an image from at least one processor (121). The scan performed in the third manner (203) may include providing an image from the memory (124) to the display panel (122) via the path (128) while not receiving an image from at least one processor (110). The scan within the third manner (203) may be described as a scan performed while deactivating the paths (126) and (127) and activating the path (128).

[0052] The scan within the first method (201) may be performed while the scan within the second method (202) and the scan within the third method (203) are not performed. The scan within the second method (202) may be performed while the scan within the first method (201) and the scan within the third method (203) are not performed. The scan within the third method (203) may be performed while the scan within the first method (201) and the scan within the second method (202) are not performed. The scan within the first method (201) and the scan within the second method (202) may not be performed simultaneously. The scan within the first method (201) and the scan within the third method (203) may not be performed simultaneously. The scan within the second method (202) and the scan within the third method (203) may not be performed simultaneously. The scan within the first method (201), the scan within the second method (202), and the scan within the third method (203) may not be performed simultaneously.

[0053] The scan within the first method (201) is not performed simultaneously with the scan within the second method (202), but the scan within the first method (201) and the scan within the second method (202) may be performed together within a time interval corresponding to a vertical synchronization signal (or a time interval corresponding to a refresh rate). For example, the scan within the first method (201) may be performed within a first part of the time interval, and the scan within the second method (202) may be performed within a second part of the time interval. The second part of the time interval during which the scan is performed in the second method (202) may not overlap with the first part of the time interval during which the scan is performed in the first method (201).

[0054] The scan within the first method (201) is not performed simultaneously with the scan within the third method (203), but the scan within the first method (201) and the scan within the third method (203) may be performed together within the time interval. For example, the scan within the first method (201) may be performed within a first part of the time interval, and the scan within the third method (203) may be performed within a second part of the time interval. The second part of the time interval during which the scan is performed using the third method (203) may not overlap with the first part of the time interval during which the scan is performed using the first method (201).

[0055] The scan within the second method (202) is not performed simultaneously with the scan within the third method (203), but the scan within the second method (202) and the scan within the third method (203) may be performed together within the time interval. For example, the scan within the second method (202) may be performed within a first part of the time interval, and the scan within the third method (203) may be performed within a second part of the time interval. The second part of the time interval during which the scan is performed using the third method (203) may not overlap with the first part of the time interval during which the scan is performed using the second method (202).

[0056] The scan within the first method (201) is not performed simultaneously with the scan within the second method (202) and the scan within the third method (203), but the scan within the first method (201), the scan within the second method (202), and the scan within the third method (203) may be performed together within a time interval corresponding to a vertical synchronization signal (or a time interval corresponding to a refresh rate). For example, the scan within the first method (201) may be performed within a first part of the time interval, the scan within the second method (202) may be performed within a second part of the time interval, and the scan within the third method (203) may be performed within a third part of the time interval. The first part of the time interval in which the scan is performed in the first manner (201), the second part of the time interval in which the scan is performed in the second manner (202), and the third part of the time interval in which the scan is performed in the third manner (203) may not overlap with each other.

[0057] At least one processor (110) may transmit an image to be displayed through a portion of the display panel (122) to the display driving circuit (121) through the interface (130). The image to be displayed through the portion of the display panel (122) may be transmitted to the display driving circuit (121) through a vertical synchronization signal. The image may be stored in the memory (124) based on the first command from the at least one processor (110). The image may be stored in the memory (124) based on a decision of the display driving circuit (121). The display driving circuit (121) may perform the scan in the second manner (202) when the image is stored in the memory (124). The image may not be stored in the memory (124) based on the second command from the at least one processor (110). The image may not be stored in the memory (124) based on a decision of the display driving circuit (121). The display driving circuit (121) may perform the scan in the first manner (201) when the image is not stored in the memory (124). The display (120) may or may not support multi-frequency driving (MFD), which performs display on a second portion of the display panel (122) at a second refresh rate while performing display on a first portion of the display panel (122) at a first refresh rate. The multi-frequency driving will be described in more detail with reference to FIG. 4.

[0058] For example, the display driving circuit (121) within the display (120) supporting the multi-frequency driving may receive an image to be displayed through a portion of the display panel (122) through the vertical synchronization signal, and perform scanning of the image in relation to the portion of the display panel (122) in a first manner (201) or a second manner (202) within a time period corresponding to the vertical synchronization signal, and may not perform scanning in relation to another portion (or the remaining portion) of the display panel (122). The operations of the display driving circuit (121) within the display (120) supporting the multi-frequency driving will be described with reference to FIG. 5.

[0059] For example, the display driving circuit (121) in the display (120) that does not support the multi-frequency driving may receive an image to be displayed through a portion of the display panel (122) through the vertical synchronization signal, and perform scanning of the image with respect to the portion of the display panel (122) within a time period corresponding to the vertical synchronization signal in a first manner (201) or a second manner (202), and perform scanning with respect to another portion (or the remaining portion) of the display panel (122) in a third manner (203). The operations of the display driving circuit (121) in the display (120) that does not support the multi-frequency driving will be described with reference to FIG. 3.

[0060] At least one processor (110) may not transmit an image to be displayed through the display panel (122) to the display driving circuit (121) through the interface (130). During a time period in which at least one processor (110) does not transmit an image to the display driving circuit (121), the display driving circuit (121) may refrain from performing a scan in the first manner (201), performing a scan in the second manner (202), and performing a scan in the third manner (203). During a time period in which at least one processor (110) does not transmit an image to the display driving circuit (121), the display driving circuit (121) may perform a scan in the third manner (203). The display driving circuit (121) within the display (120) that does not support the multi-frequency driving may perform the scan in the third manner (203) with respect to the display panel (122) (or with respect to the entire display panel (122)) within the time interval. The display driving circuit (121) within the display (120) that supports the multi-frequency driving may perform the scan in the third manner (203) with respect to a portion of the display panel (122) within a portion of the time interval. The scan within the third manner (203) may be performed based on a command from at least one processor (110) and / or a decision of the display driving circuit (121).

[0061] FIG. 3 illustrates the operation of a display driving circuit performed based on reception of an image to be displayed on a portion of a display panel.

[0062] Referring to FIG. 3, at least one processor (110) may transmit an image (310) to be displayed on a display panel (122) to a display driving circuit (121) through the interface (130), such as a state (301) of the interface (130). The image (310) may be transmitted according to the video hybrid mode. The at least one processor (110) may transmit the image (310) to the display driving circuit (121) based on transmitting information (397-1) about a position of the display panel (122) corresponding to the image (310) and a vertical synchronization signal (VSS) packet (398-1) for the image (310) to the display driving circuit (121). As a non-limiting example, the image (310) may be transmitted after the first command is transmitted to the display driving circuit (121). The image (310) can be transmitted in connection with the first command.

[0063] The display driving circuit (121) can scan the image (310) received from at least one processor (110) in a second manner (202). The scanning in the second manner (202) can be performed based on the first command. The display driving circuit (121) can store the image (310) in the memory (124) as indicated by arrow (361) by providing the image (310) to the memory (124) through the path (127) as indicated by state (381). Providing the image (310) to the memory (124) as indicated by state (381) can be performed according to a vertical synchronization signal (399-1) for the display driving circuit (121). Storing the image (310) in the memory (124) as indicated by arrow (361) can be performed according to information (397-1). The display driving circuit (121) can perform the scan within the second method (202) by scanning the image (310) through the path (126) as indicated by the arrow (362) while storing the image (310) in the memory (124) as indicated by the arrow (361). The image (310) can be displayed through the display panel (122) according to the scan within the second method (202). The image (310) can be displayed through the display panel (122) according to the vertical synchronization signal (399-1).

[0064] At least one processor (110) can transmit an image (320) to be displayed through a first portion (371) of a display panel (122) to the display driving circuit (121) through the interface (130), such as a state (302) of the interface (130). The image (320) can be transmitted according to the video hybrid mode. At least one processor (110) can transmit the image (320) to the display driving circuit (121) based on transmitting information (397-2) about a position of the display panel (122) corresponding to the image (320) (e.g., the first portion (371) of the display panel (122)) and a VSS packet (398-2) for the image (320) to the display driving circuit (121). As a non-limiting example, the image (320) may be transmitted after the first command is transmitted to the display driving circuit (121). The image (320) may be transmitted in relation to the first command.

[0065] The display driving circuit (121) can scan the image (320) received from at least one processor (110) in the second manner (202). The scanning in the second manner (202) can be performed based on the first command. The display driving circuit (121) can store the image (320) in the memory (124) as indicated by arrow (363) by providing the image (320) to the memory (124) through the path (127) as indicated by state (382). Providing the image (320) to the memory (124) as indicated by state (382) can be performed according to a vertical synchronization signal (399-2) for the display driving circuit (121). Storing the image (320) in the memory (124) as indicated by arrow (363) can be performed according to information (397-2). A first part (311) of an image (310) stored in a memory (124) can be maintained after storing the image (320) in the memory (124) as indicated by an arrow (363). The display driving circuit (121) can perform the scan within the second method (202) by scanning the image (320) through a path (126) as indicated by an arrow (364) while storing the image (320) in the memory (124) as indicated by an arrow (363). The image (320) can be displayed through the first part (371) of the display panel (122) according to the scan within the second method (202).

[0066] The display driving circuit (121) in the display (120) that does not support the above multi-frequency driving can perform the scan within the third method (203), which acquires a first part (311) of the image (310) from the memory (124) based on scanning the image (320), and performs scanning of the first part (311) of the image (310) acquired from the memory (124) as indicated by an arrow (365). The scan within the third method (203) can be performed according to a vertical synchronization signal (399-2). The first part (311) of the image (310) can be displayed through the second part (372) of the display panel (122) according to the scan within the third method (203).

[0067] The display driving circuit (121) can perform a scan of the image (320) in a second manner (202) within a first portion of a time interval corresponding to a vertical synchronization signal (399-2), and can perform a scan of the first portion (311) of the image (310) in a third manner (203) within a second portion of the time interval. The display driving circuit (121) can display the image (320) and the first portion (311) of the image (310) based on the scan of the image (320) performed in the second manner (202) within the first portion of the time interval and the scan of the first portion (311) of the image (310) performed in the third manner (203) within the second portion of the time interval.

[0068] At least one processor (110) can transmit an image (330) to be displayed through the fourth part (374) of the display panel (122) to the display driving circuit (121) through the interface (130), such as the state (303) of the interface (130). The image (330) can be transmitted according to the video hybrid mode. At least one processor (110) can transmit the image (330) to the display driving circuit (121) based on transmitting information (397-3) about a position of the display panel (122) corresponding to the image (330) (e.g., the fourth part (374) of the display panel (122)) and a VSS packet (398-3) for the image (330) to the display driving circuit (121). As a non-limiting example, the image (330) may be transmitted after the second command is transmitted to the display driving circuit (121). The image (330) may be transmitted in connection with the second command.

[0069] The display driving circuit (121) can scan an image (330) received from at least one processor (110) in a first manner (201). The scan in the first manner (201) can be performed based on the second command. The display driving circuit (121) can perform the scan in the first manner (201) by performing the scan of the image (330) through the path (126) as indicated by the arrow (366) without providing the image to the memory (124) through the path (127) as indicated by the state (383). The scan in the first manner (201) can be performed according to the vertical synchronization signal (399-3). The image (330) can be displayed through the fourth part (374) of the display panel (122) according to the scan in the first manner (201).

[0070] The display driving circuit (121) in the display (120) that does not support the above multi-frequency driving can perform a scan within the third method (203) before performing the scan of the image (330) within the first method (201). The display driving circuit (121) can perform the scan within the third method (203) by obtaining, from the memory (124), the second part (312) of the image (310) to be displayed through the third part (373) of the display panel (122) and the image (320) to be displayed through the first part (371) of the display panel (122), and performing a scan of the second part (312) of the image (310) and the image (320) obtained from the memory (124) as indicated by an arrow (367). The scan within the third method (203) can be performed according to a vertical synchronization signal (399-3). The second part (312) and the image (320) of the image (310) can be displayed respectively through the third part (373) of the display panel (122) and the first part (371) of the display panel (122), according to the scan within the third method (203).

[0071] The display driving circuit (121) can scan the image (320) in a third manner (203) within a first part of a time interval corresponding to a vertical synchronization signal (399-3), scan the second part (312) of the image (310) in a third manner (203) within a second part of the time interval, and scan the image (330) in a first manner (201) within a third part of the time interval. The display driving circuit (121) can display the image (320), the second part (312) of the image (310), and the image (330) based on the scanning of the image (320) performed in the third manner (203) within the first part of the time interval, the scanning of the second part (312) of the image (310) performed in the third manner (203) within the second part of the time interval, and the scanning of the image (330) performed in the first manner (201) within the third part of the time interval.

[0072] At least one processor (110) can transmit an image (340) to be displayed through a fourth part (374) of the display panel (122) to the display driving circuit (121) through the interface (130), such as the state (304) of the interface (130). The image (340) can be transmitted according to the video hybrid mode. At least one processor (110) can transmit the image (340) to the display driving circuit (121) based on transmitting information (397-4) about a position of the display panel (122) corresponding to the image (340) (e.g., the fourth part (374) of the display panel (122)) and a VSS packet (398-4) for the image (340) to the display driving circuit (121). As a non-limiting example, the image (340) may be transmitted after the first command is transmitted to the display driving circuit (121). The image (340) may be transmitted in connection with the first command.

[0073] The display driving circuit (121) can scan the image (340) received from at least one processor (110) in the second manner (202). The scanning in the second manner (202) can be performed based on the first command. The display driving circuit (121) can store the image (340) in the memory (124) as indicated by arrow (368) by providing the image (340) to the memory (124) through the path (127) as indicated by state (384). Providing the image (340) to the memory (124) as indicated by state (384) can be performed according to a vertical synchronization signal (399-4) for the display driving circuit (121). Storing the image (340) in the memory (124) as indicated by arrow (368) can be performed according to information (397-4). The second part (312) of the image (310) stored in the memory (124) and the image (320) can be maintained after storing the image (340) in the memory (124) as indicated by the arrow (368). The display driving circuit (121) can perform the scan within the second method (202) by scanning the image (340) through the path (126) as indicated by the arrow (369) while storing the image (340) in the memory (124) as indicated by the arrow (368). The image (340) can be displayed through the fourth part (374) of the display panel (122) according to the scan within the second method (202).

[0074] The display driving circuit (121) in the display (120) that does not support the above multi-frequency driving can perform a scan within the third method (203) before performing the scan of the image (340) within the second method (202). The display driving circuit (121) can perform the scan within the third method (203) by obtaining, from the memory (124), the second part (312) of the image (310) to be displayed through the third part (373) of the display panel (122) and the image (320) to be displayed through the first part (371) of the display panel (122), and performing a scan of the second part (312) of the image (310) and the image (320) obtained from the memory (124) as indicated by an arrow (370). The scan within the third method (203) can be performed according to a vertical synchronization signal (399-4). The second part (312) and the image (320) of the image (310) can be displayed respectively through the third part (373) of the display panel (122) and the first part (371) of the display panel (122), according to the scan within the third method (203).

[0075] The display driving circuit (121) can scan the image (320) in a third manner (203) within a first portion of a time interval corresponding to a vertical synchronization signal (399-4), scan the second portion (312) of the image (310) in a third manner (203) within a second portion of the time interval, and scan the image (340) in a second manner (202) within a third portion of the time interval. The display driving circuit (121) can display the image (320), the second part (312) of the image (310), and the image (340) based on the scanning of the image (320) performed in the third manner (203) within the first part of the time interval, the scanning of the second part (312) of the image (310) performed in the third manner (203) within the second part of the time interval, and the scanning of the image (340) performed in the second manner (202) within the third part of the time interval.

[0076] At least one processor (110) can transmit an image (350) to be displayed through a first part (371) of the display panel (122) and an image (360) to be displayed through a third part (373) of the display panel (122) to the display driving circuit (121) through the interface (130), such as a state (305) of the interface (130). The image (350) and the image (360) can be transmitted according to the video hybrid mode. At least one processor (110) may transmit the image (350) and the image (360) to the display driving circuit (121) based on transmitting information (397-5) about the location of the display panel (122) corresponding to each of the image (350) and the image (360) (e.g., each of the first portion (371) of the display panel (122) and the third portion (373) of the display panel (122)) and a VSS packet (398-5) for the image (350) and the image (360) to the display driving circuit (121). As a non-limiting example, the image (350) may be transmitted after the second command is transmitted to the display driving circuit (121). The image (350) may be transmitted in connection with the second command. As a non-limiting example, the image (360) may be transmitted after the first command is transmitted to the display driving circuit (121). The image (360) can be transmitted in connection with the first command.

[0077] The display driving circuit (121) can scan an image (350) received from at least one processor (110) in a first manner (201). The scan in the first manner (201) can be performed based on the second command. The display driving circuit (121) can perform the scan in the first manner (201) by performing the scan of the image (350) through the path (126) as indicated by the arrow (376) without providing the image (350) to the memory (124) through the path (127) as indicated by the state (385). The scan in the first manner (201) can be performed according to a vertical synchronization signal (399-5). The image (350) can be displayed through the first part (371) of the display panel (122) according to the scan in the first manner (201).

[0078] The display driving circuit (121) can scan the image (360) received from at least one processor (110) in a second manner (202). The scanning in the second manner (202) can be performed based on the first command. The display driving circuit (121) can store the image (360) in the memory (124) as indicated by arrow (377) by providing the image (360) to the memory (124) through the path (127) as indicated by state (385). Providing the image (360) to the memory (124) as indicated by state (385) can be performed according to a vertical synchronization signal (399-5) for the display driving circuit (121). Storing the image (360) in the memory (124) as indicated by arrow (377) can be performed according to information (397-5). The image (320) and the image (340) stored in the memory (124) can be maintained after storing the image (360) in the memory (124) as indicated by the arrow (377). The display driving circuit (121) can perform the scan within the second method (202) by scanning the image (360) through the path (126) as indicated by the arrow (378) while storing the image (360) in the memory (124) as indicated by the arrow (377). The image (360) can be displayed through the third part (373) of the display panel (122) according to the scan within the second method (202).

[0079] The display driving circuit (121) in the display (120) that does not support the above multi-frequency driving can perform the scan in the third method (203) based on performing the scan of the image (350) in the first method (201) and performing the scan of the image (360) in the second method (202). The display driving circuit (121) can perform the scan in the third method (203) by obtaining the image (340) to be displayed through the fourth part (374) of the display panel (122) from the memory (124) and performing the scan of the image (340) obtained from the memory (124) as indicated by the arrow (379). The scan in the third method (203) can be performed according to the vertical synchronization signal (399-5). The image (340) can be displayed through the fourth part (374) of the display panel (122) according to the scan in the third method (203).

[0080] The display driving circuit (121) can scan the image (350) in a first manner (201) within a first portion of a time interval corresponding to a vertical synchronization signal (399-5), scan the image (360) in a second manner (202) within a second portion of the time interval, and scan the image (340) in a third manner (203) within a third portion of the time interval. The display driving circuit (121) can display the image (350), the image (360), and the image (340) based on the scanning of the image (350) performed in the first manner (201) within the first portion of the time interval, the scanning of the image (360) performed in the second manner (202) within the second portion of the time interval, and the scanning of the image (340) performed in the third manner (203) within the third portion of the time interval.

[0081] The display driving circuit (121) can reduce or optimize the power consumed to display an image through a portion of the display panel (122) through the operations described with reference to FIG. 3.

[0082] Unlike what is described in FIG. 3, the display (120) can support multi-frequency driving.

[0083] Figure 4 illustrates an example of multi-frequency driving.

[0084] Referring to FIG. 4, the display panel (122) within the display (120) supporting the multi-frequency driving may include a display area (410) (or active area (410)) that is viewable from the front side of the electronic device (100). The display area (410) may define at least a portion of the front side of the electronic device (100). The display area (410) may be usable for displaying a screen viewable from the front side of the electronic device (100). For example, the display area (410) may be used for displaying a screen (490).

[0085] A screen (490) displayed on a display area (410) may include a first portion (491), a second portion (492), and a third portion (493). The first portion (491) of the screen (490), the second portion (492) of the screen (490), and the third portion (493) of the screen (490) may be displayed simultaneously at one (a) timing or within one (a) time interval. The first portion (491) of the screen (490) may be displayed on the first portion (411) of the display area (410). The second portion (492) of the screen (490) may be displayed on the second portion (412) of the display area (410) while the first portion (491) of the screen (490) is displayed on the first portion (411) of the display area (410). The third part (493) of the screen (490) can be displayed on the third part (413) of the display area (410) while the first part (491) of the screen (490) is displayed on the first part (411) of the display area (410) and the second part (492) of the screen (490) is displayed on the second part (412) of the display area (410).

[0086] For example, the first part (491) of the screen (490) may be used to provide the status of the electronic device (100). The first part (491) of the screen (490) may be an indicator area. For example, the second part (492) of the screen (490) and the third part (493) of the screen (490) may be used to provide a user interface (or execution screen) of a software application. The second part (492) of the screen (490) may represent a sub-region of the user interface that provides one or more contents whose status changes (over time) independently (or regardless) of whether a user input for the electronic device (100) is received. The third part (493) of the screen (490) may represent a sub-region of the user interface that provides one or more contents whose status changes on the condition that a user input for the electronic device (100) is received. The second portion (492) of the screen (490) may represent a sub-region of the user interface that is used to provide one or more other contents whose state changes more frequently than one or more contents provided within the third portion (493) of the screen (490). As a non-limiting example, the second portion (492) of the screen (490) may represent a sub-region of the user interface that provides a moving picture that is being played, and the third portion (493) of the screen (490) may represent a sub-region of the user interface that provides visual information (e.g., still images, text, characters, graphical objects, and / or visual objects) related to the moving picture.

[0087] For example, at least one processor (110) may obtain an image provided through a first portion (491) of a screen (490) in response to an event causing a change in the state of the electronic device (100). For example, at least one processor (110) may obtain (or generate) one or more images provided through a second portion (492) of the screen (490) and a third portion (493) of the screen (490) using the software application. As a non-limiting example, at least one processor (110) may generate (or acquire) one or more images to be provided through the second portion (492) of the screen (490) every first period using the software application, and may generate (or acquire) one or more images to be provided through the third portion (493) of the screen (490) every second period longer than the first period using the software application. As a non-limiting example, at least one processor (110) can periodically acquire, using the software application, one or more images to be presented through a second portion (492) of the screen (490), independently of whether a user input is received with respect to the user interface, and can acquire, using the software application, one or more images to be presented through a third portion (493) of the screen (490), on the condition that a user input is received with respect to the user interface.

[0088] The state of the second part (492) of the screen (490) may change more frequently than the state of the first part (491) of the screen (490) and the state of the third part (493) of the screen (490). The state of the second part (492) of the screen (490) may change while the states of the first part (491) of the screen (490) and the third part (493) of the screen (490) are maintained.

[0089] Since the speed of change of the state of the second part (492) of the screen (490) is faster than the speed of change of the state of the first part (491) of the screen (490) and the speed of change of the state of the third part (493) of the screen (490), the second refresh rate suitable for providing the second part (492) of the screen (490) may be higher than the first refresh rate suitable for providing the first part (491) of the screen (490) and the third refresh rate suitable for providing the third part (493) of the screen (490). As a non-limiting example, since the second refresh rate is higher than the first refresh rate and the third refresh rate, performing display on the second portion (492) of the screen (490) at the second refresh rate while performing display on the first portion (491) of the screen (490) at the first refresh rate and performing display on the third portion (493) of the screen (490) at the third refresh rate can be utilized within the electronic device (100) to reduce power consumption. For example, the electronic device (100) can display the second portion (492) of the screen (490) at the second refresh rate while displaying the first portion (491) of the screen (490) at the first refresh rate and displaying the third portion (493) of the screen (490) at the third refresh rate, using less power than the power consumed by providing the screen (490) at the second refresh rate. As a non-limiting example, the third playback rate may be different from the first playback rate. As a non-limiting example, the third playback rate may be the same as the first playback rate.

[0090] The electronic device (100) may perform display on a second part (412) of the display area (410) at the second refresh rate while performing display on a first part (411) of the display area (410) at the first refresh rate to display a second part (492) of the screen (490) at the second refresh rate while displaying a first part (491) of the screen (490) and a third part (493) of the screen (490) at the first refresh rate. For example, driving (or controlling) (or causing) the display (120) (or the display panel (122)) to perform display on a second part (412) of the display area (410) at the second refresh rate while performing display on the first part (411) of the display area (410) at the first refresh rate may be described as multi-frequency driving.

[0091] FIG. 5 illustrates the operation of a display driving circuit performed based on reception of an image to be displayed on a portion of a display panel within a display supporting multi-frequency driving.

[0092] Referring to FIG. 5, at least one processor (110) may transmit an image (510) to be displayed on a display panel (122) to a display driving circuit (121) through the interface (130), such as a state (501) of the interface (130). The image (510) may be transmitted according to the video hybrid mode. The at least one processor (110) may transmit the image (510) to the display driving circuit (121) based on transmitting information (597-1) about a position of the display panel (122) corresponding to the image (510) and a vertical synchronization signal (VSS) packet (598-1) for the image (510) to the display driving circuit (121). As a non-limiting example, the image (510) may be transmitted after the first command is transmitted to the display driving circuit (121). The image (510) can be transmitted in connection with the first command.

[0093] The display driving circuit (121) can scan the image (510) received from at least one processor (110) in a second manner (202). The scanning in the second manner (202) can be performed based on the first command. The display driving circuit (121) can store the image (510) in the memory (124) as indicated by arrow (561) by providing the image (510) to the memory (124) through the path (127) as indicated by state (581). Providing the image (510) to the memory (124) as indicated by state (581) can be performed according to a vertical synchronization signal (599-1) for the display driving circuit (121). Storing the image (510) in the memory (124) as indicated by arrow (561) can be performed according to information (597-1). The display driving circuit (121) can perform the scan within the second method (202) by scanning the image (510) through the path (126) as indicated by the arrow (562) while storing the image (510) in the memory (124) as indicated by the arrow (561). The image (510) can be displayed through the display panel (122) according to the scan within the second method (202). The image (510) can be displayed through the display panel (122) according to the vertical synchronization signal (599-1).

[0094] At least one processor (110) can transmit an image (520) to be displayed through a first portion (571) of a display panel (122) to the display driving circuit (121) through the interface (130), such as a state (502) of the interface (130). The image (520) can be transmitted according to the video hybrid mode. At least one processor (110) can transmit the image (520) to the display driving circuit (121) based on transmitting information (597-2) about a position of the display panel (122) corresponding to the image (520) (e.g., the first portion (571) of the display panel (122)) and a VSS packet (598-2) for the image (520) to the display driving circuit (121). As a non-limiting example, the image (520) may be transmitted after the first command is transmitted to the display driving circuit (121). The image (520) may be transmitted in relation to the first command.

[0095] The display driving circuit (121) can scan the image (520) received from at least one processor (110) in the second manner (202). The scanning in the second manner (202) can be performed based on the first command. The display driving circuit (121) can store the image (520) in the memory (124) as indicated by arrow (563) by providing the image (520) to the memory (124) through the path (127) as indicated by state (582). Providing the image (520) to the memory (124) as indicated by state (582) can be performed according to a vertical synchronization signal (599-2) for the display driving circuit (121). Storing the image (520) in the memory (124) as indicated by arrow (563) can be performed according to information (597-2). A first part (511) of an image (510) stored in the memory (124) can be maintained after storing the image (520) in the memory (124) as indicated by an arrow (563). The display driving circuit (121) can perform the scan within the second method (202) by scanning the image (520) through a path (126) as indicated by an arrow (564) while storing the image (520) in the memory (124) as indicated by an arrow (563). The image (520) can be displayed through the first part (571) of the display panel (122) according to the scan within the second method (202).

[0096] The display driving circuit (121) within the display (120) supporting the above multi-frequency driving may refrain from performing a scan with respect to a second portion (572) of the display panel (122) based on scanning the image (520). The display driving circuit (121) may bypass or skip the scan with respect to the second portion (572) of the display panel (122). The scan with respect to the second portion (572) of the display panel (122) may be skipped, but the first portion (511) of the image (510) displayed according to the vertical synchronization signal (599-1) may be maintained.

[0097] The display driving circuit (121) can perform a scan of the image (520) in the second manner (202) within a portion of the time interval corresponding to the vertical synchronization signal (599-2). The display driving circuit (121) can change the first portion (511) of the image (510) and the remaining portion of the other image (510) into the image (520) based on the scan of the image (520) performed in the second manner (202) within the portion of the time interval. The refresh rate provided through the first portion (571) of the display panel (122) can be higher than the refresh rate provided through the second portion (572) of the display panel (122) depending on the image (520) changed from the remaining portion of the image (510).

[0098] At least one processor (110) can transmit an image (530) to be displayed through a fourth part (574) of the display panel (122) to the display driving circuit (121) through the interface (130), such as a state (503) of the interface (130). The image (530) can be transmitted according to the video hybrid mode. At least one processor (110) can transmit the image (530) to the display driving circuit (121) based on transmitting information (597-3) about a position of the display panel (122) corresponding to the image (530) (e.g., the fourth part (574) of the display panel (122)) and a VSS packet (598-3) for the image (530) to the display driving circuit (121). As a non-limiting example, the image (530) may be transmitted after the second command is transmitted to the display driving circuit (121). The image (530) may be transmitted in connection with the second command.

[0099] The display driving circuit (121) can scan an image (530) received from at least one processor (110) in a first manner (201). The scan in the first manner (201) can be performed based on the second command. The display driving circuit (121) can perform the scan in the first manner (201) by performing the scan of the image (530) through the path (126) as indicated by the arrow (566) without providing the image to the memory (124) through the path (127) as indicated by the state (583). The scan in the first manner (201) can be performed according to the vertical synchronization signal (599-3). The image (530) can be displayed through the fourth part (574) of the display panel (122) according to the scan in the first manner (201).

[0100] The display driving circuit (121) can perform a scan within the third method (203) before performing the scan of the image (530) within the first method (201). The display driving circuit (121) can perform the scan within the third method (203) by obtaining, from the memory (124), the second part (512) of the image (510) to be displayed through the third part (573) of the display panel (122) and the image (520) to be displayed through the first part (571) of the display panel (122), and performing a scan of the second part (512) of the image (510) and the image (520) obtained from the memory (124) as indicated by an arrow (567). The scan within the third method (203) can be performed according to a vertical synchronization signal (599-3). The second part (512) and the image (520) of the image (510) can be displayed respectively through the third part (573) of the display panel (122) and the first part (571) of the display panel (122), according to the scan within the third method (203).

[0101] The display driving circuit (121) can scan the image (520) in a third manner (203) within a first portion of a time interval corresponding to a vertical synchronization signal (599-3), scan the second portion (512) of the image (510) in a third manner (203) within a second portion of the time interval, and scan the image (530) in a first manner (201) within a third portion of the time interval. The display driving circuit (121) can display the image (520), the second part (512) of the image (510), and the image (530) based on the scanning of the image (520) performed in the third manner (203) within the first part of the time interval, the scanning of the second part (512) of the image (510) performed in the third manner (203) within the second part of the time interval, and the scanning of the image (530) performed in the first manner (201) within the third part of the time interval.

[0102] At least one processor (110) can transmit an image (540) to be displayed through a fourth part (574) of the display panel (122) to the display driving circuit (121) through the interface (130), such as a state (504) of the interface (130). The image (540) can be transmitted according to the video hybrid mode. At least one processor (110) can transmit the image (540) to the display driving circuit (121) based on transmitting information (597-4) about a position of the display panel (122) corresponding to the image (540) (e.g., the fourth part (574) of the display panel (122)) and a VSS packet (598-4) for the image (540) to the display driving circuit (121). As a non-limiting example, the image (540) may be transmitted after the first command is transmitted to the display driving circuit (121). The image (540) may be transmitted in connection with the first command.

[0103] The display driving circuit (121) can scan the image (540) received from at least one processor (110) in the second manner (202). The scanning in the second manner (202) can be performed based on the first command. The display driving circuit (121) can store the image (540) in the memory (124) as indicated by arrow (568) by providing the image (540) to the memory (124) through the path (127) as indicated by state (584). Providing the image (540) to the memory (124) as indicated by state (584) can be performed according to a vertical synchronization signal (599-4) for the display driving circuit (121). Storing the image (540) in the memory (124) as indicated by arrow (568) can be performed according to information (597-4). The second part (512) of the image (510) stored in the memory (124) and the image (520) can be maintained after storing the image (540) in the memory (124) as indicated by the arrow (568). The display driving circuit (121) can perform the scan within the second method (202) by scanning the image (540) through the path (126) as indicated by the arrow (569) while storing the image (540) in the memory (124) as indicated by the arrow (568). The image (540) can be displayed through the fourth part (574) of the display panel (122) according to the scan within the second method (202).

[0104] The display driving circuit (121) within the display (120) supporting the above multi-frequency driving may refrain from performing a scan with respect to the first part (571) and the third part (573) of the display panel (122) before performing the scan of the image (540) in the second manner (202). The display driving circuit (121) may perform a scan according to the vertical synchronization signal (599-4) in the second manner (202) in response to a timing corresponding to the fourth part (574) of the display panel (122). The display driving circuit (121) may bypass or skip the scan with respect to the first part (571) and the third part (573) of the display panel (122). The scans related to the first part (571) and the third part (573) of the display panel (122) are skipped, but the second part (512) and the image (520) of the image (510) displayed according to the vertical synchronization signal (599-3) can be maintained.

[0105] The display driving circuit (121) can perform a scan of the image (540) in the second manner (202) within a portion of the time interval corresponding to the vertical synchronization signal (599-4). The display driving circuit (121) can change the image (530) into the image (540) based on the scan of the image (540) performed in the second manner (202) within the portion of the time interval. The refresh rate provided through the fourth portion (574) of the display panel (122) may be different from the refresh rate provided through the first portion (571) of the display panel (122) and the refresh rate provided through the third portion (573) of the display panel (122), depending on the image (540) changed from the image (530).

[0106] At least one processor (110) can transmit an image (550) to be displayed through a first part (571) of the display panel (122) and an image (560) to be displayed through a third part (573) of the display panel (122) to the display driving circuit (121) through the interface (130), such as a state (505) of the interface (130). The image (550) and the image (560) can be transmitted according to the video hybrid mode. At least one processor (110) may transmit the image (550) and the image (560) to the display driving circuit (121) based on transmitting information (597-5) about the location of the display panel (122) corresponding to each of the image (550) and the image (560) (e.g., each of the first portion (571) of the display panel (122) and the third portion (573) of the display panel (122)) and a VSS packet (598-5) for the image (550) and the image (560) to the display driving circuit (121). As a non-limiting example, the image (550) may be transmitted after the second command is transmitted to the display driving circuit (121). The image (550) may be transmitted in connection with the second command. As a non-limiting example, the image (560) may be transmitted after the first command is transmitted to the display driving circuit (121). The image (560) can be transmitted in connection with the first command.

[0107] The display driving circuit (121) can scan an image (550) received from at least one processor (110) in a first manner (201). The scan in the first manner (201) can be performed based on the second command. The display driving circuit (121) can perform the scan in the first manner (201) by performing the scan of the image (550) through the path (126) as indicated by the arrow (576) without providing the image (550) to the memory (124) through the path (127) as indicated by the state (585). The scan in the first manner (201) can be performed according to a vertical synchronization signal (599-5). The image (550) can be displayed through the first part (571) of the display panel (122) according to the scan in the first manner (201).

[0108] The display driving circuit (121) can scan the image (560) received from at least one processor (110) in the second manner (202). The scanning in the second manner (202) can be performed based on the first command. The display driving circuit (121) can store the image (560) in the memory (124) as indicated by arrow (577) by providing the image (560) to the memory (124) through the path (127) as indicated by state (585). Providing the image (560) to the memory (124) as indicated by state (585) can be performed according to a vertical synchronization signal (599-5) for the display driving circuit (121). Storing the image (560) in the memory (124) as indicated by arrow (577) can be performed according to information (597-5). The image (520) and the image (540) stored in the memory (124) can be maintained after storing the image (560) in the memory (124) as indicated by the arrow (577). The display driving circuit (121) can perform the scan within the second method (202) by scanning the image (560) through the path (126) as indicated by the arrow (578) while storing the image (560) in the memory (124) as indicated by the arrow (577). The image (560) can be displayed through the third part (573) of the display panel (122) according to the scan within the second method (202).

[0109] The display driving circuit (121) within the display (120) supporting the above multi-frequency driving may refrain from performing a scan with respect to the fourth portion (574) of the display panel (122) based on performing the scan of the image (550) in the first manner (201) and performing the scan of the image (560) in the second manner (202). The display driving circuit (121) may bypass or skip the scan with respect to the fourth portion (574) of the display panel (122). Although the scan with respect to the fourth portion (574) of the display panel (122) is skipped, the image (540) displayed according to the vertical synchronization signal (599-4) may be maintained.

[0110] The display driving circuit (121) can perform a scan of the image (550) in a first manner (201) within a first portion of a time interval corresponding to a vertical synchronization signal (599-5) and can perform a scan of the image (560) in a second manner (202) within a second portion of the time interval. The display driving circuit (121) can change the image (520) and the second portion (512) of the image (510) into the image (550) and the image (560), respectively, based on the scan of the image (550) performed in the first manner (201) within the first portion of the time interval and the scan of the image (560) performed in the second manner (202) within the second portion of the time interval. The refresh rate provided through each of the first part (571) of the display panel (122) and the third part (573) of the display panel (122) may be different from the refresh rate provided through the fourth part (574) of the display panel (122) depending on each of the images (550) and (560) that have been changed from each of the second part (512) of the image (520) and the image (510).

[0111] The operations described with reference to FIG. 5 can be applied with respect to FIG. 4. Referring again to FIG. 4, the display driving circuit (121) can perform scanning in the third manner (203) to display a first portion (491) of the screen (490), perform scanning in the first manner (201) to display a second portion (492) of the screen (490), and perform scanning in the second manner (202) to display a third portion (493) of the screen (490). For example, the scanning in the third manner (203) can be performed to maintain the first portion (491) of the screen (490) before the content in the first portion (491) of the screen (490) changes from the first content (e.g., 10:23 or 23) to the second content (e.g., 10:24 or 24). For example, the scan within the first mode (201) may be performed to change the content within the first portion (491) of the screen (490). For example, the scan within the second mode (202) may be performed to change the content within the third portion (493) of the screen (490) according to a user input. As a non-limiting example, the display driver circuit (121) may perform a scan within the third mode (203) with respect to the third portion (493) of the screen (490) when no user input is received for a certain period of time after performing the scan within the second mode (202) for the third portion (493) of the screen (490).

[0112] The display driving circuit (121) can reduce or optimize the power consumed to display an image through a portion of the display panel (122) through the operations described with reference to FIGS. 4 and 5.

[0113] Transmitting location information (e.g., information (397-1), information (397-2), information (397-3), information (397-4), information (397-5), information (597-1), information (597-2), information (597-3), information (597-4), and information (597-5)) from at least one processor (110) to the display driving circuit (121) may be optional. The display driving circuit (121) may identify the location information according to the time (or time interval) (or timing) (or point in time) at which the image is received from at least one processor (110) via the interface (130). In other words, identifying the location information may be implemented in various ways. Transmitting an image from at least one processor (110) to the display driving circuit (121) in relation to the location information is described with reference to FIGS. 6 to 8.

[0114] Figures 6 to 8 illustrate a method for identifying location information.

[0115] Referring to FIG. 6, at least one processor (110) and display driving circuit (121) can operate for the video hybrid mode.

[0116] The display panel (122) may have a horizontal direction (691) and a vertical direction (692). The display driving circuit (121) may sequentially perform scans in the horizontal direction (691) for display on the display area of ​​the display panel (122). The scans in the horizontal direction (691) may be sequentially performed in the vertical direction (692). For example, the display area of ​​the display panel (122) may include a first horizontal line and a second horizontal line extending in the horizontal direction (691), respectively. The first horizontal line and the second horizontal line may be arranged in the vertical direction (692). For example, the display driving circuit (121) may perform the scans sequentially performed in the vertical direction (692) by performing a scan in relation to the second horizontal line based on performing a scan in relation to the first horizontal line.

[0117] At least one processor (110) can generate a second image (672) to be displayed on a portion (680) of the display area while displaying a first image on the display area, such as in state (600). At least one processor (110) can transmit the second image (672) to the display driving circuit (121) via the interface (130).

[0118] The display driving circuit (121) can receive a second image (672) from at least one processor (110) via an interface (130). The second image (672) can be received via a vertical synchronization signal (610). The vertical synchronization signal (610) can include a vertical front porch portion (611), a vertical active portion (612), and a vertical back porch portion (613). Since the time at which the second image (672) is received from at least one processor (110) according to the video hybrid mode corresponds to the position of a portion (680) of the display area related to the second image (672), the display driving circuit (121) can identify the position information according to the position of a blank region (614) (e.g., a blanking or low power period (BLLP)) within the vertical active portion (612) of the vertical synchronization signal (610) (or the position of a data region (616) within the vertical active portion (612) of the vertical synchronization signal (610) corresponding to the second image (672). The blank region (614) can be described as a region of the vertical synchronization signal (610) that includes only timing packets. The data region (616) can be described as a region of the vertical synchronization signal (610) that includes timing packets and data packets. For example, the display driving circuit (121) can identify the position information by counting horizontal lines within the display area corresponding to the blank area (614). For example, the display driving circuit (121) can identify the position information by identifying whether there is a data packet for a horizontal line within the vertical active portion (612) following a timing packet for a horizontal line within the vertical active portion (612).

[0119] The display driving circuit (121) can change a part (674) of the first image into a second image (672), such as in state (650), by performing a scan according to the identified location information.

[0120] Referring to FIG. 7, at least one processor (110) and display driving circuit (121) can operate for the video hybrid mode.

[0121] The display panel (122) may have a horizontal direction (691) and a vertical direction (692). The display driving circuit (121) may sequentially perform scans in the horizontal direction (691) for display on the display area of ​​the display panel (122). The scans in the horizontal direction (691) may be sequentially performed in the vertical direction (692). For example, the display area of ​​the display panel (122) may include a first horizontal line and a second horizontal line extending in the horizontal direction (691), respectively. The first horizontal line and the second horizontal line may be arranged in the vertical direction (692). For example, the display driving circuit (121) may perform the scans sequentially performed in the vertical direction (692) by performing a scan in relation to the second horizontal line based on performing a scan in relation to the first horizontal line.

[0122] The display driving circuit (121) can perform a scan with respect to a portion of a horizontal line. The display driving circuit (121) can perform a scan with respect to a portion of a horizontal line and refrain from performing a scan with respect to another portion of the horizontal line. For example, the display driving circuit (121) can perform a scan with respect to a portion of horizontal line (765), which is one of the horizontal lines of the display area of ​​the display panel (122), and skip the scan with respect to at least one other portion of the horizontal line (765).

[0123] At least one processor (110) may generate a second image (772) to be displayed on a portion (780) of the display area while displaying a first image on the display area, such as in a state (700). At least one processor (110) may transmit the second image (772) to the display driving circuit (121) via the interface (130). The transmission of the data may be partial line transmission. The partial line transmission may be performed within (or according to) a non-burst mode. The non-burst mode may be described as a mode in which pixel clock timing corresponds to horizontal position information.

[0124] The display driving circuit (121) can receive a second image (772) from at least one processor (110) via the interface (130). A portion of the second image (772) corresponding to a horizontal line (765) can be received via a horizontal synchronization signal (710). The horizontal synchronization signal (710) can include a horizontal front porch portion (711), a horizontal active portion (712), a horizontal back porch portion (713), and a blank portion (714). Since the time at which the part of the second image (772) is received from at least one processor (110) according to the video hybrid mode corresponds to the position (e.g., the position information) of the part (780) of the display area related to the second image (772) according to the non-burst mode, the display driving circuit (121) can identify the position information according to the position of a blank region (717) (e.g., a blanking or low power period (BLLP)) within the horizontal active portion (712) of the horizontal synchronization signal (710) (or the position of a data region (716) within the horizontal active portion (712) of the horizontal synchronization signal (710) corresponding to the second image (772). For example, the display driving circuit (121) can identify the position information by counting a pixel clock according to the blank region (714).

[0125] The display driving circuit (121) can change a part (774) of the first image into a second image (772), such as in state (750), by performing a scan according to the identified location information.

[0126] Referring to FIG. 8, at least one processor (110) and display driving circuit (121) can operate for the video hybrid mode.

[0127] The display panel (122) may have a horizontal direction (691) and a vertical direction (692). The display driving circuit (121) may sequentially perform scans in the horizontal direction (691) for display on the display area of ​​the display panel (122). The scans in the horizontal direction (691) may be sequentially performed in the vertical direction (692). For example, the display area of ​​the display panel (122) may include a first horizontal line and a second horizontal line extending in the horizontal direction (691), respectively. The first horizontal line and the second horizontal line may be arranged in the vertical direction (692). For example, the display driving circuit (121) may perform the scans sequentially performed in the vertical direction (692) by performing a scan in relation to the second horizontal line based on performing a scan in relation to the first horizontal line.

[0128] The display driving circuit (121) may perform a scan with respect to a portion of a horizontal line. The display driving circuit (121) may perform a scan with respect to a portion of a horizontal line and refrain from performing a scan with respect to another portion of the horizontal line.

[0129] At least one processor (110) may generate a second image (772) to be displayed on a portion (780) of the display area while displaying a first image on the display area, such as in a state (700). At least one processor (110) may transmit the second image (772) to the display driving circuit (121) via the interface (130). The transmission of the data may be a partial line transmission. The partial line transmission may be performed within (or according to) a burst mode. The burst mode may be described as a mode in which pixel clock timing does not correspond to horizontal position information.

[0130] The display driving circuit (121) can receive a second image (772) from at least one processor (110) via the interface (130). A portion of the second image (772) corresponding to a horizontal line (765) can be received via a horizontal synchronization signal (710). The horizontal synchronization signal (710) can include a horizontal front porch portion (711), a horizontal active portion (712), a horizontal back porch portion (713), and a blank portion (714). Since the time at which the portion of the second image (772) is received from the at least one processor (110) according to the video hybrid mode does not correspond to a position (e.g., the position information) of a portion (780) of the display area associated with the second image (772) according to the burst mode, the at least one processor (110) can transmit the position information to the display driving circuit (121) prior to the horizontal synchronization signal (710). The above location information may be transmitted to indicate the location of a portion (780) of the display area corresponding to a data area (816) within a horizontal active portion (712) of a horizontal synchronization signal (710).

[0131] The display driving circuit (121) can use the position information to identify that the second image (772) acquired through the data area (816) within the horizontal active portion (712) corresponds to a portion (780) of the display area. The display driving circuit (121) can change a portion (774) of the first image into the second image (772) by performing a scan according to the identification.

[0132] As a non-limiting example, the display driving circuit (121) may be in a state for lower power consumption through the blank area (817) of the horizontal active portion (712) of the horizontal synchronization signal (710) and / or the blank area (714) of the horizontal synchronization signal (710). Since the blank area (817) and the blank area (714) of the horizontal synchronization signal (710) are continuous according to the burst mode, the display driving circuit (121) may reduce power consumption for display on the display panel (122) through the burst mode.

[0133] The operations described above can be executed within the electronic device (901) of FIGS. 9 and 10.

[0134] FIG. 9 is a block diagram of an electronic device (901) within a network environment (900) according to various embodiments. Referring to FIG. 9, in the network environment (900), the electronic device (901) may communicate with the electronic device (902) via a first network (998) (e.g., a short-range wireless communication network), or may communicate with at least one of the electronic device (904) or the server (908) via a second network (999) (e.g., a long-range wireless communication network). In one embodiment, the electronic device (901) may communicate with the electronic device (904) via the server (908). According to one embodiment, the electronic device (901) may include a processor (920), a memory (930), an input module (950), an audio output module (955), a display module (960), an audio module (970), a sensor module (976), an interface (977), a connection terminal (978), a haptic module (979), a camera module (980), a power management module (988), a battery (989), a communication module (990), a subscriber identification module (996), or an antenna module (997). In some embodiments, the electronic device (901) may omit at least one of these components (e.g., the connection terminal (978)), or may have one or more other components added. In some embodiments, some of these components (e.g., the sensor module (976), the camera module (980), or the antenna module (997)) may be integrated into one component (e.g., the display module (960)).

[0135] The processor (920) may, for example, execute software (e.g., a program (940)) to control at least one other component (e.g., a hardware or software component) of the electronic device (901) connected to the processor (920) and perform various data processing or operations. According to one embodiment, as at least a part of the data processing or operations, the processor (920) may store commands or data received from other components (e.g., a sensor module (976) or a communication module (990)) in a volatile memory (932), process the commands or data stored in the volatile memory (932), and store result data in a non-volatile memory (934). According to one embodiment, the processor (920) may include a main processor (921) (e.g., a central processing unit or an application processor) or an auxiliary processor (923) (e.g., a graphics processing unit, a neural processing unit (NPU), an image signal processor, a sensor hub processor, or a communication processor) that can operate independently or together with the main processor (921). For example, when the electronic device (901) includes the main processor (921) and the auxiliary processor (923), the auxiliary processor (923) may be configured to use less power than the main processor (921) or to be specialized for a given function. The auxiliary processor (923) may be implemented separately from the main processor (921) or as a part thereof.

[0136] The auxiliary processor (923) may control at least a portion of functions or states associated with at least one component (e.g., a display module (960), a sensor module (976), or a communication module (990)) of the electronic device (901), for example, on behalf of the main processor (921) while the main processor (921) is in an inactive (e.g., sleep) state, or together with the main processor (921) while the main processor (921) is in an active (e.g., application execution) state. In one embodiment, the auxiliary processor (923) (e.g., an image signal processor or a communication processor) may be implemented as a part of another functionally related component (e.g., a camera module (980) or a communication module (990)). In one embodiment, the auxiliary processor (923) (e.g., a neural network processing unit) may include a hardware structure specialized for processing artificial intelligence models. The artificial intelligence models may be generated through machine learning. This learning can be performed, for example, on the electronic device (901) itself where the artificial intelligence model is executed, or can be performed through a separate server (e.g., server (908)). The learning algorithm can include, for example, supervised learning, unsupervised learning, semi-supervised learning, or reinforcement learning, but is not limited to the examples described above. The artificial intelligence model can include multiple artificial neural network layers.The artificial neural network may be one of a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), a restricted Boltzmann machine (RBM), a deep belief network (DBN), a bidirectional recurrent deep neural network (BRDNN), a deep Q-network, or a combination of two or more of the above, but is not limited to the examples described above. In addition to, or alternatively to, a hardware structure, an artificial intelligence model may include a software structure.

[0137] The memory (930) can store various data used by at least one component (e.g., the processor (920) or the sensor module (976)) of the electronic device (901). The data can include, for example, software (e.g., the program (940)) and input data or output data for commands related thereto. The memory (930) can include a volatile memory (932) or a non-volatile memory (934).

[0138] The program (940) may be stored as software in the memory (930) and may include, for example, an operating system (942), middleware (944), or an application (946).

[0139] The input module (950) can receive commands or data to be used in a component of the electronic device (901) (e.g., a processor (920)) from an external source (e.g., a user) of the electronic device (901). The input module (950) can include, for example, a microphone, a mouse, a keyboard, a key (e.g., a button), or a digital pen (e.g., a stylus pen).

[0140] The audio output module (955) can output audio signals to the outside of the electronic device (901). The audio output module (955) can include, for example, a speaker or a receiver. The speaker can be used for general purposes, such as multimedia playback or recording playback. The receiver can be used to receive incoming calls. In one embodiment, the receiver can be implemented separately from the speaker or as part of the speaker.

[0141] The display module (960) can visually provide information to an external party (e.g., a user) of the electronic device (901). The display module (960) may include, for example, a display, a holographic device, or a projector and a control circuit for controlling the device. In one embodiment, the display module (960) may include a touch sensor configured to detect a touch, or a pressure sensor configured to measure the intensity of a force generated by the touch.

[0142] The audio module (970) can convert sound into an electrical signal, or vice versa, convert an electrical signal into sound. According to one embodiment, the audio module (970) can acquire sound through the input module (950), output sound through the sound output module (955), or an external electronic device (e.g., electronic device (902)) (e.g., speaker or headphone) directly or wirelessly connected to the electronic device (901).

[0143] The sensor module (976) can detect the operating status (e.g., power or temperature) of the electronic device (901) or the external environmental status (e.g., user status) and generate an electrical signal or data value corresponding to the detected status. According to one embodiment, the sensor module (976) can include, for example, a gesture sensor, a gyro sensor, a barometric pressure sensor, a magnetic sensor, an acceleration sensor, a grip sensor, a proximity sensor, a color sensor, an IR (infrared) sensor, a biometric sensor, a temperature sensor, a humidity sensor, or an illuminance sensor.

[0144] The interface (977) may support one or more designated protocols that may be used to directly or wirelessly connect the electronic device (901) with an external electronic device (e.g., the electronic device (902)). In one embodiment, the interface (977) may include, for example, a high definition multimedia interface (HDMI), a universal serial bus (USB) interface, an SD card interface, or an audio interface.

[0145] The connection terminal (978) may include a connector through which the electronic device (901) may be physically connected to an external electronic device (e.g., the electronic device (902)). In one embodiment, the connection terminal (978) may include, for example, an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

[0146] The haptic module (979) can convert electrical signals into mechanical stimuli (e.g., vibration or movement) or electrical stimuli that a user can perceive through tactile or kinesthetic sensations. According to one embodiment, the haptic module (979) can include, for example, a motor, a piezoelectric element, or an electrical stimulation device.

[0147] The camera module (980) can capture still images and videos. According to one embodiment, the camera module (980) may include one or more lenses, image sensors, image signal processors, or flashes.

[0148] The power management module (988) can manage the power supplied to the electronic device (901). According to one embodiment, the power management module (988) can be implemented as, for example, at least a part of a power management integrated circuit (PMIC).

[0149] A battery (989) may power at least one component of the electronic device (901). In one embodiment, the battery (989) may include, for example, a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell.

[0150] The communication module (990) may support the establishment of a direct (e.g., wired) communication channel or a wireless communication channel between the electronic device (901) and an external electronic device (e.g., electronic device (902), electronic device (904), or server (908)), and the performance of communication through the established communication channel. The communication module (990) may operate independently from the processor (920) (e.g., application processor) and may include one or more communication processors that support direct (e.g., wired) communication or wireless communication. According to one embodiment, the communication module (990) may include a wireless communication module (992) (e.g., a cellular communication module, a short-range wireless communication module, or a global navigation satellite system (GNSS) communication module) or a wired communication module (994) (e.g., a local area network (LAN) communication module, or a power line communication module). Any of these communication modules may communicate with an external electronic device (904) via a first network (998) (e.g., a short-range communication network such as Bluetooth, wireless fidelity (WiFi) direct, or infrared data association (IrDA)) or a second network (999) (e.g., a long-range communication network such as a legacy cellular network, a 5G network, a next-generation communication network, the Internet, or a computer network (e.g., a LAN or WAN)). These various types of communication modules may be integrated into a single component (e.g., a single chip) or implemented as multiple separate components (e.g., multiple chips). The wireless communication module (992) may use subscriber information (e.g., an international mobile subscriber identity (IMSI)) stored in the subscriber identification module (996) to verify or authenticate the electronic device (901) within a communication network such as the first network (998) or the second network (999).

[0151] The wireless communication module (992) can support 5G networks and next-generation communication technologies following the 4G network, such as NR access technology (new radio access technology). The NR access technology can support high-speed transmission of high-capacity data (eMBB (enhanced mobile broadband)), minimization of terminal power and connection of multiple terminals (mMTC (massive machine type communications)), or high reliability and low latency communications (URLLC (ultra-reliable and low-latency communications)). The wireless communication module (992) can support, for example, a high-frequency band (e.g., mmWave band) to achieve a high data transmission rate. The wireless communication module (992) may support various technologies for securing performance in a high-frequency band, such as beamforming, massive multiple-input and multiple-output (MIMO), full dimensional MIMO (FD-MIMO), array antenna, analog beam-forming, or large scale antenna. The wireless communication module (992) may support various requirements specified in the electronic device (901), an external electronic device (e.g., the electronic device (904)), or a network system (e.g., the second network (999)). According to one embodiment, the wireless communication module (992) can support a peak data rate (e.g., 20 Gbps or more) for eMBB realization, a loss coverage (e.g., 164 dB or less) for mMTC realization, or a U-plane latency (e.g., 0.5 ms or less for downlink (DL) and uplink (UL), or 1 ms or less for round trip) for URLLC realization.

[0152] The antenna module (997) can transmit or receive signals or power to or from an external device (e.g., an external electronic device). In one embodiment, the antenna module (997) may include an antenna including a radiator formed of a conductor or a conductive pattern formed on a substrate (e.g., a PCB). In one embodiment, the antenna module (997) may include a plurality of antennas (e.g., an array antenna). In this case, at least one antenna suitable for a communication method used in a communication network, such as the first network (998) or the second network (999), may be selected from the plurality of antennas, for example, by the communication module (990). A signal or power may be transmitted or received between the communication module (990) and the external electronic device via the at least one selected antenna. In some embodiments, in addition to the radiator, another component (e.g., a radio frequency integrated circuit (RFIC)) may be additionally formed as a part of the antenna module (997).

[0153] According to various embodiments, the antenna module (997) may form a mmWave antenna module. In one embodiment, the mmWave antenna module may include a printed circuit board, an RFIC disposed on or adjacent a first side (e.g., a bottom side) of the printed circuit board and capable of supporting a designated high frequency band (e.g., a mmWave band), and a plurality of antennas (e.g., an array antenna) disposed on or adjacent a second side (e.g., a top side or a side side) of the printed circuit board and capable of transmitting or receiving signals in the designated high frequency band.

[0154] At least some of the above components can be interconnected and exchange signals (e.g., commands or data) with each other via a communication method between peripheral devices (e.g., a bus, GPIO (general purpose input and output), SPI (serial peripheral interface), or MIPI (mobile industry processor interface)).

[0155] According to one embodiment, commands or data may be transmitted or received between the electronic device (901) and an external electronic device (904) via a server (908) connected to a second network (999). Each of the external electronic devices (902 or 904) may be the same or a different type of device as the electronic device (901). According to one embodiment, all or part of the operations executed in the electronic device (901) may be executed in one or more of the external electronic devices (902, 904, or 908). For example, when the electronic device (901) is to perform a certain function or service automatically or in response to a request from a user or another device, the electronic device (901) may, instead of or in addition to executing the function or service itself, request one or more external electronic devices to perform the function or at least a part of the service. One or more external electronic devices that receive the request may execute at least a portion of the requested function or service, or an additional function or service related to the request, and transmit the result of the execution to the electronic device (901). The electronic device (901) may process the result as is or additionally and provide it as at least a portion of a response to the request. For this purpose, cloud computing, distributed computing, mobile edge computing (MEC), or client-server computing technology may be used, for example. The electronic device (901) may provide an ultra-low latency service by using distributed computing or mobile edge computing, for example. In one embodiment, the external electronic device (904) may include an Internet of Things (IoT) device. The server (908) may be an intelligent server utilizing machine learning and / or a neural network. According to one embodiment, the external electronic device (904) or the server (908) may be included in the second network (999).The electronic device (901) can be applied to intelligent services (e.g., smart home, smart city, smart car, or healthcare) based on 5G communication technology and IoT-related technology.

[0156] FIG. 10 is a block diagram (1000) of a display module (960) according to various embodiments. Referring to FIG. 10, the display module (960) may include a display (1010) and a display driver IC (DDI) (1030) for controlling the display (1010). The DDI (1030) may include an interface module (1031), a memory (1033) (e.g., a buffer memory), an image processing module (1035), or a mapping module (1037). The DDI (1030) may receive image information including, for example, image data or an image control signal corresponding to a command for controlling the image data, from another component of the electronic device (901) through the interface module (1031). For example, according to one embodiment, image information may be received from a processor (920) (e.g., a main processor (921) (e.g., an application processor)) or an auxiliary processor (923) (e.g., a graphics processing unit) that operates independently of the function of the main processor (921). The DDI (1030) may communicate with a touch circuit (1050) or a sensor module (976) through the interface module (1031). In addition, the DDI (1030) may store at least a portion of the received image information in the memory (1033), for example, on a frame basis. The image processing module (1035) may, for example, perform preprocessing or postprocessing (e.g., resolution, brightness, or size adjustment) on at least a portion of the image data based at least on characteristics of the image data or characteristics of the display (1010). The mapping module (1037) may generate a voltage value or a current value corresponding to the image data that has been preprocessed or postprocessed through the image processing module (1035).According to one embodiment, the generation of voltage values ​​or current values ​​may be performed at least in part based on, for example, properties of pixels of the display (1010) (e.g., arrangement of pixels (RGB stripe or pentile structure), or size of each sub-pixel). At least some pixels of the display (1010) may be driven at least in part based on, for example, the voltage values ​​or current values, so that visual information (e.g., text, images, or icons) corresponding to the image data may be displayed through the display (1010).

[0157] According to one embodiment, the display module (960) may further include a touch circuit (1050). The touch circuit (1050) may include a touch sensor (1051) and a touch sensor IC (1053) for controlling the same. The touch sensor IC (1053) may control the touch sensor (1051) to detect, for example, a touch input or a hovering input for a specific location of the display (1010). For example, the touch sensor IC (1053) may detect a touch input or a hovering input by measuring a change in a signal (e.g., voltage, light quantity, resistance, or charge quantity) for a specific location of the display (1010). The touch sensor IC (1053) may provide information (e.g., location, area, pressure, or time) regarding the detected touch input or hovering input to the processor (920). According to one embodiment, at least a portion of the touch circuit (1050) (e.g., touch sensor IC (1053)) may be included as part of the display driver IC (1030), or as part of the display (1010), or as part of another component (e.g., auxiliary processor (923)) disposed external to the display module (960).

[0158] According to one embodiment, the display module (960) may further include at least one sensor (e.g., a fingerprint sensor, an iris sensor, a pressure sensor, or an illuminance sensor) of the sensor module (976), or a control circuit therefor. In this case, the at least one sensor or the control circuit therefor may be embedded in a part of the display module (960) (e.g., the display (1010) or the DDI (1030)) or a part of the touch circuit (1050). For example, when the sensor module (976) embedded in the display module (960) includes a biometric sensor (e.g., a fingerprint sensor), the biometric sensor may obtain biometric information (e.g., a fingerprint image) associated with a touch input through a part of the display (1010). For another example, if the sensor module (976) embedded in the display module (960) includes a pressure sensor, the pressure sensor may obtain pressure information associated with a touch input through a portion or the entire area of ​​the display (1010). According to one embodiment, the touch sensor (1051) or the sensor module (976) may be disposed between pixels of a pixel layer of the display (1010), or above or below the pixel layer.

[0159] The technical problems to be achieved in the present disclosure are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by a person having ordinary knowledge in the technical field to which the present disclosure pertains.

[0160] As described above, an electronic device (e.g., electronic device (100)) may include at least one processor (e.g., at least one processor (110)) including a processing circuit, a display driving circuit (e.g., display driving circuit (121)) including a memory (e.g., GRAM (124)), and a display panel (e.g., display panel (122)). The display driving circuit may be configured to receive first image data from the at least one processor within a first portion of a time interval corresponding to one frame, and display a first image through the first portion of the display panel based on the first image data received from the at least one processor, and to acquire, within a second portion of the time interval, second image data stored in the memory before the time interval from the memory, and to display a second image through the second portion of the display panel based on the second image data acquired from the memory.

[0161] The display driving circuit may be configured to store the first image data received from the at least one processor in a first area of ​​the memory, and scan the first image data received from the at least one processor, within the first portion of the time interval.

[0162] The display driving circuit may be configured to refrain from storing the first image data received from the at least one processor in the memory within the first portion of the time interval, and to scan the first image data received from the at least one processor.

[0163] The display driving circuit may be configured to scan the second image data obtained from the memory within the second portion of the time interval.

[0164] The display driving circuit may be configured to refrain from scanning the image data within a third portion of the time interval that is different from the first portion of the time interval and the second portion of the time interval.

[0165] As described above, an electronic device (e.g., electronic device (100)) may include at least one processor (e.g., at least one processor (110)) including a processing circuit, a display driving circuit (e.g., display driving circuit (121)) including a memory (e.g., GRAM (124)), and a display panel (e.g., display panel (122)). The display driving circuit may be configured to receive first image data from the at least one processor within a first portion of a time interval corresponding to one frame, store the first image data received from the at least one processor in a first area of ​​the memory, and display a first image through a first portion of the display panel based on the first image data received from the at least one processor, and to receive second image data from the at least one processor within a second portion of the time interval, refrain from storing the second image data received from the at least one processor in the memory, and display a second image through a second portion of the display panel based on the second image data.

[0166] The display driving circuit may be configured to refrain from scanning image data within a third portion of the time interval that is different from the first portion of the time interval and the second portion of the time interval.

[0167] The display driving circuit may be configured to, within a third portion of the time interval, acquire third image data stored in the memory before the time interval from the memory, and display a third image through the third portion of the display panel based on the third image data acquired from the memory.

[0168] As described above, an electronic device (e.g., electronic device (100)) may include at least one processor (e.g., at least one processor (110)) including a processing circuit, a display driving circuit (e.g., display driving circuit (121)) including a graphic random access memory (GRAM) (e.g., GRAM (124)), and a display panel (e.g., display panel (122)). The display driving circuit may be configured to receive, from the at least one processor, a first image to be displayed through a first portion of the display panel via a vertical synchronization signal, scan the first image received from the at least one processor to display the first image through the first portion of the display panel within a first portion of a time interval corresponding to the vertical synchronization signal, and store the first image received from the at least one processor in a first area of ​​the GRAM, obtain, from the GRAM, a second image stored in a second area of ​​the GRAM before receiving the first image, and scan the second image obtained from the GRAM to display the second image through the second portion of the display panel.

[0169] The display driving circuit may be configured to further receive, from the at least one processor, a third image to be displayed through a third portion of the display panel via the vertical synchronization signal, scan the third image received from the at least one processor to display the third image through the third portion of the display panel within the third portion of the time interval, and refrain from storing the third image received from the at least one processor in a third area of ​​the GRAM.

[0170] The display driving circuit may be configured to store the first image in the first area of ​​the GRAM within the first portion of the time interval based on a first command received from the at least one processor in relation to the first image, and to refrain from storing the third image in the third area of ​​the GRAM within the third portion of the time interval based on a second command received from the at least one processor in relation to the third image. The second image may be stored in the second area of ​​the GRAM based on the first command received from the at least one processor in relation to the second image.

[0171] The display driving circuit may be configured to refrain from performing a scan with respect to a third portion of the display panel within a third portion of the time interval.

[0172] The third image displayed on the display panel before receiving the first image may be maintained within the time period.

[0173] The display driving circuit may be configured to identify the first portion of the time interval based on a timing at which the first image is received.

[0174] The display driving circuit may be configured to receive, before receiving the first image, position information of the first part of the display panel on which the first image is to be displayed, from the at least one processor, and identify the first part of the time interval based on the position information.

[0175] The display driving circuit may include a first path to the display panel, bypassing the GRAM, and a second path to an input terminal of the GRAM.

[0176] The first path may be available for scanning an image received from the at least one processor by bypassing the GRAM, and the second path may be available for storing the image received from the at least one processor in the GRAM while scanning the image received from the at least one processor.

[0177] The above display driving circuit may include a third path from the output terminal of the GRAM to the display panel.

[0178] The display driving circuit may be configured to scan the first image by providing the first image to the display panel via the first path within the first portion of the time interval, and to scan the second image by providing the second image to the display panel from the GRAM via the third path within the second portion of the time interval.

[0179] The display driving circuit may include a first path to the display panel, bypassing the GRAM, and a second path to an input terminal of the GRAM. The display driving circuit may be configured to further receive, from the at least one processor, a third image to be displayed on a third portion of the display panel via the vertical synchronization signal, scan the third image received from the at least one processor to display the third image via the third portion of the display panel within a third portion of the time interval, and refrain from storing the third image received from the at least one processor in a third area of ​​the GRAM while scanning the third image. Scanning the third image may be performed by providing the third image to the display panel via the first path, and storing the third image may be refrained from by disabling the second path.

[0180] As described above, an electronic device (e.g., electronic device (100)) may include at least one processor (e.g., at least one processor (110)) including a processing circuit, a display driving circuit (e.g., display driving circuit (121)) including a graphic random access memory (GRAM) (e.g., GRAM (124)), and a display panel (e.g., display panel (122)). The display driving circuit may be configured to receive, from the at least one processor, a first image to be displayed through a first portion of the display panel via a vertical synchronization signal, scan the first image received from the at least one processor to display the first image through the first portion of the display panel within a first portion of a time interval corresponding to the vertical synchronization signal, and refrain from storing the first image received from the at least one processor in a first area of ​​the GRAM, obtain, from the GRAM, the second image stored in a second area of ​​the GRAM before receiving the first image, and scan the second image obtained from the GRAM to display the second image through a second portion of the display panel.

[0181] The display driving circuit may be configured to further receive, from the at least one processor, a third image to be displayed through a third portion of the display panel, via the vertical synchronization signal, scan the third image received from the at least one processor to display the third image through the third portion of the display panel within the third portion of the time interval, and store the third image received from the at least one processor in a third area of ​​the GRAM within the third portion of the time interval.

[0182] The display driving circuit may be configured to refrain from storing the first image based on a second command received from the at least one processor in relation to the first image, and to store the third image while scanning the third image based on a first command received from the at least one processor in relation to the third image. The second image may be stored in the second area of ​​the GRAM based on the first command received from the at least one processor in relation to the second image.

[0183] The display driving circuit may be configured to refrain from performing a scan with respect to a third portion of the display panel within a third portion of the time interval.

[0184] The third image displayed on the display panel before receiving the first image may be maintained within the time period.

[0185] The display driving circuit may include a first path to the display panel, bypassing the GRAM, and a second path to an input terminal of the GRAM.

[0186] As described above, an electronic device (e.g., electronic device (100)) may include at least one processor (e.g., at least one processor (110)) including a processing circuit, a display driving circuit (e.g., display driving circuit (121)) including a graphic random access memory (GRAM) (e.g., GRAM (124)), and a display panel (e.g., display panel (122)). The display driving circuit may be configured to receive, from the at least one processor, a first image to be displayed through a first portion of the display panel and a second image to be displayed through a second portion of the display panel via a vertical synchronization signal, scan the first image received from the at least one processor to display the first image through the first portion of the display panel within a first portion of a time interval corresponding to the vertical synchronization signal, and store the first image received from the at least one processor in a first area of ​​the GRAM, scan the second image received from the at least one processor to display the second image through the second portion of the display panel within a second portion of the time interval, and refrain from storing the second image received from the at least one processor in the second area of ​​the GRAM.

[0187] The display driving circuit may be configured to, within a third portion of the time interval, acquire a third image stored in a third area of ​​the GRAM from the GRAM before receiving the first image and the second image, and scan the third image acquired from the GRAM to display the third image through a third portion of the display panel.

[0188] The effects that can be obtained from the present disclosure are not limited to the effects mentioned above, and other effects that are not mentioned will be clearly understood by a person having ordinary skill in the art to which the present disclosure pertains.

[0189] Electronic devices according to the various embodiments disclosed in this document may take various forms. Electronic devices may include, for example, portable communication devices (e.g., smartphones), computer devices, portable multimedia devices, portable medical devices, cameras, wearable devices, or home appliances. Electronic devices according to the embodiments of this document are not limited to the aforementioned devices.

[0190] The various embodiments of this document and the terminology used therein are not intended to limit the technical features described in this document to specific embodiments, but should be understood to include various modifications, equivalents, or substitutes of the embodiments. In connection with the description of the drawings, similar reference numerals may be used for similar or related components. The singular form of a noun corresponding to an item may include one or more of the items, unless the context clearly indicates otherwise. In this document, each of the phrases "A or B", "at least one of A and B", "at least one of A or B", "A, B, or C", "at least one of A, B, and C", and "at least one of A, B, or C" can include any one of the items listed together in the corresponding phrase among those phrases, or all possible combinations thereof. Terms such as "first," "second," or "first" or "second" may be used merely to distinguish one component from another, and do not limit the components in any other respect (e.g., importance or order). When a component (e.g., a first component) is referred to as "coupled" or "connected" to another (e.g., a second component), with or without the terms "functionally" or "communicatively," it means that the component can be connected to the other component directly (e.g., wired), wirelessly, or through a third component.

[0191] The term "module" used in various embodiments of this document may include a unit implemented in hardware, software, or firmware, and may be used interchangeably with terms such as logic, logic block, component, or circuit. A module may be an integral component, or a minimum unit or part of such a component that performs one or more functions. For example, according to one embodiment, a module may be implemented in the form of an application-specific integrated circuit (ASIC).

[0192] Various embodiments of the present document may be implemented as software (e.g., a program (940)) including one or more instructions stored in a storage medium (e.g., an internal memory (936) or an external memory (938)) readable by a machine (e.g., an electronic device (901)). For example, a processor (e.g., a processor (920)) of the machine (e.g., an electronic device (901)) may call at least one instruction among the one or more instructions stored from the storage medium and execute it. This enables the machine to operate to perform at least one function according to the at least one called instruction. The one or more instructions may include code generated by a compiler or code executable by an interpreter. The machine-readable storage medium may be provided in the form of a non-transitory storage medium. Here, 'non-transitory' simply means that the storage medium is a tangible device and does not contain signals (e.g., electromagnetic waves), and the term does not distinguish between cases where data is stored semi-permanently or temporarily on the storage medium.

[0193] According to one embodiment, the method according to various embodiments disclosed in this document may be provided as included in a computer program product. The computer program product may be traded as a commodity between a seller and a buyer. The computer program product may be distributed in the form of a machine-readable storage medium (e.g., compact disc read-only memory (CD-ROM)), or may be distributed online (e.g., downloaded or uploaded) via an application store (e.g., Play Store™) or directly between two user devices (e.g., smart phones). In the case of online distribution, at least a portion of the computer program product may be temporarily stored or temporarily generated in a machine-readable storage medium, such as the memory of a manufacturer's server, an application store's server, or an intermediary server.

[0194] According to various embodiments, each component (e.g., a module or a program) of the above-described components may include one or more entities, and some of the entities may be separated and placed in other components. According to various embodiments, one or more components or operations of the aforementioned components may be omitted, or one or more other components or operations may be added. Alternatively or additionally, a plurality of components (e.g., a module or a program) may be integrated into a single component. In such a case, the integrated component may perform one or more functions of each of the plurality of components identically or similarly to those performed by the corresponding component among the plurality of components prior to the integration. According to various embodiments, the operations performed by a module, program, or other component may be executed sequentially, in parallel, iteratively, or heuristically, or one or more of the operations may be executed in a different order, omitted, or one or more other operations may be added.

Claims

1. In electronic devices, At least one processor comprising a processing circuit; A display driving circuit including a graphic random access memory (GRAM); and Includes a display panel, The above display driving circuit, Receive a first image to be displayed through a first portion of the display panel from the at least one processor via a vertical synchronization signal; Within a first portion of the time interval corresponding to the above vertical synchronization signal: Scanning the first image received from the at least one processor to display the first image through the first part of the display panel, and Store the first image received from the at least one processor in the first area of ​​the GRAM; and Within the second part of the above time interval: Acquire a second image stored in a second area of ​​the GRAM before receiving the first image from the GRAM, and configured to scan the second image obtained from the GRAM to display the second image through the second part of the display panel; Electronic devices.

2. In claim 1, the display driving circuit, Through the vertical synchronization signal, further receiving a third image to be displayed through a third part of the display panel from the at least one processor; and Within the third part of the above time interval: Scanning the third image received from the at least one processor to display the third image through the third part of the display panel, and configured to refrain from storing the third image received from the at least one processor in the third area of ​​the GRAM, Electronic devices.

3. In claim 2, the display driving circuit, Based on a first command received from the at least one processor in relation to the first image, storing the first image in the first area of ​​the GRAM within the first part of the time interval; and Based on a second command received from the at least one processor in relation to the third image, the third image is configured to be refrained from being stored in the third area of ​​the GRAM within the third part of the time interval, The second image above is, stored in the second area of ​​the GRAM based on the first command received from the at least one processor in relation to the second image; Electronic devices.

4. In claim 1, the display driving circuit, configured to refrain from performing a scan with respect to a third part of the display panel within a third part of the said time interval, Electronic devices.

5. In claim 4, the third image displayed on the display panel before receiving the first image is, Maintained within the above time interval, Electronic devices.

6. In claim 1, the display driving circuit, configured to identify the first part of the time interval based on the timing at which the first image is received, Electronic devices.

7. In claim 1, the display driving circuit, Before receiving the first image, position information of the first part of the display panel on which the first image is to be displayed is received from the at least one processor, Based on the above location information, configured to identify the first part of the time interval, Electronic devices.

8. In claim 1, the display driving circuit, a first path to the display panel, bypassing the GRAM; and including a second path to the input terminal of the above GRAM, Electronic devices.

9. In claim 8, the first path is: available to scan an image received from said at least one processor by bypassing said GRAM, The second path above is, Available for storing the image received from the at least one processor in the GRAM while scanning the image received from the at least one processor, Electronic devices.

10. In claim 8, the display driving circuit, Further comprising a third path from the output terminal of the GRAM to the display panel; Electronic devices.

11. In claim 10, the display driving circuit, Within the first part of the time interval, scanning the first image by providing the first image to the display panel through the first path, and configured to scan the second image by providing the second image from the GRAM to the display panel through the third path within the second part of the time interval; Electronic devices.

12. In claim 1, the display driving circuit, a first path to the display panel, bypassing the GRAM; and Including a second path to the input terminal of the above GRAM, The above display driving circuit, Further receiving a third image to be displayed on a third portion of the display panel from the at least one processor through the vertical synchronization signal, Within the third part of the above time interval: Scanning the third image received from the at least one processor to display the third image through the third part of the display panel, and configured to refrain from storing the third image received from the at least one processor in the third area of ​​the GRAM while scanning the third image, Scanning the above third image, By providing the third image to the display panel through the first path, Saving the third image above is By disabling the second path, Electronic devices.

13. A method of an electronic device including at least one processor, a display driving circuit including a graphic random access memory (GRAM), and a display panel, An operation in which the display driving circuit receives a first image to be displayed through a first part of the display panel from the at least one processor via a vertical synchronization signal; Within a first portion of the time interval corresponding to the above vertical synchronization signal: The display driving circuit scans the first image received from the at least one processor to display the first image through the first part of the display panel, and An operation in which the display driving circuit stores the first image received from the at least one processor in the first area of ​​the GRAM; and Within the second part of the above time interval: Acquire a second image stored in a second area of ​​the GRAM before receiving the first image from the GRAM, and comprising an operation of scanning the second image obtained from the GRAM to display the second image through the second part of the display panel; method.

14. In claim 13, An operation in which the display driving circuit further receives a third image to be displayed through a third part of the display panel from the at least one processor through the vertical synchronization signal; Within the third part of the above time interval: Scanning the third image received from the at least one processor to display the third image through the third part of the display panel, and An operation of refraining from storing the third image received from the at least one processor in the third area of ​​the GRAM, method.

15. In claim 14, An operation in which the display driving circuit stores the first image in the first area of ​​the GRAM within the first part of the time interval based on a first command received from the at least one processor in relation to the first image; An operation in which the display driving circuit refrains from storing the third image in the third area of ​​the GRAM within the third part of the time interval based on a second command received from the at least one processor in relation to the third image, The second image above is, stored in the second area of ​​the GRAM based on the first command received from the at least one processor in relation to the second image; method.

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