Method and apparatus for multiple level envelope tracking using half bridges

Abstract

The disclosure relates to a 5G or 6G communication system for supporting a higher data transmission rate. Methods and systems multiple level envelope tracking using multi half bridges. A power modulator system includes one or more power supply modulators configured to provide a power amplifier drain voltage, each of the one or more power supply modulators including, one or more half bridges including one or more drivers, and one or more logic and dead time adjust circuits. A method includes generating one or more power supply modulators using one or more half bridges, providing power amplifier drain voltage based on the one or more power supply modulators, and setting a dead time set for each of the one or more half bridges using one or more logic and dead time adjust circuits.

Description

METHOD AND APPARATUS FOR MULTIPLE LEVEL ENVELOPE TRACKING USING HALF BRIDGES

[0001] The present disclosure relates generally to wireless communication systems. More specifically, the present disclosure relates to a system and method for multiple level envelope tracking using half bridges.

[0002] Considering the development of wireless communication from generation to generation, the technologies have been developed mainly for services targeting humans, such as voice calls, multimedia services, and data services. Following the commercialization of 5G (5th generation) communication systems, it is expected that the number of connected devices will exponentially grow. Increasingly, these will be connected to communication networks. Examples of connected things may include vehicles, robots, drones, home appliances, displays, smart sensors connected to various infrastructures, construction machines, and factory equipment. Mobile devices are expected to evolve in various form-factors, such as augmented reality glasses, virtual reality headsets, and hologram devices. In order to provide various services by connecting hundreds of billions of devices and things in the 6G (6th generation) era, there have been ongoing efforts to develop improved 6G communication systems. For these reasons, 6G communication systems are referred to as beyond-5G systems.

[0003] 6G communication systems, which are expected to be commercialized around 2030, will have a peak data rate of tera (1,000 giga)-level bit per second (bps) and a radio latency less than 100μsec, and thus will be 50 times as fast as 5G communication systems and have the 1 / 10 radio latency thereof.

[0004] In order to accomplish such a high data rate and an ultra-low latency, it has been considered to implement 6G communication systems in a terahertz (THz) band (for example, 95 gigahertz (GHz) to 3THz bands). It is expected that, due to severer path loss and atmospheric absorption in the terahertz bands than those in mmWave bands introduced in 5G, technologies capable of securing the signal transmission distance (that is, coverage) will become more crucial. It is necessary to develop, as major technologies for securing the coverage, Radio Frequency (RF) elements, antennas, novel waveforms having a better coverage than Orthogonal Frequency Division Multiplexing (OFDM), beamforming and massive Multiple-input Multiple-Output (MIMO), Full Dimensional MIMO (FD-MIMO), array antennas, and multiantenna transmission technologies such as large-scale antennas. In addition, there has been ongoing discussion on new technologies for improving the coverage of terahertz-band signals, such as metamaterial-based lenses and antennas, Orbital Angular Momentum (OAM), and Reconfigurable Intelligent Surface (RIS).

[0005] Moreover, in order to improve the spectral efficiency and the overall network performances, the following technologies have been developed for 6G communication systems: a full-duplex technology for enabling an uplink transmission and a downlink transmission to simultaneously use the same frequency resource at the same time; a network technology for utilizing satellites, High-Altitude Platform Stations (HAPS), and the like in an integrated manner; an improved network structure for supporting mobile base stations and the like and enabling network operation optimization and automation and the like; a dynamic spectrum sharing technology via collision avoidance based on a prediction of spectrum usage; an use of Artificial Intelligence (AI) in wireless communication for improvement of overall network operation by utilizing AI from a designing phase for developing 6G and internalizing end-to-end AI support functions; and a next-generation distributed computing technology for overcoming the limit of UE computing ability through reachable super-high-performance communication and computing resources (such as Mobile Edge Computing (MEC), clouds, and the like) over the network. In addition, through designing new protocols to be used in 6G communication systems, developing mechanisms for implementing a hardware-based security environment and safe use of data, and developing technologies for maintaining privacy, attempts to strengthen the connectivity between devices, optimize the network, promote softwarization of network entities, and increase the openness of wireless communications are continuing.

[0006] It is expected that research and development of 6G communication systems in hyper-connectivity, including person to machine (P2M) as well as machine to machine (M2M), will allow the next hyper-connected experience. Particularly, it is expected that services such as truly immersive eXtended Reality (XR), high-fidelity mobile hologram, and digital replica could be provided through 6G communication systems. In addition, services such as remote surgery for security and reliability enhancement, industrial automation, and emergency response will be provided through the 6G communication system such that the technologies could be applied in various fields such as industry, medical care, automobiles, and home appliances.

[0007] The present disclosure relates to method and apparatus for “Multiple Level Envelope Tracking Using Half Bridges" in a wireless communication system.

[0008] According to an aspect of an exemplary embodiment, there is provided a communication method in a wireless communication system.

[0009] Aspects of the present disclosure provide efficient communication methods in a wireless communication system.

[0010] For a more complete understanding of the present disclosure and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which like reference numerals represent like parts:

[0011] FIG. 1 illustrates an example wireless network according to embodiments of the present disclosure;

[0012] FIG. 2 illustrates an example gNB according to embodiments of the present disclosure;

[0013] FIG. 3 illustrates an example UE according to embodiments of the present disclosure;

[0014] FIG. 4 illustrates a digital envelope tracking system according to embodiments of the present disclosure;

[0015] FIG. 5 illustrates an example block diagram of a half bridge to support multiple level envelope tracking according to embodiments of the present disclosure;

[0016] FIG. 6 illustrates an example block diagram of a switch capacitor voltage divider to support multiple level envelope tracking according to embodiments of the present disclosure;

[0017] FIG. 7 illustrates an example block diagram of a supply voltage modulator to support multiple level envelope tracking according to embodiments of the present disclosure;

[0018] FIG. 8 illustrates an example block diagram of a voltage supply system to support multiple level envelope tracking according to embodiments of the present disclosure;

[0019] FIG. 9 illustrates an example block diagram of a voltage supply system using multi-level supply voltage modulators to support multiple level envelope tracking according to embodiments of the present disclosure; and

[0020] FIG. 10 illustrates an example flow chart of a method for applying multiple level envelope tracking using multi half bridges according to embodiments of the present disclosure.

[0021] FIG. 11 illustrates a block diagram of a user equipment, according to embodiments of the present disclosure.

[0022] FIG. 12 illustrates a block diagram of a base station, according to embodiments of the present disclosure.

[0023] FIG. 13 illustrates a block diagram of a network entity, according to embodiments of the present disclosure.

[0024] The present disclosure relates generally to wireless communication systems and, more specifically, the present disclosure relates to a system and method for multiple level envelope tracking using half bridges.

[0025] In one embodiment, a power modulator system is provided. The power modulator system includes one or more power supply modulators configured to provide a power amplifier drain voltage, each of the one or more power supply modulators including, one or more half bridges including one or more drivers, and one or more logic and dead time adjust circuits.

[0026] In another embodiment, a method is provided. The method includes generating one or more power supply modulators using one or more half bridges, providing power amplifier drain voltage based on the one or more power supply modulators, and setting a dead time set for each of the one or more half bridges.

[0027] In yet another embodiment, an electronic device is provided. The electronic device includes one or more trackers, one or more power amplifiers, and a processor operably coupled to the one or more trackers and the one or more power amplifiers. The processor is configured to cause the electronic device to generate one or more power supply modulators using one or more half bridges, provide power amplifier drain voltage based on the one or more power supply modulators, and set a dead time set for each of the one or more half bridges.

[0028] Hereinafter, embodiments of the disclosure will be described in detail with reference to the accompanying drawings.

[0029] In describing the embodiments, descriptions related to technical contents well-known in the art and not associated directly with the disclosure will be omitted. Such an omission of unnecessary descriptions is intended to prevent obscuring of the main idea of the disclosure and more clearly transfer the main idea.

[0030] For the same reason, in the accompanying drawings, some elements may be exaggerated, omitted, or schematically illustrated. Further, the size of each element does not completely reflect the actual size. In the drawings, identical or corresponding elements are provided with identical reference numerals or different reference numerals.

[0031] The advantages and features of the disclosure and ways to achieve them will be apparent by making reference to embodiments as described below in detail in conjunction with the accompanying drawings. However, the disclosure is not limited to the embodiments set forth below, but may be implemented in various different forms. The following embodiments are provided only to completely disclose the disclosure and inform those skilled in the art of the scope of the disclosure, and the disclosure is defined only by the scope of the appended claims. Throughout the specification, the same or like reference numerals designate the same or like elements. Furthermore, in describing the disclosure, a detailed description of known functions or constitution incorporated herein will be omitted in the case that it is determined that the description may make the subject matter of the disclosure unnecessarily unclear. The terms which will be described below are terms defined in consideration of the functions in the disclosure, and may be different according to users, intentions of the operators, or customs. Therefore, the definitions of the terms should be made based on the contents throughout the specification.

[0032] Herein, it will be understood that each block of the flowchart illustrations, and combinations of blocks in the flowchart illustrations, may be performed based on computer program instructions. These computer program instructions may be loaded collectively onto at least one processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which perform through any one of, or in any combination of, the at least one processor of the computer or other programmable data processing apparatus, create means for performing the functions specified in the flowchart block(s). These computer program instructions may also be stored in a non-transitory computer usable or computer-readable memory that may direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer usable or computer-readable memory produce an article of manufacture including instruction means that perform the function specified in the flowchart block(s). The computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable data processing apparatus to produce a computer executed process such that the instructions that perform on the computer or other programmable data processing apparatus provide steps for executing the functions specified in the flowchart block(s).

[0033] Further, each block may represent a module, segment, or portion of code, which includes one or more executable instructions for executing the specified logical function(s). It should also be noted that in some alternative implementations, the functions noted in the blocks may occur out of the order. For example, two blocks(or functions) shown in succession may in fact be performed substantially concurrently or the blocks may sometimes be performed in the reverse order, depending upon the functionality involved.

[0034] As used in embodiments of the disclosure, a “~unit” may refer to a software element or a hardware element, such as a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC), which performs a predetermined function. However, the term including the word “~unit” does not always have a meaning limited to software or hardware. The “~unit” may be constructed either to be stored in an addressable storage medium or to execute one or more processors. Therefore, the “~unit” includes, for example, software elements, object-oriented software elements, components such as class elements and task elements, processes, functions, properties, procedures, sub-routines, segments of a program code, drivers, firmware, micro-codes, circuits, data, database, data structures, tables, arrays, and parameters. The components and functions provided by the “~unit” may be either combined into a smaller number of components and a “~unit,” or divided into additional components and a “~unit.” Moreover, the components and “~units” may be implemented to reproduce one or more central processing units (CPUs) within a device or a security multimedia card. Further, in the embodiments, the “~unit” may include one or more processors.

[0035] It should be appreciated that the blocks in each flowchart and combinations of the flowcharts may be performed by one or more computer programs which include instructions. The entirety of the one or more computer programs may be stored in a single memory device or the one or more computer programs may be divided with different portions stored in different multiple memory devices.

[0036] Any of the functions or operations described herein can be processed by one processor or a combination of processors. The one processor or the combination of processors is circuitry performing processing and includes circuitry like an application processor (AP, e.g. a CPU), a communication processor (CP, e.g., a modem), a graphics processing unit (GPU), a neural processing unit (NPU) (e.g., an artificial intelligence (AI) chip), a Wi-Fi chip, a Bluetooth® chip, a global positioning system (GPS) chip, a near field communication (NFC) chip, connectivity chips, a sensor controller, a touch controller, a finger-print sensor controller, a display driver integrated circuit (IC), an audio CODEC chip, a universal serial bus (USB) controller, a camera controller, an image processing IC, a microprocessor unit (MPU), a system on chip (SoC), an IC, or the like.

[0037] It will be appreciated that various embodiments of the disclosure according to the claims and description in the specification can be realized in the form of hardware, software or a combination of hardware and software.

[0038] Any such software may be stored in non-transitory computer readable storage media. The non-transitory computer readable storage media store one or more computer programs (software modules), the one or more computer programs include computer-executable instructions that, when executed by one or more processors of an electronic device individually or collectively, cause the electronic device to perform a method of the disclosure.

[0039] Any such software may be stored in the form of volatile or non-volatile storage such as, for example, a storage device like read only memory (ROM), whether erasable or rewritable or not, or in the form of memory such as, for example, random access memory (RAM), memory chips, device or integrated circuits or on an optically or magnetically readable medium such as, for example, a compact disk (CD), digital versatile disc (DVD), magnetic disk or magnetic tape or the like. It will be appreciated that the storage devices and storage media are various embodiments of non-transitory machine-readable storage that are suitable for storing a computer program or computer programs comprising instructions that, when executed, implement various embodiments of the disclosure. Accordingly, various embodiments of the present disclosure may provide a program comprising code for implementing apparatus or a method as claimed in any one of the claims of this specification and a non-transitory machine-readable storage storing such a program.

[0040] Hereinafter, the determination of priority between A and B in the present disclosure may refer to various actions such as selecting the one having a higher priority based on a predefined priority rule and performing an operation corresponding thereto, or omitting or dropping an operation corresponding to the one having a lower priority.

[0041] Hereinafter, "A or B" as described in the present disclosure may be understood as "A and / or B," which may include A, or B, or both A and B.

[0042] In addition, "at least one of A, B, and C" as described in the present disclosure may be understood to include A, or B, or C, or any combination of A, B, and C.

[0043] In addition, "at least one of A, B, or C" as described in the present disclosure may be understood to include A, or B, or C, or any combination of A, B, and C.

[0044] Furthermore, "A / B" as described in the present disclosure may be understood as "A and / or B," which may include A, or B, or both A and B.

[0045] Furthermore, "A, B" as described in the present disclosure may be understood as "A and / or B," which may include A, or B, or both A and B.

[0046] Furthermore, "A and B" as described in the present disclosure may be understood as "A and / or B," which may include A, or B, or both A and B.

[0047] Furthermore, “if condition A and condition B are satisfied,” as described in the present disclosure, may not be limited to a case where both condition A and condition B are satisfied, but may be understood to include a case where either condition A or condition B is individually satisfied, both condition A and condition B are satisfied, or one or more additional conditions are satisfied in combination.

[0048] Furthermore, throughout this disclosure, ordinal terms such as "first," "second," "third," etc., (and similar qualifiers) are used merely to distinguish between different instances, occurrences, configurations, messages, stages, or aspects of elements, operations, or information as described herein. Unless the context clearly dictates otherwise, the use of such ordinal terms does not itself require that the elements, operations, or information distinguished by these terms be structurally different, numerically distinct, or substantively dissimilar. For example, a "first signal" and a "second signal" may refer to instances of the same signal transmitted at different times or containing the same core information despite minor variations, or they may refer to signals with different content or characteristics, depending on the specific context. Similarly, a "first value" and a "second value" may represent the same magnitude but measured or applied in different circumstances, or they may represent different magnitudes. The interpretation should be guided by the specific technical context, function, and relationship described in the relevant portion of the specification and claims.

[0049] Furthermore, the terms “first ~”, “second ~”, etc., as described in the present disclosure with respect to various elements (e.g., information, objects, operation, sequences, or the like), should not limit those elements. These terms may only be intended to distinguish one element from another, and may not be intended to indicate a specific order. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element.

[0050] Furthermore, even if “first ~” and “second ~” are described in the present disclosure, it may be understood that element(s) referred to by “first ~” and “second ~” may be the same or different. For example, in case of element(s) being information, first information and second information may both be same information and, in some cases, are separate and different information.

[0051] In addition, the terms “if ~” and “in case that ~” as used in the disclosure or claims may be interpreted to include the meanings of “when (or upon) ~,” “in response to ~,” “based on ~,” or “according to ~,” and may be used interchangeably with these expressions. In addition, expressions other than those exemplified herein may also be used, as long as they have substantially the same meaning and do not impair the technical features of the present disclosure.

[0052] For example, the physical layer signaling may be referred to as Layer 1 (L1) signaling and may include downlink control information (DCI). In addition, the higher layer signaling may include a medium access control (MAC) control message, a radio resource control (RRC) signaling message, a non-access stratum (NAS) signaling message, or an application layer message. The RRC signaling message may be referred to as L3 (layer 3) signaling. It should be noted, however, that the higher layer signaling is not limited to the aforementioned examples.

[0053] In addition, the term "not perform" as used in the present disclosure or claims may, in context, be understood to mean that the corresponding step is omitted or skipped. Such a term may be replaced with other terms having the same or substantially equivalent meaning.

[0054] In addition, "transmitting a message including A and B" as described in the present disclosure, may be understood as encompassing both (i) transmitting A and B in a single message, and (ii) transmitting A and B separately via multiple messages (e.g., transmitting a first message including A and a second message including B). This interpretation may also apply to messages that include two or more items (e.g., A, B, C), transmitted either together or separately.

[0055] In addition, "transmitting a message including A and transmitting a message including B" may also be interpreted as transmitting a message including A and B in a single message.

[0056] In the specific embodiments of the present disclosure described below, terms or components included in the disclosure may be expressed in singular or plural form depending on the specific embodiments presented. However, such singular or plural expressions are selected appropriately for convenience of description, and the present disclosure is not limited to a singular or plural number of components. A component expressed in the plural form may be implemented as a single component, and a component expressed in the singular form may be implemented as multiple components.

[0057] The drawings or flowcharts described below illustrate exemplary methods that may be implemented according to the principles of the present disclosure, and various modifications may be made to the methods illustrated in the flowcharts of the present disclosure. For example, although illustrated as a series of steps, various steps in each drawing or flowchart may overlap, occur in parallel, occur in a different order, or be repeated. In other examples, any step may be omitted or replaced with another step.

[0058] The methods and apparatuses proposed in the embodiments of the present disclosure are not limited to each embodiment individually, but may also be applied in combination of all or some of the embodiments proposed in the disclosure. Therefore, the embodiments of the present disclosure may be modified and applied without significantly departing from the scope of the present disclosure, as would be understood by those skilled in the art.

[0059] In this case, even if certain wordings are described differently across embodiments, they may be used interchangeably or in substitution or in combination if their underlying concepts are equivalent. For example, for the same or equivalent concept, even if one embodiment uses the expression "A" and another embodiment uses the expression "B", such expressions may be understood interchangeably, in substitution, or in combination.

[0060] The terms used in the following description to refer to access nodes, network entities, messages, interfaces between network entities, various types of identification information, and the like, are provided merely for the convenience of explanation by way of example. Therefore, the present disclosure is not limited to the terms described below, and other terms having equivalent technical meanings may also be used. Such terms may also be interchangeable with terms defined in any 3rd generation partnership project (3GPP) technical specifications (TS) where appropriate.

[0061] Hereinafter, a base station is an entity that allocates resources to terminals, and may be at least one of a gNode B, an eNode B, a Node B, a base station (BS), a wireless access unit, a BS controller, or a node on a network.

[0062] Furthermore, the base station of the present disclosure may include a split architecture comprising a central unit (CU) and a distributed unit (DU). In this structure, the CU is configured to process the higher layers of the control and user planes, while the DU is configured to process lower-layer radio resource functions. The embodiments of the present disclosure may be equally applicable to 5G base station architectures in which such CU and DU functional splits are implemented.

[0063] A terminal may include a UE, a mobile station (MS), a cellular phone, a smartphone, a computer, or a multimedia system capable of performing communication functions.

[0064] In the disclosure, a downlink (DL) refers to a radio link through which a BS transmits a signal to a UE, and an uplink (UL) refers to a radio link through which a UE transmits a signal to a BS.

[0065] Furthermore, hereinafter, 5th generation (5G) mobile communication technologies (e.g., 5G new radio (NR)), 6th generation (6G) mobile communication technologies may be described by way of example, but the embodiments of the present disclosure may also be applied to other communication systems having similar technical backgrounds or channel types. For example, newly evolved mobile communication systems developed after 5G and 6G may be included. Furthermore, based on determinations by those skilled in the art, the embodiments of the present disclosure may also be applied to other communication systems (e.g., Wi-Fi systems) through some modifications without significantly departing from the scope of the present disclosure

[0066] In the following description, the terms physical channel and signal may be used interchangeably with data or control signal. For example, the term physical downlink shared channel (PDSCH) refers to a physical channel through which data is transmitted, but the term PDSCH may also be used to refer to the data itself. That is, in the present disclosure, the expression "transmit a physical channel" may be interpreted as being equivalent to the expression "transmit data or a signal via a physical channel."

[0067] Hereinafter, in the context of the present disclosure, higher layer signaling may refer to signaling corresponding to at least one or any combination of the following: master information block (MIB), system information block (SIB) or SIB M (M = 1, 2, ...), radio resource control (RRC), or medium access control (MAC) control element (CE), or a non-access stratum (NAS) signaling message, or an application layer message. The RRC signaling message may be referred to as L3 (layer 3) signaling.

[0068] In addition, L1 signaling may refer to signaling corresponding to at least one or any combination of signaling techniques using the at least one or any combination of the following physical layer channels or signaling: physical downlink control channel (PDCCH), downlink control information (DCI), user equipment (UE)-specific DCI, group-common DCI, common DCI, scheduling DCI (e.g., DCI used for scheduling downlink or uplink data), non-scheduling DCI (e.g., DCI not used for scheduling downlink or uplink data) physical uplink control channel (PUCCH), or uplink control information (UCI). The L1 signaling message may be referred to as a physical layer signaling.

[0069] Hereinafter, the expression that information is configured by the BS, as used in the present disclosure or claims, may, in context, be understood to mean that the terminal receives the corresponding information from the BS via a physical layer signaling or a higher layer signaling. Such an expression may be replaced with other terms having the same or substantially equivalent meaning.

[0070] Hereinafter, the operational principle of the present disclosure will be described in detail with reference to the accompanying drawings.

[0071] The present application claims priority to U.S. Provisional Patent Application No. 63 / 679,472, filed on August 5, 2024. The contents of the above-identified patent documents are incorporated herein by reference.

[0072] Other technical features may be readily apparent to one skilled in the art from the following figures, descriptions, and claims.

[0073] It may be advantageous to set forth definitions of certain words and phrases used throughout this patent document. The term “couple” and its derivatives refer to any direct or indirect communication between two or more elements, whether or not those elements are in physical contact with one another. The terms “transmit,” “receive,” and “communicate,” as well as derivatives thereof, encompass both direct and indirect communication. The terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation. The term “or” is inclusive, meaning and / or. The phrase “associated with,” as well as derivatives thereof, means to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, have a relationship to or with, or the like. The term “controller” means any device, system, or part thereof that controls at least one operation. Such a controller may be implemented in hardware or a combination of hardware and software and / or firmware. The functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. The phrase “at least one of,” when used with a list of items, means that different combinations of one or more of the listed items may be used, and only one item in the list may be needed. For example, “at least one of: A, B, and C” includes any of the following combinations: A, B, C, A and B, A and C, B and C, and A and B and C.

[0074] Moreover, various functions described below can be implemented or supported by one or more computer programs, each of which is formed from computer readable program code and embodied in a computer readable medium. The terms “application” and “program” refer to one or more computer programs, software components, sets of instructions, procedures, functions, objects, classes, instances, related data, or a portion thereof adapted for implementation in a suitable computer readable program code. The phrase “computer readable program code” includes any type of computer code, including source code, object code, and executable code. The phrase “computer readable medium” includes any type of medium capable of being accessed by a computer, such as read only memory (ROM), random access memory (RAM), a hard disk drive, a compact disc (CD), a digital video disc (DVD), or any other type of memory. A “non-transitory” computer readable medium excludes wired, wireless, optical, or other communication links that transport transitory electrical or other signals. A non-transitory computer readable medium includes media where data can be permanently stored and media where data can be stored and later overwritten, such as a rewritable optical disc or an erasable memory device.

[0075] Definitions for other certain words and phrases are provided throughout this patent document. Those of ordinary skill in the art should understand that in many if not most instances, such definitions apply to prior as well as future uses of such defined words and phrases.

[0076] FIG. 1 through FIG. 13, discussed below, and the various embodiments used to describe the principles of the present disclosure in this patent document are by way of illustration only and should not be construed in any way to limit the scope of the disclosure. Those skilled in the art will understand that the principles of the present disclosure may be implemented in any suitably arranged system or device.

[0077] As introduced above, power amplifiers typically consume the majority of the power budget of the base station. Moreover, their power-added efficiency (PAE), the main performance metric of a power amplifier, is often as low as 20%. The lower PAE is indicative of wasted power that contributes significantly to thermal concerns and increases the operational expenditure costs of a system. Additionally, the PAE tends to be lower for higher RF frequencies, further exacerbating the challenge for 6G design where Frequency Range 3 upper mid-band is being considered.

[0078] Digital envelope tracking (DET) improves the PAE of a power amplifier by reducing the bias voltage whenever possible. In a DET system, the power tracking and envelope tracking modulator is a DC power modulator that modulates the power amplifier drain supply by following the power and envelope of a baseband signal. In particular, the modulator is usually a DC switch supply or power digital-to-analog converter (DAC) to achieve multi-level DC supply. The 8-level power DAC, however, may need four individual DC power supply, and an 8-level DC switch supply may need eight individual DC supplies. This creates conflict and increases implementation cost related to DC supply. Additionally, the amount of DC supplies needed increase the difficulty of setting a dead time needed to protect the switch circuits from damage (e.g., from being burned).

[0079] The present disclosure provides systems and methods for multiple level envelope tracking using multi half bridges. As described herein, the present disclosure includes a system that uses one or more half bridges to generate one or more power supply modulators with multiple levels. The power supply modulator is generated to have an even-numbered integer (e.g., 2, 4, 6, 8, 10, 12, etc.) level and an output power in an inclusive range between 0.5 W and 1000 W. Additionally, the present disclosure allows for a dead time to be set for each half bridge to avoid burning a field-effect transistor (FET).

[0080] To meet the demand for wireless data traffic having increased since deployment of 4G communication systems and to enable various vertical applications, 5G / NR communication systems have been developed and are currently being deployed. The 5G / NR communication system is considered to be implemented in higher frequency (mmWave) bands, e.g., 28 GHz or 60GHz bands, so as to accomplish higher data rates or in lower frequency bands, such as 6 GHz, to enable robust coverage and mobility support. To decrease propagation loss of the radio waves and increase the transmission distance, the beamforming, massive multiple-input multiple-output (MIMO), full dimensional MIMO (FD-MIMO), array antenna, an analog beam forming, large scale antenna techniques are discussed in 5G / NR communication systems.

[0081] In addition, in 5G / NR communication systems, development for system network improvement is under way based on advanced small cells, cloud radio access networks (RANs), ultra-dense networks, device-to-device (D2D) communication, wireless backhaul, moving network, cooperative communication, coordinated multi-points (CoMP), reception-end interference cancelation and the like.

[0082] The discussion of 5G systems and frequency bands associated therewith is for reference as certain embodiments of the present disclosure may be implemented in 5G systems. However, the present disclosure is not limited to 5G systems or the frequency bands associated therewith, and embodiments of the present disclosure may be utilized in connection with any frequency band. For example, aspects of the present disclosure may also be applied to deployment of 5G communication systems, 6G or even later releases which may use terahertz (THz) bands.

[0083] In 6G extreme-MIMO systems, there are likely to be over a thousand power amplifiers in a single base station. These power amplifiers typically consume the majority of the power budget of the base station. Moreover, their power-added efficiency (PAE), the main performance metric of a power amplifier, is often as low as 20%. The lower PAE is indicative of wasted power that contributes significantly to thermal concerns and increases the operational expenditure costs of a system. To address this, digital envelope tracking is used to improve power efficiency at different power backoff levels. However, the amount of power supplies required by the digital envelope tracking system complicate implementation in large MIMO systems.

[0084] Accordingly, there is a need for systems and methods for improved envelope tracking systems that overcome these challenges.

[0085] FIGS. 1-3 below describe various embodiments implemented in wireless communications systems and with the use of orthogonal frequency division multiplexing (OFDM) or orthogonal frequency division multiple access (OFDMA) communication techniques. The descriptions of FIGS. 1-3 are not meant to imply physical or architectural limitations to the manner in which different embodiments may be implemented. Different embodiments of the present disclosure may be implemented in any suitably arranged communications system.

[0086] FIG. 1 illustrates an example wireless network according to embodiments of the present disclosure. The embodiment of the wireless network shown in FIG. 1 is for illustration only. Other embodiments of the wireless network 100 could be used without departing from the scope of this disclosure.

[0087] As shown in FIG. 1, the wireless network includes a gNB 101 (e.g., base station, BS), a gNB 102, and a gNB 103. The gNB 101 communicates with the gNB 102 and the gNB 103. The gNB 101 also communicates with at least one network 130, such as the Internet, a proprietary Internet Protocol (IP) network, or other data network.

[0088] The gNB 102 provides wireless broadband access to the network 130 for a first plurality of user equipments (UEs) within a coverage area 120 of the gNB 102. The first plurality of UEs includes a UE 111, which may be located in a small business; a UE 112, which may be located in an enterprise; a UE 113, which may be a WiFi hotspot; a UE 114, which may be located in a first residence; a UE 115, which may be located in a second residence; and a UE 116, which may be a mobile device, such as a cell phone, a wireless laptop, a wireless PDA, or the like. The gNB 103 provides wireless broadband access to the network 130 for a second plurality of UEs within a coverage area 125 of the gNB 103. The second plurality of UEs includes the UE 115 and the UE 116. In some embodiments, one or more of the gNBs 101-103 may communicate with each other and with the UEs 111-116 using 5G / NR, long term evolution (LTE), long term evolution-advanced (LTE-A), WiMAX, WiFi, or other wireless communication techniques.

[0089] Depending on the network type, the term “base station” or “BS” can refer to any component (or collection of components) configured to provide wireless access to a network, such as transmit point (TP), transmit-receive point (TRP), an enhanced base station (eNodeB or eNB), a 5G / NR base station (gNB), a macrocell, a femtocell, a WiFi access point (AP), or other wirelessly enabled devices. Base stations may provide wireless access in accordance with one or more wireless communication protocols, e.g., 5G / NR 3rdgeneration partnership project (3GPP) NR, long term evolution (LTE), LTE advanced (LTE-A), high speed packet access (HSPA), Wi-Fi 802.11a / b / g / n / ac, etc. For the sake of convenience, the terms “BS” and “TRP” are used interchangeably in this patent document to refer to network infrastructure components that provide wireless access to remote terminals. Also, depending on the network type, the term “user equipment” or “UE” can refer to any component such as “mobile station,” “subscriber station,” “remote terminal,” “wireless terminal,” “receive point,” or “user device.” For the sake of convenience, the terms “user equipment” and “UE” are used in this patent document to refer to remote wireless equipment that wirelessly accesses a BS, whether the UE is a mobile device (such as a mobile telephone or smartphone) or is normally considered a stationary device (such as a desktop computer or vending machine).

[0090] Dotted lines show the approximate extents of the coverage areas 120 and 125, which are shown as approximately circular for the purposes of illustration and explanation only. It should be clearly understood that the coverage areas associated with gNBs, such as the coverage areas 120 and 125, may have other shapes, including irregular shapes, depending upon the configuration of the gNBs and variations in the radio environment associated with natural and man-made obstructions.

[0091] Although FIG. 1 illustrates one example of a wireless network, various changes may be made to FIG. 1. For example, the wireless network could include any number of gNBs and any number of UEs in any suitable arrangement. Also, the gNB 101 could communicate directly with any number of UEs and provide those UEs with wireless broadband access to the network 130. Similarly, each gNB 102-103 could communicate directly with the network 130 and provide UEs with direct wireless broadband access to the network 130. Further, the gNBs 101, 102, and / or 103 could provide access to other or additional external networks, such as external telephone networks or other types of data networks.

[0092] FIG. 2 illustrates an example gNB 102 according to embodiments of the present disclosure. The embodiment of the gNB 102 illustrated in FIG. 2 is for illustration only, and the gNBs 101 and 103 of FIG. 1 could have the same or similar configuration. However, gNBs come in a wide variety of configurations, and FIG. 2 does not limit the scope of this disclosure to any particular implementation of a gNB.

[0093] As shown in FIG. 2, the gNB 102 includes multiple antennas 205a-205n, multiple transceivers 210a-210n, a controller / processor 225, a memory 230, and a backhaul or network interface 235.

[0094] The transceivers 210a-210n receive, from the antennas 205a-205n, incoming RF signals, such as signals transmitted by UEs in the network 100. The transceivers 210a-210n down-convert the incoming RF signals to generate IF or baseband signals. The IF or baseband signals are processed by receive (RX) processing circuitry in the transceivers 210a-210n and / or controller / processor 225, which generates processed baseband signals by filtering, decoding, and / or digitizing the baseband or IF signals. The controller / processor 225 may further process the baseband signals.

[0095] Transmit (TX) processing circuitry in the transceivers 210a-210n and / or controller / processor 225 receives analog or digital data (such as voice data, web data, e-mail, or interactive video game data) from the controller / processor 225. The TX processing circuitry encodes, multiplexes, and / or digitizes the outgoing baseband data to generate processed baseband or IF signals. The transceivers 210a-210n up-converts the baseband or IF signals to RF signals that are transmitted via the antennas 205a-205n.

[0096] The controller / processor 225 can include one or more processors or other processing devices that control the overall operation of the gNB 102. For example, the controller / processor 225 could control the reception of UL channel signals and the transmission of DL channel signals by the transceivers 210a-210n in accordance with well-known principles. The controller / processor 225 could support additional functions as well, such as more advanced wireless communication functions. For instance, the controller / processor 225 could support beam forming or directional routing operations in which outgoing / incoming signals from / to multiple antennas 205a-205n are weighted differently to effectively steer the outgoing signals in a desired direction. Any of a wide variety of other functions could be supported in the gNB 102 by the controller / processor 225.

[0097] The controller / processor 225 is also capable of executing programs and other processes resident in the memory 230, such as an OS. The controller / processor 225 can move data into or out of the memory 230 as required by an executing process.

[0098] The controller / processor 225 is also coupled to the backhaul or network interface 235. The backhaul or network interface 235 allows the gNB 102 to communicate with other devices or systems over a backhaul connection or over a network. The interface 235 could support communications over any suitable wired or wireless connection(s). For example, when the gNB 102 is implemented as part of a cellular communication system (such as one supporting 5G / NR, LTE, or LTE-A), the interface 235 could allow the gNB 102 to communicate with other gNBs over a wired or wireless backhaul connection. When the gNB 102 is implemented as an access point, the interface 235 could allow the gNB 102 to communicate over a wired or wireless local area network or over a wired or wireless connection to a larger network (such as the Internet). The interface 235 includes any suitable structure supporting communications over a wired or wireless connection, such as an Ethernet or transceiver.

[0099] The memory 230 is coupled to the controller / processor 225. Part of the memory 230 could include a RAM, and another part of the memory 230 could include a Flash memory or other ROM.

[0100] Although FIG. 2 illustrates one example of gNB 102, various changes may be made to FIG. 2. For example, the gNB 102 could include any number of each component shown in FIG. 2. Also, various components in FIG. 2 could be combined, further subdivided, or omitted and additional components could be added according to particular needs.

[0101] FIG. 3 illustrates an example UE 116 according to embodiments of the present disclosure. The embodiment of the UE 116 illustrated in FIG. 3 is for illustration only, and the UEs 111-115 of FIG. 1 could have the same or similar configuration. However, UEs come in a wide variety of configurations, and FIG. 3 does not limit the scope of this disclosure to any particular implementation of a UE.

[0102] As shown in FIG. 3, the UE　116 includes antenna(s) 305, a transceiver(s) 310, and a microphone 320. The UE　116 also includes a speaker 330, a processor 340, an input / output (I / O) interface (IF) 345, an input 350, a display 355, and a memory 360. The memory 360 includes an operating system (OS) 361 and one or more applications 362.

[0103] The transceiver(s) 310 receives, from the antenna 305, an incoming RF signal transmitted by a gNB of the network 100. The transceiver(s) 310 down-converts the incoming RF signal to generate an intermediate frequency (IF) or baseband signal. The IF or baseband signal is processed by RX processing circuitry in the transceiver(s) 310 and / or processor 340, which generates a processed baseband signal by filtering, decoding, and / or digitizing the baseband or IF signal. The RX processing circuitry sends the processed baseband signal to the speaker 330 (such as for voice data) or is processed by the processor 340 (such as for web browsing data).

[0104] TX processing circuitry in the transceiver(s) 310 and / or processor 340 receives analog or digital voice data from the microphone 320 or other outgoing baseband data (such as web data, e-mail, or interactive video game data) from the processor 340. The TX processing circuitry encodes, multiplexes, and / or digitizes the outgoing baseband data to generate a processed baseband or IF signal. The transceiver(s) 310 up-converts the baseband or IF signal to an RF signal that is transmitted via the antenna(s) 305.

[0105] The processor 340 can include one or more processors or other processing devices and execute the OS 361 stored in the memory 360 in order to control the overall operation of the UE 116. For example, the processor 340 could control the reception of DL channel signals and the transmission of UL channel signals by the transceiver(s) 310 in accordance with well-known principles. In some embodiments, the processor 340 includes at least one microprocessor or microcontroller.

[0106] The processor 340 is also capable of executing other processes and programs resident in the memory 360. The processor 340 can move data into or out of the memory 360 as required by an executing process. In some embodiments, the processor 340 is configured to execute the applications 362 based on the OS 361 or in response to signals received from gNBs or an operator. The processor 340 is also coupled to the I / O interface 345, which provides the UE 116 with the ability to connect to other devices, such as laptop computers and handheld computers. The I / O interface 345 is the communication path between these accessories and the processor 340.

[0107] The processor 340 is also coupled to the input 350, which includes for example, a touchscreen, keypad, etc., and the display 355. The operator of the UE 116 can use the input 350 to enter data into the UE 116. The display 355 may be a liquid crystal display, light emitting diode display, or other display capable of rendering text and / or at least limited graphics, such as from web sites.

[0108] The memory 360 is coupled to the processor 340. Part of the memory 360 could include a random-access memory (RAM), and another part of the memory 360 could include a Flash memory or other read-only memory (ROM).

[0109] Although FIG. 3 illustrates one example of UE 116, various changes may be made to FIG. 3. For example, various components in FIG. 3 could be combined, further subdivided, or omitted and additional components could be added according to particular needs. As a particular example, the processor 340 could be divided into multiple processors, such as one or more central processing units (CPUs) and one or more graphics processing units (GPUs). In another example, the transceiver(s) 310 may include any number of transceivers and signal processing chains and may be connected to any number of antennas. Also, while FIG. 3 illustrates the UE 116 configured as a mobile telephone or smartphone, UEs could be configured to operate as other types of mobile or stationary devices.

[0110] The TX processing circuitry of the gNB 101 may also include one or more power amplifiers coupled to one or more digital-to-analog converters and configured to amplify the baseband signal prior to transmission using the antenna. The one or more power amplifiers receive a supply voltage sufficient to cover the signal envelope of the baseband signal, as shown in FIG.　4.

[0111] FIG. 4 illustrates a digital envelope tracking system 400 according to embodiments of the present disclosure. For ease of explanation, the digital envelope tracking system 400 will be described as including one or more components of the wireless network 100 of FIG. 1, such as the gNB 102; however, the digital envelope tracking system 400 could be implemented using any other suitable device or system. The embodiment of the digital envelope tracking system 400 shown in FIG. 4 is for illustration only. Other embodiments of the digital envelope tracking system 400 could be used without departing from the scope of this disclosure.

[0112] As shown in FIG.　4, the digital envelope tracking system 400 includes a level shifter 402 and a bootstrap 404. The level shifter 402 is configured to receive an envelope signal 406 (e.g., from a gNB 102) and level shift the envelope signal 406 before passing it to one or more gate drivers 408. The envelope signal 406 and the one or more gate drivers 408 are configured to receive a driver voltage 410. The signals from the one or more gate drivers 408 are provided to a generator 420 and a tracker 430. The generator may be a switch capacitor voltage divider (SVD) or other suitable voltage divider configured to produce one or more voltages. The generator 420 also receives a first voltage 440 and a second voltage 450. The first voltage 440 is a high voltage and the second voltage 450 is a low voltage, meaning that the first voltage 440 includes a first voltage level and the second voltage includes a second voltage level that is less than the first voltage level of the first voltage 440. The generator 420 uses the first voltage 440 and the second voltage 450 to generate one or more intermediate voltages 422. That is, the generator 420 generates one or more intermediate voltages 422 having voltage levels between the first voltage 440 and the second voltage 450. For example, the generator 420 may generate two intermediate voltages 422 where a first intermediate voltage includes a voltage level of one-third of the difference between the first voltage 440 and the second voltage 450 and a second intermediate voltage includes a voltage level of two-thirds of the difference between the first voltage 440 and the second voltage 450. Alternatively, other intermediate voltage levels may be used, such as non-uniform voltages or more than two intermediate voltages, such as three or more.

[0113] The tracker 430 receives the first voltage 440, the second voltage 450, and the one or more intermediate voltages 422 and provides them to a power amplifier 460. The power amplifier 460 then uses the first voltage 440, the second voltage 450, and the one or more intermediate voltages 422 to amplify an RF signal corresponding to the envelope signal 406 to produce an output signal 462.

[0114] As shown in FIG. 4, the generator 420 includes six switches and the tracker 430 includes four switches. This configuration allows for four voltage levels (e.g., the first voltage 440, the second voltage 450, and two of the one or more intermediate voltages 422) to be provided to the power amplifier 460. For example, two switches are coupled to the first voltage 440 and configured to generate a first of the one or more intermediate voltages 422, an additional two switches are coupled to the first of the one or more intermediate voltages 422 and configured to generate a second of the one or more intermediate voltages 422, and a third set of two switches are coupled between the second of the one or more intermediate voltages 422 and the second voltage 450. Additionally, the each of the four switches of the tracker 430 are configured to receive one of the first voltage 440, the second voltage 450, the first of the one or more intermediate voltages 422, or the second of the one or more intermediate voltages 422. The tracker 430 then determines which of the voltages (e.g., the first voltage 440, the second voltage 450, the first of the one or more intermediate voltages 422, or the second of the one or more intermediate voltages 422) to provide to the power amplifier 460 based on the envelope signal 406.

[0115] Although FIG. 4 illustrates one example of a digital envelope tracking system, various changes may be made to FIG. 4. For example, various components in FIG. 4 could be combined, further subdivided, or omitted and additional components could be added according to particular needs.

[0116] FIG. 5 illustrates an example block diagram of a half bridge 500 to support multiple level envelope tracking according to embodiments of the present disclosure. In particular, the half bridge 500 may be used as one or more of the switches in the generator 420 or the tracker 430 of FIG. 4. The embodiment of the half bridge 500 illustrated in FIG. 5 is for illustration only. Other embodiments of the half bridge 500 could be used without departing from the scope of the present disclosure.

[0117] As shown in FIG. 5, the half bridge 500 includes a first transistor 502, a second transistor 504, a driver 506, a level shifter 508, an isolated buffer amplifier 510, a bootstrap 512, and a low dropout regulator 514. The half bridge 500 uses the first transistor 502 and the second transistor 504, connected in series, to alternate between two states, creating a pulsed output voltage. The pulsed output voltage may include a square wave or pulse width modulated (PWM) waveform that is bipolar, meaning that the waveform oscillates between positive and negative values.

[0118] The first transistor 502 and the second transistor 504 may be any suitable transistors, such as gallium nitride field-effect transistors (GaNFETs) or metal-oxide-semiconductor field-effect transistors (MOSFETs). The current limitation (e.g., the amount of current each transistor is capable of handling) of each of the first transistor 502 and the second transistor 504 determines the holding power of the respective transistor. For example, at any given moment, only one of the first transistor 502 and the second transistor 504 is ON and the other is OFF. Alternatively, the first transistor 502 and the second transistor 504 may both be OFF, but both cannot be ON at same time as the current passing through both will cause damage (e.g., both the first transistor 502 and the second transistor 504 will be broken or burned). As such, a dead time may need to be seat for each of the first transistor 502 and the second transistor 504.

[0119] A pulse width modulation (PWM) power on / off control signal 520 is input into one or more logic and dead time adjust circuits 522, which generate two signals, an upper signal 524 (DTQUP) and a lower signal 526 (DTQLOW) after driver 506.

[0120] The one or more logic and dead time adjust circuits 522 may set a dead time for a half bridge 500 by adjusting the delay between the turn-off signal of the first transistor 502 (e.g., the high-side switch) and the turn-on signal of the second transistor　504 (low-side switch) or vice versa using a dedicated "dead time" setting on the gate driver of the one or more logic and dead time adjust circuits 522 to create a time window where both the first transistor 502 and the second transistor 504 are OFF. The dead time setting may be a predetermined value or may be computed by the one or more logic and dead time adjust circuits 522 based on characteristics of the first transistor 502 and the second transistor 504.

[0121] A bias voltage (VBIAS) 528 is input to a DC supply DC-DC convertor 530 for the logic and dead time adjust circuits 522 and the driver 506. The DC-DC convertor 530 generates two DC supply voltages, a common collector voltage (VCC) 532 and a transistor drain voltage (VDD) 534 with an isolated ground (GND). The VCC 532 relates the GND and the VDD 534 relates to a PGND (Vo), which is floating GND. The isolated buffer amplifier 510 is a buffer amplifier of the positive PWM signals and negative PWM signals of the control signal 520 with an isolated GND (PGND).

[0122] Although FIG. 5 illustrates one example of a half bridge to support multiple level envelope tracking, various changes may be made to FIG. 5. For example, various components in FIG. 5 could be combined, further subdivided, or omitted and additional components could be added according to particular needs.

[0123] FIG. 6 illustrates an example block diagram of a switch capacitor voltage divider (SCVD) 600 to support multiple level envelope tracking according to embodiments of the present disclosure. The embodiment of the SCVD 600 illustrated in FIG. 6 is for illustration only. Other embodiments of the SCVD 600 could be used without departing from the scope of the present disclosure.

[0124] As shown in FIG. 6, the SCVD 600 includes a first half bridge 602, a second half bridge 604, and a fourth half bridge 606. The first half bridge 602, the second half bridge 604, and the fourth half bridge 606 are coupled to each other in series. For example, the first half bridge 602 is coupled to the second half bridge 604 and the second half bridge 604 is coupled to the fourth half bridge 606. The first half bridge 602 and the second half bridge 604 are coupled to a first capacitor 620. Similarly, the second half bridge 604 and the fourth half bridge 606 are coupled to a second capacitor 622. The first capacitor 620 is coupled to a third capacitor 624 and a fourth capacitor 626. The second capacitor 622 is coupled to the fourth capacitor 626 and a fifth capacitor 628.

[0125] Each of the first half bridge 602, the second half bridge 604, and the fourth half bridge 606 receive a clock signal 610 that acts as a control signal (e.g., the control signal 520). The first half bridge 602 receives the first voltage 440 as an input voltage, passes the first voltage 440 through its first transistor or second transistor (e.g., the first transistor 502 or the second transistor 504) and outputs a voltage to charge the first capacitor 620. Similarly, the second half bridge 604 charges the first capacitor 620 and the second capacitor 622 while the fourth half bridge 606 only charges the second capacitor 622. The first capacitor 620 discharges its voltage to charge the third capacitor 624 and the fourth capacitor 626 while the second capacitor 622 discharges its voltage to charge the fourth capacitor 626 and the fifth capacitor 628. The first voltage 440 also charges the third capacitor 624 while the second voltage 450 also charges the fifth capacitor 628. The third capacitor 624 and the fourth capacitor 626 discharge and produce a first intermediate voltage 630 having a voltage value of about two-thirds of the voltage difference between the first voltage 440 and the second voltage 450 above the second voltage 450. Similarly, the fourth capacitor 626 and the fifth capacitor 628 discharge and produce a second intermediate voltage 640 having a voltage value of about one-third of the voltage difference between the first voltage 440 and the second voltage 450. The four voltages (e.g., the first voltage 440, the first intermediate voltage 630, the second intermediate voltage 640, and the second voltage 450) are output to a modulator (e.g., the tracker 430).

[0126] Although FIG. 6 illustrates one example of a switch capacitor voltage divider to support multiple level envelope tracking, various changes may be made to FIG. 6. One or more half bridges,N, may be used to generateN+1 voltage levels in the SCVD, whereNis an odd integer. For example, one half bridge may generate a two-level SCVD and five half bridges may generate a six-level SCVD.

[0127] FIG. 7 illustrates an example block diagram of a supply voltage modulator to support multiple level envelope tracking according to embodiments of the present disclosure. The embodiment of the supply voltage tracker 700 illustrated in FIG. 7 is for illustration only. Other embodiments of the supply voltage tracker 700 could be used without departing from the scope of the present disclosure.

[0128] As shown in FIG. 7, the supply voltage tracker 700 includes a first half bridge 702, a second half bridge 704, and a third half bridge 706. The first half bridge 702 is configured to receive the first voltage 440 and the first intermediate voltage 630. The first half bridge 702 produces a first modulated PA supply voltage 710 and a first modulated signal 730. The third half bridge 706 is configured to receive the second intermediate voltage 640 and the second voltage 450. The third half bridge 706 produces a second modulated PA supply voltage 720 and a first modulated signal 730. The first modulated PA supply voltage 710 and the second modulated PA supply voltage 720 are input into the second half bridge 704. The second half bridge 704 then produces a second modulated signal 740. Both the first modulated signal 730 and the second modulated signal 740 are provided to a power amplifier to generate a DET voltage level. For example, the amplitudes of the first modulated signal 730 and the second modulated signal 740 may be added to produce a desired voltage level. As the first modulated signal 730 and the second modulated signal 740 fluctuate (e.g., due to different pulse widths) the voltage level may decrease or increase based on the envelope of an input power amplifier (PA) signal.

[0129] The supply voltage tracker 700 is a power amplifier DC supply level selector following power level or envelope of the input PA signal. When the input PA signal level is low, for example, the supply voltage tracker 700 reduces the PA drain voltage to reduce energy waste and maintain high signal quality to increase power amplifier efficiency. When the input PA signal is high, the supply voltage tracker 700 increases PA drain voltage to avoid signal saturation.

[0130] Although FIG. 7 illustrates one example of a supply voltage modulator to support multiple level envelope tracking, various changes may be made to FIG. 7. One or more half bridges,N, may be used to receiveN+1 voltage levels from a generator, whereNis an odd integer. For example, one half bridge may be capable of receiving voltages from a two-level SCVD, five half bridges may be capable of receiving voltages from receive a six-level SCVD, and eight half bridges may be capable of receiving voltages from an eight-level SCVD.

[0131] FIG. 8 illustrates an example block diagram of a voltage supply system 800 to support multiple level envelope tracking according to embodiments of the present disclosure. The embodiment of the voltage supply system 800 illustrated in FIG. 8 is for illustration only. Other embodiments of the voltage supply system 800 could be used without departing from the scope of the present disclosure.

[0132] As shown in FIG. 8, the voltage supply system 800 includes a DC-DC converter 810 coupled to a generator 820 and a supply voltage tracker 830. The DC-DC converter 810 includes a converter half bridge 812 and configured to receive the first voltage 440 using a converter input 814 and provide the second voltage 450 using a converter output 816 to the generator 820. The converter half bridge 812 of the DC-DC converter 810 may be the half bridge 500 of FIG. 5. The generator 820 includes a first generator half bridge 822, a second generator half bridge 824, and a third generator half bridge 826. The generator 820 is configured similarly to the SCVD 600 of FIG. 6. The generator 820 provides the first voltage 440, the 422 (two shown), and the second voltage 450 to the supply voltage tracker 830. The supply voltage tracker 830 includes a first tracker half bridge 832, a second tracker half bridge 834, and a third tracker half bridge 836. The supply voltage tracker 830 is configured similarly to the supply voltage tracker 700 of FIG. 7.

[0133] The voltage supply system 800 is configured as a four-level DC power modulator for use in digital envelope tracking (DET) or power tracking (PT). Although shown using a four-level SCVD and a four-level modulator, the voltage supply system 800 may include any level SCVD and any level modulator. For example, the SCVD may be a two-level SCVD using one half bridge, a three-level SCVD using two half bridges, or a five-level SCVD using four half bridges. Similarly, the modulator may be a two-level modulator using one half bridge, a three-level modulator using two half bridges, or a five-level modulator using four half bridges. In this embodiment, all specifications, such rising time and falling time, max load current hold, and adjusting dead time are completed using half bridges.

[0134] Although FIG. 8 illustrates one example of a voltage supply system to support multiple level envelope tracking, various changes may be made to FIG. 8. For example, multiple modulators may be used in series for a single generator as shown in FIG. 9.

[0135] FIG. 9 illustrates an example block diagram of a voltage supply system 900 using multi-level supply voltage modulators to support multiple level envelope tracking according to embodiments of the present disclosure. The embodiment of the voltage supply system 900 illustrated in FIG. 9 is for illustration only. Other embodiments of the voltage supply system 900 could be used without departing from the scope of the present disclosure.

[0136] As shown in FIG. 9, the voltage supply system 900 includes a DC-DC converter 910 coupled to a generator 920, a first tracker 930, and a second tracker 940. The DC-DC converter 910 includes a converter half bridge 912 and configured to receive the first voltage 440 using a converter input 914 and provide the second voltage 450 using a converter output 916. The converter half bridge 912 of the DC-DC converter 910 may be the half bridge 500 of FIG. 5. The generator 920 includes a first generator half bridge 922, a second generator half bridge 924, and a third generator half bridge 926. The generator 920 is configured similarly to the SCVD 600 of FIG. 6. The generator 920 provides the first voltage 440, the one or more intermediate voltages 422 (two shown), and the second voltage 450 to the first tracker 930 and the second tracker 940. The first tracker 930 includes a first tracker half bridge 932, a second tracker half bridge 934, and a third tracker half bridge 936. The second tracker 940 includes a fourth tracker half bridge 942, a fifth tracker half bridge 944, and a sixth tracker half bridge 946. The first tracker 930 and the second tracker 940 are configured similarly to the supply voltage tracker 700 of FIG. 7. The first tracker 930 and the second tracker 940 each receive the first voltage 440, the one or more intermediate voltages 422, and the second voltage 450 in parallel and each produce two PWM output signals and provide their respective signals to a power amplifier of a DET system (e.g., the power amplifier 460 of the DET system 400) where the two PWM output signals then combine to produce a power amplifier drain voltage.

[0137] The multi-layered modulator (e.g., the first tracker 930 and the second tracker 940) allow for additional PWM output signals to be provided to the power amplifier, resulting in more available voltage levels for envelope tracking without requiring additional generators (e.g., two or more SCVDs) or a higher level generator (e.g., an eight-level SCVD). Alternatively, the multi-layer modulator configuration may support one or more power amplifiers using one of the at least one SCVD. For example, the first tracker 930 may be coupled to a first power amplifier and the second tracker 940 may be coupled to a second power amplifier. This allows the generator 920 to provide the first voltage 440, the one or more intermediate voltages 422, and the second voltage 450 to both the first and second power amplifiers. This configuration may be beneficial to reduce space used by a DET system in MIMO configurations with multiple power amplifiers.

[0138] Although FIG. 9 illustrates one example of a voltage supply system using multi-level supply voltage modulators, various changes may be made to FIG. 9. For example, the voltage supply system may include three or more modulators connected in parallel.

[0139] FIG. 10 illustrates an example method 1000 for applying multiple level envelope tracking using multi half bridges according to embodiments of the present disclosure. An embodiment of the method illustrated in FIG. 10 is for illustration only. One or more of the components illustrated in FIG. 10 may be implemented in specialized circuitry configured to perform the noted functions or one or more of the components may be implemented by one or more processors executing instructions to perform the noted functions. Other embodiments of multiple level envelope tracking using multi half bridges could be used without departing from the scope of this disclosure.

[0140] As illustrated in FIG. 10, one or more power supply modulators of a digital envelope tracking system are generated using one or more half bridges at step 1002. For example, one or more half bridges 500 may be used to generate at least one SCVD (e.g., the generator 820) and at least one tracker 830 as a DC supply modulator configured to provide the power amplifier drain voltage. This may also include generating at least two trackers (e.g., the first tracker 930 and the second tracker 940) operably coupled to the at least one SCVD (e.g., the SCVD 920).

[0141] A dead time is set for each of the one or more half bridges one or more logic and dead time adjust circuits at step 1004. For example, the one or more logic and dead time adjust circuits 522 may set a dead time for a half bridge 500 by adjusting the delay between the turn-off signal of the first transistor 502 (e.g., the high-side switch) and the turn-on signal of the second transistor　504 (low-side switch) or vice versa using a dedicated "dead time" setting on the gate driver of the one or more logic and dead time adjust circuits 522 to create a time window where both the first transistor 502 and the second transistor 504 are OFF. The dead time setting may be a predetermined value or may be computed by the one or more logic and dead time adjust circuits 522 based on characteristics of the first transistor 502 and the second transistor 504.

[0142] A power amplifier drain voltage is provided based on the one or more power supply modulators at step 1006. For example, a first voltage 440 and a second voltage 450 may be provided to the generator 920 (e.g., by the DC-DC converter 910). The SCVD 920 may then generate one or more intermediate voltages 422 and subsequently provide the first voltage 440, the one or more intermediate voltages 422, and the second voltage 450 to the first tracker 930. The first tracker 930 receives the first voltage 440, the one or more intermediate voltages 422, and the second voltage 450 and uses them to generate two PWM output signals. The two PWM output signals then combine (e.g., at the power amplifier 460) to produce a power amplifier drain voltage. Additionally, providing a power amplifier drain voltage may include supporting one or more trackers (e.g., the first tracker 930 and the second tracker 940) and one or more power amplifiers using one of the at least one SCVD (e.g., the generator 920).

[0143] Although FIG. 10 illustrates one example method for multiple level envelope tracking using multi half bridges, various changes may be made to FIG. 10. For example, while shown as a series of steps, various steps in FIG. 10 could overlap, occur in parallel, occur in a different order, or occur any number of times.

[0144] The above flowchart illustrates example methods that can be implemented in accordance with the principles of the present disclosure and various changes could be made to the methods illustrated in the flowcharts herein. For example, while shown as a series of steps, various steps could overlap, occur in parallel, occur in a different order, or occur multiple times. In another example, steps may be omitted or replaced by other steps.

[0145] FIG. 11 is a block diagram of a terminal or user equipment (UE) 1100 according to an embodiment of the disclosure. Furthermore , the UE of FIG. 11 may correspond to UE (or terminal) of FIG. 3.

[0146] The terminal is an electronic device capable of wireless communication, may include a User Equipment (UE), a portable phone, a smartphone, a tablet, an Internet of things (IoT) device, etc., having various form factors, and may perform wireless communication with a base station (BS) through a wireless channel.

[0147] Referring to FIG. 11, the UE 1100 may include at least one transceiver (hereinafter, referred to as simply “transceiver”) 1101, at least one processor (hereinafter, referred to as simply “processor”) 1102, and at least one memory (hereinafter, referred to as simply “memory”) 1103. According to at least one or a combination of methods corresponding to the embodiments described in the present disclosure, the transceiver 1101, the processor 1102, and the memory 1103 of the UE 1100 may operate. However, components of the UE 1100 are not limited to the exemplary components illustrated in FIG. 11. In another embodiment, the UE 1100 may further include additional components in addition to the above-mentioned components, or some components may be omitted. Further, in some embodiments, any combination of the transceiver 1101, the processor 1102, or the memory 1103 may be integrated in the form of one component.

[0148] The transceiver 1101 may be a communication circuit or communication circuitry that enables the UE 1100 to perform wireless communication with a node or an entity of a network. For example, the transceiver 1101 may enable the UE 1100 to transmit or receive a signal to or from a BS through cellular communication, or to transmit or receive a signal to or from another UE through cellular communication. For example, the transceiver 1101 may support at least one of various cellular communication technologies including 3rd generation (3G), 4thgeneration (4G), long term evolution (LTE), 5th generation (5G) NR, 6thgeneration (6G), and various cellular wireless communication technologies supported by the transceiver (1101) may include all subsequent generations of evolved wireless communications.

[0149] According to an embodiment, the UE 1100 may include a plurality of transceivers. For example, in the case of supporting evolved-universal terrestrial radio access-new radio (E-UTRA-NR) sual connectivity (EN-DC), the UE 1100 may include a first transceiver supporting the 4G LTE wireless communication and a second transceiver supporting the 5G NR wireless communication. According to another embodiment, in the case of supporting NR-dual connectivity (NR-DC), the UE 1100 may include a plurality of transceivers supporting the 5G NR wireless communication. According to still another embodiment, in the case of supporting near field wireless communication, the UE 1100 may separately include a transceiver supporting at least one standard in the group of wireless communication protocol standards as defined in the protocol standards for Bluetooth®, wireless local area network (WLAN) network (including institute of electrical and electronics engineers (IEEE) 802.11-2016 standard or its amendments, e.g., 802.11ah, 802.11ad, 802.11ay, 802.11ax, 802.11az, 802.11ba, and 802.11be, without being limited thereto).

[0150] According to an embodiment, the transceiver 1101 may include various circuit structures used to transmit or receive signals to or from a BS through a wireless channel. The signals may include control information and data. For example, the transceiver 1101 may include a radio frequency (RF) transmitter for up-converting and amplifying the frequency of a transmitted signal and an RF receiver for low-noise-amplifying a received signal and down-converting the frequency thereof. The transceiver 1101 may output a signal received through a wireless channel to the processor 1102 and may transmit, through a wireless channel, a signal output from the processor 1102.

[0151] The processor 1102 may control general operations of the UE 1100 according to embodiments of the disclosure. The processor 1102 may be implemented by one or more integrated circuit (or circuitry) (IC) chips and may execute various data processings. The processor 1102 may include at least one electric circuit, and may execute instructions (or a program, codes, data, etc.) stored in the memory 1103, individually, collectively or in any combination thereof. Further, the processor 1102 may include a single-core processor or multi-core processor, and may include a processor assembly including a plurality of processing circuits (circuitry) according to a specific implementation scheme.

[0152] The processor 1102 may be electrically, operatively, or communicatively coupled to the transceiver 1101 to control the transceiver 1101.

[0153] The processor 1102 may include at least one processor (or processing circuitry), and the at least one processor may perform the following operations individually, collectively or in any combination thereof. For example, the processor 1102 may include a communication processor (CP) configured to control communication operations and an application processor (AP) configured to control execution of an upper layer (for example, an application layer) . In a specific embodiment, at least a part of the processor 1102 may be included in one chip and the other part of the processor 1102 may be included in another chip. Otherwise, at least one processor may be included in another component, for example, the transceiver 1101 or the memory 1103.

[0154] The processor 1102 may perform or control or cause an operation of the UE 1100 for executing at least one or a combination of methods according to embodiments of the disclosure. For example, the processor 1102 may control operations of the UE 1100 for processing a downlink signal received from a BS or generating and transmitting an uplink signal to a BS. To this end, the processor 1102 may execute a computer program, codes, or instructions stored in the memory 1103, so as to control other components of the UE 1100 to enable execution of various operations.

[0155] The memory 1103 corresponds to a hardware storage device capable of temporarily or permanently storing information and may include one or more storage media. For example, the memory 1103 may include a memory assembly including one or more storage media. For example, the one or more storage media may include permanent memory, such as a hard drive, flash memory, or read-only memory (ROM), semipermanent memory, such as random access memory (RAM), cache memory, or a combination thereof.

[0156] The memory 1103 may be electrically, operatively, or communicatively coupled to the processor 1102 and may be accessed by the processor 1102.

[0157] The memory 1103 may store a computer program, codes, or instructions executable by the processor 1102. According to an embodiment, a computer program, codes, or instructions executable by the processor 1102 may be either stored in a single memory device or separated and distributedly stored in two or more memory devices. By executing the instructions stored in the memory 1103, the processor 1102 may perform various functions according to an embodiment of the disclosure.

[0158] According to an embodiment of the disclosure, operations of the UE 1100 may be caused to be performed based on execution of instructions (or a computer program or codes) stored in the memory 1103 by at least one processor (or processing circuitry) configured to execute the same individually, collectively, or in any combination thereof, based on processing circuitry that is not configured to execute instructions, and / or based on components of processing circuitry that is not configured to execute instructions.

[0159] FIG. 12 is a block diagram of a base station (BS) 1200 according to an embodiment of the disclosure. Furthermore, the base station of FIG. 12 may correspond to the base station of FIG. 2.

[0160] The BS 1200 may perform wireless communication with at least one user equipment (UE) located within the area of the BS 1200 through a wireless channel.

[0161] Referring to FIG. 12, the BS 1200 may include at least one transceiver (hereinafter, referred to as simply “transceiver”) 1201, at least one processor (hereinafter, referred to as simply “processor”) 1202, and at least one memory (hereinafter, referred to as simply “memory”) 1203. According to at least one or a combination of methods corresponding to the embodiments described in the present disclosure, the transceiver 1201, the processor 1202, and the memory 1203 of the BS 1200 may operate. However, components of the BS 1200 are not limited to the exemplary components illustrated in FIG. 12. In another embodiment, the BS 1200 may further include additional components in addition to the above-mentioned components, or some components may be omitted. Further, in some embodiments, any combination of the transceiver 1201, the processor 1202, or the memory 1203 may be integrated in the form of one component.

[0162] The transceiver 1201 may be a communication circuit or communication circuitry that enables the BS 1200 to perform wireless communication with a node or an entity of a network. For example, the transceiver 1201 may enable the BS 1200 to transmit or receive a signal to or from the UE 1100 through cellular communication, or to transmit or receive a signal to or from another network entity through wireless communication. For example, the transceiver 1201 may support various cellular communication technologies including 3rd generation (3G), 4th generation (4G), long term evolution (LTE), 5th generation (5G) NR, 6th generation (6G), and various cellular wireless communication technologies supported by the transceiver (1201) may include all subsequent generations of evolved wireless communications.. According to an embodiment, the transceiver 1201 may include various circuit structures used to transmit or receive signals to or from a UE through a wireless channel. The signals may include control information and data. For example, the transceiver 1201 may include a radio frequency (RF) transmitter for up-converting and amplifying the frequency of a transmitted signal and an RF receiver for low-noise-amplifying a received signal and down-converting the frequency thereof. The transceiver 1201 may output a signal received through a wireless channel to the processor 1202 and may transmit, through a wireless channel, a signal output from the processor 1202.

[0163] Meanwhile, according to an embodiment of the present disclosure, the BS 1200 may perform communication with a node or an entity of a network through wired or wireless communication. For example, the BS 1200 may perform wired or wireless communication with an adjacent BS, or a node or an entity of a core network through a backhaul network. Although not illustrated in FIG. 12, when the BS 1200 performs wired communication, the BS 1200 may further include a separate network interface for wired communication in addition to the transceiver 1201. The network interface may be referred to as network interface circuitry or communication interface circuitry.

[0164] The processor 1202 may control general operations of the BS 1200 according to embodiments of the disclosure. The processor 1202 may be implemented by one or more integrated circuit (or circuitry) (IC) chips and may execute various data processings. The processor 1202 may include at least one electric circuit, and may execute instructions (or a program, codes, data, etc.) stored in the memory 1203, individually, collectively or in any combination thereof. Further, the processor 1202 may include a single-core processor or multi-core processor, and may include a processor assembly including a plurality of processing circuits (circuitry) according to a specific implementation scheme.

[0165] The processor 1202 may be electrically, operatively, or communicatively coupled to the transceiver 1201 to control the transceiver 1201.

[0166] The processor 1202 may include at least one processor (or processing circuitry), and the at least one processor may perform the following operations individually, collectively or in any combination thereof. In a specific embodiment, at least a part of the processor 1202 may be included in one chip and the other part of the processor 1202 may be included in another chip. Otherwise, at least one processor may be included in another component, for example, the transceiver 1201 or the memory 1203.

[0167] The processor 1202 may perform or control or cause an operation of the BS 1200 for executing at least one or a combination of methods according to embodiments of the disclosure. For example, the processor 1202 may control operations of the BS 1200 for generating and transmitting a downlink signal to a UE or processing an uplink signal received from a UE. Otherwise, the BS 1200 may transmit or receive a signal to or from a neighboring BS, transfer a signal received from a UE to an upper node of the network, or transmit a signal transferred from an upper node of the network to a UE. To this end, the processor 1202 may execute a computer program, codes, or instructions stored in the memory 1203, so as to control other components of the BS 1200 to enable execution of various operations.

[0168] The memory 1203 corresponds to a hardware storage device capable of temporarily or permanently storing information and may include one or more storage media. For example, the memory 1203 may include a memory assembly including one or more storage media. For example, the one or more storage media may include permanent memory, such as a hard drive, flash memory, or read-only memory (ROM), semipermanent memory, such as random access memory (RAM), cache memory, or a combination thereof.

[0169] The memory 1203 may be electrically, operatively, or communicatively coupled to the processor 1202 and may be accessed by the processor 1202.

[0170] The memory 1203 may store a computer program, codes, or instructions executable by the processor 1202. According to an embodiment, a computer program, codes, or instructions executable by the processor 1202 may be either stored in a single memory device or separated and distributedly stored in two or more memory devices. By executing the instructions stored in the memory 1203, the processor 1202 may perform various functions according to an embodiment of the disclosure.

[0171] According to an embodiment of the disclosure, operations of the BS 1200 may be caused to be performed based on execution of instructions (or a computer program or codes) stored in the memory 1203 by at least one processor (or processing circuitry) configured to execute the same individually, collectively, or in any combination thereof, based on processing circuitry that is not configured to execute instructions, and / or based on components of processing circuitry that is not configured to execute instructions.

[0172] The UE or the base station may perform various communication procedures related to the control plane or the user plane by cooperating with one or more network entities based on wireless communication. For example, the UE may communicate with network entity such as an Access and Mobility Management Function (AMF) or a Session Management Function (SMF) via the base station, or the base station may perform at least one communication procedure by directly transmitting and receiving signals to / from, or relaying signals between, the network entities.

[0173] The structure of the above-described network entity will be described in more detail with reference to the drawings.

[0174] FIG. 13 is a block diagram of a network entity 1300 according to an embodiment of the disclosure.

[0175] The network entity 1300 may include an entity (apparatus, device, or server, etc.) that performs one or more network functions (NFs) or a part of a network function constituting a core network (e.g., a 5th generation (5G) core (5GC)) in a communication system. In this case, multiple NFs may be implemented within a single network entity, or a single NF may be distributed and implemented across a plurality of network entities. In addition, when an NF is implemented within the network entity, the NF may be implemented in the form of software, and in such a case, a program for operating the NF may be stored in memory of the network entity 1300.

[0176] A single NF may be implemented by one or more instances, which may be deployed on the same network entity or distributed across multiple network entities to operate. The instance may be a software unit that logically executes a specific network function, and may be implemented in a form that is decoupled from physical hardware resources. Further, one or more NFs may be implemented in the form of one network slice to operate to satisfy specifications required by a particular service.

[0177] The NF may include at least one of an access and mobility management function (AMF), a session management function (SMF), a local session management function (L-SMF), a user plane function (UPF), a local user plane function (L-UPF), a policy control function (PCF), a unified data management (UDM), a unified data repository (UDR), a network exposure function (NEF), a network repository function (NRF), an application function (AF), a network slice selection function (NSSF), a network data analytics function (NWDAF), a network slice admission control function (NSACF), an authentication server function (AUSF), or a data network (DN).

[0178] Referring to FIG. 13, the network entity 1300 may include at least one network interface 1301, at least one processor 1302 (hereinafter, “processor”), and at least one memory 1303 (hereinafter, “memory”). As described above, a NF may be implemented in the form of a physical device such as the network entity 1300, or may be virtualized and executed in the form of an instance. When implemented as an instance, the NF need not necessarily include physical components as illustrated in FIG. 13. In such a case, the instance may be logically represented as comprising one or more logical functional elements.

[0179] According to at least one or a combination of methods corresponding to the embodiments described in the present disclosure, the network interface 1301, the processor 1302, and the memory 1303 of the network entity 1300 may operate. However, components of the network entity 1300 are not limited to the exemplary components illustrated in FIG. 13. In another embodiment, the network entity 1300 may further include additional components in addition to the above-mentioned components, or some components may be omitted. Further, in an embodiment, the network interface 1301, the processor 1302, or the memory 1303 may be integrated in the form of one component.

[0180] The network interface 1301 is a collective term for a transmitter part of the network entity 1300 and a receiver part of the network entity 1300, and may be a communication circuit for transmitting or receiving a signal to or from a user equipment (UE), a base station (BS), or another network entity. Here, the communication circuit may include both a communication circuit for wireless communication and a communication circuit for a wired communication. For example, the network interface 1301 may include a circuit, logic, hardware, etc., configured to exchange a control plane message or a user plane message with a UE, a BS, or other core network entities through wireless communication or wired communication. The network interface 1301 may operate using various protocols (e.g., non-access stratum (NAS) protocol). The network interface 1301 may also be referred to, for convenience of description or depending on implementation, as communication circuitry, network interface circuitry, or a communication interface circuitry.

[0181] The processor 1302 may control general operations of the network entity 1300 according to embodiments of the disclosure. The processor 1302 may be implemented by one or more integrated circuit (or circuitry) (IC) chips and may execute various data processings. The processor 1302 may include at least one electric circuit, and may execute instructions (or a program, codes, data, etc.) stored in the memory 1303, individually, collectively or in any combination thereof. Further, the processor 1302 may include a single-core processor or multi-core processor, and may include a processor assembly including a plurality of processing circuits (circuitry) according to a specific implementation scheme. Further, it should be noted that, according to another embodiment, in a case where NF is implemented in the form of an instance, the network function may be not necessarily configured by physical hardware.

[0182] According to an embodiment, the processor 1302 may be electrically, operatively, or communicatively coupled to the network interface 1301 to control the network interface 1301.

[0183] The processor 1302 may include at least one processor (or processing circuitry), and the at least one processor may perform the following operations individually, collectively or in any combination thereof. In a specific embodiment, at least a part of the processor 1302 may be included in one chip and the other part of the processor 1302 may be included in another chip. Otherwise, at least one processor may be included in another component, for example, the network interface 1301 or the memory 1303.

[0184] The processor 1302 may perform or control or cause an operation of the network entity 1300 for executing at least one or a combination of methods according to embodiments of the disclosure. For example, the processor 1302 may control operations of the network entity 1300 for exchanging a control plane message or a user plane message with a UE, a BS, or other core network entities through wireless or wired communication, using various protocols (e.g., NAS protocol). To this end, the processor 1302 may execute a computer program, codes, or instructions stored in the memory 1303, so as to control other components of the network entity 1300 to enable execution of various operations.

[0185] The memory 1303 corresponds to a hardware storage device capable of temporarily or permanently storing information and may include one or more storage media. For example, the memory 1303 may include a memory assembly including one or more storage media. For example, the one or more storage media may include permanent memory, such as a hard drive, flash memory, or read-only memory (ROM), semipermanent memory, such as random access memory (RAM), cache memory, or a combination thereof.

[0186] The memory 1303 may be electrically, operatively, or communicatively coupled to the processor 1302 and may be accessed by the processor 1302.

[0187] The memory 1303 may store a computer program, codes, or instructions executable by the processor 1302. According to an embodiment, a computer program, codes, or instructions executable by the processor 1302 may be either stored in a single memory device or separated and distributedly stored in two or more memory devices. By executing the instructions stored in the memory 1303, the processor 1302 may perform various functions according to an embodiment of the disclosure.

[0188] According to an embodiment of the disclosure, operations of the network entity 1300 may be caused to be performed based on execution of instructions (or a computer program or codes) stored in the memory 1303 by at least one processor (or processing circuitry) configured to execute the same individually, collectively, or in any combination thereof, based on processing circuitry that is not configured to execute instructions, and / or based on components of processing circuitry that is not configured to execute instructions.

[0189] In one embodiment, a power modulator system is provided, which comprises: one or more power supply modulators configured to provide a power amplifier drain voltage, each of the one or more power supply modulators comprising: one or more half bridges including one or more drivers; and one or more logic and dead time adjust circuits.

[0190] In another embodiment, the power modulator system is provided, wherein the one or more power supply modulators comprise at least one switch capacitor voltage divider (SCVD).

[0191] In another embodiment, the power modulator system is provided, wherein the at least one SCVD is coupled to at least one tracker and one or more power amplifiers.

[0192] In another embodiment, the power modulator system is provided, wherein the one or more power supply modulators comprise at least one SCVD and at least one tracker configured to provide the power amplifier drain voltage.

[0193] In another embodiment, the power modulator system is provided, wherein the at least one tracker comprises at least two trackers operably coupled to the at least one SCVD.

[0194] In another embodiment, the power modulator system is provided, wherein each of the one or more half bridges comprises a metal-oxide-semiconductor field-effect transistor (MOSFET) or a gallium nitride field-effect transistor (GaNFET).

[0195] In another embodiment, the power modulator system is provided, wherein each of the one or more half bridges includes at least one of a driver, a level shifter, an isolated buffer amplifier, a bootstrap, and a low dropout regulator.

[0196] In one embodiment, a method is provided, which comprises: generating one or more power supply modulators using one or more half bridges; setting a dead time set for each of the one or more half bridges using one or more logic and dead time adjust circuits; and providing power amplifier drain voltage based on the one or more power supply modulators.

[0197] In another embodiment, the method is provided, wherein the one or more power supply modulators comprise at least one switch capacitor voltage divider (SCVD).

[0198] In another embodiment, the method is provided, which further comprises: supporting one or more trackers and one or more power amplifiers using one of the at least one SCVD.

[0199] In another embodiment, the method is provided, wherein generating the one or more power supply modulators using the one or more half bridges includes generating at least one SCVD and at least one tracker as a DC supply modulator configured to provide the power amplifier drain voltage.

[0200] In another embodiment, the method is provided, wherein generating at least one SCVD and at least one tracker comprises generating at least two trackers operably coupled to the at least one SCVD.

[0201] In another embodiment, the method is provided, wherein each of the one or more half bridges include at least one of a metal-oxide-semiconductor field-effect transistor (MOSFET) or a gallium nitride field-effect transistor (GaNFET).

[0202] In another embodiment, the method is provided, wherein each of the one or more half bridges includes a driver, a level shifter, an isolated buffer amplifier, a bootstrap, and a low dropout regulator.

[0203] In one embodiment, an electronic device is provided, which comprises: one or more trackers; one or more power amplifiers; and a processor operably coupled to the one or more trackers and the one or more power amplifiers, configured to cause the electronic device to: generate one or more power supply modulators using one or more half bridges; set a dead time set for each of the one or more half bridges using one or more logic and dead time adjust circuits; and provide power amplifier drain voltage based on the one or more power supply modulators.

[0204] In another embodiment, the electronic device is provided, wherein the one or more power supply modulators comprise at least one switch capacitor voltage divider (SCVD).

[0205] In another embodiment, the electronic device is provided, wherein the processor is further configured to cause the electronic device to support the one or more trackers and the one or more power amplifiers using one of the at least one SCVD.

[0206] In another embodiment, the electronic device is provided, wherein, while generating the one or more power supply modulators using the one or more half bridges, the processor is further configured to cause the electronic device to generate at least one SCVD and at least one tracker as a DC supply modulator configured to provide the power amplifier drain voltage.

[0207] In another embodiment, the electronic device is provided, wherein, while generating at least one SCVD and at least one tracker, the processor is further configured to cause the electronic device to generate at least two trackers operably coupled to the at least one SCVD.

[0208] In another embodiment, the electronic device is provided, wherein each of the one or more half bridges includes a driver, a level shifter, an isolated buffer amplifier, a bootstrap, and a low dropout regulator.

[0209] Meanwhile, although specific embodiments of the present disclosure have been described in detail, various modifications may be made without departing from the scope of the present disclosure. Therefore, the scope of the present disclosure should not be limited to the described embodiments, but should be defined by the claims and equivalents thereof.

Claims

1.A power modulator system comprising:one or more power supply modulators configured to provide a power amplifier drain voltage, each of the one or more power supply modulators comprising:one or more half bridges including one or more drivers; andone or more logic and dead time adjust circuits.2.The power modulator system of claim 1, wherein the one or more power supply modulators comprise at least one switch capacitor voltage divider (SCVD).3.The power modulator system of claim 2, wherein the at least one SCVD is coupled to at least one tracker and one or more power amplifiers.4.The power modulator system of claim 1, wherein the one or more power supply modulators comprise at least one SCVD and at least one tracker configured to provide the power amplifier drain voltage.5.The power modulator system of claim 4, wherein the at least one tracker comprises at least two trackers operably coupled to the at least one SCVD.6.The power modulator system of claim 1, wherein each of the one or more half bridges comprises a metal-oxide-semiconductor field-effect transistor (MOSFET) or a gallium nitride field-effect transistor (GaNFET).7.The power modulator system of claim 6, wherein each of the one or more half bridges includes at least one of a driver, a level shifter, an isolated buffer amplifier, a bootstrap, and a low dropout regulator.8.A method, comprising:generating one or more power supply modulators using one or more half bridges;setting a dead time set for each of the one or more half bridges using one or more logic and dead time adjust circuits; andproviding power amplifier drain voltage based on the one or more power supply modulators.9.The method of claim 8, wherein the one or more power supply modulators comprise at least one switch capacitor voltage divider (SCVD).10.The method of claim 9, further comprising:supporting one or more trackers and one or more power amplifiers using one of the at least one SCVD.11.The method of claim 8, wherein generating the one or more power supply modulators using the one or more half bridges includes generating at least one SCVD and at least one tracker as a DC supply modulator configured to provide the power amplifier drain voltage.12.The method of claim 11, wherein generating at least one SCVD and at least one tracker comprises generating at least two trackers operably coupled to the at least one SCVD.13.The method of claim 8, wherein each of the one or more half bridges include at least one of a metal-oxide-semiconductor field-effect transistor (MOSFET) or a gallium nitride field-effect transistor (GaNFET).14.The method of claim 13, wherein each of the one or more half bridges includes a driver, a level shifter, an isolated buffer amplifier, a bootstrap, and a low dropout regulator.15.An electronic device, comprising:one or more trackers;one or more power amplifiers; anda processor operably coupled to the one or more trackers and the one or more power amplifiers, configured to cause the electronic device to:generate one or more power supply modulators using one or more half bridges;set a dead time set for each of the one or more half bridges using one or more logic and dead time adjust circuits; andprovide power amplifier drain voltage based on the one or more power supply modulators.

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