Overwriting memory to protect security sensitive data begore memory built-in self-test

Abstract

Techniques and apparatuses are described for securing a memory built-in self-test. In an example aspect, an integrated circuit (106) includes an override circuit (206), which evaluates a first programmable instruction for a memory built-in self-test. If an operation of the first instruction is not associated with one of the allowable operations, the operation of the first instruction is overridden with one of the allowable operations. This ensures that any security-sensitive information within a memory (202) of the integrated circuit (106) is overwritten before the memory built-in self-test executes another programmable instruction involving a read operation. The override circuit (206) can be simpler and cheaper to implement compared to other techniques that rely on a complex finite-state machine. This technique ensures diagnosis capability of the memory built-in self-test is maintained by enabling a portion of the memory (202) that stores security-sensitive information to be tested.

Description

SECURING A MEMORY BUILT-IN SELF-TESTBACKGROUND

[0001] Testing is an important factor in the design, development, and manufacturing of integrated circuits. Some tests are perfonned using automatic test equipment (ATE). The automatic test equipment connects to the integrated circuit and can execute and evaluate a variety of different tests. These tests can enable early detection of faults, which can save time and money in addition to ensuring an integrated circuit works as intended.

[0002] Testing via the automatic test equipment, however, is not without its challenges. Firstly, the automatic test equipment can be expensive and bulky. Use of the automatic test equipment can therefore be limited to testing in a lab prior to distributing a product to a customer. Secondly, it can take time for engineers to configure the automatic test equipment for testing different products and / or for performing different types of test on a same product. There is a general need to make testing easier, faster, and cheaper.SUMMARY

[0003] Techniques and apparatuses are described for securing a memory built-in self-test (MBIST). In example aspects, an integrated circuit includes an override circuit, which evaluates a first programmable instruction for a memory built-in self-test. If an operation of the first instruction is not associated with one of the allowable operations, the operation of the first instruction is overridden with one of the allowable operations. The allowable operations include any type of write operation. This ensures that any security-sensitive information within a memory of the integrated circuit is overwritten before the memory built-in self-test executes another programmable instruction involving a read operation. The override circuit can be simpler and cheaper to implement compared to other techniques that rely on a complex finite-state machine. In some cases, the features of the override circuit can be readily integrated within existing controllers. Furthermore, this technique ensures diagnosis capability of the memory7built-in selftest is maintained by enabling a portion of the memory that stores security -sensitive information to be tested.

[0004] Aspects described below include a method performed by a controller for securing a memory7built-in self-test. The method includes receiving a set of programmable instructions associated with a memory built-in self-test. The set of programmable instructions includes a first instruction that is to be executed prior to executing other instructions of the set of programmable instructions. The method also includes determining that an operation corresponding to the firstinstruction differs from operations within a set of allowable operations. The method additionally includes performing, based on the determining, the memory built-in self-test using a default operation instead of the operation corresponding to the first instruction. The default operation includes an operation within the set of allowable operations.

[0005] Aspects described below also include an apparatus comprising an integrated circuit configured to perform any of the described methods.

[0006] Aspects described below include a computer-readable storage medium comprising computer-executable instructions that, responsive to execution by a controller, cause the controller to perform any one of the described methods.

[0007] Aspects described below also include a system with means for securing a memory built- in self-test.BRIEF DESCRIPTION OF DRAWINGS

[0008] Apparatuses for and techniques for securing a memory built-in self-test are described with reference to the following drawings. The same numbers are used throughout the drawings to reference like features and components:FIG. 1 illustrates an example environment in which securing a memoiy built-in self-test can be implemented;FIG. 2 illustrates an example implementation of a computing device that can implement aspects of securing a memory built-in self-test;FIG. 3 illustrates an example implementation of a controller capable of securing a memoiy' built-in self-test;FIG. 4 illustrates example programmable instructions associated with a memory built-in self-test;FIG. 5 illustrates an example implementation of an override circuit for performing aspects of securing a memory built-in self-test;FIG. 6 illustrates example allowable operations for securing a memoiy built-in self-test;FIG. 7 illustrates an example scheme for securing a memoiy' built-in self-test;FIG. 8 illustrates an example method for securing a memory' built-in self-test; andFIG. 9 illustrates an example computing system embodying, or in which techniques may be implemented that enable use of, securing a memoiy built-in self-test.DETAILED DESCRIPTION

[0009] Testing is an important factor in the design, development, and manufacturing of integrated circuits. Although testing can be performed using automatic test equipment (ATE), there is ageneral need to make testing easier, faster, and cheaper. Some manufacturers address this by taking a design-for-testability (DFT) approach in the manufacturing of their products. With design for testability, an integrated circuit can be implemented with additional hardw are that provides built-in testability features. This means that the integrated circuit can execute and evaluate built- in self-tests, which can reduce the manufacturer’s reliance on automatic test equipment.

[0010] Some built-in self-tests support programmable instructions, which can be provided by a user or a technician at a repair store. While this can provide flexibility in supporting testing after manufacturing and distribution, it provides a security concern. Without additional security protection, an external entity can provide instructions for a built-in self-test that reads securitysensitive information that is stored within a memory of the integrated circuit. This securitysensitive information can include security keys, license keys, and / or personal information associated with the user. It is therefore desirable to protect this security-sensitive information from being accessed using a built-in self-test.

[0011] A first technique addresses this by preventing access to portions of a memory that stores the security -sensitive information. A second technique performs a power-down procedure to erase the security -sensitive information and prevent it from being accessed prior to executing a built-in self-test. A third technique cause dummy information to be provided instead of the securitysensitive information. All of these techniques, however, limit diagnosis capabilities of the built- in self-test. This can be undesirable particularly in cases in which the built-in self-test is used to identity' and / or repair a problem. Also, some of these techniques may rely on a finite-state machine (FSM) to provide the security' feature, which can add additional complexity' and cost to incorporating the design for testability features within a product.

[0012] To address this challenge, techniques are described for securing a memory built-in selftest. In example aspects, an integrated circuit includes an override circuit, which evaluates a first programmable instruction for a memory' built-in self-test. If an operation of the first instruction is not associated with one of the allowable operations, the operation of the first instruction is overridden with one of the allowable operations. The allowable operations include any type of write operation. This ensures that any security-sensitive information within a memory of the integrated circuit is overwritten before the memory built-in self-test executes another programmable instruction involving a read operation. The override circuit can be simpler and cheaper to implement compared to other techniques that rely on a complex finite-state machine. In some cases, the features of the override circuit can be readily integrated within existing controllers. Furthermore, this technique ensures diagnosis capability of the memory built-in self-test is maintained by enabling a portion of the memory that stores security -sensitive information to be tested.Operating Environment

[0013] FIG. 1 is an illustration of an example environment 100 in which securing a memory built- in self-test can be implemented. In the example environment 100, a computing device 102 provides features and / or services to a user 104. Although depicted as a smartphone, the computing device 102 can include other types of devices, including those described with respect to FIG. 2. The computing device 102 includes at least one integrated circuit 106. which stores data 108. The data 108 can include non-security-sensitive information as well as security -sensitive information.

[0014] Security-sensitive information includes any ty pe of information that is to be protected to maintain a security of the computing device 102. Some types of security -sensitive information include security keys (e.g., user-specific keys) and / or license keys. Other types of securitysensitive information can include information that is personal to the user 104 and is to be protected for security or privacy. Personal information can include passwords, account information, and so forth. Non-security -sensitive information can include any other type of information that, if provided to another entity, does not compromise a security of the computing device 102 and / or compromise the user 104’s privacy.

[0015] Consider an example situation in which the user 104 notices a problem with the computing device 102. The computing device 102 may not be functioning as normal or may be reporting some ty pe of error. A built-in self-test can be used to identify and / or resolve the problem. The built-in self-test can include evaluating the performance and / or the functionality of the integrated circuit 106. This can include testing a memory of the integrated circuit 106 that stores the data 108 using a memory built-in self-test.

[0016] In some circumstances, the user 104 may tty to run a memory7built-in self-test. In other circumstances, the user 104 can take the computing device 102 to a repair shop and a technician may try to identify the problem by running the memory built-in self-test. In yet another circumstance, the computing device 102 may be returned to a manufacturer and the manufacturer may run the built-in self-test to evaluate the integrated circuit 106.

[0017] To perform a memory7built-in self-test, an entity provides programmable instructions 110 (e.g., soft-coded instructions) associated with the memory built-in self-test to the integrated circuit 106. The entity can include the user 104, the technician at a repair shop, and / or a test engineer employed by the manufacturer. To protect the data 108 and prevent it from being accessed by the entity, the integrated circuit 106 performs a secure memory7built-in self-test 112.

[0018] The secure memory built-in self-test 112 evaluates a first instruction of the programmable instructions 110. The first instruction represents an instruction that is to be executed prior to executing the remaining programmable instructions 110. If the secure memory' built-in selftest 112 determines that an operation of the first instruction is not associated with one of the allowable operations, the secure memory built-in self-test 112 overrides the operation of the first instruction with one of the allowable operations. This ensures that any security-sensitive information within the data 108 is overwritten before the memory built-in self-test executes one of the other instructions involving a read operation.

[0019] Use of the secure memory built-in self-test 112 is also beneficial in situations in which the computing device 102 is stolen and / or accessible by an unauthorized entity (e.g., a hacker). In this case, the secure memory' built-in self-test 112 prevents the unauthorized entity' from reading the data 108 and getting access to the security-sensitive information within the data 108 through a memory’ built-in self-test. As described above, the secure memory’ built-in self-test 122 enables the memory of the integrated circuit 106 to be tested by authorized (or unauthorized) entities while preventing the data 108 (and in particular security-sensitive information) from being read by the entity'. The computing device 102 is further described with respect to FIG. 2.

[0020] FIG. 2 illustrates an example computing device 102. The computing device 102 is illustrated with various non-limiting example devices including a desktop computer 102-1, atablet 102-2, a laptop 102-3, a television 102-4, a computing watch 102-5, computing glasses 102-6, a gaming system 102-7, a microwave 102-8, and a vehicle 102-9. Other devices may also be used, such as a home service device, a smart speaker, a smart thermostat, a baby monitor, a Wi-Fi™ router, a drone, a trackpad, a drawing pad, a netbook, an e-reader. a home automation and control system, a wall display, and another home appliance. Note that the computing device 102 can be wearable, non-wearable but mobile, or relatively immobile (e.g., desktops and appliances).

[0021] The computing device 102 includes at least one integrated circuit 106 capable of securing a memory built-in self-test. The integrated circuit 106 includes memory 202 and at least one controller 204. The memory 202, which can also be referred to as a computer-readable medium, is capable of storing the data 108. The controller 204 is coupled to the memory 202 and can perform the secure memory' built-in self-test 112 on the memory 202. An example implementation of the controller 204 is further described with respect to FIG. 3.

[0022] Although a single instance of the memory 202 and the controller 204 is shown in FIG. 2, the computing device 102 can include multiple instances of the memory 202 and / or the controller 204. Consider an example in which the computing device 102 includes a central processing unit (CPU) and / or a graphics processing unit (GPU). In this case, each one of thecentral processing unit and / or the graphics processing unit can be associated with at least one memory 202 and at least one controller 204.

[0023] The controller 204 includes at least one override circuit 206, which implements aspects of securing a memory built-in self-test. In an example implementation, the override circuit 206 employs comparator logic to evaluate one of the programmable instructions 110 and selection logic to override one of the programmable instructions 1 10. An example implementation of the override circuit 206 is further described with respect to FIG. 5.

[0024] In example implementations, the override circuit 206 can be incorporated into controllers 204 of the computing device 102 with access to memory 202 that stores securitysensitive information. These controllers 204 can therefore perform a secure memory built-in selftest 112 to prevent the security-sensitive information from being accessed by an entity. For other controllers that have access to memory' 202 that does not store security-sensitive data, these controllers can be implemented without the override circuit 206 and can perform normal memory’ built-in self-tests (e.g., not the secure memory built-in self-test 112).

[0025] In another example implementation, multiple controllers 204 include the override circuit 206. The manufacturer (or in some cases the user 104) can identity7the memories 202 that store security -sensitive information. In this case, the multiple controllers 204 coupled to these memories 202 can appropriately configure themselves to perform a secure memory built-in selftest 112 or a normal memory built-in self-test. More specifically, each controller 204 can appropriately enable or disable the override circuit 206 based on whether it is coupled to a memory' 202 that stores security-sensitive information or another memory' 202 that stores nonsecurity-sensitive infonnation.

[0026] The computing device 102 can also include a network interface 208 for communicating data over wired, wireless, or optical networks. For example, the network interface 208 may communicate data over a local-area-network (LAN), a wireless local-area-network (WLAN), a personal-area-network (PAN), a wire-area-network (WAN), an intranet, the Internet, a peer-to- peer network, point-to-point network, a mesh network. Bluetooth™, and the like. In some implementations, the network interface 208 provides the programmable instructions 110 to the integrated circuit 106. The computing device 102 may also include a display 210. An operation of the controller 204 is further described w ith respect to FIG. 3.Securing a Memory Built-In Self-Test

[0027] FIG. 3 illustrates an example implementation of the controller 204, which is coupled to the memory' 202. In the depicted configuration, the controller 204 includes at least one first computer-readable medium 302-1 (first CRM 302-1) and at least one second computer-readable medium 302-2 (second CRM 302-2). The first and second computer-readable mediums 302-1 and 302-2 can also be referred to as first and second computer-readable storage mediums. The first computer-readable medium 302-2 stores hard-coded instructions 304 for performing a memory built-in self-test. In an example implementation, the first computer-readable medium 302-1 is implemented using non-volatile memory, such as a fuse array, a flash memory, metal bits, a programmable read-only memory, a one-time programmable memory, and so on.

[0028] The second computer-readable medium 302-2 stores the programmable instructions 110 for performing a memory built-in self-test. The programmable instructions 110 can also be referred to as a set of instructions. Generally speaking, the programmable instructions 110 include multiple instructions (e.g., more than two instructions), some of which may be associated with some ty pe of read operation. The programmable instructions 110 can be provided by another entity, such as the user 104, a technician at a repair shop, a test engineer employed by a manufacturer, or an unauthorized entity (e.g., a hacker).

[0029] In an example implementation, the second computer-readable medium 302-2 is implemented using volatile memory. such as a cache memory', a random-access memory', or a portion of a memory array. In another example implementation, the second computer-readable medium 302-2 is implemented using a set of registers, which are programmable. This means that an entity can change the contents that are stored within the set of registers.

[0030] The controller 204 also includes at least one mode-selection circuit 306, at least one finite- state machine 308, at least one read / write control 310 (R / W control 310), at least one data generator 312, and at least one address generator 314. Other types of components (not shown) that support the execution and evaluation of a memory built-in self-test can also be included as part of the controller 204. The mode selection circuit 306 is coupled to the first computer-readable medium 302-1, the second computer-readable medium 302-2, and the finite-state machine 308. The mode selection circuit 306 passes the hard-coded instructions 304 or the programmable instructions 110 to the finite-state machine 308 based on a mode control signal 316.

[0031] The finite-state machine 308 passes the appropriate information to the read / write control 310, the data generator 312, and the address generator 314 to execute the memory' built-in self-test in accordance with the instructions passed by the mode selection circuit 306. With the read / write control 310. the data generator 312, and the address generator 314, the controller 204 can perform write and / or read operations on the memory 202 to execute and / or evaluate a memory' built-in self-test. With the read / write control 310, the data generator 312, and the address generator 314, data can pass between the controller 204 and the memory' 202.

[0032] The controller 204 also includes the override circuit 206, which is coupled between the second computer-readable medium 302-2 and the mode selection circuit 306. The override circuit 206 evaluates at least a first instruction of the programmable instructions 110 based on allowable operations 318 (e.g., a set of allowable operations 318). The controller 204 can store or have access to a computer-readable medium that stores the allowable operations 318. Example allowable operations 318 are further described in FIG. 6. In some cases, the override circuit 206 overwrites the first instruction of the programmable instructions 110 to perform aspects of securing a memoiy built-in self-test. The programmable instructions 110 are further described with respect to FIG. 4.

[0033] FIG. 4 illustrates example programmable instructions 110 associated with a memory built- in self-test. In the depicted configuration, the programmable instructions 110 include instructions 402-1, 402-2... 402 -N, where N represents a positive number. Each instruction 402 can include an operation 404 and an address scheme and control 406. The operation 404 specifies an operation that is to be performed by the memory 202. Example operations 404 can include a write operation and / or a read operation. A variety of different types of operations 404 can be supported by the controller 204, including the ones that are described with respect to FIG. 6.

[0034] The address scheme and control 406 specifies the one or more addresses in which to apply the operation 404. In some cases, the address scheme and control 406 specifies an order in which addresses are accessed, such as in a row-first or a column-first manner. Although not explicitly depicted, the instruction 402 can also specify other parameters, such as a mode or other types of controls.

[0035] An order of the instructions 402-1 to 402-N represents an order in which the instructions 402-1 to 402-N are executed. In this example, the first instruction 402-1 represents an instruction that is executed first. Also, the instruction 402-N represents an instruction that is executed last. The first instruction 402-1 can also be referred to as “instruction 0.” The techniques for securing a memoiy built-in self-test are applied to at least the first instruction 402-1, as further described with respect to FIG. 5.

[0036] FIG. 5 illustrates an example implementation of the override circuit 206, which is coupled to at least a portion of the second computer-readable medium 302-2 that stores the first instruction 402-1. For example, the override circuit 206 can be coupled to one or more registers that store the operation 404 and the address scheme and control 406 corresponding to the first instruction 402-1. The override circuit 206 includes at least one comparator circuit 502, at least one operation selection circuit 504, and at least one address scheme selection circuit 506. The comparator circuit 502 has an output that is coupled to control inputs of the operation selectioncircuit 504 and the address scheme selection circuit 506. Although not explicitly shown in FIG. 5, the operation selection circuit 504 and the address scheme selection circuit 506 are coupled to the mode selection circuit 306 and / or the finite-state machine 308 of FIG. 3.

[0037] During operation, the comparator circuit 502 compares the operation 404 of the first instruction 402-1 to the allowable operations 318. The comparator circuit 502 generates an override flag 508 based on the comparison. If the operation 404 differs from the operations included within the allowable operations 318, the comparator circuit 502 causes the override flag 508 to have a first value, which initiates features for securing the memory built-in self-test by enabling the first instruction 402-1 to be overwritten. Otherwise, if the operation 404 is the same as one of the allowable operations 318, the comparator circuit 502 causes the override flag 508 to have a second value, which enables the memory7built-in self-test to be executed with the first instruction 402-1.

[0038] The operation selection circuit 504 outputs a default operation 510 or the operation 404 of the first instruction 402-1 based on the override flag 508. The default operation 510 can be one of the allowable operations 318. The address scheme selection circuit 506 outputs a default address scheme and control 512 or the address scheme and control 406 of the first instruction 402-1 based on the override flag 508. In an example implementation, the default address scheme and control 512 can include at least a portion of the addresses associated with the memory 202 that store the security-sensitive information. In another example implementation, the default address scheme and control 512 can also include at least a portion of the addresses that store the non-security-sensitive information.

[0039] If the override flag 508 has the first value, the override circuit 206 overwrites the first instruction 402-1 by providing the default operation 510 and the default address scheme and control 512 to the finite-state machine 308. Otherwise, if the override flag 508 has the second value, the override circuit 206 passes the first instruction 402-1 to the finite-state machine 308. Examples of the allowable operations 318 are further described with respect to FIG. 6.

[0040] FIG. 6 illustrates example allowable operations 318 and example excluded operations 602 associated with a security memory built-in self-test 112. The allowable operations 318 represent any type of operation 404 that can overwrite the security-sensitive information stored within the memory 202 thereby preventing an entity from accessing this information using a memory built- in self-test. Example allowable operations 318 can include any type of write operation 604, such as a standalone write operation 606 (e.g., a normal write operation 606), a write-read-compare operation 608, a write-fast operation 610, and so forth. The default operation 510 can include any one of the write operations 604 specified as allow able operations 318.

[0041] In contrast, the excluded operations 602 represent any type of operation 404 that does not enable the security -sensitive information stored within the memory 202 to be overwritten. In some cases, the excluded operations 602 can enable the security -sensitive information to be read and thereby accessed by an entity. The excluded operations 602 can include any type of read operation 612, such as a standalone read operation 614 (e.g., anormal read operation 614), a readmodify-write operation 616, a read-write-read invert operation 618, and so forth.

[0042] Although identified as “excluded” operations 602, the excluded operations 602 are only applicable to the first instruction 402-1. Generally speaking, other instructions 402-2 to 402-N of the programmable instructions 110 can include the excluded operations 602. To secure the memory built-in self-test, the controller 204 ensures one of the allowable operations 318 are performed prior to performing one of the excluded operations 602. The override circuit 206 provides this security by determining that the operation 404 of the first instruction 402-1 is one of the allowable operations 318 and therefore can be executed, or by overwriting the operation 404 of the instruction 402-1 to be one of the allowable operations 318, as further described with respect to FIG. 7.

[0043] FIG. 7 illustrates an example scheme 700 for securing a memory built-in self-test. Optionally at 702, some implementations of the controller 204 can determine if the secure memory' built-in self-test 112 is to be performed. For example, the controller 204 can determine that the secure memory built-in self-test 112 is to be performed based on the presence of security-sensitive information within the memory 202 coupled to the controller 204. In this case, the controller 204 can cause the override circuit 206 to be in an active or an enabled state, and the process can continue at 704.

[0044] Alternatively, the controller 204 can determine that a normal memory built-in self-test can be performed based on the absence of security-sensitive information within the memory 202. In this case, the controller 204 can cause the override circuit 206 to be in an inactive or a disabled state, and the process can continue at 708.

[0045] In other implementations, the override circuit 206 may not be able to be disabled. In this case, the controller 204 performs the secure memory built-in self-test 112 by skipping 702 and proceeding directly to 704. At 704, the override circuit 206 compares the operation 404 of the first instruction 402-1 to the allowed operations 318. For example, the override circuit 206 compares a code that is associated with the operation 404 to codes associated with the allowed operations 318. The override circuit 206 can continue performing this comparison by looping through the set of allowed operations 318 until a match is found or optionally until all of the allowed operations in the set of allowed operations 318 have been evaluated.

[0046] At 706, the override circuit 206 determines if the operation 404 of the first instruction 402-1 is allowed (e.g., if the operation 404 of the first instruction 402-1 is one of the allowed operations 318). If the operation 404 is allowed, the process continues at 708. In this case, the override flag 508 is set to the second value and the controller 204 can proceed with executing the first instruction 402-1 without further modification.

[0047] At 708, the operation 404 of the first instruction 402-1 is sent to the finite-state machine 308 of the controller 204. For example, the override circuit 504 passes the operation 404 of the first instruction 402-1 to the finite-state machine 308 via the operation selection circuit 504 and via the mode selection circuit 306. At 710, the controller 204 performs (e.g., initiates or executes) a memory built-in self-test using the operation 404 of the first instruction 402-1. The memorv built-in self-test can be referred to as the secure memory built-in self-test as the override circuit 504 ensures the operation 404 of the first instruction 402-1 involves writing over the security-sensitive infonnation within the memory 202.

[0048] If the operation 404 is not allowed at 706, the process continues at 712. In this case, the override flag 508 is set to the first value and the override circuit 206 overwrites the operation 404 of the first instruction 402-1 with the default operation 510. The override circuit 206 can also overwrite the address scheme and control 406 with the default address scheme and control 512.

[0049] At 712, the default operation 510 is sent to the finite-state machine 308 of the controller 204. For example, the override circuit 504 passes the default operation 610 to the finite- state machine 308 via the operation selection circuit 504 and via the mode selection circuit 306. At 714, the controller 204 performs (e.g., initiates or executes) a memory built-in self-test using the default operation 510. In the above scheme 700, the memory built-in self-tests performed at 710 and 714 can be referred to as a secure memory built-in self-test 112 as the override circuit 504 ensures the security-sensitive information within the memory 202 is overwritten prior to executing a read operation associated with another instruction 402 (e.g., one of the instructions 402-2 to 402-N).

[0050] Consider an example in which the operation 404 of the first instruction 402-1 is a read operation 612, such as a read-all-zeros operation. At 706, the override circuit 706 determines that the read operation 612 is not one of the allowable operations 318. As such, the override circuit 706 causes the controller 204 to perform a write operation 604 instead. In this example, the overwriting of the operation 404 of the first instruction 402-1 with the default operation 510 can cause the controller 204 to perform a write-all-zeros operation. Other examples are also possible in which a read-all -ones operation of the first instruction 402-1 is modified by the override circuitat 712 to be a write-all-ones operation. In yet another example, a do-nothing operation (e.g., a NOP) becomes a write-all-zeros operation at 712.

[0051] Consider a different example in which to operation 404 of the first instruction 402-1 is one of the allowable operations 318. The operation 404 of the first instruction 402-1 can be a write- checkerboard-pattem operation, for instance. In this case, the override circuit 206 does not modify the first instruction 402-1 and instead passes the checkerboard-pattern operation to the finite-state machine 308.

[0052] For securing a memory' built-in self-test, the controller 204 ensures one of the allowable operations 318 (e.g., a write operation 604) is performed prior to performing one of the excluded operations 602 (e.g., a read operation 612). In the example described above with respect to FIGs. 5 and 7, the override circuit 206 performs this by evaluating, and sometimes overwriting, the operation 404 corresponding to the first instruction 402-1. Other implementations are also possible in which additional logic can be applied to the override circuit 206 to enable it to evaluate other instructions 402-2 to 402-N. This can be beneficial in situations in which the controller 204 supports partial write operations (e.g., write operations that are applied to a portion of the memory 202).

[0053] Consider an example in which the override circuit 206 continues evaluating instructions 402 until it identifies an instruction 402 associated with a read operation 612 or until it determines that one of the instructions 402 is a write operation 604 that overwrites the securitysensitive information within the memory 202. In this case, the override circuit 206 can have additional logic to allow it to loop through the instructions 402- 1 to 402-N and to determine if the address scheme and control 406 corresponding to an instruction 402 includes the addresses associated with the security-sensitive information. If the override circuit 206 determines that one of the instructions 402 has an operation 404 and an address scheme and control 406 that overwrites the security' sensitive information within the memory' 202 and occurs prior to another instruction 402 having a read operation 612, the override circuit 206 enables the instructions 402-1 to 402-N to be executed without modification. Alternatively, the override circuit 206 can modify’ an address scheme and control 406 associated with a partial write operation that occurs prior to the instruction 402 corresponding to the read operation 612 to ensure the security' sensitive information is overwritten. As another alternative, the override circuit 206 can overwrite the read operation 612 to be one of the allowable operations 318.Example Method

[0054] FIG. 8 depicts example method 800 for implementing aspects of securing a memon built- in self-test. Method 800 is show n as a set of operations (or acts) performed but not necessarily limited to the order or combinations in which the operations are shown herein. Further, any of one or more of the operations may be repeated, combined, reorganized, or linked to provide a wide array of additional and / or alternate methods. Tn portions of the following discussion, reference may be made to the environment 100 of FIG. 1, and entities detailed in FIG. 2 and 3, reference to which is made for example only. The techniques are not limited to performance by one entity or multiple entities operating on one device.

[0055] At 802 in FIG. 8, a set of programmable instructions associated with a memory built-in self-test is received. The set of programmable instructions comprise a first instruction that is to be executed prior to executing other instructions of the set of programmable instructions. For example, the controller 204 receives the programmable instructions 110 associated with a memon' built-in self-test, as shown in FIG. 3. The programmable instructions 110 comprise a first instruction 402-1 that is to be executed prior to executing other instructions (e.g., instructions 402-2 to 402-N), as shown in FIG. 4. In various situations, the programmable instructions 110 can be provided by the user 104, a technician of a repair shop, a test engineer of a manufacturer, or an unauthorized entity. The programmable instructions 110 can be stored within registers of the controller 204.

[0056] At 804 in FIG. 8, an operation corresponding to the first instruction is determined to differ from operations within a set of allowable operations. For example, the override circuit 206 determines that the operation 404 corresponding to the first instruction 402-1 differs (or is not included within) the allowable operations 318, as shown at 706 in FIG. 7. Example allowable operations 318 are described with respect to FIG. 6. Generally speaking, the override circuit 206 determines that the operation 404 corresponding to the first instruction 402-1 is allowed if the operation 404 corresponding to the first instruction 402-1 is some type of write operation 604 (e.g., is not some type of read operation 612). Other implementations are also possible in which the override circuit 206 determines that the operation 404 corresponding to the first instruction 402-1 is the same as one of the excluded operations 602 of FIG. 6.

[0057] At 806, the memory built-in self-test is performed using, based on the determining, a default operation instead of the operation corresponding to the first instruction. The default operation comprises an operation within the set of allowable operations. For example, the controller 204 performs the memoiy built-in self-test using, based on the determining, the default operation 510 instead of the operation 404 corresponding to the first instruction 404-1, as shownat 712 in FIG. 7. The default operation 510 comprises an operation within the allowable operations 318. For example, the default operation 510 can be some type of write operation 602, such as a standalone write operation 604. The method 800 can also include performing the memory built-in self-test using a default address scheme and control 512 instead of the address scheme and control 406 corresponding to the first instruction 402-1. The default address scheme and control 512 can ensure that at least the addresses that store the security-sensitive information have their data overwritten using the default operation 510. In some cases, the default address scheme and control 512 causes the controller 204 to overwrite all of the data stored within the memory 202 (e.g.. overwrite addresses that store the security-sensitive information and non- security-sensitive information).Example Computing System

[0058] FIG. 9 illustrates various components of an example computing system 900 that can be implemented as any type of client, server, and / or computing device as described with reference to the previous FIGs. 2 and 3 to implement aspects of securing a memory built-in self-test.

[0059] The computing system 900 includes communication devices 902 that enable wired and / or wireless communication of device data 904 (e.g., received data, data that is being received, data scheduled for broadcast, or data packets of the data). The device data 904 or other device content can include configuration settings of the device, media content stored on the device, and / or information associated with a user of the device. Media content stored on the computing system 900 can include any type of audio, video, and / or image data. The device data 904 can also include security-sensitive information, such as security keys (e g., user-specific keys), license keys, and / or personal information of the user 104. The computing system 900 includes one or more data inputs 906 via which any type of data, media content, and / or inputs can be received, including programmable instructions 110 received from any content and / or data source.

[0060] The computing system 900 also includes communication interfaces 908, which can be implemented as any one or more of a serial and / or parallel interface, a wireless interface, any type of network interface, a modem, and as any other type of communication interface. The communication interfaces 908 provide a connection and / or communication links between the computing system 900 and a communication network by which other electronic, computing, and communication devices communicate data with the computing system 900.

[0061] The computing system 900 includes one or more processors 910 (e.g., any of microprocessors, controllers, and the like), which process various computer-executable instructions to control the operation of the computing system 900. Alternatively or in addition,the computing system 900 can be implemented with any one or combination of hardware, firmware, or fixed logic circuitry that is implemented in connection with processing and control circuits which are generally identified at 912. Although not shown, the computing system 900 can include a system bus or data transfer system that couples the various components within the device. A system bus can include any one or combination of different bus structures, such as a memory bus or memory controller, a peripheral bus, a universal serial bus, and / or a processor or local bus that utilizes any of a variety of bus architectures.

[0062] The computing system 900 also includes a computer-readable medium 914, such as one or more memory devices that enable persistent and / or non-transitory data storage (i. e. , in contrast to mere signal transmission), examples of which include random access memory (RAM), non-volatile memory (e.g., any one or more of a read-only memory (ROM), flash memory, EPROM, EEPROM, etc.), and a disk storage device. The disk storage device may be implemented as any type of magnetic or optical storage device, such as a hard disk drive, a recordable and / or rewriteable compact disc (CD), any type of a digital versatile disc (DVD), and the like. The computing system 900 can also include a mass storage medium device (storage medium) 916.

[0063] The computer-readable medium 914 provides data storage mechanisms to store the device data 904, as well as various device applications 918 and any other types of information and / or data related to operational aspects of the computing system 900, including the programmable instructions 110. For example, an operating system can be maintained as a computer application with the computer-readable medium 914 and executed on the processors 910. The device applications 918 may include a device manager, such as any form of a control application, software application, signal-processing and control module, code that is native to a particular device, a hardware abstraction layer for a particular device, and so on. The computer system 900 also includes any system components, engines, or managers to implement the override circuit 206.

[0064] Throughout this disclosure, examples are described where a computing system 900 (e.g., the computing device 102, a client device, a server device, a computer, or another type of computing system) may store security-sensitive information (e.g.. various audible and / or ultrasound signals) associated with a user and / or the computing system 900. Further to the descriptions above, a user 104 may be provided with controls allowing the user 104 to make an election as to both if and when systems, programs, and / or features described herein may enable storage of security-sensitive information (e.g., information about a user’s social network, social actions, social activities, profession, a user’s preferences, a user’s current location), and if the user 104 is sent content or communications from a server. The computing system 900 can be configured to only use the information after the computing system 900 receives explicitpermission from the user 104 to use the data. For example, individual users 104 may be provided with an opportunity to provide input to control whether programs or features of the computing system 900 can collect and make use of the data. Further, individual users 104 may have constant control over what programs can or cannot do with the information.

[0065] In addition, information collected may be pre-treated in one or more ways before it is transferred, stored, or otherwise used, so that personally-identifiable information is removed. For example, before the computing system 900 shares data with another device, a user 104’s identity may be treated so that no personally identifiable information can be determined for the user 104. Thus, the user 104 may have control over whether information is collected about the user 104 and the user 104’s device, and how such information, if collected, may be used by the computing system 900 and / or a remote computing system.Conclusion

[0066] Although techniques using, and apparatuses including, securing a memory built-in selftest have been described in language specific to features and / or methods, it is to be understood that the subject of the appended claims is not necessarily limited to the specific features or methods described. Rather, the specific features and methods are disclosed as example implementations of securing a memory built-in self-test.

[0067] Some Examples are described below. Features of any of the embodiments described above can be combined with any of these examples.

[0068] Example 1 : A method performed by a controller, the method comprising: receiving a set of programmable instructions associated with a memory’ built-in self-test, the set of programmable instructions comprising a first instruction that is to be executed prior to executing other instructions of the set of programmable instructions; determining that an operation corresponding to the first instruction differs from operations within a set of allowable operations; and performing, based on the determining, the memory’ built-in self-test using a default operation instead of the operation corresponding to the first instruction, the default operation comprising an operation within the set of alloyvable operations.

[0069] Example 2: The method of example 1, wherein the performing of the memory built-in selftest using the default operation comprises ovenvriting at least a portion of a memory that stores security-sensitive data.

[0070] Example 3: The method of example 2, wherein the ovenvriting further comprises overw riting at least a second portion of the memory that stores non-security-sensitive data.

[0071] Example 4: The method of example 2 or 3, wherein the security-sensitive data comprises user-specific keys.

[0072] Example 5: The method of any previous example, wherein the performing of the memoi)' built-in self-test comprises using a default address scheme and control instead of an address scheme and control corresponding to the first instruction.

[0073] Example 6: The method of any previous example, wherein: the operation corresponding to the first instruction comprises a read operation; and the default operation comprises a write operation.

[0074] Example 7: The method of example 6. wherein the write operation comprises: a standalone write operation; a w rite-read-co pare operation; or a write-fast operation.

[0075] Example 8: The method of example 6 or 7, wherein the read operation comprises: a standalone read operation; a read-modify -write operation; or a read-write-read invert operation.

[0076] Example 9: The method of any previous example, further comprising: receiving a second set of programmable instructions associated with a second memory’ built-in self-test, the second set of programmable instructions comprising a first instruction that is to be executed prior to executing other instructions of the second set of programmable instructions; determining that an operation corresponding to the first instruction of the second set of programmable instructions is similar to one of the operations within the set of allowable operations; and performing, based on the determining that the operation corresponding to the first instruction of the second set of programmable instructions is similar to one of the operations within the set of allowable operations, the memory built-in self-test using the first instruction of the second set of programmable instructions.

[0077] Example 10: The method of any previous example, further comprising: determining that the controller is coupled to a memory that stores security-sensitive information; and comparing, based on the determining that the controller is coupled to the memory, the operation corresponding to the first instruction to the operations within the set of allowable operations,wherein the determining that the operation corresponding to the first instruction differs from the operations within the set of allowable operations is based on the comparing.

[0078] Example 11 : The method of any previous example, further comprising: storing the set of programmable instructions within a set of registers of the controller.

[0079] Example 12: An apparatus comprising: an integrated circuit comprising a memory and a controller, the integrated circuit configured to perform, using the controller and the memory', any one of the methods of examples 1 to I E

[0080] Example 13: The apparatus of example 12, wherein the controller comprises: at least one register configured to store the first instruction; at least one finite-state machine configured to perform the memory built-in self-test on the memory7; and at least one override circuit coupled between the at least one register and the at least one finite-state machine, the at least one override circuit configured to pass the default operation to the at least one finite-state machine instead of the operation corresponding to the first instruction based on the determining that the operation corresponding to the first instruction differs from the operations within the set of allowable operations.

[0081] Example 14: The apparatus of example 13, wherein the override circuit comprises: at least one comparator circuit coupled to the at least one register; and at least one operation selection circuit having a control input coupled to an output of the at least one comparator circuit and having an output coupled to the at least one finite-state machine.

[0082] Example 15: A computer-readable storage medium comprising instructions that, responsive to execution by' a controller, cause the controller to perform any one of the methods of examples 1-11.

Claims

CLAIMSWhat is claimed is:

1. A method performed by a controller, the method comprising: receiving a set of programmable instructions associated with a memory built-in self-test, the set of programmable instructions comprising a first instruction that is to be executed prior to executing other instructions of the set of programmable instructions; determining that an operation corresponding to the first instruction differs from operations within a set of allowable operations; and performing, based on the determining, the memory built-in self-test using a default operation instead of the operation corresponding to the first instruction, the default operation comprising an operation within the set of allowable operations.

2. The method of claim 1, wherein the performing of the memory built-in self-test using the default operation comprises overwriting at least a portion of a memory that stores securitysensitive data.

3. The method of claim 2, wherein the overwriting further comprises overwriting at least a second portion of the memory that stores non-security-sensitive data.

4. The method of claim 2 or 3, wherein the security-sensitive data comprises user-specific keys.

5. The method of any previous claim, wherein the performing of the memory built-in selftest comprises using a default address scheme and control instead of an address scheme and control corresponding to the first instruction.

6. The method of any previous claim, wherein: the operation corresponding to the first instruction comprises a read operation; and the default operation comprises a write operation.

7. The method of claim 6, wherein the write operation comprises: a standalone write operation; a write-read-compare operation; or a write-fast operation.

8. The method of claim 6 or 7, wherein the read operation comprises: a standalone read operation; a read-modify -write operation; or a read-write-read invert operation.

9. The method of any previous claim, further comprising: receiving a second set of programmable instructions associated with a second memory' built-in self-test, the second set of programmable instructions comprising a first instruction that is to be executed prior to executing other instructions of the second set of programmable instructions; determining that an operation corresponding to the first instruction of the second set of programmable instructions is similar to one of the operations within the set of allowable operations; and performing, based on the determining that the operation corresponding to the first instruction of the second set of programmable instructions is similar to one of the operations within the set of allowable operations, the memory built-in self-test using the first instruction of the second set of programmable instructions.

10. The method of any previous claim, further comprising: determining that the controller is coupled to a memory that stores security-sensitive information; and comparing, based on the determining that the controller is coupled to the memory, the operation corresponding to the first instruction to the operations within the set of allowable operations, wherein the determining that the operation corresponding to the first instruction differs from the operations within the set of allowable operations is based on the comparing.

11. The method of any previous claim, further comprising: storing the set of programmable instructions within a set of registers of the controller.

12. An apparatus comprising: an integrated circuit comprising a memory and a controller, the integrated circuit configured to perform, using the controller and the memory. any one of the methods of claims 1 to 11.

13. The apparatus of claim 12, wherein the controller comprises: at least one register configured to store the first instruction; at least one finite-state machine configured to perform the memory' built-in self-test on the memory; and at least one override circuit coupled between the at least one register and the at least one finite-state machine, the at least one override circuit configured to pass the default operation to the at least one finite-state machine instead of the operation corresponding to the first instruction based on the determining that the operation corresponding to the first instruction differs from the operations within the set of allowable operations.

14. The apparatus of claim 13, wherein the override circuit comprises: at least one comparator circuit coupled to the at least one register; and at least one operation selection circuit having a control input coupled to an output of the at least one comparator circuit and having an output coupled to the at least one finite-state machine.

15. A computer-readable storage medium comprising instructions that, responsive to execution by a controller, cause the controller to perform any one of the methods of claims 1-1 1.

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