Asynchronous deployment method for computing task of hardware acceleration unit, and heterogeneous computing terminal, apparatus, medium, and program product

Abstract

Provided in the present application are an asynchronous deployment method for a computing task of a hardware acceleration unit, and a heterogeneous computing terminal, an apparatus, a medium, and a program product. By means of asynchronously deploying a computing task of a hardware acceleration unit, the task deployment of a control unit and the task execution of the hardware acceleration unit can be synchronously performed, and systems no longer need to wait for each other, thereby improving the resource utilization rate, the throughput and the computing efficiency of each system. In addition, the hardware acceleration unit automatically jumps to a next computing task after the deployment is completed, thereby further improving the utilization rate of the hardware acceleration unit. Such a processing method not only reduces the waiting time of each system, but also accelerates the response speed of each system, improves the stability, enhances the adaptability of each system, and better meets different computing scenarios and task requirements.

Description

Asynchronous deployment method of hardware acceleration unit computing task, heterogeneous computing terminal, device, medium and program product TECHNICAL FIELD

[0001] The present application relates to the field of digital data processing, in particular to an asynchronous deployment method of hardware acceleration unit computing task, a heterogeneous computing terminal, a device, a medium and a program product. BACKGROUND

[0002] The deployment of a hardware acceleration unit refers to deploying specific algorithms or computing tasks to specific hardware devices so that these tasks can be run on the devices and perform inference or computation. The synchronous deployment method refers to the need for synchronization between the hardware acceleration unit and the control unit, that is, the hardware acceleration unit is in a blocked state before the control unit deploys a task; after the hardware acceleration unit finishes executing a task, the control unit deploys the next task. Figure 1 shows a flowchart of the deployment method in the prior art. When there is one or more tasks in the task pool, the system reads a task from the task pool according to the priority and other attributes of the task, and deploys it to the hardware acceleration unit according to the task description. After the hardware acceleration unit starts executing the task, the control unit waits for the hardware acceleration unit to finish executing, then obtains the task result and performs subsequent processing. Finally, the above steps are repeated until the task pool is empty.

[0003] However, the existing deployment method has some defects. During the process of submitting a task from the control unit to the hardware acceleration unit, the work of the control unit and the hardware acceleration unit is synchronous, and there is a problem of mutual waiting between the two. The hardware acceleration unit needs to wait for the control unit to deploy the task before it can start executing, while the control unit needs to wait for the hardware acceleration unit to finish executing before it can read the result and deploy the next task. The control unit needs to participate in scheduling before the hardware acceleration unit finishes executing the current task and starts executing the next task. During the period when the control unit participates in task scheduling, the hardware acceleration unit is in an idle state, resulting in a decrease in the utilization rate of the hardware acceleration unit. In addition, after the hardware acceleration unit finishes executing a task, the control unit senses the completion of the task and performs the process of result reading and subsequent processing, during which the hardware acceleration unit is still in an idle state. This mutual waiting and scheduling delay results in a large waste of hardware resources of the hardware acceleration unit, especially in the case of heavy tasks.

[0004] SUMMARY

[0005] In view of the above-mentioned defects of the prior art, the purpose of the present application is to provide an asynchronous deployment method of hardware acceleration unit computing task, a heterogeneous computing terminal, a device, a medium and a program product, which solves the problem of the idle state of the hardware acceleration unit caused by the mutual waiting between the control unit and the hardware acceleration unit in the existing synchronous deployment method, reduces the utilization rate of the hardware acceleration unit, and causes waste of hardware resources.

[0006] To achieve the above object and other related objects, the first aspect of the present application provides a method for asynchronously deploying a computing task of a hardware acceleration unit, applied to a control unit, which comprises the following steps: first, reading a computing task from a task pool and deploying the computing task to the hardware acceleration unit in a standard deployment mode so that the hardware acceleration unit performs a corresponding operation on the computing task, and writing the identification information corresponding to the computing task into a waiting queue; then, performing the following operations in parallel: reading a next computing task from the task pool as a current computing task, deploying the current computing task to the hardware acceleration unit asynchronously so that the hardware acceleration unit performs a corresponding operation on the current computing task, and writing the identification information corresponding to the current computing task into the waiting queue; continuing to perform the operations of reading a next computing task, deploying the next computing task to the hardware acceleration unit, and writing the identification information corresponding to the next computing task into the waiting queue until the task pool is empty; reading an identification information from the waiting queue as a current identification information in sequence, detecting whether an interrupt signal corresponding to the current identification information sent by the hardware acceleration unit is received, if the interrupt signal is received, obtaining an operation result of a corresponding computing task based on the current identification information, and continuing to perform the operations of reading a next identification information, detecting whether an interrupt signal corresponding to the next identification information sent by the hardware acceleration unit is received, and obtaining an operation result of a corresponding computing task based on the next identification information until the waiting queue is empty; if the interrupt signal is not received, continuing to wait until the interrupt signal corresponding to the current identification information sent by the hardware acceleration unit is received.

[0007] In some embodiments of the first aspect of the present application, the method further comprises the following step: after deploying the current computing task to the hardware acceleration unit asynchronously, inserting a jump instruction at the end of the instruction of the previous computing task, wherein the target address of the jump instruction is the starting address of the current computing task, so that the hardware acceleration unit automatically jumps to the current computing task and performs the operation after the operation of the previous computing task is completed.

[0008] In some embodiments of the first aspect of the present application, the task content of each computing task comprises an operation type, operation data, and control instructions; the type of the control instructions comprises: an operation execution instruction, which is an instruction for instructing the hardware acceleration unit to perform a corresponding operation on the current computing task; a task completion instruction, which is an instruction for instructing the hardware acceleration unit to send a message to the control unit that the current computing task has been completed; and a jump instruction, which is an instruction for instructing the hardware acceleration unit to directly jump to the next computing task after the operation of the current computing task is completed.

[0009] In some embodiments of the first aspect of the present disclosure, the hardware acceleration unit comprises a plurality of cores, and the process of deploying the current computing task asynchronously into the hardware acceleration unit for the hardware acceleration unit to perform corresponding operation on the current computing task comprises: determining whether one or more cores for deploying the current computing task are in an idle state; if the one or more cores are all in the idle state, deploying the current computing task into the hardware acceleration unit in a standard deployment manner; otherwise, deploying the current computing task into the hardware acceleration unit asynchronously.

[0010] In some embodiments of the first aspect of the present disclosure, the computing task comprises a plurality of different operation data and computing tasks of the same computing type.

[0011] In some embodiments of the first aspect of the present disclosure, the process of deploying a plurality of different operation data and computing tasks of the same computing type asynchronously comprises: deploying a first computing task into the hardware acceleration unit in a standard deployment manner to perform corresponding computing operation; after detecting that the hardware acceleration unit has executed the running of the input / output related instruction in the first computing task, modifying the input data of the current computing task, and generating a next computing task, deploying the next computing task into the hardware acceleration unit in an asynchronous deployment manner to perform corresponding computing operation; and continuing to perform the process of modifying the input data of the current computing task and performing corresponding computing operation after detecting that the hardware acceleration unit has executed the running of the input / output related instruction in the current computing task until a preset termination condition is met.

[0012] In some embodiments of the first aspect of the present disclosure, the preset termination condition comprises one or more of the following combinations of termination conditions: terminating the operation after the input data of the first computing task is modified for a preset number of times; terminating the operation when the total time length of the computing operation performed by the hardware acceleration unit reaches a preset time length; and terminating the operation when the computing resource in the hardware acceleration unit is lower than a preset standard.

[0013] In some embodiments of the first aspect of the present disclosure, when the current computing task is the last computing task in the waiting queue, the last instruction of the current computing task is an end instruction.

[0014] In some embodiments of the first aspect of the present disclosure, the identification information comprises a memory address, and the process of obtaining the operation result of the corresponding computing task based on the current identification information comprises: reading the operation result in the current memory address from the memory.

[0015] To achieve the above object and other related objects, the second aspect of the present application provides a heterogeneous computing terminal, comprising a control unit and a hardware acceleration unit, and the control unit and the hardware acceleration unit comprise the following interaction process: first, the control unit reads a computing task from a task pool and deploys the computing task to the hardware acceleration unit in a standard deployment manner so that the hardware acceleration unit performs a corresponding operation on the computing task, and writes identification information corresponding to the computing task into a waiting queue; subsequently, the following operations are performed in parallel: the control unit reads a next computing task from the task pool as a current computing task, deploys the current computing task to the hardware acceleration unit asynchronously, the hardware acceleration unit performs a corresponding operation on the current computing task, the control unit writes identification information corresponding to the current computing task into the waiting queue; the control unit continues to perform the operations of reading a next computing task, deploying the next computing task to the hardware acceleration unit, and writing identification information corresponding to the next computing task into the waiting queue until the task pool is empty; the control unit reads an identification information from the waiting queue as a current identification information in sequence, detects whether an interrupt signal corresponding to the current identification information sent by the hardware acceleration unit is received, if the control unit receives the interrupt signal, obtains an operation result of a corresponding computing task based on the current identification information, and continues to perform the operations of reading a next identification information, detecting whether an interrupt signal corresponding to the next identification information sent by the hardware acceleration unit is received, and obtaining an operation result of a corresponding computing task based on the next identification information until the waiting queue is empty; if the control unit does not receive the interrupt signal, continues to wait until the interrupt signal corresponding to the current identification information sent by the hardware acceleration unit is received.

[0016] In some embodiments of the second aspect of the present application, the task content of each computing task comprises an operation type, operation data, and a control instruction; the type of the control instruction comprises: an operation execution instruction, an instruction for instructing the hardware acceleration unit to perform a corresponding operation on the current computing task; a task completion instruction, an instruction for instructing the hardware acceleration unit to send the control unit that the current computing task has been completed; and a jump instruction, an instruction for instructing the hardware acceleration unit to directly jump to a next computing task completed by the asynchronous deployment after the operation of the current computing task is completed.

[0017] In some embodiments of the second aspect of the present application, the interaction process of the terminal further comprises: after the current computing task is deployed to the hardware acceleration unit asynchronously, a jump instruction is inserted at the end of the instruction of the previous computing task, the target address of the jump instruction is the starting address of the current computing task, so that the hardware acceleration unit automatically jumps to the current computing task and performs after the operation of the previous computing task is completed.

[0018] In some embodiments of the second aspect of the present application, the hardware acceleration unit comprises a plurality of cores, and the process of asynchronously deploying the current computing task into the hardware acceleration unit for the hardware acceleration unit to perform corresponding operation on the current computing task comprises: judging whether one or more cores used for deploying the current computing task are in an idle state; if the one or more cores are all in the idle state, deploying the current computing task into the hardware acceleration unit in a standard deployment manner; otherwise, asynchronously deploying the current computing task into the hardware acceleration unit.

[0019] In some embodiments of the second aspect of the present application, the computing task comprises a plurality of different operation data and computing tasks of the same computing type.

[0020] In some embodiments of the second aspect of the present application, the process of asynchronously deploying the plurality of different operation data and computing tasks of the same computing type comprises: deploying a first computing task into the hardware acceleration unit in a standard deployment manner to perform corresponding computing operation; after detecting that the hardware acceleration unit has executed the running of an input / output related instruction in the first computing task, modifying the input data of the current computing task, and generating a next computing task, deploying the next computing task into the hardware acceleration unit in an asynchronous deployment manner to perform corresponding computing operation; and continuing to perform the process of modifying the input data of the current computing task and performing corresponding computing operation after detecting that the hardware acceleration unit has executed the running of an input / output related instruction in the current computing task until a preset termination condition is met.

[0021] In some embodiments of the second aspect of the present application, the preset termination condition comprises one or more of the following termination conditions: terminating the operation after the input data of the first computing task is modified for a preset number of times; terminating the operation when the total time length of the computing operation performed by the hardware acceleration unit reaches a preset time length; and terminating the operation when the computing resource in the hardware acceleration unit is lower than a preset standard.

[0022] In some embodiments of the second aspect of the present application, when the current computing task is the last computing task in the waiting queue, the last instruction of the current computing task is an end instruction.

[0023] In some embodiments of the second aspect of the present application, the identification information comprises a memory address, and the process of obtaining the operation result of the corresponding computing task based on the current identification information comprises: reading the operation result in the current memory address from the memory.

[0024] To achieve the above object and other related objects, the third aspect of the present application provides an asynchronous deployment device of a hardware acceleration unit computing task, comprising: a task acquisition module, configured to read a computing task from a task pool, and deploy the computing task to a hardware acceleration unit in a standard deployment mode so that the hardware acceleration unit performs a corresponding operation on the computing task, and write identification information corresponding to the computing task into a waiting queue; a task deployment module, configured to read a next computing task from the task pool as a current computing task, deploy the current computing task to the hardware acceleration unit asynchronously so that the hardware acceleration unit performs a corresponding operation on the current computing task, and write identification information corresponding to the current computing task into the waiting queue; continue to perform the operations of reading a next computing task, deploying the next computing task to the hardware acceleration unit, and writing identification information corresponding to the next computing task into the waiting queue until the task pool is empty; and a result waiting module, configured to read an identification information from the waiting queue as a current identification information in sequence, detect whether an interrupt signal corresponding to the current identification information sent by the hardware acceleration unit is received, if the interrupt signal is received, acquire an operation result of a corresponding computing task based on the current identification information, and continue to perform the operations of reading a next identification information, detecting whether an interrupt signal corresponding to the next identification information sent by the hardware acceleration unit is received, and acquiring an operation result of a corresponding computing task based on the next identification information until the waiting queue is empty; and if the interrupt signal is not received, continue to wait until the interrupt signal corresponding to the current identification information sent by the hardware acceleration unit is received.

[0025] To achieve the above object and other related objects, the fourth aspect of the present application provides a computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to implement the asynchronous deployment method of the hardware acceleration unit computing task.

[0026] To achieve the above object and other related objects, the fifth aspect of the present application provides a computer program product, which comprises computer program codes, and when the computer program codes are run on a computer, the computer program codes make the computer implement the asynchronous deployment method of the hardware acceleration unit computing task.

[0027] The hardware acceleration unit computing task asynchronous deployment method, the heterogeneous computing terminal, the device, the medium and the program product of the present application have the following beneficial effects: by deploying the computing task of the hardware acceleration unit asynchronously, the task deployment of the control unit and the task execution of the hardware acceleration unit can be performed asynchronously, the system no longer needs to wait for each other, thereby improving the resource utilization, throughput and computing efficiency of the system, and improving the utilization rate of the hardware acceleration unit. This way can also reduce the waiting time of the system, improve the response speed and stability of the system, make the system more adaptive, and better meet different computing scenarios and task requirements. BRIEF DESCRIPTION OF DRAWINGS

[0028] FIG. 1 shows a flowchart of a prior art hardware acceleration unit computing task asynchronous deployment method.

[0029] FIG. 2 shows a flowchart of an embodiment of the hardware acceleration unit computing task asynchronous deployment method of the present application.

[0030] FIG. 3 shows a flowchart of another embodiment of the hardware acceleration unit computing task asynchronous deployment method of the present application.

[0031] FIG. 4 shows a flowchart of repeating the same task in an embodiment of the hardware acceleration unit computing task asynchronous deployment method of the present application.

[0032] FIG. 5 shows a flowchart of instructions in an embodiment of the hardware acceleration unit computing task asynchronous deployment method of the present application.

[0033] FIG. 6 shows a task time diagram of a prior art hardware acceleration unit computing task asynchronous deployment method.

[0034] FIG. 7 shows a task time diagram of an embodiment of the hardware acceleration unit computing task asynchronous deployment method of the present application.

[0035] FIG. 8 shows a flowchart of multi-core hardware acceleration unit instructions in an embodiment of the hardware acceleration unit computing task asynchronous deployment system of the present application.

[0036] FIG. 9 shows a structural diagram of an embodiment of the hardware acceleration unit computing task asynchronous deployment device of the present application. DETAILED DESCRIPTION

[0037] The present application can be implemented or applied in other different specific embodiments, and various modifications or changes can be made to the details of the present application based on different views and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0038] Before the present application is further described, the terms and terminology used in the embodiments of the present application are explained, and the terms and terminology used in the embodiments of the present application are applicable to the following explanations:

[0039] <1> Hardware acceleration unit: a hardware component specially designed to perform specific types of computing tasks, achieving high efficiency acceleration through specific hardware structure and instruction set. By combining with control units such as CPUs, a heterogeneous computing platform is built to improve computing efficiency and performance. Common hardware acceleration units include GPUs (Graphics Processing Units) and TPUs (Tensor Processing Units) and the like.

[0040] <2> Control unit: the control unit includes but is not limited to CPU (Central Processing Unit), MCU (Microcontroller) and the like, which is used to coordinate and manage various parts of the computer or device, control and operate the hardware acceleration unit, so as to ensure that the instructions are effectively executed, and then optimize the system performance and response speed.

[0041] <3> Asynchronous deployment: the process of deploying tasks by the control unit and executing tasks by the hardware acceleration unit is asynchronous, and the control unit does not need to wait for the hardware acceleration unit to complete the current task.

[0042] <4> Task queue: a data structure used to store and manage tasks to be executed, usually using a first-in first-out (FIFO) method to manage the execution order of tasks.

[0043] <5> Operation instruction: an instruction used to control the basic operation of the processor, such as addition, subtraction, multiplication, division and the like.

[0044] <6> Task completion instruction: an instruction used by the hardware acceleration unit to notify the control unit, usually an interrupt.

[0045] <7> Jump instruction: an instruction used to change the program execution flow, instructing the hardware acceleration unit to jump to the specified program address for execution.

[0046] For the convenience of understanding the embodiments of the present application, first, a detailed description is made in combination with FIG. 2. FIG. 2 shows a flowchart of a method for asynchronously deploying a hardware acceleration unit computing task according to an embodiment of the present application. The method for asynchronously deploying a hardware acceleration unit computing task according to the embodiment mainly includes the following steps:

[0047] Step S21: First, a computing task is read from a task pool, and the computing task is deployed to a hardware acceleration unit in a standard deployment manner so that the hardware acceleration unit performs a corresponding operation on the computing task, and the identification information corresponding to the computing task is written into a waiting queue; subsequently, step S22 and step S23 are executed in parallel.

[0048] In an embodiment of the present application, the hardware acceleration unit is a special hardware IP core, which is designed to provide hardware acceleration functions for specific operation tasks to improve computing performance and energy efficiency. It includes but is not limited to neural network processing IP (NPU-Neural Network Processing Unit), visual processing IP (VPU-Vision Processing Unit IP), audio processing IP (APU-Audio Processing Unit IP), encryption processing IP (CEU-Cryptography Engine Unit IP), image / video coding IP (VDEC / VENC-Video Decoder / Encoder IP), and image / video coding IP (VDEC / VENC-Video Decoder / Encoder IP) and other hardware acceleration units. These special computing IPs are similar to NPU processors, which are IP cores optimized for certain specific application scenarios. Compared with general arithmetic logic unit IP (ALU IP) and floating point operation unit IP (FPU IP), the hardware acceleration unit can significantly improve the computing performance and energy efficiency of related tasks.

[0049] In an embodiment of the present application, the method further includes: after the current computing task is asynchronously deployed to the hardware acceleration unit, a jump instruction is inserted at the end of the instruction of the previous computing task, and the target address pointed to by the jump instruction is the starting address of the current computing task, so that the hardware acceleration unit automatically jumps to the current computing task and executes after the previous computing task is executed.

[0050] In this embodiment, the control unit is a CPU processor responsible for core computing tasks, while the hardware acceleration unit handles specific operations such as graphics rendering and machine learning. The CPU processor and the hardware acceleration unit interact through a high-speed bus, enabling low-latency and high-bandwidth data transmission. The CPU processor allocates complex tasks to the hardware acceleration unit, which processes the results and feeds them back to the CPU processor, completing data processing and control logic.

[0051] It should be noted that the deployment of the CPU processor and the execution of the hardware acceleration unit are asynchronous processes. When the CPU processor is deployed, the instructions of the previous computing task are modified, and a jump instruction is inserted at the end of the previous computing task, causing it to jump to the starting address of the current computing task, and then the CPU processor deployment ends. When the hardware acceleration unit executes the previous computing task to the end, it parses the jump instruction and jumps to the current computing task to start execution. In this process, the hardware acceleration unit does not need the participation of the CPU processor, but only reads instructions from memory and executes them. Instructions stored in memory include, for example, synchronization instructions, computing instructions, and end instructions. During deployment, the CPU processor modifies some instructions to enable correct jumping between computing tasks. For example, a task initially generates 1000 instructions, including different types of instructions. During asynchronous deployment, the CPU processor modifies some of the instructions, such as adding jump instructions or end instructions to achieve the asynchronous deployment process described above.

[0052] As shown in FIG. 3, a flowchart of the asynchronous deployment method of the hardware acceleration unit computing task in an embodiment of the present application is shown. In this embodiment, one or more computing tasks that need to be executed by the hardware acceleration unit are stored in the task pool. First, according to the priority order, a task with the highest priority is read from the task pool, which is used as the first task executed by the hardware acceleration unit, and the first task is deployed to the hardware acceleration unit through a standard deployment method for the hardware acceleration unit to execute the corresponding operation. At this time, the hardware acceleration unit is in a busy state. In this state, the hardware acceleration unit can be asynchronously deployed, but the hardware acceleration unit cannot execute operations on other tasks. Therefore, the present application sets up an asynchronous deployment module containing a waiting module and a deployment module for asynchronously deploying the hardware acceleration unit in a busy state to improve the utilization of the hardware acceleration unit. To distinguish between the deployment operation performed by the hardware acceleration unit in an idle state and the deployment operation performed by the hardware acceleration unit in a busy state, the process of deploying the first task in an idle state is called "standard deployment", while the process of deploying subsequent computing tasks in a busy state is called "asynchronous deployment".

[0053] The "standard deployment" refers to a sequential deployment manner, i.e., each step has to wait for the previous step to be completed before proceeding to the next step. In this traditional deployment manner, there can be a mutual waiting situation between the control unit and the hardware acceleration unit, i.e., a step needs the processing result of the control unit to be delivered to the hardware acceleration unit, and waits for the hardware acceleration unit to complete the processing before proceeding to the next step. This can cause some delay and inefficiency in the deployment process. Therefore, compared with the asynchronous deployment, the standard deployment manner can cause more waiting time and resource waste.

[0054] In an embodiment of the present application, the task content of each computing task includes an operation type, operation data, and a control instruction; and the type of the control instruction includes an operation execution instruction, a task completion instruction, and a jump instruction. The operation execution instruction is used to instruct the hardware acceleration unit to perform a corresponding operation on the current computing task. The task completion instruction is used to instruct the hardware acceleration unit to send a message to the control unit that the current computing task has been completed. The jump instruction is used to instruct the hardware acceleration unit to directly jump to the next computing task after the current computing task is completed.

[0055] In an embodiment of the present application, the computing task includes a plurality of computing tasks of different operation data and the same computing type. Specifically, in the fields of image processing, speech recognition, natural language processing, machine learning, deep learning, high-performance computing, cryptography, and scientific computing, the hardware acceleration unit needs to perform the same operation on a large amount of data multiple times. In order to improve efficiency, the asynchronous deployment method of the hardware acceleration unit computing task provided by the present application can perform the same operation on different data. Specifically, the same operation tasks for different data are respectively named as a first task and a second task. When the control unit completes the deployment of the first task, and detects that the hardware acceleration unit has completed the running of the input / output related instruction in the first task, the control unit modifies the input / output related instruction in the first task in a preset manner to generate the second task. Then, the control unit deploys the second task to the hardware acceleration unit again to enable the hardware acceleration unit to perform the task twice in succession, but each time using different input and output. As shown in FIG. 4, the control unit first deploys task 0. When the hardware acceleration unit completes the input / output instruction of task 0, the control unit modifies the input / output instruction contained in task 0. When the hardware acceleration unit completes the computing task, the jump instruction is executed and jumps to the updated input / output instruction to read new data. Then, task 0 is deployed and calculated again based on the updated data, so as to enable the hardware acceleration unit to perform the same type of computing task twice in succession, and each time using different input and output.

[0056] Further, the process of asynchronously deploying a plurality of different computing data and the same computing type of computing includes: deploying a first computing task in a standard deployment manner to the hardware acceleration unit to perform a corresponding computing operation; after detecting that the hardware acceleration unit has completed execution of the input / output related instructions in the first computing task, modifying the input data of the current computing task, and generating a next computing task, deploying the next computing task to the hardware acceleration unit in an asynchronous deployment manner to perform a corresponding computing operation; and continuing to perform the operation of modifying the input data of the current computing task and performing a corresponding computing operation after detecting that the hardware acceleration unit has completed execution of the input / output related instructions in the current computing task until a preset termination condition is met.

[0057] Preferably, the preset termination condition includes one or a combination of the following termination conditions: terminating the operation after the input data of the first computing task is modified a preset number of times; terminating the operation when the total duration of the computing operation performed by the hardware acceleration unit reaches a preset duration; and terminating the operation when the computing resources in the hardware acceleration unit are below a preset standard. The computing resources in the hardware acceleration unit include, but are not limited to, insufficient memory and high usage of the hardware acceleration unit. When it is detected that the preset termination condition is met, the last instruction in the input data of the current computing task is modified to an end instruction to terminate the operation.

[0058] Illustratively, in an image classification task, the NPU can first process a picture of a cat and identify that the picture category is "cat". Subsequently, the control unit modifies the input picture address and transmits a second picture address (e.g., a picture of a dog) to the NPU and deploys the task again. At this time, the NPU will process the second picture and identify that the picture category is "dog". Through this preset modification manner, the control unit can quickly generate a new task and deploy it to the NPU to achieve the same processing of different data.

[0059] Step S22: reading a next computing task from the task pool as a current computing task, asynchronously deploying the current computing task to the hardware acceleration unit for the hardware acceleration unit to perform a corresponding computing operation on the current computing task, and writing identification information corresponding to the current computing task into the waiting queue; and continuing to perform the operations of reading a next computing task, deploying the next computing task to the hardware acceleration unit, and writing identification information corresponding to the next computing task into the waiting queue until the task pool is empty.

[0060] In an embodiment of the present application, the asynchronous deployment of the current computing task to the hardware acceleration unit comprises the following steps: when the hardware acceleration unit is busy, the computing tasks are read from the task pool in order of priority from high to low. For each computing task, the task is deployed to the hardware acceleration unit according to the description information contained in the computing task. The asynchronous deployment process of the computing task is shown in FIG. 5, and each computing instruction contains three types of instructions: task operation instruction, task completion instruction and jump instruction. In particular, for the last computing task in the waiting queue, the last instruction is an end instruction. Each instruction is used to let the hardware acceleration unit execute the corresponding operation.

[0061] More preferably, when the current computing task is the last computing task in the waiting queue, the last instruction of the current computing task is an end instruction.

[0062] It is worth noting that for each computing task in the present application, the jump instruction is contained at the end of the instruction set. When the computing task executes the task execution instruction and the task completion instruction, the jump instruction is used to jump to a specific target address, so as to jump to the starting address of the next computing task instruction, thereby completing the jump between the previous and next tasks. Specifically, when the hardware acceleration unit finishes executing the previous computing task, the hardware acceleration unit will immediately jump to the current computing task and start executing. Thus, the hardware acceleration unit can autonomously switch between computing tasks without the intervention of the control unit, i.e. the hardware acceleration unit is not idle during the switching between computing tasks, thereby greatly improving the utilization rate of the hardware acceleration unit.

[0063] Further, after the current computing task is deployed, the corresponding identification information is written into the waiting queue. The queue is used to assist the control unit to detect the deployment process of the computing task, and to obtain the corresponding operation result from the computing task that has been executed according to the queue order. Step S22 is repeated until the waiting queue and the task pool are empty, i.e. all computing tasks have been deployed.

[0064] In an embodiment of the present application, the identification information contains a memory address, and the process of obtaining the operation result of the corresponding computing task based on the current identification information comprises: reading the operation result in the current memory address from the shared memory space.

[0065] Further, the identification information includes a memory address and a data tag. The memory address is used to determine the physical location of the data in the memory, and the control unit can accurately locate and access the specific data in the memory by specifying the memory address. The data tag is more used to identify the type, attribute, calculation task type or other information of the data, which is used to help the control unit to identify and process the data in the memory. When processing the calculation result of the hardware acceleration unit, the data tag can help the control unit to identify the type and characteristics of the data, so as to correctly process the data.

[0066] It should be noted that the identification information further includes a task identifier. The task identifier is a unique identifier of the calculation task, which is used to distinguish different tasks. Exemplarily, the task identifier adopts a unique number or code. The task identifier can be used to find, track, manage and allocate tasks, and ensure that the tasks can be accurately located and identified.

[0067] Step S23: sequentially read an identification information from the waiting queue as a current identification information, detect whether an interrupt signal corresponding to the current identification information and sent by the hardware acceleration unit is received, if the interrupt signal is received, obtain the calculation result of the corresponding calculation task based on the current identification information, and continue to perform the operations of reading a next identification information, detecting whether an interrupt signal corresponding to the next identification information and sent by the hardware acceleration unit is received, and obtaining the calculation result of the corresponding calculation task based on the next identification information, until the waiting queue is empty; if the interrupt signal is not received, continue to wait until the interrupt signal corresponding to the current identification information and sent by the hardware acceleration unit is received.

[0068] In an embodiment of the present application, the control unit is responsible for monitoring and obtaining the calculation result of the completed deployed calculation task. The specific process is as follows: the control unit reads the result reading task from the waiting queue, and waits for the hardware acceleration unit to complete the calculation of the calculation task corresponding to the current result reading task. After the control unit receives the interrupt sent back by the hardware acceleration unit, the control unit executes the result reading task, obtains the corresponding calculation result, and performs subsequent operations on the result. The above steps are repeatedly executed until the waiting queue is empty. The subsequent operations performed by the control unit include: storing the result, data analysis, data conversion, data fusion, updating the system state, triggering other tasks, sending messages, displaying the result or providing user feedback, etc.

[0069] In an embodiment of the present application, when the hardware acceleration unit finishes a task, it sends an interrupt to the control unit. The interrupt includes identification information of the finished task, such as a task identifier, a memory address, or a data tag, so that the control unit can obtain the operation result of the hardware acceleration unit from the memory through the information. In this process, the operation result is stored in the memory, rather than in the hardware acceleration unit or the control unit. After receiving the interrupt, the control unit finds the corresponding data in the memory according to the identification information, and performs subsequent processing or output. In this way, the control unit can quickly obtain the operation result of the hardware acceleration unit, and continue to execute the next task, thereby improving the efficiency and response speed of the system.

[0070] Figure 6 is a diagram of task time in the prior art. At T0, task 0 is submitted, and is completed at T1. Before T2, the control unit detects that the hardware acceleration unit has finished the operation on task 0, the control unit obtains the result and performs subsequent processes. Then task 1 is submitted at T2, and task 1 is completed at T3. Task 2 is not submitted until T4, and is completed at T5. Therefore, there is a certain idle time of the hardware acceleration unit between each task. Figure 7 shows a diagram of task time in an embodiment of the present application. As shown in Figure 7, task 0 is submitted at T0, and in the process of processing task 0 by the hardware acceleration unit, through the asynchronous deployment module, task 1 and task 2 are deployed in advance at T1 and T2 respectively. At T3, when task 0 is completed, the hardware acceleration unit immediately executes task 1 without interruption, and the control unit can perform subsequent processes such as result obtaining of task 0. Then, during T3 to T4, subsequent tasks 3 and 4 (not shown) are also deployed, and at T4, when task 1 is completed, the hardware acceleration unit immediately executes task 2 without interruption, and the control unit can perform subsequent processes such as result obtaining of task 1. It can be seen that for the hardware acceleration unit, there is no idle time in the process of processing tasks 0, 1, and 2, so the utilization rate of the hardware acceleration unit is greatly improved. As described above, this is an embodiment of the present application. In T1 and T2, only two computing tasks are deployed in advance, but the present application does not limit the number of computing tasks deployed between the two time points. The present application can deploy a plurality of computing tasks between any two adjacent time points until the task pool is empty.

[0071] In an embodiment of the present application, the terms "first", "second", and the like are used to distinguish the same or similar items with substantially the same functions and effects. For example, the first task and the second task are only used to distinguish different queues, and do not limit the order. Those skilled in the art can understand that the terms "first", "second", and the like do not limit the number and execution order, and the terms "first", "second", and the like do not necessarily mean different.

[0072] It should be noted that, in the embodiments of the present application, the words "exemplary" or "for example" indicate an example, illustration or description. Any embodiment or design solution described as "exemplary" or "for example" in the present application should not be interpreted as more preferred or more advantageous than other embodiments or design solutions. Rather, the use of the words "exemplary" or "for example" is intended to present the relevant concept in a specific manner.

[0073] In the embodiments of the present application, "at least one" means one or more, and "multiple" means two or more. The association relationship between the associated objects is described, which means that there can be three relationships, for example, A and / or B, which can represent the following three cases: A exists alone, A and B exist together, and B exists alone, wherein A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after it. "At least one of the following" or similar expressions means any combination of these items, including any combination of single or multiple items. For example, at least one of a, b or c can represent a, b, c, a-b, a-c, b-c or a-b-c, wherein a, b and c can be single or multiple.

[0074] According to the method provided in the embodiments of the present application, the present application further provides a heterogeneous computing terminal, which comprises a control unit and a hardware acceleration unit, and the control unit and the hardware acceleration unit comprise the following interaction process:

[0075] Firstly, the control unit reads a computing task from the task pool and deploys the computing task to the hardware acceleration unit in a standard deployment manner for the hardware acceleration unit to perform a corresponding operation operation on the computing task and writes identification information corresponding to the computing task into a waiting queue; subsequently, the following is performed in parallel: the control unit reads a next computing task from the task pool as a current computing task, deploys the current computing task to the hardware acceleration unit asynchronously, the hardware acceleration unit performs a corresponding operation operation on the current computing task, and the control unit writes identification information corresponding to the current computing task into the waiting queue; the control unit continues to perform the operations of reading a next computing task, deploying the next computing task to the hardware acceleration unit, and writing identification information corresponding to the next computing task into the waiting queue until the task pool is empty; the control unit reads an identification information from the waiting queue as a current identification information in sequence, detects whether an interrupt signal corresponding to the current identification information sent by the hardware acceleration unit is received, if the control unit receives the interrupt signal, obtains an operation result of a corresponding computing task based on the current identification information, and continues to perform the operations of reading a next identification information, detecting whether an interrupt signal corresponding to the next identification information sent by the hardware acceleration unit is received, and obtaining an operation result of a corresponding computing task based on the next identification information until the waiting queue is empty; if the control unit does not receive the interrupt signal, continues to wait until the interrupt signal corresponding to the current identification information sent by the hardware acceleration unit is received.

[0076] In an embodiment of the present application, the interaction process of the terminal further comprises: after the current computing task is deployed to the hardware acceleration unit asynchronously, a jump instruction is inserted at the end of an instruction of a previous computing task, a target address pointed to by the jump instruction being a first address of the current computing task, so as to make the hardware acceleration unit automatically jump to the current computing task and perform after the previous computing task is executed.

[0077] In an embodiment of the present application, the task content of each computing task comprises: an operation type, operation data, and a control instruction; the type of the control instruction comprises: an operation execution instruction, an instruction for making the hardware acceleration unit perform a corresponding operation operation on a current computing task; a task completion instruction, an instruction for making the hardware acceleration unit send to the control unit that a current computing task has been completed; and a jump instruction, an instruction for making the hardware acceleration unit directly jump to a next computing task completed by the asynchronous deployment after the current computing task is operated.

[0078] In an embodiment of the present application, the hardware acceleration unit comprises a plurality of cores, and the process of asynchronously deploying the current computing task into the hardware acceleration unit for the hardware acceleration unit to perform corresponding operation operation on the current computing task comprises: judging whether one or more cores used for deploying the current computing task are in an idle state; if the one or more cores are all in the idle state, deploying the current computing task into the hardware acceleration unit in a standard deployment manner; otherwise, asynchronously deploying the current computing task into the hardware acceleration unit.

[0079] As shown in FIG. 8, a schematic diagram of the hardware acceleration unit comprising a plurality of cores in an embodiment of the present application is shown. In the embodiment, the hardware acceleration unit has two cores, wherein the first core is executing task 0, and the second core is executing task 1. Task 2 needs two cores to perform a computing operation, and the first core immediately jumps to task 2 after completing task 0, and the second core also jumps to task 2 after completing task 1. If the operations of the first core and the second core are not completed synchronously, whichever core completes the task first will immediately jump to task 2 and wait for the other core. Only when both the cores are ready to execute task 2, task 2 will automatically start to be executed. After task 2 is executed, the first core executes a jump instruction and jumps to task 3 for execution, and then the second core jumps to task 4 for execution.

[0080] In an embodiment of the present application, the computing task comprises a plurality of different operation data and computing tasks of the same computing type.

[0081] For brevity, the specific process of the control unit and the hardware acceleration unit in the system in executing the corresponding steps is described in detail in the method embodiment, and will not be repeated here.

[0082] FIG. 9 is a schematic block diagram of an asynchronous deployment device 900 of a computing task of a hardware acceleration unit provided in an embodiment of the present application. As shown in FIG. 9, the device comprises a task acquisition module 901, a task deployment module 902, and a result waiting module 903.

[0083] The task acquisition module 901 is configured to read a computing task from a task pool, and deploy the computing task into a hardware acceleration unit in a standard deployment manner for the hardware acceleration unit to perform a corresponding operation operation on the computing task, and write identification information corresponding to the computing task into a waiting queue.

[0084] The task deployment module 902 is configured to read a next computing task from the task pool as a current computing task, deploy the current computing task to the hardware acceleration unit asynchronously for the hardware acceleration unit to perform a corresponding operation on the current computing task, and write identification information corresponding to the current computing task into the waiting queue; continue to perform the operations of reading a next computing task, deploying the next computing task to the hardware acceleration unit, and writing identification information corresponding to the next computing task into the waiting queue until the task pool is empty.

[0085] The result waiting module 903 is configured to read an identification information from the waiting queue as a current identification information in sequence, detect whether an interrupt signal corresponding to the current identification information sent by the hardware acceleration unit is received, if the interrupt signal is received, obtain an operation result of a corresponding computing task based on the current identification information, and continue to perform the operations of reading a next identification information, detecting whether an interrupt signal corresponding to the next identification information sent by the hardware acceleration unit is received, and obtaining an operation result of a corresponding computing task based on the next identification information until the waiting queue is empty; if the interrupt signal is not received, continue to wait until the interrupt signal corresponding to the current identification information sent by the hardware acceleration unit is received.

[0086] It should be understood that the specific process of each module performing the corresponding steps described above has been described in detail in the method embodiments described above, and thus will not be described here again for the sake of brevity.

[0087] It should also be understood that the division of the modules in the embodiments of the present application is illustrative, and is only a logical functional division. In actual implementation, another division manner can be used. In addition, each functional module in each embodiment of the present application can be integrated in one processor, or can be physically separated, or two or more modules can be integrated in one module. The integrated module can be realized in the form of hardware or in the form of a software functional module.

[0088] According to the method provided in the embodiments of the present application, the present application further provides a computer program product, which includes computer program codes, when the computer program codes run on a computer, the computer program codes make the computer perform the hardware acceleration unit computing task asynchronous deployment method in any one of the embodiments of the hardware acceleration unit computing task asynchronous deployment to the hardware acceleration unit computing task.

[0089] According to the method provided in the embodiments of the present application, the present application further provides a computer readable storage medium storing program codes, which, when executed on a computer, cause the computer to perform the hardware acceleration unit computing task asynchronous deployment method of any one of the embodiments of the hardware acceleration unit computing task asynchronous deployment method of the hardware acceleration unit computing task asynchronous deployment to a graph hardware acceleration unit.

[0090] As used in this description, the terms "component," "module," "system," and the like are intended to refer to a computer-related entity, either hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to being, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, and / or a computer. By way of illustration, both an application running on a computing device and the computing device can be a component. One or more components can reside within a process and / or thread of execution and a component can be localized, partially localized, and / or distributed across two or more computers. Also, these components can execute from various computer readable media having various data structures stored thereon. The components can communicate by way of local and / or remote processes such as in accordance with a signal having one or more data packets (e.g., data from one component interacting with another component in a local system, distributed system, and / or across a network such as the Internet with other systems via the signal).

[0091] Those of skill in the art would understand that the various illustrative logical blocks, modules, and steps described in connection with the embodiments disclosed herein can be implemented as electronic hardware, computer software, or combinations of both. The choice of hardware or software, or combinations of both, would be dependent on the specific application and design constraints imposed on the overall system. Skilled artisans can implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

[0092] Those of skill in the art would understand that, for the purposes of description and brevity, the specific process of the system, device and unit described above can refer to the corresponding process in the foregoing method embodiments, which will not be described here.

[0093] In several embodiments provided in the present application, it should be understood that the disclosed system, device and method can be implemented in other manners. For example, the described device embodiments are merely schematic. For example, the division of the units is only a logical function division. There can be another division manner for the actual implementation, for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections between the units can be indirect couplings or communication connections through some interfaces, devices or units, and can be electrical, mechanical or in other forms.

[0094] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, i.e., they can be located in one place, or distributed on multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0095] In addition, the functional units in the various embodiments of the present application can be integrated in one processing unit, or each unit can be physically present separately, or two or more units can be integrated in one unit.

[0096] In the above embodiments, the functions of the functional units can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented by software, the functions can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions (programs). When the computer program instructions (programs) are loaded and executed on a computer, the whole or part of the processes or functions according to the embodiments of the present application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer readable storage medium, or transferred from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions can be transferred from one website site, computer, server or data center to another website site, computer, server or data center through wired (such as coaxial cable, optical fiber, digital subscriber line (Digital Subscriber Line, DSL)) or wireless (such as infrared, wireless, microwave, etc.) mode. The computer readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. integrated with one or more available media. The available media can be magnetic media (such as floppy disk, hard disk, magnetic tape), optical media (such as high-density digital video disc (Digital Video Disc, DVD), or semiconductor media (such as solid state disk (Solid State Disk, SSD), etc.

[0097] If the functions are implemented in the form of software function units and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application can be embodied in the form of a software product, which is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0098] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

[0099] In summary, the present application provides a hardware acceleration unit computing task asynchronous deployment method, a heterogeneous computing terminal, an apparatus, a medium and a program product, and the present application provides a neural network asynchronous deployment method for improving the utilization rate of a hardware acceleration unit. By asynchronously deploying the computing tasks of the hardware acceleration unit, the task deployment of the control unit and the task execution of the hardware acceleration unit can be performed synchronously, and the system no longer needs to wait for each other, thereby improving the resource utilization rate, throughput and computing efficiency of the system. In addition, the hardware acceleration unit automatically jumps to the next computing task after deployment, further improving the utilization rate of the hardware acceleration unit. This processing method not only reduces the waiting time of the system, but also speeds up the response speed of the system and improves the stability, enhances the adaptability of the system, and better meets the different computing scenarios and task requirements. Therefore, the present application effectively overcomes the various shortcomings in the prior art and has high industrial utilization value.

[0100] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not intended to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical idea disclosed in the present application should be covered by the claims of the present application.

Claims

1. A method for asynchronous deployment of hardware acceleration unit computing tasks, the method comprising: The method is applied to a control unit and comprises the following steps: First, a computing task is read from a task pool and deployed to a hardware acceleration unit in a standard deployment manner for the hardware acceleration unit to perform a corresponding operation on the computing task, and identification information of the computing task is written into a waiting queue; subsequently, the following steps are performed in parallel: A next computing task is read from the task pool as a current computing task, the current computing task is asynchronously deployed to the hardware acceleration unit for the hardware acceleration unit to perform a corresponding operation on the current computing task, and identification information of the current computing task is written into the waiting queue; the operation of reading a next computing task, deploying the next computing task to the hardware acceleration unit, and writing identification information of the next computing task into the waiting queue is continuously performed until the task pool is empty; One identification information is read from the waiting queue as current identification information, it is detected whether an interrupt signal corresponding to the current identification information and sent by the hardware acceleration unit is received, if the interrupt signal is received, an operation result of a corresponding computing task is obtained based on the current identification information, and the operation of reading a next identification information, detecting whether an interrupt signal corresponding to the next identification information and sent by the hardware acceleration unit is received, and obtaining an operation result of a corresponding computing task based on the next identification information is continuously performed until the waiting queue is empty; if the interrupt signal is not received, it is continuously waited until the interrupt signal corresponding to the current identification information and sent by the hardware acceleration unit is received.

2. The method of claim 1, wherein the hardware acceleration unit computes the task asynchronously. The method further comprises the following steps: After the current computing task is asynchronously deployed to the hardware acceleration unit, a jump instruction is inserted at the end of an instruction of a previous computing task, a target address of the jump instruction is a first address of the current computing task, so that the hardware acceleration unit automatically jumps to the current computing task and performs an operation after the previous computing task is executed.

3. The method of Claim 1, wherein the hardware acceleration unit asynchronously deploys the computing task. Task content of each computing task comprises an operation type, operation data, and a control instruction; the type of the control instruction comprises: An operation execution instruction for instructing the hardware acceleration unit to perform a corresponding operation on the current computing task; A task completion instruction for instructing the hardware acceleration unit to send a current computing task to the control unit The instruction that has been completed; A jump instruction for instructing the hardware acceleration unit to directly jump to a next computing task after the current computing task is operated.

4. The method of Claim 1, wherein the hardware acceleration unit asynchronously deploys the computing task. The hardware acceleration unit comprises a plurality of cores, and the process in which the control unit asynchronously deploys the current computing task to the hardware acceleration unit for the hardware acceleration unit to perform a corresponding operation on the current computing task comprises the following steps: The control unit determines whether one or more cores used for deploying the current computing task are in an idle state; if the one or more cores are all in the idle state, the control unit deploys the current computing task to the hardware acceleration unit in a standard deployment manner; otherwise, the control unit asynchronously deploys the current computing task to the hardware acceleration unit.

5. The method of Claim 1, wherein the hardware acceleration unit asynchronously deploys the computing task. The computing task comprises a plurality of different computing data and computing tasks of the same computing type.

6. The method of claim 5, wherein the hardware acceleration unit computes the task asynchronously. The process of asynchronously deploying the computing of the plurality of different computing data and the same computing type comprises: deploying a first computing task in a standard deployment manner to the hardware acceleration unit to perform a corresponding computing operation; after detecting that the hardware acceleration unit has performed the running of the input / output related instruction in the first computing task, modifying the input data of the current computing task, and generating a next computing task, deploying the next computing task to the hardware acceleration unit in an asynchronous deployment manner to perform a corresponding computing operation; continuing to perform the operation of modifying the input data of the current computing task and performing the corresponding computing operation after detecting that the hardware acceleration unit has performed the running of the input / output related instruction in the current computing task until a preset termination condition is met.

7. The method of claim 6, wherein the hardware acceleration unit computes the task asynchronously. The preset termination condition comprises one or a combination of the following termination conditions: terminating the operation after a preset number of input data modifications of the first computing task; terminating the operation when the total duration of the computing operation performed by the hardware acceleration unit reaches a preset duration; terminating the operation when the computing resource in the hardware acceleration unit is lower than a preset standard.

8. The method of Claim 3, wherein the hardware acceleration unit computes tasks asynchronously, and When the current computing task is the last computing task in the waiting queue, the last instruction of the current computing task is an end instruction.

9. The method of claim 1, wherein the hardware acceleration unit computes tasks asynchronously. The identification information contains a memory address, and the process of obtaining the computing result of the corresponding computing task based on the current identification information comprises reading the computing result in the current memory address from the memory.

10. A heterogeneous computing terminal, characterized by, The control unit and the hardware acceleration unit comprise the following interaction process: First, the control unit reads a computing task from the task pool and deploys the computing task to the hardware acceleration unit in a standard deployment manner for the hardware acceleration unit to perform a corresponding computing operation on the computing task, and writes the identification information corresponding to the computing task into the waiting queue; Subsequently, the following are performed in parallel: the control unit reads a next computing task from the task pool as a current computing task, deploys the current computing task to the hardware acceleration unit, the hardware acceleration unit performs a corresponding computing operation on the current computing task, and the control unit writes the identification information corresponding to the current computing task into the waiting queue; the control unit continues to perform the operations of reading a next computing task, deploying the next computing task to the hardware acceleration unit, and writing the identification information corresponding to the next computing task into the waiting queue until the task pool is empty; the control unit reads an identification information from the waiting queue as a current identification information, detects whether an interrupt signal corresponding to the current identification information sent by the hardware acceleration unit is received, if the control unit receives the interrupt signal, obtains the computing result of the corresponding computing task based on the current identification information, and continues to perform the operations of reading a next identification information, detecting whether an interrupt signal corresponding to the next identification information sent by the hardware acceleration unit is received, and obtaining the computing result of the corresponding computing task based on the next identification information until the waiting queue is empty; If the control unit does not receive the interrupt signal, it continues to wait until it receives the interrupt signal corresponding to the current identification information sent by the hardware acceleration unit.

11. The heterogeneous computing terminal of claim 10, wherein, The interaction process of the terminal further includes: After the current computing task is asynchronously deployed into the hardware acceleration unit, a jump instruction is inserted at the end of the instruction of the previous computing task, and the target address of the jump instruction is the starting address of the current computing task, so that the hardware acceleration unit automatically jumps to the current computing task and executes it after the execution of the previous computing task is completed.

12. The heterogeneous computing terminal of claim 10, wherein, The task content of each computing task includes an operation type, operation data, and control instructions, and the type of the control instructions includes: An operation execution instruction, which is used to instruct the hardware acceleration unit to perform a corresponding operation on the current computing task; A task completion instruction, which is used to instruct the hardware acceleration unit to send a current computing task completion instruction to the control unit; A jump instruction, which is used to instruct the hardware acceleration unit to directly jump to the next computing task after the operation of the current computing task is completed.

13. The heterogeneous computing terminal of claim 10, wherein, The hardware acceleration unit includes multiple cores, and the process of asynchronously deploying the current computing task into the hardware acceleration unit to perform a corresponding operation on the current computing task by the hardware acceleration unit includes: The control unit determines whether one or more cores used to deploy the current computing task are in an idle state; if the one or more cores are in the idle state, the control unit deploys the current computing task into the hardware acceleration unit in a standard deployment manner; otherwise, the control unit asynchronously deploys the current computing task into the hardware acceleration unit.

14. The heterogeneous computing terminal of claim 10, wherein, The computing task includes multiple computing tasks of different operation data and the same computing type.

15. The heterogeneous computing terminal of claim 14, wherein, The process of asynchronously deploying the computing tasks of different operation data and the same computing type includes: Deploying the first computing task into the hardware acceleration unit in a standard deployment manner to perform a corresponding computing operation; After detecting that the hardware acceleration unit has executed the running of the input / output related instruction in the first computing task, modifying the input data of the current computing task, and generating the next computing task, the next computing task is deployed into the hardware acceleration unit in an asynchronous deployment manner to perform a corresponding computing operation; Continuing to perform the operation of modifying the input data of the current computing task and performing a corresponding computing operation after detecting that the hardware acceleration unit has executed the running of the input / output related instruction in the current computing task until a preset termination condition is met.

16. The heterogeneous computing terminal of claim 15, wherein, The preset termination condition includes one or more of the following termination conditions: After the input data of the first computing task is modified for a preset number of times, the operation is terminated; When the total duration of the computing operation performed by the hardware acceleration unit reaches a preset duration, the operation is terminated; When the computing resources in the hardware acceleration unit are lower than a preset standard, the operation is terminated.

17. The heterogeneous computing terminal of claim 12, wherein, When the current computing task is the last computing task in the waiting queue, the last instruction of the current computing task is an end instruction.

18. The method of Claim 10, wherein the hardware acceleration unit computes tasks asynchronously, and The identification information includes a memory address, and the process of obtaining the operation result of the corresponding computing task based on the current identification information includes reading the operation result in the current memory address from the memory.

19. An asynchronous deployment device for computing tasks of a hardware acceleration unit, characterized in that, The method comprises the following steps: The task obtaining module is configured to read a computing task from the task pool and deploy the computing task to the hardware acceleration unit in a standard deployment manner so that the hardware acceleration unit performs a corresponding operation on the computing task, and write identification information corresponding to the computing task into the waiting queue; The task deployment module is configured to read a next computing task from the task pool as a current computing task, deploy the current computing task to the hardware acceleration unit asynchronously so that the hardware acceleration unit performs a corresponding operation on the current computing task, and write identification information corresponding to the current computing task into the waiting queue; The method continues to read the next computing task, deploy the next computing task to the hardware acceleration unit, and write the identification information corresponding to the next computing task into the waiting queue until the task pool is empty; The result waiting module is configured to read an identification information from the waiting queue as a current identification information, detect whether an interrupt signal corresponding to the current identification information sent by the hardware acceleration unit is received, obtain an operation result of a corresponding computing task based on the current identification information if the interrupt signal is received, and continue to read a next identification information, detect whether an interrupt signal corresponding to the next identification information sent by the hardware acceleration unit is received, and obtain an operation result of a corresponding computing task based on the next identification information until the waiting queue is empty; if the interrupt signal is not received, continue to wait until the interrupt signal corresponding to the current identification information sent by the hardware acceleration unit is received. The computer program is executed by the processor to implement the hardware acceleration unit computing task asynchronous deployment method in any one of claims 1 to 9.

20. A computer readable storage medium having stored thereon a computer program, characterized in that, The computer program product includes computer program code, and when the computer program code is run on a computer, the computer implements the hardware acceleration unit computing task asynchronous deployment method as described in any one of claims 1 to 9.

21. A computer program product, characterised in that, ​

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