Contact-optimized oxide semiconductor transistor and preparation method therefor

Abstract

A contact-optimized oxide semiconductor transistor and a preparation method therefor, relating to the technical field of information materials and devices. In the oxide semiconductor transistor, an oxide semiconductor contact layer is inserted in situ into a contact region between source / drain metal electrode layers and an oxide semiconductor channel layer, and the carrier concentration of the oxide semiconductor contact layer is different from the carrier concentration of the oxide semiconductor channel layer, thereby forming dipole pairs at the contact interface. The present invention can reduce source / drain contact resistance without affecting a threshold voltage and carrier mobility, thereby improving on-state performance such as an on-state current and transconductance without increasing process complexity, realizing ultra-short-channel devices, and particularly facilitating realization of high-performance devices with contact dimensions smaller than 20 nm.

Description

Contact-optimized oxide semiconductor transistor and preparation method thereof TECHNICAL FIELD

[0001] The present application relates to a contact-optimized oxide semiconductor transistor and a preparation method thereof, and belongs to the technical field of information materials and devices. BACKGROUND

[0002] In the past decade, oxide semiconductor materials have been widely used in the display field due to their high light transmittance, high mobility, and large-area uniformity, and the device size is mostly micron level. In recent years, with the continuous development of integrated circuit industry, oxide semiconductor materials with low thermal budget process have shown great potential in the field of logic, storage and radio frequency compatible with the later process. At present, through material and preparation process optimization, oxide transistors with channel length less than 10 nanometers have been realized, but the reduction of transistor lateral size mainly reflects the miniaturization of contacted gate pitch (CGP), including channel length and contact length. The contact length of the current oxide transistor still stays at the sub-micron level, and as the contact length decreases, the contact resistance increases, which limits the on-state performance of the transistor. Therefore, in order to realize high-density, low-power and high-performance oxide semiconductor transistors, the present application proposes a contact-optimized oxide semiconductor field effect transistor and a preparation method thereof. The present application has great potential in improving the performance of oxide semiconductor transistors and the integration density of the later compatible process.

[0003] With the miniaturization of the channel length and the contact length of the oxide semiconductor transistor, the influence of contact resistance on the on-state performance is more significant. According to the unique permeation conduction mechanism of oxide semiconductor, increasing the carrier concentration can improve the carrier mobility, thereby reducing the contact resistance and improving the on-state current. However, high carrier concentration will cause the threshold voltage to move negatively, and even affect the normal turn-off of the transistor, which is not conducive to integrated circuit applications. Therefore, seeking a process that optimizes the threshold voltage and on-state current is crucial for promoting the application of oxide semiconductors. SUMMARY

[0004] In order to solve the size miniaturization bottleneck of existing oxide semiconductor devices and improve the integrated circuit density, the present application proposes a contact-optimized oxide semiconductor field effect transistor and a preparation method thereof.

[0005] To achieve the above purpose, the technical scheme adopted by the present application is as follows:

[0006] An oxide semiconductor field effect transistor, comprising a substrate, a gate electrode layer, a gate dielectric layer, an oxide semiconductor channel layer and a source / drain metal electrode layer, characterized in that an oxide semiconductor contact layer is in-situ inserted between the source / drain metal electrode layer and the oxide semiconductor channel layer, the carrier concentration of the oxide semiconductor contact layer is different from that of the oxide semiconductor channel layer, and a dipole pair is formed at the contact interface.

[0007] Further, the transistor device structure includes, but is not limited to, a back-gate, a top-gate, a dual-gate, a FinFET, a GAA, a CAA, a VFET, etc.

[0008] Further, the substrate is a glass substrate, a silicon substrate, a silicon carbide substrate, a diamond substrate, a diamond-like carbon film substrate or a PI, PET flexible substrate.

[0009] Further, the gate electrode layer material is Ti, Ni, Au, Pt, Pd, Al, W, Y, Sc, Mo and their alloys, TiN, metallic oxide ITO, IZO, and the thickness is 5-300 nm.

[0010] Further, the gate dielectric layer material is SiO2, SiN x , Al2O3, HfO2, HfSiOx, HfLaO x , HfAlOx, HfZrO x and their multi-doped combination dielectrics, and the thickness is 2-100 nm.

[0011] Further, the channel layer material is In2O3, SnO2, Ga2O3, ZnO, ITO, IGO, IZO, IGZO, IAZO, ITZO, IWO, ITWO oxide semiconductor thin film and multi-layer oxide thin film stack composite, and the thickness is 0.5-50 nm.

[0012] Further, the oxide semiconductor contact layer material is In2O3, SnO2, Ga2O3, ZnO, ITO, IGO, IZO, IGZO, IAZO, ITZO, IWO, ITWO oxide semiconductor thin film and multi-layer oxide thin film stack composite, and the thickness is 0.5-50 nm.

[0013] Further, the source / drain metal electrode layer material is Ti, Ni, Au, Pt, Pd, W, Al, Y, Sc, Mo and their alloys, TiN, metallic oxide ITO, IZO, and the thickness is 3-300 nm.

[0014] The application further provides a preparation method of the double-gate oxide semiconductor field effect transistor, comprising the following process steps:

[0015] Step 1.1, cleaning the substrate;

[0016] Step 1.2, defining a gate pattern by adopting an optical lithography, electron beam lithography process or laser direct writing process, and preparing a bottom gate metal electrode layer by adopting an electron beam evaporation, magnetron sputtering, thermal evaporation or atomic layer deposition process;

[0017] Step 1.3, preparing a bottom gate dielectric layer by adopting a thermal oxidation, plasma enhanced chemical vapor deposition, inductively coupled plasma chemical vapor deposition, magnetron sputtering, electron beam evaporation, pulsed vapor deposition or atomic layer deposition process;

[0018] Step 1.4, preparing an oxide semiconductor channel layer by adopting a magnetron sputtering, chemical vapor deposition, molecular beam epitaxy or atomic layer deposition process;

[0019] Step 1.5, preparing an oxide semiconductor contact layer by adopting a magnetron sputtering, chemical vapor deposition, molecular beam epitaxy or atomic layer deposition process;

[0020] Step 1.6, preparing a source and drain contact metal electrode by adopting an electron beam evaporation, magnetron sputtering, ion beam sputtering, thermal evaporation or atomic layer deposition process method;

[0021] Step 1.7, preparing a top gate dielectric by adopting the same method as in step 1.3;

[0022] Step 1.8, preparing a top gate electrode by adopting the same method as in step 1.2.

[0023] Further, a preparation method of a vertical structure oxide semiconductor field effect transistor comprises the following process steps:

[0024] Step 2.1, cleaning the substrate;

[0025] Step 2.2, preparing a source electrode and an oxide semiconductor contact layer by adopting an electron beam evaporation, magnetron sputtering, ion beam sputtering, thermal evaporation or atomic layer deposition process method;

[0026] Step 2.3, preparing a passivation layer by adopting a plasma enhanced chemical vapor deposition, inductively coupled plasma chemical vapor deposition, magnetron sputtering, electron beam evaporation, pulsed vapor deposition or atomic layer deposition process;

[0027] Step 2.4, defining a gate pattern by adopting an optical lithography, electron beam lithography process or laser direct writing process, and preparing a gate electrode by adopting an electron beam evaporation, magnetron sputtering, thermal evaporation or atomic layer deposition process;

[0028] Step 2.5, a low dielectric constant passivation layer is prepared by using the same method as in step 2.3;

[0029] Step 2.6, a channel region is defined by using an optical lithography, electron beam lithography process or laser direct writing process, and the opening of the channel region is completed by using a dry etching or wet etching process, so as to form a trench;

[0030] Step 2.7, a gate dielectric layer is prepared by using a thermal oxidation, plasma enhanced chemical vapor deposition, inductively coupled plasma chemical vapor deposition, magnetron sputtering, electron beam evaporation, pulsed vapor deposition or atomic layer deposition process, and the gate dielectric layer is located between the gate electrode layer and the oxide semiconductor channel layer;

[0031] Step 2.8, an oxide semiconductor channel layer is prepared by using a magnetron sputtering, chemical vapor deposition, molecular beam epitaxy or atomic layer deposition process;

[0032] Step 2.9, a filling layer is grown in the trench by using a plasma enhanced chemical vapor deposition or atomic layer deposition process;

[0033] Step 2.10, an oxide semiconductor contact layer and a metal drain electrode layer are prepared by using a spin coating, baking, photolithography, development, electron beam evaporation, magnetron sputtering and stripping process.

[0034] The beneficial effects of the present application are as follows:

[0035] The present application inserts an oxide semiconductor contact layer in the contact region between the source and drain metal electrode layers and the oxide semiconductor channel layer, the carrier concentration of the oxide semiconductor contact layer is different from that of the oxide semiconductor channel layer, a dipole pair is formed at the contact interface, the carrier concentration below the contact region is increased, so as to reduce the contact resistance and the transmission length, realize a high-performance small-size transistor, and facilitate the improvement of the integrated circuit density. Meanwhile, the carrier concentration of the channel and the source and drain regions is separated, and low contact resistance and positive threshold voltage are simultaneously realized. The present application relates to all structures formed by using equivalent transformation or equivalent transformation, such as a bottom gate structure, a top gate structure, a double gate structure, a fin-type gate structure, a surround gate structure, a ring channel structure and a vertical channel structure. That is, this contact method does not change the carrier concentration of the channel region, can keep the threshold voltage unchanged, breaks the contradiction between the threshold voltage and the on-state current of the oxide semiconductor, and has great potential in improving the electrical characteristics of the oxide semiconductor field effect transistor and reducing the overall size of the transistor. BRIEF DESCRIPTION OF DRAWINGS

[0036] Fig. 1 is a schematic diagram of a double gate structure oxide semiconductor field effect transistor according to an embodiment of the present application;

[0037] Figure 2 is a flow chart of a method for preparing a double-gate structure oxide semiconductor field effect transistor according to an embodiment of the present application;

[0038] Figure 3 is a structural schematic diagram of a vertical structure oxide semiconductor field effect transistor according to an embodiment of the present application;

[0039] Figure 4 is a flow chart of a method for preparing a vertical structure oxide semiconductor field effect transistor according to an embodiment of the present application;

[0040] Figure 5 is a legend for Figures 1-4;

[0041] Figure 6 is a comparative schematic diagram of an oxide semiconductor transistor with an oxide semiconductor contact prepared according to the present application and a planar oxide semiconductor transistor with a metal contact, in which (a) is a transfer characteristic curve and (b) is a transfer transconductance curve. DETAILED DESCRIPTION

[0042] Embodiments of the present application are described in detail below with reference to the accompanying drawings. The embodiments described below are exemplary only, and are not to be construed as limiting the present application.

[0043] The present application provides a contact-optimized oxide semiconductor field effect transistor and a method for preparing the same. The device structure includes, but is not limited to, a back-gate structure, a top-gate structure, a dual-gate structure, a FinFET structure, a gate-all-around structure, a cylindrical channel around structure, a vertical field effect transistor (VFET) structure, etc.

[0044] Figure 1 is a contact-optimized dual-gate structure oxide semiconductor field effect transistor, which includes, from bottom to top, a substrate, a bottom gate electrode layer, a bottom gate dielectric layer, an oxide semiconductor channel layer, an oxide semiconductor contact layer, a source / drain metal electrode layer, a top gate dielectric layer, and a top gate electrode layer. The carrier concentration of the oxide semiconductor contact layer is different from that of the oxide semiconductor channel layer, and a dipole pair is formed at the contact interface.

[0045] The present application provides a method for preparing the above-mentioned dual-gate structure oxide semiconductor field effect transistor, which specifically includes the following steps:

[0046] S001: Obtain and use a cleaned substrate. RCA1 is used to clean the particles and organic matter on the substrate, and high-purity nitrogen is used to dry the substrate after cleaning.

[0047] The substrate can be a glass substrate, a silicon substrate, a silicon carbide substrate, a diamond substrate, a diamond-like carbon film substrate, or a flexible substrate such as PI, PET, etc. In the present embodiment, the substrate is a high-resistance silicon substrate with a resistivity > 10000 Ω·cm.

[0048] S002, a bottom gate electrode is prepared by using a spin coating, baking, photolithography, developing, electron beam evaporation, and peeling process. In this embodiment, the bottom gate metal layer is 20 nm Pt.

[0049] S003, a gate dielectric layer is prepared by using an atomic layer deposition process. In this embodiment, the bottom gate dielectric layer is 5 nm HfLaO x .

[0050] S004, a channel active region is prepared by using a spin coating, baking, photolithography, developing, magnetron sputtering, and peeling process. In this embodiment, the oxide semiconductor channel layer is 8 nm IGZO.

[0051] S005, an oxide semiconductor contact layer and a metal source-drain electrode layer are prepared by using photolithography, magnetron sputtering, and electron beam evaporation process, and a source-drain region definition is completed by using a peeling technology. In this embodiment, the oxide semiconductor contact layer is 8 nm ITO, and the source-drain contact electrode is 20 nm Ni.

[0052] Further, in order to realize a <20 nm contact electrode length, a photoresist with higher exposure accuracy is selected, such as PMMA A3, PMMA A2, ZEP520A, ARP6200.09, and the like, and a low-temperature developing process technology is combined.

[0053] S006, a top gate dielectric layer is prepared by using an atomic layer deposition process. In this embodiment, the top gate dielectric layer is 5 nm HfLaO x .

[0054] S007, a top gate electrode is prepared by using a spin coating, baking, photolithography, developing, electron beam evaporation, and peeling process. In this embodiment, the top gate electrode layer is 20 nm Pt.

[0055] S008, a test electrode is exposed after etching and removing the photoresist by using a photolithography and etching process.

[0056] The above S001-S008 correspond to (1)-(8) shown in FIG. 2, respectively.

[0057] Fig. 3 is a vertical structure oxide semiconductor field effect transistor, comprising a substrate, a source / drain metal electrode layer, a gate electrode layer, an oxide semiconductor channel layer, a drain, a source metal electrode layer, the oxide semiconductor channel layer is in a groove shape, an oxide semiconductor contact layer is arranged between the groove bottom of the oxide semiconductor channel layer and the source and drain metal electrode layer, a gate dielectric layer is arranged outside the groove, the gate dielectric layer is arranged between the gate electrode layer and the oxide semiconductor channel layer, a growth filling layer is arranged in the groove of the oxide semiconductor channel layer, an oxide semiconductor contact layer is arranged between the groove top of the oxide semiconductor channel layer and the drain and source metal electrode layer, a passivation layer is arranged between the source and drain metal electrode layer, the gate electrode layer and the oxide semiconductor channel layer, the carrier concentration of the oxide semiconductor contact layer is different from the carrier concentration of the oxide semiconductor channel layer, and a dipole pair is formed at the contact interface.

[0058] The application provides a preparation method of the vertical structure oxide semiconductor field effect transistor.

[0059] S001: a substrate is obtained and cleaned. RCA1 is used to clean particles and organic matters on the substrate, and high-purity nitrogen is used to dry the substrate after cleaning.

[0060] The substrate can be a glass substrate, a silicon substrate, a silicon carbide substrate, a diamond substrate, a diamond-like carbon film substrate or a flexible substrate such as PI and PET. In the embodiment, the substrate is a high-resistance silicon substrate with a resistivity of >10000 Ω·cm.

[0061] S002: the preparation of the metal source electrode layer and the oxide semiconductor contact layer is completed by using the process steps of spin coating, baking, photolithography, development, electron beam evaporation, magnetron sputtering and stripping. In the embodiment, the oxide semiconductor contact layer is 8 nm ITO, and the source and drain contact electrodes are 20 nm Ni.

[0062] S003: the SiO2 passivation layer is grown by using a plasma-enhanced chemical vapor deposition process or an atomic layer deposition process.

[0063] S004: the gate electrode is prepared by using the process steps of spin coating, baking, photolithography, development, electron beam evaporation and stripping. In the embodiment, the gate electrode is 20 nm Pt.

[0064] S005: the SiO2 passivation layer is grown by using a plasma-enhanced chemical vapor deposition process or an atomic layer deposition process.

[0065] S006: the opening of the channel region is completed by using the process steps of spin coating, baking, photolithography, development, etching and glue removal, and a groove is formed.

[0066] S007, a gate dielectric layer is prepared outside the trench by atomic layer deposition process, and the gate dielectric layer is between the gate electrode layer and the oxide semiconductor channel layer. In this embodiment, the gate dielectric layer is 5 nm HfLaO x .

[0067] S008, the oxide semiconductor channel layer is prepared by atomic layer deposition, uniform coating, baking, photolithography, development, etching and other process steps. In this embodiment, the oxide semiconductor channel layer is 8 nm IGZO.

[0068] S009, a filling layer is grown in the trench by plasma enhanced chemical vapor deposition or atomic layer deposition process. In this embodiment, the filling layer is SiO2.

[0069] S010, the preparation of the oxide semiconductor contact layer and the metal drain electrode layer is completed by uniform coating, baking, photolithography, development, electron beam evaporation, magnetron sputtering, stripping and other process steps. In this embodiment, the oxide semiconductor contact layer is 8 nm ITO, and the source and drain contact electrodes are 20 nm Ni.

[0070] The above S001-S010 correspond to (1)-(10) shown in FIG. 4, respectively.

[0071] Compared with the prior art, the present application significantly reduces the contact resistance and the effective transmission length without affecting the channel threshold voltage. Compared with pure metal contact, the present application achieves more excellent electrical performance with smaller contact size. As shown in FIG. 6, the transfer characteristic curve and the transfer transconductance curve of the planar oxide semiconductor transistor prepared by the metal contact and the oxide semiconductor contact are compared. The on-state current and the transfer transconductance of the oxide semiconductor transistor with a channel length of 30 nm and a contact length of 50 nm are both improved by more than 2 times after the oxide semiconductor contact insertion layer is used.

[0072] It should be noted that the above embodiments illustrate the present application rather than limit the present application, and those skilled in the art can design alternative embodiments without departing from the scope of the appended claims.

Claims

1. An oxide semiconductor field effect transistor comprising a substrate, a gate electrode layer, a gate dielectric layer, an oxide semiconductor channel layer, and a source and drain metal electrode layer, characterized by, In the contact area between the source and drain metal electrode layer and the oxide semiconductor channel layer, an oxide semiconductor contact layer is inserted in situ, the carrier concentration of the oxide semiconductor contact layer is different from the carrier concentration of the oxide semiconductor channel layer, and a dipole pair is formed at the contact interface.

2. The oxide semiconductor field effect transistor according to claim 1, wherein The oxide semiconductor field effect transistor structure is a bottom gate structure, a top gate structure, a double gate structure, a fin gate structure, a surround gate structure, a ring channel structure or a vertical channel structure.

3. The oxide semiconductor field effect transistor according to claim 1, wherein The substrate is a glass substrate, a silicon substrate, a silicon carbide substrate, a diamond substrate, a diamond-like carbon film substrate or a PI, PET flexible substrate.

4. The oxide semiconductor field effect transistor according to claim 1, wherein The gate electrode layer material is Ti, Ni, Au, Pt, Pd, Al, W, Y, Sc, Mo and alloys thereof, TiN, metallic oxide ITO, IZO, with a thickness of 5-300 nanometers.

5. The oxide semiconductor field effect transistor according to claim 1, wherein The gate dielectric layer material is SiO2, SiN x , Al2O3, HfO2, HfSiOx, HfLaO x , HfAlOx, HfZrO x and its multi-doped combination dielectric, with a thickness of 2-100 nanometers.

6. The oxide semiconductor field effect transistor according to claim 1, wherein The channel layer material is In2O3, SnO2, Ga2O3, ZnO, ITO, IGO, IZO, IGZO, IAZO, ITZO, IWO, ITWO oxide semiconductor thin film and a composite material of a multilayer oxide thin film stack, with a thickness of 0.5-50 nanometers.

7. The oxide semiconductor field effect transistor according to claim 1, wherein The oxide semiconductor contact insertion layer material is In2O3, SnO2, Ga2O3, ZnO, ITO, IGO, IZO, IGZO, IAZO, ITZO, IWO, ITWO oxide semiconductor thin film and a composite material of a multilayer oxide thin film stack, with a thickness of 0.5-50 nanometers.

8. The oxide semiconductor field effect transistor according to claim 1, wherein The source / drain metal electrode layer material is Ti, Ni, Au, Pt, Pd, W, Al, Y, Sc, Mo and alloys thereof, TiN, metallic oxide ITO, IZO, with a thickness of 3-300 nanometers.

9. A preparation method of a double gate structure oxide semiconductor field effect transistor, comprising the following process steps: Step 1.1, cleaning the substrate; Step 1.2, defining a gate pattern by optical lithography, electron beam lithography process or laser direct writing process, and preparing a bottom gate metal electrode layer by electron beam evaporation, magnetron sputtering, thermal evaporation or atomic layer deposition process; Step 1.3, preparing a bottom gate dielectric layer by thermal oxidation, plasma enhanced chemical vapor deposition, inductively coupled plasma chemical vapor deposition, magnetron sputtering, electron beam evaporation, pulsed vapor deposition or atomic layer deposition process; Step 1.4, preparing an oxide semiconductor channel layer by magnetron sputtering, chemical vapor deposition, molecular beam epitaxy or atomic layer deposition process; Step 1.5, preparing an oxide semiconductor contact layer by magnetron sputtering, chemical vapor deposition, molecular beam epitaxy or atomic layer deposition process; Step 1.6, preparing a source and drain contact metal electrode by electron beam evaporation, magnetron sputtering, ion beam sputtering, thermal evaporation or atomic layer deposition process; Step 1.7, preparing a top gate dielectric by the same method as in step 1.3; Step 1.8, preparing a top gate electrode by the same method as in step 1.

2.

10. A preparation method of a vertical structure oxide semiconductor field effect transistor, comprising the following process steps: Step 2.1, cleaning the substrate; Step 2.2, source electrode and oxide semiconductor contact layer are prepared by electron beam evaporation, magnetron sputtering, ion beam sputtering, thermal evaporation or atomic layer deposition process; Step 2.3, passivation layer is prepared by plasma enhanced chemical vapor deposition, inductively coupled plasma chemical vapor deposition, magnetron sputtering, electron beam evaporation, pulsed vapor deposition or atomic layer deposition process; Step 2.4, gate pattern is defined by optical lithography, electron beam lithography process or laser direct writing process, and gate electrode is prepared by electron beam evaporation, magnetron sputtering, thermal evaporation or atomic layer deposition process; Step 2.5, low dielectric constant passivation layer is prepared by the same method as in step 2.3; Step 2.6, channel region is defined by optical lithography, electron beam lithography process or laser direct writing process, and opening of channel region is completed by dry etching or wet etching process, forming a trench; Step 2.7, gate dielectric layer is prepared by thermal oxidation, plasma enhanced chemical vapor deposition, inductively coupled plasma chemical vapor deposition, magnetron sputtering, electron beam evaporation, pulsed vapor deposition or atomic layer deposition process, which is between gate electrode layer and oxide semiconductor channel layer; Step 2.8, oxide semiconductor channel layer is prepared by magnetron sputtering, chemical vapor deposition, molecular beam epitaxy or atomic layer deposition process; Step 2.9, filling layer is grown in the trench by plasma enhanced chemical vapor deposition or atomic layer deposition process; Step 2.10, oxide semiconductor contact layer and metal drain electrode layer are prepared by uniform coating, baking, photolithography, development, electron beam evaporation, magnetron sputtering and stripping process.

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