Scan driving circuit and display panel comprising same

Abstract

A scan driving circuit (10) and a display panel comprising same. The scan driving circuit (10) comprises a plurality of shift registers in series connection and a timing controller (11). Each shift register comprises nine transistors and three capacitors, and the timing controller (11) controls the shift registers by means of three signal lines. The structure of the scan driving circuit (10) is improved, and the number of elements inside of the shift registers is reduced, thereby reducing the number of required elements, and also reducing the costs of an OLED panel and the required bezel width.

Description

Scan driving circuit and display panel comprising same TECHNICAL FIELD

[0001] The present application relates to the field of electric control components, in particular to a scan driving circuit and a display panel comprising same. BACKGROUND

[0002] The scan driving circuit comprising shift registers is an indispensable important component of OLED panels. With the increasing demand for narrow frame OLED panels in the market, when designing the scan driving circuit comprising shift registers for OLED panels, it is necessary to use as few components as possible while maintaining correct and stable output in order to reduce the required frame width of the OLED panel.

[0003] SUMMARY

[0004] The present application aims to provide a scan driving circuit and a display panel comprising same, which improves the structure of the scan driving circuit, thereby reducing the number of required components and the frame width of the required OLED panel.

[0005] The present application solves the above technical problems by the following technical solutions:

[0006] The present application provides a scan driving circuit, which comprises a plurality of serially connected shift registers, each of which comprises:

[0007] a first transistor, which is electrically connected with a first node and an input terminal;

[0008] a second transistor, the first electrode of which is electrically connected with a first power supply, the second electrode of which is electrically connected with the first node, and the gate of which is electrically connected with a first control terminal;

[0009] a third transistor, the first electrode of which is electrically connected with the first power supply, the second electrode of which is electrically connected with a second node, and the gate of which is electrically connected with the first control terminal;

[0010] a fourth transistor, the first electrode of which is electrically connected with the input terminal, the second electrode of which is electrically connected with the second node, and the gate of which is electrically connected with a third control terminal;

[0011] a fifth transistor, the first electrode of which is electrically connected with a third node, the second electrode of which is electrically connected with the first power supply (VDD), and the gate of which is electrically connected with the second node;

[0012] a sixth transistor, the first electrode of which is electrically connected with the third node, the second electrode of which is electrically connected with a second power supply (VEE), and the gate of which is electrically connected with the first control terminal;

[0013] A seventh transistor, a first electrode of the seventh transistor is electrically connected with the first power supply, a second electrode is electrically connected with the fifth node, and a gate electrode is electrically connected with the third node;

[0014] An eighth transistor, a first electrode of the eighth transistor is electrically connected with the fifth node, a second electrode is electrically connected with the second control end, and a gate electrode is electrically connected with the fourth node;

[0015] A ninth transistor, a first electrode of the ninth transistor is electrically connected with the first node, a second electrode is electrically connected with the fourth node, and a gate electrode is electrically connected with the second power supply;

[0016] A first capacitor, two ends of the first capacitor are respectively electrically connected with the first power supply and the third node;

[0017] A second capacitor, two ends of the second capacitor are respectively electrically connected with the fourth node and the fifth node;

[0018] A third capacitor, two ends of the third capacitor are respectively electrically connected with the first power supply and the second node;

[0019] An output end is arranged between the seventh transistor and the fifth node;

[0020] The scan driving circuit further comprises a timing controller for controlling each of the shift registers.

[0021] In some embodiments, a first electrode of the first transistor is electrically connected with the first node, a second electrode is electrically connected with the input end, and a gate electrode is electrically connected with the third control end.

[0022] In some embodiments, a first electrode of the first transistor is electrically connected with the first node, a second electrode is electrically connected with the second power supply, and a gate electrode is electrically connected with the input end.

[0023] In some embodiments, the scan driving circuit further comprises a first signal line, a second signal line and a third signal line, the first signal line, the second signal line and the third signal line are electrically connected with the timing controller, and each of the shift registers is electrically connected with the first signal line, the second signal line and the third signal line;

[0024] The first signal line is used for outputting a first clock signal, the second signal line is used for outputting a second clock signal, and the third signal line is used for outputting a third clock signal.

[0025] In some embodiments, the first clock signal, the second clock signal and the third clock signal are periodic square wave signals with the same frequency, one period of the square wave signal has a length of 3t, including a low level with a length of t and a high level with a length of 2t.

[0026] In some embodiments, the first clock signal is delayed by t from an input signal of the shift register, the second clock signal is delayed by t from the first clock signal, and the third clock signal is delayed by t from the second clock signal.

[0027] In some embodiments, the first control terminal of the 3N-2th stage of the shift register is electrically connected to the first signal line, the second control terminal is electrically connected to the second signal line, and the third control terminal is electrically connected to the third signal line; N is a positive integer.

[0028] In some embodiments, the first control terminal of the 3N-1th stage of the shift register is electrically connected to the third signal line, the second control terminal is electrically connected to the first signal line, and the third control terminal is electrically connected to the second signal line; N is a positive integer.

[0029] In some embodiments, the first control terminal of the 3Nth stage of the shift register is electrically connected to the second signal line, the second control terminal is electrically connected to the third signal line, and the third control terminal is electrically connected to the first signal line; N is a positive integer.

[0030] The application also provides a display panel, characterized by comprising a data driver, a display area, a light-emitting driving circuit, and the scanning driving circuit.

[0031] The data driver is electrically connected to the timing controller and the display area, the light-emitting driving circuit is electrically connected to the timing controller and the display area, and the scanning driving circuit is electrically connected to the display area.

[0032] On the basis of common general knowledge in the art, the above-mentioned preferred conditions can be combined arbitrarily, thereby obtaining preferred examples of the application.

[0033] The positive progress effect of the application is that:

[0034] The scanning driving circuit and the display panel comprising the same improve the structure of the scanning driving circuit, reduce the number of elements inside the shift register, thereby reducing the number of required elements, and also reduce the cost of the OLED panel and the required frame width. BRIEF DESCRIPTION OF DRAWINGS

[0035] The above and other features and advantages of the present application will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which:

[0036] Fig. 1 is a schematic diagram of a display panel according to embodiments 1-2 of the application.

[0037] Fig. 2 is a partial cascade schematic diagram of a scanning driving circuit according to embodiments 1-2 of the application.

[0038] Fig. 3 is a waveform diagram of the shift register of the scan driving circuit of the embodiment 1-2 of the present application.

[0039] Fig. 4 is a circuit diagram of the shift register of the scan driving circuit of the embodiment 1 of the present application.

[0040] Fig. 5 is a circuit diagram of the shift register of the scan driving circuit of the embodiment 2 of the present application.

[0041] Fig. 6 is a conduction state diagram of the shift register of the scan driving circuit of the embodiment 1 of the present application at the stage t1 in Fig. 3.

[0042] Fig. 7 is a conduction state diagram of the shift register of the scan driving circuit of the embodiment 1 of the present application at the stage t2 in Fig. 3.

[0043] Fig. 8 is a conduction state diagram of the shift register of the scan driving circuit of the embodiment 1 of the present application at the stage t3 in Fig. 3.

[0044] Fig. 9 is a conduction state diagram of the shift register of the scan driving circuit of the embodiment 1 of the present application at the stage t4 in Fig. 3.

[0045] Fig. 10 is a conduction state diagram of the shift register of the scan driving circuit of the embodiment 1 of the present application at the stage t5 in Fig. 3.

[0046] T1 first transistor T2 second transistor T3 third transistor T4 fourth transistor T5 fifth transistor T6 sixth transistor T7 seventh transistor T8 eighth transistor T9 ninth transistor C1 first capacitor C2 second capacitor C3 third capacitor P1 first node P2 second node P3 third node P4 fourth node P5 fifth node CK1 first signal line CK2 second signal line CK3 third signal line VDD first power supply VEE second power supply K1 first control terminal K2 second control terminal K3 third control terminal IN input terminal OUT output terminal 1 first shift register 2 second shift register 3 third shift register 4 fourth shift register 5 fifth shift register 10 scan driving circuit 11 timing controller 20 data driver 30 light emitting driving circuit 40 display area DETAILED DESCRIPTION

[0047] The present application is described by way of specific examples, and those skilled in the art will readily recognize how best to make and use the present application with the details given herein. The present application may, however, be carried out in ways other than those specifically set forth herein without departing from the essential scope of the application. It is to be understood that the specific examples herein are merely illustrative and that the present application can be embodied in other specific forms without departing from the spirit of the application. The various features of the application are described in more detail below.

[0048] The embodiments of the present application will be described in detail below with reference to the drawings, so that those skilled in the art to which the present application pertains can easily implement the present application. The present application can be embodied in various ways, and is not limited to the embodiments described herein.

[0049] In the description of the present application, the expressions "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" etc. mean that the specific features, structures, materials or characteristics represented in connection with the embodiment or example are included in at least one embodiment or example of the present application. Also, the specific features, structures, materials or characteristics represented can be combined in an appropriate manner in any one or more embodiments or examples. In addition, the person skilled in the art can combine and combine the different embodiments or examples represented in the present application and the features of the different embodiments or examples, without contradiction.

[0050] In addition, the terms "first", "second" are used only for the purpose of representation, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined with "first", "second" can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise specifically limited.

[0051] In order to clearly explain the present application, the devices irrelevant to the description are omitted, and the same reference numerals are assigned to the same or similar constituent elements throughout the specification.

[0052] Throughout the specification, when it is said that a device is "connected" to another device, it includes not only the case of "direct connection", but also the case of "indirect connection" in which other elements are interposed therebetween. In addition, when it is said that a device "includes" a certain constituent element, unless otherwise specifically stated, other constituent elements are not excluded, but it means that other constituent elements can also be included.

[0053] When it is said that a device is "on" another device, it can be directly on the other device, but can also be accompanied by other devices therebetween. When it is said that a device is "directly" on another device, there are no other devices therebetween.

[0054] As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and / or "including", when used herein, specify the presence of stated features, steps, operations, elements, components, items, kinds and / or groups but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, items, kinds and / or groups thereof. As used herein, the terms "or" and "and / or" are to be interpreted as inclusive, i.e., as meaning one or any combination of the items. Thus, "A, B or C" or "A, B and / or C" means any of the following: A; B; C; A and B; A and C; B and C; A, B and C. Exceptions to this definition apply only when the combination of elements, functions, steps or acts are mutually exclusive by their nature, as is evident to one of ordinary skill in the art.

[0055] Although not differently defined, technical and scientific terms used herein include technical terms and scientific terms as commonly understood within the technical field of the present application. Terms defined in commonly used dictionaries are to be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and are not to be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0056] Embodiment 1

[0057] As shown in FIG. 4, each shift register in the scan driving circuit in the present embodiment includes:

[0058] a first transistor T1, a first electrode of the first transistor T1 is electrically connected with the first node P1, a second electrode is electrically connected with the input terminal IN, and a gate electrode is electrically connected with the third control terminal K3;

[0059] a second transistor T2, a first electrode of the second transistor T2 is electrically connected with the first power supply VDD, a second electrode is electrically connected with the first node P1, and a gate electrode is electrically connected with the first control terminal K1;

[0060] a third transistor T3, a first electrode of the third transistor T3 is electrically connected with the first power supply VDD, a second electrode is electrically connected with the second node P2, and a gate electrode is electrically connected with the first control terminal K1;

[0061] a fourth transistor T4, a first electrode of the fourth transistor T4 is electrically connected with the input terminal IN, a second electrode is electrically connected with the second node P2, and a gate electrode is electrically connected with the third control terminal K3;

[0062] a fifth transistor T5, a first electrode of the fifth transistor T5 is electrically connected with the third node P3, a second electrode is electrically connected with the first power supply VDD, and a gate electrode is electrically connected with the second node P2;

[0063] The sixth transistor T6 has its first electrode electrically connected to the third node P3, its second electrode electrically connected to the second power supply VEE, and its gate electrically connected to the first control end K1.

[0064] The seventh transistor T7 has its first electrode electrically connected to the first power supply VDD, its second electrode electrically connected to the fifth node P5, and its gate electrically connected to the third node P3.

[0065] The eighth transistor T8 has its first electrode electrically connected to the fifth node P5, its second electrode electrically connected to the second control end K2, and its gate electrically connected to the fourth node P4.

[0066] The ninth transistor T9 has its first electrode electrically connected to the first node P1, its second electrode electrically connected to the fourth node P4, and its gate electrically connected to the second power supply VEE.

[0067] The first capacitor C1 has its two ends electrically connected to the first power supply VDD and the third node P3, respectively.

[0068] The second capacitor C2 has its two ends electrically connected to the fourth node P4 and the fifth node P5, respectively.

[0069] The third capacitor C3 has its two ends electrically connected to the first power supply VDD and the second node P2, respectively.

[0070] The seventh transistor T7 and the fifth node P5 are provided with an output end OUT.

[0071] The scan driving circuit 10 further comprises a timing controller 11 for controlling the shift registers.

[0072] In the embodiment, the first transistor T1 to the ninth transistor T9 are all PMOS transistors. The control end of the PMOS transistor is the gate, the first electrode is the source, and the second electrode is the drain, or the first electrode is the drain, and the second electrode is the source. The on potential of the PMOS transistor is the low potential L, and the off potential is the high potential H.

[0073] In other embodiments, according to design requirements, all the transistors can be replaced by NMOS transistors or CMOS transistors.

[0074] In the embodiment, as shown in FIG. 2, the scan driving circuit 10 comprises a plurality of serially connected shift registers.

[0075] Taking five cascaded shift register units as an example, the signal input end IN1 of the first shift register 1 inputs a start pulse signal STV as an input signal, the output end OUT1 outputs a scanning signal out1 as an input signal in2 of the second shift register 2, and is connected with the input end IN2 of the second shift register 2; the output end OUT2 of the second shift register 2 outputs a scanning signal out2 as an input signal in3 of the third shift register 3, and is connected with the input end IN3 of the third shift register 3; the output end OUT3 of the third shift register 3 outputs a scanning signal out3 as an input signal in4 of the fourth shift register 4, and is connected with the input end IN4 of the fourth shift register 4; the output end OUT4 of the fourth shift register 4 outputs a scanning signal out4 as an input signal in5 of the fifth shift register 5, and is connected with the input end IN5 of the fifth shift register 5; the subsequent shift registers are repeated in this way to form the scanning driving circuit 10.

[0076] As shown in FIG. 2, the scanning driving circuit 10 further includes a first signal line CK1, a second signal line CK2 and a third signal line CK3, the first signal line CK1, the second signal line CK2 and the third signal line CK3 are electrically connected with the timing controller 11, and each shift register is electrically connected with the first signal line CK1, the second signal line CK2 and the third signal line CK3; the first signal line CK1 is used for outputting a first clock signal ck1; the second signal line CK2 is used for outputting a second clock signal ck2; and the third signal line CK3 is used for outputting a third clock signal ck3.

[0077] Further, the first control end K1 of the 3N-2th shift register is electrically connected with the first signal line CK1, the second control end K2 is electrically connected with the second signal line CK2, and the third control end K3 is electrically connected with the third signal line CK3, N being a positive integer; the first control end K1 of the 3N-1th shift register is electrically connected with the third signal line CK3, the second control end K2 is electrically connected with the first signal line CK1, and the third control end K3 is electrically connected with the second signal line CK2, N being a positive integer; the first control end K1 of the 3Nth shift register is electrically connected with the second signal line CK2, the second control end K2 is electrically connected with the third signal line CK3, and the third control end K3 is electrically connected with the first signal line CK1; N being a positive integer. Each shift register of the scanning driving circuit 10 receives three kinds of clock signals according to the above rules.

[0078] As shown in FIG. 3, the first clock signal ck1, the second clock signal ck2 and the third clock signal ck3 are periodic square wave signals with the same frequency; one period of the square wave signal has a length of 3t, including a low level with a length of t and a high level with a length of 2t; the first clock signal ck1 is delayed by t from the input signal in of the shift register, the second clock signal ck2 is delayed by t from the first clock signal ck1, and the third clock signal ck3 is delayed by t from the second clock signal ck2.

[0079] As shown in FIG. 3, the waveform diagram mainly includes five processes of t1 to t5, and in the five processes, the output signal out of the output end OUT of the shift register completes a process from setting to resetting.

[0080] As shown in FIG. 3 and FIG. 6, in the t1 process, the start pulse signal STV or the input signal in inputs a low potential L, the first signal line CK1 inputs a high potential H, the second signal line CK2 inputs a high potential H, and the third signal line CK3 inputs a low potential L. At this time, the second transistor T2, the third transistor T3, the sixth transistor T6 and the seventh transistor T7 are all closed by the high potential H input by the first signal line CK1; the first transistor T1 and the fourth transistor T4 are both opened by the low potential L input by the third signal line CK3 and the input end IN; the fifth transistor T5 is opened by the low potential L written by the fourth transistor T4 through the second node P2, the ninth transistor T9 is opened by the low potential L written by the first transistor T1 through the first node P1, and the eighth transistor T8 is opened by the low potential L written by the ninth transistor T9 through the fourth node P4. Finally, the output end OUT outputs a high potential by the eighth transistor T8 through the second signal line CK2.

[0081] As shown in FIG. 3 and FIG. 7, in the t2 process, the start pulse signal STV or the input signal in inputs a high potential H, the first signal line CK1 inputs a high potential H, the second signal line CK2 inputs a low potential L, and the third signal line CK3 inputs a high potential H. At this time, the second transistor T2, the third transistor T3, the sixth transistor T6 and the seventh transistor T7 are all closed by the high potential H input by the first signal line CK1; the first transistor T1 and the fourth transistor T4 are both closed by the high potential H input by the third signal line CK3 and the input end IN; the eighth transistor T8 is opened by the low potential L input by the second signal line CK2, the ninth transistor T9 is opened by the low potential L written by the eighth transistor T8 through the fourth node P4, and the fifth transistor T5 is opened. Finally, the output end OUT outputs a low potential by the eighth transistor T8 through the second signal line CK2.

[0082] As shown in FIG. 3 and FIG. 8, during t3, the start pulse signal STV or the input signal in inputs high potential H, the first signal line CK1 inputs low potential L, the second signal line CK2 inputs high potential H, and the third signal line CK3 inputs high potential H. At this time, the second transistor T2, the third transistor T3, the sixth transistor T6, and the seventh transistor T7 are all opened by the low potential L inputted by the first signal line CK1; the first transistor T1 and the fourth transistor T4 are simultaneously closed by the high potential H inputted by the third signal line CK3 and the input terminal IN; the eighth transistor T8 is closed by the high potential H inputted by the second signal line CK2 and the input, the ninth transistor T9 is opened by the low potential L written by the second transistor T2 through the first node P1, and the fifth transistor T5 is closed. Finally, the output terminal OUT outputs high potential H by the first power supply VDD through the seventh transistor T7.

[0083] As shown in FIG. 3 and FIG. 9, during t4, the start pulse signal STV or the input signal in inputs high potential H, the first signal line CK1 inputs high potential H, the second signal line CK2 inputs high potential H, and the third signal line CK3 inputs low potential L. At this time, the second transistor T2, the third transistor T3, and the sixth transistor T6 are all closed by the high potential H inputted by the first signal line CK1; the first transistor T1 and the fourth transistor T4 are opened by the low potential L inputted by the third signal line CK3; the eighth transistor T8 is closed by the high potential H inputted by the second signal line CK2, the ninth transistor T9 is opened by the low potential L written by the first transistor T1 through the first node P1, the fifth transistor T5 is closed, and the seventh transistor T7 is opened. Finally, the output terminal OUT outputs high potential H by the first power supply VDD through the seventh transistor T7.

[0084] As shown in FIG. 3 and FIG. 10, during t5, the start pulse signal STV or the input signal in inputs high potential H, the first signal line CK1 inputs high potential H, the second signal line CK2 inputs low potential L, and the third signal line CK3 inputs high potential H. At this time, the second transistor T2, the third transistor T3, the fifth transistor T5, and the sixth transistor T6 are all closed by the high potential H inputted by the first signal line CK1; the first transistor T1 and the fourth transistor T4 are simultaneously closed by the high potential H inputted by the third signal line CK3 and the input terminal IN; the eighth transistor T8 is closed by the high potential H written by the first transistor T1 through the first node P1, the ninth transistor T9 is opened, and the seventh transistor T7 is opened. Finally, the output terminal OUT outputs high potential H by the first power supply VDD through the seventh transistor T7.

[0085] As shown in FIG. 3, the working steps of the shift register after the t5 process are repeated t3 to t5 processes, and the output signal out continuously is high potential H until the start pulse signal STV or the input signal in is low potential L, and re-enters the next round of t1 process.

[0086] In the embodiment, the relationship between the input and the output of the shift register is that if the start pulse signal STV or the input signal in is low L in a certain process, then under the control of the first signal line CK1, the second signal line CK2 and the third signal line CK3, the output terminal OUT also outputs low L in the next process. In other processes, the start pulse signal STV or the input signal in and the output signal out all maintain high H until the start pulse signal STV or the input signal in becomes low L again, and the output terminal OUT outputs low L again. That is, the shift register outputs low L from the output terminal OUT after delaying the low L from the start pulse signal STV or the input signal in.

[0087] As shown in FIG. 1, the embodiment also provides a display panel, comprising the data driver 20, the display area 40, the light-emitting driving circuit 30 and the scan driving circuit 10 as any one of the above; the data driver 20 is electrically connected with the timing controller 11 and the display area 40, the light-emitting driving circuit 30 is electrically connected with the timing controller 11 and the display area 40, and the scan driving circuit 10 is electrically connected with the display area 40.

[0088] The scan driving circuit and the display panel comprising the same in the embodiment improve the structure of the scan driving circuit, reduce the number of elements inside the shift register, thereby reducing the required number of elements, and reduce the cost of the OLED panel and the required frame width.

[0089] Embodiment 2

[0090] As shown in FIG. 1 and FIG. 5, the embodiment is different from embodiment 1 in that:

[0091] The first electrode of the first transistor T1 is electrically connected with the first node P1, the second electrode is electrically connected with the input terminal IN, and the gate electrode is electrically connected with the third control terminal K3.

[0092] In summary, the purpose of the present application is to provide a scan driving circuit and a display panel comprising the same, which improves the structure of the scan driving circuit, thereby reducing the required number of elements and the required frame width of the OLED panel.

[0093] The above is a further detailed description of the present application in combination with specific preferred embodiments, and the specific implementation of the present application cannot be limited to these descriptions. For ordinary skilled persons in the technical field to which the present application belongs, a number of simple deductions or replacements can be made without departing from the concept of the present application, and all of them should be regarded as falling within the protection scope of the present application.

Claims

1. A scan driving circuit, characterized by comprising: The scan driving circuit (10) comprises a plurality of serially connected shift registers, each of which comprises: a first transistor (T1) having a first node (P1) and an input terminal (IN) electrically connected thereto; a second transistor (T2) having a first electrode electrically connected to a first power supply (VDD), a second electrode electrically connected to the first node (P1), and a gate electrically connected to a first control terminal (K1); a third transistor (T3) having a first electrode electrically connected to the first power supply (VDD), a second electrode electrically connected to a second node (P2), and a gate electrically connected to the first control terminal (K1); a fourth transistor (T4) having a first electrode electrically connected to the input terminal (IN), a second electrode electrically connected to the second node (P2), and a gate electrically connected to a third control terminal (K3); a fifth transistor (T5) having a first electrode electrically connected to a third node (P3), a second electrode electrically connected to the first power supply (VDD), and a gate electrically connected to the second node (P2); a sixth transistor (T6) having a first electrode electrically connected to the third node (P3), a second electrode electrically connected to a second power supply (VEE), and a gate electrically connected to the first control terminal (K1); a seventh transistor (T7) having a first electrode electrically connected to the first power supply (VDD), a second electrode electrically connected to a fifth node (P5), and a gate electrically connected to the third node (P3); an eighth transistor (T8) having a first electrode electrically connected to the fifth node (P5), a second electrode electrically connected to a second control terminal (K2), and a gate electrically connected to a fourth node (P4); a ninth transistor (T9) having a first electrode electrically connected to the first node (P1), a second electrode electrically connected to the fourth node (P4), and a gate electrically connected to the second power supply (VEE); a first capacitor (C1) having two ends electrically connected to the first power supply (VDD) and the third node (P3), respectively; a second capacitor (C2) having two ends electrically connected to the fourth node (P4) and the fifth node (P5), respectively; a third capacitor (C3) having two ends electrically connected to the first power supply (VDD) and the second node (P2), respectively; an output terminal (OUT) is provided between the seventh transistor (T7) and the fifth node (P5); The scan driving circuit (10) further comprises a timing controller (11) for controlling each of the shift registers.

2. The scan driving circuit according to claim 1, wherein The first transistor (T1) has a first electrode electrically connected to the first node (P1), a second electrode electrically connected to the input terminal (IN), and a gate electrically connected to the third control terminal (K3).

3. The scan driving circuit according to claim 1, wherein The first electrode of the first transistor (T1) is electrically connected with the first node (P1), the second electrode is electrically connected with the second power supply (VEE), and the gate electrode is electrically connected with the input end (IN).

4. The scan driving circuit according to claim 1, wherein The scan driving circuit (10) further comprises a first signal line (CK1), a second signal line (CK2) and a third signal line (CK3), wherein the first signal line (CK1), the second signal line (CK2) and the third signal line (CK3) are electrically connected with the timing controller (11), and each of the shift registers is electrically connected with the first signal line (CK1), the second signal line (CK2) and the third signal line (CK3). The first signal line (CK1) is used for outputting a first clock signal; the second signal line (CK2) is used for outputting a second clock signal; and the third signal line (CK3) is used for outputting a third clock signal.

5. The scan driving circuit according to claim 4, wherein The first clock signal, the second clock signal and the third clock signal are periodic square wave signals with the same frequency; and the length of one period of the square wave signal is 3t, including a low level with a length of t and a high level with a length of 2t.

6. The scan driving circuit according to claim 5, wherein The first clock signal is delayed by t from the input signal of the shift register, the second clock signal is delayed by t from the first clock signal, and the third clock signal is delayed by t from the second clock signal.

7. The scan driving circuit according to claim 4, wherein The first control end (K1) of the shift register at the 3N-2th stage is electrically connected with the first signal line (CK1), the second control end (K2) is electrically connected with the second signal line (CK2), and the third control end (K3) is electrically connected with the third signal line (CK3); N is a positive integer.

8. The scan driving circuit according to claim 7, wherein The first control end (K1) of the shift register at the 3N-1th stage is electrically connected with the third signal line (CK3), the second control end (K2) is electrically connected with the first signal line (CK1), and the third control end (K3) is electrically connected with the second signal line (CK2); N is a positive integer.

9. The scan driving circuit according to claim 8, wherein The first control end (K1) of the shift register at the 3Nth stage is electrically connected with the second signal line (CK2), the second control end (K2) is electrically connected with the third signal line (CK3), and the third control end (K3) is electrically connected with the first signal line (CK1); N is a positive integer.

10. A display panel, characterized by, The display panel comprises a data driver (20), a display area (40), a light-emitting driving circuit (30) and the scan driving circuit (10) according to any one of claims 1-9. The data driver (20) is electrically connected with the timing controller (11) and the display area (40), the light-emitting driving circuit (30) is electrically connected with the timing controller (11) and the display area (40), and the scan driving circuit (10) is electrically connected with the display area (40).

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