Chip packaging unit, package-on-package, and electronic device

Abstract

The present application relates to the field of chips, and provides a chip packaging unit, a package-on-package, and an electronic device. The chip packaging unit comprises a first chip and a second chip that are stacked, a redistribution layer, and a vertical interconnection structure. The vertical interconnection structure is arranged on side surfaces of the first chip and the second chip. The redistribution layer is arranged on the side of one chip where an active surface is located, and is connected to the active surface. Alternatively, the redistribution layer is arranged between active surfaces of the two chips, and is connected to the two active surfaces. Moreover, the redistribution layer is connected to the vertical interconnection structure. The active surfaces of the chips are fanned out using the redistribution layer, and longitudinal interconnection is achieved by means of the vertical interconnection structure located on the side surfaces of the chips; thus, the need for through silicon vias passing through the chips is eliminated, and the manufacturing process complexity can be reduced, thereby lowering manufacturing costs.

Description

Chip packaging unit, stacked package and electronic device TECHNICAL FIELD

[0001] The present application relates to the field of chips, in particular to a chip packaging unit, a stacked package and an electronic device. BACKGROUND

[0002] POP (package on package) packaging is a technology of packaging multiple chips together, which can also be referred to as stacked packaging. In POP packaging, multiple chips are vertically stacked together and are interconnected in the vertical direction through through silicon vias (TSV) passing through the chips. This technology can improve the space utilization of the circuit board, reduce the overall size and weight of the device, and improve performance.

[0003] Taking an HBM (high bandwidth memory) package as an example, as shown in FIG. 1, the HBM package includes multiple DRAMs (dynamic random access memories) stacked together, and the multiple DRAMs are interconnected in the vertical direction through through silicon vias TSVs. The multiple DRAMs are below a logic chip, and the logic chip controls the multiple DRAMs. In this packaging structure, the manufacturing process of the through silicon vias TSVs is difficult, the yield of the product is low, and the cost of the product is high. SUMMARY

[0004] The present application provides a chip packaging unit, a stacked package and an electronic device. A fan-out manner is adopted, vertical interconnection structures located on the side surfaces of the chips are used to realize vertical interconnection, and through silicon vias are not needed, which can reduce the manufacturing process difficulty and in turn reduce the manufacturing cost.

[0005] The present application provides a chip packaging unit, which includes a first chip and a second chip stacked together, multiple vertical interconnection structures, a rewiring layer, and multiple first soldering points. The passive surface of the first chip is arranged opposite to the passive surface of the second chip. The multiple vertical interconnection structures are located on the side surfaces of the first chip and the second chip stacked together. The rewiring layer is located on the side of the active surface of the first chip. The multiple first soldering points are respectively arranged on the active surface of the second chip and the side of the multiple vertical interconnection structures away from the rewiring layer. The active surface of the first chip and the first ends of the multiple vertical interconnection structures are electrically connected to the rewiring layer, and the active surface of the second chip and the second ends of the multiple vertical interconnection structures are electrically connected to the multiple first soldering points.

[0006] When the plurality of chip packaging units are stacked, the first solder joints can be used to connect two chip packaging units. In this case, the first chip in the chip packaging unit is electrically connected to the vertical interconnection structure on the side surface through the redistribution layer in a fan-out manner, so as to realize the interconnection communication in the longitudinal direction. The second chip can realize the interconnection communication in the longitudinal direction through the redistribution layer and the vertical interconnection structure in the chip packaging unit stacked below. That is, the chip packaging unit does not need to pass through the through silicon via when applied to the stacked packaging structure, but is connected to the vertical interconnection structure on the side surface of the chip through the redistribution layer in a fan-out manner, so as to realize the interconnection of the chip in the longitudinal direction. Since the vertical interconnection structure is located on the side surface of the chip and does not need to pass through the chip, the manufacturing process is relatively low in difficulty, so that the yield of the product is improved and the cost is reduced.

[0007] In some possible implementations, the chip packaging unit further includes a plurality of first connection pads arranged on the surface of the redistribution layer away from the first chip. The plurality of connection pads can be used to realize the interconnection between other devices (such as packaging units) arranged thereon. For example, the chip packaging unit can be interconnected with another chip packaging unit stacked on the top through the plurality of first connection pads.

[0008] In some possible implementations, the chip packaging unit includes a prefabricated interconnection module, and the plurality of vertical interconnection structures are arranged in the prefabricated interconnection module. The prefabricated interconnection module is provided with a plurality of second solder joints on the side close to the redistribution layer, and the vertical interconnection structures are electrically connected to the redistribution layer through the plurality of second solder joints. In the case that the vertical interconnection structures are manufactured in the prefabricated interconnection module, the prefabricated interconnection module is provided with the solder joints connected to the vertical interconnection structures on the side close to the redistribution layer, so that the height of the vertical interconnection structures can be reduced, and the manufacturing difficulty can be reduced, and the yield can be improved. In addition, the prefabricated interconnection module can be manufactured separately, so that the prefabricated interconnection module can be detected in advance, and the unqualified prefabricated interconnection module can be avoided to cause the whole chip packaging unit to be unqualified, so that the yield can be improved.

[0009] In some possible implementations, the prefabricated interconnection module includes a silicon wafer and a plurality of through silicon vias (TSVs) arranged in the silicon wafer. The plurality of through silicon vias are used to form the plurality of vertical interconnection structures, and the plurality of through silicon vias are electrically connected to the redistribution layer through the plurality of second solder joints.

[0010] In some possible implementation manners, the pre-prepared interconnection module includes a glass sheet and a plurality of through glass vias (TGVs) arranged in the glass sheet. The plurality of through glass vias are used to form a plurality of vertical interconnection structures, and the plurality of through glass vias are electrically connected to the redistribution layer through a plurality of second solder joints.

[0011] In some possible implementation manners, the pre-prepared interconnection module includes a molding layer and a plurality of through molding vias (TMVs) arranged in the molding layer. The plurality of through molding vias are used to form a plurality of vertical interconnection structures, and the plurality of through molding vias are electrically connected to the redistribution layer through a plurality of second solder joints.

[0012] In some possible implementation manners, the vertical interconnection structure adopts a through insulator via (TIV). In this case, the vertical interconnection structure can be directly fabricated on the redistribution layer and in direct contact with the redistribution layer in the process of fabricating the chip packaging unit, and the plurality of vertical interconnection structures can be molded by using the same molding process as the first chip and the second chip.

[0013] The application further provides a chip packaging unit, which includes a redistribution layer, a first chip, a plurality of first vertical interconnection structures, a second chip, a plurality of second vertical interconnection structures, and a plurality of first solder joints. The redistribution layer includes oppositely arranged first and second surfaces. The first chip and the plurality of first vertical interconnection structures are arranged on one side of the first surface. The second chip and the plurality of second vertical interconnection structures are arranged on one side of the second surface. The plurality of first solder joints are arranged on a side of the plurality of second vertical interconnection structures away from the redistribution layer and connected to the plurality of second vertical interconnection structures. The first chip has an active surface facing the first surface and electrically connected to the first surface. The second chip has an active surface facing the second surface and electrically connected to the second surface. The first vertical interconnection structures are arranged on a side of the first chip and connected to the first surface. The second vertical interconnection structures are arranged on a side of the second chip and connected between the first solder joints and the second surface.

[0014] When a plurality of chip packaging units are stacked, two adjacent chip packaging units can be electrically connected through a plurality of solder joints. The first chip and the second chip are connected to the vertical interconnection structures on the side in a fan-out manner through the redistribution layer, so as to realize the interconnection of the chips in the longitudinal direction. Since the vertical interconnection structures are arranged on the side of the chip and do not need to pass through the chip, the manufacturing process is relatively low in difficulty, so that the yield of the product is improved and the cost is reduced.

[0015] In some possible implementation manners, the chip packaging unit further includes a plurality of first connection pads located on a side of the plurality of first vertical interconnection structures away from the redistribution layer and connected with the plurality of first vertical interconnection structures. The plurality of first connection pads are used to realize interconnection between the chip packaging unit and other devices (such as a packaging unit) located thereon. For example, the chip packaging unit can be interconnected with another chip packaging unit stacked on top through the plurality of first connection pads.

[0016] In some possible implementation manners, the chip packaging unit includes a first prefabricated interconnection module, the plurality of first vertical interconnection structures are arranged in the first prefabricated interconnection module, the first prefabricated interconnection module is arranged with a plurality of second solder joints on a side close to the first surface, and the first vertical interconnection structures are connected with the first surface through the plurality of second solder joints. The first prefabricated interconnection module can be used to reduce the height of the first vertical interconnection structures through the second solder joints, thereby reducing the manufacturing difficulty and improving the yield.

[0017] In some possible implementation manners, the first prefabricated interconnection module includes a first silicon wafer and a plurality of first through silicon vias arranged in the first silicon wafer. The plurality of first through silicon vias are used to form the plurality of first vertical interconnection structures, and the plurality of first through silicon vias are connected with the first surface through the plurality of second solder joints.

[0018] In some possible implementation manners, the first prefabricated interconnection module includes a first glass wafer and a plurality of first through glass vias arranged in the first glass wafer. The plurality of first through glass vias are used to form the plurality of first vertical interconnection structures, and the plurality of first through glass vias are connected with the first surface through the plurality of second solder joints.

[0019] In some possible implementation manners, the first prefabricated interconnection module includes a first molding layer and a plurality of first through molding vias arranged in the first molding layer. The plurality of first through molding vias are used to form the plurality of first vertical interconnection structures, and the plurality of first through molding vias are connected with the first surface through the plurality of second solder joints.

[0020] In some possible implementation manners, the first vertical interconnection structure is a through-insulator via (TIV). In this case, the first vertical interconnection structure can be manufactured in the process of manufacturing the chip packaging unit, the second vertical interconnection structure can be directly in contact with the redistribution layer, and the first vertical interconnection structure and the first chip can be molded by using the same molding process.

[0021] In some possible implementation manners, the chip packaging unit includes a second pre-interconnection module, and a plurality of second vertical interconnection structures are arranged in the second pre-interconnection module. The second pre-interconnection module is arranged with a plurality of third soldering points on a side close to the second surface, and the plurality of second vertical interconnection structures are connected to the second surface through the plurality of third soldering points. The second pre-interconnection module can be used to reduce the height of the second vertical interconnection structures through the third soldering points, thereby reducing the manufacturing difficulty and improving the yield rate. In addition, the second pre-interconnection module can be manufactured separately, so that the second pre-interconnection module can be detected in advance, and the entire chip packaging unit can be prevented from being unqualified due to unqualified second pre-interconnection modules, thereby improving the yield rate.

[0022] In some possible implementation manners, the second pre-interconnection module includes a second silicon wafer and a plurality of second through silicon vias arranged in the second silicon wafer. The plurality of second through silicon vias are used to form the plurality of second vertical interconnection structures, and the plurality of second through silicon vias are connected to the second surface through the plurality of third soldering points.

[0023] In some possible implementation manners, the second pre-interconnection module includes a second glass wafer and a plurality of second through glass vias arranged in the second glass wafer. The plurality of second through glass vias are used to form the plurality of second vertical interconnection structures, and the plurality of second through glass vias are connected to the second surface through the plurality of third soldering points.

[0024] In some possible implementation manners, the second pre-interconnection module includes a second molding layer and a plurality of second through molding vias and a plurality of third soldering points arranged in the second molding layer. The plurality of second through molding vias are used to form the plurality of second vertical interconnection structures, and the plurality of second through molding vias are connected to the second surface through the plurality of third soldering points.

[0025] In some possible implementation manners, the second vertical interconnection structure is a through-insulator via (TIV). In this case, the second vertical interconnection structure can be manufactured in the process of manufacturing the chip packaging unit, the second vertical interconnection structure is in direct contact with the redistribution layer, and the second vertical interconnection structure and the second chip can be molded by using the same molding process.

[0026] The application further provides a stacked package including at least two chip packaging units provided in any of the foregoing implementation manners and stacked.

[0027] The application also provides another kind of stack package, which comprises a substrate and a first chip, a second chip and a third chip stacked in sequence in a direction close to the substrate. The active surfaces of the first chip, the second chip and the third chip all face the substrate. The active surface of the first chip comprises a first region and a second region, the second region overlaps the second chip, and the second region protrudes from the edge of the second chip. The active surface of the second chip comprises a third region and a fourth region, the fourth region overlaps the third chip, and the third region protrudes from the edge of the third chip; the first region and the third region are located on the same side of the third chip. The stack package further comprises a plurality of first vertical interconnection structures, a plurality of second vertical interconnection structures and a plurality of third vertical interconnection structures. The plurality of first vertical interconnection structures are located on the side surface of the second chip; the plurality of second vertical interconnection structures and the plurality of third vertical interconnection structures are located on the side surface of the third chip; the plurality of second vertical interconnection structures are connected with the third region, and the plurality of third vertical interconnection structures are connected with the first region through the plurality of first vertical interconnection structures.

[0028] In the above stack package, a through-silicon via penetrating through the chip is not needed, and the vertical interconnection structure located on the side surface of the chip is used to realize the vertical interconnection of the chip. Since the vertical interconnection structure is located on the side surface of the chip and does not need to penetrate through the chip, the manufacturing process is relatively low in difficulty, thereby improving the yield rate of the product and reducing the cost.

[0029] In some possible implementation manners, the above stack package comprises a first pre-interconnection module, and the plurality of first vertical interconnection structures are located in the first pre-interconnection module. The first pre-interconnection module is provided with a plurality of first soldering points on the side close to the first region, and the plurality of first vertical interconnection structures are connected with the first region through the plurality of first soldering points. In the case that the first vertical interconnection structure is manufactured in the first pre-interconnection module, the first pre-interconnection module is provided with the soldering points connected with the first vertical interconnection structure on the side close to the redistribution layer, thereby reducing the height of the first vertical interconnection structure and further reducing the manufacturing difficulty and improving the yield rate. In addition, the first pre-interconnection module can be manufactured separately, thereby enabling the first pre-interconnection module to be detected in advance and avoiding the case that the entire chip packaging unit is unqualified due to the unqualified first pre-interconnection module, thereby improving the yield rate.

[0030] In some possible implementation manners, the first pre-interconnection module comprises a first silicon wafer and a plurality of first through-silicon vias arranged in the first silicon wafer. The plurality of first through-silicon vias are used to form the plurality of first vertical interconnection structures, and the plurality of first through-silicon vias are connected with the first region through the plurality of first soldering points.

[0031] In some possible implementation manners, the first pre-prepared interconnection module includes a first glass sheet and a plurality of first glass through holes arranged in the first glass sheet, the plurality of first glass through holes being used to form a plurality of first vertical interconnection structures, and the plurality of first glass through holes being connected to the first region through a plurality of first solder joints.

[0032] In some possible implementation manners, the first pre-prepared interconnection module includes a first molding layer and a plurality of first molding through holes arranged in the first molding layer, the plurality of first molding through holes being used to form a plurality of first vertical interconnection structures, and the plurality of first molding through holes being connected to the first region through a plurality of first solder joints.

[0033] In some possible implementation manners, the first vertical interconnection structure can be a through insulator via (TIV). In this case, the first vertical interconnection structure does not need to be provided with a solder joint at one end close to the first region, and the connection structure of the first vertical interconnection structure and the first region is directly in contact. Moreover, the first vertical interconnection structure can be molded by using the same molding process as the first chip.

[0034] In some possible implementation manners, the second pre-prepared interconnection module is included in the stacked package, and the plurality of second vertical interconnection structures and the plurality of third vertical interconnection structures are located in the second pre-prepared interconnection module. The second pre-prepared interconnection module is provided with a plurality of second solder joints on a side away from the substrate; the plurality of second vertical interconnection structures are connected to the third region through the plurality of second solder joints, and the plurality of third vertical interconnection structures are connected to the plurality of first vertical interconnection structures through the plurality of second solder joints.

[0035] In the case of manufacturing the second vertical interconnection structure in the second pre-prepared interconnection module, the second pre-prepared interconnection module is provided with a solder joint connected to the second vertical interconnection structure on a side close to the redistribution layer, so that the height of the second vertical interconnection structure can be reduced, and the manufacturing difficulty can be reduced, and the yield can be improved. In addition, the second pre-prepared interconnection module can be manufactured separately, so that the second pre-prepared interconnection module can be detected in advance, and the entire chip packaging unit can be prevented from being unqualified due to unqualified second pre-prepared interconnection modules, so that the yield can be improved.

[0036] In some possible implementation manners, the second pre-prepared interconnection module includes a second silicon sheet and a plurality of second silicon through holes arranged in the second silicon sheet, the plurality of second silicon through holes being used to form the plurality of second vertical interconnection structures and the plurality of third vertical interconnection structures, and a plurality of second solder joints being arranged on a side of the second silicon sheet close to the first chip and connected to the plurality of second silicon through holes.

[0037] In some possible implementation manners, the second prefabricated interconnection module comprises a second glass sheet and a plurality of second glass through holes arranged in the second glass sheet, the plurality of second glass through holes being used to form a plurality of second vertical interconnection structures and a plurality of third vertical interconnection structures; and a plurality of second solder joints are arranged on a side of the second glass sheet close to the first chip and connected with the plurality of second glass through holes.

[0038] In some possible implementation manners, the second prefabricated interconnection module comprises a second molding layer and a plurality of second molding through holes arranged in the second molding layer, the plurality of second molding through holes being used to form a plurality of second vertical interconnection structures and a plurality of third vertical interconnection structures; and a plurality of second solder joints are arranged on a side of the second molding layer close to the first chip and connected with the plurality of second molding through holes.

[0039] In some possible implementation manners, the second vertical interconnection structure and the third vertical interconnection structure can adopt a through insulator via (TIV). In this case, the second vertical interconnection structure and the third vertical interconnection structure do not need to be provided with a solder joint at an end close to the first chip, and the second vertical interconnection structure is directly connected with the connection structure of the third region. Moreover, the second vertical interconnection structure and the third vertical interconnection structure can be molded by using the same molding process as the third chip.

[0040] The application further provides an electronic device comprising a circuit board and a stacked package provided in any of the possible implementation manners described above, and the circuit board is electrically connected with the stacked package. BRIEF DESCRIPTION OF DRAWINGS

[0041] FIG. 1 is a structural schematic diagram of a stacked package provided in the prior art;

[0042] FIG. 2 is a structural schematic diagram of a stacked package provided in an embodiment of the application;

[0043] FIG. 3 is a structural schematic diagram of a chip packaging unit provided in an embodiment of the application;

[0044] FIG. 4 is a schematic diagram of a chip packaging unit in a manufacturing process provided in an embodiment of the application;

[0045] FIG. 5 is a structural schematic diagram of a chip packaging unit provided in an embodiment of the application;

[0046] FIG. 6 is a structural schematic diagram of a prefabricated interconnection module provided in an embodiment of the application;

[0047] FIG. 7 is a structural schematic diagram of a prefabricated interconnection module provided in an embodiment of the application;

[0048] FIG. 8 is a structural schematic diagram of a prefabricated interconnection module provided in an embodiment of the application;

[0049] Fig. 9 is a structural schematic diagram of a prefabricated interconnection module according to an embodiment of the present application;

[0050] Fig. 10 is a schematic diagram of a prefabricated interconnection module in a manufacturing process according to an embodiment of the present application;

[0051] Fig. 11 is a schematic diagram of a chip packaging unit in a manufacturing process according to an embodiment of the present application;

[0052] Fig. 12 is a schematic diagram of a stacked package in a manufacturing process according to an embodiment of the present application;

[0053] Fig. 13 is a schematic diagram of a stacked package in a manufacturing process according to an embodiment of the present application;

[0054] Fig. 14 is a structural schematic diagram of a chip packaging unit according to an embodiment of the present application;

[0055] Fig. 15 is a structural schematic diagram of a chip packaging unit according to an embodiment of the present application;

[0056] Fig. 16 is a schematic diagram of a stacked package in a manufacturing process according to an embodiment of the present application;

[0057] Fig. 17 is a schematic diagram of a stacked package in a manufacturing process according to an embodiment of the present application;

[0058] Fig. 18 is a schematic diagram of a stacked package in a manufacturing process according to an embodiment of the present application;

[0059] Fig. 19 is a schematic diagram of a stacked package in a manufacturing process according to an embodiment of the present application;

[0060] Fig. 20 is a structural schematic diagram of a stacked package according to an embodiment of the present application;

[0061] Fig. 21 is a schematic diagram of a stacked package in a manufacturing process according to an embodiment of the present application;

[0062] Fig. 22 is a schematic diagram of a stacked package in a manufacturing process according to an embodiment of the present application. DETAILED DESCRIPTION

[0063] In order to make the objectives, technical solutions and advantages of the present application clearer, the technical solutions in the present application will be described clearly and completely below with reference to the drawings in the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0064] The terms "first", "second", etc. in the description embodiments of the present application and claims and drawings are only used for distinguishing description purposes and cannot be understood as indicating or implying relative importance, nor can be understood as indicating or implying sequence. "And / or" is used to describe the association relationship of the associated objects, which means that there can be three relationships, for example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, wherein A and B can be singular or plural. The character " / " generally represents an "or" relationship between the front and rear associated objects. "At least one (item)" means one or more, and "multiple" means two or more. "Installation", "connection", "connection" and the like should be broadly understood, for example, it can be an electrical connection, or a mechanical connection; it can be a fixed connection, or a detachable connection, or an integral connection; it can be a direct connection, or an indirect connection through an intermediate medium, or a communication between two elements. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a series of steps or units. The method, system, product or device does not have to be limited to those steps or units clearly listed, but can include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices. "Up", "down", "left", "right" and the like are only used for the orientation of the components in the drawings, and these directional terms are relative concepts, which are used for relative description and clarification, which can change accordingly according to the change of the orientation of the components in the drawings.

[0065] The electronic device provided by the embodiments of the present application adopts a new type of chip stack packaging (which can be referred to as stack packaging for short), and the packaging structure adopts a fan-out mode to realize longitudinal interconnection through a vertical interconnection structure located on the side surface of the chip, without using through-silicon vias penetrating through the chip, so as to reduce the difficulty of manufacturing process, and further reduce the manufacturing cost.

[0066] The embodiments of the present application do not limit the setting form of the above-mentioned electronic device, and the electronic device can be any electronic product provided with the chip stack packaging, such as consumer electronic products, home electronic products, vehicle-mounted electronic products, financial terminal products, communication electronic products, etc.

[0067] For example, the consumer electronic product can be a mobile phone, a tablet computer, a notebook computer, a personal computer (PC), a personal digital assistant (PDA), a smart wearable product (for example, a smart watch, a smart bracelet, etc.), a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a drone, etc. The home electronic product can be a smart door lock, a television, a smart speaker, a refrigerator, a sweeping robot, etc. The vehicle-mounted electronic product can be a vehicle-mounted navigator, a vehicle-mounted display, etc. The financial terminal product can be an automated teller machine (ATM), a self-service electronic device, etc. The communication electronic product can be a server, a memory, a radar, a base station, etc.

[0068] According to actual needs, the electronic device can further be provided with other devices electrically connected with the chip stack package, such as a printed circuit board (PCB), an input / output device, etc., which are not limited in the present application.

[0069] The present application does not limit the application scenarios of the chip stack package, which can be set as needed in practice.

[0070] For example, in some possible implementation manners, the chip stack package provided by the embodiments of the present application can be applied to storage class package products, such as DRAM (dynamic random access memory), UFS (universal flash storage) and other storage packages.

[0071] For another example, in some possible implementation manners, the chip stack package provided by the embodiments of the present application can be applied to a SOC (system on chip).

[0072] The following embodiments are all taken as an example of HBM stack package using DRAM to illustrate the stack package structure provided by the present application.

[0073] As shown in FIG. 2, the HBM package provided by the embodiment of the present application includes a substrate 100, a plurality of memory chip packaging units U1, and a logic chip packaging unit U2. The logic chip packaging unit U2 is disposed on the substrate 100, and the plurality of memory chip packaging units U1 are stacked on the logic chip packaging unit U2. The substrate 100 can be a redistribution layer (RDL) substrate, an ABF (ajinomoto build-up film) substrate, a PCB (printed circuit board) substrate, or the like, which is not limited in the present application.

[0074] The plurality of memory chip packaging units U1 can adopt the novel chip packaging unit provided by the present application, which realizes vertical interconnection by the vertical interconnection structure on the side of the chip, without using through-silicon vias.

[0075] The novel chip packaging unit and related content provided by the present application are described below by specific embodiments.

[0076] Embodiment One

[0077] As shown in FIG. 3, the chip packaging unit 1 provided by the embodiment one includes a redistribution layer RDL, a first chip D1, a second chip D2, a plurality of vertical interconnection structures 10, and a plurality of solder joints 21 (also referred to as first solder joints). The first chip D1 and the second chip D2 can be memory chips, such as DRAMs.

[0078] The first chip D1 and the second chip D2 are stacked, and the passive surfaces of the first chip D1 and the second chip D2 are disposed opposite to each other, i.e., the back surfaces of the first chip D1 and the second chip D2 are disposed opposite to each other (B2B). The passive surfaces of the first chip D1 and the second chip D2 can be fixed by a die attach film (DAF).

[0079] Continuing to refer to FIG. 3, the plurality of vertical interconnection structures 10 are located on the side of the stacked first chip D1 and the second chip D2. The redistribution layer RDL is located on the side of the active surface A1 of the first chip D1. The active surface A1 of the first chip D1 and the upper ends (also referred to as first ends) of the plurality of vertical interconnection structures 10 are electrically connected to the redistribution layer RDL. The redistribution layer RDL can realize high-density interconnection in the horizontal direction. The plurality of vertical interconnection structures 10 can realize high-density interconnection in the vertical direction.

[0080] With continued reference to FIG. 3, the plurality of solder joints 21 are located on a side of the active surface A2 of the second chip D2. The plurality of solder joints 21 are respectively disposed below (i.e. away from the redistribution layer RDL) the active surface A2 of the second chip D2 and the plurality of vertical interconnect structures 10, and are electrically connected to the active surface A2 of the second chip D2 and the lower ends (may also be referred to as second ends) of the plurality of vertical interconnect structures 10. The chip packaging unit 1 is connected to other devices (such as packaging units) through the plurality of solder joints 21.

[0081] It should be noted that one solder joint 21 can be electrically connected to one vertical interconnect structure 10, or can be electrically connected to a plurality of vertical interconnect structures 10, which is not limited in the present application, and can be set as needed in practice.

[0082] The solder joint 21 can be a micro bump (μbump) such as a copper pillar bump (Cu pillar bump) or a solder bump, which is not limited in the present application. The solder joint involved in the following is the same, which will not be described hereinafter.

[0083] It should be understood that the chip (such as D1, D2) includes an active device layer (such as a field effect transistor layer) made by a front end of line (FEOL) process on the front surface of the substrate, and a metal trace layer made by a back end of line (BEOL) process, which is connected to the active device layer. The active surface of the chip refers to the side surface on which the active device layer and the metal trace layer are disposed, and the inactive surface refers to the surface on the back surface of the substrate on which the active device layer is not disposed, and the inactive surface is disposed opposite to the active surface.

[0084] In addition, with continued reference to FIG. 3, in some possible implementations, the chip packaging unit 1 further includes a plurality of connection pads P1 (may also be referred to as first connection pads), which are disposed on the upper surface of the redistribution layer RDL (i.e. away from the first chip) to realize interconnection between other devices (such as packaging units) located thereon through the plurality of connection pads P1. For example, the chip packaging unit can be interconnected with another chip packaging unit stacked on top through the plurality of connection pads P1.

[0085] Of course, in some possible implementations, in the case where no other devices (such as packaging units) are stacked on top of the chip packaging unit 1, the upper surface of the redistribution layer RDL can not be provided with the connection pads P1.

[0086] In this embodiment one, when the plurality of chip packaging units 1 are stacked, the chip packaging unit 1 on the top can be electrically connected to the connection pad P1 on the top of the chip packaging unit 1 below through the plurality of solder joints 21. The first chip D1 is connected to the vertical interconnection structure 10 on the side through the upper redistribution layer RDL for fan-out, to realize the interconnection communication in the longitudinal direction. The second chip D2 can realize the interconnection communication in the longitudinal direction through the redistribution layer RDL and the vertical interconnection structure 10 in the chip packaging unit 1 below.

[0087] In the existing stacked packaging, a through-silicon via passing through the chip is needed to realize the longitudinal interconnection. However, the through-silicon via passing through the chip has the disadvantage of high process difficulty, which will cause the yield of the product to decrease, and thus the cost of the product is high.

[0088] In contrast, the chip packaging unit 1 provided in this embodiment one does not need to set a through-silicon via passing through the chip when applied to a stacked packaging structure, but is connected to the vertical interconnection structure 10 on the side of the chip (D1, D2) through the redistribution layer RDL in a fan-out manner, to realize the interconnection of the chip in the longitudinal direction. Since the vertical interconnection structure 10 is located on the side of the chip (D1, D2), it does not need to pass through the chip, and thus the process difficulty is relatively low, so that the yield of the product is improved and the cost is reduced.

[0089] This embodiment one does not limit the specific setting mode of the vertical interconnection structure 10, which can be set as needed in practice.

[0090] Setting mode one

[0091] In some possible implementation manners, as shown in FIG. 3, the vertical interconnection structure 10 can be an insulator via TIV (through insulator via) directly made on the redistribution layer RDL in the process of making the chip packaging unit 1. In this case, the insulator via TIV (10) is in direct contact with the redistribution layer RDL, and no solder joint needs to be set between the two.

[0092] In this setting mode, the manufacturing process of the chip packaging unit 1 can include:

[0093] First, as shown in (a) of FIG. 4, the redistribution layer RDL is made on the carrier board.

[0094] Then, as shown in (b) of FIG. 4, the insulator via TIV is made on the redistribution layer RDL as the vertical interconnection structure 10.

[0095] Then, referring to (c) of FIG. 4, the first chip D1 and the second chip D2 arranged in the stack are soldered on the redistribution layer RDL. The arrangement of the first chip D1 and the second chip D2 can refer to the foregoing, and will not be described herein.

[0096] Then, referring to (d) of FIG. 4, the chips (D1, D2) and the plurality of insulator vias TIV(10) are collectively encapsulated by using a plastic encapsulation process, and the chips (D1, D2) and the plurality of insulator vias TIV are encapsulated into the molding layer 30.

[0097] Then, subsequent manufacturing processes can be performed according to actual needs.

[0098] Arrangement Mode Two

[0099] In some possible implementation manners, referring to FIG. 5, the vertical interconnection structure 10 can be arranged in the prefabricated interconnection module 2, and the vertical interconnection structure 10 can be a through-silicon via TSV, a through-glass via TGV, or a through-molding via TMV. In this case, the prefabricated interconnection module 2 is provided with a soldering point 22 (a second soldering point) on a side close to the redistribution layer RDL, and during manufacturing of the chip packaging unit 1, the prefabricated interconnection module 2 can be directly soldered to the redistribution layer RDL, and in this case, the vertical interconnection structure 10 is interconnected with the redistribution layer RDL through the soldering point 22.

[0100] Hereinafter, the structure of the prefabricated interconnection module 2 will be described by taking examples of the vertical interconnection structure 10 being a through-silicon via TSV, a through-glass via TGV, and a through-molding via TMV, respectively.

[0101] For example, referring to FIG. 6, the prefabricated interconnection module 2 includes a silicon wafer 20a, a plurality of through-silicon vias TSV, a soldering point 22, and a connecting pad P2 (such as a copper pillar). The plurality of through-silicon vias TSV penetrate through the silicon wafer 20a and are used as the vertical interconnection structure 10. The soldering point 22 and the connecting pad P2 are respectively arranged at two ends of the through-silicon via TSV and connected with the two ends of the through-silicon via TSV. In this case, in combination with FIGS. 5 and 6, during manufacturing of the chip packaging unit 1, the prefabricated interconnection module 2 is connected with the redistribution layer RDL through the soldering point 22 and connected with the soldering point 21 through the connecting pad P2.

[0102] For example, referring to FIG. 7, the prefabricated interconnection module 2 includes a glass sheet 20b, a plurality of glass vias TGV, a solder joint 22, and a connecting pad P2 (e.g., a copper pillar). The plurality of glass vias TGV pass through the glass sheet 20b and serve as the vertical interconnection structure 10. The solder joint 22 and the connecting pad P2 are respectively arranged at two ends of the glass via TGV and are connected to the two ends of the glass via TGV. In this case, referring to FIGS. 5 and 7, when the chip packaging unit 1 is manufactured, the prefabricated interconnection module 2 is connected to the redistribution layer RDL through the solder joint 22 and is connected to the solder joint 21 through the connecting pad P2.

[0103] For example, referring to FIG. 8, the prefabricated interconnection module 2 includes a molding layer 20c, a plurality of molding vias TMV, a solder joint 22, and a connecting pad P2 (e.g., a copper pillar). The plurality of molding vias TMV pass through the molding layer 20c and serve as the vertical interconnection structure 10. The solder joint 22 and the connecting pad P2 are respectively arranged at two ends of the molding via TMV and are connected to the two ends of the molding via TMV. In this case, referring to FIGS. 5 and 7, when the chip packaging unit 1 is manufactured, the prefabricated interconnection module 2 is connected to the redistribution layer RDL through the solder joint 22 and is connected to the solder joint 21 through the connecting pad P2.

[0104] Compared with the first arrangement mode, in which the vertical interconnection structure 10 is directly manufactured on the redistribution layer RDL during the manufacturing of the chip packaging unit 1, in the second arrangement mode, the vertical interconnection structure 10 is manufactured on the prefabricated interconnection module 2. In this case, the prefabricated interconnection module 2 is arranged with the solder joint 22 connected to the vertical interconnection structure 10 on the side close to the redistribution layer RDL, so that the height of the vertical interconnection structure 10 can be reduced, and the manufacturing difficulty can be reduced, and the yield can be improved.

[0105] In addition, in the first arrangement mode, in which the vertical interconnection structure 10 is directly manufactured on the redistribution layer RDL during the manufacturing of the chip packaging unit 1, if the vertical interconnection structure 10 is unqualified, the entire packaging unit 1 will be unqualified, resulting in a low yield. In the second arrangement mode, the prefabricated interconnection module 2 is separately manufactured, and the prefabricated interconnection module 2 can be detected in advance, so that the entire chip packaging unit 1 can be prevented from being unqualified due to the unqualified prefabricated interconnection module 2, and the yield can be improved.

[0106] In the prefabricated interconnection module 2 shown in FIGS. 6, 7, and 8, the connecting pad P2 is arranged on the top of the vertical interconnection structure 10 (TSV, TGV, TMV), but the present application is not limited thereto. In another possible implementation, referring to FIG. 9, the connecting pad P2 is not arranged on the top of the vertical interconnection structure 10 (TSV, TGV, TMV), and the vertical interconnection structure 10 is directly connected to the solder joint 21.

[0107] It should be understood that by providing the connecting pad P2 on the top of the vertical interconnection structure 10 (TSV, TGV, TMV), the height of the vertical interconnection structure 10 (TSV, TGV, TMV) can be reduced, and the manufacturing difficulty can be reduced, and the yield can be improved.

[0108] Taking the vertical interconnection structure 10 as an example, the manufacturing process of the prefabricated interconnection module 2 is briefly described as follows.

[0109] In some possible implementation manners, the manufacturing process of the prefabricated interconnection module 2 can include the following steps.

[0110] First, as shown in (a) of FIG. 10, a plurality of metal columns (i.e., vertical interconnection structures 10) are manufactured on a carrier plate C2 (such as a glass plate).

[0111] Then, as shown in (b) of FIG. 10, the plurality of metal columns (10) are molded by using a molding process, and the top of the metal column (10) is exposed by grinding, so that the plurality of metal columns form a through mold via TMV (10) in the molding layer.

[0112] Then, as shown in (c) of FIG. 10, a solder joint 22 is manufactured on the top of the through mold via TMV.

[0113] Then, as shown in (d) of FIG. 10, the carrier plate C1 is debonded (DB), and another carrier plate C2 is temporarily bonded (TB) on one side of the solder joint 22.

[0114] Then, as shown in (e) of FIG. 10, a connecting pad P2 is manufactured on the top of the through mold via TMV.

[0115] Then, as shown in (f) of FIG. 10, the side provided with the connecting pad P2 is pasted to a frame, and the carrier plate C2 is debonded (DB), and the prefabricated interconnection module 2 is formed by cutting.

[0116] In addition, taking the vertical interconnection structure 10 as an example, the manufacturing process of the chip packaging unit 1 is described as follows.

[0117] In some possible implementation manners, the manufacturing process of the chip packaging unit 1 provided in the embodiment can include the following steps.

[0118] First, as shown in (a) of FIG. 11, a redistribution layer RDL is manufactured on a carrier plate (such as glass).

[0119] Then, as shown in (b) of FIG. 11, the stacked first chip D1 and second chip D2, and the prefabricated interconnection module 2 are welded to the redistribution layer RDL. As for the related settings of the stacked first chip D1 and second chip D2, and the prefabricated interconnection module 2, reference can be made to the related content described above, which will not be repeated here.

[0120] Then, as shown in (c) of FIG. 11, the stacked first chip D1 and second chip D2, and the prefabricated interconnection module 2 are molded by using a molding process, and then polished by using a polishing process, and finally the solder joint 21 connected to the prefabricated interconnection module 2 and the second chip D2 is made.

[0121] Then, according to actual needs, subsequent manufacturing processes can be performed, such as debonding the bottom carrier board, etc.

[0122] Taking the application of the chip packaging unit 1 provided in Embodiment One in HBM stacked packaging as an example, the manufacturing process of HBM stacked packaging is described below.

[0123] In addition, Embodiment One also provides a manufacturing method of HBM stacked packaging, which can include:

[0124] First, as shown in (a) of FIG. 12, a redistribution layer RDL1 is made on a carrier board (such as glass) as a substrate. Then one or more logic chips logic are welded to the redistribution layer RDL1, and a prefabricated interconnection module 2 is installed on the side of the logic chip. Then the prefabricated interconnection module 2 and the logic chip logic are molded by using a molding process, and the top is polished. Then a redistribution layer RDL2 is made above the prefabricated interconnection module 2 and the logic chip logic. The vertical interconnection structure 10 in the prefabricated interconnection module 2 is electrically connected between the redistribution layer RDL1 and the redistribution layer RDL2.

[0125] FIG. 12 is described by taking the vertical interconnection structure 10 located in the prefabricated interconnection module 2 as an example, in other possible implementation manners, the vertical interconnection structure 10 can be directly made on the redistribution layer RDL1 and directly contact the redistribution layer RDL1. As for different setting modes of the vertical interconnection structure 10, reference can be made to the related description described above, which will not be repeated here.

[0126] Then, as shown in (b) of FIG. 12, the plurality of chip packaging units 1 (storage chip packaging units) provided in the embodiment are first stacked and welded, and then welded to the surface of the redistribution layer RDL2.

[0127] Then, referring to FIG. 13, the chip packaging unit 1 and the logic chip logic can be molded. The bottom carrier is debonded, and solder balls are made on the bottom of the RDL1. The single stacked package is formed by cutting.

[0128] Embodiment Two

[0129] As shown in FIGS. 14 and 15, the chip packaging unit 1 includes an RDL, a first chip D1, a second chip D2, a plurality of first vertical interconnection structures 11, a plurality of second vertical interconnection structures 12, and a plurality of solder joints 21 (also referred to as first solder joints). The first chip D1 and the second chip D2 can be memory chips, such as DRAMs.

[0130] The first chip D1 and the plurality of first vertical interconnection structures 11 are disposed on the upper surface of the RDL. The active surface of the first chip D1 faces the RDL and is connected (e.g., soldered) to the RDL. The plurality of first vertical interconnection structures 11 are in direct contact with the RDL or connected to the RDL through solder joints, as described in detail below.

[0131] The second chip D2 and the plurality of second vertical interconnection structures 12 are disposed on the lower surface of the RDL. The active surface of the second chip D2 faces the RDL and is connected (e.g., soldered) to the RDL. The plurality of second vertical interconnection structures 12 are in direct contact with the RDL or connected to the RDL through solder joints, as described in detail below.

[0132] The plurality of solder joints 21 are disposed below (i.e., away from the RDL) the plurality of second vertical interconnection structures 12 and connected to the plurality of second vertical interconnection structures 12, respectively. The chip packaging unit 1 is connected to other devices (e.g., packaging units) through the plurality of solder joints 21.

[0133] Of course, in the case where the top of the chip packaging unit 1 is not stacked with other devices (e.g., packaging units), in some possible implementations, the first vertical interconnection structures 11 can not be disposed. In other possible implementations, the plurality of first vertical interconnection structures 11 can be disposed for heat dissipation and not for electrical connection.

[0134] In this embodiment two, the RDL disposed between the first chip D1 and the second chip D2 is used for fan-out, which can achieve high-density interconnection in the horizontal direction. The plurality of first vertical interconnection structures 11 and the plurality of second vertical interconnection structures 12 can achieve high-density interconnection in the vertical direction.

[0135] The arrangement of the plurality of first vertical interconnection structures 11 and the plurality of second vertical interconnection structures 12 is similar to the arrangement of the vertical interconnection structure 10 in Embodiment One.

[0136] For the plurality of first vertical interconnection structures 11, for example:

[0137] In some possible implementation manners, as shown in FIG. 14, the plurality of first vertical interconnection structures 11 can be made of insulator vias TIV directly on the upper surface of the redistribution layer RDL. In this case, the plurality of first vertical interconnection structures 11 can be encapsulated by the same encapsulation process as the first chip D1, and the plurality of first vertical interconnection structures 11 are in direct contact with the redistribution layer RDL. For details, please refer to the related description in Embodiment One.

[0138] In the case where the plurality of first vertical interconnection structures 11 are made of insulator vias TIV, a connecting pad can be made on the top (the side away from the redistribution layer) of the first vertical interconnection structure 11, and the connecting pad is used to realize electrical connection with other stacked packaging units on the top. Of course, the top of the first vertical interconnection structure 11 can also not be provided with a connecting pad, and other stacked packaging units on the top are directly connected to the top of the first vertical interconnection structure 11 through a soldering point.

[0139] In some possible implementation manners, as shown in FIG. 15, the plurality of first vertical interconnection structures 11 can be arranged in the first prefabricated interconnection module 2a, in which case the first vertical interconnection structure 11 can be connected to the redistribution layer RDL through a soldering point (such as a copper pillar), and the first vertical interconnection structure 11 can be made of a silicon via TSV, a glass via TGV, or a molded via TMV, etc. For details, please refer to the description of the prefabricated interconnection module in Embodiment One, which will not be repeated here.

[0140] For the plurality of second vertical interconnection structures 12, for example:

[0141] In some possible implementation manners, as shown in FIG. 14, the plurality of second vertical interconnection structures 12 can be made of insulator vias TIV directly on the lower surface of the redistribution layer RDL, in which case the plurality of second vertical interconnection structures 12 can be encapsulated by the same encapsulation process as the second chip D2, and the plurality of second vertical interconnection structures 12 are in direct contact with the redistribution layer RDL. For details, please refer to the related description in Embodiment One.

[0142] In some possible implementation manners, referring to FIG. 15, a plurality of second vertical interconnection structures 12 can be arranged in the second prefabricated interconnection module 2b, in which case, the second vertical interconnection structure 12 can be connected with the redistribution layer RDL through a solder joint, and the second vertical interconnection structure 12 can be a through-silicon via TSV, a through-glass via TGV or a through-mold via TMV, and specific details can be referred to the description of the prefabricated interconnection module in Embodiment One, which will not be repeated here.

[0143] In this embodiment two, when a plurality of chip packaging units 1 are stacked, the chip packaging unit 1 located on the upper side can be electrically connected with the first vertical interconnection structure 11 in the chip packaging unit 1 located on the lower side through a plurality of solder joints 21. In this case, the first chip D1 and the second chip D2 are fan-out through the redistribution layer RDL and connected with the second vertical interconnection structure 12 on the side surface, so as to realize the interconnection communication in the longitudinal direction.

[0144] That is to say, the chip packaging unit 1 provided in this embodiment does not need to be provided with a through-silicon via passing through the chip when applied to a stacked packaging structure, but is connected with the vertical interconnection structure (11, 12) on the side surface of the chip (D1, D2) in a fan-out manner through the redistribution layer RDL, so as to realize the interconnection of the chip in the longitudinal direction. Since the vertical interconnection structure (11, 12) is located on the side surface of the chip (D1, D2) and does not need to pass through the chip, the manufacturing process is relatively low in difficulty, so that the yield of the product is improved and the cost is reduced.

[0145] In addition, referring to FIG. 14 and FIG. 15, the chip packaging unit 1 can be provided with a suspended connection structure 23, such as a bump, on the surface on the side of the second chip D2, so as to improve the heat dissipation performance of the product, and the connection structure 23 can be used for welding with another chip packaging unit 1 stacked below.

[0146] In addition, referring to FIG. 14 and FIG. 15, in order to realize the stacking of the chip packaging unit 1, the chip packaging unit 1 can be provided with a suspended connection structure 24, such as a pad, on the surface on the side of the first chip D1, so as to be welded with another chip packaging unit 1 on the top of the chip packaging unit 1.

[0147] Hereinafter, taking the first vertical interconnection structure 11 and the second vertical interconnection structure 12 as both being an insulator via TIV as an example, the manufacturing process of the chip packaging unit 1 provided in this embodiment two will be described.

[0148] In some possible implementation manners, the manufacturing process of the chip packaging unit 1 provided in this embodiment two can include the following steps.

[0149] First, as shown in (a) of FIG. 16, insulator vias TIV are made on the carrier C1 as the first vertical interconnection structure 11, and the passive side of the first chip D1 is attached to the carrier C1 through a chip adhesive film DAF.

[0150] Then, as shown in (b) of FIG. 16, the first chip D1 and the first vertical interconnection structure 11 are molded, and the first vertical interconnection structure 11 and the solder (e.g., copper pillar) on the active side of the first chip D1 are exposed by grinding.

[0151] Then, as shown in (c) of FIG. 16, a redistribution layer RDL is made to connect the first vertical interconnection structure 11.

[0152] Then, as shown in (a) of FIG. 17, insulator vias TIV are made on the redistribution layer RDL as the second vertical interconnection structure 12, and the active side of the second chip D2 is soldered to the redistribution layer RDL.

[0153] Then, as shown in (b) of FIG. 17, the second chip D2 and the second vertical interconnection structure 12 are molded, and the second vertical interconnection structure 12 is exposed by grinding.

[0154] Then, as shown in (c) of FIG. 17, a solder 21 is made on the top of the second vertical interconnection structure 12.

[0155] Subsequent processes can be performed according to actual needs, such as debonding the bottom carrier C1.

[0156] Taking the application of the chip packaging unit 1 provided in Embodiment Two in HBM stacked packaging as an example, the manufacturing process of HBM stacked packaging is described below.

[0157] In an embodiment, a manufacturing method of HBM stacked packaging is provided, which can include:

[0158] First, as shown in (a) of FIG. 18, a redistribution layer RDL1 is made on a carrier (e.g., glass) as a substrate. Then, one or more logic chips logic are soldered to the redistribution layer RDL1, and a prefabricated interconnection module 2 is mounted on the side of the logic chip. Then, the prefabricated interconnection module 2 and the logic chip logic are molded, and the top is ground. Then, a redistribution layer RDL2 is made above the prefabricated interconnection module 2 and the logic chip logic. The vertical interconnection structure 10 in the prefabricated interconnection module 2 is electrically connected between the redistribution layer RDL1 and the redistribution layer RDL2.

[0159] In FIG. 18, the vertical interconnection structure 10 is located in the prefabricated interconnection module 2 as an example. In other possible implementations, the vertical interconnection structure 10 can be directly fabricated on the redistribution layer RDL1 and directly contact the redistribution layer RDL1. Of course, the vertical interconnection structure 10 can also use a through-insulator via TIV. For the arrangement of the vertical interconnection structure 10, please refer to the previous description, which will not be repeated here.

[0160] Then, as shown in (b) of FIG. 18, the plurality of chip packaging units 1 (storage chip packaging units) provided in this embodiment 2 are first stacked and welded in multiple layers, and then welded to the redistribution layer RDL2.

[0161] Then, as shown in FIG. 19, the chip packaging unit 1 and the logic chip logic can be molded by a molding process; then the bottom carrier board is debonded, and solder balls are made at the bottom of the redistribution layer RDL1, and a single stacked package is formed by cutting.

[0162] Embodiment Three

[0163] This embodiment three provides another chip stacked package, as shown in FIG. 20, which includes a substrate (RDL), and a first chip D1, a second chip D2 and a third chip D3 arranged on the substrate (RDL). Among them, the first chip D1, the second chip D2 and the third chip D3 are arranged in sequence from top to bottom (i.e. close to the substrate (RDL) direction), and the active surfaces of the first chip D1, the second chip D2 and the third chip D3 all face the substrate (RDL) side.

[0164] Continuing to refer to FIG. 20, the active surface of the first chip D1 includes a first area A1 and a second area A2, and the active surface of the second chip D2 includes a third area A2 and a third area A3. The first area A1 of the first chip D1 protrudes from the edge of the second chip D2, and the second area A2 of the first chip D1 overlaps the second chip D2. The third area A3 of the second chip D2 protrudes from the edge of the third chip D3, and the fourth area A4 of the second chip D2 overlaps the third chip D3. And the first area A1 and the third area A3 are located on the same side of the third chip D3.

[0165] Continuing to refer to FIG. 20, the chip stack package further includes a plurality of first vertical interconnection structures 11, a plurality of second vertical interconnection structures 12, and a plurality of third vertical interconnection structures 13. The plurality of first vertical interconnection structures 11 are located on the side of the second chip D2, and the plurality of second vertical interconnection structures 12 and the plurality of third vertical interconnection structures 13 are located on the side of the third chip D3. The plurality of first vertical interconnection structures 11 are located opposite to the first region A1 of the first chip D1, and the plurality of first vertical interconnection structures 11 are electrically connected to the connection structure of the first region A1. The plurality of second vertical interconnection structures 12 and the plurality of third vertical interconnection structures 13 are located on the same layer and on the side of the third chip D3. The plurality of second vertical interconnection structures 12 are located opposite to the third region A3, and are electrically connected to the connection structure of the third region A3. The plurality of third vertical interconnection structures 13 are located opposite to the first region A1, and the plurality of third vertical interconnection structures 13 are electrically connected to the connection structure of the first region A1 through the plurality of first vertical interconnection structures 11.

[0166] In this case, the first chip D1 is led out to the side of the substrate (RDL) through the plurality of first vertical interconnection structures 11 and the plurality of third vertical interconnection structures 13 in the first region A1, so as to realize the interconnection communication in the longitudinal direction. The second chip D2 is led out to the side of the substrate (RDL) through the plurality of second vertical interconnection structures 12 in the third region, so as to realize the interconnection communication in the longitudinal direction. The third chip D3 can be similar to the arrangement of the second chip D2, and realizes the interconnection communication in the longitudinal direction through the vertical interconnection structures located below. The lowermost chip can be directly connected to the substrate (RDL).

[0167] The stack package provided in the third embodiment does not need to be provided with through silicon vias passing through the chip, but realizes the interconnection of the chip in the longitudinal direction through the vertical interconnection structures (11, 12, 13) located on the side of the chip. Since the vertical interconnection structures (11, 12, 13) are located on the side of the chip and do not need to pass through the chip, the manufacturing process is relatively low in difficulty, so that the yield of the product is improved and the cost is reduced.

[0168] In addition, the arrangement of the plurality of first vertical interconnection structures 11, the plurality of second vertical interconnection structures 12, and the plurality of third vertical interconnection structures 13 is similar to the arrangement of the vertical interconnection structure 10 in the first embodiment, and can be directly manufactured on the active surface side of the chip during the packaging process; or can be manufactured in advance on the prefabricated interconnection module and welded on the active surface side of the chip.

[0169] For the first vertical interconnection structure 11, for example:

[0170] In some possible implementation manners, the plurality of first vertical interconnection structures 11 can be made of through-insulation vias (TIVs) in the process of the stacked packaging. In this case, the plurality of first vertical interconnection structures 11 and the first chip D1 can be encapsulated by using the same encapsulation process, and the plurality of first vertical interconnection structures 11 are directly connected to the connection structure of the first chip D1 in the first region A1, and the plurality of first vertical interconnection structures 11 do not need to be separately provided with soldering points at the end close to the first chip D1. For details, refer to the related description in Embodiment One.

[0171] In some possible implementation manners, the plurality of first vertical interconnection structures 11 can be provided in a first pre-prepared interconnection module. In the process of the stacked packaging, the first pre-prepared interconnection module can be soldered to the connection structure of the first chip D1 in the first region A1. In this case, the first vertical interconnection structure 11 is connected to the connection structure of the first chip D1 in the first region A1 through a soldering point, and the first vertical interconnection structure 11 can be made of a through-silicon via (TSV), a through-glass via (TGV), or a through-mold via (TMV).

[0172] For the second vertical interconnection structure 12 and the third vertical interconnection structure 13, for example:

[0173] In order to simplify the process and reduce the manufacturing cost, the second vertical interconnection structure 12 and the third vertical interconnection structure 13 can be processed by using the same process.

[0174] In some possible implementation manners, the plurality of second vertical interconnection structures 12 and the plurality of third vertical interconnection structures 13 can be made of through-insulation vias (TIVs) in the process of the stacked packaging. In this case, the plurality of second vertical interconnection structures 12 and the plurality of third vertical interconnection structures 13 and the first chip D1 can be encapsulated by using the same encapsulation process, and the plurality of second vertical interconnection structures 12 are directly connected to the connection structure of the third chip D3 in the third region A3, and the plurality of third vertical interconnection structures 13 are directly connected to the end of the plurality of first vertical interconnection structures 11. The plurality of second vertical interconnection structures 12 and the plurality of third vertical interconnection structures 13 do not need to be separately provided with soldering points at the end close to the first chip D1.

[0175] In some possible implementations, the second vertical interconnection structure 12 and the third vertical interconnection structure 13 can be provided in a second prefabricated interconnection module, and the second prefabricated interconnection module is welded to the third region A3 and the first prefabricated interconnection module through soldering in the process of the stack packaging. In this case, the second vertical interconnection structure 12 is connected to the connecting structure of the second chip D2 in the third region A3 through soldering, and the third vertical interconnection structure 13 is connected to the first vertical interconnection structure 11 in the first prefabricated interconnection module through soldering. The second vertical interconnection structure 12 and the third vertical interconnection structure 13 can be a through silicon via TSV, a through glass via TGV, or a through molding via TMV, etc.

[0176] The structures of the first prefabricated interconnection module and the second prefabricated interconnection module are similar to the structure of the prefabricated interconnection module 2 in Embodiment One, and details can be referred to the related description of the prefabricated interconnection module 2 in Embodiment One, which will not be repeated here.

[0177] In addition, in the stack packaging provided in Embodiment Three, the first vertical interconnection structure 11, the second vertical interconnection structure 12, and the third vertical interconnection structure 13 can all be fabricated in the process of the stack packaging, or all be fabricated in the prefabricated interconnection module, or some of the vertical interconnection structures be fabricated in the process of the stack packaging and some of the vertical interconnection structures be fabricated in the prefabricated interconnection module. The present application does not limit this, and in practice, it can be set as needed.

[0178] In addition, Embodiment Two further provides a fabrication method of stack packaging, which can include:

[0179] First, as shown in (a) of FIG. 21, the passive surface of the first chip D1 is attached to a carrier plate (such as glass). In this case, the active surface of the first chip D1 faces upward, and the first region A1 of the active surface is provided with a connecting pad (or soldering point).

[0180] Then, as shown in (a) of FIG. 21, the second chip D2 is stacked on the active surface side of the first chip D1, and the first region A1 of the first chip D1 is exposed, and the second chip D2 is arranged overlapping the second region A2 of the first chip D1. A first prefabricated interconnection module 2a provided with a plurality of first vertical interconnection structures 11 is provided, and the first prefabricated interconnection module 2a is welded to the first region A1, so that the plurality of first vertical interconnection structures 11 are connected to the first chip D1 in the first region A1 through soldering. Then, a molding process is performed for molding, and the connecting structure on the surface of the second chip A2 and the first prefabricated interconnection module 2a is exposed by grinding.

[0181] Then, referring to (b) of FIG. 21, a third chip D3 is stacked on the active side of the second chip D2, exposing the third region A3 of the second chip D2, and the third chip D3 is arranged overlapping the fourth region A4 of the second chip D2. A second pre-interconnection module 2b provided with a plurality of second vertical interconnection structures 12 and a plurality of third vertical interconnection structures 13 is provided, and the second pre-interconnection module 2b is welded with the third region A3 and the first pre-interconnection module 2a, so that the plurality of second vertical interconnection structures 12 are interconnected with the second chip D2 at the third region A3 through the welding points, and the plurality of third vertical interconnection structures 13 are connected with the plurality of first vertical interconnection structures 11 in the first pre-interconnection module 2a through the welding points, thereby realizing the interconnection with the first region A1. After that, molding is performed, and the connection structures on the surface of the third chip A3 and the second pre-interconnection module 2b are exposed by grinding.

[0182] Then, referring to (a) of FIG. 22, the stacking of the subsequent other chips and the pre-interconnection modules is performed, and after the stacking is completed, a redistribution layer RDL is made as a substrate, and solder balls are made on the surface of the redistribution layer RDL.

[0183] Then, referring to (b) of FIG. 22, the carrier plate at the bottom of the first chip D1 is debonded, and a single stacked package is formed by cutting.

[0184] It should be understood that the manufacturing processes in the above embodiments do not mean an absolute execution sequence, and the execution sequence of each process should be determined according to its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0185] In addition, other related contents in each manufacturing method can be correspondingly referred to the corresponding part in the structure, which will not be described here; for other related setting structures, the corresponding manufacturing method and related process can be adjusted, which will not be described one by one here.

[0186] The related structures and manufacturing methods in different embodiments can be correspondingly referred to and adjusted, which will not be described one by one here.

[0187] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A chip package unit, characterized by, Comprising: a first chip and a second chip in a stacked arrangement, a passive surface of the first chip being oppositely arranged to a passive surface of the second chip; a plurality of vertical interconnection structures located at sides of the stacked arrangement of the first chip and the second chip; a redistribution layer located at a side of the first chip facing an active surface of the first chip; a plurality of first soldering points respectively arranged at a side of the active surface of the second chip and the plurality of vertical interconnection structures away from the redistribution layer; wherein the active surface of the first chip and a first end of the plurality of vertical interconnection structures are electrically connected to the redistribution layer, and the active surface of the second chip and a second end of the plurality of vertical interconnection structures are electrically connected to the plurality of first soldering points.

2. The chip package unit of claim 1, further comprising a plurality of first connection pads arranged on a surface of the redistribution layer away from the first chip.

3. The chip package unit of claim 1 or 2, wherein the chip package unit comprises a pre-interconnection module, and the plurality of vertical interconnection structures are arranged in the pre-interconnection module; and the pre-interconnection module comprises a plurality of second soldering points arranged at a side of the pre-interconnection module close to the redistribution layer, and the vertical interconnection structures are electrically connected to the redistribution layer through the plurality of second soldering points.

4. The chip package unit of claim 3, wherein the pre-interconnection module comprises a silicon wafer and a plurality of through-silicon vias (TSVs) arranged in the silicon wafer, the plurality of TSVs being used to form the plurality of vertical interconnection structures, and the plurality of TSVs being electrically connected to the redistribution layer through the plurality of second soldering points; or the pre-interconnection module comprises a glass wafer and a plurality of through-glass vias (TGVs) arranged in the glass wafer, the plurality of TGVs being used to form the plurality of vertical interconnection structures, and the plurality of TGVs being electrically connected to the redistribution layer through the plurality of second soldering points; or the pre-interconnection module comprises a molding layer and a plurality of through-molding vias (TMVs) arranged in the molding layer, the plurality of TMVs being used to form the plurality of vertical interconnection structures, and the plurality of TMVs being electrically connected to the redistribution layer through the plurality of second soldering points.

5. The chip package unit of claim 1 or 2, wherein the plurality of vertical interconnection structures are through-insulator vias (TIVs). Comprising: a redistribution layer comprising a first surface and a second surface oppositely arranged; a first chip and a plurality of first vertical interconnection structures arranged at a side of the first surface; a second chip and a plurality of second vertical interconnection structures arranged at a side of the second surface; a plurality of first soldering points located at a side of the plurality of second vertical interconnection structures away from the redistribution layer and connected to the plurality of second vertical interconnection structures; ​ ​ 6. A chip package unit, characterized by comprising: ​ ​ ​ ​ ​ The active surface of the first chip faces the first surface and is electrically connected to the first surface; the active surface of the second chip faces the second surface and is electrically connected to the second surface; the first vertical interconnection structure is located on the side surface of the first chip and is connected to the first surface; and the second vertical interconnection structure is located on the side surface of the second chip and is connected between the first solder joint and the second surface.

7. The chip package unit according to claim 6, wherein: the chip package unit comprises a first prefabricated interconnection module, and the first vertical interconnection structures are arranged in the first prefabricated interconnection module; the first prefabricated interconnection module is provided with a plurality of second solder joints on the side close to the first surface, and the first vertical interconnection structures are connected to the first surface through the second solder joints.

8. The chip package unit according to claim 7, wherein: the first prefabricated interconnection module comprises a first silicon wafer and a plurality of first through silicon vias arranged in the first silicon wafer, the first through silicon vias are used to form the first vertical interconnection structures, and the first through silicon vias are connected to the first surface through the second solder joints; or, the first prefabricated interconnection module comprises a first glass wafer and a plurality of first through glass vias arranged in the first glass wafer, the first through glass vias are used to form the first vertical interconnection structures, and the first through glass vias are connected to the first surface through the second solder joints; or, the first prefabricated interconnection module comprises a first molding layer and a plurality of first through molding vias arranged in the first molding layer, the first through molding vias are used to form the first vertical interconnection structures, and the first through molding vias are connected to the first surface through the second solder joints.

9. The chip package unit according to claim 6, wherein: the first vertical interconnection structure adopts a through insulator via (TIV).

10. The chip package unit according to any one of claims 6-9, wherein: the chip package unit comprises a second prefabricated interconnection module, and the second vertical interconnection structures are arranged in the second prefabricated interconnection module; the second prefabricated interconnection module is provided with a plurality of third solder joints on the side close to the second surface, and the second vertical interconnection structures are connected to the second surface through the third solder joints.

11. The chip package unit according to claim 10, wherein: the second prefabricated interconnection module comprises a second silicon wafer and a plurality of second through silicon vias arranged in the second silicon wafer, the second through silicon vias are used to form the second vertical interconnection structures, and the second through silicon vias are connected to the second surface through the third solder joints; or, the second prefabricated interconnection module comprises a second glass wafer and a plurality of second through glass vias arranged in the second glass wafer, the second through glass vias are used to form the second vertical interconnection structures, and the second through glass vias are connected to the second surface through the third solder joints. Alternatively, the second pre-prepared interconnection module comprises a second molding layer and a plurality of second molding through holes arranged in the second molding layer, the plurality of second molding through holes are used to form the plurality of second vertical interconnection structures, and the plurality of second molding through holes are connected with the second surface through the plurality of third solder joints.

12. The chip package unit according to any one of claims 6-9, wherein, The second vertical interconnection structure adopts a through insulator via (TIV).

13. A stacked package, comprising: The chip package unit according to any one of claims 1-12, wherein, 14. A stacked package, comprising: The chip package unit comprises a substrate and a first chip, a second chip and a third chip arranged in sequence along a direction close to the substrate; Active surfaces of the first chip, the second chip and the third chip all face the substrate; the active surface of the first chip comprises a first region and a second region, the second region overlaps with the second chip, and the second region protrudes from an edge of the second chip; the active surface of the second chip comprises a third region and a fourth region, the fourth region overlaps with the third chip, and the third region protrudes from an edge of the third chip; the first region and the third region are located on the same side of the third chip; The stack package further comprises a plurality of first vertical interconnection structures, a plurality of second vertical interconnection structures and a plurality of third vertical interconnection structures; the plurality of first vertical interconnection structures are located on a side of the second chip; the plurality of second vertical interconnection structures and the plurality of third vertical interconnection structures are located on a side of the third chip; the plurality of second vertical interconnection structures are connected with the third region, and the plurality of third vertical interconnection structures are connected with the first region through the plurality of first vertical interconnection structures.

15. The stack package according to claim 14, wherein, The stack package comprises a first pre-prepared interconnection module, and the plurality of first vertical interconnection structures are located in the first pre-prepared interconnection module; The first pre-prepared interconnection module is provided with a plurality of first solder joints on a side close to the first region, and the plurality of first vertical interconnection structures are connected with the first region through the plurality of first solder joints.

16. The stack package according to claim 15, wherein, The first pre-prepared interconnection module comprises a first silicon wafer and a plurality of first silicon through holes arranged in the first silicon wafer, the plurality of first silicon through holes are used to form the plurality of first vertical interconnection structures, and the plurality of first silicon through holes are connected with the first region through the plurality of first solder joints; Alternatively, the first pre-prepared interconnection module comprises a first glass wafer and a plurality of first glass through holes arranged in the first glass wafer, the plurality of first glass through holes are used to form the plurality of first vertical interconnection structures, and the plurality of first glass through holes are connected with the first region through the plurality of first solder joints; Alternatively, the first pre-made interconnect module includes a first molding layer and a plurality of first molding vias disposed in the first molding layer, the plurality of first molding vias being used to form the plurality of first vertical interconnect structures, and the plurality of first molding vias being connected to the first region through the plurality of first solder joints.

17. The package-on-package of claim 14, wherein: the first vertical interconnect structures are through insulator vias (TIVs).

18. The package-on-package of any one of claims 14-17, wherein: a second pre-made interconnect module is included in the package-on-package, the plurality of second vertical interconnect structures and the plurality of third vertical interconnect structures being located in the second pre-made interconnect module; the second pre-made interconnect module is provided with a plurality of second solder joints on a side distal to the substrate, the plurality of second vertical interconnect structures being connected to the third region through the plurality of second solder joints, and the plurality of third vertical interconnect structures being connected to the plurality of first vertical interconnect structures through the plurality of second solder joints.

19. The package-on-package of claim 18, wherein: the second pre-made interconnect module includes a second silicon wafer and a plurality of second through silicon vias disposed in the second silicon wafer, the plurality of second through silicon vias being used to form the plurality of second vertical interconnect structures and the plurality of third vertical interconnect structures, and the plurality of second through silicon vias being connected to the plurality of second solder joints; Alternatively, the second pre-made interconnect module includes a second glass wafer and a plurality of second through glass vias disposed in the second glass wafer, the plurality of second through glass vias being used to form the plurality of second vertical interconnect structures and the plurality of third vertical interconnect structures, and the plurality of second through glass vias being connected to the plurality of second solder joints; Alternatively, the second pre-made interconnect module includes a second molding layer and a plurality of second molding vias disposed in the second molding layer, the plurality of second molding vias being used to form the plurality of second vertical interconnect structures and the plurality of third vertical interconnect structures, and the plurality of second molding vias being connected to the plurality of second solder joints.

20. The package-on-package of any one of claims 14-17, wherein: the second vertical interconnect structures and the third vertical interconnect structures are through insulator vias (TIVs).

21. An electronic device, comprising: a circuit board is electrically connected to the package-on-package as claimed in any one of claims 13-20.

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