Chip package-on-package and manufacturing method therefor, and electronic device

Abstract

The present application relates to the field of package-on-package. Provided are a chip package-on-package and a manufacturing method therefor, and an electronic device, which can shorten the packaging cycle time and maintain a higher interconnection density while improving the heat dissipation performance. The chip package-on-package comprises a redistribution layer, a first chip, a substrate, a second chip, a vertical connection structure, a first heat dissipation member and a welding joint, wherein the first chip is disposed on a surface of the redistribution layer and is electrically connected to the redistribution layer; the substrate is disposed on the side of the first chip away from the redistribution layer, and the substrate is provided with a hollowed-out region; the second chip is disposed on the side of the substrate away from the first chip, and is electrically connected to the substrate; the vertical connection structure is connected between the substrate and the redistribution layer; the first heat dissipation member is disposed on the surface of the first chip on the side close to the substrate and extends into the hollowed-out region; and the welding joint is disposed on the side of the redistribution layer away from the first chip, and is electrically connected to the redistribution layer.

Description

Chip stack package, manufacturing method thereof and electronic device TECHNICAL FIELD

[0001] The present application relates to the field of stack package, in particular to a chip stack package, a manufacturing method thereof and an electronic device. BACKGROUND

[0002] POP (Package on Package) stack package is a technology of packaging multiple integrated circuits (IC, chip) together to realize smaller, lighter and thinner electronic devices. In the POP package, one package is stacked on another package and connected by solder balls. This technology can improve the space utilization of the circuit board, reduce the overall size and weight of the device, and improve the performance.

[0003] With the continuous development of electronic products, the size of components is becoming smaller and smaller. In addition, the structure of the POP package is relatively complex, and the problems of high-density interconnection, heat dissipation and cost become more and more important. SUMMARY

[0004] The present application provides a chip stack package, a manufacturing method thereof and an electronic device, which can shorten the packaging cycle time while improving the heat dissipation performance and maintaining a high interconnection density.

[0005] The present application provides a chip stack package, which comprises a redistribution layer, a first chip, a substrate, a second chip, a vertical connection structure, a first heat dissipation member and a solder point. The first chip is arranged on the surface of the redistribution layer and electrically connected with the redistribution layer. The substrate is arranged on the side of the first chip away from the redistribution layer, and the substrate is provided with a hollow area. The second chip is arranged on the side of the substrate away from the first chip and electrically connected with the substrate. The vertical connection structure is connected between the substrate and the redistribution layer. The first heat dissipation member is arranged on the surface of the first chip close to the substrate and extends into the hollow area. The solder point is arranged on the side of the redistribution layer away from the first chip and electrically connected with the redistribution layer.

[0006] In the stack package structure provided by the present application, the substrate provided with the hollow area is used to carry the second chip. On the one hand, the first heat dissipation member can be arranged at the position of the hollow area to improve the heat dissipation performance of the stack package structure. On the other hand, the substrate can be pre-manufactured, and the assembly can be performed during packaging, so that the packaging cycle time can be greatly shortened, the overall packaging process can be optimized, and the cost can be reduced. In addition, the redistribution layer is used to carry the first chip, and the redistribution layer is manufactured by photolithography and electroplating. The photolithography and electroplating process can stably achieve a line size within a few microns, which can make the hole and the wire smaller, so as to improve the distribution density of the solder point and realize high-density interconnection.

[0007] In some possible implementation manners, the surface of the first heat dissipation member protrudes from the surface of the substrate on the side away from the first chip, so as to improve the heat dissipation performance of the packaging structure.

[0008] In some possible implementation manners, the first heat dissipation member includes a first heat dissipation structure and a second heat dissipation structure, the first heat dissipation structure and the second heat dissipation structure are stacked on the first chip, and the second heat dissipation structure is located on the side of the first heat dissipation structure away from the first chip. The first heat dissipation structure, the vertical interconnection structure, the first chip and the substrate are encapsulated in a first molding layer, and on the side away from the first chip, the surface of the first heat dissipation structure is flush with the surface of the first molding layer. By stacking the first heat dissipation structure and the second heat dissipation structure on the first chip, the second heat dissipation structure can protrude from the surface of the substrate, so as to improve the heat dissipation performance.

[0009] In some possible implementation manners, the chip stack package further includes a second heat dissipation member. The second heat dissipation member is arranged on the side of the substrate away from the first chip and connected with the substrate, so as to improve the heat dissipation performance of the packaging structure.

[0010] In some possible implementation manners, the second heat dissipation member is distributed around the second chip, so as to improve the heat dissipation performance of the packaging structure.

[0011] In some possible implementation manners, the first chip includes a system on chip (SOC).

[0012] In some possible implementation manners, the second chip includes a double data rate (DDR) synchronous dynamic random access memory chip.

[0013] The application further provides a manufacturing method of a chip stack package, which can include: manufacturing a redistribution layer on a carrier board, manufacturing a vertical interconnection structure on the redistribution layer, and flip-chip mounting a first chip on the redistribution layer. A first heat dissipation structure is fixed on the back surface of the first chip, and a substrate is flip-chip mounted on the first chip; wherein the back surface of the substrate is provided with a soldering point, the front surface of the substrate is provided with a connecting structure and connected with the vertical interconnection structure through the connecting structure, the substrate is provided with a hollow area, and the first heat dissipation member extends into the hollow area. The first heat dissipation structure, the first chip, the vertical interconnection structure and the substrate are encapsulated, and the soldering point on the back surface of the substrate is exposed by grinding. A second chip is soldered with the soldering point on the back surface of the substrate, and the second chip is encapsulated. The carrier board is removed, and ball placement is performed on the back surface of the redistribution layer.

[0014] By using the manufacturing method, the first chip is carried by the redistribution layer, the distribution density of the solder joints is improved, and high-density interconnection can be realized. The second chip is carried by the substrate provided with the hollow area, on one hand, the first heat dissipation member can be arranged at the position of the hollow area, and the heat dissipation performance of the stacked packaging structure is improved; on the other hand, the substrate can be manufactured in advance, and the assembly can be performed when packaging is performed, so that the packaging cycle time can be greatly shortened, the overall packaging process is optimized, and the cost is reduced.

[0015] In some possible implementation manners, the plastic packaging of the first heat dissipation structure, the first chip, the vertical interconnection structure and the substrate, and the exposure of the solder joints on the back surface of the substrate by grinding include: plastic packaging of the first heat dissipation structure, the first chip, the vertical interconnection structure and the substrate, and exposure of the solder joints on the back surface of the first heat dissipation structure and the substrate by grinding, and mounting the second heat dissipation structure on the surface of the first heat dissipation structure. By arranging the second heat dissipation structure, the heat dissipation performance can be further improved.

[0016] In some possible implementation manners, the welding of the second chip and the solder joints on the back surface of the substrate, and the plastic packaging of the second chip include: arranging the second heat dissipation member on the back surface of the substrate, welding the second chip and the solder joints on the back surface of the substrate, and plastic packaging of the second heat dissipation member and the second chip. By arranging the second heat dissipation member, the heat dissipation performance can be further improved.

[0017] The application also provides a manufacturing method of a chip stacked packaging, which can include: manufacturing a redistribution layer on a carrier plate, and flip-chip mounting a first chip on the redistribution layer. A first heat dissipation structure is fixed on the back surface of the first chip, and a substrate is flip-chip mounted on the first chip; wherein the back surface of the substrate is provided with solder joints, the front surface of the substrate is provided with a vertical interconnection structure and connected with a connecting structure on the surface of the redistribution layer through the vertical interconnection structure, the substrate is provided with a hollow area, and the first heat dissipation member extends into the hollow area. The first heat dissipation structure, the first chip, the vertical interconnection structure and the substrate are plastic packaged, and the solder joints on the back surface of the substrate are exposed by grinding. The second chip is welded with the solder joints on the back surface of the substrate, and the second chip is plastic packaged. The carrier plate is removed, and ball mounting is performed on the back surface of the redistribution layer.

[0018] By using the manufacturing method, the first chip is carried by the redistribution layer, the distribution density of the solder joints is improved, and high-density interconnection can be realized. The second chip is carried by the substrate provided with the hollow area, on one hand, the first heat dissipation member can be arranged at the position of the hollow area, and the heat dissipation performance of the stacked packaging structure is improved; on the other hand, the substrate can be manufactured in advance, and the assembly can be performed when packaging is performed, so that the packaging cycle time can be greatly shortened, the overall packaging process is optimized, and the cost is reduced.

[0019] In some possible implementation manners, the above packaging the first heat dissipation structure, the first chip, the vertical interconnection structure and the substrate, and exposing the solder joints on the back surface of the substrate by grinding, comprises: packaging the first heat dissipation structure, the first chip, the vertical interconnection structure and the substrate, exposing the solder joints on the back surface of the first heat dissipation structure and the substrate by grinding, and mounting the second heat dissipation structure on the surface of the first heat dissipation structure. The second heat dissipation structure is arranged, and the heat dissipation performance is further improved.

[0020] In some possible implementation manners, the above welding the second chip to the solder joints on the back surface of the substrate, and packaging the second chip, comprises: arranging the second heat dissipation member on the back surface of the substrate, welding the second chip to the back surface of the substrate, and packaging the second heat dissipation member and the second chip. The second heat dissipation member is arranged, and the heat dissipation performance is further improved.

[0021] The application further provides an electronic device, which comprises a circuit board and a chip stack package provided in any one of the possible implementation manners described above, and the circuit board is electrically connected to the chip stack package. BRIEF DESCRIPTION OF DRAWINGS

[0022] FIG. 1 is a schematic diagram of a chip stack structure provided in an embodiment of the application;

[0023] FIG. 2 is a schematic diagram of a substrate structure in a chip stack structure provided in an embodiment of the application;

[0024] FIG. 3 is a schematic diagram of a chip stack structure provided in an embodiment of the application;

[0025] FIG. 4 is a schematic diagram of a chip stack structure provided in an embodiment of the application;

[0026] FIG. 5 is a schematic diagram of a chip stack structure provided in an embodiment of the application;

[0027] FIG. 6 is a flowchart of a manufacturing method of a chip stack structure provided in an embodiment of the application;

[0028] FIG. 7 is a schematic diagram of a chip stack structure in a manufacturing process provided in an embodiment of the application;

[0029] FIG. 8 is a schematic diagram of a chip stack structure in a manufacturing process provided in an embodiment of the application;

[0030] FIG. 9 is a schematic diagram of a chip stack structure in a manufacturing process provided in an embodiment of the application;

[0031] FIG. 10 is a schematic diagram of a chip stack structure in a manufacturing process provided in an embodiment of the application;

[0032] FIG. 11 is a schematic diagram of a chip stack structure in a manufacturing process provided in an embodiment of the application;

[0033] Fig. 12 is a schematic diagram of a chip stack structure in a manufacturing process according to an embodiment of the present application;

[0034] Fig. 13 is a flow chart of a manufacturing method of a chip stack structure according to an embodiment of the present application;

[0035] Fig. 14 is a schematic diagram of a chip stack structure in a manufacturing process according to an embodiment of the present application;

[0036] Fig. 15 is a schematic diagram of a chip stack structure in a manufacturing process according to an embodiment of the present application;

[0037] Fig. 16 is a schematic diagram of a chip stack structure in a manufacturing process according to an embodiment of the present application;

[0038] Fig. 17 is a schematic diagram of a chip stack structure in a manufacturing process according to an embodiment of the present application;

[0039] Fig. 18 is a schematic diagram of a chip stack structure in a manufacturing process according to an embodiment of the present application;

[0040] Fig. 19 is a schematic diagram of a chip stack structure in a manufacturing process according to an embodiment of the present application. DETAILED DESCRIPTION

[0041] In order to make the objectives, technical solutions and advantages of the present application clearer, the technical solutions in the present application will be described clearly and completely below with reference to the drawings in the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall into the scope of the present application.

[0042] The terms "first", "second", etc. in the description embodiments of the present application and claims and drawings are only used for distinguishing description purposes and cannot be understood as indicating or implying relative importance, nor can be understood as indicating or implying sequence. "And / or" is used to describe the association relationship of the associated objects, which means that there can be three kinds of relationships, for example, "A and / or B" can represent: only A exists, only B exists, and A and B exist at the same time, wherein A and B can be singular or plural. The character " / " generally represents that the associated objects before and after it are in an "or" relationship. "At least one (item)" means one or more, and "multiple" means two or more. "Installation", "connection", "connection" and the like should be broadly understood, for example, it can be an electrical connection, or a mechanical connection; it can be a fixed connection, or a detachable connection, or an integral connection; it can be a direct connection, or an indirect connection through an intermediate medium, or a communication between two elements. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a series of steps or units. The method, system, product or device is not necessarily limited to those steps or units clearly listed, but can include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices. "Up", "down", "left", "right" and the like are only used for the orientation of the components in the drawings, and these directional terms are relative concepts, which are used for relative description and clarification, which can change accordingly according to the change of the orientation of the components in the drawings.

[0043] The electronic device provided by the embodiments of the present application adopts a new chip stacking structure, which can shorten the packaging cycle time while improving the heat dissipation performance and maintaining a high interconnection density.

[0044] The electronic device provided by the embodiments of the present application adopts a new chip stacking structure, which can shorten the packaging cycle time while improving the heat dissipation performance and maintaining a high interconnection density.

[0045] The consumer electronic product can be a mobile phone, a tablet computer, a notebook computer, a personal computer (PC), a personal digital assistant (PDA), a smart wearable product (for example, a smart watch, a smart bracelet, etc.), a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a drone, or the like. The home electronic product can be a smart door lock, a television, a smart speaker, a refrigerator, a sweeping robot, or the like. The vehicle-mounted electronic product can be a vehicle-mounted navigator, a vehicle-mounted display, or the like. The financial terminal product can be an automated teller machine (ATM), a self-service electronic device, or the like. The communication electronic product can be a server, a memory, a radar, a base station, or the like.

[0046] According to actual needs, other devices such as a printed circuit board (PCB) and an input / output device can be electrically connected to the chip stacking structure, and the present application does not limit this.

[0047] The present application does not limit the application field of the chip stacking structure. The chip stacking structure can be applied to the storage field.

[0048] The specific structure of the chip stacking package provided by the embodiment of the present application is described below.

[0049] The chip stacking package provided by the embodiment of the present application can include a redistribution layer (RDL), a substrate 10, a first chip D1, a second chip D2, a vertical connection structure 20, a first heat dissipation member 31, and a solder joint 40. The solder joint 40 can be a micro bump, but is not limited thereto.

[0050] Referring to FIG. 1, the first chip D1 is disposed on the front surface of the RDL and is electrically connected to the RDL. The solder joint 40 is disposed on the back surface of the RDL and is electrically connected to the RDL. The substrate 10 is disposed above the first chip D1 (i.e., away from the RDL) and has a hollow area 101 (see FIG. 2) disposed thereon, which is opposite to the first chip D1. The second chip D2 is disposed on the upper surface of the substrate 10 (i.e., away from the RDL) and is electrically connected to the substrate 10. The first heat sink 31 is disposed on the first chip D1 (i.e., away from the RDL) and extends upward into the hollow area 101 in the substrate 10. The vertical connection structure 20 is connected between the substrate 10 and the RDL, and the vertical connection structure 20 can be distributed on the side surface of the first chip D1.

[0051] The present application does not limit the type of the first chip D1, the connection mode between the first chip D1 and the RDL, etc.

[0052] In some possible implementations, the first chip D1 can be a system on chip (SOC). The first chip D1 can be soldered on the upper surface of the RDL in a flip chip (FC) manner to achieve electrical connection between the first chip D1 and the RDL, but is not limited thereto.

[0053] Similarly, the present application does not limit the type of the second chip D2, the connection mode between the second chip D2 and the substrate 10, etc.

[0054] In some possible implementations, the second chip D2 can be a double data rate (DDR) synchronous dynamic random access memory (SDRAM) chip. The second chip D2 can be fixed on the surface of the substrate 10 in a surface mount technology (SMT) manner and is electrically connected to the solder joint 102 (see FIG. 2) disposed around the hollow area 101, but is not limited thereto. The solder joint 102 can be a pad, a solder ball, etc.

[0055] It should be understood that the substrate is made of ABF (ajinomoto build-up film) material and copper (Cu) material, Cu as a line, can be made into different patterns according to the needs, so as to form a hollow area by digging a hole in the area without a line, so as to meet the setting of the first heat dissipation member in the hollow area, so as to improve the heat dissipation performance of the product. And, using the substrate can be directly interconnected by die, without photoetching and electroplating like the redistribution layer (RDL), thereby shortening the packaging time and reducing the cost.

[0056] It should also be understood that the redistribution layer is made by photoetching and electroplating, and the current photoetching and electroplating process can stably make lines within a few microns, which can make the hole and the wire smaller (or thinner), and has the advantage of high interconnection density.

[0057] Illustratively, the above-mentioned redistribution layer RDL can include a plurality of alternating dielectric layers and metal layers. Among them, the dielectric layer can be made of a dielectric material such as PI (polyimide), and the metal layer can be made of a metal material such as copper Cu.

[0058] In summary, in the stacked packaging structure provided by the embodiments of the present application, the substrate 10 provided with the hollow area 101 is used to carry the second chip D2, on the one hand, the setting of the first heat dissipation member 31 at the position of the hollow area 101 can improve the heat dissipation performance of the stacked packaging structure; on the other hand, the substrate 10 can be pre-made, and assembled during packaging, thereby greatly shortening the packaging cycle time, optimizing the overall packaging process, and further reducing the cost. In addition, the redistribution layer RDL is used to carry the first chip D1, and since the redistribution layer RDL is made by photoetching and electroplating process, photoetching and electroplating can stably make lines within a few microns, so as to realize a higher bump density and interconnection density.

[0059] On this basis, in order to further improve the heat dissipation performance of the packaging structure, as shown in FIG. 3, in some possible implementations, the stacked packaging structure can further include a second heat dissipation member 32, which is arranged on the side of the second chip D2 and connected with the substrate 10.

[0060] The present application does not limit the material, structure, etc. of the above-mentioned second heat dissipation member 32, as long as it can meet the needs of the packaging structure.

[0061] Illustratively, in some possible implementations, the second heat dissipation member 32 can be made of one or more of silicon (Si), metal, etc. Among them, the metal material can be copper (Cu), titanium (Ti), etc.

[0062] Illustratively, in some possible implementation manners, the second heat dissipation member 32 can be a ring structure arranged around the second chip D2, or can be a plurality of column structures arranged around the second chip D2.

[0063] In addition, the present application does not limit the material, structure, etc. of the first heat dissipation member 31, as long as it can meet the needs of the packaging structure.

[0064] Illustratively, in some possible implementation manners, the first heat dissipation member 31 can adopt one or more of silicon (Si), metal, etc. The metal material can be copper (Cu), titanium (Ti), etc.

[0065] Of course, the materials adopted by the first heat dissipation member 31 and the second heat dissipation member 32 can be the same or different, and the present application does not limit this, which can be set as needed in practice.

[0066] Illustratively, in some possible implementation manners, the first heat dissipation member 31 can be one heat dissipation structure, or can be a plurality of heat dissipation structures arranged in a stack.

[0067] In addition, in order to provide the heat dissipation performance of the packaging structure, as shown in FIG. 3, in some possible implementation manners, the top of the first heat dissipation member 31 can be protruded from the surface of the substrate 10.

[0068] Illustratively, as shown in FIG. 4, in some possible implementation manners, the first heat dissipation member 31 can include a first heat dissipation structure 31a and a second heat dissipation structure 31b. The first heat dissipation structure 31a is arranged in a stack on the first chip D1, and the second heat dissipation structure 31b is arranged in a stack on the first heat dissipation structure 31a. The first heat dissipation structure 31a, the first chip D1, the vertical connection structure 20, and the substrate 10 are molded in a molding layer M1 (which can also be referred to as a first molding layer), and the top of the first heat dissipation structure 31a is flush with the upper surface of the molding layer M1 (the surface on the side away from the redistribution layer). The second heat dissipation structure 31b located at the top of the first heat dissipation structure 31a can extend to the bottom of the second chip D2 and be wrapped by an under fill. The related manufacturing process can be referred to below.

[0069] Continuing to refer to FIG. 4, the second chip D2 and the second heat dissipation member 32 can be molded in a molding layer M2 (which can also be referred to as a second molding layer).

[0070] In addition, the present application does not limit the arrangement form of the vertical connection structure 20, which can be manufactured as needed in practice.

[0071] For example, referring to FIG. 4, in some possible implementation manners, the vertical connection structure 20 can be fabricated on the redistribution layer RDL, in which case, the top of the vertical connection structure 20 can be connected with a connection structure 103 (such as a land or a copper core ball, etc.) arranged on the surface of the substrate 10, so as to realize the interconnection between the redistribution layer RDL and the substrate 10.

[0072] For another example, referring to FIG. 5, in some possible implementation manners, the vertical connection structure 20 can be fabricated on the substrate 10, in which case, the bottom of the vertical connection structure 20 is connected with a connection structure P1 (such as a land or a solder ball, etc.) arranged on the surface of the redistribution layer RDL, so as to realize the interconnection between the redistribution layer RDL and the substrate 10.

[0073] The chip stack package provided by the embodiments of the present application is further described below in combination with different fabrication methods.

[0074] Fabrication method one

[0075] For example, the fabrication method of the chip stack package provided by the embodiments of the present application can include the following steps.

[0076] Step 11, referring to FIG. 7, fabricating the redistribution layer RDL on the carrier board C1, fabricating the vertical interconnection structure 20 on the redistribution layer RDL, and flip-chip mounting the first chip D1 on the redistribution layer RDL.

[0077] For example, in some possible implementation manners, the above step 11 can include: referring to FIG. 7(a), first fabricating the redistribution layer RDL on the carrier board C1 (such as glass), and fabricating a through insulator via (TIV) as the vertical interconnection structure 20 on the redistribution layer RDL. Then, referring to FIG. 7(b), the SOC (D1) can be welded on the surface of the redistribution layer RDL in a flip-chip (FC) manner.

[0078] Step 12, referring to FIG. 8, fixing the first heat dissipation structure 31a on the back surface of the first chip D1, and flip-chip mounting the substrate 10 on the redistribution layer RDL; wherein the back surface of the substrate 10 is provided with a soldering point 102, the front surface of the substrate is provided with a connection structure 103 and connected with the vertical interconnection structure 20 through the connection structure 103, the substrate 10 is provided with a hollow area 101, and the first heat dissipation structure 31a extends into the hollow area 101.

[0079] In some possible implementation manners, step 12 can include the following. As shown in FIG. 8, a substrate 10 provided with a hollow area 101 is provided, and the back surface of the substrate 10 is provided with solder joints 102, and the front surface is provided with connection structures 103. The solder joints 102 can be solder balls, and the connection structures 103 can be copper core balls. Then, a first heat dissipation structure 31a is fixed to the back surface of the first chip D1, and the substrate 10 is flip chip (FC) on a redistribution layer (RDL). In this case, the substrate 10 is connected to the vertical interconnection structure 20 (TIV) through the connection structures 103 provided on the front surface, the hollow area 101 provided on the substrate 10 corresponds to the position of the first heat dissipation structure 31a, and the first heat dissipation structure 31a extends into the hollow area 101.

[0080] The application does not limit the mounting sequence of the first heat dissipation structure 31a and the substrate 10. The first heat dissipation structure 31a can be mounted first, and then the substrate 10 is mounted. The substrate 10 can be mounted first, and then the first chip D1 is mounted.

[0081] Step 13, as shown in FIG. 9, the first heat dissipation structure 31a, the first chip D1, the vertical interconnection structure 20 and the substrate 10 are molded, and the solder joints 102 are exposed by grinding.

[0082] In some possible implementation manners, step 13 can include the following. As shown in FIG. 9, the first heat dissipation structure 31a, the first chip D1, the vertical interconnection structure 20 and the substrate 10 are molded, and the solder joints 102 are exposed by grinding, so as to encapsulate the first heat dissipation structure 31a, the first chip D1, the vertical interconnection structure 20 and the substrate 10 in a molding layer M1.

[0083] Of course, in some possible implementation manners, the top of the first heat dissipation structure 31a protrudes from the substrate 10, and the first heat dissipation structure 31a is exposed at the same time as the solder joints 102 are exposed by the grinding process. In this case, the first heat dissipation structure 31a is flush with the molding layer M1.

[0084] Based on this, in some possible implementation manners, in order to improve the heat dissipation performance, as shown in FIG. 10, step 13 can further include the following. A second heat dissipation structure 31b is attached to the top of the first heat dissipation structure 31a, and the second heat dissipation structure 31b can be distributed around the second chip D2. The arrangement of the second heat dissipation structure 31b can be referred to the foregoing, and details are not described herein.

[0085] Step 14, as shown in FIG. 11, the second chip D2 is soldered to the solder joints 102, and the second chip D2 is molded.

[0086] In some possible implementation manners, step 14 can include, as shown in FIG. 11, soldering the DDR (D2) to the soldering points 102 on the surface of the substrate 10 by using surface mount technology (SMT). Then, the DDR (D2) can be molded by using a molding process, so as to be encapsulated in the molding layer M2 of the DDR (D2).

[0087] Of course, according to actual needs, in some possible implementation manners, step 14 can also fix the heat dissipation member 32 on the surface of the substrate on the side of the second chip D2, and encapsulate the heat dissipation member 32 in the molding layer M2 of the second chip D2.

[0088] Step 15, as shown in FIG. 12, the carrier board C1 is removed, and ball mounting is performed on the back of the redistribution layer RDL.

[0089] In some possible implementation manners, step 15 can include, as shown in FIG. 12(a), debonding the carrier board C1, and then, as shown in FIG. 12(b), performing ball mounting (BM) on the back of the redistribution layer RDL, so as to form the soldering points 40 (bumps) on the back of the redistribution layer RDL.

[0090] Of course, according to actual needs, other manufacturing processes can be performed before and after the ball mounting. For example, before the ball mounting, a capacitor device can be mounted (SMT) on the back of the redistribution layer RDL; after the ball mounting, the back of the second chip D2 is exposed by grinding, and the stacked package structure monomer is formed by cutting, and the like.

[0091] Manufacturing method two

[0092] In some possible implementation manners, the manufacturing method of the chip stacked package can include, as shown in FIG. 13, the following steps.

[0093] Step 21, as shown in FIG. 14, a redistribution layer RDL is manufactured on the carrier board C1, and the first chip D1 is flip-chip mounted on the redistribution layer RDL.

[0094] In some possible implementation manners, step 21 can include, as shown in FIG. 14(a), first manufacturing the redistribution layer RDL on the carrier board C1 (such as glass). Then, as shown in FIG. 14(b), the SOC (D1) can be soldered on the surface of the redistribution layer RDL by using flip-chip (FC).

[0095] Step 22, referring to FIG. 15, the first heat dissipation structure 31a is fixed on the back of the first chip D1, and the substrate 10 is flip-chip mounted on the RDL. The back of the substrate 10 is provided with solder joints 102, and the front of the substrate 10 is provided with vertical interconnection structures 20 and connected to the connecting structure P1 on the surface of the RDL through the vertical interconnection structures 20. The substrate 10 is provided with a hollow area 101, and the first heat dissipation structure 31a extends into the hollow area 101.

[0096] Illustratively, in some possible implementation manners, the above step 22 can include: referring to FIG. 15, providing a substrate 10 provided with a hollow area 101, and the back of the substrate 10 is provided with solder joints 102, and the front of the substrate 10 is provided with vertical interconnection structures 20. The solder joints 102 can be solder balls, and the connecting structure 103 can be a copper core ball. The vertical interconnection structure 20 can be a through insulator via (TIV). Then, the first heat dissipation structure 31a is fixed on the back of the first chip D1, and the substrate 10 is flip-chip mounted (FC) on the RDL. In this case, the substrate 10 is connected to the connecting structure P1 on the surface of the RDL through the vertical interconnection structures 20. The hollow area 101 provided on the substrate 10 corresponds to the position of the first heat dissipation structure 31a, and the first heat dissipation structure 31a extends into the hollow area 101. The connecting structure P1 on the surface of the RDL can be a pad, and according to actual needs, the pad can be provided with a solder ball.

[0097] The application does not limit the installation sequence of the first heat dissipation structure 31a and the substrate 10. The first heat dissipation structure 31a can be installed first, and then the substrate 10 is installed. The substrate 10 can be installed first, and then the first chip D1 is installed.

[0098] Step 23, referring to FIG. 16, the first heat dissipation structure 31a, the first chip D1, the vertical interconnection structure 20 and the substrate 10 are molded, and the solder joints 102 are exposed by grinding.

[0099] Illustratively, in some possible implementation manners, the above step 23 can include: referring to FIG. 16, using a molding process to mold the first heat dissipation structure 31a, the first chip D1, the vertical interconnection structure 20 and the substrate 10, and using a grinding process to expose the solder joints 102, so as to encapsulate the first heat dissipation structure 31a, the first chip D1, the vertical interconnection structure 20 and the substrate 10 in a molding layer M1.

[0100] Of course, in some possible implementation manners, the top of the first heat dissipation structure 31a is protruded from the substrate 10, and the first heat dissipation structure 31a is exposed at the same time when the soldering points 102 are exposed by a grinding process. In this case, the first heat dissipation structure 31a is flush with the molding layer M1.

[0101] Based on this, in some possible implementation manners, in order to improve the heat dissipation performance, referring to FIG. 17, the step 23 can further include: attaching a second heat dissipation structure 31b on the top of the first heat dissipation structure 31a, and the second heat dissipation structure 31b can be distributed along the periphery of the second chip D2. The arrangement of the second heat dissipation structure 31b can refer to the foregoing, and will not be described here again.

[0102] Step 24, referring to FIG. 18, the second chip D2 is soldered with the soldering points 102, and the second chip D2 is molded.

[0103] Illustratively, in some possible implementation manners, the step 24 can include: referring to FIG. 18, using the surface mounting technology (SMT) to solder the DDR (D2) with the soldering points 102 on the surface of the substrate 10. Then, the molding process can be used to mold the DDR (D2) in the molding layer M2 of the molded DDR (D2).

[0104] Of course, according to actual needs, in some possible implementation manners, the heat dissipation member 32 can be fixed on the surface of the substrate on the side of the second chip D2 through the step 24, and the heat dissipation member 32 can be molded in the molding layer M2 of the second chip D2.

[0105] Step 25, referring to FIG. 19, the carrier board C1 is removed, and the ball mounting is performed on the back of the redistribution layer RDL.

[0106] Illustratively, in some possible implementation manners, the step 25 can include: referring to FIG. 19(a), the carrier board C1 is debonded; then, referring to FIG. 19(b), the ball mounting (BM) is performed on the back of the redistribution layer RDL to form the soldering points 40 (μbump) on the back of the redistribution layer RDL.

[0107] Of course, according to actual needs, other manufacturing processes can be performed before and after the ball mounting, such as: before the ball mounting, the capacitor device can be attached (SMT) on the back of the redistribution layer RDL; after the ball mounting, the back of the second chip D2 is exposed by grinding, and the stack package structure monomer is formed by cutting, and the like.

[0108] It should be understood that the size of the sequence number of each process does not mean the order of execution, and the execution order of each process should be determined according to its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0109] For other related contents in the above manufacturing method, the corresponding parts in the foregoing structural embodiment can be referred to, and details are not repeated here. For other setting structures in the foregoing structural embodiment, the foregoing manufacturing method and related manufacturing methods can be adjusted, and details are not repeated here.

[0110] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited to this. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A chip stack package, characterized by, The chip stack package comprises: a redistribution layer; a first chip disposed on a surface of the redistribution layer and electrically connected to the redistribution layer; a substrate disposed on a side of the first chip away from the redistribution layer, and the substrate is provided with a hollow area; a second chip disposed on a side of the substrate away from the first chip and electrically connected to the substrate; a vertical connection structure connected between the substrate and the redistribution layer; a first heat dissipation member disposed on a surface of the first chip close to the substrate and extending into the hollow area; a soldering point disposed on a side of the redistribution layer away from the first chip and electrically connected to the redistribution layer.

2. The chip stack package according to claim 1, wherein on a side away from the first chip, a surface of the first heat dissipation member protrudes from a surface of the substrate.

3. The chip stack package according to claim 1 or 2, wherein the first heat dissipation member comprises a first heat dissipation structure and a second heat dissipation structure, the first heat dissipation structure and the second heat dissipation structure are stacked on the first chip, and the second heat dissipation structure is located on a side of the first heat dissipation structure away from the first chip; the first heat dissipation structure, the vertical connection structure, the first chip and the substrate are molded in a first molding layer, and on a side away from the first chip, a surface of the first heat dissipation structure is flush with a surface of the first molding layer.

4. The chip stack package according to any one of claims 1-3, wherein the chip stack package further comprises a second heat dissipation member; the second heat dissipation member is disposed on a side of the substrate away from the first chip and connected to the substrate.

5. The chip stack package according to claim 4, wherein the second heat dissipation member is distributed around the second chip.

6. The chip stack package according to any one of claims 1-5, wherein the first chip comprises a system on chip (SOC).

7. The chip stack package according to any one of claims 1-6, wherein the second chip comprises a double data rate (DDR) synchronous dynamic random access memory (SDRAM).

8. A method of fabricating a chip stack package, comprising: The method for manufacturing the chip stack package comprises: manufacturing a redistribution layer on a carrier board, manufacturing a vertical interconnection structure on the redistribution layer, and flip-chip mounting a first chip on the redistribution layer; fixing a first heat dissipation structure on a back surface of the first chip, and flip-chip mounting a substrate on the first chip; wherein a back surface of the substrate is provided with a soldering point, a front surface of the substrate is provided with a connection structure and connected to the vertical interconnection structure through the connection structure, the substrate is provided with a hollow area, and the first heat dissipation structure extends into the hollow area; molding the first heat dissipation structure, the first chip, the vertical interconnection structure and the substrate, and exposing the soldering point by grinding; soldering a second chip to the soldering point, and molding the second chip; removing the carrier board, and ball mounting on a back surface of the redistribution layer.

9. The method for manufacturing the chip stack package according to claim 8, wherein The first heat dissipation structure, the first chip, the vertical interconnection structure and the substrate are encapsulated, and the soldering points are exposed by grinding. The first heat dissipation structure, the first chip, the vertical interconnection structure and the substrate are encapsulated, and the soldering points and the first heat dissipation structure are exposed by grinding, and a second heat dissipation structure is attached to the surface of the first heat dissipation structure. 10.The method according to claim 8 or 9, wherein The second chip is soldered to the soldering points, and the second chip is encapsulated. A second heat dissipation structure is attached to the back surface of the substrate, the second chip is soldered to the soldering points, and the second heat dissipation structure and the second chip are encapsulated.

11. A method of fabricating a chip stack package, comprising: It comprises: A redistribution layer is formed on a carrier board, and a first chip is flip-chip mounted on the redistribution layer; A first heat dissipation structure is fixed to the back surface of the first chip, and the substrate is flip-chip mounted on the first chip; wherein the back surface of the substrate is provided with soldering points, the front surface of the substrate is provided with a vertical interconnection structure and connected to a connecting structure on the surface of the redistribution layer through the vertical interconnection structure, the substrate is provided with a hollow area, and the first heat dissipation structure extends into the hollow area; The first heat dissipation structure, the first chip, the vertical interconnection structure and the substrate are encapsulated, and the soldering points are exposed by grinding. The second chip is soldered to the soldering points, and the second chip is encapsulated. The carrier board is removed, and balls are planted on the back surface of the redistribution layer. 12.The method according to claim 11, wherein The first heat dissipation structure, the first chip, the vertical interconnection structure and the substrate are encapsulated, and the soldering points are exposed by grinding. The first heat dissipation structure, the first chip, the vertical interconnection structure and the substrate are encapsulated, and the soldering points and the first heat dissipation structure are exposed by grinding, and a second heat dissipation structure is attached to the surface of the first heat dissipation structure. 13.The method according to claim 11 or 12, wherein The second chip is soldered to the soldering points, and the second chip is encapsulated. A second heat dissipation structure is attached to the back surface of the substrate, the second chip is soldered to the soldering points, and the second heat dissipation structure and the second chip are encapsulated.

14. An electronic device, comprising: It comprises a circuit board and a chip stack package as claimed in any one of claims 1-7, and the circuit board is electrically connected to the chip stack package.

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