Shift register unit and driving method, gate driving circuit, and display panel

Abstract

The present application discloses a shift register unit and a driving method, a gate driving circuit, and a display panel. The shift register unit comprises: an input module, at least connected to a first node and a second node; a first control module, connected between a first power supply end and the first node, wherein a control end of the first control module is connected to the second node; a second control module, connected between the first node and the second node, wherein a control end of the second control module receives a first clock signal provided by a first clock end; and an output module, connected between a second power supply end and a shift output end, wherein a control end of the output module is connected to the second node.

Description

Shift register unit and driving method, gate driving circuit and display panel

[0001] This application claims priority to the Chinese patent application No. 202411118445.X, filed on August 14, 2024, to the Chinese Patent Office, the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the technical field of display, for example, to a shift register unit and driving method, a gate driving circuit and a display panel. BACKGROUND

[0003] In a display panel, the driving circuit arranged in the non-display area is an indispensable circuit structure for realizing the display, touch control and other functions of the display panel.

[0004] The driving circuit is usually composed of multiple stages of shift registers, and the driving chip provides driving signals to each stage of shift registers in the driving circuit through a signal line to make the driving circuit operate normally.

[0005] However, the output of the shift register in the related art is unstable, which affects the display effect. SUMMARY

[0006] The present application provides a shift register unit and driving method, a gate driving circuit and a display panel to solve the problem of unstable output of the shift register in the related art.

[0007] According to an aspect of the present application, a shift register unit is provided, comprising:

[0008] An input module connected to at least the first node and the second node, configured to control the potential of the first node and the potential of the second node;

[0009] A first control module connected between the first power supply end and the first node, the control end of the first control module connected to the second node, configured to control the on-off between the first power supply end and the first node in response to the potential of the second node;

[0010] A second control module connected between the first node and the second node, the control end of the second control module receiving a first clock signal provided by the first clock end, configured to control the on-off between the first node and the second node in response to the first clock signal of the first clock end;

[0011] An output module connected between the second power supply end and the shift output end, the control end of the output module connected to the second node, configured to control the on-off between the second power supply end and the shift output end in response to the potential of the second node.

[0012] According to another aspect of the present application, there is provided a driving method of a shift register unit, the shift register unit being as described above.

[0013] The driving method of the shift register unit comprises:

[0014] In a non-output phase, the input module controls the potential of the second node, and the first control module and the output module are simultaneously switched to an off state.

[0015] In an output phase, the input module controls the on-off state of the second control module and the potential of the second node, and the first control module and the output module are simultaneously switched to an on state, and the signal of the first power supply end is written to the first node.

[0016] According to another aspect of the present application, there is provided a gate drive circuit comprising the shift register unit as described above.

[0017] According to another aspect of the present application, there is provided a display panel comprising the gate drive circuit as described above. BRIEF DESCRIPTION OF DRAWINGS

[0018] FIG. 1 is a schematic diagram of a conventional shift register unit;

[0019] FIG. 2 is a timing diagram of the shift register unit shown in FIG. 1;

[0020] FIG. 3 is a schematic diagram of a shift register unit provided by an embodiment of the present application;

[0021] FIG. 4 is a schematic diagram of another shift register unit provided by an embodiment of the present application;

[0022] FIG. 5 is a schematic diagram of yet another shift register unit provided by an embodiment of the present application;

[0023] FIG. 6 is a schematic diagram of yet another shift register unit provided by an embodiment of the present application;

[0024] FIG. 7 is a schematic diagram of yet another shift register unit provided by an embodiment of the present application;

[0025] FIG. 8 is a schematic diagram of yet another shift register unit provided by an embodiment of the present application;

[0026] FIG. 9 is a timing diagram of the shift register unit shown in FIG. 8;

[0027] FIG. 10 is a schematic diagram of yet another shift register unit provided by an embodiment of the present application;

[0028] Fig. 11 is a timing diagram of the shift register unit shown in Fig. 10;

[0029] Fig. 12 is a timing diagram of a driving method of a shift register unit according to an embodiment of the present application;

[0030] Fig. 13 is another timing diagram of the shift register unit shown in Fig. 8;

[0031] Fig. 14 is a schematic diagram of a gate driving circuit according to an embodiment of the present application;

[0032] Fig. 15 is a schematic diagram of a display panel according to an embodiment of the present application. DETAILED DESCRIPTION

[0033] In order to make the persons skilled in the art better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application.

[0034] It should be noted that the terms "first", "second", and the like in the specification and claims of the present application and the above-described drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or a chronological sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product, or device that includes a series of steps or units does not necessarily have to be limited to only those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to the process, method, product, or device.

[0035] Fig. 1 is a schematic diagram of a conventional shift register unit, as shown in Fig. 1, the shift register unit includes a node control module 10, a transistor Ma, a transistor Mb, a transistor Mc, a capacitor C1, and a capacitor C2.

[0036] The node control module 10 is connected to a first clock signal end CK, a second clock signal end XCK, an input signal end IN, a high-level signal end VGH, a low-level signal end VGL, a node N1, a node N2, and a node N3.

[0037] The gate of the transistor Ma is connected to the second clock signal end XCK, and the transistor Ma is connected between the node N1 and the node N2.

[0038] The gate of the transistor Mb is connected to the node N2, and the transistor Mb is connected between the high-level signal end VGH and an output end OUT. The capacitor C1 is connected between the high-level signal end VGH and the node N2.

[0039] The gate of the transistor Mc is connected to a node N3, and the transistor Mc is connected between a low-level signal terminal VGL and an output terminal OUT. A capacitor C2 is connected between the output terminal OUT and the node N3.

[0040] The optional transistors are all P-type transistors.

[0041] The conventional shift register unit has the problem of poor output stability.

[0042] Fig. 2 is a timing diagram of the shift register unit shown in Fig. 1. As shown in Figs. 1 and 2, for example, after the node N2 jumps from a high level to a low level, the low level as an on level can control the transistor Mb to be turned on, and the output terminal OUT outputs a high-level signal VGH. During the process that the node N2 outputs a low level, the node N1 will jump between a high level and a low level. To ensure that the node N2 maintains a low level, the transistor Ma is in an off state when the node N1 outputs a high level. The second clock signal terminal XCK provides an alternating high level and low level electrical signal. During the process that the node N1 outputs a high level, the second clock signal terminal XCK outputs a high level to make the transistor Ma off. Optionally, during the process that the node N1 outputs a low level, the second clock signal terminal XCK outputs a low level to make the transistor Ma on.

[0043] However, in practice, the transistor Ma in the off state will have a leakage current. Therefore, when the node N1 jumps from a low level to a high level, the potential of the node N2 will be coupled to be pulled up due to the leakage current of the transistor Ma. Therefore, during the process that the node N1 outputs a high level, the potential of the node N2 will be gradually coupled to be pulled up. Then, during the process that the transistor Mb is turned on, the potential rise of the node N2 will cause the output signal of the output terminal OUT to have a large jitter, resulting in poor output stability of the shift register unit.

[0044] For example, the low level at which the node N1 jumps is -7V, the high level at which the node N1 jumps is +15V, and the low level at which the node N2 jumps is -7V. During T11 to T12, the second clock signal terminal XCK outputs a high level to make the transistor Ma off; the node N1 jumps from -7V to +15V; due to the leakage current of the transistor Ma, the low level of the potential of the node N2 will be coupled to be slowly pulled up, and the potential of the node N2 can be slowly pulled up from -7V to -1.1V. Therefore, it can be known that, by T12, the voltage amplitude at which the node N2 is coupled to be pulled up is 5.9V, and the output voltage jitter of the output terminal OUT of the transistor Mb can reach 10mV. The shift register unit has poor output stability.

[0045] To solve the above problems, the embodiment of the present application provides a shift register unit, and Fig. 3 is a schematic diagram of the shift register unit provided by the embodiment of the present application. As shown in Fig. 3, the shift register unit comprises: an input module 101 connected to at least a first node N1 and a second node N2, configured to control the potential of the first node N1 and the potential of the second node N2; a first control module 102 connected between a first power supply end VG1 and the first node N1, a control end of the first control module 102 connected to the second node N2, configured to control the on-off between the first power supply end VG1 and the first node N1 in response to the potential of the second node N2; a second control module 103 connected between the first node N1 and the second node N2, a control end of the second control module 103 receiving a first clock signal provided by a first clock end CK1, configured to control the on-off between the first node N1 and the second node N2 in response to the first clock signal of the first clock end CK1; and an output module 104 connected between a second power supply end VG2 and a shift output end GOUT, a control end of the output module 104 connected to the second node N2, configured to control the on-off between the second power supply end VG2 and the shift output end GOUT in response to the potential of the second node N2.

[0046] In the embodiment, the shift register unit is connected to at least a first power supply end VG1, a second power supply end VG2, a third power supply end VG3, a first clock end CK1, a second clock end CK2, a first signal end STV and a shift output end GOUT. The first power supply end VG1 provides a first power supply signal, the second power supply end VG2 provides a second power supply signal, and the third power supply end VG3 provides a third power supply signal, wherein the first power supply signal, the second power supply signal and the third power supply signal are fixed voltage signals, the first clock end CK1 provides a first clock signal with high and low levels alternately jumping, the second clock end CK2 provides a second clock signal with high and low levels alternately jumping, and the first signal end STV provides a first trigger signal, which is an electrical signal with high and low levels alternately jumping. The shift register unit works in response to the electrical signals provided by the signal ends and outputs an electrical signal through the shift output end GOUT.

[0047] The shift register unit comprises the input module 101. The input module 101 is connected to at least the first node N1 and the second node N2, and is further connected to the second power supply end VG2, the third power supply end VG3, the first clock end CK1, the second clock end CK2 and the first signal end STV. The input module 101 controls the potential of the first node N1 and the potential of the second node N2 in response to the electrical signals provided by the signal ends, so that the potential of the first node N1 jumps between high and low levels and the potential of the second node N2 jumps between high and low levels.

[0048] The shift register unit comprises a first control module 102. The first control module 102 is connected between a first power supply end VG1 and a first node N1, and a control end of the first control module 102 is connected to a second node N2. A potential of the second node N2 controls on-off states of the first control module 102. If the potential of the second node N2 controls the first control module 102 to be on, a transmission path between the first power supply end VG1 and the first node N1 is turned on, and a first power supply signal is written into the first node N1. If the potential of the second node N2 controls the first control module 102 to be off, the transmission path between the first power supply end VG1 and the first node N1 is turned off.

[0049] The shift register unit comprises a second control module 103. The second control module 103 is connected between the first node N1 and the second node N2, and a control end of the second control module 103 receives a first clock signal provided by a first clock end CK1. The first clock signal provided by the first clock end CK1 controls on-off states of the second control module 103. If the first clock signal controls the second control module 103 to be on, a transmission path between the first node N1 and the second node N2 is turned on. If the first clock signal controls the second control module 103 to be off, the transmission path between the first node N1 and the second node N2 is turned off.

[0050] The shift register unit comprises an output module 104. The output module 104 is connected between a second power supply end VG2 and a shift output end GOUT, and a control end of the output module 104 is connected to the second node N2. A potential of the second node N2 controls on-off states of the output module 104. If the potential of the second node N2 controls the output module 104 to be on, a transmission path between the second power supply end VG2 and the shift output end GOUT is turned on, and a second power supply signal is written into the shift output end GOUT. If the potential of the second node N2 controls the output module 104 to be off, the transmission path between the second power supply end VG2 and the shift output end GOUT is turned off.

[0051] As described above, the second node N2 is connected to the control end of the output module 104, and the second node N2 is also connected to the control end of the first control module 102. The potential of the second node N2 controls the output module 104 and the first control module 102 to be on at the same time, or controls the output module 104 and the first control module 102 to be off at the same time.

[0052] The working process of the shift register unit at least comprises an output stage. In the output stage, the input module 101 controls potentials of the first node N1 and the second node N2, so that the potential of the second node N2 drives the first control module 102 and the output module 104 to be on at the same time, and the first clock signal provided by the first clock end CK1 drives the second control module 103 to be off.

[0053] The first power supply signal provided by the first power supply end VG1 is designed to be at the same low level or high level as the turn-on level of the output module 104.

[0054] In this embodiment, the turn-on level of the output module 104 is taken as an example for illustration. In the output stage, the input module 101 controls the potential of the second node N2 to be at a low level. The first power supply signal provided by the first power supply end VG1 is designed to be at a low level.

[0055] In the output stage, the potential of the second node N2 is at a low level, and the output module 104 and the first control module 102 are controlled to be turned on at the same time. The transmission path between the first power supply end VG1 and the first node N1 is turned on, and the transmission path between the second power supply end VG2 and the shift output end GOUT is turned on. The first power supply signal is written into the first node N1, and the second power supply signal is written into the shift output end GOUT. The input module 101 and the first power supply end VG1 jointly affect the potential of the first node N1.

[0056] In the output stage, the input module 101 controls the potential of the first node N1 to jump between a high level and a low level.

[0057] If the input module 101 controls the potential of the first node N1 to jump from a first high level to a first low level, the first power supply signal written into the first node N1 will maintain the potential of the first node N1 at a low level. The second control module 103 in the off state will have a leakage current, which will cause the potential of the second node N2 to be coupled to a low level, but the potential of the second node N2 is still at a low level, which can ensure that the output module 104 stably outputs the second power supply signal.

[0058] If the input module 101 controls the potential of the first node N1 to jump from the first low level to the first high level, in the process of the potential of the first node N1 jumping to the first high level, the first power supply signal writing into the first node N1 will pull down the potential of the first node N1, and therefore the potential of the first node N1 finally reaches a level lower than the first high level, assuming that the potential of the first node N1 finally reaches a second high level lower than the first high level. Leakage of the second control module 103 in the off state will cause the potential of the second node N2 to be coupled to be pulled up, and the greater the jump range of the potential of the first node N1, the greater the range of the potential of the second node N2 being coupled to be pulled up. Based on this, compared with the potential of the first node N1 jumping from the first low level to the first high level, in the embodiment, by adding the first control module 102, the potential of the first node N1 can only finally jump to the second high level lower than the first high level, and therefore by reducing the jump range of the potential of the first node N1 to reduce the coupled charge amount of the first node N1 to the second node N2, the fluctuation range of the potential of the second node N2 being coupled to be pulled up is further reduced, and thus the degree of jitter of the second power supply signal output by the shift output end GOUT when the output module 104 is turned on can be reduced, and the output stability of the shift register unit is improved. The second high level is greater than or equal to the first low level.

[0059] It can be understood that by reasonably designing the first power supply signal, the voltage difference between the second high level and the first low level can be reduced, which can effectively reduce the voltage range of the potential of the second node N2 being coupled to be pulled up, and improve the output stability of the shift register unit.

[0060] In the present application, a first control module is added to the shift register unit, the first control module is connected between the first power supply end and the first node, the second node is connected to the control end of the first control module and the control end of the output module, the second control module is connected between the first node and the second node, the control end of the second control module receives the first clock signal, and the input module controls the potentials of the first node and the second node. In the present application, when the potential of the second node is at the on level, the first control module and the output module are turned on at the same time, and then the first power supply signal of the first power supply end is written into the first node, the first power supply end and the input module jointly act to adjust the potential of the first node, so as to reduce the coupled charge amount of the first node to the second node, and further reduce the fluctuation range of the potential of the second node being coupled, and thus the degree of jitter of the second power supply signal output by the shift output end when the output module is turned on can be reduced, the output stability of the shift register unit is improved, and the display effect is improved.

[0061] Figure 4 is a schematic diagram of another shift register unit according to an embodiment of the present application. As shown in Figure 4, the optional output module 104 includes a first transistor M1 and a first capacitor C1. The gate of the first transistor M1 is connected to the second node N2, and the first transistor M1 is connected between the second power supply terminal VG2 and the shift output terminal GOUT. The first capacitor C1 is connected between the second power supply terminal VG2 and the second node N2. The second control module 103 includes a second transistor M2. The gate of the second transistor M2 is connected to the first clock terminal CK1, and the second transistor M2 is connected between the first node N1 and the second node N2. The optional first control module 102 includes a third transistor M3. The gate of the third transistor M3 is connected to the second node N2, and the third transistor M3 is connected between the first power supply terminal VG1 and the first node N1. The third transistor M3 is a PMOS, and the first power supply terminal VG1 provides a low voltage vgl. The first transistor M1 and the third transistor M3 are both PMOS. The second transistor M2 is a PMOS, but is not limited thereto.

[0062] In this embodiment, the first transistor M1 and the third transistor M3 are both PMOS, so that the low level of the second node N2 is the on level, and the high level of the second node N2 is the off level. When the potential of the second node N2 is at the low level, the first transistor M1 in the output module 104 is turned on, and the third transistor M3 in the first control module 102 is also turned on. When the potential of the second node N2 is at the high level, the first transistor M1 in the output module 104 is turned off, and the third transistor M3 in the first control module 102 is also turned off.

[0063] In the output phase, the potential of the second node N2 is maintained at the low level, and the input module 101 controls the potential of the first node N1 to jump between the high level and the low level.

[0064] The first node N1 jumps from the first high level to the first low level, and the low voltage vgl of the first power supply terminal VG1 is written into the first node N1. Although the second transistor M2 is turned off and has a leakage current, the potential of the second node N2 is coupled to be pulled low, so that the potential of the second node N2 is still at the low level, the output module 104 remains on, and the shift output terminal GOUT stably outputs the second power supply signal.

[0065] In the process that the first node N1 jumps from the first low level to the first high level, the low voltage vgl of the first power supply end VG1 is written into the first node N1 to pull down the potential of the first node N1, so that the second high level that the potential of the first node N1 finally jumps to is necessarily less than the first high level. The off leakage of the second transistor M2 causes the potential of the second node N2 to be pulled up. Compared with the potential of the first node N1 jumping from the first low level to the first high level, the final jump of the first node N1 to the second high level less than the first high level reduces the voltage increment of the first node N1, and further reduces the fluctuation range of the potential of the second node N2 being pulled up, thereby improving the output stability of the shift register unit.

[0066] Referring to FIG. 4, the optional input module 101 is configured to control the potential of the first node N1 to switch between the first low level and the first high level; the third transistor M3 is a PMOS, the first power supply signal provided by the first power supply end VG1 is a low voltage vgl, the low voltage vgl of the first power supply end VG1 is less than 0V, or the low voltage vgl of the first power supply end VG1 is less than or equal to the average of the first low level and the first high level.

[0067] In this embodiment, the low voltage vgl of the first power supply end VG1 is less than 0V, or the low voltage vgl of the first power supply end VG1 is less than the first high level. Then in the process that the first node N1 jumps from the first low level to the first high level, the low voltage vgl of the first power supply end VG1 can pull down the potential of the first node N1, so that the potential of the first node N1 finally cannot jump to the first high level, but can only jump to the second high level lower than the first high level, which is beneficial to reduce the fluctuation range of the potential of the second node N2 being pulled up.

[0068] The width-length ratio of the optional first transistor M1 is greater than the width-length ratio of the third transistor M3. The width-length ratio of the optional third transistor M3 is greater than the width-length ratio of the second transistor M2.

[0069] For a transistor, the greater the channel width-length ratio of the transistor, the smaller the on-resistance of the transistor, and the greater the current gain through the transistor, and accordingly, the charging performance of the transistor can be improved. Based on the functions of different transistors in the shift register unit and the connection mode thereof, the width-length ratio of each transistor can be reasonably designed. The first transistor M1 is a transistor of the output module 104, and the width-length ratio of the first transistor M1 is large, which is beneficial to improve the current output performance of the output module 104 and reduce the output loss. The third transistor M3 is a transistor of the first control module 102, and the channel width-length ratio of the third transistor M3 is reasonably designed, which is beneficial to write the electrical signal of the first power supply end VG1 into the first node N1, and further adjust the potential of the first node N1, thereby improving the output stability of the shift register unit.

[0070] Referring to FIG. 4, the optional input module 101 is further connected to the third node N3 and configured to control the potential of the third node N3; the shift register unit further comprises an output control module 105 connected between the third power supply end VG3 and the shift output end GOUT, and the control end of the output control module 105 is connected to the third node N3; the output control module 105 is configured to control the on-off between the third power supply end VG3 and the shift output end GOUT in response to the potential of the third node N3.

[0071] The optional output control module 105 comprises a fourth transistor M4 and a second capacitor C2; the gate of the fourth transistor M4 is connected to the third node N3, and the fourth transistor M4 is connected between the third power supply end VG3 and the shift output end GOUT; the second capacitor C2 is connected between the third node N3 and the shift output end GOUT. In this embodiment, the optional fourth transistor M4 is a P-type transistor PMOS, but is not limited thereto.

[0072] The capacitance of the optional first capacitor C1 is greater than that of the second capacitor C2. In this embodiment, the first capacitor C1 mainly plays a coupling role and can block the second power supply end VG2 and the second node N2. The second capacitor C2 mainly plays a coupling role and can block the shift output end GOUT and the third node N3. Of course, the second capacitor C2 also has a bootstrap function, and the second capacitor C2 can adjust the potential of the third node N3 according to the signal change of the shift output end GOUT. The greater the capacitance, the more the stored charge, and therefore the more stable the provided current. In this design, the capacitance of the second capacitor C2 is less than that of the first capacitor C1, which can improve the output current stability of the output module 104.

[0073] It can be understood that the overlapping area of the two metal layers forming the capacitor determines the capacitance of the capacitor. The two metal layers forming the first capacitor C1 are the first metal layer and the second metal layer arranged in a stacked insulation manner, and the overlapping area of the first metal layer and the second metal layer determines the capacitance of the first capacitor C1. The two metal layers forming the second capacitor C2 are the third metal layer and the fourth metal layer arranged in a stacked insulation manner, and the overlapping area of the third metal layer and the fourth metal layer determines the capacitance of the second capacitor C2. Therefore, the overlapping area of the first metal layer and the second metal layer is greater than that of the third metal layer and the fourth metal layer.

[0074] The first metal layer, the second metal layer, the third metal layer and the fourth metal layer can be four different metal layers arranged in a stacked insulation manner. Alternatively, the first metal layer can be in the same layer as the third metal layer or the fourth metal layer, and the second metal layer is not in the same layer as the third metal layer and not in the same layer as the fourth metal layer. Alternatively, the first metal layer can be in the same layer as one of the third metal layer and the fourth metal layer, and the second metal layer can be in the same layer as the other of the third metal layer and the fourth metal layer.

[0075] Referring to FIG. 4, the second power supply signal provided by the optional second power supply terminal VG2 is a high voltage, and the third power supply signal provided by the third power supply terminal VG3 is a low voltage. The output module 104 and the output control module 105 are turned on at different times. The potential of the second node N2 is low, and the first transistor M1 of the output module 104 is turned on. The potential of the third node N3 is high, and the fourth transistor M4 of the output control module 105 is turned off. Alternatively, the potential of the second node N2 is high, and the first transistor M1 of the output module 104 is turned off. The potential of the third node N3 is low, and the fourth transistor M4 of the output control module 105 is turned on.

[0076] FIG. 5 is a schematic diagram of another shift register unit provided by an embodiment of the present application. The shift register unit shown in FIG. 5 has the same structure as that shown in FIG. 4, wherein the first transistor M1 and the third transistor M3 are both PMOS, and the first power supply signal provided by the first power supply terminal VG1 is a low voltage vgl. The second power supply signal provided by the second power supply terminal VG2 is a high voltage, and the third power supply signal provided by the third power supply terminal VG3 is a low voltage. Based on this, as shown in FIG. 5, the optional first transistor M1 is PMOS, and the third power supply terminal VG3 is multiplexed as the first power supply terminal VG1. The low voltage vgl provided by the third power supply terminal VG3 can be transmitted to the fourth transistor M4 and the third transistor M3 at the same time. Therefore, the shift register unit shown in FIG. 5 can reduce a signal line connected to the first power supply terminal VG1.

[0077] FIG. 6 is a schematic diagram of another shift register unit provided by an embodiment of the present application. The difference between FIG. 6 and FIG. 4 is that the type of at least one transistor is different, and the potential of the corresponding part of the signal terminal is changed. In FIG. 6, the optional third transistor M3 is NMOS, and the first power supply signal provided by the first power supply terminal VG1 is a high voltage vgh. The optional first transistor M1 and the third transistor M3 are both NMOS.

[0078] The optional second transistor M2 and the fourth transistor M4 are both N-type transistors NMOS, but are not limited thereto.

[0079] In this embodiment, the first transistor M1 and the third transistor M3 are both NMOS. Therefore, the high level of the second node N2 is the on level, and the low level of the second node N2 is the off level. When the potential of the second node N2 is high, the first transistor M1 in the output module 104 is turned on, and the third transistor M3 in the first control module 102 is also turned on.

[0080] In the output phase, the potential of the second node N2 is maintained at a high level, and the input module 101 controls the potential of the first node N1 to jump between high and low levels.

[0081] The first node N1 jumps from the first low level to the first high level, and the high voltage vgh of the first power supply end VG1 is written into the first node N1. Although the second transistor M2 is off, the potential of the second node N2 is coupled to be pulled high, and thus the potential of the second node N2 is still at the high level, the output module 104 remains on, and the shift output end GOUT stably outputs the second power supply signal.

[0082] In the process that the first node N1 jumps from the first high level to the first low level, the high voltage vgh of the first power supply end VG1 is written into the first node N1 to pull up the potential of the first node N1, so that the potential of the first node N1 finally jumps to the second low level which is necessarily greater than the first low level. The leakage of the off second transistor M2 causes the potential of the second node N2 to be coupled to be pulled down. Compared with the potential of the first node N1 jumping from the first high level to the first low level, the final jump of the first node N1 to the second low level which is greater than the first low level reduces the voltage drop of the first node N1, and further reduces the fluctuation amplitude of the potential of the second node N2 being coupled to be pulled down, thereby improving the output stability of the shift register unit.

[0083] Referring to FIG. 6, the optional input module 101 is configured to control the potential of the first node N1 to switch between the first low level and the first high level; the third transistor M3 is an NMOS, the first power supply signal provided by the first power supply end VG1 is a high voltage vgh, the high voltage vgh of the first power supply end VG1 is greater than 1V, or the high voltage vgh of the first power supply end VG1 is greater than or equal to the average of the first low level and the first high level.

[0084] In this embodiment, the high voltage vgh of the first power supply end VG1 is greater than 1V, or the high voltage vgh of the first power supply end VG1 is greater than the first low level. Then in the process that the first node N1 jumps from the first high level to the first low level, the high voltage vgh of the first power supply end VG1 can pull up the potential of the first node N1, so that the potential of the first node N1 finally cannot jump to the first low level, but can only jump to the second low level which is greater than the first low level, which is beneficial to reduce the fluctuation amplitude of the potential of the second node N2 being coupled to be pulled down.

[0085] Referring to FIG. 6, the second power supply signal provided by the optional second power supply end VG2 is a high voltage, and the third power supply signal provided by the third power supply end VG3 is a low voltage.

[0086] FIG. 7 is a schematic diagram of another shift register unit according to an embodiment of the present application. The shift register unit shown in FIG. 7 has the same structure as that shown in FIG. 6, where the first transistor M1 and the third transistor M3 are both NMOS, the first power supply end VG1 provides a high voltage vgh, and the second power supply end VG2 provides a high voltage vgh and the third power supply end VG3 provides a low voltage. Based on this, as shown in FIG. 7, the first transistor M1 can be an NMOS, and the second power supply end VG2 is multiplexed as the first power supply end VG1. The high voltage vgh provided by the second power supply end VG2 can be transmitted to the first transistor M1 and the third transistor M3 at the same time, so that the shift register unit shown in FIG. 7 can reduce one signal line connected to the first power supply end VG1.

[0087] It can be understood that the input module 101 of the shift register unit further includes a plurality of transistors. For example, in FIG. 4, the plurality of transistors of the input module 101 can all be PMOS, or in FIG. 6, the plurality of transistors of the input module 101 can all be NMOS.

[0088] However, the shift register unit can also have other structures. In other embodiments, the structure of the shift register unit includes a plurality of transistors, some of which can be NMOS and the remaining ones of which can be PMOS, where the first transistor and the third transistor are both PMOS or both NMOS, and based on this, the signals provided by the respective signal ends are adaptively adjusted to ensure the normal operation of the shift register unit.

[0089] The first transistor includes a first gate metal layer, a first source metal layer, and a first drain metal layer, and the third transistor includes a third gate metal layer, a third source metal layer, and a third drain metal layer. The first gate metal layer and the third gate metal layer do not overlap in a first direction, and the first direction is perpendicular to the layer on which the metal layers are located. In the direction perpendicular to the metal layers, the first gate metal layer of the first transistor and the third gate metal layer of the third transistor do not overlap, which can reduce the parasitic capacitance between the first transistor and the third transistor, improve the potential stability of the second node N2, and thus improve the working stability of the shift register unit.

[0090] FIG. 8 is a schematic diagram of another shift register unit according to an embodiment of the present application. As shown in FIG. 8, the input module 101 is further connected to a fourth node N4, which is configured to control the potential of the fourth node N4. The input module 101 includes a third capacitor C3 connected between the fourth node N4 and the first node N1. The capacitance of the first capacitor C1 is greater than that of the third capacitor C3.

[0091] Referring to FIG. 8, the optional input module 101 is further connected to the third node N3 and the fourth node N4, and is configured to control the potential of the third node N3 and the potential of the fourth node N4; the input module 101 comprises a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11 and a twelfth transistor M12; the gate of the fifth transistor M5 is connected to the second clock end CK2, and the fifth transistor M5 is connected between the third power supply end VG3 and the input end N4a of the sixth transistor M6; the gate of the sixth transistor M6 is connected to the third power supply end VG3, and the sixth transistor M6 is connected between the output end N4a of the fifth transistor M5 and the fourth node N4; the gate of the seventh transistor M7 is connected to the fourth node N4, and the seventh transistor M7 is connected between the first clock end CK1 and the first node N1; the gate of the eighth transistor M8 is connected to the second clock end CK2, and the eighth transistor M8 is connected between the first signal end STV and the fifth node N5; the gate of the ninth transistor M9 is connected to the third power supply end VG3, and the ninth transistor M9 is connected between the fifth node N5 and the third node N3; the gate of the tenth transistor M10 is connected to the fifth node N5, and the tenth transistor M10 is connected between the first clock end CK1 and the input end N4a of the sixth transistor M6; the gate of the eleventh transistor M11 is connected to the reset signal end RST, and the eleventh transistor M11 is connected between the second power supply end VG2 and the fifth node N5; the gate of the twelfth transistor M12 is connected to the fifth node N5, and the twelfth transistor M12 is connected between the second power supply end VG2 and the second node N2.

[0092] The optional eighth transistor M8 comprises a first sub-transistor M8a and a second sub-transistor M8b; the ninth transistor M9 comprises a third sub-transistor M9a and a fourth sub-transistor M9b; the gate of the first sub-transistor M8a and the gate of the second sub-transistor M8b are both connected to the second clock end CK2, the first sub-transistor M8a is connected between the first signal end STV and the input end N5 of the third sub-transistor M9a, and the second sub-transistor M8b is connected between the first signal end STV and the input end N5 of the fourth sub-transistor M9b; the gate of the third sub-transistor M9a and the gate of the fourth sub-transistor M9b are both connected to the third power supply end VG3, the output end of the third sub-transistor M9a is connected to the third node N3, and the output end of the fourth sub-transistor M9b is connected to the first sub-node N3a; the connection end of the first sub-transistor M8a and the third sub-transistor M9a serves as the fifth node N5.

[0093] The optional input module 101 further comprises a thirteenth transistor M13, a fourteenth transistor M14 and a fourth capacitor C4; the gate of the thirteenth transistor M13 is connected to the input end N4a of the sixth transistor M6, the thirteenth transistor M13 is connected between the second power supply end VG2 and the first end N3b of the fourth capacitor C4; the gate of the fourteenth transistor M14 is connected to the second end of the fourth capacitor C4, the fourteenth transistor M14 is connected between the first clock end CK1 and the first end N3b of the fourth capacitor C4; and the second end of the fourth capacitor C4 is connected to the first sub-node N3a.

[0094] The optional input module 101 further comprises a fifteenth transistor M15; the gate and the input end of the fifteenth transistor M15 are both connected to the first sub-node N3a, and the output end of the fifteenth transistor M15 is connected to the third node N3.

[0095] In the embodiment, all the transistors in the optional shift register unit are PMOS. The first power supply signal provided by the optional first power supply end VG1 is a low voltage vgl, the second power supply signal provided by the second power supply end VG2 is a high voltage vgh, and the third power supply signal provided by the third power supply end VG3 is a low voltage vgl.

[0096] Fig. 9 is a timing diagram of the shift register unit shown in Fig. 8. As shown in Figs. 8 and 9, after the input module 101 controls the second node N2 to jump from a high level to a low level, the low level as an on level can control the first transistor M1 to be turned on, and then the second power supply signal vgh provided by the second power supply end VG2 is transmitted to the shift output end GOUT through the first transistor M1. In the process of the second node N2 outputting a low level, the input module 101 controls the first node N1 to jump between a high level and a low level. In order to ensure that the second node N2 maintains a low level, when the first node N1 jumps from a low level to a high level, the first clock end CK1 provides a high level signal to make the second transistor M2 be turned off, so that the high level of the first node N1 will not be directly written into the second node N2. The second transistor M2 in the off state will have a leakage current, the low potential of the second node N2 makes the third transistor M3 be turned on, and then the low voltage provided by the first power supply end VG1 can pull down the potential of the first node N1, which is conducive to reducing the fluctuation amplitude of the potential of the second node N2 being coupled to be pulled up.

[0097] For example, the low level of the first node N1 jumping is -7V, the high level of the first node N1 jumping is +15V, the low level of the second node N2 jumping is -7V, and the low voltage vgl provided by the first power supply end VG1 is -7V.

[0098] At the moment of T21 to T22, the first clock end CK1 outputs high level to make the second transistor M2 turn off; the first node N1 jumps from -7V to +15V; because of the leakage of the second transistor M2, the first node N1 is coupled to pull up the second node N2, and the low level (-7V) of the potential of the second node N2 is coupled to be slowly pulled up; but the potential of the second node N2 which is slowly pulled up can still maintain low voltage, so that the third transistor M3 remains on, and thus the low voltage (-7V) provided by the first power supply end VG1 is written into the first node N1 to pull down the potential of the first node N1; based on this, the input module 101 pulls up the potential of the first node N1 to +15V, and the low voltage (-7V) provided by the first power supply end VG1 pulls down the potential of the first node N1 to -7V, so that the high level finally reached by the first node N1 in the process of jumping from -7V to +15V must be less than +15V, and the high level finally reached by the first node N1 in the example is only +6.6V.

[0099] Based on this, at the moment of T21 to T22, the first node N1 finally jumps from -7V to +6.6V, and the leakage of the second transistor M2 causes the potential of the second node N2 to be coupled to be slowly pulled up, and the potential of the second node N2 is coupled to be slowly pulled up from -7V to finally reach -3.8V. Compared with the voltage amplitude of 5.9V by which the node N2 is coupled to be pulled up in FIG. 2 and the output voltage jitter of 10mV of the output end OUT, in the embodiment, the voltage amplitude by which the second node N2 is coupled to be pulled up is only 3.2V by T22, and the output voltage jitter of the output end GOUT of the first transistor M1 is only 2mV.

[0100] Compared with FIG. 2, the output stability of the shift register unit in the embodiment is effectively improved.

[0101] FIG. 10 is a schematic diagram of another shift register unit provided by the embodiment of the application. The structure of the shift register unit shown in FIG. 10 is the same as that of FIG. 8, and the difference lies in that the optional first transistor M1 and the third transistor M3 in FIG. 10 are both NMOS. The first power supply signal provided by the first power supply end VG1 is high voltage vgh, the second power supply signal provided by the second power supply end VG2 is high voltage vgh, and the third power supply signal provided by the third power supply end VG3 is low voltage vgl.

[0102] Figure 11 is a timing diagram of the shift register unit shown in Figure 10. In combination with Figures 10 and 11, the input module 101 controls the second node N2 to jump from low level to high level, which is used as the on level to control the first transistor Ml to turn on, and then the second power supply signal vgh provided by the second power supply terminal VG2 is transmitted to the shift output terminal GOUT through the first transistor Ml. During the process of the second node N2 outputting high level, the input module 101 controls the first node Nl to jump from high level to low level. In order to ensure that the second node N2 maintains high level, the first clock terminal CKl provides high level signal to make the second transistor M2 turn off when the first node Nl jumps from high level to low level, so that the low level of the first node Nl will not be directly written into the second node N2. The second transistor M2 in the off state will have leakage, and the high potential of the second node N2 makes the third transistor M3 turn on, so that the high voltage provided by the first power supply terminal VGl will pull up the potential of the first node Nl, which is conducive to reducing the fluctuation amplitude of the potential of the second node N2 being coupled to pull down.

[0103] For example, the low level of the first node Nl jumping is -7V, the high level of the first node Nl jumping is +15V, the high level of the second node N2 jumping is +7V, and the high voltage vgh provided by the first power supply terminal VGl is +15V.

[0104] At T31 and T32, the first clock terminal CKl outputs high level to make the second transistor M2 turn off; the first node Nl jumps from +15V to -7V; due to the leakage of the second transistor M2, the first node Nl couples to pull down the second node N2, and the high level (+7V) of the potential of the second node N2 is coupled to slowly pull down; but the potential of the second node N2 being slowly pulled down can still maintain high voltage, so that the third transistor M3 remains on, and thus the high voltage (+15V) provided by the first power supply terminal VGl will be written into the first node Nl to pull up the potential of the first node Nl; based on this, the input module 101 pulls down the potential of the first node Nl to -7V, and the high voltage (+15V) provided by the first power supply terminal VGl pulls up the potential of the first node Nl to +15V, so that the low level of the first node Nl finally jumping to during the process of the first node Nl jumping from +15V to -7V must be greater than -7V, and for example, the low level of the first node Nl finally jumping to is only +3.3V.

[0105] Based on this, at T31 to T32, the first node N1 finally jumps from +15V to +3.3V, and the drain current of the second transistor M2 causes the potential of the second node N2 to be coupled and slowly pulled down, and the potential of the second node N2 is coupled and slowly pulled down from +7V to finally reach +3.8V. Thus, it can be seen that, by T32, the voltage amplitude of the second node N2 coupled and pulled down is only 3.2V, and the output voltage jitter of the output end GOUT of the first transistor M1 is only 2mV.

[0106] The output stability of the shift register unit of the embodiment is effectively improved.

[0107] Based on the same inventive concept, the embodiment of the present application provides a driving method of a shift register unit, which is the shift register unit described in any of the above embodiments.

[0108] FIG. 12 is a schematic diagram of a driving method of a shift register unit according to an embodiment of the present application. As shown in FIG. 12, the driving method of the shift register unit includes the following steps.

[0109] In step 201, in a non-output phase, the input module controls the potential of the second node, so that the first control module and the output module are simultaneously switched to an off state.

[0110] In step 202, in an output phase, the input module controls the on-off state of the second control module and the potential of the second node, so that the first control module and the output module are simultaneously switched to an on state, and the signal of the first power supply end is written to the first node.

[0111] Referring to the shift register unit shown in FIG. 8, the driving process of the shift register unit is described. FIG. 13 is another timing diagram of the shift register unit shown in FIG. 8.

[0112] As shown in FIG. 8 and FIG. 13, the working process of the shift register unit includes at least a first sub-phase T41, a second sub-phase T42, a third sub-phase T43, a fourth sub-phase T44, and a fifth sub-phase T45. Among them, the output phase of the shift register unit includes the second sub-phase T42 and the third sub-phase T43. Optionally, the first power supply signal provided by the first power supply end VG1 is a low voltage vgl, the second power supply signal provided by the second power supply end VG2 is a high voltage vgh, the third power supply signal provided by the third power supply end VG3 is a low voltage vgl, the first trigger signal provided by the first signal end STV jumps between high and low levels, the first clock signal provided by the first clock end CK1 jumps between high and low levels, and the second clock signal provided by the second clock end CK2 jumps between high and low levels.

[0113] The working process of the shift register unit is as follows:

[0114] In the first sub-stage T41, the first signal terminal STV is at high level, the first clock terminal CK1 is at high level, and the second clock terminal CK2 is at low level; the fifth transistor M5 is turned on, and the node N4a is at low level; the thirteenth transistor M13 is turned on, and the node N3b is at high level; the sixth transistor M6 is turned on, and the fourth node N4 is at low level; the seventh transistor M7 is turned on, and the first node N1 is at high level; the second transistor M2 is turned off; the first sub-transistor M8a and the second sub-transistor M8b are both turned on, and the fifth node N5 is at high level; the tenth transistor M10 and the twelfth transistor M12 are both turned off; the third sub-transistor M9a and the fourth sub-transistor M9b are both turned on, and the node N3a and the third node N3 are both at high level; the fourteenth transistor M14 and the fifteenth transistor M15 are both turned off; the fourth transistor M4 is turned off; the second node N2 maintains the high level of the previous stage, and the first transistor M1 and the third transistor M3 are both turned off; and the shift output terminal GOUT maintains the low level of the previous stage.

[0115] In the second sub-stage T42, the first signal terminal STV is at high level, the first clock terminal CK1 is toggled between low level and high level, and the second clock terminal CK2 is toggled between high level and low level; the node N4a is at low level; the thirteenth transistor M13 is turned on, and the node N3b is at high level; the sixth transistor M6 is turned on, and the fourth node N4 is at low level; the seventh transistor M7 is turned on; in this sub-stage, the first clock terminal CK1 is first toggled to low level, and then the second transistor M2 is turned on, and the low level of the first clock terminal CK1 is written into the first node N1 and the second node N2 in sequence; then the first clock terminal CK1 is toggled to high level, and then the second transistor M2 is turned off, the first node N1 is at high level, and the second node N2 maintains low level; then the first clock terminal CK1 continues to be toggled in the order of low level, high level, low level, and high level, and the potential of the first node N1 is toggled following the first clock signal CK1, and the second node N2 maintains low level; the fifth node N5 is at high level; the tenth transistor M10 and the twelfth transistor M12 are both turned off; the third sub-transistor M9a and the fourth sub-transistor M9b are both turned on, and the node N3a and the third node N3 are both at high level; the fourteenth transistor M14 and the fifteenth transistor M15 are both turned off; the fourth transistor M4 is turned off; the second node N2 maintains low level, the first transistor M1 and the third transistor M3 are both turned on, the low level of the first power supply terminal VG1 is written into the first node N1, and the potential of the first node N1 is pulled low when it is at high level; and the shift output terminal GOUT outputs the second power supply signal vgh provided by the second power supply terminal VG2.

[0116] In the third sub-stage T43, the first signal terminal STV is at low level, the first clock terminal CK1 is at low level, and the second clock terminal CK2 is at high level; the fifth transistor M5 is turned off, the node N4a is maintained at the low level of the previous stage; the thirteenth transistor M13 is turned on, the node N3b is at high level; the sixth transistor M6 is turned on, the fourth node N4 is at low level; the seventh transistor M7 is turned on, the first node N1 is at low level; the second transistor M2 is turned on, the second node N2 is at low level; the first sub-transistor M8a and the second sub-transistor M8b are both turned off, the fifth node N5 is maintained at the high level of the previous stage; the tenth transistor M10 and the twelfth transistor M12 are both turned off; the third sub-transistor M9a and the fourth sub-transistor M9b are both turned on, the node N3a and the third node N3 are both at high level; the fourteenth transistor M14 and the fifteenth transistor M15 are both turned off; the fourth transistor M4 is turned off; the second node N2 is at low level, the first transistor M1 and the third transistor M3 are both turned on, and the low level vgl of the first power supply terminal VG1 is written to the first node N1, so that the first node N1 and the second node N2 are stabilized at low level; the shift output terminal GOUT outputs the second power supply signal vgh provided by the second power supply terminal VG2.

[0117] In the fourth sub-stage T44, the first signal terminal STV is at low level, the first clock terminal CK1 is at high level, and the second clock terminal CK2 is at low level; the fifth transistor M5 is turned on; the first sub-transistor M8a and the second sub-transistor M8b are both turned on, and the fifth node N5 is at low level; the tenth transistor M10 and the twelfth transistor M12 are both turned on, the node N4a jumps from low level to high level, and the second node N2 is at high level; the thirteenth transistor M13 is turned off; the sixth transistor M6 is turned on, and the fourth node N4 is at high level; the seventh transistor M7 is turned off, and the second transistor M2 is turned off; the third sub-transistor M9a and the fourth sub-transistor M9b are both turned on, and the node N3a and the third node N3 are both at low level; the fourteenth transistor M14 and the fifteenth transistor M15 are both turned on, and the node N3b is at high level; the fourth transistor M4 is turned on; the second node N2 is at high level, and the first transistor M1 and the third transistor M3 are both turned off; the shift output terminal GOUT outputs the third power supply signal vgl provided by the third power supply terminal VG3.

[0118] In the fifth sub-stage T45, the first signal terminal STV is at low level, the first clock terminal CK1 is at low level, and the second clock terminal CK2 is at high level; the fifth transistor M5 is turned off; the first sub-transistor M8a and the second sub-transistor M8b are both turned off, and the fifth node N5 is maintained at low level; the tenth transistor M10 and the twelfth transistor M12 are both turned on, the node N4a is at low level, and the second node N2 is at high level; the sixth transistor M6 is turned on, the fourth node N4 is at low level; the seventh transistor M7 is turned on, the first node N1 is at low level; the second transistor M2 is turned on; the thirteenth transistor M13 is turned on; the second node N2 is at high level, the first transistor M1 and the third transistor M3 are both turned off; the third sub-transistor M9a and the fourth sub-transistor M9b are both turned off, and the node N3a and the third node N3 are maintained at low level; the fourteenth transistor M14 and the fifteenth transistor M15 are both turned on, and the node N3b is at low level; the fourth transistor M4 is turned on; and the shift output terminal GOUT outputs the third power supply signal vgl provided by the third power supply terminal VG3.

[0119] As described above, in the fourth sub-stage T44 and after, no matter whether the first clock terminal CK1 is at low level or high level, whether the second clock terminal CK2 is at high level or low level, the second node N2 is at high level, so that the first transistor M1 is turned off; the third node N3 is at low level, so that the fourth transistor M4 is turned on; and the shift output terminal GOUT outputs the third power supply signal vgl provided by the third power supply terminal VG3. Until the electrical signal provided by the first signal terminal STV jumps to high level, the shift register unit controls the shift output terminal GOUT to output the second power supply signal vgh provided by the second power supply terminal VG2 according to the change of each signal terminal.

[0120] In the embodiment, in the output stage (the second sub-stage T42 and the third sub-stage T43), the second node N2 is at low level, the first transistor M1 and the third transistor M3 are both turned on, the low level vgl of the first power supply terminal VG1 is written to the first node N1, so that the potential of the first node N1 is pulled low when it is at high level, and the first node N1 will couple the second node N2 through the turned-off second transistor M2. Since the high level of the first node N1 is pulled low by the first power supply terminal VG1 when it jumps from low level to high level, the voltage increment of the first node N1 is reduced, so that the fluctuation amplitude of the potential of the second node N2 being pulled high by coupling can be reduced, and thus the output stability of the shift register unit can be improved.

[0121] It should be noted that the shift register unit comprises an eleventh transistor M11, the gate of the eleventh transistor M11 is connected to the reset signal terminal RST, and the eleventh transistor M11 is connected between the second power supply terminal VG2 and the fifth node N5. Optionally, the eleventh transistor M11 is a PMOS.

[0122] In the embodiment, when the electrical signal provided by the reset signal terminal RST is low, the high-level signal provided by the second power supply terminal VG2 is written into the fifth node N5. When the electrical signal provided by the reset signal terminal RST is high, the second power supply terminal VG2 is disconnected with the fifth node N5.

[0123] Optionally, in the power-on stage of the shift register unit, the electrical signal provided by the reset signal terminal RST is low, the second power supply terminal VG2 is connected with the fifth node N5, and the high-level signal provided by the second power supply terminal VG2 is written into the fifth node N5. The high-level signal of the fifth node N5 is transmitted to the third node N3 through the opened ninth transistor M9, and the high-level signal of the third node N3 controls the fourth transistor M4 to be turned off. Based on this, the signal output by the shift output terminal GOUT of the shift register unit in the power-on stage can be maintained as the potential of the last stage, thereby solving the problem of screen flashing in power-on.

[0124] Based on the same inventive concept, the embodiment of the present application provides a gate drive circuit, which comprises the shift register unit as described in any of the above embodiments.

[0125] FIG. 14 is a schematic diagram of a gate drive circuit provided by the embodiment of the present application. As shown in FIG. 14, the gate drive circuit 300 comprises a plurality of shift register units 301. The shift output terminal GOUT of each shift register unit 301 outputs a gate drive signal, and the signal output by the shift output terminal GOUT of the i-th shift register unit 301 is GOUT(i).

[0126] Optionally, the shift output terminal GOUT of the i-th shift register unit 301 is further connected to the first signal terminal STV of the (i+m)-th shift register unit 301.

[0127] Referring to FIG. 14, m can be optionally 1. The shift output end GOUT of the (x-2)th shift register unit 301 outputs a signal GOUT(x-2), and the shift output end GOUT of the (x-2)th shift register unit 301 is also connected to the first signal end STV of the (x-1)th shift register unit 301. In sequence, the shift output end GOUT of the (x-1)th shift register unit 301 outputs a signal GOUT(x-1), and the shift output end GOUT of the (x-1)th shift register unit 301 is also connected to the first signal end STV of the (x)th shift register unit 301. In sequence, the shift output end GOUT of the (x)th shift register unit 301 outputs a signal GOUT(x), and the shift output end GOUT of the (x)th shift register unit 301 is also connected to the first signal end STV of the (x+1)th shift register unit 301. In sequence, the shift output end GOUT of the (x+1)th shift register unit 301 outputs a signal GOUT(x+1), and the shift output end GOUT of the (x+1)th shift register unit 301 is also connected to the first signal end STV of the (x+2)th shift register unit 301. In sequence, the shift output end GOUT of the (x+2)th shift register unit 301 outputs a signal GOUT(x+2), and the shift output end GOUT of the (x+2)th shift register unit 301 is also connected to the first signal end STV of the next shift register unit 301. And so on.

[0128] In other embodiments, m can also be greater than 1, and the cascade connection is not limited to adjacent shift register units, but can be cascade connection of every m shift register units, where m can be equal to 2, 4, 6, or other values, and the cascade connection relationship can be set as required.

[0129] Based on the same inventive concept, the embodiments of the present application also provide a display panel, which comprises the gate drive circuit according to any of the above embodiments.

[0130] FIG. 15 is a schematic diagram of a display panel according to an embodiment of the present disclosure. As shown in FIG. 15, the display panel comprises a first area 401 and a second area 402.

[0131] The first area 401 is configured to display, and the first area 401 comprises a plurality of sub-pixels 410. Optionally, the sub-pixels 410 in the first area 401 are arranged in an array, and the plurality of sub-pixels 410 are arranged along a first direction A1 to form a row of sub-pixels 410, and the plurality of sub-pixels 410 are arranged along a second direction A2 to form a column of sub-pixels 410, and the first direction A1 and the second direction A2 intersect. However, the arrangement of the sub-pixels in the first area can also be other arrangement modes, and is not limited to the array arrangement mode.

[0132] The second area 402 includes a circuit structure for driving the sub-pixels 410 in the first area 401 to display, for example, the second area 402 includes at least one gate driving circuit 300, the gate driving circuit 300 includes a plurality of stage shift register units 301, the gate driving circuit 300 is configured to drive the sub-pixels 410 in the first area 401 to display, and one stage shift register unit 301 can drive one or more rows of sub-pixels 410 in the first area 401 to display.

[0133] The first area 401 of the optional display panel is a display area of the display panel, and the second area 402 is a non-display area of the display panel; the sub-pixels 410 in the display area can be organic light-emitting display units, micro light-emitting diode display units, or other types of sub-pixels, which are not limited.

[0134] The display panel provided in the embodiments of the present application has the corresponding functional modules of the gate driving circuit as described in any of the above embodiments. The display panel can be applied to terminal devices such as smart phones, vehicle-mounted displays, tablet computers, notebook computers, ultra-mobile personal computers, netbooks, smart wearable devices, augmented reality (AR) / virtual reality (VR) devices, etc.

[0135] It should be understood that the steps shown above can be reordered, added, or deleted using various forms of flow. For example, the steps described in the present application can be executed in parallel, sequentially, or in different orders, as long as the desired results of the technical solutions of the present application can be achieved, and the present application is not limited herein.

[0136] The above specific embodiments do not constitute a limitation on the scope of protection of the present application. Those skilled in the art should understand that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A shift register unit, comprising: an input module connected to at least a first node and a second node, the input module configured to control a potential of the first node and a potential of the second node; a first control module connected between a first power terminal and the first node, a control terminal of the first control module connected to the second node, the first control module configured to control a connection between the first power terminal and the first node in response to the potential of the second node; a second control module connected between the first node and the second node, a control terminal of the second control module receiving a first clock signal provided by a first clock terminal, the second control module configured to control a connection between the first node and the second node in response to the first clock signal of the first clock terminal; and an output module connected between a second power terminal and a shift output terminal, a control terminal of the output module connected to the second node, the output module configured to control a connection between the second power terminal and the shift output terminal in response to the potential of the second node. the output module comprises a first transistor and a first capacitor, a gate of the first transistor connected to the second node, the first transistor connected between the second power terminal and the shift output terminal, the first capacitor connected between the second power terminal and the second node; the second control module comprises a second transistor, a gate of the second transistor connected to the first clock terminal, the second transistor connected between the first node and the second node; the first control module comprises a third transistor, a gate of the third transistor connected to the second node, the third transistor connected between the first power terminal and the first node; the third transistor is a PMOS, and a first power signal provided by the first power terminal is a low voltage; or the third transistor is an NMOS, and the first power signal provided by the first power terminal is a high voltage; the input module is configured to switch the potential of the first node between a first low level and a first high level; the third transistor is a PMOS, the first power signal provided by the first power terminal is a low voltage, the low voltage of the first power terminal is less than 0V, or the low voltage of the first power terminal is less than or equal to an average of the first low level and the first high level; or the third transistor is an NMOS, the first power signal provided by the first power terminal is a high voltage, the high voltage of the first power terminal is greater than 1V, or the high voltage of the first power terminal is greater than or equal to the average of the first low level and the first high level; a width-length ratio of the first transistor is greater than a width-length ratio of the third transistor; the width-length ratio of the third transistor is greater than a width-length ratio of the second transistor; the first transistor and the third transistor are both NMOSs; or the first transistor and the third transistor are both PMOSs; the first transistor is an NMOS, and the second power terminal is multiplexed as the first power terminal. ​ ​ ​ ​ 2. The shift register cell of claim 1, wherein, ​ ​ 3. The shift register cell of claim 2, wherein, ​ ​ 4. The shift register cell of claim 3, wherein, ​ ​ 5. The shift register cell of claim 3, wherein, ​ ​ ​ 6. The shift register cell of claim 3, wherein, ​ 7. The shift register cell of claim 3, wherein, ​ 8. The shift register cell of claim 3, wherein, ​ 9. The shift register cell of claim 3, wherein, ​ 10. The shift register cell of claim 3, wherein, The first transistor comprises a first gate metal layer, a first source metal layer and a first drain metal layer; The third transistor comprises a third gate metal layer, a third source metal layer and a third drain metal layer; The first gate metal layer and the third gate metal layer do not overlap in a first direction, and the first direction is perpendicular to a layer where the metal layers are located.

11. The shift register cell of claim 2, wherein, The input module is further connected to a third node, and the input module is configured to control an electric potential of the third node; The output control module comprises a fourth transistor and a second capacitor; 12. The shift register cell of claim 11, wherein, The fourth transistor is connected between the third power supply end and the shift output end, and a gate of the fourth transistor is connected to the third node; The second capacitor is connected between the third node and the shift output end. The capacitance of the first capacitor is greater than that of the second capacitor.

13. The shift register cell of claim 12, wherein, The first transistor is a PMOS, and the third power supply end is multiplexed as the first power supply end.

14. The shift register cell of claim 12, wherein, The input module is further connected to a fourth node, and the input module is configured to control an electric potential of the fourth node; 15. The shift register cell of claim 2, wherein, The input module comprises a third capacitor connected between the fourth node and the first node. The capacitance of the first capacitor is greater than that of the third capacitor.

16. The shift register cell of claim 15, wherein, The input module is further connected to a third node and a fourth node, and the input module is configured to control an electric potential of the third node and an electric potential of the fourth node; 17. The shift register cell of claim 1, wherein, The input module comprises a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor and a twelfth transistor; The gate of the fifth transistor is connected to a second clock end, and the fifth transistor is connected between a third power supply end and an input end of the sixth transistor; The gate of the sixth transistor is connected to the third power supply end, and the sixth transistor is connected between an output end of the fifth transistor and the fourth node; The gate of the seventh transistor is connected to the fourth node, and the seventh transistor is connected between the first clock end and the first node; The gate of the eighth transistor is connected to the second clock end, and the eighth transistor is connected between a first signal end and a fifth node; The gate of the ninth transistor is connected to the third power supply end, and the ninth transistor is connected between the fifth node and the third node; The gate of the tenth transistor is connected to the fifth node, and the tenth transistor is connected between the first clock end and the input end of the sixth transistor; The gate of the eleventh transistor is connected to a reset signal end, and the eleventh transistor is connected between the second power supply end and the fifth node; The gate of the twelfth transistor is connected to the fifth node, and the twelfth transistor is connected between the second power supply end and the second node. ​ 18. The shift register cell of claim 17, wherein, The eighth transistor comprises a first sub-transistor and a second sub-transistor; and the ninth transistor comprises a third sub-transistor and a fourth sub-transistor. The gate of the first sub-transistor and the gate of the second sub-transistor are connected to the second clock terminal, the first sub-transistor is connected between the first signal terminal and the input terminal of the third sub-transistor, and the second sub-transistor is connected between the first signal terminal and the input terminal of the fourth sub-transistor. The gate of the third sub-transistor and the gate of the fourth sub-transistor are connected to the third power terminal, the output terminal of the third sub-transistor is connected to the third node, and the output terminal of the fourth sub-transistor is connected to a first sub-node. The connection terminal of the first sub-transistor and the third sub-transistor serves as the fifth node.

19. The shift register cell of claim 18, wherein, The input module further comprises a thirteenth transistor, a fourteenth transistor and a fourth capacitor. The gate of the thirteenth transistor is connected to the input terminal of the sixth transistor, and the thirteenth transistor is connected between the second power terminal and the first terminal of the fourth capacitor. The gate of the fourteenth transistor is connected to the second terminal of the fourth capacitor, and the fourteenth transistor is connected between the first clock terminal and the first terminal of the fourth capacitor. The second terminal of the fourth capacitor is connected to the first sub-node.

20. The shift register cell of claim 18, wherein, The input module further comprises a fifteenth transistor. The gate and input terminal of the fifteenth transistor are both connected to the first sub-node, and the output terminal of the fifteenth transistor is connected to the third node.

21. A driving method of a shift register unit, wherein the shift register unit is any one of the shift register units of claims 1-20. The driving method of the shift register unit comprises: In a non-output stage, the input module controls the potential of the second node, so that the first control module and the output module are simultaneously switched to an off state. In an output stage, the input module controls the on-off state of the second control module and the potential of the second node, so that the first control module and the output module are simultaneously switched to an on state, and the signal of the first power terminal is written to the first node.

22. A gate drive circuit comprising the shift register unit of any one of claims 1-20.

23. A display panel comprising the gate drive circuit of claim 22.

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