Timing driver, control terminal, display panel, and display device

Abstract

The present disclosure relates to the technical field of display, and provides a timing driver, a control terminal, a display panel, and a display device. The timing controller comprises a first buffer and a second buffer; the timing controller is configured to, in a full-screen refresh mode, enable the first buffer to store full-screen image data and drive, on the basis of the full-screen image data, the display panel to perform full-screen refresh; the timing controller is further configured to, in a local refresh mode and a switching mode, enable the second buffer to store local image data and drive, on the basis of the local image data, the display panel to perform local refresh. The present disclosure can reduce the refresh power consumption of a system.

Description

Timing driver, control terminal, display panel and display device

[0001] Cross-reference to related applications

[0002] The present disclosure claims priority to Chinese Patent Application No. 202411108398.0, filed on August 13, 2024, entitled “Timing driver, control terminal, display panel and display device”, the entire contents of which are incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present disclosure relates to the technical field of display, in particular, to a timing driver, a control terminal, a display panel and a display device. BACKGROUND

[0004] The display panel is refreshed in a full-screen refresh manner. When a local refresh area of the display panel needs to be refreshed, the local refresh area still needs to be refreshed in a full-screen refresh manner, thereby increasing the power consumption of the system.

[0005] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY

[0006] The purpose of the present disclosure is to overcome the shortcomings of the prior art, and to provide a timing driver, a control terminal, a display panel and a display device, which can reduce the power consumption of the system.

[0007] According to a first aspect of the present disclosure, a timing controller is provided, the timing controller comprising a first buffer, a second buffer;

[0008] The timing controller is configured to, in a full-screen refresh mode, cause the first buffer to store full-screen picture data and drive the display panel to refresh in a full-screen refresh manner according to the full-screen picture data;

[0009] The timing controller is further configured to, in a local refresh mode and a switching mode, cause the second buffer to store local picture data and drive the display panel to refresh in a local refresh manner according to the local picture data.

[0010] In an embodiment of the present disclosure, the timing controller is configured to, in the full-screen refresh mode, receive initial full-screen picture data and store the initial full-screen picture data directly in the first buffer;

[0011] The timing controller is further configured to receive initial partial picture data in the partial refresh mode and store the initial partial picture data in the second buffer after processing.

[0012] In one embodiment of the present disclosure, the timing controller further comprises a mode selection unit.

[0013] The mode selection unit is configured to cause the full screen picture data to be stored in the first buffer in the full screen refresh mode and to cause the partial picture data to be stored in the second buffer in the partial refresh mode.

[0014] In one embodiment of the present disclosure, the timing controller is further configured to operate in the switching mode for one frame after receiving a switching instruction and switch to the full screen refresh mode or the partial refresh mode after one frame after receiving the switching instruction.

[0015] In one embodiment of the present disclosure, the timing controller is further provided with an extraction unit; the switching mode comprises a first switching mode; the timing controller is in the full screen refresh mode one frame before the first switching mode;

[0016] The extraction unit is configured to receive partial address information in the first switching mode and obtain partial picture data from the full screen picture data stored in the first buffer according to the partial address information and store the partial picture data in the second buffer;

[0017] The timing controller is configured to drive the display panel according to the partial picture data provided by the extraction unit to the second buffer in the first switching mode and switch to the partial refresh mode one frame after the first switching mode.

[0018] In one embodiment of the present disclosure, the switching mode comprises a second switching mode; the timing controller is in the partial refresh mode one frame before the second switching mode;

[0019] The timing controller is configured to drive the display panel according to the partial picture data in the second buffer in the second switching mode and switch to the full screen refresh mode one frame after the second switching mode.

[0020] In one embodiment of the present disclosure, for driving the display panel; at least part of the data lines of the display panel is connected with a pre-charge unit; the pre-charge unit comprises a buffer capacitor and a switching element, and the buffer capacitor is electrically connected with the data line through the switching element;

[0021] The timing controller is further configured to, in the full-screen refresh mode, load a pre-charge signal to each of the pre-charge units to make each of the switch elements electrically conductive before the first row of sub-pixels is loaded with the driving voltage until after the first row of sub-pixels is loaded with the driving voltage.

[0022] The timing controller is further configured to, in the full-screen refresh mode, continuously load a lock signal to each of the pre-charge units to make each of the switch elements electrically non-conductive after the first row of sub-pixels is loaded with the driving voltage.

[0023] In an embodiment of the present disclosure, a display panel is driven; at least part of data lines of the display panel are connected with pre-charge units; the pre-charge units comprise buffer capacitors and switch elements, and the buffer capacitors are electrically connected with the data lines through the switch elements;

[0024] The switching mode comprises a first switching mode; the timing controller is in the full-screen refresh mode at a frame time before the first switching mode;

[0025] The timing controller is configured to, in the first switching mode, load a pre-charge signal to each of the pre-charge units connected with the data lines of the local refresh area to make each of the switch elements electrically conductive before the first row of sub-pixels of the local refresh area is loaded with the driving voltage; and continuously load a lock signal to each of the pre-charge units connected with each of the data lines outside the local refresh area to make each of the switch elements electrically non-conductive;

[0026] The timing controller is configured to, in the first switching mode, continuously load a lock signal to each of the pre-charge units connected with each of the data lines to make each of the switch elements electrically non-conductive when the first row of sub-pixels of the local refresh area is loaded with the driving voltage until after the first row of sub-pixels is loaded with the driving voltage.

[0027] In an embodiment of the present disclosure, a display panel is driven; at least part of data lines of the display panel are connected with pre-charge units; the pre-charge units comprise buffer capacitors and switch elements, and the buffer capacitors are electrically connected with the data lines through the switch elements;

[0028] The switching mode comprises a second switching mode; the timing controller is in the local refresh mode at a frame time before the second switching mode;

[0029] The timing controller is configured to, in the local refresh mode and the second switching mode, load a pre-charge signal to each of the pre-charge units connected to the data lines corresponding to the local refresh area before and after the first row of sub-pixels of the local refresh area is loaded with the driving voltage, so as to make each of the switch elements electrically conductive.

[0030] The timing controller is further configured to, in the local refresh mode and the second switching mode, continuously load a lock signal to each of the pre-charge units connected to the data lines corresponding to the local refresh area after the first row of sub-pixels of the local refresh area is loaded with the driving voltage, so as to make each of the switch elements electrically non-conductive.

[0031] The timing controller is further configured to, in the local refresh mode and the second switching mode, continuously load a lock signal to each of the pre-charge units connected to each of the data lines outside the local refresh area, so as to make each of the switch elements electrically non-conductive.

[0032] In an embodiment of the present disclosure, the timing controller is further configured to, in the second switching mode, after the last row of sub-pixels of the local refresh area is loaded with the driving voltage, sequentially perform the following processes:

[0033] first, load a pre-charge signal to each of the pre-charge units connected to the data lines corresponding to the local refresh area, so as to make each of the switch elements electrically conductive;

[0034] then, load a corresponding compensation driving voltage to any one of the data lines in each of the local refresh areas; the driving compensation voltage of the data line is a driving voltage determined according to compensation data of the data line; the compensation data of the data line is the data of the sub-pixel connected to the data line in the first row of sub-pixels of the display panel in the first buffer.

[0035] According to a second aspect of the present disclosure, a control terminal is provided for interacting with the timing controller described above; wherein the control terminal is configured to send initial full-screen picture data to the timing controller in the full-screen refresh mode, and send initial local picture data to the timing controller in the local refresh mode.

[0036] In an embodiment of the present disclosure, the timing controller is further provided with an extraction unit; the extraction unit is configured to, in the first switching mode, receive local address information, and read local picture data from the last frame of full-screen picture data in the full-screen refresh mode according to the local address information and write the local picture data into the second buffer.

[0037] Before the timing controller receives the first frame of the partial refresh mode, the timing controller is configured to drive the display panel to perform partial refresh according to the first switching mode of the partial picture data in the second buffer;

[0038] The control terminal is further configured to determine whether to perform the first switching mode, and send local address information of the partial refresh area to the timing controller when it is determined to perform the first switching mode.

[0039] According to a third aspect of the present disclosure, a display panel is provided for cooperating with the timing controller described above; wherein the display panel has a source driver; the source driver can receive picture data from the timing controller and drive the display panel according to the picture data.

[0040] According to a fourth aspect of the present disclosure, a display panel is provided for cooperating with the timing controller described above; wherein the display panel is provided with a plurality of data lines arranged in a column direction in a display area; at least part of the data lines are connected with a pre-charge unit; a control end of the pre-charge unit is electrically connected with a pre-charge control trace; the pre-charge control trace is used to load a pre-charge signal and a lock signal.

[0041] In an embodiment of the present disclosure, the pre-charge unit comprises a switching element and a buffer capacitor;

[0042] Wherein a first electrode plate of the buffer capacitor is electrically connected with the data line through the switching element, and a second electrode plate of the buffer capacitor is grounded;

[0043] A control end of the switching element is electrically connected with the pre-charge control trace; the switching element is configured to be electrically conducted in response to the pre-charge signal;

[0044] The switching element is further configured to be electrically disconnected in response to the lock signal.

[0045] According to a fifth aspect of the present disclosure, a display device is provided, comprising the timing controller described above;

[0046] And / or the display panel described above.

[0047] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0048] The accompanying drawings, which are incorporated herein and constitute part of the specification, illustrate embodiments consistent with the present disclosure and, together with the description, further serve to explain the principles of the present disclosure. It is to be understood that the drawings are only schematic, and that they do not purport to be to scale with respect to one another. The embodiments will be described with reference to the drawings in conjunction with a detailed description.

[0049] FIG. 1 is a schematic diagram of a display device in an embodiment of the present disclosure.

[0050] FIG. 2 is a schematic diagram of signal interaction of a control terminal, a timing controller, a source driver and a display panel in an embodiment of the present disclosure.

[0051] FIG. 3 is a schematic diagram of a display panel in an embodiment of the present disclosure.

[0052] FIG. 4 is a schematic diagram of a display panel in an embodiment of the present disclosure.

[0053] FIG. 5 is a schematic diagram of signal interaction of a control terminal, a timing controller and a source driver in an embodiment of the present disclosure.

[0054] FIG. 6 is a schematic diagram of a display panel in an embodiment of the present disclosure.

[0055] FIG. 7 is a schematic diagram of signal interaction of a control terminal, a timing controller and a source driver in an embodiment of the present disclosure.

[0056] FIG. 8 is a schematic diagram of signal interaction of a control terminal, a timing controller and a source driver in an embodiment of the present disclosure.

[0057] FIG. 9 is a schematic diagram of signal interaction of a control terminal, a timing controller and a source driver in an embodiment of the present disclosure.

[0058] FIG. 10 is a schematic diagram of signal interaction of a control terminal, a timing controller and a source driver in an embodiment of the present disclosure.

[0059] FIG. 11 is a schematic diagram of a display panel in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0060] Example implementations will now be described more fully with reference to the accompanying drawings. Example implementations can be implemented in any of various forms, and are not limited to the implementations set forth in this document; rather, the implementations are provided as non-limiting examples so that this disclosure will be thorough and complete, and will fully convey the scope of the example implementations to those skilled in the art. Like reference numerals may be used to refer to like elements throughout and detailed descriptions of the like elements will not be repeated. In addition, the drawings are only schematic and the dimensions are not necessarily to scale.

[0061] Although relative terms such as "upper", "lower", etc. are used herein to describe one component's relationship to another component of the icon, these terms are used herein for convenience only and are not necessarily limiting. It will be understood that, if the icon were turned over so that the upper portion is now the lower portion, the described "upper" component would now be the "lower" component. When a structure is "on" another structure, it can mean that the structure is formed integrally with the other structure or that the structure is "directly" on the other structure or that the structure is "indirectly" on the other structure via another structure.

[0062] The terms "one", "a", "an", "the", and "at least one" are used to mean that "one or more" of something is present; the terms "comprising", "having", and "including" are used to mean "including, but not limited to"; and the term "or" is used in its inclusive sense (and not in its exclusive sense) so that when used, for example, in a list of two or more items, the term "or" covers all of the following interpretations of the word: any of the items in the list, all of the items in the list, or some combination of items in the list. The term "first", "second", and "third", etc. are used to denote names of similar objects, and are not limits to number of objects.

[0063] The display device according to the embodiments of the present disclosure can include a display module and / or a driving module for driving the display module. In one example, the display device can include the display module. In another example, the display device can include the driving module. In other examples, the display device can include the display module and the driving module.

[0064] Referring to FIG. 1, the display module can include a display panel PNL and a source driver SIC. The driving module can include a power manager PMIC, a timing controller TCON, a main circuit board MPCB, etc. In other embodiments of the present disclosure, the display module can include a display panel PNL. The driving module can include a power manager PMIC, a timing controller TCON, a source driver SIC, a main circuit board MPCB, etc. Referring to FIG. 2, the timing controller TCON receives initial picture data, processes the picture data, and transmits the processed picture data to the source driver SIC. The source driver SIC loads a driving voltage Vdata to the display panel PNL according to the received picture data, so that the display panel PNL displays a picture.

[0065] Referring to FIG. 1, the source driver SIC receives a clock signal and a data signal from the timing controller TCON, and then loads a driving voltage Vdata to the display panel PNL according to a predetermined timing. In some embodiments, the source driver SIC can be a source driving chip. In one example, the source driving chip can be fixed on a flexible conductive film, and then assembled into a chip on film (COF). The chip on film (COF) is electrically connected to the bonding pad of the display panel PNL, and can be bent to the backlight side of the display panel PNL to reduce the frame of the display device. In another example, the source driving chip can be fixed on the display panel PNL, and electrically connected to the main circuit board MPCB through the flexible conductive film.

[0066] In one example, referring to FIG. 1, there are multiple chip on films (COF), and at least one source driving chip as a source driver SIC is arranged on each chip on film (COF). The multiple chip on films (COF) are arranged side by side, and each chip on film (COF) drives multiple data wires.

[0067] In one embodiment of the present disclosure, referring to FIG. 1, the power manager PMIC and the timing controller TCON are arranged on the main circuit board MPCB. The main circuit board MPCB is electrically connected to the multiple chip on films (COF). In this way, the power manager PMIC and the timing controller TCON can load power voltage and signals to the source driver SIC through the main circuit board MPCB and the chip on film (COF).

[0068] In one embodiment of the present disclosure, the display panel PNL can be an organic light-emitting diode (OLED) display panel, a micro light-emitting diode (Micro LED) display panel, a quantum dot-organic light-emitting diode (QD-OLED) display panel, a quantum dot light-emitting diode (QLED) display panel, an LCD (liquid crystal) display panel, or other types of display panels.

[0069] In one embodiment of the present disclosure, referring to FIG. 3, the display panel PNL includes arrayed display units UU, and each display unit UU includes a sub-pixel PIX and a sub-pixel driving circuit PDC driving the sub-pixel PIX. Wherein, the display panel PNL is provided with multiple scan lines GL arranged along the row direction DH in the display area AA, and each scan line GL is arranged one-to-one with each display unit row HUU. The scan line GL is connected to each sub-pixel driving circuit PDC of the corresponding display unit row HUU.

[0070] The display panel PNL is provided with a plurality of data lines DL arranged along the column direction DV in the display area AA, each data line DL is arranged in one-to-one correspondence with each display unit column; the data line DL is connected with each sub-pixel drive circuit PDC of the corresponding display unit column. In this way, the sub-pixel drive circuit PDC of each display unit UU is connected with one scan line GL and one data line DL. When the gate signal GS is loaded on the scan line GL, the data voltage loaded on the data line DL can be written into the sub-pixel drive circuit PDC, so that the sub-pixel drive circuit PDC can control the brightness of the sub-pixel PIX according to the written data voltage.

[0071] In an embodiment of the present disclosure, referring to FIG. 4, the peripheral area BB of the display panel PNL can be provided with a gate drive circuit GOA, which can include a plurality of shift registers SR cascaded in sequence. The scan line GL is connected in one-to-one correspondence with at least part of the shift registers SR, so that the gate signal generated by the shift register SR can be loaded on the corresponding scan line GL.

[0072] In the related art, the display panel PNL is refreshed in a full-screen refresh mode. When the local refresh area of the display panel needs to be refreshed, the local refresh area still needs to be refreshed in the full-screen refresh mode, thereby increasing the refresh power consumption of the system.

[0073] In order to solve the above problems, in an embodiment of the present disclosure, referring to FIG. 5, the timing controller TCON includes a first buffer MU1 and a second buffer MU2. The first buffer MU1 is used to store full-screen picture data in a full-screen refresh mode, and the full-screen picture data is used to drive the display panel PNL to perform full-screen refresh. The second buffer MU2 is used to store local picture data in a local refresh mode and a switching mode, and the local picture data is used to drive the display panel PNL to perform local refresh. In this way, by providing independent first buffer MU1 and second buffer MU2 in the timing controller TCON, the first buffer MU1 stores the full-screen picture data in the full-screen refresh mode, and the second buffer MU2 stores the local picture data in the local refresh mode and the switching mode. When the local refresh area of the display panel PNL needs to be refreshed, the local picture data is stored in the second buffer MU2 in the local refresh mode, and the local refresh of the display panel PNL does not need to be realized in the full-screen refresh mode in the related art, thereby facilitating to reduce the refresh power consumption of the system.

[0074] In one embodiment of the present disclosure, the timing controller TCON is configured to receive initial full-screen picture data in the full-screen refresh mode and store the initial full-screen picture data directly in the first buffer MU1 or store the initial full-screen picture data after processing in the first buffer MU1. In one example, the timing controller TCON is configured to receive initial full-screen picture data in the full-screen refresh mode and store the initial full-screen picture data as full-screen picture data directly in the first buffer MU1. In another example, the timing controller TCON is configured to receive initial full-screen picture data in the full-screen refresh mode and store the initial full-screen picture data after processing as full-screen picture data in the first buffer MU1.

[0075] It can be understood that, in one example, the initial full-screen picture data is full-screen picture data. In another example, the initial partial picture data is partial picture data.

[0076] In one embodiment of the present disclosure, the timing controller TCON is further configured to receive initial partial picture data in the partial refresh mode and store the initial partial picture data directly in the second buffer MU2 or store the initial partial picture data after processing in the second buffer MU2. In one example, the timing controller TCON is further configured to receive initial partial picture data in the partial refresh mode and store the initial partial picture data as partial picture data directly in the second buffer MU2. In another example, the timing controller TCON is further configured to receive initial partial picture data in the partial refresh mode and store the initial partial picture data after processing as partial picture data in the second buffer MU2.

[0077] In one embodiment of the present disclosure, referring to FIG. 5, the timing controller TCON is configured to receive full-screen picture data in the full-screen refresh mode and store the full-screen picture data directly in the first buffer MU1. The timing controller TCON is further configured to receive partial picture data in the partial refresh mode and store the partial picture data after processing in the second buffer MU2.

[0078] In one embodiment of the present disclosure, referring to FIG. 5, the timing controller TCON further comprises a mode selection unit MSU. The mode selection unit MSU is configured to cause the full-screen picture data to be stored in the first buffer MU1 in the full-screen refresh mode, and to cause the partial picture data to be stored in the second buffer MU2 in the partial refresh mode. Thus, in the full-screen refresh mode, the mode selection unit MSU causes the full-screen picture data to be stored in the first buffer MU1, and causes the partial picture data not to be stored in the second buffer MU2. In the partial refresh mode, the mode selection unit MSU causes the partial picture data to be stored in the second buffer MU2, and causes the full-screen picture data not to be stored in the first buffer MU1. The mode selection unit MSU controls the switching between the two refresh modes.

[0079] In one embodiment of the present disclosure, the timing controller TCON is configured to work in the switching mode for one frame time after receiving the switching instruction, and to switch to the full-screen refresh mode or to the partial refresh mode after the one frame time.

[0080] It can be understood that, in the full-screen refresh mode, the timing controller TCON continues to work in the full-screen refresh mode when no switching instruction is received. In the partial refresh mode, the timing controller TCON continues to work in the partial refresh mode when no switching instruction is received. When the timing controller TCON receives the switching instruction, it works in the switching mode for only one frame time, and after the one frame time, the timing controller TCON works in the full-screen refresh mode or in the partial refresh mode.

[0081] In one embodiment of the present disclosure, referring to FIG. 5, the timing controller TCON is further provided with an image processing unit IPU configured to process the picture data. The image processing unit IPU is configured to, in the full-screen refresh mode, receive and process the full-screen picture data sent by the first buffer MU1, or receive and process the initial full-screen picture data sent by the mode selection unit MSU. In one example, the image processing unit IPU is configured to receive and process the full-screen picture data sent by the first buffer MU1. In another example, the image processing unit IPU is configured to receive and process the initial full-screen picture data sent by the mode selection unit MSU.

[0082] In one embodiment of the present disclosure, the image processing unit IPU is further configured to, in the partial refresh mode, receive and process the partial picture data sent by the second buffer MU2, or receive and process the initial partial picture data sent by the mode selection unit MSU. In one example, the image processing unit IPU is configured to receive and process the partial picture data sent by the second buffer MU2. In another example, the image processing unit IPU is configured to receive and process the initial partial picture data sent by the mode selection unit MSU.

[0083] It can be understood that the processing of the picture data by the image processing unit IPU refers to the processing of the color, quality, contrast, etc. of the picture data. For example, in the full-screen refresh mode, the image processing unit IPU performs color, quality, contrast, etc. processing on the full-screen picture data. For another example, in the partial refresh mode, the image processing unit IPU performs color, quality, contrast, etc. processing on the partial picture data.

[0084] When the full-screen refresh mode is switched to the partial refresh mode, since at least one frame of picture data is required for the switching of the resolution (number of pixels) and the frame rate, for example, switching the picture data of high resolution and low frame rate to the picture data of low resolution and high frame rate, it results in that the first frame of partial picture data of the partial refresh mode cannot be timely stored in the second buffer MU2 in the partial refresh mode, thereby causing the problem of frame dropping and frame freezing of the display panel PNL when switched to the partial refresh mode.

[0085] To solve the problem of switching the refresh mode, in one embodiment of the present disclosure, referring to FIG. 5, the timing controller TCON is further provided with an extraction unit DU. The extraction unit DU is configured to receive the local address information ADP in the first switching mode, and read the local picture data from the last frame of full-screen picture data in the full-screen refresh mode stored in the first buffer MU1 according to the local address information ADP and write the local picture data into the second buffer MU2. The timing controller TCON is configured to drive the display panel PNL according to the local picture data provided by the extraction unit DU to the second buffer MU2 in the first switching mode, and switch to the local refresh mode after one frame time of the first switching mode. Before the timing controller TCON receives the first frame of local picture data in the local refresh mode, the timing controller TCON is further configured to drive the display panel PNL to perform local refresh according to the local picture data in the first switching mode in the second buffer MU2. Before the timing controller TCON receives the first frame of full-screen picture data in the full-screen refresh mode, the timing controller TCON is further configured to drive the display panel PNL to perform local refresh according to the local picture data in the second switching mode in the second buffer MU2. In this way, when the timing controller TCON receives the first switching instruction, the extraction unit DU reads the local picture data in the first switching mode from the last frame of full-screen picture data in the full-screen refresh mode and stores the local picture data in the second buffer MU2. The local picture data in the second buffer MU2 drives the display panel PNL to perform local refresh, and at this time, the resolution and frame rate are switched. When the full-screen refresh mode is switched to the local refresh mode, the switching can be smoothly and smoothly, and there is no situation of picture jamming and frame dropping.

[0086] It should be noted that the switching mode includes the first switching mode and the second switching mode. The first switching mode is one frame time of switching from the full-screen refresh mode to the local refresh mode. The second switching mode is one frame time of switching from the local refresh mode to the full-screen refresh mode. The switching instruction includes the first switching instruction and the second switching instruction. The first switching instruction is used to start the first switching mode, and the second switching instruction is used to start the second switching mode.

[0087] It can be understood that the first frame of picture data and the last frame of picture data in a refresh mode refer to the first frame of picture data and the last frame of picture data continuously in the refresh mode. In an example, the first frame of picture data and the last frame of picture data in the full-screen refresh mode refer to the first frame of picture data and the last frame of picture data continuously in the full-screen refresh mode. In other words, the full-screen refresh mode is not switched to the local refresh mode or the switching mode. In another example, the first frame of picture data and the last frame of picture data in the local refresh mode refer to the first frame of picture data and the last frame of picture data continuously in the local refresh mode. In other words, the local refresh mode is not switched to the full-screen refresh mode or the switching mode.

[0088] It should be further noted that the local address information ADP refers to the starting coordinate and the length of the local picture data in the first switching mode. In other words, the local address information ADP refers to the starting coordinate and the ending coordinate in the first switching mode.

[0089] In an embodiment of the present disclosure, the timing controller TCON is configured to drive the display panel PNL according to the local picture data in the second buffer MU2 in the second switching mode, and switch to the full-screen refresh mode after a frame time of the second switching mode. In this way, the second switching mode is inserted between the local refresh mode and the full-screen refresh mode, and the timing controller TCON drives the display panel PNL according to the local picture data in the second buffer MU2 in the second switching mode, so that the display panel PNL is smoothly and smoothly switched when the local refresh mode is switched to the full-screen refresh mode, avoiding the display panel PNL from dropping frames and flashing screens, and improving the display quality of the display panel PNL.

[0090] In an embodiment of the present disclosure, referring to FIGS. 5 and 6, the timing controller TCON is configured to drive the display panel PNL. At least part of the data lines DL of the display panel PNL is connected with a pre-charge unit PCU. In an example, part of the data lines DL of the display panel PNL is connected with the pre-charge unit PCU. In another example, all of the data lines DL of the display panel PNL is connected with the pre-charge unit PCU. In which, each data line DL can be connected with one pre-charge unit PCU, or multiple data lines DL can be connected with one pre-charge unit PCU.

[0091] The pre-charge unit PCU includes a buffer capacitor CST and a switching element SW. The buffer capacitor CST is electrically connected with the data line DL through the switching element SW. The switching element SW can be a thin film transistor or a transistor.

[0092] The timing controller TCON is further configured to load a pre-charge signal to each pre-charge unit PCU to make each switch element SW electrically conductive before and after the first row of sub-pixels is loaded with the driving voltage Vdata in the full-screen refresh mode. The timing controller TCON is further configured to continuously load a lock signal to each pre-charge unit PCU to make each switch element SW electrically non-conductive after the first row of sub-pixels is loaded with the driving voltage Vdata in the full-screen refresh mode.

[0093] Thus, before the first row of sub-pixels is loaded with the driving voltage Vdata in the full-screen refresh mode, the timing controller TCON loads the pre-charge signal to the pre-charge unit PCU to make the switch element SW electrically conductive, at which time the charge stored in the buffer capacitor CST pre-charges the first row of sub-pixels of the display panel PNL. Then the driving voltage Vdata is loaded to the first row of sub-pixels while the buffer capacitor CST is charged. After the first row of sub-pixels is loaded with the driving voltage Vdata, the timing controller TCON loads the lock signal to the pre-charge unit PCU to make the switch element SW electrically non-conductive, which stores the charge in the buffer capacitor CST. The above steps are repeated to pre-charge the first row of sub-pixels before the display panel PNL displays the next frame of full-screen image, which facilitates to improve the charging speed of the sub-pixels and to improve the display quality of the display panel PNL.

[0094] It can be understood that in the drawings of the present disclosure, a triangle is used to represent the connection between the data line DL and the source driver SIC. Among them, the black triangle represents that the source driver SIC does not load the driving voltage Vdata to the connected data line DL; in other words, the sub-pixel PIX corresponding to the data line DL connected by the black triangle is not refreshed. The white triangle represents that the source driver SIC loads the driving voltage Vdata to the connected data line DL; in other words, the sub-pixel PIX corresponding to the data line DL connected by the white triangle is refreshed.

[0095] In one embodiment of the present disclosure, referring to FIG. 5 and FIG. 6, the timing controller TCON is configured to, in the first switching mode, load a pre-charge signal to each of the pre-charge units PCU connected to the data lines DL corresponding to the local refresh region to make each of the switch elements SW electrically conductive before loading the driving voltage Vdata to the first row of sub-pixels of the local refresh region; and continuously load a lock signal to each of the pre-charge units PCU connected to each of the data lines DL outside the local refresh region to make each of the switch elements SW electrically non-conductive. In this way, since the local picture data in the first switching mode is extracted from the full-screen picture data of the last frame, the first row of sub-pixels of the local refresh region can be pre-charged before the driving voltage Vdata is loaded to the first row of sub-pixels of the local refresh region in the first switching mode, so as to improve the charging rate. Since the sub-pixels outside the local refresh region do not emit light, the sub-pixels outside the local refresh region are not pre-charged, and the buffer capacitor CST outside the local refresh region stores the charge of the full-screen refresh mode, so as to pre-charge the first row of sub-pixels of the first frame of the full-screen refresh mode when the local refresh mode is switched to the full-screen refresh mode.

[0096] The timing controller TCON is configured to, in the first switching mode, continuously load a lock signal to each of the pre-charge units PCU connected to the data lines DL corresponding to the local refresh region to make each of the switch elements SW electrically non-conductive when the driving voltage Vdata is loaded to the first row of sub-pixels of the local refresh region until after the driving voltage Vdata is loaded to the first row of sub-pixels; and load a lock signal to each of the pre-charge units PCU connected to each of the data lines DL outside the local refresh region to make each of the switch elements SW electrically non-conductive. Since the local picture data in the local refresh mode is different from the local picture data in the first switching mode, the buffer capacitor CST of the local refresh region is not used to store the charge in the first switching mode, so as to avoid the case that the driving voltage Vdata of the first row of sub-pixels is written incorrectly in the local refresh mode.

[0097] The timing controller TCON is configured to, in the first switching mode, continuously load a lock signal to each of the pre-charge units PCU connected to each of the data lines DL to make each of the switch elements SW electrically non-conductive after the driving voltage Vdata is loaded to the first row of sub-pixels of the local refresh region.

[0098] In one embodiment of the present disclosure, referring to FIG. 5 and FIG. 6, a timing controller TCON is configured to drive a display panel PNL. At least part of data lines DL of the display panel PNL are connected with a pre-charge unit PCU. In one example, part of data lines DL of the display panel PNL are connected with a pre-charge unit PCU. In another example, all of data lines DL of the display panel PNL are connected with a pre-charge unit PCU. In which, each data line DL can be connected with one pre-charge unit PCU, or multiple data lines DL can be connected with one pre-charge unit PCU.

[0099] The pre-charge unit PCU includes a buffer capacitor CST and a switching element SW. In which, the buffer capacitor CST is electrically connected with the data line DL through the switching element SW. The switching element SW can be a thin film transistor or a triode.

[0100] The timing controller TCON is configured to, in the local refresh mode and the second switching mode, load a pre-charge signal to each pre-charge unit PCU connected with the data line DL corresponding to the local refresh area before and after loading the driving voltage Vdata to the first row of sub-pixels of the local refresh area, so as to electrically turn on each switching element SW.

[0101] The timing controller TCON is further configured to, in the local refresh mode and the second switching mode, continuously load a lock signal to each pre-charge unit PCU connected with the data line DL corresponding to the local refresh area after loading the driving voltage Vdata to the first row of sub-pixels of the local refresh area, so as to electrically turn off each switching element SW.

[0102] The timing controller TCON is further configured to, in the local refresh mode and the second switching mode, continuously load a lock signal to each pre-charge unit PCU connected with each data line DL outside the local refresh area, so as to electrically turn off each switching element SW.

[0103] Thus, before the first row of sub-pixels in the local refresh area is loaded with the driving voltage Vdata in the local refresh mode and the second switching mode, the timing controller TCON loads a pre-charge signal to the pre-charge unit PCU connected to the data line DL corresponding to the local refresh area, so that the switch element SW is electrically turned on, and at this time, the charge stored in the cache capacitor CST is used to pre-charge the first row of sub-pixels in the local refresh area; at the same time, the timing controller TCON loads a lock signal to the pre-charge unit PCU connected to the data line DL outside the local refresh area, so that the switch element SW is electrically turned off; then the driving voltage Vdata is loaded to the first row of sub-pixels in the local refresh area, and at the same time, the cache capacitor CST corresponding to the local refresh area is charged; after the first row of sub-pixels is loaded with the driving voltage Vdata, the timing controller TCON loads a lock signal to the pre-charge unit PCU corresponding to the local refresh area, so that the switch element SW in the local refresh area is electrically turned off, and the charge is cached in the cache capacitor CST in the local refresh area. Before the display panel PNL displays the next frame of local picture, the above steps are repeated to pre-charge the first row of sub-pixels in the local refresh area, so as to improve the charging speed of the sub-pixels and improve the display quality of the display panel PNL.

[0104] Of course, in the full-screen refresh mode, when the display panel PNL displays the last frame of full-screen picture, before the first row of sub-pixels of the last frame of full-screen picture is loaded with the driving voltage Vdata, the timing controller TCON first loads a pre-charge signal to all pre-charge units PCU, so that each switch element SW is electrically turned on, and at this time, the charge stored in each cache capacitor CST is used to pre-charge the first row of sub-pixels of the display panel PNL, so as to improve the charging rate of the sub-pixels. After the charge in the cache capacitor CST is released, the pre-charge signal is continuously loaded to each pre-charge unit PCU, so that each switch element SW is electrically turned on, so as to charge each cache capacitor CST. However, in this process, the cache capacitor CST outside the local refresh area is charged, so as to pre-charge the first row of sub-pixels of the first frame of full-screen picture when the local refresh mode is switched back to the full-screen refresh mode, and improve the charging rate of the sub-pixels.

[0105] In an embodiment of the present disclosure, the timing controller TCON is further configured to, in the second switching mode, after the last row of sub-pixels in the local refresh area is loaded with the driving voltage Vdata, sequentially perform the following processes:

[0106] First, a pre-charge signal is loaded to each pre-charge unit PCU connected to the data line DL corresponding to the local refresh area to electrically turn on each switch element SW.

[0107] Then, a corresponding compensation driving voltage is loaded to any one of the data lines DL in each local refresh area. The driving compensation voltage of the data line DL is a driving voltage determined according to the compensation data of the data line DL. The compensation data of the data line DL is the data of the sub-pixel connected with the data line DL in the first row of the sub-pixels of the display panel PNL in the first buffer MU1.

[0108] Thus, when the local refresh mode is switched to the full-screen refresh mode, the second switching mode is needed to transit, so that the local refresh mode is smoothly switched to the full-screen refresh mode. In the second switching mode, after the display panel PNL displays the last row of the sub-pixels of the local picture of the second switching mode, before the driving voltage Vdata is loaded to the first row of the sub-pixels of the full-screen picture of the first frame of the full-screen refresh mode, the pre-charge signal is loaded to the pre-charge unit PCU corresponding to the local refresh area, so that the switch element SW corresponding to the local refresh area is electrically conducted, and thus the buffer capacitor CST corresponding to the local refresh area is discharged (at this time, the scanning signal of the gate driving circuit is not loaded to the first row of the sub-pixels, and thus the first row of the sub-pixels is not charged), after the buffer capacitor CST corresponding to the local refresh area is discharged, the compensation driving voltage of the first row of the sub-pixels of the first frame of the full-screen picture is inserted, so that the compensation driving voltage is buffered in the buffer capacitor CST, and the compensation driving voltage is stored in the first buffer MU1. Then, the pre-charge signal is loaded to the pre-charge unit PCU corresponding to the local refresh area by the timing controller TCON, so that the switch element SW corresponding to the local refresh area is electrically conducted, at this time, the compensation driving voltage buffered in the buffer capacitor CST corresponding to the local refresh area will pre-charge the first row of the sub-pixels of the local refresh area; meanwhile, the pre-charge signal is loaded to the pre-charge unit PCU corresponding to the local refresh area outside by the timing controller TCON, so that the switch element SW corresponding to the local refresh area outside is electrically conducted, at this time, the charge buffered in the buffer capacitor CST corresponding to the local refresh area outside will pre-charge the first row of the sub-pixels outside the local refresh area. Finally, the driving voltage Vdata is loaded to each data line corresponding to the first row of the sub-pixels, to charge the buffer capacitor CST and the first row of the sub-pixels, so as to realize the full-screen refresh. After the driving voltage Vdata is loaded to the first row of the sub-pixels of the full-screen picture, the lock signal is loaded to each pre-charge unit PCU by the timing controller TCON, so that each switch element SW is electrically turned off, to realize buffering the charge in each buffer capacitor CST. Before the display panel PNL displays the next frame of the full-screen picture, the pre-charge signal is loaded to each pre-charge unit PCU, so that each buffer capacitor CST pre-charges the first row of the sub-pixels, and thus the charging speed of the sub-pixels is improved, to improve the display quality of the display panel PNL.

[0109] In an embodiment of the present disclosure, referring to FIG. 5 and FIG. 6, the display panel PNL is configured to cooperate with the timing controller TCON. In this embodiment, the display panel PNL is provided with a source driver SIC. The source driver SIC can receive picture data from the timing controller TCON and drive the display panel PNL according to the picture data. In an example, the source driver SIC can receive full-screen picture data from the timing controller TCON and drive the display panel PNL for full-screen refresh according to the full-screen picture data. In another example, the source driver SIC can receive local picture data from the timing controller TCON and drive the display panel PNL for local refresh according to the local picture data.

[0110] In an embodiment of the present disclosure, referring to FIG. 5 and FIG. 6, the display panel PNL is configured to cooperate with the timing controller TCON. In this embodiment, the display panel PNL is provided with a plurality of data lines DL arranged along the column direction in the display area AA. At least part of the data lines DL are connected with a pre-charge unit PCU. The control terminal of the pre-charge unit PCU is electrically connected with a pre-charge control trace. The pre-charge control trace is configured to load a pre-charge signal and a lock signal. In this way, by loading the pre-charge signal to the pre-charge control trace, the pre-charge unit PCU can be enabled to perform pre-charge. By loading the lock signal to the pre-charge control trace, the pre-charge unit PCU can be enabled to perform charge caching.

[0111] In an embodiment of the present disclosure, referring to FIG. 6, the pre-charge unit PCU includes a switching element SW and a cache capacitor CST. In this embodiment, the first electrode plate of the cache capacitor CST is electrically connected with the data line DL through the switching element SW, and the second electrode plate of the cache capacitor CST is grounded. The control terminal of the switching element SW is electrically connected with the pre-charge control trace. The switching element SW is configured to be electrically conducted in response to the pre-charge signal. The switching element SW is also configured to be electrically interrupted in response to the lock signal. In other embodiments of the present disclosure, the pre-charge unit PCU can include a plurality of switching elements SW and a plurality of cache capacitors CST.

[0112] In an embodiment of the present disclosure, referring to FIG. 2 and FIG. 5, the control terminal AP is configured to interact with the timing controller TCON. In this embodiment, the control terminal AP is configured to send initial full-screen picture data to the timing controller TCON in the full-screen refresh mode, and send initial local picture data to the timing controller TCON in the local refresh mode.

[0113] In an embodiment of the present disclosure, referring to FIG. 5, the timing controller TCON is further provided with an extraction unit DU. The extraction unit DU is configured to receive the local address information ADP in the first switching mode, and read the local picture data from the last frame of full-screen picture data in the full-screen refresh mode according to the local address information ADP and write the local picture data into the second buffer MU2. Before the timing controller TCON receives the first frame of local picture data in the local refresh mode, the timing controller TCON is configured to drive the display panel PNL to perform local refresh according to the local picture data in the first switching mode in the second buffer MU2. The control terminal AP is further configured to determine whether to perform the first switching mode, and send the local address information ADP of the local refresh area to the timing controller TCON when it is determined to perform the first switching mode. In other words, the control terminal AP sends a switching instruction to the timing controller TCON. For example, the control terminal AP sends a second switching instruction to the timing controller TCON to make the timing controller TCON switch to the full-screen refresh mode. For another example, the control terminal AP sends a first switching instruction to the timing controller TCON to make the timing controller TCON switch to the local refresh mode.

[0114] In an embodiment of the present disclosure, the display device includes a display module and a driving module. Referring to FIGS. 2 and 5, the display module can include a display panel PNL and a source driver SIC. The source driver SIC is disposed in the peripheral region BB of the display panel PNL. The source driver SIC can receive picture data from the timing controller TCON, and generate a driving voltage Vdata according to the picture data to make the display panel PNL display a picture.

[0115] Referring to FIG. 1, the driving module includes a power manager PMIC, a timing controller TCON, a main circuit board MPCB, etc. The power manager PMIC and the timing controller TCON are disposed on the main circuit board MPCB. The main circuit board MPCB is electrically connected with a plurality of chip on film COFs. In this way, the power manager PMIC and the timing controller TCON can load power voltage and signals to the source driver SIC through the main circuit board MPCB and the chip on film COF.

[0116] Referring to FIG. 6, the display panel PNL is provided with a plurality of data lines DL arranged along the column direction in the display area AA. At least part of the data lines DL is connected with a pre-charge unit PCU. The pre-charge unit PCU includes a switch element SW and a buffer capacitor CST. A first electrode plate of the buffer capacitor CST is electrically connected with the switch element SW and the data line DL, and a second electrode plate of the buffer capacitor CST is grounded. A control terminal of the switch element SW is electrically connected with a pre-charge control line. The pre-charge control line is used to load a pre-charge signal and a lock signal. The switch element SW is configured to be electrically conducted in response to the pre-charge signal. The switch element SW is also configured to be electrically interrupted in response to the lock signal. In this way, the switch element SW can be electrically conducted by loading the pre-charge signal to the pre-charge control line. The switch element SW can be electrically interrupted by loading the lock signal to the pre-charge control line.

[0117] Referring to FIG. 5, the timing controller TCON includes a mode selection unit MSU, a first buffer MU1, a second buffer MU2, an image processing unit IPU and an extraction unit DU. The first buffer MU1 is used to store full-screen picture data in the full-screen refresh mode, and the full-screen picture data is used to drive the display panel PNL to perform full-screen refresh. The second buffer MU2 is used to store partial picture data in the partial refresh mode, and the partial picture data is used to drive the display panel PNL to perform partial refresh. The mode selection unit MSU is used to store the full-screen picture data in the first buffer MU1 in the full-screen refresh mode, and is used to store the partial picture data in the second buffer MU2 in the partial refresh mode. The image processing unit IPU is used to receive and process the full-screen picture data sent by the first buffer MU1 in the full-screen refresh mode, and is used to receive and process the initial partial picture data sent by the mode selection unit MSU in the partial refresh mode. The extraction unit DU is used to receive the partial address information ADP, and read the partial picture data from the last frame of full-screen picture data according to the partial address information ADP and write the partial picture data into the second buffer MU2. Before the timing controller TCON receives the first frame of partial picture data, the timing controller TCON is also configured to drive the display panel PNL to perform partial refresh according to the partial picture data in the second buffer MU2.

[0118] The timing controller TCON is also configured to work in the switching mode within one frame of time after receiving the switching instruction, and switch to the full-screen refresh mode or the partial refresh mode after receiving the switching instruction for one frame of time.

[0119] Referring to FIG. 5 and FIG. 6, the timing controller TCON is further configured to, in the full-screen refresh mode, load a pre-charge signal to each of the pre-charge units PCU connected to the data lines DL corresponding to the first row of sub-pixels before and after the driving voltage Vdata is loaded to the first row of sub-pixels to make each of the switch elements SW electrically conductive and non-conductive, respectively.

[0120] Referring to FIG. 5 and FIG. 6, the timing controller TCON is further configured to, in the first switching mode, load a pre-charge signal to each of the pre-charge units PCU connected to the data lines DL corresponding to the first row of sub-pixels in the local refresh area before the driving voltage Vdata is loaded to the first row of sub-pixels to make each of the switch elements SW electrically conductive; and load a lock signal to each of the pre-charge units PCU connected to each of the data lines DL outside the local refresh area to make each of the switch elements SW electrically non-conductive.

[0121] The timing controller TCON is configured to, in the first switching mode, load a lock signal to each of the pre-charge units PCU connected to each of the data lines DL to make each of the switch elements SW electrically non-conductive from when the driving voltage Vdata is loaded to the first row of sub-pixels in the local refresh area until after the driving voltage Vdata is loaded to the first row of sub-pixels.

[0122] Referring to FIG. 5 and FIG. 6, the timing controller TCON is further configured to, in the local refresh mode, load a pre-charge signal to each of the pre-charge units PCU connected to the data lines DL corresponding to the first row of sub-pixels in the local refresh area before and after the driving voltage Vdata is loaded to the first row of sub-pixels to make each of the switch elements SW electrically conductive and non-conductive, respectively. The timing controller TCON is further configured to, in the local refresh mode, load a lock signal to each of the pre-charge units PCU connected to the data lines DL corresponding to the local refresh area after the driving voltage Vdata is loaded to the first row of sub-pixels in the local refresh area to make each of the switch elements SW electrically non-conductive. The timing controller TCON is further configured to, in the local refresh mode, load a lock signal to each of the pre-charge units PCU connected to each of the data lines DL outside the local refresh area to make each of the switch elements SW electrically non-conductive.

[0123] Referring to FIGS. 5 and 6, the timing controller TCON is further configured to, in the second switching mode, after the last row of sub-pixels of the local refresh area is loaded with the driving voltage Vdata, sequentially perform the following processes: first, load the pre-charge signal to each pre-charge unit PCU connected to the data line DL of the local refresh area to make each switch element SW conductive. Then, load the corresponding compensation driving voltage to any data line DL in each local refresh area. The driving compensation voltage of the data line DL is the driving voltage determined according to the compensation data of the data line DL. The compensation data of the data line DL is the data of the sub-pixel connected to the data line DL in the first row of sub-pixels of the display panel PNL in the first buffer MU1.

[0124] Next, the working principles of the full-screen refresh mode, the switching mode and the local refresh mode of the present disclosure are described from two aspects of the timing controller TCON and the display panel PNL.

[0125] On the one hand, for the timing controller TCON, referring to FIGS. 6 and 7, in the full-screen refresh mode, the mode selection unit MSU stores the initial full-screen picture data as the full-screen picture data in the first buffer MU1, the full-screen picture data of the last frame in the first buffer MU1 is sent to the source driver SIC after image processing by the image processing unit IPU, the source driver SIC generates the driving voltage Vdata according to the received full-screen picture data, and finally loads the driving voltage Vdata to the data line DL of the display panel PNL for full-screen refresh of the display panel PNL.

[0126] In the first switching mode, referring to FIGS. 6 and 8, the extraction unit DU receives the local address information ADP, and reads the local picture data from the full-screen picture data of the last frame in the full-screen refresh mode according to the local address information ADP and stores the local picture data in the second buffer MU2, the local picture data stored in the second buffer MU2 drives the display panel PNL to perform local refresh. At this time, the resolution and frame rate are switched. Since the first switching mode can display the local picture of the last frame of the full-screen picture, the switching between the full-screen refresh mode and the local refresh mode can be smoothly and smoothly, and there is no situation of frame freezing and frame dropping.

[0127] In the local refresh mode, referring to FIGS. 6 and 9, the mode selection unit MSU stores the initial local picture data as the local picture data in the second buffer MU2 after image processing by the image processing unit IPU, the local picture data of the last frame in the second buffer MU2 is sent to the source driver SIC, the source driver SIC generates the driving voltage Vdata according to the received local picture data, and finally loads the driving voltage Vdata to the data line DL of the display panel PNL for local refresh of the display panel PNL.

[0128] In the second switching mode, referring to FIG. 6 and FIG. 10, the timing controller TCON receives the second switching instruction, and the timing controller TCON still outputs the last frame of partial picture data in the partial refresh mode to drive the display panel PNL to display the partial picture, while the resolution and frame rate are switched. Since in the second switching mode, the display panel PNL still displays the partial picture to achieve smooth switching from the partial refresh mode to the full-screen refresh mode, there is no frame drop and flicker, and the display quality of the display panel is improved.

[0129] On the other hand, for the display panel PNL, in the full-screen refresh mode, referring to FIG. 6, before the driving voltage Vdata is loaded to the first row of sub-pixels, the timing controller TCON loads the pre-charge signal to the pre-charge unit PCU, so that the switch element SW is electrically conducted, at this time, the charge stored in the cache capacitor CST will pre-charge the first row of sub-pixels of the display panel PNL; then the driving voltage Vdata is loaded to the first row of sub-pixels, and the cache capacitor CST is charged at the same time; when the first row of sub-pixels is loaded with the driving voltage Vdata, the timing controller TCON loads the lock signal to the pre-charge unit PCU, so that the switch element SW is electrically disconnected, and the charge is cached to the cache capacitor CST. Before the display panel PNL displays the next frame of full-screen picture, the above steps are repeated to pre-charge the first row of sub-pixels, which facilitates to improve the charging speed of the sub-pixel, and to improve the display quality of the display panel PNL.

[0130] In the first switching mode, referring to FIG. 6, the display panel PNL displays a partial picture of the last full-screen picture in the full-screen refresh mode, so that the full-screen refresh mode and the partial refresh mode can be smoothly switched. The specific working process is as follows (since the partial picture data in the first switching mode is extracted from the last full-screen picture data in the full-screen refresh mode, the working process is similar to that in the full-screen refresh mode, but the cache capacitor CST of the partial refresh area does not store the driving voltage Vdata of the first row of sub-pixels in the partial refresh mode in advance): Before the driving voltage Vdata is loaded to the first row of sub-pixels in the partial refresh area in the first switching mode, the timing controller TCON first loads the pre-charge signal to the pre-charge unit PCU corresponding to the partial refresh area, so that the switch element SW corresponding to the partial refresh area is electrically connected, at this time, the charge stored in the cache capacitor CST corresponding to the partial refresh area will pre-charge the first row of sub-pixels of the display panel PNL, so as to improve the charging rate of the sub-pixels. After the charge in the cache capacitor CST is released, the pre-charge unit PCU of the partial refresh area is loaded with the lock signal, so that the switch element SW of the partial refresh area is electrically disconnected. Then when the driving voltage Vdata is loaded to the first row of sub-pixels in the partial refresh area in the first switching mode, the lock signal is loaded to the pre-charge unit PCU corresponding to the partial refresh area, so that the switch element SW corresponding to the partial refresh area is electrically disconnected, and the cache capacitor CST of the partial refresh area is not charged, because the driving voltage Vdata in the full-screen refresh mode and the partial refresh mode is different, and the cache capacitor CST of the partial refresh area is charged in this process, which will cause the phenomenon of data mismatch, affecting the display quality of the display panel PNL. However, in the first switching mode, the pre-charge unit PCU corresponding to the partial refresh area needs to be continuously loaded with the lock signal, so that the switch element SW outside the partial refresh area is continuously electrically disconnected, so as to store the voltage in the full-screen refresh mode in the cache capacitor CST outside the partial refresh area. When the partial refresh mode switches back to the full-screen refresh mode, in order to pre-charge the first row of sub-pixels of the first full-screen picture and improve the charging rate of the sub-pixels.

[0131] In the partial refresh mode, referring to FIG. 11, before the driving voltage Vdata is loaded to the first row of sub-pixels of the partial refresh area, the timing controller TCON loads a pre-charge signal to the pre-charge unit PCU connected to the data line DL corresponding to the partial refresh area, so that the switch element SW is electrically conducted, at this time, the charge stored in the cache capacitor CST will pre-charge the first row of sub-pixels of the partial refresh area; at the same time, the timing controller TCON loads a lock signal to the pre-charge unit PCU connected to the data line DL outside the partial refresh area, so that the switch element SW is electrically disconnected. Then the driving voltage Vdata is loaded to the first row of sub-pixels of the partial refresh area, and at the same time, the cache capacitor CST corresponding to the partial refresh area is charged. When the driving voltage Vdata is loaded to the first row of sub-pixels, the timing controller TCON loads a lock signal to the pre-charge unit PCU corresponding to the partial refresh area, so that the switch element SW of the partial refresh area is electrically disconnected, and the charge is cached to the cache capacitor CST of the partial refresh area. Before the display panel PNL displays the next frame of partial picture in the partial refresh mode, the above steps are repeated to pre-charge the first row of sub-pixels of the partial refresh area, so as to improve the charging speed of the sub-pixels and improve the display quality of the display panel PNL.

[0132] In the second switching mode, referring to FIG. 5 and FIG. 6, the timing controller TCON receives a second switching instruction, and the display panel PNL still displays the last frame of partial picture in the partial refresh mode. The specific working process is the same as that in the partial refresh mode.

[0133] When the timing controller TCON switches from the local refresh mode to the full-screen refresh mode, after the display panel PNL displays the last row of sub-pixels of the local picture in the second switching mode, before the timing controller TCON loads the driving voltage Vdata to the first row of sub-pixels of the full-screen picture of the first frame, the timing controller TCON loads the pre-charge signal to the pre-charge unit PCU corresponding to the local refresh area, so that the switch element SW corresponding to the local refresh area is electrically conducted, thereby the buffer capacitor CST corresponding to the local refresh area is discharged (at this time, the scanning signal of the gate drive circuit is not loaded to the first row of sub-pixels, so that the first row of sub-pixels is not charged), after the buffer capacitor CST corresponding to the local refresh area is discharged, the compensation driving voltage of the first row of sub-pixels of the full-screen picture of the first frame is inserted, so that the compensation driving voltage is buffered in the buffer capacitor CST, and the compensation driving voltage is stored in the first buffer MU1. Then the timing controller TCON loads the pre-charge signal to the pre-charge unit PCU corresponding to the local refresh area, so that the switch element SW corresponding to the local refresh area is electrically conducted, at this time, the compensation driving voltage buffered in the buffer capacitor CST corresponding to the local refresh area will pre-charge the first row of sub-pixels of the local refresh area; at the same time, the timing controller TCON loads the pre-charge signal to the pre-charge unit PCU corresponding to the area outside the local refresh area, so that the switch element SW corresponding to the area outside the local refresh area is electrically conducted, at this time, the charge buffered in the buffer capacitor CST corresponding to the area outside the local refresh area will pre-charge the first row of sub-pixels of the area outside the local refresh area. Finally, the driving voltage Vdata is loaded to each data line corresponding to the first row of sub-pixels, to charge the buffer capacitor CST and the first row of sub-pixels, so as to realize the full-screen refresh. When the driving voltage Vdata is loaded to the first row of sub-pixels of the full-screen picture, the timing controller TCON loads the lock signal to each pre-charge unit PCU, so that each switch element SW is electrically turned off, to buffer the charge in each buffer capacitor CST. Before the display panel PNL displays the next frame of the full-screen picture, the pre-charge signal is loaded to each pre-charge unit PCU, so as to pre-charge the first row of sub-pixels by each buffer capacitor CST, thereby the charging speed of the sub-pixels is improved, so as to improve the display quality of the display panel PNL.

[0134] Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the features disclosed herein. It is intended that the specification and examples be considered as exemplary only, with the true scope and spirit of the disclosure being indicated by the following claims.

Claims

1. A timing controller, wherein, The timing controller comprises a first buffer and a second buffer; The timing controller is configured to, in a full-screen refresh mode, enable the first buffer to store full-screen picture data and drive the display panel to perform full-screen refresh according to the full-screen picture data; The timing controller is further configured to, in a local refresh mode and a switching mode, enable the second buffer to store local picture data and drive the display panel to perform local refresh according to the local picture data.

2. The timing controller of claim 1, wherein, The timing controller is configured to, in the full-screen refresh mode, receive initial full-screen picture data and store the initial full-screen picture data in the first buffer directly; The timing controller is further configured to, in the local refresh mode, receive initial local picture data and store the initial local picture data in the second buffer after processing.

3. The timing controller of claim 1, wherein, The timing controller further comprises a mode selection unit; The mode selection unit is used to enable the full-screen picture data to be stored in the first buffer in the full-screen refresh mode, and is used to enable the local picture data to be stored in the second buffer in the local refresh mode.

4. The timing controller of claim 1, wherein, The timing controller is further configured to, in the switching mode, work within one frame time after receiving a switching instruction, and switch to the full-screen refresh mode or the local refresh mode after one frame time of receiving the switching instruction.

5. The timing controller of claim 1, wherein, The timing controller is further provided with an extraction unit; the switching mode comprises a first switching mode; the timing controller is in the full-screen refresh mode at one frame time before the first switching mode; The extraction unit is configured to, in the first switching mode, receive local address information, acquire local picture data from the full-screen picture data stored in the first buffer according to the local address information, and store the local picture data in the second buffer; The timing controller is configured to, in the first switching mode, drive the display panel according to the local picture data provided by the extraction unit to the second buffer, and switch to the local refresh mode at one frame time after the first switching mode.

6. The timing controller of claim 1, wherein, The switching mode comprises a second switching mode; the timing controller is in the local refresh mode at one frame time before the second switching mode; The timing controller is configured to, in the second switching mode, drive the display panel according to the local picture data in the second buffer, and switch to the full-screen refresh mode at one frame time after the second switching mode.

7. The timing controller of claim 1, wherein, The timing controller is further configured to, in the full-screen refresh mode, load a pre-charging signal to each pre-charging unit to enable each switch element to be electrically conducted before a driving voltage is loaded to a first row of sub-pixels until after the driving voltage is loaded to the first row of sub-pixels. ​ The timing controller is further configured to, in the full-screen refresh mode, continuously load a lock signal to each of the pre-charge units connected to the data line of the first row of sub-pixels after the driving voltage is loaded to the first row of sub-pixels, so that each of the switch elements is electrically turned off.

8. The timing controller of claim 1, wherein, The display panel is driven; at least part of the data lines of the display panel is connected with a pre-charge unit; the pre-charge unit comprises a buffer capacitor and a switch element, and the buffer capacitor is electrically connected with the data line through the switch element; The switching mode comprises a first switching mode; the timing controller is in the full-screen refresh mode at a frame time before the first switching mode; The timing controller is configured to, in the first switching mode, load a pre-charge signal to each of the pre-charge units connected to the data line of the local refresh area before the driving voltage is loaded to the first row of sub-pixels of the local refresh area, so that each of the switch elements is electrically turned on; and continuously load a lock signal to each of the pre-charge units connected to each of the data lines outside the local refresh area, so that each of the switch elements is electrically turned off. The timing controller is configured to, in the first switching mode, continuously load a lock signal to each of the pre-charge units connected to each of the data lines from when the driving voltage is loaded to the first row of sub-pixels of the local refresh area until after the driving voltage is loaded to the first row of sub-pixels, so that each of the switch elements is electrically turned off.

9. The timing controller of claim 1, wherein, The display panel is driven; at least part of the data lines of the display panel is connected with a pre-charge unit; the pre-charge unit comprises a buffer capacitor and a switch element, and the buffer capacitor is electrically connected with the data line through the switch element; The switching mode comprises a second switching mode; the timing controller is in the local refresh mode at a frame time before the second switching mode; The timing controller is configured to, in the local refresh mode and the second switching mode, load a pre-charge signal to each of the pre-charge units connected to the data line of the local refresh area before the driving voltage is loaded to the first row of sub-pixels of the local refresh area until after the driving voltage is loaded to the first row of sub-pixels, so that each of the switch elements is electrically turned on; The timing controller is further configured to, in the local refresh mode and the second switching mode, continuously load a lock signal to each of the pre-charge units connected to the data line of the local refresh area after the driving voltage is loaded to the first row of sub-pixels of the local refresh area, so that each of the switch elements is electrically turned off; The timing controller is further configured to, in the second switching mode, sequentially perform the following processes after the driving voltage is loaded to the last row of sub-pixels of the local refresh area:

10. The timing controller of claim 9, wherein, First, load a pre-charge signal to each of the pre-charge units connected to the data line of the local refresh area, so that each of the switch elements is electrically turned on; ​ Then a corresponding compensation driving voltage is loaded to any one of the data lines in each local refresh area; the driving compensation voltage of the data line is a driving voltage determined according to compensation data of the data line; the compensation data of the data line is data of a sub-pixel connected with the data line in a first row of sub-pixels of the display panel in the first buffer.

11. A control terminal for interacting with a timing controller as claimed in any one of claims 1 to 10; wherein, The control terminal is configured to send initial full-screen picture data to the timing controller in the full-screen refresh mode, and send initial local picture data to the timing controller in the local refresh mode.

12. The control terminal according to claim 11, wherein, The timing controller is further provided with an extraction unit; the extraction unit is configured to receive local address information in a first switching mode, and read local picture data from the last frame of full-screen picture data in the full-screen refresh mode according to the local address information and write the local picture data into a second buffer; Before the timing controller receives the first frame of local picture data in the local refresh mode, the timing controller is configured to drive the display panel to perform local refresh according to the local picture data in the first switching mode in the second buffer; The control terminal is further configured to determine whether to perform the first switching mode; when it is determined to perform the first switching mode, send local address information of a local refresh area to the timing controller.

13. A display panel for use with the timing controller of any one of claims 1 to 10; wherein, The display panel has a source driver; the source driver can receive picture data from the timing controller and drive the display panel according to the picture data.

14. A display panel for use with the timing controller of any one of claims 1 to 10; wherein, The display panel is provided with a plurality of data lines arranged in a column direction in a display area; at least part of the data lines are connected with a pre-charging unit; a control end of the pre-charging unit is electrically connected with a pre-charging control trace; the pre-charging control trace is used to load a pre-charging signal and a lock signal.

15. The display panel of claim 14, wherein, The pre-charging unit includes a switching element and a buffer capacitor; The first electrode plate of the buffer capacitor is electrically connected with the data line through the switching element, and the second electrode plate of the buffer capacitor is grounded; The control end of the switching element is electrically connected with the pre-charging control trace; the switching element is configured to be electrically conducted in response to the pre-charging signal; The switching element is further configured to be electrically disconnected in response to the lock signal.

16. A display device comprising: The timing controller includes any one of claims 1-10; And / or, the display panel includes any one of claims 13-15.

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