Semiconductor device and method for producing same

Abstract

This semiconductor device is provided with a first semiconductor chip (101) and a second semiconductor chip (102) that is thinner than the first semiconductor chip (101). The first semiconductor chip (101) is provided with a first substrate integrated waveguide (121) that is composed of a plurality of through-substrate vias (101a). The second semiconductor chip (102) is provided with a second substrate integrated waveguide (122) that is composed of a plurality of through-substrate vias (102a). An on-chip resin layer (103) is formed on the second semiconductor chip (102). The on-chip resin layer (103) has the same thickness as the difference in thickness between the first semiconductor chip (101) and the second semiconductor chip (102).

Description

Semiconductor device and manufacturing method thereof

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof.

[0002] In recent years, there has been remarkable progress in the data rates of mobile communications. While the maximum data rate of the fifth-generation mobile communications system (5G), which was commercially introduced in 2020, is approximately 10 Gb / s, Beyond 5G communications, which are expected to be introduced in the 2030s, require data rates of 100 Gb / s to 1 Tb / s. To achieve such high data rates, the use of broadband millimeter waves and terahertz waves is expected. However, the use of millimeter waves and terahertz waves faces many challenges, one of which is the significant propagation loss in transmission lines.

[0003] Given this background, the use of substrate integrated waveguides (SIWs) has been attracting attention in the high-frequency region, particularly in the terahertz band, for the purpose of reducing propagation loss in transmission lines on integrated substrates (see Non-Patent Document 1). A substrate integrated waveguide is a transmission line in which through-substrate vias (TSVs) are densely formed within a semiconductor substrate. For example, a common configuration involves forming through-substrate vias within a semiconductor substrate at a density of at least one-fourth the wavelength of the propagating signal. In a substrate integrated waveguide, the propagating signal propagates within the substrate in a waveguide mode (TE or TM mode), which has the advantage of suppressing radiation loss even in the terahertz region.

[0004] Typically, as shown in Figures 8A to 8C, a method of connecting semiconductor chips on which substrate integrated waveguides are formed can be considered. A first semiconductor chip 301 and a second semiconductor chip 302 on which substrate integrated waveguides are formed each have a top-surface ground and a bottom-surface ground, and are assumed to have the same thickness. The first semiconductor chip 301 and the second semiconductor chip 302 are mounted on a common back-surface metal layer 303 with their bottom-surface grounds facing toward each other. In addition, a bridge metal layer 304 is formed so as to span the top-surface grounds of the first semiconductor chip 301 and the second semiconductor chip 302. A physical space (L g) are opened and aligned so that the propagation directions of the electromagnetic waves in each substrate integrated waveguide are aligned.

[0005] According to this connection structure, L g By shortening the length of L (approximately one-fourth of the signal wavelength or less), it is possible to suppress connection loss even in the terahertz region from the first semiconductor chip 301 to the second semiconductor chip 302. This connection loss is caused by L g The larger is, the greater the increase.

[0006] The second semiconductor chip 302 is disposed on the right side of the first semiconductor chip 301 (FIG. 8C). g is set to four levels (25 μm, 50 μm, 100 μm, 300 μm), and the pass loss S21 from the left side of the first semiconductor chip 301 to the right end of the second semiconductor chip 302 is calculated in the range from 250 GHz to 350 GHz. The results are shown in FIG. g It can be seen that the larger the L, the greater the insertion loss and the worse the characteristics. g The calculation result for φ=300 μm is significantly worse. This deterioration in characteristics is due to the signal leaking from the side of the semiconductor chip when the signal propagates from the substrate integrated waveguide of first semiconductor chip 301 to the substrate integrated waveguide of second semiconductor chip 302.

[0007] The setting conditions for the electromagnetic field simulation described above are as follows: The substrate material of the first semiconductor chip 301 and the second semiconductor chip 302 was made of InP, a compound semiconductor that is often used in the terahertz band. The relative dielectric constant of InP was set to 12.6. The space between the first semiconductor chip 301 and the second semiconductor chip 302 was set to air (relative dielectric constant 1). All metal materials used in the electromagnetic field simulation, such as through-substrate vias and top-surface ground, were set to Au, with a conductivity of 41×10 6 S / m.

[0008] The lengths of the first semiconductor chip 301 and the second semiconductor chip 302 in the signal propagation direction were set to L1 = 1000 μm and L2 = 1000 μm, respectively. All of the through-substrate vias were cylindrical with a diameter of 20 μm, and the pitch L v1 , L v2was set to 50 μm. The pitches W1 and W2 of the through-substrate vias in the direction perpendicular to the signal propagation direction were both set to 200 μm. The thicknesses of the first semiconductor chip and the second semiconductor chip were set to 50 μm. Note that the thickness of each metal layer (back metal layer, bridge metal layer, top ground, and bottom ground) was set to 2 μm, but from the perspective of shielding signals (electromagnetic waves), the size of this value does not affect the calculation results as long as the thickness is equal to or greater than the skin depth.

[0009] D. Deslandes and K. Wu, "Integrated Microstrip and Rectangular Waveguide in Planar Form", IEEE Microwave and Wireless Components Letters, vol. 11, no. 2, pp. 68-70, 2001.

[0010] As described above, conventional connection methods can suppress an increase in connection loss by reducing the distance between two semiconductor chips, but they have the following problems. When the first semiconductor chip and the second semiconductor chip have different thicknesses, it is difficult to form a bridge metal layer. When the two semiconductor chips have the same thickness, a connection structure can be easily achieved by fixing a rectangular parallelepiped metal structure to the top ground of each semiconductor chip using silver paste or the like. However, when the thicknesses are different, it is difficult to arrange the bridge metal layer. Thus, when the thicknesses of two semiconductor chips on which substrate integrated waveguides are formed are different, it is difficult to connect the two.

[0011] The present invention has been made to solve the above problems, and has as its object to easily connect two semiconductor chips having different thicknesses on which substrate integrated waveguides are formed.

[0012] A semiconductor device according to the present invention includes a first semiconductor chip on which a first substrate integrated waveguide is formed, a second semiconductor chip thinner than the first semiconductor chip on which a second substrate integrated waveguide is formed, an on-chip resin layer formed on the second semiconductor chip and having a thickness equal to the difference in thickness between the first semiconductor chip and the second semiconductor chip, a laminated structure of the second semiconductor chip and the on-chip resin layer, an inter-chip resin layer formed to fill the gap between the first semiconductor chip, a first metal layer formed from the top surface of the first semiconductor chip to the top surface of the on-chip resin layer and connected to a first ground layer on the top surface of the first semiconductor chip, and a first semiconductor layer of the second semiconductor chip. The semiconductor device comprises a connecting metal layer that connects the second ground layer on the upper surface of the chip side end to the first metal layer, and a second metal layer that is formed from the lower surface of the first semiconductor chip to the lower surface of the second semiconductor chip and connects the third ground layer on the lower surface of the first semiconductor chip to the fourth ground layer on the lower surface of the second semiconductor chip, the first semiconductor chip and the second semiconductor chip being arranged so that the electromagnetic wave propagation directions of the first substrate integrated waveguide and the second substrate integrated waveguide are aligned, and the connecting metal layer exists over a width that is larger than the pitch in a direction perpendicular to the electromagnetic wave propagation direction of the through-substrate vias that constitute the first substrate integrated waveguide and the second substrate integrated waveguide.

[0013] Furthermore, a semiconductor device according to the present invention includes a first semiconductor chip on which a first substrate integrated waveguide is formed, a second semiconductor chip thinner than the first semiconductor chip on which a second substrate integrated waveguide is formed, a connection metal layer formed on the second semiconductor chip to cover a region where the second substrate integrated waveguide is formed and having the same thickness as the difference in thickness between the first semiconductor chip and the second semiconductor chip, a first metal layer formed from an upper surface of the first semiconductor chip to an upper surface of the connection metal layer and connected to a first ground layer and the connection metal layer on the upper surface of the first semiconductor chip, a stacked structure of the second semiconductor chip and the first metal layer, and the first semiconductor chip. and a second metal layer formed from the underside of the first semiconductor chip to the underside of the second semiconductor chip, connecting a third ground layer on the underside of the first semiconductor chip to a fourth ground layer on the underside of the second semiconductor chip, wherein the first semiconductor chip and the second semiconductor chip are arranged so that the electromagnetic wave propagation directions of the first substrate integrated waveguide and the second substrate integrated waveguide coincide with each other, and the connecting metal layer exists over a width greater than the pitch in a direction perpendicular to the electromagnetic wave propagation direction of the through-substrate vias that constitute the first substrate integrated waveguide and the second substrate integrated waveguide.

[0014] A method for manufacturing a semiconductor device according to the present invention includes a first step of mounting, on a carrier substrate, a first semiconductor chip having a first substrate integrated waveguide formed thereon and a second semiconductor chip having a second substrate integrated waveguide formed thereon and being thinner than the first semiconductor chip; a second step of forming a molded resin layer to cover the first semiconductor chip and the second semiconductor chip mounted on the carrier substrate; a third step of thinning the molded resin layer to expose a first ground layer on the upper surface of the first semiconductor chip; a fourth step of forming a through hole in the molded resin layer that reaches the upper surface of the end of the second semiconductor chip on the first semiconductor chip side; a fifth step of filling the through hole formed in the molded resin layer with metal to connect to the second ground layer on the upper surface of the end of the second semiconductor chip on the first semiconductor chip side and to form a connecting metal layer that reaches the upper surface of the thinned molded resin layer; and a fifth step of forming a first metal layer that connects to the first ground layer on the upper surface of the first semiconductor chip from the upper surface of the first semiconductor chip onto the molded resin layer above the second semiconductor chip. and an eighth step of forming a second metal layer from the underside of the first semiconductor chip to the underside of the second semiconductor chip and connecting a third ground layer on the underside of the first semiconductor chip to a fourth ground layer on the underside of the second semiconductor chip by the second metal layer. The first semiconductor chip and the second semiconductor chip are arranged so that the electromagnetic wave propagation directions of the first substrate integrated waveguide and the second substrate integrated waveguide coincide with each other. From the molded resin layer, there are formed an on-chip resin layer that is formed on the second semiconductor chip and has the same thickness as the difference in thickness between the first semiconductor chip and the second semiconductor chip, and an inter-chip resin layer that is formed so as to fill the gap between the stacked structure of the second semiconductor chip and the on-chip resin layer and the first semiconductor chip. The connecting metal layer is formed over a width that is larger than the pitch in a direction perpendicular to the electromagnetic wave propagation direction of the through-substrate vias that constitute the first substrate integrated waveguide and the second substrate integrated waveguide.

[0015] Furthermore, a method for manufacturing a semiconductor device according to the present invention includes a first step of mounting a first semiconductor chip on a carrier substrate, the first semiconductor chip having a first substrate integrated waveguide formed thereon, and a second semiconductor chip having a second substrate integrated waveguide formed thereon and thinner than the first semiconductor chip, with a connection metal layer having a thickness equal to the difference in thickness between the first and second semiconductor chips stacked thereon; a second step of forming a molded resin layer to cover the first semiconductor chip mounted on the carrier substrate and the second semiconductor chip on which the connection metal layer is stacked; a third step of thinning the molded resin layer to expose a first ground layer on the top surface of the first semiconductor chip and an upper surface of the connection metal layer; and a third step of forming a first metal layer connected to the first ground layer on the top surface of the first semiconductor chip from the top surface of the first semiconductor chip to the upper surface of the connection metal layer, the first metal layer and a fourth step of connecting the connecting metal layer to the first semiconductor chip; a fifth step of removing the carrier substrate; and a sixth step of forming a second metal layer from the underside of the first semiconductor chip to the underside of the second semiconductor chip and connecting the third ground layer on the underside of the first semiconductor chip to the fourth ground layer on the underside of the second semiconductor chip with the second metal layer, wherein the first semiconductor chip and the second semiconductor chip are arranged so that the electromagnetic wave propagation directions of the first substrate integrated waveguide and the second substrate integrated waveguide coincide with each other, and an inter-chip resin layer is formed from the molded resin layer so as to fill the gap between the second semiconductor chip and the stacked structure of the second semiconductor chip and the connecting metal layer, and the first semiconductor chip, and the connecting metal layer is formed over a width greater than the pitch in a direction perpendicular to the electromagnetic wave propagation direction of the through-substrate vias that constitute the first substrate integrated waveguide and the second substrate integrated waveguide.

[0016] As described above, according to the present invention, a chip-mounted resin layer having a thickness equal to the difference in thickness between the first semiconductor chip and the second semiconductor chip is provided on the second semiconductor chip, thereby making it possible to easily connect two semiconductor chips having different thicknesses on which substrate-integrated waveguides are formed.

[0017] FIG. 1A is a perspective view showing a configuration of a semiconductor device according to a first embodiment of the present invention. FIG. 1B is a cross-sectional view showing a configuration of the semiconductor device according to the first embodiment of the present invention. FIG. 1C is a plan view showing a partial configuration of the semiconductor device according to the first embodiment of the present invention. FIG. 2 is a characteristic diagram showing a difference in transmission loss between a first semiconductor chip 101 and a second semiconductor chip 102 depending on whether a connection metal layer 106 is present (solid line) or not (dotted line). FIG. 3A is a cross-sectional view showing a state of a semiconductor device in an intermediate step for explaining a manufacturing method of a semiconductor device according to the first embodiment of the present invention. FIG. 3B is a cross-sectional view showing a state of a semiconductor device in an intermediate step for explaining a manufacturing method of a semiconductor device according to the first embodiment of the present invention. FIG. 3C is a cross-sectional view showing a state of a semiconductor device in an intermediate step for explaining a manufacturing method of a semiconductor device according to the first embodiment of the present invention. FIG. 3D is a cross-sectional view showing a state of a semiconductor device in an intermediate step for explaining a manufacturing method of a semiconductor device according to the first embodiment of the present invention. FIG. 3E is a cross-sectional view showing a state of a semiconductor device in an intermediate step for explaining a manufacturing method of a semiconductor device according to the first embodiment of the present invention. FIG. 3F is a plan view showing a state of a semiconductor device in an intermediate step for explaining a manufacturing method of a semiconductor device according to the first embodiment of the present invention. FIG. 3G is a cross-sectional view showing a state of a semiconductor device in an intermediate step for explaining a manufacturing method of a semiconductor device according to the first embodiment of the present invention. FIG. 3H is a plan view showing a state of a semiconductor device in an intermediate process for explaining a method for manufacturing a semiconductor device according to embodiment 1 of the present invention. FIG. 3I is a cross-sectional view showing a state of a semiconductor device in an intermediate process for explaining a method for manufacturing a semiconductor device according to embodiment 1 of the present invention. FIG. 3J is a cross-sectional view showing a state of a semiconductor device in an intermediate process for explaining a method for manufacturing a semiconductor device according to embodiment 1 of the present invention. FIG. 4A is a perspective view showing a configuration of a semiconductor device according to embodiment 2 of the present invention. FIG. 4B is a plan view showing a partial configuration of a semiconductor device according to embodiment 2 of the present invention. FIG. 5A is a perspective view showing a configuration of a semiconductor device according to embodiment 3 of the present invention. FIG. 5B is a plan view showing a partial configuration of a semiconductor device according to embodiment 3 of the present invention. FIG. 6A is a cross-sectional view showing a state of a semiconductor device in an intermediate process for explaining a method for manufacturing a semiconductor device according to embodiment 3 of the present invention.FIG. 6B is a cross-sectional view showing a state of a semiconductor device in an intermediate process for explaining a manufacturing method of a semiconductor device according to a third embodiment of the present invention. FIG. 6C is a cross-sectional view showing a state of a semiconductor device in an intermediate process for explaining a manufacturing method of a semiconductor device according to the third embodiment of the present invention. FIG. 6D is a cross-sectional view showing a state of a semiconductor device in an intermediate process for explaining a manufacturing method of a semiconductor device according to the third embodiment of the present invention. FIG. 6E is a cross-sectional view showing a state of a semiconductor device in an intermediate process for explaining a manufacturing method of a semiconductor device according to the third embodiment of the present invention. FIG. 6F is a cross-sectional view showing a state of a semiconductor device in an intermediate process for explaining a manufacturing method of a semiconductor device according to the third embodiment of the present invention. FIG. 7 is a perspective view showing a configuration of a semiconductor device. FIG. 8A is a perspective view showing a configuration of a conventional semiconductor device. FIG. 8B is a cross-sectional view showing a configuration of a conventional semiconductor device. FIG. 8C is a plan view showing a partial configuration of a conventional semiconductor device. FIG. 9 is a characteristics diagram showing a result of calculating the insertion loss from the left side of a first semiconductor chip 301 to the right end of a second semiconductor chip 302 in a conventional semiconductor device.

[0018] A semiconductor device according to an embodiment of the present invention will be described below.

[0019] 1A, 1B, and 1C, a semiconductor device according to a first embodiment of the present invention will be described. The semiconductor device includes a first semiconductor chip 101 and a second semiconductor chip 102 that is thinner than the first semiconductor chip 101.

[0020] The first semiconductor chip 101 has a first substrate integrated waveguide 121 formed from a plurality of through-substrate vias 101a. The second semiconductor chip 102 has a second substrate integrated waveguide 122 formed from a plurality of through-substrate vias 102a. The first semiconductor chip 101 and the second semiconductor chip 102 are arranged such that the electromagnetic wave propagation directions of the first substrate integrated waveguide 121 and the second substrate integrated waveguide 122 are aligned.

[0021] In addition, an on-chip resin layer 103 is formed on the second semiconductor chip 102. The on-chip resin layer 103 has a thickness equal to the difference in thickness between the first semiconductor chip 101 and the second semiconductor chip 102. The total thickness of the second semiconductor chip 102 and the on-chip resin layer 103 is equal to the thickness of the first semiconductor chip 101.

[0022] Furthermore, an inter-chip resin layer 104 is formed so as to fill the space between the stacked structure of the second semiconductor chip 102 and the on-chip resin layer 103 and the first semiconductor chip 101. The length L of the inter-chip resin layer 104 along the electromagnetic wave propagation direction is g For example, when the relative dielectric constant of the inter-chip resin layer 104 is 4.4 and the signal frequency is 300 GHz, the signal wavelength is about 480 μm, so L g The length L of the inter-chip resin layer 104 along the electromagnetic wave propagation direction can be set to approximately 120 μm or less (120 μm at most). g is the distance between the first semiconductor chip 101 and the second semiconductor chip 102 with the inter-chip resin layer 104 disposed between them.

[0023] For example, the on-chip resin layer 103 and the inter-chip resin layer 104 can be formed from a part of the mold resin layer that molds the first semiconductor chip 101 and the second semiconductor chip 102 .

[0024] Furthermore, a first metal layer 105 is formed from the top surface of the first semiconductor chip 101 to the top surface of the on-chip resin layer 103. The first metal layer 105 is formed on the top surface of the first semiconductor chip 101, the top surface of the inter-chip resin layer 104, and the top surface of the on-chip resin layer 103, which are continuous and form the same plane. The first metal layer 105 is connected to a first ground layer (not shown) on the top surface of the first semiconductor chip 101. The first metal layer 105 is connected by a connection metal layer 106 to a second ground layer (not shown) on the top surface of the end of the second semiconductor chip 102 on the first semiconductor chip 101 side.

[0025] The connection metal layer 106 exists (is formed) over a width larger than the pitch, in a direction perpendicular to the electromagnetic wave propagation direction, of the through-substrate vias that constitute the first substrate integrated waveguide 121 and the second substrate integrated waveguide 122. The connection metal layer 106 may have an outer shape of a rectangular parallelepiped.

[0026] In addition, a second metal layer 107 is formed from the underside of first semiconductor chip 101 to the underside of second semiconductor chip 102. Second metal layer 107 connects a third ground layer (not shown) on the underside of first semiconductor chip 101 to a fourth ground layer (not shown) on the underside of second semiconductor chip 102.

[0027] According to the first embodiment described above, even between semiconductor chips having different thicknesses, low-loss connection in which radiation loss is suppressed is possible.

[0028] Here, we will explain the difference in transmission loss between first semiconductor chip 101 and second semiconductor chip 102 depending on whether or not connecting metal layer 106 is present. Figure 2 shows the results of calculating the transmission loss S21 from the left end of first semiconductor chip 101 to the right end of second semiconductor chip 102 shown in Figure 1C in the range from 250 GHz to 350 GHz for two levels, with and without connecting metal layer 106.

[0029] If the connecting metal layer 106 is not present, electromagnetic waves leak from the inter-chip resin layer 104 through the on-chip resin layer 103, resulting in degradation of the transmission characteristics as shown by the dotted line in Fig. 2. In contrast, if the connecting metal layer 106 is present, leakage of electromagnetic waves is prevented, and degradation of the transmission characteristics does not occur as shown by the solid line in Fig. 2.

[0030] In the above calculations, the substrate material of the first semiconductor chip 101 and the second semiconductor chip 102 was InP, a compound semiconductor that is often used in the terahertz band. The inter-chip resin layer 104 sandwiched between the first semiconductor chip 101 and the second semiconductor chip 102 was made of a general mold resin with a relative dielectric constant of 4.4. All of the metal materials constituting the through-substrate vias, the first ground layer, the second ground layer, the third ground layer, the fourth ground layer, the first metal layer 105, the connection metal layer 106, the second metal layer 107, etc. were Au (conductivity 41×10 6 S / m).

[0031] The lengths of the first semiconductor chip 101 and the second semiconductor chip 102 in the electromagnetic wave propagation direction were set to L1 = 1000 μm and L2 = 1000 μm, respectively. All of the through-substrate vias were cylindrical with a diameter of 20 μm, and the pitch L v1 ,L v2 The pitches W1 and W2 of the through-substrate vias in the transverse direction were set to 200 μm. The thicknesses of the first semiconductor chip 101 and the second semiconductor chip 102 were set to 100 μm and 50 μm, respectively. The length L of the inter-chip resin layer 104 was set to 100 μm. g was set to 50 μm.

[0032] Here, the connecting metal layer 106 exists over a width greater than the pitch in the direction perpendicular to the electromagnetic wave propagation direction of the through-substrate vias that constitute the first substrate integrated waveguide 121 and the second substrate integrated waveguide 122, and thereby serves to reduce the electromagnetic waves that leak from the inter-chip resin layer 104 through the on-chip resin layer 103.

[0033] In addition, the total thickness of the second semiconductor chip 102 and the chip-on-chip resin layer 103, the thickness of the first semiconductor chip 101, and the thickness of the inter-chip resin layer 104 can be made the same, and the first metal layer 105 placed on top of these can be formed thin, while still ensuring mechanical strength.

[0034] Next, a method for manufacturing the semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS. 3A to 3J.

[0035] 3A , a first semiconductor chip 101 having a first substrate integrated waveguide formed thereon and a second semiconductor chip 102 having a second substrate integrated waveguide formed thereon and being thinner than the first semiconductor chip 101 are mounted on a carrier substrate 201 (first step). The first semiconductor chip 101 and the second semiconductor chip 102 are arranged so that the electromagnetic wave propagation directions of the first substrate integrated waveguide and the second substrate integrated waveguide are aligned. The distance between the first semiconductor chip 101 and the second semiconductor chip 102, where an inter-chip resin layer (described later) is formed, is set to be equal to or less than one-fourth of the signal wavelength.

[0036] The carrier substrate 201 can be a Si substrate, a glass substrate, or a metal substrate made of Cu or the like. For example, the first semiconductor chip 101 and the second semiconductor chip 102 can be mounted on the carrier substrate 201 by fixing them to a sacrificial layer (not shown) formed on the carrier substrate 201. For example, each semiconductor chip can be mounted on the carrier substrate 201 by using a chip transfer machine such as a flip-chip bonder.

[0037] As will be described later, the carrier substrate 201 is removed in a subsequent process. Therefore, the sacrificial layer can be made of a material that has adhesive strength when the chip is mounted but that becomes less adhesive when the carrier substrate is peeled off. For example, a sacrificial layer with a thermal peeling function or a UV irradiation peeling function can be used. For example, if the sacrificial layer is irradiated with UV light or laser light through the carrier substrate 201 during this removal, it is important that the carrier substrate 201 is made of a glass material that has a high transmittance for these lights.

[0038] Next, as shown in FIG. 3B , a molded resin layer 202 is formed to cover the first semiconductor chip 101 and the second semiconductor chip 102 mounted on the carrier substrate 201 (second step). For example, the molded resin layer 202 can be formed by compression molding the molded resin using a compression molding device. The molded resin layer 202 can be made of a material with low conductivity. Typically, the molded resin layer 202 can be made of a material containing approximately 90% silica filler, approximately 5% epoxy resin, and other additives.

[0039] Next, the molded resin layer 202 is thinned to expose the first ground layer on the top surface of the first semiconductor chip 101, as shown in FIG. 3C (third step). For example, the molded resin layer 202 can be thinned by grinding it with a back grinder. By thinning the molded resin layer 202, an inter-chip resin layer 104 is formed between the first semiconductor chip 101 and the second semiconductor chip 102, and an on-chip resin layer 103 is formed on the second semiconductor chip 102. Furthermore, the top surfaces of the first semiconductor chip 101, the inter-chip resin layer 104, and the on-chip resin layer 103 form a single plane.

[0040] 3D , through-holes 202a are formed in the mold resin layer 202 (on-chip resin layer 103) (step 4), reaching the top surface of the end of the second semiconductor chip 102 on the side of the first semiconductor chip 101. The through-holes 202a are regions in which the connection metal layer 106 is formed, and are formed over a width wider than the larger of the pitches W1 and W2, in the direction perpendicular to the electromagnetic wave propagation direction, of the through-substrate vias that constitute the first substrate integrated waveguide 121 and the second substrate integrated waveguide 122. For example, the through-holes 202a can be formed by a highly accurate processing method such as laser processing.

[0041] Next, by filling the through holes 202a formed in the molded resin layer 202 with metal, a connection metal layer 106 is formed that connects to the second ground layer on the top surface of the end of the second semiconductor chip 102 on the side of the first semiconductor chip 101 and reaches the top surface of the thinned molded resin layer 202, as shown in Figures 3E and 3F (step 5). For example, the connection metal layer 106 can be formed by filling the through holes 202a with a metal such as Au or Cu using a known plating method. The connection metal layer 106 is formed over a width that is larger than the pitch in the direction perpendicular to the electromagnetic wave propagation direction of the through-substrate vias that constitute the first substrate integrated waveguide 121 and the second substrate integrated waveguide 122.

[0042] Next, as shown in FIGS. 3G and 3H , a first metal layer 105 connected to the first ground layer on the top surface of the first semiconductor chip 101 is formed from the top surface of the first semiconductor chip 101 to the molded resin layer 202 (the top surface of the chip-on-chip resin layer 103) above the second semiconductor chip 102 (step 6). The formed first metal layer 105 connects the first metal layer to the connecting metal layer 106. For example, the first metal layer 105 can be formed by depositing a metal such as Au or Cu using a known plating method. In this way, the first metal layer 105 is formed on the top surfaces of the first semiconductor chip 101, the inter-chip resin layer 104, and the chip-on-chip resin layer 103, which are all continuous and form the same plane, ensuring mechanical strength even when formed thinly.

[0043] Next, the carrier substrate 201 is removed to expose the undersides of the first semiconductor chip 101 and the second semiconductor chip 102, as shown in FIG. 3I (step 7). For example, if a thermally peelable sacrificial layer is used, the carrier substrate 201 can be removed (peeled off) by heating it to a desired temperature with a heater. Also, if a sacrificial layer whose adhesive strength decreases when exposed to UV light is used, the carrier substrate 201 can be peeled off by irradiating the sacrificial layer with UV light of a desired wavelength from the underside of the carrier substrate 201.

[0044] The lower surfaces of first semiconductor chip 101, inter-chip resin layer 104, and second semiconductor chip 102, which were formed on the upper surface of carrier substrate 201, now form the same plane and are continuous.

[0045] 3J, a second metal layer 107 is formed from the underside of the first semiconductor chip 101 to the underside of the second semiconductor chip 102, and the third ground layer on the underside of the first semiconductor chip 101 and the fourth ground layer on the underside of the second semiconductor chip 102 are connected by the second metal layer 107 (step 8). For example, the second metal layer 107 can be formed by depositing a metal such as Au or Cu using a known plating method. In this way, the first metal layer 105 is formed on the underside of the first semiconductor chip 101, the underside of the inter-chip resin layer 104, and the underside of the second semiconductor chip 102, which are all continuous and form the same plane. Therefore, the second metal layer 107 can be formed thinly and still have sufficient mechanical strength.

[0046] By manufacturing as described above, the on-chip resin layer 103 and the inter-chip resin layer 104 can be configured by a part of the molded resin layer 202 that molds the first semiconductor chip 101 and the second semiconductor chip 102 .

[0047] 4A and 4B, a semiconductor device according to a second embodiment of the present invention will be described. This semiconductor device includes a first semiconductor chip 101 and a second semiconductor chip 102 that is thinner than first semiconductor chip 101. This configuration is similar to that of the first embodiment described above.

[0048] The first semiconductor chip 101 has a first substrate integrated waveguide 121 formed from a plurality of through-substrate vias 101a. The second semiconductor chip 102 has a second substrate integrated waveguide 122 formed from a plurality of through-substrate vias 102a. The first semiconductor chip 101 and the second semiconductor chip 102 are arranged such that the electromagnetic wave propagation directions of the first substrate integrated waveguide 121 and the second substrate integrated waveguide 122 are aligned.

[0049] In addition, an on-chip resin layer 103 is formed on the second semiconductor chip 102. The on-chip resin layer 103 has a thickness equal to the difference in thickness between the first semiconductor chip 101 and the second semiconductor chip 102. The total thickness of the second semiconductor chip 102 and the on-chip resin layer 103 is equal to the thickness of the first semiconductor chip 101.

[0050] Furthermore, inter-chip resin layer 104 is formed so as to fill the gap between first semiconductor chip 101 and the stacked structure of second semiconductor chip 102 and on-chip resin layer 103. The length of inter-chip resin layer 104 along the electromagnetic wave propagation direction can be equal to or less than one-fourth of the signal wavelength. Note that the length of inter-chip resin layer 104 along the electromagnetic wave propagation direction is the distance between first semiconductor chip 101 and second semiconductor chip 102, between which inter-chip resin layer 104 is disposed.

[0051] For example, the on-chip resin layer 103 and the inter-chip resin layer 104 can be formed from a part of the mold resin layer that molds the first semiconductor chip 101 and the second semiconductor chip 102 .

[0052] Furthermore, a first metal layer 105 is formed from the top surface of the first semiconductor chip 101 to the top surface of the second semiconductor chip 102. The first metal layer 105 is formed on the top surface of the first semiconductor chip 101, the top surface of the inter-chip resin layer 104, and the top surface of the on-chip resin layer 103, which are continuous and form the same plane. The first metal layer 105 is connected to a first ground layer (not shown) on the top surface of the first semiconductor chip 101. The first metal layer 105 is connected to a second ground layer (not shown) on the top surface of the end of the second semiconductor chip 102 on the first semiconductor chip 101 side by a connection metal layer 106a.

[0053] Connection metal layer 106a exists (is formed) over a width larger than the pitch, in the direction perpendicular to the electromagnetic wave propagation direction, of the through-substrate vias that constitute first substrate integrated waveguide 121 and second substrate integrated waveguide 122. In the second embodiment, connection metal layer 106a is composed of a plurality of through-substrate vias that are formed at a pitch of one-fourth of the signal wavelength or less.

[0054] In addition, a second metal layer 107 is formed from the underside of first semiconductor chip 101 to the underside of second semiconductor chip 102. Second metal layer 107 connects a third ground layer (not shown) on the underside of first semiconductor chip 101 to a fourth ground layer (not shown) on the underside of second semiconductor chip 102.

[0055] In the second embodiment described above, low-loss connection that suppresses radiation loss is also possible even between semiconductor chips of different thicknesses. Note that the semiconductor device according to the second embodiment can be manufactured using the same manufacturing method as the first embodiment described above. In the second embodiment, manufacturing can be carried out by replacing the formation of the connection metal layer 106 described with reference to Figures 3D to 3H with a connection metal layer 106a composed of a plurality of through-substrate vias.

[0056] 5A and 5B, a semiconductor device according to a third embodiment of the present invention will be described. This semiconductor device includes a first semiconductor chip 101 and a second semiconductor chip 102 that is thinner than first semiconductor chip 101. This configuration is similar to that of the first embodiment described above.

[0057] The first semiconductor chip 101 has a first substrate integrated waveguide 121 formed from a plurality of through-substrate vias 101a. The second semiconductor chip 102 has a second substrate integrated waveguide 122 formed from a plurality of through-substrate vias 102a. The first semiconductor chip 101 and the second semiconductor chip 102 are arranged such that the electromagnetic wave propagation directions of the first substrate integrated waveguide 121 and the second substrate integrated waveguide 122 are aligned.

[0058] A connection metal layer 106b is formed on the second semiconductor chip 102. The connection metal layer 106b is formed on the second semiconductor chip 102, covering the region where the second substrate integrated waveguide 122 is formed. The connection metal layer 106b has a thickness equal to the difference in thickness between the first semiconductor chip 101 and the second semiconductor chip 102. The total thickness of the second semiconductor chip 102 and the connection metal layer 106b is equal to the thickness of the first semiconductor chip 101. Note that the side of the connection metal layer 106b opposite to the side on which the first semiconductor chip 101 is disposed and the side perpendicular to the electromagnetic wave propagation direction can be covered with a mold resin layer 103a formed to bury the first semiconductor chip 101 and the second semiconductor chip 102. The connection metal layer 106b can be formed to have the same area as the second semiconductor chip 102.

[0059] Furthermore, inter-chip resin layer 104 is formed so as to fill the gap between first semiconductor chip 101 and the stacked structure of second semiconductor chip 102 and connecting metal layer 106b. The length of inter-chip resin layer 104 along the electromagnetic wave propagation direction can be equal to or less than one-fourth of the signal wavelength. Note that the length of inter-chip resin layer 104 along the electromagnetic wave propagation direction is the distance between first semiconductor chip 101 and second semiconductor chip 102, between which inter-chip resin layer 104 is disposed.

[0060] For example, inter-chip resin layer 104 can be formed by a part of the molding resin layer that molds first semiconductor chip 101 and second semiconductor chip 102 .

[0061] Furthermore, a first metal layer 105 is formed from the top surface of the first semiconductor chip 101 to the top surface of the connection metal layer 106b. The first metal layer 105 is connected to a first ground layer (not shown) on the top surface of the first semiconductor chip 101 and to the connection metal layer 106b. The first metal layer 105 is connected to a second ground layer (not shown) on the top surface of the second semiconductor chip 102 by the connection metal layer 106b.

[0062] The connection metal layer 106b exists (is formed) over a width greater than the pitch, in a direction perpendicular to the electromagnetic wave propagation direction, of the through-substrate vias that constitute the first substrate integrated waveguide 121 and the second substrate integrated waveguide 122. In the third embodiment, the connection metal layer 106b is formed to cover the formation region of the second substrate integrated waveguide 122. The connection metal layer 106b has a thickness equal to the difference in thickness between the first semiconductor chip 101 and the second semiconductor chip 102. The total thickness of the second semiconductor chip 102 and the connection metal layer 106b is equal to the thickness of the first semiconductor chip 101. The connection metal layer 106b may have an outer shape of a rectangular parallelepiped.

[0063] In the third embodiment, the total thickness of the second semiconductor chip 102 and the connecting metal layer 106b, the thickness of the first semiconductor chip 101, and the thickness of the inter-chip resin layer 104 can be made the same. Therefore, the top surface of the first semiconductor chip 101, the top surface of the connecting metal layer 106b, and the top surface of the on-chip resin layer 103 can be made to be continuous and form the same plane. In this way, the first metal layer 105 is formed on the top surfaces of the first semiconductor chip 101, the top surface of the connecting metal layer 106b, and the top surface of the on-chip resin layer 103, which are continuous and form the same plane, so that mechanical strength is ensured even when the first metal layer 105 is formed thin.

[0064] In addition, a second metal layer 107 is formed from the underside of first semiconductor chip 101 to the underside of second semiconductor chip 102. Second metal layer 107 connects a third ground layer (not shown) on the underside of first semiconductor chip 101 to a fourth ground layer (not shown) on the underside of second semiconductor chip 102.

[0065] In the third embodiment described above, low-loss connection that suppresses radiation loss is possible even between semiconductor chips of different thicknesses. Furthermore, according to the third embodiment, the connection metal layer 106b not only prevents leakage of electromagnetic waves but also serves as a heat dissipation path in the second semiconductor chip 102 in place of a resin with low thermal conductivity.

[0066] Next, a method for manufacturing a semiconductor device according to a third embodiment of the present invention will be described with reference to FIGS. 6A to 6F.

[0067] 6A , a first semiconductor chip 101 having a first substrate-integrated waveguide formed thereon is mounted on a carrier substrate 201. Furthermore, a second semiconductor chip 102 having a second substrate-integrated waveguide formed thereon and thinner than the first semiconductor chip 101 is mounted on the carrier substrate 201 with a connection metal layer 106b having a thickness equal to or greater than the difference in thickness between the first semiconductor chip 101 and the second semiconductor chip 102 stacked thereon (first step). For example, a conductive adhesive such as silver paste can be used to mount the connection metal layer 106b on the second semiconductor chip 102.

[0068] The first semiconductor chip 101 and the second semiconductor chip 102 are arranged so that the electromagnetic wave propagation directions of the first substrate integrated waveguide and the second substrate integrated waveguide are aligned. The distance between the first semiconductor chip 101 and the second semiconductor chip 102, where an inter-chip resin layer (described later) is formed, is set to be equal to or less than one-fourth of the signal wavelength.

[0069] The carrier substrate 201 can be a Si substrate, a glass substrate, or a metal substrate made of Cu or the like. For example, the first semiconductor chip 101 and the second semiconductor chip 102 can be mounted on the carrier substrate 201 by fixing them to a sacrificial layer (not shown) formed on the carrier substrate 201. For example, each semiconductor chip can be mounted on the carrier substrate 201 by using a chip transfer machine such as a flip-chip bonder.

[0070] As will be described later, the carrier substrate 201 is removed in a subsequent process. Therefore, the sacrificial layer can be made of a material that has adhesive strength when the chip is mounted but that becomes less adhesive when the carrier substrate is peeled off. For example, a sacrificial layer with a thermal peeling function or a UV irradiation peeling function can be used. For example, if the sacrificial layer is irradiated with UV light or laser light through the carrier substrate 201 during this removal, it is important that the carrier substrate 201 is made of a glass material that has a high transmittance for these lights.

[0071] Next, as shown in FIG. 6B , a molded resin layer 202 is formed to cover the first semiconductor chip 101 mounted on the carrier substrate 201 and the second semiconductor chip 102, which is laminated with the connecting metal layer 106b (second step). For example, the molded resin layer 202 can be formed by compression molding the molded resin using a compression molding device. The molded resin layer 202 can be made of a material with low conductivity. Typically, the molded resin layer 202 can be made of a material containing approximately 90% silica filler, approximately 5% epoxy resin, and other additives.

[0072] 6C , the molded resin layer 202 is thinned to expose the first ground layer and the upper surface of the connection metal layer 106b on the upper surface of the first semiconductor chip 101 (third step). For example, the molded resin layer 202 can be thinned by grinding the molded resin layer 202 with a back grinder. By thinning the molded resin layer 202, an inter-chip resin layer 104 is formed between the first semiconductor chip 101 and the second semiconductor chip 102.

[0073] At this point, the upper surface of connecting metal layer 106b can also be ground to some extent, so that the thickness of connecting metal layer 106b is the same as the difference in thickness between first semiconductor chip 101 and second semiconductor chip 102. In other words, the height of first semiconductor chip 101 and the height of the stacked structure of second semiconductor chip 102 and connecting metal layer 106b can be made the same on carrier substrate 201, and the upper surface of first semiconductor chip 101, the upper surface of inter-chip resin layer 104, and the upper surface of connecting metal layer 106b can form the same plane.

[0074] Next, as shown in FIG. 6D , a first metal layer 105, which connects to the first ground layer on the top surface of the first semiconductor chip 101, is formed from the top surface of the first semiconductor chip 101 to the top surface of the connection metal layer 106b (step 4). The formed first metal layer 105 connects the first metal layer and the connection metal layer 106b. For example, the first metal layer 105 can be formed by depositing a metal such as Au or Cu using a known plating method. In this way, the first metal layer 105 is formed on the top surface of the first semiconductor chip 101, the top surface of the inter-chip resin layer 104, and the top surface of the connection metal layer 106b, which are all continuous and form the same plane, so that mechanical strength is ensured even when the first metal layer 105 is formed thinly.

[0075] Next, the carrier substrate 201 is removed to expose the undersides of the first semiconductor chip 101 and the second semiconductor chip 102, as shown in Fig. 6E (step 5). For example, if a thermally peelable sacrificial layer is used, the carrier substrate 201 can be removed (peeled off) by heating it to a desired temperature with a heater. Also, if a sacrificial layer whose adhesive strength decreases with UV irradiation is used, the carrier substrate 201 can be peeled off by irradiating the sacrificial layer with UV light of a desired wavelength from the underside of the carrier substrate 201.

[0076] The lower surfaces of first semiconductor chip 101, inter-chip resin layer 104, and second semiconductor chip 102, which were formed on the upper surface of carrier substrate 201, now form the same plane and are continuous.

[0077] 6F, a second metal layer 107 is formed from the underside of the first semiconductor chip 101 to the underside of the second semiconductor chip 102, and the third ground layer on the underside of the first semiconductor chip 101 and the fourth ground layer on the underside of the second semiconductor chip 102 are connected by the second metal layer 107 (step 6). For example, the second metal layer 107 can be formed by depositing a metal such as Au or Cu using a known plating method. In this way, the second metal layer 107 formed on the underside of the first semiconductor chip 101, the underside of the inter-chip resin layer 104, and the underside of the second semiconductor chip 102, which are continuous and form the same plane, ensures mechanical strength even when formed thinly.

[0078] By manufacturing as described above, inter-chip resin layer 104 can be formed by a part of mold resin layer 202 that molds first semiconductor chip 101 and second semiconductor chip 102. According to the third embodiment, a semiconductor device can be manufactured with fewer steps than in the first embodiment.

[0079] 7, the semiconductor device may include a first semiconductor chip 101' and a second semiconductor chip 102' having the same thickness as the first semiconductor chip 101'. The first semiconductor chip 101' has a first substrate integrated waveguide 121 formed from a plurality of through-substrate vias 101a. The second semiconductor chip 102' has a second substrate integrated waveguide 122 formed from a plurality of through-substrate vias 102a. The first semiconductor chip 101' and the second semiconductor chip 102' are arranged such that the electromagnetic wave propagation directions of the first substrate integrated waveguide 121 and the second substrate integrated waveguide 122 are aligned.

[0080] This semiconductor device includes an inter-chip resin layer 104 between a first semiconductor chip 101′ and a second semiconductor chip 102′. In this configuration, there is no need to provide a structure on the second semiconductor chip 102′ to make it have the same thickness as the first semiconductor chip 101′.

[0081] A first metal layer 105 is formed on the top surface of first semiconductor chip 101′, the top surface of inter-chip resin layer 104, and the top surface of second semiconductor chip 102′, which are continuous and form the same plane. First metal layer 105 is connected to a first ground layer (not shown) on the top surface of first semiconductor chip 101′ and a second ground layer (not shown) on the top surface of second semiconductor chip 102.

[0082] In addition, a second metal layer 107 is formed from the underside of first semiconductor chip 101 to the underside of second semiconductor chip 102. Second metal layer 107 connects a third ground layer (not shown) on the underside of first semiconductor chip 101 to a fourth ground layer (not shown) on the underside of second semiconductor chip 102.

[0083] The thickness of the first semiconductor chip 101' and the thickness of the second semiconductor chip 102' are the same, and the thickness of these and the inter-chip resin layer 104' can be made the same, and the first metal layer 105 placed on them can be formed thin while still ensuring mechanical strength.

[0084] As described above, according to the embodiment of the present invention, an on-chip resin layer having a thickness equal to the difference in thickness between the first semiconductor chip and the second semiconductor chip is provided on the second semiconductor chip, thereby making it possible to easily connect two semiconductor chips having different thicknesses on which substrate integrated waveguides are formed.

[0085] The first metal layer formed between the first semiconductor chip and the second semiconductor chip can be thin from the perspective of shielding electromagnetic waves. However, because the structure spans the space between the first semiconductor chip and the second semiconductor chip, if there is air between them, it needs to be thick enough to support its own weight and prevent deflection. For this reason, in the past, the first metal layer was formed thick to prevent this deflection. Due to the demand for miniaturization of semiconductor devices and components, it is not desirable to make the first semiconductor layer thicker than necessary. According to the present invention, the first metal layer can be made thinner, thereby preventing the semiconductor device from overheating.

[0086] It should be noted that the present invention is not limited to the embodiments described above, and it is clear that many modifications and combinations can be made by a person having ordinary knowledge in the art within the technical concept of the present invention.

[0087] 101...first semiconductor chip, 101a...through-substrate via, 102...second semiconductor chip, 102a...through-substrate via, 103...resin layer on chip, 104...resin layer between chips, 105...first metal layer, 106...connecting metal layer, 107...second metal layer, 121...first substrate integrated waveguide, 122...second substrate integrated waveguide.

Claims

1. A semiconductor device comprising: a first semiconductor chip on which a first substrate integrated waveguide is formed; a second semiconductor chip thinner than the first semiconductor chip on which a second substrate integrated waveguide is formed; an on-chip resin layer formed on the second semiconductor chip and having a thickness equal to the difference in thickness between the first semiconductor chip and the second semiconductor chip; an inter-chip resin layer formed so as to fill the gap between the stacked structure of the second semiconductor chip and the on-chip resin layer and the first semiconductor chip; a first metal layer formed from the top surface of the first semiconductor chip to the top surface of the on-chip resin layer and connecting to a first ground layer on the top surface of the first semiconductor chip; a connecting metal layer connecting a second ground layer on the top surface of the end of the second semiconductor chip on the first semiconductor chip side and the first metal layer; and a second metal layer formed from the bottom surface of the first semiconductor chip to the bottom surface of the second semiconductor chip and connecting a third ground layer on the bottom surface of the first semiconductor chip and a fourth ground layer on the bottom surface of the second semiconductor chip, a semiconductor device in which the first semiconductor chip and the second semiconductor chip are arranged so that the electromagnetic wave propagation directions of the first substrate integrated waveguide and the second substrate integrated waveguide are aligned, and the connecting metal layer is present over a width greater than the pitch of the through-substrate vias that constitute the first substrate integrated waveguide and the second substrate integrated waveguide in a direction perpendicular to the electromagnetic wave propagation direction.

2. A semiconductor device according to claim 1, wherein said connecting metal layer is composed of a plurality of through-substrate vias formed in said inter-chip resin layer at a pitch of not more than one-fourth of the signal wavelength.

3. A semiconductor device comprising: a first semiconductor chip on which a first substrate integrated waveguide is formed; a second semiconductor chip thinner than the first semiconductor chip on which a second substrate integrated waveguide is formed; a connecting metal layer formed on the second semiconductor chip to cover the forming region of the second substrate integrated waveguide and having a thickness equal to the difference in thickness between the first semiconductor chip and the second semiconductor chip; a first metal layer formed from the upper surface of the first semiconductor chip to the upper surface of the connecting metal layer and connecting to a first ground layer on the upper surface of the first semiconductor chip and the connecting metal layer; an inter-chip resin layer formed to fill the gap between the second semiconductor chip and a stacked structure of the second semiconductor chip and the first metal layer; and a second metal layer formed from the lower surface of the first semiconductor chip to the lower surface of the second semiconductor chip and connecting a third ground layer on the lower surface of the first semiconductor chip and a fourth ground layer on the lower surface of the second semiconductor chip, wherein the first semiconductor chip and the second semiconductor chip are arranged such that the electromagnetic wave propagation directions of the first substrate integrated waveguide and the second substrate integrated waveguide are aligned; A semiconductor device in which the connecting metal layer exists over a width greater than the pitch of the through-substrate vias that constitute the first substrate integrated waveguide and the second substrate integrated waveguide in a direction perpendicular to the electromagnetic wave propagation direction.

4. A semiconductor device according to any one of claims 1 to 3, wherein the length of the inter-chip resin layer along the electromagnetic wave propagation direction is equal to or less than one-fourth of the signal wavelength.

5. A first step of mounting a first semiconductor chip on a carrier substrate, the first semiconductor chip having a first substrate integrated waveguide formed thereon, and a second semiconductor chip having a second substrate integrated waveguide formed thereon and thinner than the first semiconductor chip; a second step of forming a molded resin layer to cover the first semiconductor chip and the second semiconductor chip mounted on the carrier substrate; a third step of thinning the molded resin layer to expose a first ground layer on the top surface of the first semiconductor chip; a fourth step of forming a through hole in the molded resin layer that reaches the top surface of the end of the second semiconductor chip on the side of the first semiconductor chip; and a fifth step of filling the through hole formed in the molded resin layer with metal, connecting to the second ground layer on the top surface of the end of the second semiconductor chip on the side of the first semiconductor chip, and forming a connecting metal layer that reaches the top surface of the thinned molded resin layer. the sixth step of forming a first metal layer connected to a first ground layer on the top surface of the first semiconductor chip from the top surface of the first semiconductor chip onto the molding resin layer above the second semiconductor chip, and connecting the first metal layer and the connecting metal layer; the seventh step of removing the carrier substrate; and the eighth step of forming a second metal layer from the bottom surface of the first semiconductor chip to the bottom surface of the second semiconductor chip, and connecting a third ground layer on the bottom surface of the first semiconductor chip and a fourth ground layer on the bottom surface of the second semiconductor chip with the second metal layer, the first semiconductor chip and the second semiconductor chip being arranged so that the electromagnetic wave propagation directions of the first substrate integrated waveguide and the second substrate integrated waveguide are aligned, and from the molding resin layer, an on-chip resin layer is formed on the second semiconductor chip and has the same thickness as the difference in thickness between the first semiconductor chip and the second semiconductor chip, and an inter-chip resin layer is formed so as to fill the gap between the stacked structure of the second semiconductor chip and the on-chip resin layer and the first semiconductor chip, A method for manufacturing a semiconductor device, wherein the connecting metal layer is formed over a width greater than the pitch of the through-substrate vias that constitute the first substrate integrated waveguide and the second substrate integrated waveguide in a direction perpendicular to the electromagnetic wave propagation direction.

6. A method for manufacturing a semiconductor device according to claim 5, wherein the connecting metal layer is composed of a plurality of through-substrate vias formed at a pitch of one-fourth of the signal wavelength or less.

7. A first step of mounting a first semiconductor chip on a carrier substrate, the first semiconductor chip having a first substrate integrated waveguide formed thereon, and a second semiconductor chip having a second substrate integrated waveguide formed thereon and thinner than the first semiconductor chip, with a connection metal layer having a thickness equal to the difference in thickness between the first and second semiconductor chips stacked thereon; a second step of forming a molded resin layer to cover the first semiconductor chip mounted on the carrier substrate and the second semiconductor chip on which the connection metal layer is stacked; a third step of thinning the molded resin layer to expose a first ground layer on the top surface of the first semiconductor chip and the top surface of the connection metal layer; a fourth step of forming a first metal layer connected to the first ground layer on the top surface of the first semiconductor chip from the top surface of the first semiconductor chip to the top surface of the connection metal layer, and connecting the first metal layer and the connection metal layer; and a fifth step of removing the carrier substrate. a sixth step of forming a second metal layer from the underside of the first semiconductor chip to the underside of the second semiconductor chip, and connecting a third ground layer on the underside of the first semiconductor chip and a fourth ground layer on the underside of the second semiconductor chip with the second metal layer, wherein the first semiconductor chip and the second semiconductor chip are arranged so that the electromagnetic wave propagation directions of the first substrate integrated waveguide and the second substrate integrated waveguide are aligned, and an inter-chip resin layer is formed from the molded resin layer so as to fill the gap between the first semiconductor chip and the connecting metal layer, and the second semiconductor chip, and the connecting metal layer is formed over a width greater than the pitch of through-substrate vias that constitute the first substrate integrated waveguide and the second substrate integrated waveguide in a direction perpendicular to the electromagnetic wave propagation direction.

8. A method for manufacturing a semiconductor device according to any one of claims 5 to 7, wherein the length of the inter-chip resin layer along the electromagnetic wave propagation direction is formed to be equal to or less than one-fourth of the signal wavelength.

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