Comparator and imaging device

Abstract

The purpose of the present invention is to improve the flexibility of a voltage applied to a comparator in a reset phase for balancing differential inputs.　This comparator comprises: a first transistor having a gate to which a first input is applied; a second transistor having a gate to which a second input is applied; a third transistor connected in series to the first transistor; a fourth transistor connected in series to the second transistor and having a gate connected to the gate of the third transistor; a fifth transistor connected to the first transistor and the second transistor; a bias capacitor connected to the gate of the fifth transistor; and a first switching unit that switches the connection of the gates of the third transistor and the fourth transistor between a first bias voltage and the drain of the third transistor.

Description

Comparator and imaging device

[0001] The present technology relates to a comparator and an imaging device. More particularly, the present technology relates to a comparator and an imaging device capable of differential input.

[0002] A comparator is sometimes used to compare input signals. For example, a comparator that compares a pixel signal with a ramp wave in order to perform analog-to-digital (AD) conversion of the pixel signal has been disclosed (see, for example, Patent Document 1).

[0003] Japanese Patent Application Laid-Open No. 2018-148541

[0004] However, in the above-mentioned conventional technology, the power supply voltage of the comparator needs to be higher in the reset phase for balancing the differential input than in the comparison phase, which may lead to an increase in the power supply voltage.

[0005] The present technology was developed in light of this situation and aims to improve the flexibility of the voltage applied to the comparator during the reset phase to balance the differential inputs.

[0006] The present technology has been made to solve the above-mentioned problems, and a first aspect thereof is a comparator including: a first transistor having a gate to which a first input is applied, a second transistor having a gate to which a second input is applied, a third transistor connected in series with the first transistor, a fourth transistor connected in series with the second transistor and having a gate connected to a gate of the third transistor, a fifth transistor connected to the first transistor and the second transistor, a bias capacitor connected to the gate of the fifth transistor, and a first switching unit that switches connections of the gates of the third transistor and the fourth transistor between a first bias voltage and a drain of the third transistor, thereby providing an effect that voltage drops in the third transistor and the fourth transistor are reduced by a threshold voltage of the third transistor and the fourth transistor based on a switching operation of the first switching unit.

[0007] In the first aspect, the semiconductor device may further include a second switching unit that switches the connection between the gate of the fifth transistor and the drain of the first transistor or the second transistor, thereby providing an effect that when the gate of the fifth transistor is disconnected from the drain of the first transistor or the second transistor, the gate voltage of the fifth transistor is set based on the bias voltage generated by the bias capacitor.

[0008] In the first aspect, the first switching unit may include a first switch that switches the input of a first bias voltage to the gate of the third transistor and a second switch that switches the connection between the gate and the drain of the third transistor, and the second switching unit may include a third switch that switches the connection between the gate of the fifth transistor and the drain of the third transistor. This brings about an effect that the power supply voltage of the comparator is set to be equal in the reset phase and the comparison phase while realizing the reset operation and the comparison operation of the comparator.

[0009] In the first aspect, the second switching unit may further include a fourth switch that switches a connection between the gate of the fifth transistor and the drain of the fourth transistor, thereby achieving the reset operation and comparison operation of the comparator and setting the power supply voltage of the comparator to be equal in the reset phase and the comparison phase.

[0010] In the first aspect, in the reset phase, the first switch, the third switch, and the fourth switch may be turned on and the second switch may be turned off, and in the comparison phase, the first switch, the third switch, and the fourth switch may be turned off and the second switch may be turned on. This brings about an effect that in the reset phase, gate voltages of the third transistor and the fourth transistor are set based on the first bias voltage, and in the comparison phase, the gate voltage of the fifth transistor is set based on the bias voltage generated by the bias capacitor.

[0011] In the first aspect, the transistor may further include an offset capacitor connected in series to the bias capacitor, and a third switching unit that switches the connection between the offset capacitor and the bias capacitor, thereby providing an effect of absorbing imbalances in the threshold voltages of the first transistor, the second transistor, and the fifth transistor based on the offset voltage generated by the offset capacitor.

[0012] In the first aspect, the third switching unit may include a fifth switch that switches the input of a first offset voltage to a first terminal of the offset capacitor, a sixth switch that switches the input of a second offset voltage to a second terminal of the offset capacitor, a seventh switch that switches the connection between the offset capacitor and the bias capacitor, and an eighth switch that switches the connection between the first terminal of the offset capacitor and the drain of the first transistor or the second transistor. This allows charge to be accumulated in the offset capacitor without affecting the reset operation of the comparator.

[0013] In the first aspect, the power supply may further include a first dummy transistor that operates as a dummy for the first transistor and generates the first offset voltage, and a second dummy transistor that operates as a dummy for the fifth transistor and generates the second offset voltage, thereby providing an effect of accumulating charge in the offset capacitance so as to absorb any imbalance in threshold voltages of the first transistor, the second transistor, and the fifth transistor.

[0014] In the first aspect, the third switching unit may include a fifth switch that switches the input of a first offset voltage to a first terminal of the offset capacitor, a sixth switch that switches the input of a second offset voltage to a second terminal of the offset capacitor, a seventh switch that switches the connection between the offset capacitor and the bias capacitor, and a ninth switch that switches the connection between the first terminal of the offset capacitor and the drain of the fifth transistor. This allows charge to be accumulated in the offset capacitor without affecting the reset operation of the comparator.

[0015] In the first aspect, the first offset voltage may be lower than the second offset voltage, thereby providing an effect that charge is stored in the offset capacitance so as to absorb any imbalance in the threshold voltages of the first transistor, the second transistor, and the fifth transistor without increasing the power supply voltage of the comparator.

[0016] In the first aspect, the power supply may further include a mirror transistor that generates the first offset voltage based on a current mirror operation, and a second dummy transistor that operates as a dummy for the fifth transistor and generates the second offset voltage, thereby achieving the effect of storing charge in the offset capacitance so as to absorb any imbalance in the threshold voltages of the first, second, and fifth transistors while making the first offset voltage lower than the second offset voltage.

[0017] In the first aspect, the amplifier may further include a first AZ (Auto Zero) switch connected between the gate and drain of the first transistor and a second AZ switch connected between the gate and drain of the second transistor, thereby providing an effect of switching the connections between the gates and drains of the first transistor and the second transistor so as to absorb imbalances in the differential inputs of the comparator.

[0018] In the first aspect, the input capacitor may further include a first input capacitance connected in series to the gate of the first transistor and a second input capacitance connected in series to the gate of the second transistor, thereby providing an effect that imbalance in the differential input of the comparator is absorbed based on the charges stored in the first input capacitance and the second input capacitance.

[0019] In the first aspect, the input amplifier may further include a third input capacitor connected in parallel to the first input capacitor with respect to the gate of the first transistor, thereby providing an effect that imbalance in the differential input of the comparator is absorbed based on the charges accumulated in the first input capacitor, the second input capacitor, and the third input capacitor while fixing the voltage applied to the second input capacitor.

[0020] In the first aspect, a signal voltage may be input to the first input capacitance, a fixed voltage may be input to the second input capacitance, and a reference voltage may be input to the third input capacitance, thereby providing an effect that the signal voltage and the reference voltage are compared while the fixed voltage is applied to one of the differential inputs of the comparator.

[0021] In the first aspect, the comparator may further include a tenth transistor having a gate connected to the drain of the second transistor, an eleventh transistor connected in series with the tenth transistor, and a fourth switching unit that switches the connection of the gate of the tenth transistor, thereby achieving an effect of amplifying the comparator output while reducing the voltage drop of the tenth transistor by the threshold voltage of the tenth transistor based on the switching operation of the fourth switching unit.

[0022] In the first aspect, the fourth switching unit may further include a twelfth switch that switches the input of the second bias voltage to the gate of the tenth transistor, and a thirteenth switch that switches the connection between the drain of the second transistor and the gate of the tenth transistor, thereby achieving an effect of amplifying the comparator output while setting the power supply voltage of the comparator equal in the reset phase and the comparison phase.

[0023] a second aspect of the present invention is an imaging device including: a pixel array unit in which pixels are arranged in a matrix in row and column directions; and a column ADC unit that performs A / D (Analog to Digital) conversion on a column basis of pixel signals output from the pixels, the column ADC unit including a comparator that compares the pixel signals with a reference signal, the comparator including a first transistor having a gate to which a first input is applied, a second transistor having a gate to which a second input is applied, a third transistor connected in series with the first transistor, a fourth transistor connected in series with the second transistor and having a gate connected to the gate of the third transistor, a fifth transistor connected to the first and second transistors, a bias capacitor connected to the gate of the fifth transistor, and a first switching unit that switches the connection of the gates of the third and fourth transistors between a first bias voltage and a drain of the third transistor, based on the switching operation of the first switching unit.

[0024] In the second aspect, the comparator may further include a second switching unit that switches the connection between the gate of the fifth transistor and the drain of the first transistor or the drain of the second transistor. This brings about an effect that, when the gate of the fifth transistor is disconnected from the drain of the first transistor or the drain of the second transistor, the gate voltage of the fifth transistor is set based on a bias voltage generated by a bias capacitor, while the pixel signal is AD converted.

[0025] In the second aspect, the comparator may further include an offset capacitor connected in series to the bias capacitor, and a third switching unit that switches the connection between the offset capacitor and the bias capacitor, thereby achieving an effect of AD-converting the pixel signal while absorbing imbalances in the threshold voltages of the first transistor, the second transistor, and the fifth transistor based on the offset voltage generated by the offset capacitor.

[0026] FIG. 1 is a circuit diagram showing a configuration example of a reset phase of a comparator according to a first embodiment. FIG. 2 is a circuit diagram showing a configuration example of a comparison phase of a comparator according to the first embodiment. FIG. 3 is a diagram showing voltages applied to each transistor of a comparator in the reset phase and comparison phase according to the first embodiment. FIG. 4 is a circuit diagram showing a configuration example of a reset phase of a comparator according to a second embodiment. FIG. 5 is a circuit diagram showing a configuration example of a comparison phase of a comparator according to a third embodiment. FIG. 6 is a circuit diagram showing a configuration example of a comparison phase of a comparator according to a third embodiment. FIG. 7 is a circuit diagram showing a configuration example of a reset phase of a comparator according to a fourth embodiment. FIG. 8 is a circuit diagram showing a configuration example of a comparison phase of a comparator according to a fifth embodiment. FIG. 9 is a circuit diagram showing a configuration example of a comparison phase of a comparator according to the fifth embodiment. FIG. 10 is a circuit diagram showing a configuration example of a reset phase of a comparator according to a sixth embodiment. FIG. 11 is a circuit diagram showing a configuration example of a comparison phase of a comparator according to the sixth embodiment. FIG. 12 is a circuit diagram showing a configuration example of a reset phase of a comparator according to a seventh embodiment. FIG. 10 is a circuit diagram showing a configuration example of a comparison phase of a comparator according to a seventh embodiment. FIG. 11 is a diagram showing a first example of voltages applied to each transistor of the comparator in the reset phase and comparison phase according to the seventh embodiment. FIG. 12 is a diagram showing a second example of voltages applied to each transistor of the comparator in the reset phase and comparison phase according to the seventh embodiment. FIG. 13 is a diagram showing a third example of voltages applied to each transistor of the comparator in the reset phase and comparison phase according to the seventh embodiment. FIG. 14 is a circuit diagram showing a configuration example of an offset circuit according to the seventh embodiment. FIG. 15 is a circuit diagram showing a configuration example of a reset phase of a comparator according to an eighth embodiment. FIG. 16 is a circuit diagram showing a configuration example of a comparison phase of a comparator according to the eighth embodiment. FIG. 17 is a circuit diagram showing a configuration example of a reset phase of a comparator according to a ninth embodiment. FIG. 18 is a circuit diagram showing a configuration example of a comparison phase of a comparator according to the ninth embodiment.13 is a circuit diagram showing a configuration example of a reset phase of a comparator according to a ninth embodiment. FIG. 14 is a circuit diagram showing a configuration example of a comparison phase of a comparator according to the ninth embodiment. FIG. 15 is a circuit diagram showing a configuration example of a reset phase of a comparator according to an eleventh embodiment. FIG. 16 is a circuit diagram showing a configuration example of a comparison phase of a comparator according to the eleventh embodiment. FIG. 17 is a circuit diagram showing a configuration example of a reset phase of a comparator according to a twelfth embodiment. FIG. 18 is a circuit diagram showing a configuration example of a comparison phase of a comparator according to the twelfth embodiment. FIG. 19 is a circuit diagram showing a configuration example of a reset phase of a comparator according to a thirteenth embodiment. FIG. 20 is a circuit diagram showing a configuration example of a comparison phase of a comparator according to the thirteenth embodiment. FIG. 21 is a diagram showing voltages applied to each transistor of a comparator in the reset phase and comparison phase according to the thirteenth embodiment. FIG. 22 is a circuit diagram showing a configuration example of an offset circuit according to the seventh embodiment. FIG. 23 is a circuit diagram showing a configuration example of a reset phase of a comparator according to a fourteenth embodiment. FIG. 24 is a circuit diagram showing a configuration example of a comparison phase of a comparator according to the fourteenth embodiment. FIG. 25 is a block diagram showing a configuration example of an imaging device according to a fifteenth embodiment. FIG. 26 is a block diagram showing a configuration example of a solid-state imaging device according to the fifteenth embodiment. FIG. 23 is a diagram showing an example of a circuit configuration of a pixel provided in a solid-state imaging device according to a fifteenth embodiment. FIG. 24 is a block diagram showing an example of a configuration for each column of a solid-state imaging device according to a fifteenth embodiment. FIG. 25 is a timing chart showing an example of a waveform of each part when a signal is read out from a solid-state imaging device according to a fifteenth embodiment. FIG. 26 is a block diagram showing a schematic example of a configuration of a vehicle control system. FIG. 27 is an explanatory diagram showing an example of an installation position of an imaging unit.

[0027] Hereinafter, modes for implementing the present technology (hereinafter referred to as embodiments) will be described. The description will be made in the following order: 1. First embodiment (an example in which the connection of the gate of a load transistor is switchable between its drain and a bias voltage, and the connection of the gate of a current source transistor and the drains of both differential transistors is switchable) 2. Second embodiment (an example in which the connection of the gate of a load transistor is switchable between its drain and a bias voltage, and the connection of the gate of a current source transistor and the drains of both differential transistors is switchable, and the load transistor is configured with an NMOS transistor, and the differential transistor and the current source transistor are configured with PMOS transistors) 3. Third embodiment (an example in which a first input of a differential transistor is generated based on parallel inputs of a signal voltage and a reference voltage, and a second input of the differential transistor is set to a fixed potential) 4. Fourth embodiment (an example in which the connection of the gate of a load transistor is switchable between its drain and a bias voltage, and the connection of the gate of a current source transistor and one of the drains of the differential transistors is switchable) 5. 5. Fifth embodiment (an example in which the connection of the gate of a load transistor can be switched between its drain and a bias voltage, and the connection of the gate of a current source transistor and the drain of the other of the differential transistors can be switched) 6. Sixth embodiment (an example in which the connection of the gate of a load transistor can be switched between its drain and a bias voltage, and the connection of the gate of a current source transistor and the drains of both of the differential transistors can be switched, and an amplifier that amplifies the comparator output is provided) 7. Seventh embodiment (an example in which the connection of the gate of a load transistor can be switched between its drain and a bias voltage, and the connection of the gate of a current source transistor and one of the drains of the differential transistors can be switched, and an offset capacitance can be connected in series with the bias capacitance connected to the gate of the current source transistor)8. Eighth Embodiment (an example in which the connection of the gate of a load transistor can be switched between its drain and a bias voltage, and the connection between the gate of a current source transistor and the other drain of a differential transistor can be switched, and an offset capacitance can be connected in parallel to the bias capacitance connected to the gate of the current source transistor) 9. Ninth Embodiment (an example in which an offset capacitance can be connected in parallel to the bias capacitance connected to the gate of a current source transistor, the load transistor is configured with an NMOS transistor, the differential transistor and the current source transistor are configured with PMOS transistors, and the connection between the gate of the current source transistor and one drain of the differential transistor is switchable) 10. Tenth Embodiment (an example in which an offset capacitance can be connected in parallel to the bias capacitance connected to the gate of a current source transistor, the load transistor is configured with an NMOS transistor, the differential transistor and the current source transistor are configured with PMOS transistors, and the connection between the gate of the current source transistor and the other drain of the differential transistor is switchable) 11. Eleventh Embodiment (an example in which an offset capacitance can be connected in parallel to the bias capacitance connected to the gate of a current source transistor, and an amplifier is provided to amplify the comparator output) 12. 12. Twelfth embodiment (an example in which an offset capacitance can be connected in parallel to a bias capacitance connected to a gate of a current source transistor, an amplifier is provided to amplify a comparator output, a first input of a differential transistor is generated based on parallel inputs of a signal voltage and a reference voltage, and a second input of the differential transistor is set to a fixed potential) 13. Thirteenth embodiment (an example in which a connection between a gate of a current source transistor and one source of a differential transistor is switchable, and an offset capacitance can be connected in parallel to a bias capacitance connected to a gate of the current source transistor) 14. Fourteenth embodiment (an example in which a connection between a gate of a current source transistor and one source of a differential transistor is switchable, an offset capacitance can be connected in parallel to a bias capacitance connected to a gate of the current source transistor, and the load transistor is configured with an NMOS transistor, and the differential transistor and the current source transistor are configured with PMOS transistors)15. Fifteenth embodiment (an example in which a comparator with a reduced power supply voltage in the reset phase is applied to an imaging device) 16. Application example to a moving body

[0028] 1. First Embodiment FIG. 1 is a circuit diagram showing an example of the configuration of the reset phase of a comparator according to a first embodiment.

[0029] In the figure, comparator CM1 balances comparator inputs DV1 and DV2 based on auto-zero operation and outputs a voltage VO corresponding to the difference between comparator inputs DV1 and DV2. Comparator CM1 includes PMOS transistors T3 and T4, NMOS transistors T1, T2, and T5, AZ (Auto Zero) switches Z1 and Z2, bias capacitor CB, and switching units K1 and K2. Note that PMOS transistors T3 and T4 operate as load transistors, NMOS transistors T1 and T2 operate as differential transistors, and NMOS transistor T5 can operate as a current source transistor.

[0030] The PMOS transistor T3 and the NMOS transistor T1 are connected in series to each other. The PMOS transistor T4 and the NMOS transistor T2 are connected in series to each other. The sources of the PMOS transistors T3 and T4 are connected to the power supply voltage VDD, and the gates of the PMOS transistors T3 and T4 are connected to each other.

[0031] An input signal VIN is input to the gate of the NMOS transistor T1 via an input capacitor C1. An input signal VIP is input to the gate of the NMOS transistor T2 via an input capacitor C2. The input signals VIN and VIP can generate a differential input.

[0032] An AZ switch Z1 is connected between the gate and drain of the NMOS transistor T1, and an AZ switch Z2 is connected between the gate and drain of the NMOS transistor T2. The sources of the NMOS transistors T1 and T2 are connected to ground potential via an NMOS transistor T5. Each of the AZ switches Z1 and Z2 is opened or closed based on the auto-zero signal AZ.

[0033] A bias capacitor CB is connected to the gate of the NMOS transistor T5, and the NMOS transistor T5 can operate as a constant current source based on the bias voltage generated by the bias capacitor CB.

[0034] The switching unit K1 switches the connection of the gates of the PMOS transistors T3 and T4 between a bias voltage VB1 and the drain of the PMOS transistor T3. The switching unit K1 includes switches W1 and W2. The switch W1 switches the input of the bias voltage VB1 to the gates of the PMOS transistors T3 and T4. The switch W2 switches the connection between the gate and drain of the PMOS transistor T3.

[0035] The switching unit K2 switches the connection between the gate of the NMOS transistor T5 and the drains of the NMOS transistors T1 and T2. The switching unit K2 includes switches W3 and W4. The switch W3 switches the connection between the gate of the NMOS transistor T5 and the drain of the NMOS transistor T1. The switch W4 switches the connection between the gate of the NMOS transistor T5 and the drain of the NMOS transistor T2.

[0036] A switching signal SN is input to the switches W1, W3, and W4, and a switching signal SP is input to the switch W2. The switching signal SN is an inverted version of the switching signal SP.

[0037] In the reset phase, the AZ switches Z1 and Z2 are turned on based on the auto-zero signal AZ. At this time, charges are accumulated in the input capacitors C1 and C2 based on the currents flowing through the PMOS transistors T3 and T4 so that the comparator inputs DV1 and DV2 are balanced.

[0038] At this time, switches W1, W3, and W4 are turned on based on the switching signal SN, and switch W2 is turned off based on the switching signal SP. A bias voltage VB1 is applied to the gates of the PMOS transistors T3 and T4, causing current to flow through the PMOS transistors T3 and T4. At this time, the voltage drop across the PMOS transistors T3 and T4 is equivalent to the source-drain voltage Vds1 of the PMOS transistors T3 and T4. On the other hand, when the gates of the PMOS transistors T3 and T4 are connected to the drain of the PMOS transistor T3, the voltage drop across the PMOS transistors T3 and T4 is equivalent to the gate-source voltage Vgs1 of the PMOS transistors T3 and T4. Therefore, when the bias voltage VB1 is applied to the gates of the PMOS transistors T3 and T4, the voltage drop across the PMOS transistors T3 and T4 is reduced by the threshold voltage Vth1 of the PMOS transistors T3 and T4 compared to when the gates of the PMOS transistors T3 and T4 are connected to the drain of the PMOS transistor T3. Therefore, the power supply voltage VDD can be reduced by the threshold voltage Vth1 of the PMOS transistors T3 and T4.

[0039] Furthermore, the gate potential of the NMOS transistor T5 is equal to the drain potential of the NMOS transistors T1 and T2. Therefore, the sum of the voltage drop across the NMOS transistors T1 and T2 and the voltage drop across the NMOS transistor T5 is equal to the gate-source voltage Vgs3 of the NMOS transistor T5. Here, the voltage drop across the NMOS transistors T1 and T2 is equal to the gate-source voltage Vgs2 of the NMOS transistors T1 and T2. The voltage drop across the NMOS transistor T5 is equal to the source-drain voltage Vds3 of the NMOS transistor T5. At this time, charges corresponding to the drain potentials of the NMOS transistors T1 and T2 are stored in the bias capacitance CB.

[0040] FIG. 2 is a circuit diagram showing an example of the configuration of the comparison phase of the comparator according to the first embodiment.

[0041] In the comparison phase, the comparator CM1 compares the comparator inputs DV1 and DV2, and outputs a voltage VO according to the comparison result. At this time, the AZ switches Z1 and Z2 are turned off based on the auto-zero signal AZ.

[0042] Furthermore, switches W1, W3, and W4 are turned off based on switching signal SN, and switch W2 is turned on based on switching signal SP. Then, the gates of PMOS transistors T3 and T4 are connected to the drain of PMOS transistor T3, and current flows through PMOS transistors T3 and T4. At this time, the voltage drop across PMOS transistors T3 and T4 is equivalent to gate-source voltage Vgs1 of PMOS transistors T3 and T4.

[0043] Furthermore, the gate potential of the NMOS transistor T5 is equal to the bias potential generated by the bias capacitor CB. Here, the NMOS transistor T5 can operate in the saturation region based on the bias potential generated by the bias capacitor CB. At this time, the voltage drop across the NMOS transistor T5 is equal to the source-drain voltage Vds3 of the NMOS transistor T5. Furthermore, the voltage drop across the NMOS transistors T1 and T2 is equal to the source-drain voltage Vds2 of the NMOS transistors T1 and T2.

[0044] Therefore, in the comparison phase, the voltage drop across the NMOS transistors T1 and T2 is lower by the threshold voltage Vth2 of the NMOS transistors T1 and T2 than in the reset phase. On the other hand, in the reset phase, the voltage drop across the PMOS transistors T3 and T4 is lower by the threshold voltage Vth1 of the PMOS transistors T3 and T4 than in the comparison phase. Therefore, the threshold voltage Vth2 of the NMOS transistors T1 and T2 in the comparison phase can be compensated for by the threshold voltage Vth1 of the PMOS transistors T3 and T4 in the reset phase, and the power supply voltage VDD can be made equal in the reset phase and the comparison phase.

[0045] 3 is a diagram showing the voltages applied to each transistor of the comparator CM1 in the reset phase and the comparison phase according to the first embodiment, where "a" in the figure represents the voltages applied to each transistor of the comparator CM1 in the comparison phase, and "b" in the figure represents the voltages applied to each transistor of the comparator CM1 in the reset phase.

[0046] In the comparison phase shown in FIG. 10A, the power supply voltage VDD is allocated to the gate-source voltage Vgs1 of the PMOS transistors T3 and T4, the source-drain voltage Vds2 of the NMOS transistors T1 and T2, and the source-drain voltage Vds3 of the NMOS transistor T5.

[0047] In the diagram (b), during the reset phase, the power supply voltage VDD is allocated to the gate-source voltage Vgs1 of the PMOS transistors T3 and T4 and the gate-source voltage Vgs3 of the NMOS transistor T5. A portion of the gate-source voltage Vgs3 of the NMOS transistor T5 is allocated to the gate-source voltage Vgs2 of the NMOS transistors T1 and T2. At this time, the reset phase can be operated based on the power supply voltage VDD reduced by the threshold voltage Vth1 of the PMOS transistors T3 and T4, thereby enabling a lower power supply voltage during the reset phase.

[0048] In this way, in the first embodiment, in the reset phase, the PMOS transistors T3 and T4 are operated as current sources based on the bias voltage VB1, which reduces the voltage drop across the PMOS transistors T3 and T4 in the reset phase by the threshold voltage Vth1, thereby enabling a lower power supply voltage for the comparator CM1.

[0049] In addition, a bias capacitor CB is connected to the gate of the NMOS transistor T5, and the charge that generates the bias voltage of the NMOS transistor T5 is stored in the bias capacitor CB during the reset phase. As a result, even if the gate of the NMOS transistor T5 is disconnected from the drains of the PMOS transistors T3 and T4 during the comparison phase, the NMOS transistor T5 can still operate, and the comparison operation of the comparator CM1 can be realized.

[0050] 2. Second Embodiment In the first embodiment described above, PMOS transistors T3 and T4 are used as load transistors, NMOS transistors T1 and T2 are used as differential transistors, and NMOS transistor T5 is used as a current source transistor. In this second embodiment, NMOS transistors are used as load transistors, and PMOS transistors are used as differential transistors and current source transistors.

[0051] FIG. 4 is a circuit diagram showing a configuration example of the reset phase of the comparator according to the second embodiment, and FIG. 5 is a circuit diagram showing a configuration example of the comparison phase of the comparator according to the second embodiment.

[0052] In the figure, this comparator CM2 includes NMOS transistors T3' and T4' and PMOS transistors T1', T2', and T5' instead of the PMOS transistors T3 and T4 and NMOS transistors T1, T2, and T5 of the first embodiment. The other configuration of the comparator CM2 of the second embodiment is the same as the configuration of the comparator CM1 of the first embodiment.

[0053] The NMOS transistor T3' and the PMOS transistor T1' are connected in series to each other. The NMOS transistor T4' and the PMOS transistor T2' are connected in series to each other. The sources of the NMOS transistors T3' and T4' are connected to the ground potential, and the gates of the NMOS transistors T3' and T4' are connected to each other.

[0054] The input signal VIN is input to the gate of the PMOS transistor T1' via an input capacitor C1, and the input signal VIP is input to the gate of the PMOS transistor T2' via an input capacitor C2.

[0055] An AZ switch Z1 is connected between the gate and drain of the PMOS transistor T1', and an AZ switch Z2 is connected between the gate and drain of the PMOS transistor T2'. The sources of the PMOS transistors T1' and T2' are connected to the power supply voltage VDD via a PMOS transistor T5'.

[0056] A bias capacitor CB is connected to the gate of the PMOS transistor T5'. The PMOS transistor T5' can operate as a constant current source based on the bias voltage generated by the bias capacitor CB.

[0057] The switching unit K1 switches the connection of the gates of the NMOS transistors T3' and T4' between a bias voltage VB1' and the drain of the NMOS transistor T3'. The switch W1 switches the input of the bias voltage VB1' to the gates of the NMOS transistors T3' and T4'. The switch W2 switches the connection between the gate and drain of the NMOS transistor T3'.

[0058] The switching unit K2 switches the connection between the gate of the PMOS transistor T5' and the drains of the PMOS transistors T1' and T2'. The switch W3 switches the connection between the gate of the PMOS transistor T5' and the drain of the PMOS transistor T1'. The switch W4 switches the connection between the gate of the PMOS transistor T5' and the drain of the PMOS transistor T1'.

[0059] In the reset phase and comparison phase of the second embodiment, the operations of the AZ switches Z1, Z2 and switches W1 to W4 are similar to the operations of the AZ switches Z1, Z2 and switches W1 to W4 of the first embodiment described above.

[0060] In this way, in the second embodiment described above, NMOS transistors T3' and T4' are used as load transistors, PMOS transistors T1' and T2' are used as differential transistors, and a PMOS transistor T5' is used as a current source transistor. This allows for a lower power supply voltage for comparator CM2 even when the polarity of the transistors used in comparator CM2 is changed.

[0061] 3. Third Embodiment In the first embodiment described above, the input signal VIN is input to the NMOS transistor T1 via the input capacitance C1, and the input signal VIP is input to the NMOS transistor T2 via the input capacitance C2. In this third embodiment, a signal voltage and a reference voltage are input in parallel to the NMOS transistor T1 via their respective input capacitances, and the input of the NMOS transistor T2 is set to a fixed potential via the input capacitance C2.

[0062] FIG. 6 is a circuit diagram showing a configuration example of the reset phase of the comparator according to the third embodiment, and FIG. 7 is a circuit diagram showing a configuration example of the comparison phase of the comparator according to the third embodiment.

[0063] In the figure, the comparator CM3 has an input capacitance C3 added to the comparator CM1 of the first embodiment. The other configuration of the comparator CM3 of the third embodiment is the same as the configuration of the comparator CM1 of the first embodiment.

[0064] The input capacitor C3 is connected in parallel to the input capacitor C1 with respect to the gate of the NMOS transistor T1. At this time, the signal voltage VSI and the reference voltage VRF are input in parallel to the gate of the NMOS transistor T1 via the input capacitors C1 and C3, respectively. The reference voltage VRF may be a ramp wave. The signal voltage VSI may be a pixel signal read out from the pixel. Furthermore, the input capacitor C2 is connected to a fixed potential. The fixed potential may be the ground potential.

[0065] In the reset phase and comparison phase of the third embodiment, the operations of the AZ switches Z1, Z2 and switches W1 to W4 are similar to the operations of the AZ switches Z1, Z2 and switches W1 to W4 of the first embodiment described above.

[0066] As described above, in the third embodiment, the signal voltage VSI and the reference voltage VRF are input in parallel to the NMOS transistor T1 via the input capacitors C1 and C3, respectively, and the input of the NMOS transistor T2 is set to a fixed potential. This allows the signal voltage VSI and the reference voltage VRF to be compared based on the comparator input DV1 without changing the potential of the comparator input DV2. This makes it possible to reduce the dynamic range of the differential input in the comparison phase of the comparator CM3, thereby lowering the power supply voltage VDD.

[0067] In the third embodiment, the input capacitor C3 is added to the comparator CM1 of the first embodiment, and the signal voltage VSI and the reference voltage VRF are input in parallel to the gate of the NMOS transistor T1 via the input capacitors C1 and C3, respectively. Alternatively, the input capacitor C3 may be added to the comparator CM2 of the second embodiment, and the signal voltage VSI and the reference voltage VRF may be input in parallel to the gate of the PMOS transistor T1′ via the input capacitors C1 and C3, respectively.

[0068] 4. Fourth Embodiment In the first embodiment described above, the connection between the gate of the NMOS transistor T5 and the drain of each of the NMOS transistors T1 and T2 is switched between the reset phase and the comparison phase. In this fourth embodiment, the connection between the gate of the NMOS transistor T5 and the drain of the NMOS transistor T1 is switched between the reset phase and the comparison phase.

[0069] FIG. 8 is a circuit diagram showing a configuration example of the reset phase of the comparator according to the fourth embodiment, and FIG. 9 is a circuit diagram showing a configuration example of the comparison phase of the comparator according to the fourth embodiment.

[0070] In the figure, this comparator CM4 includes a switching unit K12 instead of the switching unit K2 of the first embodiment. The other configuration of the comparator CM4 of the fourth embodiment is the same as the configuration of the comparator CM1 of the first embodiment.

[0071] The switching unit K12 switches the connection between the gate of the NMOS transistor T5 and the drain of the NMOS transistor T1. The switching unit K12 is the same as the switching unit K2 of the first embodiment except that the switch W4 has been removed. The other configurations of the switching unit K12 of the fourth embodiment are the same as the configuration of the switching unit K2 of the first embodiment.

[0072] In the reset phase and comparison phase of the fourth embodiment, the operations of the AZ switches Z1, Z2 and switches W1 to W3 are similar to the operations of the AZ switches Z1, Z2 and switches W1 to W3 of the first embodiment described above.

[0073] In this way, in the fourth embodiment described above, the connection between the gate of the NMOS transistor T5 and the drain of the NMOS transistor T1 is switched between the reset phase and the comparison phase, which allows the comparator CM4 to have a lower power supply voltage while reducing the number of components compared to the comparator CM1.

[0074] In the fourth embodiment, the switch W4 is removed from the comparator CM1 of the first embodiment. Alternatively, the switch W4 may be removed from the comparator CM2 of the second embodiment. Furthermore, the input capacitor C3 of the third embodiment may be added to the comparator CM1 of the first embodiment or the comparator CM2 of the second embodiment, and the signal voltage VSI and the reference voltage VRF may be input in parallel via the input capacitors C1 and C3, respectively.

[0075] 5. Fifth Embodiment In the above-described fourth embodiment, the connection between the gate of the NMOS transistor T5 and the drain of the NMOS transistor T1 is switched between the reset phase and the comparison phase. In this fifth embodiment, the connection between the gate of the NMOS transistor T5 and the drain of the NMOS transistor T2 is switched between the reset phase and the comparison phase.

[0076] FIG. 10 is a circuit diagram showing a configuration example of the reset phase of the comparator according to the fifth embodiment, and FIG. 11 is a circuit diagram showing a configuration example of the comparison phase of the comparator according to the fifth embodiment.

[0077] In the figure, this comparator CM5 includes a switching unit K22 instead of the switching unit K2 of the first embodiment. The other configuration of the comparator CM5 of the fifth embodiment is the same as the configuration of the comparator CM1 of the first embodiment.

[0078] The switching unit K22 switches the connection between the gate of the NMOS transistor T5 and the drain of the NMOS transistor T2. The switching unit K22 is the same as the switching unit K2 of the first embodiment except that the switch W3 has been removed. The remaining configuration of the switching unit K22 of the fifth embodiment is the same as the configuration of the switching unit K2 of the first embodiment.

[0079] In the reset phase and comparison phase of the fifth embodiment, the operations of the AZ switches Z1, Z2 and switches W1, W2, W4 are similar to those of the AZ switches Z1, Z2 and switches W1, W2, W4 of the first embodiment described above.

[0080] In this way, in the fifth embodiment described above, the connection between the gate of the NMOS transistor T5 and the drain of the NMOS transistor T2 is switched between the reset phase and the comparison phase, which allows the comparator CM5 to have a lower power supply voltage while reducing the number of components compared to the comparator CM1.

[0081] In the fifth embodiment, the switch W3 is omitted from the comparator CM1 of the first embodiment. Alternatively, the switch W3 may be omitted from the comparator CM2 of the second embodiment. Furthermore, the input capacitor C3 of the third embodiment may be added to the comparator CM1 of the first embodiment or the comparator CM2 of the second embodiment, and the signal voltage VSI and the reference voltage VRF may be input in parallel via the input capacitors C1 and C3, respectively.

[0082] 6. Sixth Embodiment In the first embodiment described above, in the reset phase, the PMOS transistors T3 and T4 are operated as current sources based on the bias voltage VB1, and the charge that generates the bias voltage for the NMOS transistor T5 is stored in the bias capacitor CB. In this sixth embodiment, in the reset phase, the PMOS transistors T3 and T4 are operated as current sources based on the bias voltage VB1, and the charge that generates the bias voltage for the NMOS transistor T5 is stored in the bias capacitor CB, and an amplifier that amplifies the comparator output is provided.

[0083] FIG. 12 is a circuit diagram showing a configuration example of the reset phase of the comparator according to the sixth embodiment, and FIG. 13 is a circuit diagram showing a configuration example of the comparison phase of the comparator according to the sixth embodiment.

[0084] In the figure, a comparator CM6 is configured by adding a PMOS transistor T10, an NMOS transistor T11, a switch W14, a switching unit K4, and a capacitor C4 to the comparator CM1 of the first embodiment. The other configuration of the comparator CM6 of the sixth embodiment is the same as the configuration of the comparator CM1 of the first embodiment.

[0085] The PMOS transistor T10 and the NMOS transistor T11 are connected in series. The source of the PMOS transistor T10 is connected to the power supply voltage VDD. A switch W14 is connected between the gate and drain of the NMOS transistor T11. A capacitor C4 is connected to the gate of the NMOS transistor T11. A switching unit K4 is connected to the gate of the PMOS transistor T10, and an output voltage VO is output from the drain of the NMOS transistor T11.

[0086] The switching unit K4 switches the connection of the gate of the PMOS transistor T10 between the bias voltage VB3 and the drain of the PMOS transistor T4. The switching unit K4 includes switches W12 and W13. The switch W12 switches the input of the bias voltage VB3 to the gate of the PMOS transistor T10. The switch W13 switches the connection between the gate of the PMOS transistor T10 and the drain of the PMOS transistor T4.

[0087] A switching signal SN is input to the switches W12 and W14, and a switching signal SP is input to the switch W13.

[0088] In the reset phase and comparison phase of the sixth embodiment, the operations of the AZ switches Z1, Z2 and switches W1 to W4 are similar to the operations of the AZ switches Z1, Z2 and switches W1 to W4 of the first embodiment described above.

[0089] In the reset phase, switches W12 and W14 are turned on based on the switching signal SN, and switch W13 is turned off based on the switching signal SP. A bias voltage VB3 is applied to the gate of PMOS transistor T10, causing a current to flow through the PMOS transistor T10. At this time, the voltage drop across the PMOS transistor T10 is equal to the source-drain voltage Vds4 of the PMOS transistor T10. The gate potential of NMOS transistor T11 is equal to the drain potential of NMOS transistor T11. At this time, a charge corresponding to the drain potential of NMOS transistor T11 is accumulated in capacitor C4.

[0090] In the reset phase, when the PMOS transistor T10 is connected downstream of the PMOS transistor T4', the input voltage of the PMOS transistor T10 must be set so that an appropriate current flows through the PMOS transistor T10. At this time, a voltage equivalent to the gate / source voltage of the PMOS transistor T4' must be applied to the input of the PMOS transistor T10, but in the reset phase, the output of the PMOS transistor T4' becomes a voltage equivalent to the drain / source voltage. Therefore, in the reset phase, the gate of the PMOS transistor T10 is separated from the drain of the PMOS transistor T4' via the switch W13, and a voltage equivalent to the gate / source voltage of the PMOS transistor T4' is applied as the bias voltage VB3.

[0091] In the comparison phase, comparator inputs DV1 and DV2 are compared by comparator CM6, and a voltage VO corresponding to the comparison result is amplified and output from comparator CM6. At this time, switches W12 and W14 are turned off based on switching signal SN, and switch W13 is turned on based on switching signal SP. The gate of PMOS transistor T10 is connected to the drain of PMOS transistor T4, and voltage VO corresponding to the drain potential of PMOS transistor T4 is output from the drain of PMOS transistor T10.

[0092] The gate potential of the NMOS transistor T11 is equal to the bias potential generated by the capacitor C4, and the NMOS transistor T11 can operate in the saturation region based on the bias potential generated by the capacitor C4.

[0093] As described above, in the sixth embodiment, in the reset phase, the PMOS transistors T3 and T4 are operated as current sources based on the bias voltage VB1, the charge that generates the bias voltage for the NMOS transistor T5 is stored in the bias capacitor CB, and an amplifier is provided to amplify the comparator output. This makes it possible to amplify and output the comparison result of the comparator CM6 while reducing the power supply voltage of the comparator CM6.

[0094] In the sixth embodiment, the comparator CM1 of the first embodiment is provided with an amplifier that amplifies and outputs the comparison result. Alternatively, any of the comparators CM2 to CM5 of the second to fifth embodiments may be provided with an amplifier that amplifies and outputs the comparison result.

[0095] 7. Seventh Embodiment In the first embodiment described above, in the reset phase, the PMOS transistors T3 and T4 are operated as current sources based on the bias voltage VB1, and the charge that generates the bias voltage for the NMOS transistor T5 is stored in the bias capacitor CB. In this seventh embodiment, in the reset phase, the PMOS transistors T3 and T4 are operated as current sources based on the bias voltage VB1, and the charge that generates the bias voltage for the NMOS transistor T5 can be stored in the bias capacitor CB, and an offset capacitor can be connected in series with the bias capacitor CB.

[0096] FIG. 14 is a circuit diagram showing a configuration example of a reset phase of a comparator according to the seventh embodiment, and FIG. 15 is a circuit diagram showing a configuration example of a comparison phase of a comparator according to the seventh embodiment.

[0097] In the figure, this comparator CM7 has a switching unit K3 instead of the switching unit K2 of the first embodiment. Also, this comparator CM7 has an offset capacitance CF added to the comparator CM1 of the first embodiment. Other configurations of the comparator CM7 of the seventh embodiment are the same as the configuration of the comparator CM1 of the first embodiment.

[0098] The offset capacitance CF applies an offset voltage between the gate of the NMOS transistor T5 and the drain of the NMOS transistor T1. At this time, the offset capacitance CF can be connected in series to the bias capacitance CB via the switching unit K3. The offset voltage generated by the offset capacitance CF can be given by the difference between the offset voltages VOF1 and VOF2.

[0099] The switching unit K3 switches the connection between the offset capacitance CF and the bias capacitance CB. The switching unit K3 includes switches W5 to W8. The switch W5 switches the input of the offset voltage VOF1 to the first terminal of the offset capacitance CF. The switch W6 switches the input of the offset voltage VOF2 to the second terminal of the offset capacitance CF. The switch W7 switches the connection between the first terminal of the offset capacitance CF and the drain of the NMOS transistor T1. The switch W8 switches the connection between the offset capacitance CF and the bias capacitance CB.

[0100] A switching signal SP is input to the switches W5 and W6, and a switching signal SN is input to the switches W7 and W8.

[0101] In the reset phase and comparison phase of the seventh embodiment, the operations of the AZ switches Z1, Z2 and switches W1, W2 are similar to the operations of the AZ switches Z1, Z2 and switches W1, W2 of the first embodiment described above.

[0102] During the reset phase, switches W7 and W8 are turned on based on the switching signal SN, and switches W5 and W6 are turned off based on the switching signal SP. At this time, an offset capacitor CF is connected between the gate of NMOS transistor T5 and the drain of NMOS transistor T1, and the difference between the offset voltages VOF1 and VOF2 is applied. The difference between the offset voltages VOF1 and VOF2 is adjusted so that the drain-source voltage Vds3 of NMOS transistor T5 becomes the minimum drain-source voltage. The offset voltage generated by the offset capacitor CFd can absorb any imbalance in the threshold voltages of the NMOS transistors T1, T2, and T5. This minimizes the power supply voltage VDD, reducing power consumption regardless of the balance in the threshold voltages of the NMOS transistors T1, T2, and T5. At this time, switches W5 and W6 are turned off, disconnecting the offset capacitor CF from the offset voltages VOF1 and VOF2, preventing a decrease in the accuracy of the auto-zero operation due to the source generating the offset voltages VOF1 and VOF2.

[0103] In the previous comparison phase, switches W7 and W8 are turned off based on switching signal SN, and switches W5 and W6 are turned on based on switching signal SP. At this time, offset voltages VOF1 and VOF2 are applied to offset capacitance CF with offset capacitance CF disconnected from the gate of NMOS transistor T5 and the drain of NMOS transistor T1. At this time, offset voltages VOF1 and VOF2 are applied to both terminals of offset capacitance CF, and charges corresponding to the difference between the offset voltages VOF1 and VOF2 are accumulated in offset capacitance CF. Here, by accumulating charges corresponding to the difference between the offset voltages VOF1 and VOF2 in offset capacitance CF in the previous comparison phase, it is possible to prevent a decrease in the accuracy of the auto-zero operation due to the source of generation of the offset voltages VOF1 and VOF2.

[0104] 16 is a diagram showing a first example of voltages applied to each transistor of the comparator CM7 in the reset phase and the comparison phase according to the seventh embodiment, where "a" in the figure indicates the voltage applied to each transistor of the comparator CM7 in the reset phase, and "b" in the figure indicates the voltage applied to each transistor of the comparator CM7 in the comparison phase.

[0105] In FIG. 10A, the drain-source voltage Vds3 of the NMOS transistor T5 is set to the minimum drain-source voltage Vds3min by absorbing any excess or deficiency in the drain-source voltage of the NMOS transistor T5 based on the offset voltage Vof applied to the offset capacitance CF.

[0106] In the reset phase, an offset capacitor CF is connected between the gate of the NMOS transistor T5 and the drain of the NMOS transistor T1 to apply an offset voltage Vof, thereby optimizing the drain voltages of the NMOS transistors T1 and T2. This optimal voltage is the voltage from which the gate-source voltage Vgs2 of the NMOS transistors T1 and T2 is subtracted to obtain the minimum drain-source voltage Vds3min of the NMOS transistor T5. In this case, the drain-source voltage Vds3 of the NMOS transistor T5 can be given by the sum of the minimum drain-source voltage Vds3min and the threshold voltage Vth3 of the NMOS transistor T5.

[0107] For example, suppose the gate-source voltage Vgs3 and threshold voltage Vth3 of the NMOS transistor T5 are too large relative to the gate-source voltage Vgs2 of each of the NMOS transistors T1 and T2. In this case, by adding a negative offset voltage Vof such that VOF1<VOF2, the drain-source voltage Vds3 of the NMOS transistor T5 can be lowered, eliminating the excess and achieving the minimum drain-source voltage Vds3min. On the other hand, suppose the gate-source voltage Vgs3 and threshold voltage Vth3 of the NMOS transistor T5 are too small relative to the gate-source voltage Vgs2 of each of the NMOS transistors T1 and T2. In this case, by adding a positive offset voltage Vof such that VOF1>VOF2, the drain-source voltage Vds3 of the NMOS transistor T5 can be increased, eliminating the deficiency and achieving the minimum drain-source voltage Vds3min.

[0108] In the comparison phase, as shown by b in the figure, the offset capacitance CF is disconnected from the drains of the NMOS transistors T1 and T2 and the gate of the NMOS transistor T5. At this time, the voltage drop across the NMOS transistor T5 becomes equal to the source-drain voltage Vds3 of the NMOS transistor T5, allowing it to operate in the saturation region.

[0109] 17 is a diagram showing a second example of the voltages applied to the transistors of the comparator CM7 in the reset phase and the comparison phase according to the seventh embodiment, where "a" in the figure indicates the voltages applied to the transistors of the comparator CM7 in the reset phase, and "b" in the figure indicates the voltages applied to the transistors of the comparator CM7 in the comparison phase.

[0110] In the figure, instead of lowering the power supply voltage VDD based on the offset voltage Vof, the dynamic range (maximum allowable amplitude) of the input signal may be widened while leaving the power supply voltage VDD unchanged.

[0111] In the case of an NMOS input, a typical comparator circuit determines its operating point closer to the power supply during the reset phase, and the input signal has a dynamic range in the downward direction from that point. In this case, by increasing the offset voltage Vof of the offset capacitance CF, the input signal can have a dynamic range DLI in the downward direction from the reset phase. This dynamic range DLI is in the same direction as a typical comparator circuit. For example, single-slope AD conversion used in CMOS image sensors requires a dynamic range in the downward direction of the signal. Therefore, a method of providing a dynamic range DLI based on the offset voltage Vof can be effectively applied to single-slope AD conversion.

[0112] 18 is a diagram showing a third example of voltages applied to each transistor of the comparator CM7 in the reset phase and the comparison phase according to the seventh embodiment, where "a" in the figure indicates the voltage applied to each transistor of the comparator CM7 in the reset phase, and "b" in the figure indicates the voltage applied to each transistor of the comparator CM7 in the comparison phase.

[0113] In the figure, the balance between the falling and rising dynamic ranges DLI and DHI can be freely changed depending on the application based on the offset voltage Vof of the offset capacitance CF.

[0114] FIG. 19 is a circuit diagram showing a configuration example of an offset circuit according to the seventh embodiment.

[0115] In the figure, an offset circuit OF1 generates offset voltages VOF1 and VOF2. At this time, the offset circuit OF1 can generate the offset voltages VOF1 and VOF2 based on the dummy operations of NMOS transistors T1, T2, and T5. The offset circuit OF1 includes an operational amplifier OP, PMOS transistors T21 to T23, NMOS transistors T24 to T26, and resistors R1 and R2. The PMOS transistors T21 to T23 are examples of mirror transistors as defined in the claims. The NMOS transistors T25 and T26 are examples of dummy transistors as defined in the claims.

[0116] The PMOS transistor T21 and the NMOS transistor T24 are connected in series. The PMOS transistor T22 and the NMOS transistor T25 are connected in series. The PMOS transistor T23 and the NMOS transistor T26 are connected in series. The source of each of the PMOS transistors T21 to T23 is connected to the power supply voltage VDD. The source of the NMOS transistor T24 is connected to the ground potential via a resistor R1. The source of the NMOS transistor T25 is connected to the ground potential. The source of the NMOS transistor T26 is connected to the ground potential via a resistor R2.

[0117] The gate of the PMOS transistor T21 is connected to the drain. The gate of the NMOS transistor T25 is connected to the drain. The gate of the NMOS transistor T26 is connected to the drain. A bias voltage VB11 is applied to the gates of the PMOS transistors T21 to T23. The gate of the NMOS transistor T24 is connected to the output of the operational amplifier OP. An offset voltage VOF2 is output from the drain of the NMOS transistor T25. An offset voltage VOF1 is output from the drain of the NMOS transistor T26. A reference voltage VST is applied to the non-inverting input of the operational amplifier OP. The inverting input of the operational amplifier OP is connected to the source of the NMOS transistor T24.

[0118] The NMOS transistor T25 can operate as a dummy for the NMOS transistor T5. In this case, the NMOS transistor T25 can be the same type of transistor as the NMOS transistor T5. The NMOS transistor T26 can operate as a dummy for the NMOS transistor T1. In this case, the NMOS transistor T26 can be the same type of transistor as the NMOS transistor T1.

[0119] In the operational amplifier OP, the source potential of the NMOS transistor T24 is compared with the reference voltage VST, and a current flows through the NMOS transistor T24 so that the source potential of the NMOS transistor T24 matches the reference voltage VST. Based on the current mirror operation of the PMOS transistors T21 to T23, the current flowing through the NMOS transistor T24 is copied and flows through each of the NMOS transistors T25 and T26. At this time, the voltage generated across resistor R2 determines the drain-source voltage of the NMOS transistor T5. Any imbalance in the threshold voltages of the NMOS transistors T25 and T26 is reflected in the offset voltages VOF1 and VOF2. By using the same type of resistive element for each of the resistors R1 and R2, fluctuations in the voltage generated across resistor R2 can be suppressed.

[0120] As described above, in the seventh embodiment, during the reset phase, the PMOS transistors T3 and T4 are operated as current sources based on the bias voltage VB1, allowing the charge that generates the bias voltage for the NMOS transistor T5 to be stored in the bias capacitor CB, and the offset capacitor CF to be connected in series with the bias capacitor CB. This makes it possible to absorb imbalances in the threshold voltages of the NMOS transistors T1, T2, and T5 based on the offset voltage generated by the offset capacitor CF. This eliminates the need for a margin in the power supply voltage VDD to accommodate variations in the threshold voltages of the NMOS transistors T1, T2, and T5, and increases the dynamic range of the comparator CM7.

[0121] 3. Eighth Embodiment In the seventh embodiment described above, an offset capacitance CF is connected between the gate of the NMOS transistor T5 and the drain of the NMOS transistor T1 during the reset phase. In this eighth embodiment, an offset capacitance CF is connected between the gate of the NMOS transistor T5 and the drain of the NMOS transistor T2 during the reset phase.

[0122] FIG. 20 is a circuit diagram showing a configuration example of a reset phase of a comparator according to the eighth embodiment, and FIG. 21 is a circuit diagram showing a configuration example of a comparison phase of a comparator according to the eighth embodiment.

[0123] In the figure, this comparator CM8 has a switching unit K3' instead of the switching unit K3 of the seventh embodiment. Other configurations of the comparator CM8 of the eighth embodiment are similar to the configuration of the comparator CM7 of the seventh embodiment.

[0124] The switching unit K3' switches the connection between the gate of the NMOS transistor T5 and the drain of the NMOS transistor T2. The switching unit K3' includes a switch W7' instead of the switch W7 of the seventh embodiment. The switch W7' switches the connection between the first terminal of the offset capacitance CF and the drain of the NMOS transistor T2. The other configurations of the switching unit K3' of the eighth embodiment are the same as the configuration of the switching unit K3 of the seventh embodiment.

[0125] In the reset phase and comparison phase of the eighth embodiment, the operations of the AZ switches Z1, Z2 and switches W1, W2, W5, W6, W7′, and W8 are similar to the operations of the AZ switches Z1, Z2 and switches W1, W2, W5 to W8 of the seventh embodiment described above.

[0126] In this way, in the eighth embodiment described above, the offset capacitor CF is connected between the gate of the NMOS transistor T5 and the drain of the NMOS transistor T2 in the reset phase, so that the imbalance in the threshold voltages of the NMOS transistors T1, T2, and T5 can be absorbed based on the offset voltage generated by the offset capacitor CF.

[0127] 9. Ninth Embodiment In the seventh embodiment described above, in the reset phase, an offset capacitance CF is connected between the gate of the NMOS transistor T5 and the drain of the NMOS transistor T1, and PMOS transistors T3 and T4 are used as load transistors, NMOS transistors T1 and T2 are used as differential transistors, and NMOS transistor T5 is used as a current source transistor. In this ninth embodiment, NMOS transistors T3' and T4' are used as load transistors, and PMOS transistors T1', T2', and T5' are used as differential transistors and current source transistors.

[0128] FIG. 22 is a circuit diagram showing a configuration example of a reset phase of a comparator according to the ninth embodiment, and FIG. 23 is a circuit diagram showing a configuration example of a comparison phase of a comparator according to the ninth embodiment.

[0129] In the figure, this comparator CM9 includes NMOS transistors T3' and T4' and PMOS transistors T1', T2', and T5' of the second embodiment, instead of the PMOS transistors T3 and T4 and NMOS transistors T1, T2, and T5 of the seventh embodiment. The rest of the configuration of the comparator CM9 of the ninth embodiment is the same as the configuration of the comparator CM7 of the seventh embodiment.

[0130] The switching unit K3 switches the connection between the offset capacitor CF and the bias capacitor CB. The switch W7 switches the connection between the first terminal of the offset capacitor CF and the drain of the PMOS transistor T1′.

[0131] In the reset phase and comparison phase of the ninth embodiment, the operations of the AZ switches Z1, Z2 and switches W1, W2, W5 to W8 are similar to the operations of the AZ switches Z1, Z2 and switches W1, W2, W5 to W8 in the seventh embodiment described above.

[0132] As described above, in the ninth embodiment, in the reset phase, the NMOS transistors T3′ and T4′ are operated as current sources based on the bias voltage VB1, and the charge that generates the bias voltage for the PMOS transistor T5′ can be stored in the bias capacitor CB, and the offset capacitor CF can be connected in series with the bias capacitor CB. As a result, even when the polarity of the transistors used in the comparator CM9 is changed, the imbalance in the threshold voltages of the PMOS transistors T1′, T2′, and T5′ can be absorbed based on the offset voltage generated by the offset capacitor CF.

[0133] 10. Tenth Embodiment In the eighth embodiment described above, in the reset phase, an offset capacitance CF is connected between the gate of the NMOS transistor T5 and the drain of the NMOS transistor T2, PMOS transistors T3 and T4 are used as load transistors, NMOS transistors T1 and T2 are used as differential transistors, and NMOS transistor T5 is used as a current source transistor. In this tenth embodiment, in the reset phase, an offset capacitance CF is connected between the gate of the NMOS transistor T5 and the drain of the NMOS transistor T2, NMOS transistors T3' and T4' are used as load transistors, and PMOS transistors T1', T2', and T5' are used as differential transistors and current source transistors.

[0134] FIG. 24 is a circuit diagram showing a configuration example of the reset phase of the comparator according to the tenth embodiment, and FIG. 25 is a circuit diagram showing a configuration example of the comparison phase of the comparator according to the tenth embodiment.

[0135] In the figure, this comparator CM10 includes NMOS transistors T3' and T4' and PMOS transistors T1', T2', and T5' instead of the PMOS transistors T3 and T4 and the NMOS transistors T1, T2, and T5 of the eighth embodiment. The rest of the configuration of the comparator CM10 of the tenth embodiment is the same as the configuration of the comparator CM8 of the eighth embodiment.

[0136] The switching unit K3' switches the connection between the offset capacitor CF and the bias capacitor CB. The switch W7' switches the connection between the first terminal of the offset capacitor CF and the drain of the PMOS transistor T2'.

[0137] In the reset phase and comparison phase of the tenth embodiment, the operations of the AZ switches Z1, Z2 and switches W1, W2, W5, W6, W7', and W8 are similar to the operations of the AZ switches Z1, Z2 and switches W1, W2, W5, W6, W7', and W8 of the eighth embodiment described above.

[0138] As described above, in the tenth embodiment, in the reset phase, the offset capacitor CF is connected between the gate of the PMOS transistor T5' and the drain of the PMOS transistor T2', the NMOS transistors T3' and T4' are used as load transistors, and the PMOS transistors T1', T2', and T5' are used as differential and current source transistors. As a result, even when the polarity of the transistors used in the comparator CM10 is changed, the imbalance in the threshold voltages of the PMOS transistors T1', T2', and T5' can be absorbed based on the offset voltage generated by the offset capacitor CF.

[0139] 11. Eleventh Embodiment In the above-described tenth embodiment, in the reset phase, the NMOS transistors T3′ and T4′ are operated as current sources based on the bias voltage VB1, so that the charge that generates the bias voltage for the PMOS transistor T5′ can be stored in the bias capacitance CB, and the offset capacitance CF can be connected in series with the bias capacitance CB. In this eleventh embodiment, in the reset phase, the NMOS transistors T3′ and T4′ are operated as current sources based on the bias voltage VB1, so that the charge that generates the bias voltage for the PMOS transistor T5′ can be stored in the bias capacitance CB, and the offset capacitance CF can be connected in series with the bias capacitance CB, and an amplifier that amplifies the comparator output is provided.

[0140] FIG. 26 is a circuit diagram showing a configuration example of the reset phase of the comparator according to the eleventh embodiment, and FIG. 27 is a circuit diagram showing a configuration example of the comparison phase of the comparator according to the eleventh embodiment.

[0141] In the figure, a comparator CM11 is configured by adding an NMOS transistor T10', a PMOS transistor T11', a switch W14', a switching unit K4', and a capacitor C4' to the comparator CM10 of the tenth embodiment. The other configurations of the comparator CM11 of the eleventh embodiment are the same as those of the comparator CM10 of the tenth embodiment.

[0142] The NMOS transistor T10' and the PMOS transistor T11' are connected in series. The source of the PMOS transistor T11' is connected to the power supply voltage VDD. A switch W14' is connected between the gate and drain of the PMOS transistor T11'. A capacitor C4' is connected to the gate of the PMOS transistor T11'. A switching unit K4' is connected to the gate of the NMOS transistor T10', and an output voltage VO is output from the drain of the PMOS transistor T11'.

[0143] The switching unit K4' switches the connection of the gate of the NMOS transistor T10' between the bias voltage VB3' and the drain of the NMOS transistor T4'. The switching unit K4' includes switches W12' and W13'. The switch W12' switches the input of the bias voltage VB3' to the gate of the NMOS transistor T10'. The switch W13' switches the connection between the gate of the NMOS transistor T10' and the drain of the NMOS transistor T4'.

[0144] The switches W12' and W14' receive a switching signal SN, and the switch W13' receives a switching signal SP.

[0145] In the reset phase and comparison phase of the eleventh embodiment, the operations of the AZ switches Z1, Z2 and switches W1, W2, W5, W6, W7', and W8 are similar to the operations of the AZ switches Z1, Z2 and switches W1, W2, W5, W6, W7', and W8 of the tenth embodiment described above.

[0146] In the reset phase, switches W12' and W14' are turned on based on switching signal SN, and switch W13' is turned off based on switching signal SP. A bias voltage VB3 is applied to the gate of NMOS transistor T10', causing a current to flow through NMOS transistor T10'. At this time, the voltage drop across NMOS transistor T10' is equal to the source-drain voltage Vds5 of NMOS transistor T10'.

[0147] The gate potential of the PMOS transistor T11' becomes equal to the drain potential of the PMOS transistor T11'. At this time, a charge corresponding to the drain potential of the PMOS transistor T11' is stored in the capacitor C4'.

[0148] In the comparison phase, comparator inputs DV1 and DV2 are compared by comparator CM11, and a voltage VO corresponding to the comparison result is amplified and output from comparator CM11. At this time, switches W12' and W14' are turned off based on switching signal SN, and switch W13' is turned on based on switching signal SP. The gate of NMOS transistor T10' is connected to the drain of NMOS transistor T4', and voltage VO corresponding to the drain potential of NMOS transistor T4' is output from the drain of NMOS transistor T10'.

[0149] The gate potential of the PMOS transistor T11' is equal to the bias potential generated by the capacitor C4'. Here, the PMOS transistor T11' can operate in the saturation region based on the bias potential generated by the capacitor C4'.

[0150] In this way, in the eleventh embodiment described above, in the reset phase, the NMOS transistors T3' and T4' are operated as current sources based on the bias voltage VB1, the charge that generates the bias voltage for the PMOS transistor T5' can be stored in the bias capacitor CB, the offset capacitor CF can be connected in series with the bias capacitor CB, and an amplifier is provided that amplifies the comparator output. This makes it possible to absorb imbalances in the threshold voltages of the PMOS transistors T1', T2', and T5' based on the offset voltage generated by the offset capacitor CF, and to amplify and output the comparison result of the comparator CM11.

[0151] In the eleventh embodiment, the comparator CM10 of the tenth embodiment is provided with an amplifier that amplifies and outputs the comparison result. In addition, any of the comparators CM7 to CM9 of the seventh to ninth embodiments may be provided with an amplifier that amplifies and outputs the comparison result.

[0152] 12. Twelfth Embodiment In the eleventh embodiment described above, the input signal VIN is input to the PMOS transistor T1' via the input capacitance C1, and the input signal VIP is input to the PMOS transistor T2' via the input capacitance C2. In this twelfth embodiment, the signal voltage VSI and the reference voltage VRF are input in parallel to the PMOS transistor T1' via the input capacitances, and the input of the PMOS transistor T2' is set to a fixed potential via the input capacitance C2.

[0153] FIG. 28 is a circuit diagram showing a configuration example of a reset phase of a comparator according to the twelfth embodiment, and FIG. 29 is a circuit diagram showing a configuration example of a comparison phase of a comparator according to the twelfth embodiment.

[0154] In the figure, this comparator CM12 has an input capacitor C1' instead of the input capacitor C1 of the eleventh embodiment. Also, this comparator CM12 has input capacitor C3' and capacitor C5 added to the comparator CM10 of the eleventh embodiment. Other configurations of the comparator CM12 of the twelfth embodiment are similar to the configuration of the comparator CM11 of the eleventh embodiment.

[0155] A variable capacitance can be used as the input capacitance C1'. The other configurations of the input capacitance C1' of the twelfth embodiment are the same as the configuration of the input capacitance C1 of the eleventh embodiment described above.

[0156] The input capacitor C3' can be a variable capacitor. The input capacitor C3' is connected in parallel to the input capacitor C1' with respect to the gate of the PMOS transistor T1'. At this time, the signal voltage VSI and the reference voltage VRF are input in parallel to the gate of the PMOS transistor T1' via the input capacitors C1' and C3', respectively. The capacitance values ​​of the input capacitors C1' and C3' can be set so as to balance the signal voltage VSI and the reference voltage VRF.

[0157] The capacitor C5 is connected in parallel to the NMOS transistor T4' and serves to limit the bandwidth of the output from the NMOS transistor T4'.

[0158] In the reset phase and comparison phase of the twelfth embodiment, the operations of the AZ switches Z1, Z2 and switches W1, W2, W5, W6, W7', W8, W12' to W14' are similar to the operations of the AZ switches Z1, Z2 and switches W1, W2, W5, W6, W7', W8, W12' to W14' in the eleventh embodiment described above.

[0159] In this way, in the twelfth embodiment described above, the signal voltage VSI and the reference voltage VRF are input in parallel to the PMOS transistor T1' via the input capacitors C1' and C3', respectively, and the input of the PMOS transistor T2' is set to a fixed potential via the input capacitor C2. This makes it possible to reduce the dynamic range of the differential input in the comparison phase of the comparator CM12, and to lower the power supply voltage VDD.

[0160] In the twelfth embodiment, the comparator CM10 of the tenth embodiment is provided with an amplifier that amplifies and outputs the comparison result, and the signal voltage VSI and the reference voltage VRF are input in parallel to the PMOS transistor T1' via input capacitors C1' and C3', respectively, and the input of the PMOS transistor T2' is set to a fixed potential via the input capacitor C2. Alternatively, in any of the comparators CM7 to CM9 of the seventh to ninth embodiments, an amplifier that amplifies and outputs the comparison result may be provided, and the signal voltage VSI and the reference voltage VRF may be input in parallel to one of the differential inputs, with the other differential input set to a fixed potential.

[0161] 13. Thirteenth Embodiment In the seventh embodiment described above, an offset capacitance CF is connected between the gate of the NMOS transistor T5 and the drain of the NMOS transistor T1 during the reset phase. In this thirteenth embodiment, an offset capacitance CF is connected between the gate and drain of the NMOS transistor T5 during the reset phase.

[0162] FIG. 30 is a circuit diagram showing a configuration example of the reset phase of a comparator according to the thirteenth embodiment, and FIG. 31 is a circuit diagram showing a configuration example of the comparison phase of a comparator according to the thirteenth embodiment.

[0163] In the figure, this comparator CM13 includes a switching unit K13 instead of the switching unit K3 of the seventh embodiment. The other configuration of the comparator CM13 of the thirteenth embodiment is the same as the configuration of the comparator CM7 of the seventh embodiment.

[0164] The switching unit K13 switches the connection of the offset capacitance CF between the gate and drain of the NMOS transistor T5. The switching unit K13 includes a switch W9 instead of the switch W7 of the seventh embodiment. The switch W9 switches the connection between the first terminal of the offset capacitance CF and the drain of the NMOS transistor T5. Here, the offset voltage generated by the offset capacitance CF can be set to a negative value. In this case, the relationship VOF1<VOF2 can be satisfied. The other configurations of the switching unit K3′ of the eighth embodiment are the same as those of the switching unit K3 of the seventh embodiment.

[0165] In the reset phase and comparison phase of the thirteenth embodiment, the operations of the AZ switches Z1, Z2 and switches W1, W2, W5, W6, W9, and W8 are similar to the operations of the AZ switches Z1, Z2 and switches W1, W2, W5 to W8 of the seventh embodiment described above.

[0166] 32 is a diagram showing the voltages applied to each transistor of the comparator CM13 in the reset phase and the comparison phase according to the thirteenth embodiment, where a indicates the voltage applied to each transistor of the comparator CM13 in the reset phase, and b indicates the voltage applied to each transistor of the comparator CM13 in the comparison phase.

[0167] In the reset phase, the sum of the gate-source voltage Vgs3 of the NMOS transistor T5 and the offset voltage Vof of the offset capacitance CF can be set to the minimum drain-source voltage Vds3min of the NMOS transistor T5. At this time, the offset voltage Vof of the offset capacitance CF is set to a negative level so as to cancel out the threshold voltage Vth3 of the NMOS transistor T5.

[0168] In FIG. 11B, the comparison phase is the same as that of the seventh embodiment.

[0169] FIG. 33 is a circuit diagram showing a configuration example of an offset circuit according to the thirteenth embodiment.

[0170] In the figure, the offset circuit OF2 is the same as the offset circuit OF1 of the seventh embodiment except that the NMOS transistor T26 has been removed. The drain of the PMOS transistor T23 is connected to the ground potential via a resistor R2. An offset voltage VOF1 is output from the drain of the PMOS transistor T23. The remaining configuration of the offset circuit OF2 of the thirteenth embodiment is the same as the configuration of the offset circuit OF1 of the seventh embodiment.

[0171] In this way, in the thirteenth embodiment, the offset capacitor CF is connected between the gate and drain of the NMOS transistor T5 in the reset phase, so that the imbalance in the threshold voltages of the NMOS transistors T1, T2, and T5 can be absorbed based on the offset voltage generated by the offset capacitor CF.

[0172] In the thirteenth embodiment, the connection position of the offset capacitor CF is changed in the comparator CM7 of the seventh embodiment. Alternatively, the connection position of the offset capacitor CF may be changed in any of the comparators CM7 to CM12 of the seventh to twelfth embodiments.

[0173] 14. Fourteenth Embodiment In the thirteenth embodiment described above, in the reset phase, an offset capacitance CF is connected between the gate and drain of the NMOS transistor T5, PMOS transistors T3 and T4 are used as load transistors, NMOS transistors T1 and T2 are used as differential transistors, and the NMOS transistor T5 is used as a current source transistor. In this fourteenth embodiment, NMOS transistors T3' and T4' are used as load transistors, and PMOS transistors T1', T2', and T5' are used as differential transistors and current source transistors.

[0174] FIG. 34 is a circuit diagram showing a configuration example of a reset phase of a comparator according to the fourteenth embodiment, and FIG. 35 is a circuit diagram showing a configuration example of a comparison phase of a comparator according to the fourteenth embodiment.

[0175] In the figure, this comparator CM14 includes a switching unit K13' instead of the switching unit K13 of the thirteenth embodiment. The other configuration of the comparator CM14 of the fourteenth embodiment is the same as the configuration of the comparator CM13 of the thirteenth embodiment.

[0176] The switching unit K13' switches the connection of the offset capacitance CF between the gate and drain of the PMOS transistor T5'. The switching unit K13' includes a switch W9' instead of the switch W9 of the thirteenth embodiment. The switch W9' switches the connection between the first terminal of the offset capacitance CF and the drain of the PMOS transistor T5'. Here, the offset voltage generated by the offset capacitance CF can be set to a negative value. In this case, the relationship VOF1<VOF2 can be satisfied. The other configurations of the switching unit K13' of the fourteenth embodiment are the same as those of the switching unit K13 of the thirteenth embodiment.

[0177] In the reset phase and comparison phase of the fourteenth embodiment, the operations of the AZ switches Z1, Z2 and switches W1, W2, W5, W6, W9', and W8 are similar to the operations of the AZ switches Z1, Z2 and switches W1, W2, W5, W6, W9, and W8 of the thirteenth embodiment described above.

[0178] In this way, in the above-described fourteenth embodiment, the offset capacitor CF is connected between the gate and drain of the PMOS transistor T5' in the reset phase, so that the imbalance in the threshold voltages of the PMOS transistors T1', T2', and T5' can be absorbed based on the offset voltage generated by the offset capacitor CF.

[0179] 15. Fifteenth Embodiment In the first embodiment described above, in the reset phase, the PMOS transistors T3 and T4 are operated as current sources based on the bias voltage VB1, and the charge that generates the bias voltage for the NMOS transistor T5 is stored in the bias capacitor CB. In this fifteenth embodiment, a comparator in which the power supply voltage VDD is reduced in the reset phase is applied to an imaging device.

[0180] FIG. 36 is a block diagram showing an example of the configuration of an imaging apparatus according to the fifteenth embodiment.

[0181] In the figure, the imaging device 100 includes an optical system 101, a solid-state imaging device 102, an imaging control unit 103, an image processing unit 104, a storage unit 105, a display unit 106, and an operation unit 107. The imaging control unit 103, the image processing unit 104, the storage unit 105, the display unit 106, and the operation unit 107 are connected to one another via a bus 108. The imaging device 100 may be used as a standalone device, or may be incorporated into a mobile terminal such as a smartphone, an authentication device, a monitoring device, a vehicle, or a drone.

[0182] The optical system 101 causes light from a subject to be incident on the solid-state imaging device 102, and forms an optical image on the light-receiving surface of the solid-state imaging device 102. The optical system 101 may include, for example, a focus lens, a zoom lens, and an aperture. The optical system 101 may also include multiple lenses, such as a wide-angle lens, a standard lens, and a telephoto lens.

[0183] The solid-state imaging device 102 converts an optical image formed on the light-receiving surface into an electrical signal for each pixel, digitizes the electrical signal, and outputs it. Single-slope AD conversion can be used to digitize the electrical signal. The solid-state imaging device 102 may support CDS (Correlated Double Sampling) readout or DDS (Double Data Sampling) readout. Each pixel may include a single photodiode or multiple photodiodes with different sensitivities. The solid-state imaging device 102 is, for example, a complementary metal oxide semiconductor (CMOS) image sensor. The CMOS image sensor may be a back-illuminated image sensor or a front-illuminated image sensor. The solid-state imaging device 102 may also be a lateral overflow integration capacitor (LOFIC) image sensor.

[0184] The imaging control unit 103 controls imaging by the solid-state imaging device 102 based on instructions from the operation unit 107. At this time, the imaging control unit 103 can control the exposure time, exposure amount, imaging timing, etc. of the solid-state imaging device 102.

[0185] The image processing unit 104 performs image processing based on the output from the solid-state imaging device 102. The image processing includes, for example, gamma correction, white balance processing, sharpness processing, and tone conversion processing. The image processing unit 104 may include a processor that executes processing based on software.

[0186] The storage unit 105 stores images captured by the solid-state imaging device 102 and stores imaging parameters of the solid-state imaging device 102. The storage unit 105 can also store a program that operates the imaging device 100 based on software. The storage unit 105 may include a read-only memory (ROM), a random access memory (RAM), and a memory card.

[0187] The display unit 106 displays captured images and various information that supports the image capturing operation, etc. The display unit 106 may be a liquid crystal display or an organic EL (Electro Luminescence) display.

[0188] The operation unit 107 provides a user interface for operating the imaging device 100. The operation unit 107 may include, for example, buttons, dials, and switches provided on the imaging device 100. The operation unit 107 may be configured as a touch panel together with the display unit 106.

[0189] Depending on the configuration of the imaging device 100, some of the above functions may not be present, or conversely, the imaging device 100 may further include functions that are not disclosed.

[0190] FIG. 37 is a block diagram showing an example of the configuration of a solid-state imaging device according to the fifteenth embodiment.

[0191] In the figure, the solid-state imaging device 102 includes a pixel array section 111, a vertical scanning circuit 112, a column readout circuit 113, a column signal processing section 114, a horizontal scanning circuit 115, and a control circuit 116.

[0192] The pixel array unit 111 includes a plurality of pixels PX. The pixels PX are arranged in a matrix along the row direction (also referred to as the horizontal direction) and the column direction (also referred to as the vertical direction). Each pixel PX can form a source follower with the column readout circuit 113 when reading out a signal. Each pixel PX is connected to a horizontal drive line HSL for each row and to a vertical signal line VSL for each column. The horizontal drive line HSL drives each pixel PX for each row when reading out a signal from each pixel PX. The vertical signal line VSL transmits the pixel signals read out from the pixels PX to the column signal processing unit 114 for each column.

[0193] Each pixel PX may be a single pixel, a four-pixel shared pixel, or an eight-pixel shared pixel. The pixels PX may be arranged in a Bayer array or a quad-Bayer array. The light received by each pixel PX may be visible light, near infrared light (NIR), short wavelength infrared light (SWIR), ultraviolet light, X-rays, or the like.

[0194] The vertical scanning circuit 112 scans the pixels PX to be read in the column direction. The vertical scanning circuit 112 may be configured to include a vertical register. Here, when reading out signals from each pixel PX, the vertical scanning circuit 112 can drive each pixel PX row by row via a horizontal drive line HSL.

[0195] The column readout circuit 113 can form a source follower with each pixel PX when reading out a signal from the pixel PX. At this time, the column readout circuit 113 can change the potential of the vertical signal line VSL for each column based on the charge held in each pixel PX.

[0196] The column signal processing unit 114 processes signals transmitted in the column direction from each pixel PX. For example, the column signal processing unit 114 can perform correlated double sampling (CDS) processing based on the signals transmitted in the column direction from each pixel PX. The column signal processing unit 114 can also perform AD (Analog to Digital) conversion processing based on the signals transmitted in the column direction from each pixel PX, and output an image pickup signal Gout. The column signal processing unit 114 includes a column ADC unit 114A.

[0197] The column ADC unit 114A can perform AD conversion processing in parallel for each column, based on the comparison result between the pixel signal read from the pixel PX and the reference signal REF.

[0198] The horizontal scanning circuit 115 scans the pixels PX to be read in the row direction. The horizontal scanning circuit 115 may be configured to include a horizontal register.

[0199] The control circuit 116 controls the vertical scanning circuit 112, the column readout circuit 113, the column signal processing unit 114, and the horizontal scanning circuit 115. For example, the control circuit 116 can control the scanning timing in the column direction, the scanning timing in the row direction, the operation timing of the column readout circuit 113, and the processing timing of the column signal processing unit 114. At this time, the control circuit 116 can coordinate the vertical scanning circuit 112, the column readout circuit 113, the column signal processing unit 114, and the horizontal scanning circuit 115 so that the accumulation operation, the shutter operation, and the read operation are performed for each row in each frame.

[0200] FIG. 38 is a block diagram showing an example of a circuit configuration of a pixel provided in a solid-state imaging device according to the fifteenth embodiment.

[0201] 1, a pixel PX includes a photodiode PD, a transfer transistor 122, a reset transistor 123, an amplification transistor 124, a selection transistor 125, and a floating diffusion FD. The transfer transistor 122, the reset transistor 123, the amplification transistor 124, and the selection transistor 125 can be MOS transistors.

[0202] The amplification transistor 124 and the selection transistor 125 are connected in series. The cathode of the photodiode PD is connected to the floating diffusion FD via the transfer transistor 122. The floating diffusion FD is connected to the power supply VDD via the reset transistor 123. The power supply VDD is connected to the vertical signal line VSL via the series circuit of the amplification transistor 124 and the selection transistor 125. The gate of the amplification transistor 124 is connected to the floating diffusion FD.

[0203] A transfer signal TGL is applied to the gate of the transfer transistor 122. A reset signal RST is applied to the gate of the reset transistor 123. A selection signal SEL is applied to the gate of the selection transistor 125. The transfer signal TGL, reset signal RST, and selection signal SEL can be transmitted to each pixel PX via the horizontal drive line HSL in FIG.

[0204] When the transfer transistor 122 is turned on, the charge accumulated in the photodiode PD is transferred to the floating diffusion FD. When the selection transistor 125 is turned on, the source potential of the amplification transistor 124 changes depending on the potential of the floating diffusion FD. The source potential of the amplification transistor 124 is applied to the vertical signal line VSL via the selection transistor 125 and transmitted via the vertical signal line VSL. When the reset transistor 123 is turned on, the charge accumulated in the floating diffusion FD is discharged.

[0205] 39 is a block diagram showing a configuration example of a signal readout unit according to the fifteenth embodiment. Although the diagram shows vertical signal lines VSL1 and VSL2 for two columns, the present invention can be similarly applied to a case where there are more vertical signal lines.

[0206] In the figure, pixels PX1 and PX2 are connected to vertical signal lines VSL1 and VSL2, respectively. At this time, the amplification transistors 124 of the pixels PX1 and PX2 are connected to the vertical signal lines VSL1 and VSL2 via selection transistors 125, respectively.

[0207] The column readout circuit 113 includes current sources LM1 and LM2. The current sources LM1 and LM2 are provided for each column. Each current source LM1 and LM2 is connected to a vertical signal line VSL1 or VSL2, respectively. During signal readout, each current source LM1 or LM2 can form a source follower with each pixel PX1 or PX2 via the vertical signal line VSL1 or VSL2, respectively. Each current source LM1 or LM2 may be a MOS transistor.

[0208] The column ADC unit 114A includes comparators CP1 and CP2 and counters CN1 and CN2 for each column. The comparator CP1 compares a pixel signal transmitted via a vertical signal line VSL1 with a reference signal REF. The comparator CP2 compares a pixel signal transmitted via a vertical signal line VSL2 with the reference signal REF.

[0209] An auto-zero signal AZ is input to each comparator CP1 and CP2. The auto-zero signal AZ activates the auto-zero operation during the auto-zero period. At this time, a DC-blocking capacitor CA1 is connected to the non-inverting input terminal of the comparator CP1, and a DC-blocking capacitor CB1 is connected to the inverting input terminal. Furthermore, a DC-blocking capacitor CA2 is connected to the non-inverting input terminal of the comparator CP2, and a DC-blocking capacitor CB2 is connected to the inverting input terminal.

[0210] Each of the comparators CP1 and CP2 may be any of the comparators CM1 to CM14 in the first to fourteenth embodiments.

[0211] In the auto-zero operation, the charges stored in the DC blocking capacitors CA1 and CB1 are controlled so that the non-inverting input and the inverting input of the comparator CP1 are balanced, and in the auto-zero operation, the charges stored in the DC blocking capacitors CA2 and CB2 are controlled so that the non-inverting input and the inverting input of the comparator CP2 are balanced.

[0212] Each counter CN1, CN2 performs a counting operation for each column until the level of the pixel signal read from each pixel PX1, PX2 matches the level of the ramp wave of the reference signal REF, and holds the digital values ​​D1, D2 of the pixel signal read from each pixel PX1, PX2 for each column. At this time, the pixel signals read from each pixel PX1, PX2 can be digitized for each row in each comparator CP1, CP2. The digital values ​​D1, D2 held in each counter CN1, CN2 can be updated for each row.

[0213] At this time, in each comparator CP1, CP2, during an AD conversion period provided in each horizontal scanning period, the pixel signals read out from each pixel PX1, PX2 are compared with the ramp wave included in the reference signal REF for each column. Then, based on the comparison results of each comparator CP1, CP2 during that AD conversion period, digital values ​​D1, D2 of the pixel signals read out from each pixel PX1, PX2 are held in each counter CN1, CN2.

[0214] 40 is a timing chart showing an example of waveforms at various parts during signal readout of the solid-state imaging device according to the fifteenth embodiment. Note that the figure shows an example of waveforms within a 1H period (one horizontal synchronization period).

[0215] In the figure, the reset signal RST rises (t1), turning on the reset transistor 123 and resetting the floating diffusion 126. Also, the selection signal SEL rises, turning on the selection transistor 125. At this time, the potentials of the vertical signal lines VSL1 and VSL2 are set based on the source follower operation when the power supply voltage VDD is applied to the gate of the amplification transistor 124.

[0216] Next, the reset signal RST falls (t2), turning off the reset transistor 123. At this time, the potentials of the vertical signal lines VSL1 and VSL2 are set based on the source follower operation when the P-phase level of the floating diffusion 126 is applied to the gate of the amplification transistor 124.

[0217] Next, in each comparator CP1, CP2, the potential of each vertical signal line VSL1, VSL2 corresponding to the P-phase level is compared with a reference signal REF, and the timing when the level of the reference signal REF matches the potential of each vertical signal line VSL1, VSL2 is output as the comparison result. At this time, the P-phase level read out from the pixel PX is AD converted for each column based on the count operation until the level of the reference signal REF matches the potential of each vertical signal line VSL1, VSL2.

[0218] Next, when the transfer signal TGL rises (t3), the transfer transistor 122 is turned on and the charge accumulated in the photodiode 121 is transferred to the floating diffusion 126. At this time, the potentials of the vertical signal lines VSL1 and VSL2 are set based on the source follower operation when the cathode potential of the photodiode 121 is applied to the gate of the amplification transistor 124.

[0219] Next, when the transfer signal TGL falls (t4), the transfer transistor 122 is turned off. At this time, the potentials of the vertical signal lines VSL1 and VSL2 are set based on the source follower operation when the D-phase level of the floating diffusion 126 is applied to the gate of the amplification transistor 124.

[0220] Next, in each comparator CP1, CP2, the potential of each vertical signal line VSL1, VSL2 corresponding to the D-phase level is compared with the reference signal REF, and the timing when the level of the reference signal REF matches the potential of each vertical signal line VSL1, VSL2 is output as the comparison result. At this time, the D-phase level read out from the pixel PX is AD converted for each column based on the count operation until the level of the reference signal REF matches the potential of each vertical signal line VSL1, VSL2.

[0221] As described above, in the fifteenth embodiment, any one of the comparators CM1 to CM14, in which the power supply voltage VDD in the reset phase is reduced, is applied to the solid-state imaging device 102. This allows the power supply voltage VDD of the column ADC unit 114A to be reduced, thereby reducing power consumption.

[0222] 16. Application Examples to Mobile Bodies The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0223] FIG. 41 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0224] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 41 , the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053.

[0225] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0226] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0227] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0228] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0229] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0230] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0231] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0232] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0233] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying information to vehicle occupants or the outside of the vehicle. In the example of Fig. 41, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0234] FIG. 42 is a diagram showing an example of the installation position of the imaging unit 12031.

[0235] In FIG. 42, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0236] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0237] 42 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0238] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0239] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which runs autonomously without relying on driver operation.

[0240] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0241] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0242] The above describes an example of a vehicle control system to which the technology according to the present disclosure can be applied. The technology according to the present disclosure can be applied to the imaging unit 12031 of the above-described configuration. Specifically, for example, each comparator in the above-described embodiment can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the vehicle control system 12000, the power supply voltage VDD of the imaging unit 12031 can be lowered, thereby reducing power consumption.

[0243] Note that the above-described embodiment shows an example for realizing the present technology, and the matters in the embodiment and the matters specifying the invention in the claims correspond to each other. Similarly, the matters specifying the invention in the claims and the matters in the embodiment of the present technology with the same title correspond to each other. However, the present technology is not limited to the embodiment, and can be realized by applying various modifications to the embodiment within the scope of the gist. Furthermore, the effects described in this specification are merely examples and are not limited, and other effects may also be present.

[0244] The present technology may also be configured as follows: (1) A comparator comprising: a first transistor having a gate to which a first input is applied; a second transistor having a gate to which a second input is applied; a third transistor connected in series with the first transistor; a fourth transistor connected in series with the second transistor and having a gate connected to a gate of the third transistor; a fifth transistor connected to the first transistor and the second transistor; a bias capacitor connected to the gate of the fifth transistor; and a first switching unit that switches the connection of the gates of the third transistor and the fourth transistor between a first bias voltage and the drain of the third transistor. (2) The comparator according to (1), further comprising: a second switching unit that switches the connection between the gate of the fifth transistor and the drain of the first transistor or the second transistor. (3) The comparator according to (2), wherein the first switching unit includes a first switch that switches the input of a first bias voltage to the gate of the third transistor and a second switch that switches the connection between the gate and drain of the third transistor, and the second switching unit includes a third switch that switches the connection between the gate of the fifth transistor and the drain of the third transistor. (4) The comparator according to (3), wherein the second switching unit further includes a fourth switch that switches the connection between the gate of the fifth transistor and the drain of the fourth transistor. (5) The comparator according to (4), wherein in a reset phase, the first switch, the third switch, and the fourth switch are turned on and the second switch is turned off, and in a comparison phase, the first switch, the third switch, and the fourth switch are turned off and the second switch is turned on. (6) The comparator according to any of (1) to (5), further including an offset capacitor connected in series with the bias capacitor, and a third switching unit that switches the connection between the offset capacitor and the bias capacitor.(7) The comparator according to (6), wherein the third switching unit comprises: a fifth switch that switches the input of a first offset voltage to a first terminal of the offset capacitor; a sixth switch that switches the input of a second offset voltage to a second terminal of the offset capacitor; a seventh switch that switches the connection between the offset capacitor and the bias capacitor; and an eighth switch that switches the connection between the first terminal of the offset capacitor and the drain of the first transistor or the second transistor. (8) The comparator according to (7), further comprising: a first dummy transistor that operates as a dummy for the first transistor and generates the first offset voltage; and a second dummy transistor that operates as a dummy for the fifth transistor and generates the second offset voltage. (9) The comparator according to (6), wherein the third switching unit comprises: a fifth switch that switches the input of the first offset voltage to the first terminal of the offset capacitor; a sixth switch that switches the input of the second offset voltage to the second terminal of the offset capacitor; a seventh switch that switches the connection between the offset capacitor and the bias capacitor; and a ninth switch that switches the connection between the first terminal of the offset capacitor and the drain of the fifth transistor. (10) The comparator according to (8), wherein the first offset voltage is lower than the second offset voltage. (11) The comparator according to (10), further comprising: a mirror transistor that generates the first offset voltage based on a current mirror operation; and a second dummy transistor that operates as a dummy for the fifth transistor and generates the second offset voltage. (12) The comparator according to any one of (1) to (11), further comprising: a first AZ (Auto Zero) switch connected between the gate and drain of the first transistor; and a second AZ switch connected between the gate and drain of the second transistor. (13) The comparator according to (12), further comprising: a first input capacitance connected in series with the gate of the first transistor; and a second input capacitance connected in series with the gate of the second transistor.(14) The comparator according to (13), further comprising a third input capacitor connected in parallel to the first input capacitor with respect to the gate of the first transistor. (15) The comparator according to (14), in which a signal voltage is input to the first input capacitor, a fixed voltage is input to the second input capacitor, and a reference voltage is input to the third input capacitor. (16) The comparator according to any of (1) to (15), further comprising: a tenth transistor whose gate is connected to the drain of the second transistor; an eleventh transistor connected in series with the tenth transistor; and a fourth switching unit that switches the connection of the gate of the tenth transistor. (17) The comparator according to (16), in which the fourth switching unit further comprises: a twelfth switch that switches the input of a second bias voltage to the gate of the tenth transistor; and a sixth switch that switches the connection between the drain of the second transistor and the gate of the tenth transistor. (18) An imaging device comprising: a pixel array unit in which pixels are arranged in a matrix in row and column directions; and a column ADC unit that performs AD (Analog to Digital) conversion for each column of pixel signals output from the pixels, wherein the column ADC unit comprises a comparator that compares the pixel signals with a reference signal, wherein the comparator comprises: a first transistor to which a first input is applied at a gate, a second transistor to which a second input is applied at a gate, a third transistor connected in series with the first transistor, a fourth transistor connected in series with the second transistor and having a gate connected to the gate of the third transistor, a fifth transistor connected to the first transistor and the second transistor, a bias capacitor connected to the gate of the fifth transistor, and a first switching unit that switches connection of the gates of the third transistor and the fourth transistor between a first bias voltage and a drain of the third transistor. (19) The imaging device according to (18), wherein the comparator further comprises a second switching unit that switches connection between the gate of the fifth transistor and the drain of the first transistor or the second transistor.(20) The imaging device described in (18) or (19), wherein the comparator further includes an offset capacitor connected in series to the bias capacitor, and a third switching unit that switches the connection between the offset capacitor and the bias capacitor.

[0245] CM1 Comparator K1, K2 Switching section T1, T2, T5 NMOS transistors T3, T4 PMOS transistors W1 to W4 Switches CB Bias capacitance Z1, Z2 AZ switch C1, C2 Input capacitance

Claims

1. A comparator comprising: a first transistor having a gate to which a first input is applied; a second transistor having a gate to which a second input is applied; a third transistor connected in series with the first transistor; a fourth transistor connected in series with the second transistor and having a gate connected to the gate of the third transistor; a fifth transistor connected to the first transistor and the second transistor; a bias capacitor connected to the gate of the fifth transistor; and a first switching unit that switches the connection of the gates of the third transistor and the fourth transistor between a first bias voltage and the drain of the third transistor.

2. The comparator according to claim 1, further comprising a second switching section that switches the connection between the gate of the fifth transistor and the drain of the first transistor or the second transistor.

3. A comparator as described in claim 2, wherein the first switching unit includes a first switch that switches the input of a first bias voltage to the gate of the third transistor, and a second switch that switches the connection between the gate and drain of the third transistor, and the second switching unit includes a third switch that switches the connection between the gate of the fifth transistor and the drain of the third transistor.

4. The comparator according to claim 3, wherein the second switching section further comprises a fourth switch that switches the connection between the gate of the fifth transistor and the drain of the fourth transistor.

5. The comparator according to claim 4, wherein in a reset phase, the first switch, the third switch, and the fourth switch are turned on and the second switch is turned off, and in a comparison phase, the first switch, the third switch, and the fourth switch are turned off and the second switch is turned on.

6. The comparator according to claim 1, further comprising: an offset capacitor connected in series to the bias capacitor; and a third switching unit that switches the connection between the offset capacitor and the bias capacitor.

7. The comparator according to claim 6, wherein the third switching unit comprises: a fifth switch that switches the input of a first offset voltage to a first terminal of the offset capacitance; a sixth switch that switches the input of a second offset voltage to a second terminal of the offset capacitance; a seventh switch that switches the connection between the offset capacitance and the bias capacitance; and an eighth switch that switches the connection between the first terminal of the offset capacitance and the drain of the first transistor or the second transistor.

8. The comparator according to claim 7, further comprising: a first dummy transistor that operates as a dummy for the first transistor and generates the first offset voltage; and a second dummy transistor that operates as a dummy for the fifth transistor and generates the second offset voltage.

9. The comparator according to claim 6, wherein the third switching unit comprises: a fifth switch that switches the input of a first offset voltage to a first terminal of the offset capacitance; a sixth switch that switches the input of a second offset voltage to a second terminal of the offset capacitance; a seventh switch that switches the connection between the offset capacitance and the bias capacitance; and a ninth switch that switches the connection between the first terminal of the offset capacitance and the drain of the fifth transistor.

10. The comparator of claim 9, wherein the first offset voltage is lower than the second offset voltage.

11. The comparator according to claim 10, further comprising: a mirror transistor that generates the first offset voltage based on a current mirror operation; and a second dummy transistor that operates as a dummy for the fifth transistor and generates the second offset voltage.

12. The comparator according to claim 1, further comprising: a first AZ (Auto Zero) switch connected between the gate and drain of the first transistor; and a second AZ switch connected between the gate and drain of the second transistor.

13. The comparator of claim 12, further comprising: a first input capacitance connected in series with the gate of the first transistor; and a second input capacitance connected in series with the gate of the second transistor.

14. The comparator of claim 13, further comprising a third input capacitance connected in parallel with the first input capacitance to the gate of the first transistor.

15. The comparator according to claim 14, wherein a signal voltage is input to the first input capacitance, a fixed voltage is input to the second input capacitance, and a reference voltage is input to the third input capacitance.

16. The comparator according to claim 1, further comprising: a tenth transistor whose gate is connected to the drain of the second transistor; an eleventh transistor connected in series with the tenth transistor; and a fourth switching unit that switches the connection of the gate of the tenth transistor.

17. The comparator according to claim 16, wherein the fourth switching unit further comprises: a twelfth switch that switches the input of a second bias voltage to the gate of the tenth transistor; and a thirteenth switch that switches the connection between the drain of the second transistor and the gate of the tenth transistor.

18. An imaging device comprising: a pixel array section in which pixels are arranged in a matrix in row and column directions; and a column ADC section that performs AD (Analog to Digital) conversion for each column of pixel signals output from the pixels, wherein the column ADC section comprises a comparator that compares the pixel signals with a reference signal, wherein the comparator comprises: a first transistor to whose gate a first input is applied; a second transistor to whose gate a second input is applied; a third transistor connected in series with the first transistor; a fourth transistor connected in series with the second transistor and whose gate is connected to the gate of the third transistor; a fifth transistor connected to the first transistor and the second transistor; a bias capacitor connected to the gate of the fifth transistor; and a first switching section that switches the connection of the gates of the third transistor and the fourth transistor between a first bias voltage and the drain of the third transistor.

19. The imaging device according to claim 18, wherein the comparator further comprises a second switching unit that switches the connection between the gate of the fifth transistor and the drain of the first transistor or the drain of the second transistor.

20. The imaging device according to claim 18, wherein the comparator further comprises: an offset capacitor connected in series to the bias capacitor; and a third switching unit that switches the connection between the offset capacitor and the bias capacitor.

Images