Display device and electronic equipment

Abstract

One purpose of the present invention is to provide a display device and an electronic equipment that are capable of improving image quality, for example.　The display device has: a plurality of pixels arranged in a prescribed direction; a plurality of signal lines connected to the plurality of pixels; a drive unit that generates pixel signals to be outputted to the plurality of signal lines; and a switch unit that switches states of connection between the drive unit and each of the plurality of signal lines. The drive unit has a first drive unit and a second drive unit, and controls the switch unit such that the first drive unit and the second drive unit are separately assigned to each group of prescribed adjacent pixels.

Description

Display devices and electronic devices

[0001] The present technology relates to a display device and an electronic device.

[0002] A display device employing a division drive method, in which the display unit is divided into multiple regions and each region is driven individually, is known. However, this type of display device has a problem in that streaky or band-like images are visible due to differences in the appearance of each region.

[0003] The following Patent Document 1 discloses a technology for scattering image quality problems that occur in the form of vertical stripes by placing a first source driver on the upper side of the screen and a second source driver on the lower side, dividing the screen horizontally, and alternately performing writing operations on each divided area using the first source driver and the second source driver.

[0004] Japanese Patent Application Laid-Open No. 2003-280613

[0005] However, in Patent Document 1, as described above, the screen is divided into left and right regions, and each region is alternately driven by the first source driver and the second source driver, and the improvement in image quality is not sufficient.

[0006] An object of the present technology is to provide, for example, a display device and an electronic device that can improve image quality.

[0007] The present technology provides a display device that includes, for example, a plurality of pixels arranged in a predetermined direction, a plurality of signal lines connected to each of the plurality of pixels, a drive unit that generates pixel signals to be output to the plurality of signal lines, and a switch unit that switches a connection state between the drive unit and each of the plurality of signal lines, wherein the drive unit has a first drive unit and a second drive unit, and controls the switch unit so that the first drive unit and the second drive unit are allocated to each group of predetermined adjacent pixels.

[0008] The present technology relates to, for example, an electronic device having a display device of the present technology.

[0009] FIG. 1 is a diagram illustrating a configuration example of a display device applicable to an embodiment of the present technology. FIG. 2 is a diagram illustrating a configuration example (Configuration Example 1) of a horizontal driver. FIG. 3 is a diagram illustrating a configuration example (Configuration Example 2) of a horizontal driver. FIG. 4 is a diagram illustrating a configuration example (Configuration Example 1) of a vertical driver. FIG. 5 is a diagram illustrating a configuration example (Configuration Example 2) of a vertical driver. FIG. 6 is a diagram illustrating an operation example of a display device in a comparative example. FIG. 7 is an image diagram illustrating a vertical band phenomenon. FIG. 8 is an image diagram illustrating a time offset method. FIG. 9 is a diagram illustrating a specific configuration example of a display device according to an embodiment. FIG. 10 is an example of a timing chart related to control of a horizontal driver. FIG. 11A is a diagram illustrating a configuration example in which a horizontal logic unit controls switches, and FIG. 11B is a diagram illustrating a configuration example in which an external device controls switches. A diagram illustrating an operation example (Operation Example 1) of the display device. A diagram illustrating an operation example (Operation Example 1) of the display device. FIG. 14 is a diagram illustrating an operation example (Operation Example 2) of the display device. FIG. 15 is a diagram illustrating an operation example (Operation Example 2) of the display device. FIG. 16 is a diagram illustrating an operation example (Operation Example 2) of the display device. FIG. 17 is a diagram showing an operation example (Operation Example 3) of the display device. FIG. 18 is a diagram showing an operation example (Operation Example 4) of the display device. FIG. 19 is a diagram showing an operation example (Operation Example 5) of the display device. FIG. 20 is a diagram showing an operation example (Operation Example 5) of the display device. FIG. 21 is a diagram showing an operation example (Operation Example 5) of the display device. FIG. 22 is a diagram showing an operation example (Operation Example 5) of the display device. FIG. 23 is a diagram showing an operation example (Operation Example 5) of the display device. FIG. 24 is a diagram showing an operation example (Operation Example 5) of the display device. FIG. 25 is a diagram showing a specific configuration example of a ramp processing unit. FIG. 26 is a detailed configuration example of an amplifier. FIG. 27 is a timing chart showing an operation example of a ramp processing circuit. FIG. 28 is a diagram explaining the offset cancellation operation of an integrator. FIG. 29 is a diagram explaining the offset cancellation operation of a Q-V conversion circuit. FIG. 30 shows another configuration example of an amplifier. FIG. 31 is a diagram showing an example configuration of a pixel circuit. FIG. 32 is a diagram showing an example configuration of a pixel circuit. FIG. 33 is a diagram showing an example configuration of a pixel circuit. 34 and 35 are diagrams showing examples of the configuration of a pixel circuit.FIG. 36 is a diagram showing an example of the configuration of a pixel circuit. FIG. 37 is a diagram showing an example of the configuration of a pixel circuit. FIG. 38 is a diagram showing an example of the configuration of a pixel circuit. FIG. 39 is a diagram showing an example of the configuration of a pixel circuit. FIG. 40 is a diagram showing an example of the configuration of a pixel circuit. FIG. 41 is a perspective view showing an example of the appearance of a head mounted display. FIG. 42 is a perspective view showing an example of the appearance of another head mounted display. FIG. 43A is a front view showing an example of the appearance of a digital still camera. FIG. 43B is a rear view showing an example of the appearance of a digital still camera. FIG. 44 is a perspective view showing an example of the appearance of a television device. FIG. 45 is a perspective view showing an example of the appearance of a smartphone. FIG. 46A is a diagram showing an example of the interior of a vehicle from the rear to the front of the vehicle. FIG. 46B is a diagram showing an example of the interior of a vehicle from diagonally rear to diagonally front of the vehicle.

[0010] Hereinafter, embodiments of the present technology will be described with reference to the drawings. The description will be made in the following order. In this specification and the drawings, components having substantially the same function or configuration will be assigned the same reference numerals, and redundant description will be omitted as appropriate. Furthermore, the shapes, sizes, positional relationships, etc. of components shown in each drawing may be exaggerated depending on the content of the description, and reference numerals may be omitted to avoid cluttering the illustrations. <1. Overview of the embodiments of the present technology> <2. Previous problems> <3. One embodiment> <4. Example configuration of a pixel circuit> <5. Modified example> <6. Application example>

[0011] 1. Overview of an embodiment of the present technology 1-1. Example of overall configuration of a display device FIG. 1 is a diagram showing an example of the configuration of a display device 1 applicable to an embodiment of the present technology. The display device 1 is a device that displays various information such as images using light-emitting elements. The light-emitting elements are, for example, LEDs (Light Emitting Diodes). LEDs include LEDs used in micro LED displays and OLEDs (Organic Light Emitting Diodes) used in organic EL (Electro-Luminescence) displays. Hereinafter, the display device 1 will be described as employing OLEDs as light-emitting elements. The display device 1 is, for example, a display mounted in an electronic device. Specific examples of electronic devices to which the display device 1 can be applied will be described later.

[0012] The display device 1 has, as circuit blocks, an input / output unit (IO) 2, a gamma processing unit 3, a power supply processing unit 4, an interface unit (IF) 5, an oscillator unit 6, a buffer 7, a timing controller (TCON) 8, a pixel unit 9, a horizontal driver 10, and a vertical driver 11. The horizontal driver 10 has a horizontal logic unit (HLOGIC) 12 and a horizontal analog unit (HANALOG) 13, and the vertical driver 11 has a vertical logic unit (VLOGIC) 14 and a vertical analog unit (VANALOG) 15. The display device 1 has these circuit blocks mounted on a substrate, for example. The substrate includes, for example, a semiconductor substrate such as silicon.

[0013] The input / output unit 2 inputs and outputs various data and is configured, for example, by an externally connectable FPC (Flexible Printed Circuits). The input / output unit 2 is connected to the gamma processing unit 3, the power supply processing unit 4, and the interface unit 5. The gamma processing unit 3 performs gamma correction processing. The gamma processing unit 3 is connected to the input / output unit 2 and the horizontal analog unit 13, and sets gamma correction based on a setting value for gamma correction input via the input / output unit 2, and gamma-corrects the pixel signal output from the horizontal analog unit 13 to the pixel unit 9.

[0014] The power supply processing unit 4 is a circuit that outputs power for driving the pixel unit 9 and is configured to include, for example, an LDO (Low Drop Out) regulator. The power supply processing unit 4 is connected to the input / output unit 2 and the pixel unit 9, and converts the supply power input via the input / output unit 2 into a power supply voltage for driving the pixel unit 9 and supplies it to the pixel unit 9. The interface unit 5 is connected to the input / output unit 2, the oscillator unit 6, the buffer 7, and the timing controller 8. The interface unit 5 is an interface for inputting and outputting image data and the like to and from the outside via the input / output unit 2. For example, a high-speed interface standard such as MIPI (Mobile Industry Processor Interface) can be adopted as this interface.

[0015] The oscillator 6 is configured, for example, by an oscillator circuit (OSC) and generates various clock signals. The oscillator 6 is connected to the interface 5, buffer 7, and timing controller 8, and supplies the generated clock signals to each component. The buffer 7 is configured, for example, by a line buffer that holds image data for one horizontal line of an image. The buffer 7 is connected to the interface 5, oscillator 6, and timing controller 8, and sequentially buffers and outputs image data based on the clock signals generated by the oscillator 6.

[0016] The timing controller 8 controls the timing of the operation of each block. The timing controller 8 is connected to the interface unit 5, the oscillator unit 6, the buffer 7, the horizontal logic unit 12, the horizontal analog unit 13, the vertical logic unit 14, and the vertical analog unit 15. The timing controller 8 outputs image data output by the buffer 7 to the horizontal logic unit 12 based on a clock signal generated by the oscillator unit 6, and outputs control signals as needed to the horizontal logic unit 12 and the horizontal analog unit 13. The timing controller 8 also outputs control signals as needed to the vertical logic unit 14 and the vertical analog unit 15 based on the clock signal generated by the oscillator unit 6. For example, the timing controller 8 outputs start pulses WSST1, DSST, and AZST to the vertical logic unit 14.

[0017] Although not shown here, the pixel unit 9 has a plurality of pixels (pixel circuits) arranged in a matrix of m rows and n columns (m and n are natural numbers), forming a pixel region. The pixel arrangement may be other than a matrix. For example, the pixels may be arranged along two intersecting directions. The pixel unit 9 includes pixels representing the three primary colors, R (red), G (green), and B (blue), to represent a color image. The color representation of the image is not limited to this, and may be configured to represent a monochrome (black and white) image, for example. The pixel configuration of the pixel unit 9 is not limited to a specific one. Specific examples of applicable pixel configurations and operation examples will be described later.

[0018] The pixel unit 9 has signal lines extending along the column direction of the pixel array and control lines extending along the row direction of the pixel array. One signal line is provided for each pixel column, and one control line is provided for each pixel row. Each signal line is connected to the output terminal of the corresponding column of the horizontal analog unit 13 and the pixel group of the corresponding column. A pixel signal SIG is supplied to each signal line. Each control line is connected to the output terminal of the corresponding row of the vertical analog unit 15 and the pixel group of the corresponding row. For example, there are three types of control lines: a control line supplied with a control signal WS, a control line supplied with a control signal DS, and a control line supplied with a control signal AZ. Note that in FIG. 1 , the signal line and the control line are each represented by a single representative line. Specifically, the control signal WS controls the writing of the pixel signal SIG to the pixel, the control signal DS controls the light emission of the pixel, and the control signal AZ appropriately initializes the pixel. More specifically, the control signals WS, DS, and AZ perform their respective controls by switching their voltage levels (for example, switching between a low voltage and a high voltage). Note that the types of signal lines connected to the horizontal analog unit 13 and control lines connected to the vertical analog unit 15 are not limited to specific types, but are changed as appropriate depending on the pixel configuration of the pixel unit 9.

[0019] The horizontal driver 10 is configured with a RAMPDAC circuit that uses a ramp waveform analog signal to generate the pixel signal SIG to be output to the signal line. The horizontal logic unit 12 distributes the image data input from the timing controller 8 to each signal line. The horizontal analog unit 13 converts the distributed image data into a gamma-corrected pixel signal SIG and outputs it to the corresponding signal line of the pixel unit 9. The configuration of the horizontal driver 10 is not limited to a specific one, and may be, for example, a voltage follower circuit having a voltage follower circuit in the output section to the signal line. Specific configuration and operation examples of the horizontal driver 10 will be described later.

[0020] The vertical driver 11 is configured as a shift register type circuit having a shift register circuit in a signal input section. The vertical logic section 14 generates shift signals (e.g., shift signals WSSR, DSSR, AZSR) from start pulses (e.g., start pulses WSST1, DSST, AZST). The vertical analog section 15 generates control signals (e.g., control signals WS, DS, AZ) from the shift signals and outputs them to the pixel section 9. The configuration of the vertical driver 11 is not limited to a specific one, and may be, for example, a circuit of an address decoder type having an address decoder in a signal input section. Specific configuration examples and operation examples of the vertical driver 11 will be described later.

[0021] [1-2. Configuration Examples of Horizontal Driver] (Configuration Example 1) Fig. 2 is a diagram showing a configuration example (Configuration Example 1) of the horizontal driver 10. The horizontal driver 10 shown in Fig. 2 is configured with a RAMPDAC-type circuit that uses a ramp waveform analog signal to generate the pixel signal SIG to be output to the signal line SGL. The horizontal logic unit 12 that constitutes this horizontal driver 10 has a shift register unit (S / R) 21, a 1ST latch unit 22, a 2ND latch unit 23, a synchronous counter 24, a DLL (delay-locked loop) circuit 25, a comparator unit 26, and a PWM generation unit 27.

[0022] The shift register unit 21 sequentially shifts image data (DATA) input from the timing controller 8 and outputs it as pixel data of a number corresponding to the number n of pixels in the row direction (for example, N-1=n). The 1st latch unit 22 is made up of the corresponding number of 1st latch circuits 22A described above, and latches each piece of pixel data input from the shift register unit 21 based on the latch clock LATCLK. The 2nd latch unit 23 is made up of the corresponding number of 2nd latch circuits 23A described above, and line-sequentially arranges each piece of latched data of the 1st latch circuits 22A based on the line pulse LINECLK.

[0023] The synchronous counter 24 receives a main clock signal MCLK from the timing controller 8 via a DLL (delay-locked loop) circuit 25. The synchronous counter 24 counts down or up in synchronization with the main clock signal MCLK and outputs a signal representing the count result.

[0024] The comparator unit 26 is composed of a corresponding number of digital comparators 26A as described above. Each digital comparator 26A compares the latch data of each 2nd latch circuit 23A with the output from the synchronous counter 24 and outputs the comparison result. The PWM generation unit 27 is composed of a corresponding number of PWM generation circuits 27A as described above. Each PWM generation circuit 27A generates a PWM (pulse width) signal corresponding to the gradation data of each pixel PIX (see FIG. 9, etc.) in response to a start pulse RAMPST input from the timing controller 8. The generated PWM signal is output to the horizontal analog unit 13. As a result, an 8-bit, 10-bit, 12-bit, etc. signal is converted into a signal having a width corresponding to the data and input to the horizontal analog unit 13.

[0025] The horizontal analog unit 13 constituting the horizontal driver 10 shown in FIG. 2 includes a level shifter unit 28, a ramp processing unit 29, and a switch unit 30. The level shifter unit 28 is composed of the same number of level shifter circuits 28A as described above, and converts the levels of the PWM signals converted by each PWM generation circuit 27A into signals of drive levels (voltage levels). This signal is used to control the PWM switches 30A in the switch unit 30. The ramp processing unit 29 generates a ramp signal whose voltage level changes over time and outputs it to the switch unit 30 via a ramp wiring RL. In this way, the ramp signal generated by the ramp processing unit 29 is supplied to the ramp wiring RL. Although not described here, the ramp processing unit 29 also functions as a gamma correction circuit, for example, and outputs a ramp voltage that has been gamma-corrected based on a setting value input from the gamma processing unit 3.

[0026] The switch unit 30 is composed of the corresponding number of PWM switches 30A described above. Each PWM switch 30A is provided between a signal line SGL connected to a pixel PIX of the pixel unit 9 and a ramp line RL, and controls the connection between the ramp line RL and the corresponding signal line SGL. Specifically, each PWM switch 30A samples the ramp waveform by turning off (closing) at a timing corresponding to the gradation to be written to the pixel PIX in accordance with the output voltage of each level shifter circuit 28A, and determines the signal voltage to be written to the pixel.

[0027] (Configuration Example 2) Fig. 3 is a diagram showing a configuration example (Configuration Example 2) of the horizontal driver 10. The horizontal driver 10 shown in Fig. 3 is configured as a voltage follower circuit having a voltage follower circuit in the output section to each signal line SGL. The horizontal logic section 12 constituting this horizontal driver 10 has the above-mentioned shift register section (S / R) 21, 1ST latch section 22, and 2ND latch section 23. In addition, the horizontal analog section 13 constituting this horizontal driver 10 has a level shifter section 31, DAC section 32, and output buffer section 33.

[0028] The level shifter unit 31 is composed of a group of level shifter circuits (not shown) and converts the level of each pixel data line-sequentially processed by the 2ND latch circuit 23A from a logic level to analog level data corresponding to the drive level. The DAC unit 32 is composed of multiple DAC (Digital-to-Analog Converter) circuits 32A and receives a grayscale voltage corresponding to the gamma resistance set by the gamma resistor unit 34, and converts the image data level-converted by each level shifter circuit from digital data to analog data. The output buffer unit 33 is composed of a voltage follower made up of multiple operational amplifiers 33A and demultiplexers 33B and outputs pixel signals SIG converted by each DAC circuit 32A to signal lines SGL connected to each pixel PIX of the pixel unit 9 in a time-division manner during each horizontal period.

[0029] As mentioned above, the configuration of the horizontal driver 10 is not limited to that shown in FIGS. 2 and 3, but can be modified as appropriate.

[0030] [1-3. Configuration Examples of Vertical Driver] (Configuration Example 1) Fig. 4 is a diagram showing a configuration example (Configuration Example 1) of the vertical driver 11. The vertical driver 11 shown in Fig. 4 is configured as a shift register type circuit having a shift register circuit in a signal input section. The vertical logic section 14 constituting this vertical driver 11 has a shift register section 41 and a logic circuit section 42. In addition, the vertical analog section 15 has a level shifter section 51 and an output buffer section 52.

[0031] The shift register unit 41 is composed of shift registers 41A whose number (e.g., m) corresponds to the number m of pixels in the column direction, and a start pulse VST is synchronized with a clock signal CLK, propagated in sequence, and output as shift signals SR0, SR1, ... in sequence for each row.

[0032] The logic circuit section 42 is composed of the corresponding number of logic circuits (LOGIC) 42A described above, and performs logical operations as needed in response to input control signals (not shown). The level shifter section 51 is composed of the corresponding number of level shifters 51A described above, and converts the levels of the signals SR0, SR1, ... that have undergone logical operations into drive level signals (control signals). The output buffer section 52 is composed of the corresponding number of buffer circuits 52A described above, and buffers and outputs the control signals.

[0033] (Configuration Example 2) Fig. 5 is a diagram showing a configuration example (Configuration Example 2) of the vertical driver 11. This vertical driver 11 has an address decoder 40 instead of the shift register unit 41 of the vertical driver 11 shown in Fig. 4. In this way, the vertical driver 11 shown in Fig. 5 is configured as an address decoder type circuit having the address decoder 40 in the signal input unit. Other configurations are the same as those of the vertical driver 11 in Fig. 4.

[0034] The address decoder 40 decodes the address based on the address information COUNT supplied from the timing controller 8, and outputs the decoded result in correspondence with the logic circuit 42A of each row. The shift register section 41 described above is configured to always shift in a predetermined order, such as from top to bottom or from bottom to top, but the address decoder 40 can sequentially specify and scan between predetermined addresses, such as incrementing from an arbitrary address to a certain address.

[0035] As mentioned above, the configuration of the vertical driver 11 is not limited to that shown in FIGS. 4 and 5, but can be modified as appropriate.

[0036] The display device 1 according to the embodiment of the present technology is characterized mainly in the portion related to the above-described horizontal driver 10. Before describing the embodiment of the present technology, the conventional problem will be described in detail.

[0037] <2. Previous Problems> [2-1. Vertical Banding Phenomenon Due to Divided Driving] FIG. 6 is a diagram illustrating an example of the operation of a display device 1A in a comparative example. The display device 1A has a configuration similar to that of the display device 1 described above. Note that FIG. 6 shows a schematic configuration of a horizontal driver 10 and a pixel unit 9, and other configurations are omitted from the illustration. Also, "HARAMP" in FIG. 6 means a horizontal analog unit 13 that applies the RAMPDAC method. Also, in FIG. 6, pixels PIX in the middle of the column direction are omitted from the illustration. These are the same for subsequent similar figures.

[0038] The display device 1A of the comparative example employs a distributed driving method in which the pixel region is divided into six regions along the column direction and six rows, and each divided region is driven individually. Specifically, the horizontal analog unit 13 of the display device 1A of the comparative example has a ramp processing unit 29 for each region that generates and outputs a ramp signal whose voltage level changes over time, and each divided region is driven using the respective ramp processing unit 29 (referred to as the HARAMP distributed driving method). With this HARAMP distributed driving method, a vertical band phenomenon (vertical stripe) can occur, which is an image quality issue.

[0039] FIG. 7 is an illustration for explaining the vertical band phenomenon. In a comparative example display device 1A employing the HARAMP distributed driving method, a risk of vertical band-like image quality abnormalities as shown in the figure is anticipated. That is, in the comparative example display device 1A, as described above, a ramp processing unit 29 is provided for each region. Therefore, if the specifications of each ramp processing unit 29 are not consistent, differences in the write voltages of each will occur, and these voltage differences can result in differences in image quality. This can result in the vertical bands shown in FIG. 7. For this reason, the comparative example display device 1A requires high specifications for the accuracy of writing the gradation voltage of the pixel signal SIG to the signal line SGL, making the design difficult. This problem is not limited to horizontal drivers 10 employing the RAMPDAC method, but can also occur in horizontal drivers 10 of other configurations, such as voltage follower configurations, as long as they are configured to perform processing on a region-by-region basis.

[0040] [2-2. Offset Cancellation at Low Frame Rates] There are two offset techniques for reducing variations in image appearance: a temporal offset method (temporal offset method) and a spatial offset method (spatial offset method). This temporal / spatial offset cancellation method is effective under high frame rate conditions, but is ineffective at low frame rates because it can cause screen flicker and screen roughness (so-called surface roughness) caused by the write voltage of the horizontal drivers 10A and 10B.

[0041] FIG. 8 is an illustration for explaining the time offset method. The reaction speed of the human eye is said to be up to about 60 Hz. Therefore, as shown in the upper part of the figure, when operating at a high frame rate (e.g., 120 Hz) that exceeds the reaction speed of the human eye, even if there are differences in brightness between each screen, as shown in the figure, the actual appearance is averaged, and the differences in brightness between each image are not visible. In this way, at a frame rate that exceeds the reaction speed of the human eye, unintended characteristic displays (display characteristics), such as brightness between each screen, can be dispersed over time to reduce variations in appearance.

[0042] In contrast, as shown in the lower part of the figure, when operating at a low frame rate (e.g., 30 Hz) below the reaction speed of the eye, if there are differences in brightness between each screen, the differences in brightness between each screen will be visible, and image quality problems such as flicker may occur.

[0043] On the other hand, even in the spatial offset cancellation method in which two horizontal drivers 10 are provided and the one that performs the writing operation to each signal line SGL is alternately switched to spatially disperse the unintended feature display described above, at low frame rates the feature display is similarly visible, which can cause image quality problems such as flicker. Therefore, at low frame rates, the temporal / spatial offset cancellation operation is not effective.

[0044] Therefore, in the embodiment described below, these problems are solved by the configuration and operation associated with the horizontal driver 10.

[0045] 3. An embodiment 3-1. Specific configuration example of a display device FIG. 9 is a diagram showing a specific configuration example of a display device 1 according to an embodiment of the present technology. The display device 1 of this embodiment includes two horizontal drivers 10, i.e., two horizontal logic units 12 and two horizontal analog units 13, as driving units that generate pixel signals SIG to be output to each signal line SGL as described above. Specifically, one horizontal driver 10A is disposed at one end (upper side of the figure) of the pixel unit 9 in the column direction and drives one pixel PIX (shown in light shade) among the odd-numbered pixels and the even-numbered pixels. The other horizontal driver 10B is disposed at the other end (lower side of the figure) of the pixel unit 9 in the column direction and drives the other pixel PIX (shown in dark shade) among the odd-numbered pixels and the even-numbered pixels. The odd-numbered pixels and the even-numbered pixels are arranged in the order of the pixels PIX in a pixel row, i.e., from one end (e.g., the left side of the figure) of the pixels PIX arranged in the row direction. In the illustrated example, the horizontal driver 10A drives odd-numbered pixels, and the horizontal driver 10B drives even-numbered pixels.

[0046] The horizontal driver 10A is composed of a horizontal logic unit 12A and a horizontal analog unit 13A, and the horizontal driver 10B is composed of a horizontal logic unit 12B and a horizontal analog unit 13B. The horizontal analog units 13A and 13B each have a ramp processing unit 29A and 29B that generates and outputs a ramp signal whose voltage level changes over time.

[0047] One end of each signal line SGL is connected to the lamp wiring RL of the lamp processing unit 29A via the switch unit 16A, and the other end of each signal line SGL is connected to the lamp wiring RL of the lamp processing unit 29B via the switch unit 16B. The switch unit 16A switches the connection state between the horizontal driver 10A and each signal line SGL, and the switch unit 16B switches the connection state between the horizontal driver 10B and each signal line SGL. The switch units 16A and 16B may be provided between the switch unit 30 ( FIG. 2 ) and the lamp processing units 29A and 29B, respectively, or may be provided between the switch unit 30 and the pixel unit 9. In other words, the connection order between the switch unit 30 and each of the switch units 16A and 16B does not matter which is closer to the pixel unit 9.

[0048] Each of the switch sections 16A and 16B is configured with a switch SW such as a transistor provided for each signal line SGL. The switch SW is a selection switch that selects whether the horizontal driver 10A or the horizontal driver 10B is to drive the pixel PIX.

[0049] The timing controller 8 receives image data (DATA) from an interface unit (IF) 5 and receives a clock signal (CLK) from an oscillator (e.g., OSC) 6. The timing controller 8 outputs image data (ODD / EVEN_DATA) of one of the odd-numbered pixels and the even-numbered pixels to the horizontal logic unit 12A. The timing controller 8 also outputs image data (XODD / EVEN_DATA) of the other of the odd-numbered pixels and the even-numbered pixels to the horizontal logic unit 12B.

[0050] The timing controller 8 controls the switch units 16A and 16B so that the horizontal driver 10A and the horizontal driver 10B are assigned to each group of predetermined adjacent pixels. For example, the group of predetermined adjacent pixels is pixels PIX arranged in the row direction, as shown in Figure 9. Specific examples of this "group of predetermined pixels" will be described later in the operation example.

[0051] Specifically, the timing controller 8 outputs a switch control signal (ODD / EVEN_EN) to the switch unit 16A in accordance with the timing of outputting image data for one of the odd and even pixels, which turns on the switch SW at one end of the signal line SGL connected to the one pixel PIX (conductive state) and turns off the switch element SW at one end of the signal line SGL connected to the other pixel PIX (non-conductive state).The timing controller 8 also outputs a switch control signal (XODD / EVEN_EN) to the switch unit 16B in accordance with the timing of outputting image data for the other of the odd and even pixels, which turns on the switch SW at the other end of the signal line SGL connected to the other pixel PIX and turns off the switch element SW provided at the other end of the signal line SGL connected to the one pixel PIX.

[0052] FIG. 10 shows an example of a timing chart relating to the control of the horizontal drivers 10A and 10B. FIG. 10 illustrates the operation of the timing controller 8, horizontal logic unit 12A (upper side of the HLOGIC), and horizontal logic unit 12B (lower side of the HLOGIC). In the diagram, XHD indicates a horizontal synchronization signal, and ODEV_EN indicates an odd / even selection signal (a signal indicating switching timing). Also, HL_ODEV_EN (upper side) indicates the odd / even selection signal of the horizontal logic unit 12A, and XHL_ODEV_EN (lower side) indicates the odd / even selection signal of the horizontal logic unit 12B. In other words, FIG. 10 illustrates an example in which the horizontal driver 10 that uses pixels for each line is switched between the horizontal driver 10A and the horizontal driver 10B. Note that blk indicates a blanking period.

[0053] For example, when ODEV_EN is at a low level (0: even number selection), HL_ODEV_EN (upper side) becomes a high level (1: odd number selection), the internal use data of the horizontal logic unit 12A becomes image data of odd number pixels (ODD_DATA), and the data of the 2nd latch unit 23 becomes image data of even number pixels (EVEN_DATA). In this case, XHL_ODEV_EN (lower side) becomes a low level (0: even number selection), the internal use data of the horizontal logic unit 12B becomes image data of even number pixels (EVEN_DATA), and the data of the 2nd latch unit 23 becomes image data of odd number pixels (ODD_DATA). In this way, in the display device 1, the timing controller 8 controls the horizontal drivers 10A and 10B so that the horizontal logic units 12A and 12B use the positive and negative phases of ODEV_EN appropriately.

[0054] The control source of the switch SW is not limited to the timing controller 8. Fig. 11 shows configuration examples in which the control source of the switch SW is different. Fig. 11A shows a configuration example in which the horizontal logic unit 12 controls the switch SW, and Fig. 11B shows a configuration example in which an external device controls the switch SW. In the example shown in Fig. 11A, the timing controller 8 outputs the above-mentioned switch control signals ODD / EVEN_EN and XODD / EVEN_EN to the horizontal logic units 12A and 12B, respectively. The horizontal logic units 12A and 12B control the switches SW of the switch units 16A and 16B as described above based on the switch control signals ODD / EVEN_EN and XODD / EVEN_EN, respectively.

[0055] 11B , the above-mentioned switch control signals ODD / EVEN_EN and XODD / EVEN_EN are supplied from an external device to the switches SW of the switch units 16A and 16B via the input / output unit 2, and thereby the switches SW of the switch units 16A and 16B are controlled as described above. In this way, the control source of the switches SW may be other than the timing controller 8.

[0056] 3-2. Operational Examples of the Display Device (Operational Example 1) FIGS. 12 and 13 are diagrams showing an operational example (Operational Example 1) of the display device 1. FIG. 12 shows the operation for odd-numbered frames, and FIG. 13 shows the operation for even-numbered frames. In this operational example, one pixel aligned in the row direction, one line along the row direction, and one frame each constitute the "predetermined pixel group" described above. That is, the horizontal driver 10A and the horizontal driver 10B are used depending on whether the pixel, line, and frame are odd or even. Specifically, the states of the switches SW are controlled as shown in the figure to alternately operate the horizontal driver 10A and the horizontal driver 10B for the pixels PIX in the row direction, and the driver is switched between the horizontal driver 10A and the horizontal driver 10B for each line. Furthermore, the driver is switched between the horizontal driver 10A and the horizontal driver 10B for each frame.

[0057] The operation is as follows: On a certain line, odd-numbered pixels are driven by horizontal driver 10A, and even-numbered pixels are driven by horizontal driver 10B. On the next line, odd-numbered pixels are driven by horizontal driver 10B, and even-numbered pixels are driven by horizontal driver 10A. After this operation is performed in a certain frame, in the next frame, odd-numbered pixels are driven by horizontal driver 10B, and even-numbered pixels are driven by horizontal driver 10A. Then, on the next line, odd-numbered pixels are driven by horizontal driver 10A, and even-numbered pixels are driven by horizontal driver 10B. The offset cancel operation (described later) of horizontal drivers 10A and 10B is also used in combination.

[0058] Specifically, as shown in FIG. 12 , for odd-numbered lines in odd-numbered frames, control is performed so that the top (horizontal driver 10A), bottom (horizontal driver 10B), top, bottom, ... are alternately used in order from the left end to the right end in the row direction. More specifically, for odd-numbered pixels PIX from the left side in the row direction, the switch SW on the horizontal driver 10A side is controlled to be on, and the switch SW on the horizontal driver 10B side is controlled to be off. For even-numbered pixels PIX from the left side in the row direction, the switch SW on the horizontal driver 10B side is controlled to be on, and the switch SW on the horizontal driver 10A side is controlled to be off. Similarly, for even-numbered lines in odd-numbered frames, control is performed so that the order of odd-numbered lines is reversed and they are alternately used in order from the left end to the right end in the row direction: bottom, top, bottom, top, ...

[0059] 13, odd-numbered lines in even-numbered frames are controlled to be used alternately in the order of bottom, top, bottom, top, etc. from the left end to the right end in the row direction, with the odd-numbered lines being used alternately in the order of top, bottom, top, bottom, etc. from the left end to the right end in the row direction, with the odd-numbered lines being used alternately in the order of top, bottom, top, bottom, etc.

[0060] As a result, in pixel units, the horizontal drivers 10 that drive adjacent pixels PIX in the row direction are different between the horizontal drivers 10A and 10B, allowing for distributed driving in the row direction. Furthermore, by switching the horizontal drivers 10 that drive each pixel PIX between the horizontal drivers 10A and 10B in row units, it is possible to distribute driving in the column direction. Furthermore, by switching the horizontal drivers 10 that drive each pixel PIX between the horizontal drivers 10A and 10B in frame units, it is possible to distribute driving in frame units. This distribution of driving allows for even distribution of the differences in write voltages for each distribution region, even when the above-mentioned distributed driving method is adopted, thereby suppressing the occurrence of the above-mentioned vertical banding phenomenon and improving image quality. Furthermore, by arranging horizontal driver 10A at one end of pixel section 9 in the column direction and horizontal driver 10B at the other end, it is possible to reduce and uniform the frame in the column direction of the display panel composed of pixel section 9 and peripheral circuits such as a DDIC (Display Driver Integrated Circuit).

[0061] 14 to 16 are diagrams showing an operation example (operation example 2) of the display device 1. In this operation example, one or more pixels arranged in the row direction constitute the above-mentioned "predetermined pixel group." In other words, horizontal driver 10A and horizontal driver 10B are used selectively depending on whether the number of pixels PIX arranged in the row direction is odd or even.

[0062] 14 shows an example in which the switching is performed pixel by pixel. In the operation example shown in FIG. 14, the state of each switch SW is controlled as shown in the figure, and the horizontal drivers 10A and 10B are alternately operated pixel by pixel in the row direction of pixels PIX. That is, in each line of each frame, the horizontal drivers are controlled so that the horizontal drivers are alternately used in units of one pixel, from the left end to the right end in the row direction, in the order of upper (horizontal driver 10A), lower (horizontal driver 10B), upper, lower, etc.

[0063] As a result, the horizontal driver 10 that drives the pixel PIX for each pixel in the row direction is different between the horizontal driver 10A and the horizontal driver 10B, and driving in the row direction can be distributed. This distribution of driving can improve image quality as in the above-mentioned Operation Example 1. Note that the use of different drivers is not limited to each pixel.

[0064] 15 shows an example in which the driver is changed every two pixels, while FIG. 16 shows an example in which the driver is changed every three pixels. In the operation example shown in FIG. 15 , the state of each switch SW is controlled as shown, causing the horizontal driver 10A and the horizontal driver 10B to alternately operate every two pixels in the row-direction pixels PIX. Also, in the operation example shown in FIG. 16 , the state of each switch SW is controlled as shown, causing the horizontal driver 10A and the horizontal driver 10B to alternately operate every three pixels in the row-direction pixels PIX. Therefore, the horizontal driver 10 that drives the pixel PIX is different between the horizontal driver 10A and the horizontal driver 10B for each set of pixels in the row direction, thereby distributing the driving in the row direction and improving image quality as in the first operation example described above. Thus, the odd / even number of pixels is not limited to the odd / even number of pixels arranged in a single pixel unit, but also includes the odd / even number of pixels arranged in a multi-pixel unit.

[0065] 17 is a diagram showing an operation example (operation example 3) of the display device 1. In this operation example, lines along the row direction are the above-mentioned "predetermined pixel collections." In other words, horizontal driver 10A and horizontal driver 10B are used depending on whether the lines along the row direction are odd or even.

[0066] Fig. 17 shows an example in which the driving voltage is changed for each line. In the operation example shown in Fig. 17, the state of each switch SW is controlled as shown in the figure, and the horizontal driver 10A and the horizontal driver 10B are operated alternately for each line. In other words, the pixels PIX on odd-numbered lines of each frame are controlled to be driven by the horizontal driver 10B, and the pixels PIX on even-numbered lines are controlled to be driven by the horizontal driver 10A.

[0067] As a result, the horizontal driver 10 that drives the pixels PIX for each line in the column direction is different between the horizontal driver 10A and the horizontal driver 10B, and driving in the column direction can be distributed. This distribution of driving can improve image quality as in the above-mentioned Operation Example 1. Note that the use of different drivers is not limited to every line, and different drivers may be used for every multiple lines. In other words, odd / even lines are not limited to odd / even lines arranged in units of one line, but also include odd / even lines arranged in units of multiple lines.

[0068] 18 is a diagram showing an operation example (operation example 4) of the display device 1. In this operation example, a frame is the above-mentioned "collection of predetermined pixels." In other words, the horizontal driver 10A and the horizontal driver 10B are used depending on whether the frame is odd or even.

[0069] Fig. 18 shows an example in which the horizontal driver 10A is changed every frame. In the operation example shown in Fig. 18, the state of each switch SW is controlled as shown in the figure, and the horizontal driver 10A and the horizontal driver 10B are operated alternately every frame. In other words, the pixel PIX in odd-numbered frames is driven by the horizontal driver 10A, and the pixel PIX in even-numbered frames is driven by the horizontal driver 10B.

[0070] As a result, the horizontal driver 10 that drives the pixel PIX for each frame is different between the horizontal driver 10A and the horizontal driver 10B, and the driving for each frame can be distributed. This distribution of driving can improve image quality, as in the above-mentioned Operation Example 1. Note that the driving drivers may be used not only for each frame but also for multiple frames. In other words, odd / even frame numbers are not limited to odd / even numbers in a single frame sequence, but also include odd / even numbers in a multiple-frame sequence.

[0071] 19 to 24 are diagrams showing an operation example (operation example 5) of the display device 1. In the above-described operation example 1, the driving driver is changed for each pixel PIX in the row direction, but this pixel PIX may include, for example, sub-pixels of the three primary colors of red, green, and blue (pixels PIX(R), (G), (B)), and the driving driver may be changed depending on the group of sub-pixels.

[0072] 19 and 20 show an example of operation in which subpixels of all colors are grouped together and a driver is changed for each group. FIG. 19 shows the operation for odd-numbered frames, and FIG. 20 shows the operation for even-numbered frames. In this example of operation, a group of all subpixels included in a pixel PIX arranged in the row direction, a line along the row direction, and a frame are each the "predetermined pixel group" described above. That is, the horizontal driver 10A and the horizontal driver 10B are used depending on whether the group of subpixels of all colors, the line, and the frame are odd or even. Specifically, as shown in FIGS. 19 and 20 , the states of the switches SW are controlled as shown, so that the horizontal driver 10A and the horizontal driver 10B operate alternately for each group in the row direction, and the driver is switched between the horizontal driver 10A and the horizontal driver 10B for each line. Furthermore, the driver is switched between the horizontal driver 10A and the horizontal driver 10B for each frame.

[0073] As a result, for each group consisting of subpixels of all colors, the horizontal driver 10 that drives adjacent groups in the row direction is different between the horizontal driver 10A and the horizontal driver 10B, thereby distributing driving in the row direction. Furthermore, by switching the horizontal driver 10 that drives each group between the horizontal driver 10A and the horizontal driver 10B for each row, driving in the column direction can be distributed. Furthermore, by switching the horizontal driver 10 that drives each group between the horizontal driver 10A and the horizontal driver 10B for each frame, driving can be distributed for each frame. This improves image quality, similar to the above-described first operation example. Furthermore, it is possible to simplify the control of the horizontal drivers 10A and 10B and improve the degree of freedom in allocation.

[0074] 21 and 22 show an example of operation in which the driver is changed only for subpixels of a highly visible color. FIG. 21 shows the operation for odd-numbered frames, and FIG. 22 shows the operation for even-numbered frames. In this example, a group of some subpixels (specifically, those of a highly visible color) included in a pixel PIX arranged in the row direction, a line along the row direction, and a frame along the row direction each constitute the "predetermined pixel group" described above. That is, the horizontal driver 10A and the horizontal driver 10B are used depending on whether the subpixels of a highly visible color (specifically, pixel PIX(G)), the line, and the frame are odd or even. Specifically, as shown in FIGS. 21 and 22 , the states of the switches SW are controlled as shown, so that the horizontal driver 10A and the horizontal driver 10B are alternately operated for the highly visible pixels (G) in the row direction. The driver is alternately switched between the horizontal driver 10A and the horizontal driver 10B for each line, and the driver is alternately switched between the horizontal driver 10A and the horizontal driver 10B for each frame. The driving of the red pixel PIX(R) is fixed to the horizontal driver 10A, and the driving of the blue pixel PIX(B) is fixed to the horizontal driver 10B.

[0075] As a result, the horizontal drivers 10 that drive adjacent highly visible pixels PIX(G) in the row direction are different between the horizontal drivers 10A and 10B, thereby distributing driving in the row direction. Furthermore, by switching the horizontal driver 10 that drives each pixel PIX(G) between the horizontal drivers 10A and 10B on a row-by-row basis, driving in the column direction can be distributed. Furthermore, by switching the horizontal driver 10 that drives each pixel (G) between the horizontal drivers 10A and 10B on a frame-by-frame basis, driving can be distributed on a frame-by-frame basis. This improves image quality, similar to the above-described first operation example. By fixing the drivers that drive the pixels PIX(R) and PIX(B) of colors with low visibility, it is also possible to omit the switch SW and save space.

[0076] 23 and 24 show an example of operation in which the driver for only subpixels of highly visible colors is changed. FIG. 23 shows the operation for odd-numbered frames, and FIG. 24 shows the operation for even-numbered frames. In this example of operation, a group of some subpixels (specifically, subpixels of highly visible colors) arranged in the row direction and included in a pixel PIX, one line along the row direction, and one frame each constitute the above-mentioned "predetermined pixel group." In other words, horizontal driver 10A and horizontal driver 10B are used depending on whether the subpixels of highly visible colors (specifically, green pixel PIX(G) and white pixel PIX(W)), line, and frame are odd or even. 23 and 24 , the state of each switch SW is controlled as shown, and horizontal drivers 10A and 10B are alternately operated for pixels PIX(G) and PIX(W), which have high visibility in the row direction. The horizontal drivers are switched between horizontal drivers 10A and 10B for each line, and further, the horizontal drivers are switched between horizontal drivers 10A and 10B for each frame. The horizontal drivers 10A and 10B are also used for pixels PIX(G) and PIX(W) that constitute the same pixel. The red pixel PIX(R) is driven by horizontal driver 10A, and the blue pixel PIX(B) is driven by horizontal driver 10B.

[0077] As a result, the horizontal drivers 10 that drive adjacent highly visible pixels (pixels PIX(G) and PIX(W)) in the row direction are different between the horizontal drivers 10A and 10B, making it possible to distribute driving in the row direction. Furthermore, by switching the horizontal drivers 10 that drive the pixels PIX(G) and PIX(W) between the horizontal drivers 10A and 10B on a row-by-row basis, it is possible to distribute driving in the column direction. This improves image quality in the same way as in the above-described first operational example. By fixing the drivers that drive the pixels PIX(R) and PIX(B) of colors with low visibility, it is also possible to omit the switch SW and save space.

[0078] In this way, the configuration (including the arrangement) of the sub-pixels is not limited to a specific one. In addition, the fixed destinations of the pixels PIX(R) and PIX(B) that are not highly visible, the number of groups of sub-pixels, and the like can be changed as appropriate.

[0079] [3-3. Offset Cancellation Function] The horizontal drivers 10A and 10B of the display device 1 of this embodiment have an offset cancellation function. Fig. 25 is a diagram showing a specific configuration example of the ramp processing unit 29. The ramp processing unit 29 has a QV conversion circuit 61, a variable current circuit 62, and an integrator 63.

[0080] The input node of the Q-V conversion circuit 61 is connected to the output node of the variable current circuit 62. The output node of the Q-V conversion circuit 61 is connected to the input node (VIN) of the integrator 63 and the output node (VOUT) of the ramp processing unit 29, that is, the ramp wiring RL (see FIG. 2). The output node (VOUT) of the integrator 63 is connected to the input node of the variable current circuit 62.

[0081] The Q-V conversion circuit 61 generates and outputs a ramp voltage as a ramp (RAMP) signal. The Q-V conversion circuit 61 includes an amplifier 64, a capacitor C1, a resistor R1, and a switch 65. The switch 65 is a switching element such as a metal oxide semiconductor field effect transistor (MOSFET) that switches between an on state and an off state in response to the PCHG signal. The switches included in the ramp processing unit 29, including the switch 65, are controlled to switch between an on state and an off state by a signal supplied from the timing controller 8, for example.

[0082] The inverting input node (-) of amplifier 64 is connected to the input node of Q-V conversion circuit 61, one end of capacitor C1, and one end of switch 65, and the non-inverting input node (+) is connected to the supply line of gradation voltage VG0. Gradation voltage VG0 is the maximum voltage when the light emission brightness of pixel PIX is expressed in 256 gradations. The other end of capacitor C1 is connected to one end of resistor R1. The output terminal of amplifier 64 is connected to the other end of resistor R1, the other end of switch 65, and the output node of Q-V conversion circuit 61.

[0083] The variable current circuit 62 outputs a variable current. The variable current circuit 62 has a variable current source 66 and a switch 67. The switch 67 is a switching element such as a MOSFET that switches between an on state and an off state in response to a PWM signal. The variable current source 66 has a setting node, and uses input power supplied from a power line to generate and output a current in accordance with the input voltage of the setting node. The setting node of the variable current source 66 is connected to the input node of the variable current circuit 62, and the output node is connected to one end of the switch 67. The other end of the switch 67 is connected to the output node of the variable current circuit 62.

[0084] The integrator 63 outputs a voltage (VOUT) obtained by integrating the input voltage (VIN) over time. The integrator 63 includes an amplifier 68, a load current source 69, a capacitor C2, a resistor R2, and switches 70 to 75. The amplifier 68 is a differential amplifier (op-amp), and the switches 70 to 75 are switching elements such as MOSFETs. The switch 70 is switched between an on state and an off state by the SMPL signal, and the switch 71 is switched between an on state and an off state by the XEN signal. The switches 72 and 73 are switched between an on state and an off state by the CS signal, and the switches 74 and 75 are switched between an on state and an off state by the XCS signal. The XCS signal is an inverted signal of the CS signal. The load power source 69 and the switches 72 to 75 function as an offset compression circuit that compresses the offset of the amplifier 68.

[0085] One end of switch 70 is connected to the other end of resistor R2, and the other end is connected to the input node (VIN) of integrator 63. One end of resistor R2 is connected to the other end of switch 74, the other end of capacitor C2, and the other end of switch 71. An inverting input node (-) of amplifier 68 is connected to one end of switch 72 and one end of switch 74, and a non-inverting input node (+) is connected to the other end of switch 72 and the supply line of gradation voltage VG255. Gradation voltage VG255 is the minimum voltage when the emission brightness of pixel PIX is expressed in 256 gradations. An output node of amplifier 68 is connected to the output of load current source 69, one end of switch 73, and the other end of switch 75.

[0086] Load current source 69 has a setting node, and generates and outputs a current corresponding to the input voltage of the setting node using input power supplied from the power line. The setting node of load current source 69 is connected to the other end of switch 73, and the output node is connected to the output node of amplifier 68, one end of switch 73, and the other end of switch 75. One end of switch 75 is connected to the output node (VOUT) of integrator 63, one end of capacitor C2, and one end of switch 71.

[0087] In this embodiment, an offset cancel function is provided in the output buffer of the ramp processing unit 29. Specifically, the amplifier 64 is configured as follows.

[0088] 26 shows a detailed configuration example of the amplifier 64. The amplifier 64 has an operational amplifier (differential amplifier) ​​641, a capacitor C3, and switches 642 to 644. The capacitor C3 and the switches 642 to 644 function as an offset compression circuit that compresses the offset of the operational amplifier 641. In other words, the amplifier 64 has a switched-capacitor offset cancellation function that combines capacitance and switches. The switches 642 to 644 are switching elements such as MOSFETs. The switches 642 and 643 are switched between an on state and an off state by the OFS_SMPL signal, and the switch 644 is switched between an on state and an off state by the OFS_HOLD signal.

[0089] The output node of operational amplifier 641 is connected to the output node of amplifier 64. The inverting input node (−) of operational amplifier 641 is connected to the other end of switch 642 and the inverting input node (−) of amplifier 64, and the non-inverting input node (+) is connected to the other end of switch 643 and one end of capacitor C3. The other end of capacitor C3 is connected to the other end of switch 644 and one end of switch 642. One end of switch 643 is connected to one end of switch 644 and the non-inverting input node (+) of amplifier 64.

[0090] 27 is a timing chart showing an example of the operation of the ramp processing unit 29. FIG. 27 shows the operation when generating a ramp voltage. Specifically, FIG. 27 shows changes in the levels of the PCHG signal, the CS signal, the OFS_SMPL signal, the OFS_HOLD signal, the PWM signal, and the SMPL signal, and the signal voltage of the ramp signal (RAMP) output from the ramp processing unit 29. In this example, when a signal level is high, the switch corresponding to that signal is turned on (conductive), and when the signal level is low, the switch corresponding to that signal is turned off (non-conductive).

[0091] At time t0, PCHG, CS, OFS_SMPL, PWM, and SMPL are at low levels, and OFS_HOLD is at high level. This holds the output voltage of the lamp processing unit 29. At the next time t1, PCHG and CS are at high levels. This causes the output voltage of the lamp processing unit 29 to rise toward the gradation voltage VG0. At the next time t2, CS is at low level. Then, the output voltage of the lamp processing unit 29 becomes the gradation voltage VG0, and OFS_HOLD is at low level.

[0092] At the next time t3, OFS_SMPL goes high, and at time t4, OFS_SMPL goes low. Thereafter, OFS_HOLD goes high. Then, at time t5, PCHG goes low and PWM goes high. As a result, the output voltage of the lamp processing unit 29 gradually decreases from the gradation voltage VG0 toward the gradation voltage VG255.

[0093] Then, at time t6, the output voltage of the lamp processing unit 29 becomes the gradation voltage VG255, and PWM becomes low level. Next, SMPL becomes high level, and then SMPL becomes low level again, at time t7. In this series of steps, offset cancellation of the Q-V conversion circuit 61 and the integrator 63 (cancellation operation of the amplifier offset voltage) is performed.

[0094] Figure 28 is a diagram illustrating the offset cancellation operation of the integrator 63. Figure 28A shows the basic state of the integrator 63 during period a (time t1 to t2) in Figure 27. Figure 28B shows the basic state of the integrator 63 during period b (time t2 to t7) in Figure 27.

[0095] 28A, during period a, switches 72 and 73 are on, and switches 74 and 75 are off. As a result, the inverting input node (−) and the non-inverting input node (+) of amplifier 68 are connected to the same potential, and the difference current generated by the offset error is held in load current source 69.

[0096] 28B, during period b, switches 72 and 73 are turned off, and switches 74 and 75 are turned on. In this way, when normal amplifier operation (operation for generating a ramp voltage) is performed, the offset voltage is compensated for. As a result, a ramp voltage can be generated by the integrator 63 with the offset canceled.

[0097] Figure 29 is a diagram illustrating the offset cancellation operation of the Q-V conversion circuit 61. Figure 29A shows the states of the Q-V conversion circuit 61 and the variable current circuit 62 during period c (times t3 to t4) in Figure 27. Figure 29B shows the states of the Q-V conversion circuit 61 and the variable current circuit 62 during period d (times t4 to t5) in Figure 27. Figure 29C shows the states of the Q-V conversion circuit 61 and the variable current circuit 62 during period e (times t5 to t6) in Figure 27.

[0098] 29A, during period c, switches 65, 642, and 643 are turned on, and switches 67 and 644 are turned off. Therefore, amplifier 64 operates as a voltage follower with the feedback load shorted. As a result, an offset voltage is held in the capacitance (capacitor C3) on the input side of operational amplifier 641.

[0099] As shown in FIG. 29B, during period d, switches 65 and 644 are turned on, and switches 67, 642, and 643 are turned off. As a result, the circuit connection is changed so that the held voltage is subtracted from the input voltage as described above, and the input voltage is applied. As shown in FIG. 29C, during period e, switches 67 and 644 are turned on, and switches 65, 642, and 643 are turned off. As a result, a constant current is applied to the feedback capacitance (capacitor C1), and a ramp waveform is output. As a result, a ramp voltage can be output by the offset-canceled Q-V conversion circuit 61.

[0100] The configuration of the lamp processing unit 29, including the configuration for realizing the offset cancellation function, is not limited to the configurations shown in Figures 25 and 26. For example, the amplifier 64 may have a configuration of an offset digital switching system in which the offset voltage is corrected by a digital circuit.

[0101] FIG. 30 shows another example configuration of the amplifier 64. The amplifier 64 shown in FIG. 30 has an offset cancellation configuration using an offset digital switching method. The amplifier 64 includes an input stage 651 that amplifies and outputs the differential voltage between the non-inverting input node (+) and the inverting input node (−), and an output stage 652 that increases the gain of the output of the input stage 651 and buffers it to an output node. The input stage 651 is composed of multiple MOSFETs. Specifically, the input stage 651 includes transistors Tr1a, Tr1b, Tr2a, and Tr2b. The transistors Tr1a and Tr1b are P-type MOSFETs, and the transistors Tr2a and Tr2b are N-type MOSFETs. The gate of the transistor Tr1a is connected to the other of the source and drain of the transistor Tr1a, the gate of the transistor Tr1b, and the other of the source and drain of the transistor Tr2a. One of the sources or drains of transistors Tr1a and Tr1b is connected to a power supply line (positive power supply). The gate of transistor Tr2a is connected to the inverting input node (-), and the gate of transistor Tr2b is connected to the non-inverting input node (+). The other of the source or drain of transistor Tr1b is connected to the input node of output stage 652 and the other of the source or drain of transistor Tr2b. One of the sources or drains of transistors Tr2a and Tr2b is connected to a power supply line (negative power supply) via an adjustment circuit.

[0102] This adjustment circuit digitally adjusts the offset of the amplifier 64 and is provided as an offset compression circuit. The adjustment circuit is, for example, a variable resistor 653. In this amplifier 64, the offset voltage can be canceled by adjusting the resistance value of the variable resistor 653. Therefore, even in this configuration, a ramp voltage can be output by the Q-V conversion circuit 61 with the offset canceled.

[0103] [3-4. Summary of One Embodiment] As described above, the display device 1 of this embodiment includes a plurality of pixels PIX arranged in the row direction, a plurality of signal lines SGL connected to each of the plurality of pixels PIX, a horizontal driver 10 that generates pixel signals SIG to be output to the plurality of signal lines SGL, and switch units 16A and 16B that switch the connection state between the horizontal driver 10 and each of the plurality of signal lines SGL. The horizontal driver 10 includes a horizontal driver 10A and a horizontal driver 10B. The display device 1 controls the switch units 16A and 16B so that the horizontal driver 10A and the horizontal driver 10B are assigned to each group of predetermined adjacent pixels. In this way, by assigning the first horizontal driver 10A and the second horizontal driver 10B to each group of predetermined adjacent pixels, minute voltage variations (potential band-like deviations in write voltage) caused by the horizontal drivers 10A and 10B can be dispersed by operation. As a result, characteristic display features on the screen are optimally dispersed, eliminating vertical banding and other phenomena, and improving image quality. In particular, by providing an offset cancellation mechanism in the horizontal drivers 10A and 10B and combining the above-described image quality improvement operation with offset cancellation by the offset cancellation mechanism, it is possible to suppress flicker at low frame rates while temporally and spatially dispersing error components, making vertical bands and other phenomena less visible even with temporal / spatial offset cancellation at low frame rates. Therefore, temporal / spatial offset cancellation can be made effective even at low frame rates.

[0104] 4. Configuration Examples of Pixel Circuits Other configuration examples of the pixel PIX will be described below. Note that the following configuration examples are merely illustrative and do not exclude other configurations.

[0105] (Configuration Example 1) Figure 31 shows an example of the configuration of a pixel PIX included in the pixel unit 9. The pixel PIX has a capacitor C01, transistors MN02 and MN03, and a light-emitting element EL. The transistors MN02 and MN03 are N-type metal oxide semiconductor field effect transistors (MOSFETs). The gate of transistor MN02 is connected to a control line WSL, the other of the source and drain is connected to a signal line SGL, and one of the source and drain is connected to the gate of transistor MN03 and one end of capacitor C01. One end of capacitor C01 is connected to one of the source and drain of transistor MN02 and the gate of transistor MN03, and the other end is connected to one of the source and drain of transistor MN03 and the anode of the light-emitting element EL. The gate of transistor MN03 is connected to one of the source and drain of transistor MN02 and one end of capacitor C01, the other of the source and drain is connected to the power supply line VCCP, and one of the source and drain is connected to the other end of capacitor C01 and the anode of light-emitting element EL. The anode of light-emitting element EL is connected to one of the source and drain of transistor MN03 and the other end of capacitor C01, and the cathode is connected to power supply line Vcath. The voltage of power supply line VCCP is switched between a first voltage and a second voltage lower than the first voltage as appropriate.

[0106] With this configuration, in pixel PIX, when transistor MN02 is turned on, the voltage across capacitor C01 is set based on the pixel signal supplied from signal line SGL. During a period when the voltage of power supply line VCCP is at a first voltage, transistor MN03 passes a current corresponding to the voltage across capacitor C01 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor MN03. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. During a period when the voltage of power supply line VCCP is at a second voltage, light-emitting element EL is turned off.

[0107] (Configuration Example 2) Figure 32 shows one configuration example of a pixel PIX included in the pixel unit 9. This pixel PIX includes capacitors C11 and C12, transistors MP12 to MP15, and a light-emitting element EL. Transistors MP12 to MP15 are P-type MOSFETs. The gate of transistor MP12 is connected to a control line WSL, one of its source and drain is connected to a signal line SGL, and the other of its source and drain is connected to the gate of transistor MP14 and the other end of capacitor C12. One end of capacitor C11 is connected to a power supply line VCCP, and the other end is connected to one end of capacitor C12, the other of the source and drain of transistor MP13, and one of the source and drain of transistor MP14. One end of capacitor C12 is connected to the other end of capacitor C11, the other of the source and drain of transistor MP13, and one of the source and drain of transistor MP14, and the other end is connected to the other of the source and drain of transistor MP12 and the gate of transistor MP14. The gate of transistor MP13 is connected to the control line DSL, one of its source and drain is connected to the power supply line VCCP, and the other of its source and drain is connected to one of the source and drain of transistor MP14, the other end of capacitor C11, and one end of capacitor C12. The gate of transistor MP14 is connected to the other of the source and drain of transistor MP12 and the other end of capacitor C12, one of its source and drain is connected to the other of the source and drain of transistor MP13, the other end of capacitor C11, and one end of capacitor C12, and the other of its source and drain is connected to the anode of the light-emitting element EL and one of the source and drain of transistor MP15. The gate of transistor MP15 is connected to the control line AZSL, one of its source and drain is connected to the other of the source and drain of transistor MP14 and the anode of the light-emitting element EL, and the other of its source and drain is connected to the power supply line VSS.The anode of the light-emitting element EL is connected to the other of the source and drain of the transistor MP14 and one of the source and drain of the transistor MP15, and the cathode is connected to the power supply line Vcath.

[0108] With this configuration, in pixel PIX, when transistor MP12 is turned on, the voltage across capacitor C12 is set based on the pixel signal supplied from signal line SGL. Transistor MP13 is turned on and off based on the signal on control line DSL. While transistor MP13 is on, transistor MP14 passes a current corresponding to the voltage across capacitor C12 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor MP14. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistor MP15 is turned on and off based on the signal on control line AZSL. While transistor MP15 is on, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line VSS.

[0109] The transistors MP12 to MP15 may be transistors using low temperature polysilicon (LTPS), and at least one of the transistors MP12 and MP15 may be a transistor using an oxide semiconductor.

[0110] (Configuration Example 3) Figure 33 shows another configuration example of pixel PIX. This pixel PIX has a capacitor C21, transistors MN22 to MN25, and a light-emitting element EL. Transistors MN22 to MN25 are N-type MOSFETs. The gate of transistor MN22 is connected to a control line WSL, the other of its source and drain is connected to a signal line SGL, and one of its source and drain is connected to the gate of transistor MN24 and one end of capacitor C21. One end of capacitor C21 is connected to one of the source and drain of transistor MN22 and the gate of transistor MN24, and the other end is connected to one of the source and drain of transistor MN24, the other of the source and drain of transistor MN25, and the anode of light-emitting element EL. The gate of transistor MN23 is connected to a control line DSL, the other of its source and drain is connected to a power supply line VCCP, and one of its source and drain is connected to the other of the source and drain of transistor MN24. The gate of transistor MN24 is connected to one of the source and drain of transistor MN22 and one end of capacitor C21, the other of the source and drain is connected to one of the source and drain of transistor MN23, one of the source and drain is connected to the other end of capacitor C21, the other of the source and drain of transistor MN25, and the anode of light-emitting element EL. The gate of transistor MN25 is connected to control line AZSL, the other of the source and drain is connected to one of the source and drain of transistor MN24, the other end of capacitor C21, and the anode of light-emitting element EL, and one of the source and drain is connected to power supply line VSS. The anode of light-emitting element EL is connected to one of the source and drain of transistor MN24, the other end of capacitor C21, and the other of the source and drain of transistor MN25, and the cathode is connected to power supply line Vcath.

[0111] With this configuration, in pixel PIX, when transistor MN22 is turned on, the voltage across capacitor C21 is set based on the pixel signal supplied from signal line SGL. Transistor MN23 is turned on and off based on the signal on control line DSL. While transistor MN23 is on, transistor MN24 passes a current corresponding to the voltage across capacitor C21 through light-emitting element EL. The light-emitting element EL emits light based on the current supplied from transistor MN24. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistor MN25 is turned on and off based on the signal on control line AZSL. While transistor MN25 is on, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line VSS.

[0112] The transistors MN22 to MN25 may be transistors using low temperature polysilicon (LTPS), and at least one of the transistors MN22 and MN25 may be a transistor using an oxide semiconductor.

[0113] (Configuration Example 4) Figure 34 shows another configuration example of pixel PIX. This pixel PIX has a capacitor C31, transistors MP32 to MP36, and a light-emitting element EL. Transistors MP32 to MP36 are P-type MOSFETs. The gate of transistor MP32 is connected to a control line WSL, one of its source and drain is connected to a signal line SGL, and the other of its source and drain is connected to the gate of transistor MP33, the other of the source and drain of transistor MP34, and the other end of capacitor C31. One end of capacitor C31 is connected to a power supply line VCCP, and the other end is connected to the other of the source and drain of transistor MP32, the gate of transistor MP33, and the other of the source and drain of transistor MP34. The gate of transistor MP33 is connected to the other of the source and drain of transistor MP32, the other of the source and drain of transistor MP34, and the other end of capacitor C31, one of its source and drain is connected to the power supply line VCCP, and the other of its source and drain is connected to one of the source and drain of transistor MP35 and one of the source and drain of transistor MP34. The gate of transistor MP34 is connected to control line AZSL1, one of its source and drain is connected to the other of the source and drain of transistor MP33 and one of the source and drain of transistor MP35, and the other of its source and drain is connected to the other of the source and drain of transistor MP32, the gate of transistor MP33, and the other end of capacitor C31. The gate of transistor MP35 is connected to control line DSL, one of its source and drain is connected to the other of the source and drain of transistor MP33 and one of the source and drain of transistor MP34, and the other of its source and drain is connected to one of the source and drain of transistor MP36 and the anode of the light-emitting element EL.The gate of the transistor MP36 is connected to the control line AZSL2, one of the source and drain is connected to the other of the source and drain of the transistor MP35 and the anode of the light-emitting element EL, the other of the source and drain is connected to the power supply line VSS, the anode of the light-emitting element EL is connected to the other of the source and drain of the transistor MP35 and one of the source and drain of the transistor MP36, and the cathode is connected to the power supply line Vcath.

[0114] With this configuration, in pixel PIX, when transistor MP32 is turned on, the voltage across capacitor C31 is set based on the pixel signal supplied from signal line SGL. Transistor MP35 is turned on and off based on the signal on control line DSL. While transistor MP35 is on, transistor MP33 passes a current corresponding to the voltage across capacitor C31 through light-emitting element EL. The light-emitting element EL emits light based on the current supplied from transistor MP33. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistor MP34 is turned on and off based on the signal on control line AZSL1. While transistor MP34 is on, the drain and gate of transistor MP33 are connected to each other. Transistor MP36 is turned on and off based on the signal on control line AZSL2. While transistor MP36 is on, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line VSS.

[0115] The transistors MP32 to MP36 may be transistors using low temperature polysilicon (LTPS), and at least one of the transistors MP32, MP34, and MP36 may be a transistor using an oxide semiconductor.

[0116] 35 shows another example of the configuration of pixel PIX. One end of capacitor C48 is connected to signal line SGL1, and the other end is connected to power supply line VSS. One end of capacitor C49 is connected to signal line SGL1, and the other end is connected to signal line SGL2. Transistor MP49 is a P-type MOSFET, and its gate is connected to control line WSL2, one of its source and drain is connected to signal line SGL1, and the other of its source and drain is connected to signal line SGL2.

[0117] The pixel PIX includes a capacitor C41, transistors MP42 to MP46, and a light-emitting element EL. The transistors MP42 to MP46 are P-type MOSFETs. The gate of transistor MP42 is connected to a control line WSL1, one of its source and drain is connected to a signal line SGL2, and the other of its source and drain is connected to the gate of transistor MP43 and the other end of capacitor C41. One end of capacitor C41 is connected to a power supply line VCCP, and the other end is connected to the other of the source and drain of transistor MP42 and the gate of transistor MP43. The gate of transistor MP43 is connected to the other of the source and drain of transistor MP42 and the other end of capacitor C41, one of its source and drain is connected to the power supply line VCCP, and the other of its source and drain is connected to one of the sources and drains of transistors MP44 and MP45. The gate of transistor MP44 is connected to control line AZSL1, one of its source and drain is connected to the other of the source and drain of transistor MP43 and one of the source and drain of transistor MP45, and the other of its source and drain is connected to signal line SGL2. The gate of transistor MP45 is connected to control line DSL, one of its source and drain is connected to the other of the source and drain of transistor MP43 and one of the source and drain of transistor MP44, and the other of its source and drain is connected to one of the source and drain of transistor MP46 and the anode of the light-emitting element EL. The gate of transistor MP46 is connected to control line AZSL2, one of its source and drain is connected to the other of the source and drain of transistor MP45 and the anode of the light-emitting element EL, and the other of its source and drain is connected to power supply line VSS. The anode of the light-emitting element EL is connected to the other of the source and drain of transistor MP45 and one of the source and drain of transistor MP46, and the cathode is connected to power supply line Vcath.The anode of the light-emitting element EL is connected to the other of the source and drain of the transistor MP124 and one of the source and drain of the transistor MP125, and the cathode is connected to the power supply line Vcath.

[0118] With this configuration, in pixel PIX, when transistor MP42 is turned on, the voltage across capacitor C41 is set based on the pixel signal supplied to signal line SGL1. Transistor MP45 is turned on and off based on the signal on control line DSL. While transistor MP45 is on, transistor MP43 passes a current corresponding to the voltage across capacitor C41 through light-emitting element EL. The light-emitting element EL emits light based on the current supplied from transistor MP43. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistor MP44 is turned on and off based on the signal on control line AZSL1. While transistor MP44 is on, the drain of transistor MP43 and signal line SGL2 are connected to each other. Transistor MP46 is turned on and off based on the signal on control line AZSL2. While transistor MP46 is on, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line VSS.

[0119] The transistors MP42 to MP46 and MP49 may be transistors using low temperature polysilicon (LTPS). At least one of the transistors MP42, MP46 and MP49 may be a transistor using an oxide semiconductor.

[0120] 36 shows another example of the configuration of the pixel PIX. A plurality of pixels PIX are arranged in a matrix in a display area 100, and the display area 100 is provided between a first control unit 91 and a second control unit 92.

[0121] The first control unit 91 includes transmission gates TG45 and TG46, transistors MP50 and MP51, and a capacitor C50. The transistors MP50 and MP51 are P-type MOSFETs. One end of the transmission gate TG45 receives a pixel signal, and the other end of the transmission gate TG45 is connected to a signal line 93a. One end of the transmission gate TG46 is connected to a signal line 93b, and the other end of the transmission gate TG46 is connected to a power supply line Vorst. One end of the capacitor C50 is connected to the signal line 93a, and the other end is connected to a power supply line VSS1. The gate of the transistor MP50 is connected to a control line INIL, one of its source and drain is connected to a power supply line Vini, and the other of its source and drain is connected to a signal line 93b. The gate of the transistor MP51 is connected to a control line ELL, one of its source and drain is connected to a power supply line Vel, and the other of its source and drain is connected to a signal line 93b.

[0122] The second control unit 92 has a transmission gate TG72, a transistor MP73, and a capacitor C82. The transistor MP73 is a P-type MOSFET. One end of the transmission gate TG72 is connected to a signal line 93a, and the other end is connected to the other of the source and drain of the transistor MP73 and one end of a capacitor C82. The gate of the transistor MP73 is connected to a control line REFL, one of the source and drain is connected to a power supply line Vref, and the other of the source and drain is connected to the other end of the transmission gate TG72 and one end of the capacitor C82. One end of the capacitor C82 is connected to the other end of the transmission gate TG72 and the other of the source and drain of the transistor MP73, and the other end is connected to a signal line 93b.

[0123] The pixel PIX includes a capacitor C132, transistors MP121 to MP125, and a light-emitting element EL. The transistors MP121 to MP125 are P-type MOSFETs. The gate of the transistor MP122 is connected to the control line WSL, one of the source and drain is connected to the signal line 93b, and the other of the source and drain is connected to the gate of the transistor MP121 and the other end of the capacitor C132. One end of the capacitor C132 is connected to the power supply line Vel, and the other end is connected to the other of the source and drain of the transistor MP122 and the gate of the transistor MP121. The gate of the transistor MP121 is connected to the other of the source and drain of the transistor MP122 and the other end of the capacitor C132, one of the source and drain is connected to the power supply line Vel, and the other of the source and drain is connected to one of the sources and drains of the transistors MP123 and MP124. The gate of transistor MP123 is connected to the control line AZSL, one of its source and drain is connected to the other of the source and drain of transistor MP121 and one of the source and drain of transistor MP124, and the other of its source and drain is connected to signal line 93b. The gate of transistor MP124 is connected to the control line DSL, one of its source and drain is connected to the other of the source and drain of transistor MP121 and one of the source and drain of transistor MP123, and the other of its source and drain is connected to one of the source and drain of transistor MP125 and the anode of the light-emitting element EL. The gate of transistor MP125 is connected to the control line AZSL, the other of its source and drain is connected to the power supply line Vorst, and one of its source and drain is connected to the other of the source and drain of transistor MP124 and the anode of the light-emitting element EL. The anode of the light-emitting element EL is connected to the other of the source and drain of transistor MP124 and one of the source and drain of transistor MP125, and the cathode is connected to the power supply line Vcath.

[0124] With this configuration, in pixel PIX, when transistor MP122 is turned on, the voltage across capacitor C132 is set based on the pixel signal supplied to one end of transmission gate TG45. Transistor MP124 is turned on and off based on the signal on control line DSL. While transistor MP124 is on, transistor MP121 passes a current corresponding to the voltage across capacitor C132 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor MP121. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistors MP123 and MP125 are turned on and off based on the signal on control line AZSL. While transistor MP123 is on, the other of the source and drain of transistor MP121 and one of the source and drain of transistor MP124 are connected to signal line 93b. While transistor MP125 is on, the voltage of the anode of light-emitting element EL is initialized by being set to the voltage of power supply line Vorst. Furthermore, transistor MP56 is turned on and off based on the signal on control line INIL, transistor MP57 is turned on and off based on the signal on control line ELL, and transistor MP73 is turned on and off based on the signal on control line REFL. When transistor MP56 is turned on, signal line 93b is set to the voltage of power supply line Vini, and when transistor MP57 is turned on, signal line 93b is set to the voltage of power supply line Vel. When transistor MP73 is turned on, one end of capacitor C82 is set to the voltage of power supply line Vref, thereby being initialized.

[0125] The transistors MP121 to MP125, MP56, and MP57 may be transistors using low temperature polysilicon (LTPS), and at least one of the transistors MP122 and MP125 may be a transistor using an oxide semiconductor.

[0126] (Configuration Example 7) Figure 37 shows another configuration example of pixel PIX. This pixel PIX has a capacitor C51, transistors MP52 to MP60, and a light-emitting element EL. Transistors MP52 to MP60 are P-type MOSFETs. The gate of transistor MP52 is connected to a control line WSL, one of its source and drain is connected to a signal line SGL, and the other of its source and drain is connected to the other of the source and drain of transistor MP53 and one of the source and drain of transistor MP54. The gate of transistor MP53 is connected to a control line DSL, one of its source and drain is connected to a power supply line VCCP, and the other of its source and drain is connected to the other of the source and drain of transistor MP52 and one of the source and drain of transistor MP54. The gate of transistor MP54 is connected to one of the source and drain of transistor MP55, the other of the source and drain of transistor MP57, and the other end of capacitor C51, with one of its source and drain connected to the other of the sources and drains of transistors MP52 and MP53, and the other connected to one of the sources and drains of transistors MP58 and MP59. Capacitor C51 has one end connected to the power supply line VCCP, and the other end connected to the gate of transistor MP54, one of the source and drain of transistor MP55, and the other of the source and drain of transistor MP57. Capacitor C51 may include two capacitors connected in parallel. The gate of transistor MP55 is connected to control line AZSL1, with one of its source and drain connected to the gate of transistor MP54, the other of the source and drain of transistor MP57, and the other end of capacitor C51, and the other connected to one of the source and drain of transistor MP56. The gate of the transistor MP56 is connected to the control line AZSL1, one of the source and drain is connected to the other of the source and drain of the transistor MP55, and the other of the source and drain is connected to the power supply line VSS.The gate of transistor MP57 is connected to the control line WSL, the other of its source and drain is connected to the gate of transistor MP54, one of the source and drain of transistor MP55, and the other end of capacitor C51, and one of its source and drain is connected to the other of the source and drain of transistor MP58. The gate of transistor MP58 is connected to the control line WSL, the other of its source and drain is connected to one of the source and drain of transistor MP57, and one of its source and drain is connected to the other of the source and drain of transistor MP54 and one of the source and drain of transistor MP59. The gate of transistor MP59 is connected to the control line DSL, one of its source and drain is connected to the other of the source and drain of transistor MP54 and one of the source and drain of transistor MP58, and the other of its source and drain is connected to one of the source and drain of transistor MP60 and the anode of the light-emitting element EL. The gate of the transistor MP60 is connected to the control line AZSL2, one of the source and drain is connected to the other of the source and drain of the transistor MP59 and the anode of the light-emitting element EL, the other of the source and drain is connected to the power supply line VSS, the anode of the light-emitting element EL is connected to the other of the source and drain of the transistor MP59 and one of the source and drain of the transistor MP60, and the cathode is connected to the power supply line Vcath.

[0127] With this configuration, in pixel PIX, transistors MP52, MP54, MP58, and MP57 are turned on, and the voltage across capacitor C51 is set based on the pixel signal supplied from signal line SGL. Transistors MP53 and MP59 are turned on and off based on the signal on control line DSL. While transistors MP53 and MP59 are on, transistor MP54 passes a current corresponding to the voltage across capacitor C51 through light-emitting element EL. The light-emitting element EL emits light based on the current supplied from transistor MP54. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistors MP55 and MP56 are turned on and off based on the signal on control line AZSL1. While transistors MP55 and MP56 are on, the gate voltage of transistor MP54 is initialized by being set to the voltage of power supply line VSS. Transistor MP60 is turned on and off based on the signal on control line AZSL2. During the period in which the transistor MP60 is in the on state, the voltage of the anode of the light-emitting element EL is initialized by being set to the voltage of the power supply line VSS.

[0128] The transistors MP52 to MP60 may be transistors using low temperature polysilicon (LTPS), and at least one of the transistors MP55 to MP58 and MP60 may be a transistor using an oxide semiconductor.

[0129] 38 shows another example of the configuration of the pixel PIX. The signal on the control line WSNL and the signal on the control line WSPL are mutually inverted signals.

[0130] The pixel PIX includes capacitors C61 and C62, transistors MN63, MP64, and MN65 to MN67, and a light-emitting element EL. The transistors MN63, MN65 to MN67 are N-type MOSFETs, and the transistor MP64 is a P-type MOSFET. The gate of the transistor MN63 is connected to a control line WSNL, and the other of its source and drain is connected to a signal line SGL and one of the source and drain of the transistor MP64, and one of its source and drain is connected to the other of the source and drain of the transistor MP64, one end of the capacitors C61 and C62, and the gate of the transistor MN65. The gate of the transistor MP64 is connected to a control line WSPL, and one of its source and drain is connected to the signal line SGL and the other of the source and drain of the transistor MN63, and the other of the source and drain is connected to one of the source and drain of the transistor MN63, one end of the capacitors C61 and C62, and the gate of the transistor MN65. The capacitor C61 is configured using, for example, a metal oxide metal (MOM) capacitor, with one end connected to one of the source and drain of transistor MN63, the other of the source and drain of transistor MP64, one end of capacitor C62, and the gate of transistor MN65, and the other end connected to the power supply line VSS2. The capacitor C61 may be configured using, for example, a metal oxide metal (MOS) capacitor or a metal insulator metal (MIM) capacitor. The capacitor C62 is configured using, for example, a MOS capacitor, with one end connected to one of the source and drain of transistor MN63, the other of the source and drain of transistor MP64, one end of capacitor C61, and the gate of transistor MN65, and the other end connected to the power supply line VSS2. The capacitor C62 may be configured using, for example, a MOM capacitor or a MIM capacitor. The other end of capacitor C62 may be connected to the power supply line VSS3 (not shown).The gate of transistor MN65 is connected to one of the source and drain of transistor MN63, the other of the source and drain of transistor MP64, and one end of capacitors C61 and C62, the other of the source and drain is connected to the power supply line VCCP, and one of the source and drain is connected to the other of the sources and drains of transistors MN66 and MN67. The gate of transistor MN66 is connected to control line AZL, the other of the source and drain is connected to one of the source and drain of transistor MN65 and the other of the source and drain of transistor MN67, and one of the source and drain is connected to the power supply line VSS1. The gate of transistor MN67 is connected to control line DSL, the other of the source and drain is connected to one of the source and drain of transistor MN65 and the other of the source and drain of transistor MN66, and one of the source and drain is connected to the anode of light-emitting element EL. The anode of light-emitting element EL is connected to one of the source and drain of transistor MN67, and the cathode is connected to the power supply line Vcath. Alternatively, the transistor MN67 and the control line DSL may be omitted, and one of the source and drain of the transistor MN65 may be connected to the other of the source and drain of the transistor MN66 and the anode of the light-emitting element EL.

[0131] With this configuration, in pixel PIX, when at least one of transistors MN63 and MP64 is turned on, the voltage across capacitors C61 and C62 is set based on the pixel signal supplied from signal line SGL. Transistor MN67 is turned on and off based on the signal on control line DSL. While transistor MN67 is on, transistor MN65 passes a current corresponding to the voltage across capacitors C61 and C62 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor MP65. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistor MN66 may be turned on and off based on the signal on control line AZL. Transistor MN66 may also function as a resistor element having a resistance value corresponding to the signal on control line AZL. In this case, transistors MN65 and MN66 form a so-called source follower circuit.

[0132] The transistors MN63, MP64, MN65 to MN67 may be transistors using low temperature polysilicon (LTPS), and at least one of the transistors MN63, MP64, and MN66 may be a transistor using an oxide semiconductor.

[0133] (Configuration Example 9) Figure 39 shows another configuration example of pixel PIX. This pixel PIX has a capacitor C71, transistors MN72 to MN77, and a light-emitting element EL. Transistors MN72 to MN77 are N-type MOSFETs. The gate of transistor MN72 is connected to a control line WSL, the other of its source and drain is connected to a signal line SGL, and one of its source and drain is connected to one of the source and drain of transistor MN74 and the other of the source and drain of transistor MN75. One end of capacitor C71 is connected to the gate of transistor MN74 and one of the source and drain of transistor MN76, and the other end is connected to the other of the source and drain of transistor MN77, one of the source and drain of transistor MN75, and the anode of the light-emitting element EL. The gate of transistor MN73 is connected to control line DSL1, the other of its source and drain is connected to power supply line VCCP, and one of its source and drain is connected to the other of transistor MN74 and the other of transistor MN76. The gate of transistor MN74 is connected to one of the source and drain of transistor MN76 and one end of capacitor C71, the other of its source and drain is connected to one of the source and drain of transistor MN73 and the other of the source and drain of transistor MN76, and one of its source and drain is connected to one of the source and drain of transistor MN72 and the other of the source and drain of transistor MN75. The gate of transistor MN75 is connected to control line DSL2, the other of its source and drain is connected to one of the source and drain of transistor MN72 and one of the source and drain of transistor MN74, and one of its source and drain is connected to the other end of capacitor C71, the other of the source and drain of transistor MN77, and the anode of light-emitting element EL.The gate of transistor MN76 is connected to control line AZSL, the other of its source and drain is connected to one of the source and drain of transistor MN73 and the other of the source and drain of transistor MN74, and one of its source and drain is connected to the gate of transistor MN74 and one end of capacitor C71. The gate of transistor MN77 is connected to control line AZSL, the other of its source and drain is connected to the other end of capacitor C71, one of the source and drain of transistor MN75, and the anode of light-emitting element EL, and one of its source and drain is connected to power supply line VSS. The anode of light-emitting element EL is connected to one of the source and drain of transistor MN75, the other of the source and drain of transistor MN77, and the other end of capacitor C71, and the cathode is connected to power supply line Vcath.

[0134] With this configuration, in pixel PIX, transistors MN72, MN74, and MN76 are turned on, and the voltage across capacitor C71 is set based on the pixel signal supplied from signal line SGL. Transistor MN73 is turned on and off based on the signal on control line DSL1, and transistor MN75 is turned on and off based on the signal on control line DSL2. While transistors MN73 and MN75 are on, transistor MN74 passes a current corresponding to the voltage across capacitor C71 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor MN74. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistor MN77 is turned on and off based on the signal on control line AZSL. While transistor MN77 is on, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line VSS.

[0135] The transistors MN72 to MN77 may be transistors using low temperature polysilicon (LTPS), and the transistor MN76 may be a transistor using an oxide semiconductor.

[0136] 5. Modifications Although the embodiments of the present technology have been specifically described above, the content of the present technology is not limited to the above-described embodiments, and various modifications based on the technical concept of the present technology are possible. For example, the configurations, methods, processes, materials, shapes, and numerical values ​​of the above-described embodiments can be combined or substituted with each other as long as they do not deviate from the spirit of the present technology. Furthermore, it is also possible to divide one thing into two or more parts, and it is also possible to omit some parts. Furthermore, as long as the present technology is applicable, the above-described configurations may be appropriately deleted, modified, or added with other configurations, or may be replaced with alternative configurations. Furthermore, the present technology may be an appropriate combination of the above-described embodiments.

[0137] For example, the above-described operational example of the display device 1 is merely an illustrative example of a specific operation, and may be combined with other operational examples to the extent possible. The types and groups of the subpixels described above can be changed as appropriate. For example, the subpixels may be configured by adding infrared laser light IR to the above-described pixels PIX(R), (G), and (B). Furthermore, rather than switching the horizontal drivers 10A and 10B regularly, such as every three lines, the horizontal drivers 10A and 10B may be switched irregularly, for example, by driving the first and second lines with the horizontal driver 10A and the next, third line with the horizontal driver 10B, and then driving the first line with the horizontal driver 10B and the second and third lines with the horizontal driver 10A in the next frame.

[0138] Furthermore, for example, in the above-described embodiment, the horizontal driver 10A is disposed at one end (specifically, at one end in the column direction) of the pixel section 9 including a plurality of pixels PIX, and the horizontal driver 10B is disposed at the other end (specifically, at the other end in the column direction). However, the arrangement is not limited to this. For example, both may be disposed on the same side, or one may be disposed at one end or the other end in the row direction. Also, a division drive may be employed in which the pixel region is divided in the row direction and driven, and the number of divisions and the division positions can be changed as desired. As described above, the vertical band phenomenon caused by division is suppressed.

[0139] Furthermore, for example, as described above, the configurations of the horizontal drivers 10A, 10B and the vertical driver 11 are not limited to a specific one, and the offset cancellation mechanisms of the horizontal drivers 10A, 10B may be configured to correspond to the configurations of the horizontal drivers 10A, 10B. The configuration and method of the offset cancellation function can also be changed as appropriate.

[0140] For example, the present technology can be applied to various displays. For example, the present technology can be applied to display panels such as SXRD (Silicon X-tal Reflective Display: registered trademark) used in projectors, and phase modulation panels using SLM (Spatial Light Modulator) for displaying holograms. In addition, the present technology can be applied to panels such as LCOS (Liquid crystal on silicon, LCoS is a trademark) and HTPS (High Temperature Poly-Silicon).

[0141] For example, in the above-described embodiment, the horizontal drivers 10A and 10B output pixel signals representing luminance by voltage to the pixel unit 9, but the horizontal drivers 10A and 10B may output pixel signals representing luminance by current. In other words, the horizontal drivers 10A and 10B serve as current sources (voltage sources in the above-described embodiment) when generating pixel signals.

[0142] 40 shows an example of the configuration of pixel PIX when this current-based adjustment is performed. This pixel PIX has a capacitor C81, transistors MP81 to MP84, and a light-emitting element EL. Transistors MP81 to MP84 are P-type MOSFETs. The gate of transistor MP81 is connected to a control line WSL and the gate of transistor MP84, one of its source and drain is connected to a signal line SGL, and the other of its source and drain is connected to one end of capacitor C81, the other of the source and drain of transistor MP82, and one of the source and drain of transistor MP83. One end of capacitor C81 is connected to the other of the sources and drains of transistors MP81 and MP82 and one of the source and drain of transistor MP83, and the other end is connected to the gate of transistor MP83 and one of the source and drain of transistor MP84. The gate of transistor MP82 is connected to the control line DSL, one of its source and drain is connected to the power supply line VCCP, and the other of its source and drain is connected to one end of capacitor C81, the other of the source and drain of transistor MP81, and one of the source and drain of transistor MP83. The gate of transistor MP83 is connected to the other end of capacitor C81 and one of the source and drain of transistor MP84, one of its source and drain is connected to one end of capacitor C81 and the other of the sources and drains of transistors MP81 and MP82, and the other of its source and drain is connected to the other of the source and drain of transistor MP84 and the anode of the light-emitting element EL. The gate of transistor MP84 is connected to the control line WSL and the gate of transistor MP81, one of its source and drain is connected to the other end of capacitor C81 and the gate of transistor MP83, and the other of its source and drain is connected to the other of the source and drain of transistor MP83 and the anode of the light-emitting element EL. The anode of the light-emitting element EL is connected to the other of the sources and drains of the transistors MP83 and MP84, and the cathode is connected to the power supply line Vcath.The signal line SGL is supplied with a signal (IDATA) having a current value corresponding to the luminance from the second drive unit 5 .

[0143] With this configuration, in pixel PIX, transistor MP82 is turned off, followed by transistors MP81 and MP84 being turned on. Then, a pixel signal of pixel current IData corresponding to the pixel is supplied from signal line SGL, again turning transistors MP81 and MP84 off. This sets the voltage across capacitor C81 based on the pixel signal supplied from signal line SGL. While transistor MP82 is in the on state, transistor MP83 passes a current corresponding to the voltage across capacitor C81 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor MP83. In this way, pixel PIX emits light at a brightness corresponding to the pixel signal.

[0144] The transistors MP81 to MP84 may be transistors using low temperature polysilicon (LTPS), and at least one of the transistors MP81 and MP84 may be a transistor using an oxide semiconductor.

[0145] 6. Application Examples Next, application examples of the display device 1 described in the above embodiment and modified examples will be described.

[0146] 41 shows an example of the appearance of a head-mounted display 110. The head-mounted display 110 has, for example, ear hooks 112 for wearing on the user's head on both sides of a glasses-shaped display unit 111. The techniques according to the above-described embodiments and the like can be applied to such a head-mounted display 110.

[0147] (Application Example 2) FIG. 42 shows an example of the appearance of another head-mounted display 120. The head-mounted display 120 is a see-through head-mounted display having a main body 121, an arm 122, and a lens barrel 123. This head-mounted display 120 is attached to eyeglasses 128. The main body 121 has a control board and a display unit for controlling the operation of the head-mounted display 120. The display unit emits image light of a display image. The arm 122 connects the main body 121 to the lens barrel 123 and supports the lens barrel 123. The lens barrel 123 projects the image light supplied from the main body 121 via the arm 122 toward the user's eyes via lenses 129 of the eyeglasses 128. The techniques according to the above-described embodiments and the like can be applied to such a head-mounted display 120.

[0148] The head-mounted display 120 is a so-called light guide plate type head-mounted display, but is not limited to this and may be, for example, a so-called birdbath type head-mounted display. The birdbath type head-mounted display includes, for example, a beam splitter and a partially transparent mirror. The beam splitter outputs light encoded with image information toward the mirror, and the mirror reflects the light toward the user's eyes. Both the beam splitter and the partially transparent mirror are partially transparent. This allows light from the surrounding environment to reach the user's eyes.

[0149] (Application Example 3) Figures 43A and 43B show an example of the appearance of a digital still camera 130, with Figure 43A showing a front view and Figure 43B showing a rear view. This digital still camera 130 is a lens-interchangeable single-lens reflex camera and has a camera body 131, a photographing lens unit 132, a grip 133, a monitor 134, and an electronic viewfinder 135. The photographing lens unit 132 is an interchangeable lens unit and is provided near the center of the front of the camera body 131. The grip 133 is provided on the left side of the front of the camera body 131, and is held by the photographer. The monitor 134 is provided to the left of the center of the back of the camera body 131. The electronic viewfinder 135 is provided above the monitor 134 on the back of the camera body 131. By looking through this electronic viewfinder 135, the photographer can visually confirm the optical image of the subject guided by the photographing lens unit 132 and determine the composition. The techniques according to the above-described embodiments can be applied to the electronic viewfinder 135.

[0150] 44 shows an example of the appearance of a television device 140. The television device 140 has an image display screen unit 141 including a front panel 142 and a filter glass 143. The techniques according to the above-described embodiments and the like can be applied to this image display screen unit 141.

[0151] 45 shows an example of the appearance of a smartphone 150. The smartphone 150 has a display unit 151 that displays various information and an operation unit 152 that includes buttons and the like that accept operation inputs from a user. The techniques according to the above-described embodiments and the like can be applied to this display unit 151.

[0152] (Application Example 6) Figures 46A and 46B show an example configuration of a vehicle to which the technology of the present disclosure is applied, where Figure 46A shows an example of the interior of the vehicle as seen from the rear of vehicle 200, and Figure 46B shows an example of the interior of the vehicle as seen from the left rear of vehicle 200.

[0153] The vehicle in Figures 46A and 46B has a center display 201, a console display 202, a head-up display 203, a digital rearview mirror 204, a steering wheel display 205, and a rear entertainment display 206.

[0154] The center display 201 is disposed on the dashboard 261 in a position facing the driver's seat 262 and the passenger's seat 263. While FIG. 46A illustrates an example of a horizontally elongated center display 201 extending from the driver's seat 262 side to the passenger's seat 263 side, the screen size and location of the center display 201 are not limited to this. The center display 201 can display information detected by various sensors. As a specific example, the center display 201 can display an image captured by an image sensor, a distance image to obstacles in front of or to the side of the vehicle measured by a ToF sensor, and the body temperature of an occupant detected by an infrared sensor. The center display 201 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information.

[0155] The safety-related information includes information based on sensor detection results, such as detection of drowsiness, distraction, child mischief, whether a seatbelt is fastened, and whether a passenger is abandoned. The operation-related information includes gesture information related to passenger operations detected by sensors. The gestures may include operations of various vehicle equipment, such as air conditioning, navigation, audiovisual (AV) equipment, and lighting. The life log includes life logs of all passengers. For example, the life log includes a record of each passenger's behavior. By acquiring and storing the life log, it is possible to determine the condition of the passengers at the time of an accident. The health-related information includes the passenger's body temperature detected using a temperature sensor and information on the passenger's health condition estimated based on the detected body temperature. Alternatively, the passenger's health condition information may be estimated based on the passenger's face captured by an image sensor. Furthermore, the passenger's health condition information may be estimated based on the passenger's responses obtained through an automated voice conversation with the passenger. The authentication / identification-related information includes information on a keyless entry function that uses a sensor to perform facial authentication, a function that automatically adjusts the seat height and position by facial recognition, etc. The entertainment-related information includes information on AV device operations by occupants detected by the sensor, and information on content to be displayed that is appropriate for the occupants detected and recognized by the sensor.

[0156] The console display 202 can be used to display, for example, life log information. The console display 202 is disposed near a shift lever 265 on a center console 264 between a driver's seat 262 and a passenger seat 263. The console display 202 can also display information detected by various sensors. The console display 202 may also display an image of the vehicle's surroundings captured by an image sensor, or an image showing the distance to an obstacle around the vehicle.

[0157] The head-up display 203 is virtually displayed behind a windshield 266 in front of the driver's seat 262. The head-up display 203 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information. Since the head-up display 203 is often virtually disposed in front of the driver's seat 262, it is suitable for displaying information directly related to vehicle operation, such as the vehicle speed, the remaining fuel level, and the remaining battery level.

[0158] The digital rearview mirror 204 can not only display the rear of the vehicle, but also display the state of passengers in the rear seats, and can therefore be used to display life log information of passengers in the rear seats, for example.

[0159] The steering wheel display 205 is disposed near the center of the vehicle's steering wheel 267. The steering wheel display 205 can be used to display at least one of, for example, safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information. In particular, because the steering wheel display 205 is located near the driver's hands, it is suitable for displaying life log information such as the driver's body temperature, and for displaying information related to the operation of AV equipment, air conditioning equipment, etc.

[0160] The rear entertainment display 206 is attached to the rear side of the driver's seat 262 and the passenger seat 263 and is intended for viewing by rear seat passengers. The rear entertainment display 206 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information. In particular, since the rear entertainment display 206 is located in front of the rear seat passengers, information related to the rear seat passengers is displayed on the rear entertainment display 206. The rear entertainment display 206 may display, for example, information related to the operation of an AV device or an air conditioning system, or may display the results of measurement of the body temperature of the rear seat passengers using a temperature sensor.

[0161] The techniques according to the above-described embodiments can be applied to the center display 201, the console display 202, the head-up display 203, the digital rearview mirror 204, the steering wheel display 205, and the rear entertainment display 206.

[0162] The present technology may also have the following configurations. (1) A display device comprising: a plurality of pixels arranged in a predetermined direction; a plurality of signal lines connected to each of the plurality of pixels; a driver unit that generates pixel signals to be output to the plurality of signal lines; and a switch unit that switches a connection state between the driver unit and each of the plurality of signal lines, wherein the driver unit has a first driver unit and a second driver unit, and controls the switch unit so that the first driver unit and the second driver unit are assigned to each group of adjacent predetermined pixels. (2) The display device according to (1), wherein the group of predetermined pixels is one or more pixels arranged in the predetermined direction. (3) The display device according to (1) or (2), wherein the group of predetermined pixels is one or more lines along the predetermined direction. (4) The display device according to any of (1) to (3), wherein the group of predetermined pixels is one or more frames. (5) The display device according to any one of (1) to (5), wherein each of the pixels includes a plurality of sub-pixels corresponding to a plurality of predetermined colors, and the predetermined pixel group is a group of all the sub-pixels included in the pixel, lined up in the row direction. (6) The display device according to any one of (1) to (5), wherein each of the pixels includes a plurality of sub-pixels corresponding to a plurality of predetermined colors, and the predetermined pixel group is a group of some of the sub-pixels included in the pixel, lined up in the row direction. (7) The display device according to (6), wherein the predetermined colors include three colors of red (R), green (G), and blue (B), and some of the sub-pixels include green (G). (8) The display device according to (6) or (7), wherein the predetermined colors include four colors of red (R), green (G), blue (B), and white (W), and some of the sub-pixels include white (W). (9) The display device according to any one of (1) to (8), wherein the drive unit includes a differential amplifier used to generate the pixel signal and an offset compression circuit that compresses an offset of the differential amplifier. (10) The display device according to (9), wherein the offset compression circuit is configured with a switched capacitor that combines a capacitance and a switch.(11) The display device according to (9), wherein the offset compression circuit is configured with an adjustment circuit that digitally adjusts the offset. (12) The display device according to any one of (1) to (11), wherein the first drive unit is arranged on one end side of a pixel unit including the plurality of pixels, and the second drive unit is arranged on the other end side. (13) An electronic device having the display device according to any one of (1) to (12).

[0163] 1... display device, 8... timing controller, 9... pixel section, 10A, 10B... horizontal driver, 12A, 12B... horizontal logic section, 13A, 13B... horizontal analog section, 16A, 16B... switch section, 29A, 29B... lamp processing section, 64, 68... amplifier, PIX... pixel, SGL... signal line

Claims

1. A display device comprising: a plurality of pixels arranged in a predetermined direction; a plurality of signal lines connected to each of the plurality of pixels; a drive unit that generates pixel signals to be output to the plurality of signal lines; and a switch unit that switches the connection state between the drive unit and each of the plurality of signal lines, wherein the drive unit has a first drive unit and a second drive unit, and controls the switch unit so that the first drive unit and the second drive unit are assigned to each group of predetermined adjacent pixels.

2. The display device according to claim 1, wherein the predetermined group of pixels is one or more pixels aligned in the predetermined direction.

3. The display device according to claim 1, wherein the predetermined group of pixels is one or more lines along the predetermined direction.

4. The display device according to claim 1, wherein the predetermined group of pixels is one or more frames.

5. The display device according to claim 1, wherein each of the pixels includes a plurality of sub-pixels corresponding to a plurality of predetermined colors, and the group of predetermined pixels is a group of all the sub-pixels included in the pixel that are arranged in the row direction.

6. The display device according to claim 1, wherein each of the pixels includes a plurality of sub-pixels corresponding to a predetermined plurality of colors, and the predetermined group of pixels is a group of some of the sub-pixels included in the pixel, arranged in the row direction.

7. The display device according to claim 6, wherein the predetermined plurality of colors include three colors of red (R), green (G), and blue (B), and some of the sub-pixels include green (G).

8. The display device according to claim 6, wherein the predetermined plurality of colors include four colors of red (R), green (G), blue (B), and white (W), and a portion of the sub-pixels includes white (W).

9. The display device according to claim 1, wherein the drive section comprises a differential amplifier used to generate the pixel signal, and an offset compression circuit that compresses the offset of the differential amplifier.

10. The display device according to claim 9, wherein the offset compression circuit is configured with a switched capacitor that combines a capacitance and a switch.

11. The display device according to claim 9, wherein the offset compression circuit is configured as an adjustment circuit that digitally adjusts the offset.

12. The display device according to claim 1, wherein the first driving section is disposed on one end side of a pixel section including the plurality of pixels, and the second driving section is disposed on the other end side.

13. An electronic device having the display device according to claim 1.

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