Antenna Anti-jamming methods and systems

Abstract

Low elevation angle nulling antenna (LEANAs) designs seek to address interference from sources along the direction of the horizon. However, in many applications, including global navigation satellite systems (GNSS), the signal sources of interest may at a number of elevations and azimuths as may interference sources. Accordingly, a controlled radiation pattern antenna (CRPA) may be employed to selectively null at one or more elevations and azimuths. However, in many applications such as GNSS continuous real-time signal acquisition is required such that the GNSS cannot be offline whilst interference sources are identified. Embodiments of the invention provide for continuous real-time signal acquisition with interference signal location acquisition and CRPA null generation.

Description

ANTENNA ANTI JAMMING METHODS AND SYSTEMSCROSS-REFERENCE TO RELATED INVENTIONS

[0001] This patent application claims the benefit of priority to U.S. Provisional Patent Application 63 / 686,874 filed August 26, 2024; the entire contents of which are incorporated herein by reference.FIELD OF THE INVENTION

[0002] This patent application relates to antennas and more particularly to methods and devices for improving the performance of antennas in the presence of interfering sources and improving anti-jamming performance of antenna systems.BACKGROUND OF THE INVENTION

[0003] Global satellite navigation systems or global navigation satellite systems (GNSS) employ a network of geo-spatially positioned satellites to broadcast precise synchronized navigation messages, thereby providing for determination of a network time and a geolocation by dedicated GNSS receivers. GNSS receivers can therefore provide for a ubiquitous and global time reference, in addition to a host of geolocation uses, ranging from consumer navigation devices to means to monitor global warming to precision agriculture and of course, military applications.

[0004] However, such GNSS receivers are typically dual-band, tri-band or multi-band GNSS receivers with a single GNSS antenna operable over the bandwidth of the GNSS receiver. As such, the GNSS receiver is susceptible to either intentional or unintentional interference and / or jamming from other sources within one or more bands of operation of the GNSS receiver.

[0005] Within the prior art low elevation angle nulling antenna (LEANAs) designs seek to address interference from sources along the direction of the horizon. However, in many applications, such as GNSS, the signal sources of interest may at a number of elevations and azimuths as may interference sources. Accordingly, a controlled radiation pattern antenna (CRPA) may be employed to selectively null at one or more elevations and azimuths. However, in many applications, such as GNSS, continuous real-time signal acquisition is required such that the receiver cannot be offline whilst interference sources are identified.

[0006] Accordingly, it would be beneficial to provide devices and methods of mitigating interference within a GNSS receiver independent of the elevation angle etc. of the interferingsource. It would be further beneficial for the devices and methods to provide for continuous real-time signal acquisition with interference signal location acquisition and CRPA null generation.

[0007] Other aspects and features of the present invention will become apparent to those ordinarily skilled in the art upon review of the following description of specific embodiments of the invention in conjunction with the accompanying figures.SUMMARY OF THE INVENTION

[0008] It is an object of the present invention to mitigate limitations within the prior art relating to antennas and more particularly to methods and devices for improving the performance of antennas in the presence of interfering sources and improving anti -jamming performance of antenna systems.

[0009] In accordance with an embodiment of the invention there is provided a method comprising: providing a first subset of a plurality of RF processing circuits where each RF processing circuit of the first subset of the plurality of RF processing circuits is coupled to a predetermined antenna of a plurality of antennas and processes RF signals within a first frequency range where; each RF processing circuit of the plurality of RF processing circuits comprises an input coupled to predetermined antenna of the plurality of antennas, a first beam forming network (Quiet BFN) comprising a first attenuator and a first phase shifter coupled to the input, a second beam forming network (Active BFN) comprising a second attenuator and a second phase shifter coupled to the input, a first output coupled to the output of the Quiet BFN, and a second output coupled to each Active BFN; providing an RF output port coupled via a combiner to each Quiet BFN of the first subset of the plurality of RF processing circuits via the first outputs of each RF processing circuit of the first subset of the plurality of RF processing circuits; providing an RF detector coupled via another combiner to each Active BFN of the first subset of the plurality of RF processing circuits via the second outputs of each RF processing circuit of the first subset of the plurality of RF processing circuits; andproviding a control circuit coupled to the RF detector, each first attenuator and first phase shifter of each Quiet BFN and to each second attenuator and a second phase shifter of each Active BFN; wherein the control circuit executes a sequence comprising: executing an anti -jamming algorithm by establishing a sweep of a null in a radiation pattern of the plurality of antennas in at least one of azimuth and elevation for the RF signals coupled through the Active BFNs of the first subset of the plurality of RF processing circuits; determining in dependence upon the output of the RF detector as the null of the radiation pattern of the plurality of antennas in at least one of azimuth and elevation is swept a location of a jamming signal; and configuring each Quiet BFN of the first subset of the plurality of RF processing circuits to establish the null in the radiation pattern of the plurality of antennas for the RF signals coupled through the Quiet BFNs of the first subset of the plurality of RF processing circuits to reduce the influence of the jamming signal on the RF signals coupled to the RF output port.

[0010] In accordance with an embodiment of the invention there is provided a system comprising: a first subset of a plurality of RF processing circuits where each RF processing circuit of the first subset of the plurality of RF processing circuits is coupled to a predetermined antenna of a plurality of antennas and processes RF signals within a first frequency range where; each RF processing circuit of the plurality of RF processing circuits comprises an input coupled to predetermined antenna of the plurality of antennas, a first beam forming network (Quiet BFN) comprising a first attenuator and a first phase shifter coupled to the input, a second beam forming network (Active BFN) comprising a second attenuator and a second phase shifter coupled to the input, a first output coupled to the output of the Quiet BFN, and a second output coupled to each Active BFN; an RF output port coupled via a combiner to each Quiet BFN of the first subset of the plurality of RF processing circuits via the first outputs of each RF processing circuit of the first subset of the plurality of RF processing circuits;an RF detector coupled via another combiner to each Active BFN of the first subset of the plurality of RF processing circuits via the second outputs of each RF processing circuit of the first subset of the plurality of RF processing circuits; and a control circuit coupled to the RF detector, each first attenuator and first phase shifter of each Quiet BFN and to each second attenuator and a second phase shifter of each Active BFN; wherein the control circuit executes a sequence comprising: executing an anti -jamming algorithm by establishing a sweep of a null in a radiation pattern of the plurality of antennas in at least one of azimuth and elevation for the RF signals coupled through the Active BFNs of the first subset of the plurality of RF processing circuits; determining in dependence upon the output of the RF detector as the null of the radiation pattern of the plurality of antennas in at least one of azimuth and elevation is swept a location of a jamming signal; and configuring each Quiet BFN of the first subset of the plurality of RF processing circuits to establish null(s) in the radiation pattern of the plurality of antennas for the RF signals coupled through the Quiet BFNs of the first subset of the plurality of RF processing circuits to reduce the influence of the jamming signal(s) on the RF signals coupled to the RF output port.

[0011] In accordance with an embodiment of the invention there is provided a system comprising: a control circuit coupled to an RF detector, each first beam forming network (Quiet BFN) comprising a first attenuator and a first phase shifter and second beam forming network (Active BFN) comprising a second attenuator and a second phase shifter of a processing circuit of a plurality of RF processing circuits; wherein the control circuit executes a sequence comprising: executing an anti -jamming algorithm by establishing a sweep of a null in a radiation pattern of a plurality of antennas in at least one of azimuth and elevation for RF signals coupled through the Active BFNs of a first subset of the plurality of RF processing circuits; determining in dependence upon the output of the RF detector as the null of the radiation pattern of the plurality of antennas in at least one of azimuth and elevation is swept a location of a jamming signal; andconfiguring each Quiet BFN of the first subset of the plurality of RF processing circuits to establish the null in the radiation pattern of the plurality of antennas for the RF signals coupled through the Quiet BFNs of the first subset of the plurality of RF processing circuits to reduce the influence of the jamming signal on the RF signals coupled to the RF output port.

[0012] Other aspects and features of the present invention will become apparent to those ordinarily skilled in the art upon review of the following description of specific embodiments of the invention in conjunction with the accompanying figures.BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Embodiments of the present invention will now be described, by way of example only, with reference to the attached Figures, wherein:

[0014] Figure 1 depicts an RF architecture according to one or more embodiments of the invention;

[0015] Figure 2 depicts a process flow schematic of a hardware and calibration architecture according to one or more embodiments of the invention for an RF architecture such as described and depicted in respect of Figure 1 ;

[0016] Figure 3 depicts a start-up procedure according to an embodiment of the invention for an RF architecture such as described and depicted in respect of Figure 1;

[0017] Figure 4 depicts a process flow for an anti-jamming architecture according to one or more embodiments of the invention for an RF architecture such as described and depicted in respect of Figure 1;

[0018] Figure 5 depicts exemplary schematics of alternate processing circuits for deployment within an RF architecture such as depicted in Figure 1;

[0019] Figure 6 depicts a schematic of a GNSS receiver according to an embodiment of the invention;

[0020] Figure 7 depicts a schematic of a GNSS receiver according to an embodiment of the invention;

[0021] Figures 8A and 8B depict schematics of GNSS receivers according to embodiments of the invention; and

[0022] Figures 9 and 10 depict exemplary detector circuits according to embodiments of the invention and as employed within embodiments of the invention.DETAILED DESCRIPTION

[0023] The present invention is directed to antennas and more particularly to antennas and more particularly to methods and devices for improving the performance of antennas in the presence of interfering sources and improving anti-jamming performance of antenna systems.

[0024] The ensuing description provides representative embodiment(s) only, and is not intended to limit the scope, applicability, or configuration of the disclosure. Rather, the ensuing description of the embodiment(s) will provide those skilled in the art with an enabling description for implementing an embodiment or embodiments of the invention. It being understood that various changes can be made in the function and arrangement of elements without departing from the spirit and scope as set forth in the appended claims. Accordingly, an embodiment is an example or implementation of the inventions and not the sole implementation. Various appearances of “one embodiment,” “an embodiment” or “some embodiments” do not necessarily all refer to the same embodiments. Although various features of the invention may be described in the context of a single embodiment, the features may also be provided separately or in any suitable combination. Conversely, although the invention may be described herein in the context of separate embodiments for clarity, the invention can also be implemented in a single embodiment or any combination of embodiments.

[0025] Reference in the specification to “one embodiment,” “an embodiment,” “some embodiments” or “other embodiments” means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least one embodiment, but not necessarily all embodiments, of the inventions. The phraseology and terminology employed herein is not to be constmed as limiting but is for descriptive purpose only. It is to be understood that where the claims or specification refer to “a” or “an” element, such reference is not to be constmed as there being only one of that element. It is to be understood that where the specification states that a component feature, stmcture, or characteristic “may,” “might,” “can” or “could” be included, that particular component, feature, stmcture, or characteristic is not required to be included.

[0026] Reference to terms such as “left,” “right,” “top,” “bottom,” “front” and “back” are intended for use in respect to the orientation of the particular feature, stmcture, or element within the figures depicting embodiments of the invention. It would be evident that such directional terminology with respect to the actual use of a device has no specific meaning as the device can be employed in a multiplicity of orientations by the user or users.

[0027] Reference to terms “including,” “comprising,” “consisting” and grammatical variants thereof do not preclude the addition of one or more components, features, steps, integers or groups thereof and that the terms are not to be constmed as specifying components, features,steps or integers. Likewise, the phrase “consisting essentially of,” and grammatical variants thereof, when used herein is not to be constmed as excluding additional components, steps, features integers or groups thereof but rather that the additional features, integers, steps, components or groups thereof do not materially alter the basic and novel characteristics of the claimed composition, device or method. If the specification or claims refer to “an additional” element, that does not preclude there being more than one of the additional element.

[0028] Table 1 below presents the operating frequencies for single and dual-band GNSS receivers for civilian and military applications. These being Beidou, Galileo, GLONASS, GPS, and NAVIC. Those for Beidou, Galileo, GLONASS and GPS with provide for dual-band operation in the frequency range 1150MHz-1610MHz. Accordingly, a GNSS antenna supporting both bands is required to support a larger 140MHz bandwidth in the lower band, between approximately 1.160GHz to 1.300GHz, than the approximately 51 MHz at the upper band, between approximately 1.559GHz and 1.610GHz. However, as noted above prior art dual band GNSS antenna structures typically provide wider bandwidth operation at the upper band relative to the lower band.Table 1: Operating Frequencies of GNSS Systems (Nearest 1MHz)

[0029] There is also increasing deployment of satellites which also provide a navigation signal on the L5 band and accordingly GNSS receivers compatible with the L1+L5 signals discretely or L1+ L2 + L5 signals are increasingly deployed. L5 offers several benefits including, but not limited to, increased power relative to L2, being within a band designated by the International Telecommunication Union (ITU) for the Aeronautical Radio-Navigation Services (ARNS)which is less prone to interference with ground based navigation aids and sharing the same frequency space as the E5A signal from Galileo. Similarly, there is benefit in having GNSS receivers compatible with the GPS and Galileo systems, for example, allowing a device comprising such a receiver to be employed in regions where one or both GNSS systems are accessible.

[0030] Whilst the embodiments of the invention are described with respect to a GNSS antenna and a system employing a GNSS receiver it would be evident to one of skill in the art that the embodiments of the invention may be employed with other antenna / receiver systems without departing from the scope of the invention.

[0031] A Controlled Reception Pattern Antenna (CRPA) is an adaptive beam steering antenna whose reception pattern can be adjusted to create nulls in the direction of interfering signals. The CRPA can establish a spatial filter that eliminates or attenuates signals from a particular direction whilst letting through signals from other directions. Accordingly, the CRPA comprises an array of antennas where the phase and amplitude of each antenna can be adjusted relative to that of the other antennae within the array of antenna.

[0032] The CRPA is connected to a processing unit which establishes and controls the reception pattern of the antenna. Within the instance of jamming of a GNSS antenna then a Controlled Reception Pattern GNSS Antenna (CRP-GNSSA) in conjunction with the processing unit identifies a jamming or interfering signal and the reception pattern is adapted to “steer” the antenna gain (or beams) towards the GNSS satellites whilst establishing antenna gain nulls (nulls) in the direction from which the interference is coming from. The control methodology of the CRPA being to protect the low noise amplifier (LNA) of the antenna and the receiver associated with the antenna from saturation.

[0033] Within embodiments of the invention a power-minimization algorithm is used to calculate the complex weight (magnitude and phase) for each antenna in the array to generate the spatial nulls in the radiation pattern. An RF detector is employed to determine the power output from the array where the goal is to ensure the power level is below a threshold that is safe for the operation of the receiver circuit coupled to the antenna array.

[0034] As will become evident from the description below with respect to the embodiments of the invention described and depicted in respect of Figures 1 to 4 if the RF power detected by the RF detector exceeds a threshold, then the antenna generates a single null which is swept around and RF power monitored as a function of the azimuth and elevation angles of this single null as it is swept, this is referred to as power mapping. A drop in the detected RF power during this power mapping implies that the antenna null was directed towards a jammer, i.e., a sourceof an interfering signal, which the inventors refer to as jammer direction finding. By extension, the detection of multiple drops in detected RF power implies multiple jammers.

[0035] Once the spatial orientations of the jammer(s) are located with respect to the antenna, in terms of azimuth angle and elevation angle, then a processing unit, e.g., microprocessor, microcontroller, or a microprocessor based circuit for example, can establish radiation pattern nulls in these directions. The solution for generating the radiation pattern null in the instance of a single jammer is already known as the single null was swept over this direction during the power mapping. However, solutions for multiple nulls must be calculated dynamically by the processing unit. For example, a CRPA may generate a maximum of M nulls for N antennas, where M and N are positive integers. For example, a CPRA may generate N-l nulls for N antennas in the antenna array.

[0036] Once a jammer or jammers are identified and nulled, then the processing unit monitors and tracks them through one or more algorithms in order to establish a continuous solution to nulling the jammers either as a result of motion of the jammer(s) and / or the GNSS antenna (e.g., it is mounted upon a mobile platform).

[0037] Referring to Figures 1 and 2, there are depicted schematics of an exemplary hardware architecture for a CRPA according to and supporting embodiments of the invention. The exemplary Hardware Architecture 100 comprises an array of N GNSS Antennas 110(1) to 110(N), where N is a positive integer. Each GNSS Antenna 110(1) to 110(N) is coupled to a Diplexer 170(1) to 170(N) which separates the input signal into lower and upper GNSS bands, e.g., LI / L2 or L2 / L5 or LI / L5 for example for GPS GNSS systems. However, whilst the embodiments of the invention are described and depicted with lower and upper GNSS bands it would be evident that the principles, algorithms, methodologies etc. depicted according to embodiments of the invention may be applied with three or more bands of a GNSS system, e.g., LI / L2 / L5 for a GPS GNSS system. Similarly, the principles, algorithms, methodologies etc. depicted according to embodiments of the invention may be applied to a single band GNSS system.

[0038] As depicted in Figure 1 the two bands are fully isolated throughout the Hardware Architecture 100 and are only combined by the Band Combiner 150 before the output from the antenna to the GNSS Receiver 160. The Hardware Architecture 100 by separating the bands ensures that saturation within one band does not affect the other band.

[0039] The output of each Diplexer 170(1) to 170(N), being lower and upper GNSS bands, are coupled to their respective Lower Processing Circuit 120B(l) to 120B(N) and Upper Processing Circuit 120A(l) to 120A(N). The design of each Lower Processing Circuit 120B(l)to 120B(N) being the same as that employed for the Upper Processing Circuits 120A(l) to 120A(N) except that the specific element specifications may be slightly different for the different frequency range of operation.

[0040] Optionally, according to the design of the respective Lower Processing Circuits 120B(l) to 120B(N) and Upper Processing Circuits 120A(l) to 120A(N) the Diplexers 170(1) to 170(N) may be programmable such that in one configuration, for example for a GPS GNSS System, the upper band is LI, the lower band is L2 whilst in another configuration the upper and lower bands are LI and L5 respectively and then within a further configuration they are L2 and L5 respectively.

[0041] As depicted, each of the Lower Processing Circuits 120B(l) to 120B(N) and Upper Processing Circuits 120A(l) to 120A(N) comprises in sequence from the diplexer:• First Filter 121;• First Amplifier 122;• Second Filter 123;• Second Amplifier 124;• Third Filter 125; and• Splitter 126 which has outputs coupled to Quiet Beam Forming Network (BFN) 129A and Active BFN 129B.

[0042] Each of the Quiet BFN 129A and Active BFN 129B comprise a Programmable Attenuator 127 and a Programmable Phase Shifter 128. The outputs from the Lower Processing Circuits 120B(l) to 120B(N) are coupled to Lower Active Combiner 130(M) whilst the outputs from the Upper Processing Circuits 120A(l) to 120A(N) are coupled to Upper Active Combiner 130(1) where M equals the number of bands that each diplexer generates.

[0043] The outputs from each Active BFN 129B of the Upper Processing Circuits 120A(l) to 120A(N) are coupled to Upper Active Combiner 130(1) and the outputs from each Active BFN 129B of the Lower Processing Circuits 120B(l) to 120B(N) are coupled to Lower Active Combiner 130(M). Each of the Upper Active Combiner 130(1) and Lower Active Combiner 130(M) comprising Combiner 131 and Detector 132.

[0044] The outputs from each Quiet BFN 129 A of the Upper Processing Circuits 120A(l) to 120A(N) are coupled to Upper Receiver Processing Circuit 140(1) and the outputs from each Quiet BFN 129A of the Lower Processing Circuits 120B(l) to 120B(N) are coupled to Lower Receiver Processing Circuit 130(M). Each of the Upper Receiver Processing Circuit 140(1) and Lower Receiver Processing Circuit 140(M) comprising:• Combiner 141;• Splitter 142;• RF Detector 143 coupled to one output of the Splitter 142;• Third Amplifier 144 coupled to the other output of the Splitter 142; and• Fourth Amplifier 145.

[0045] Optionally a Bypass 146 option may be implemented after the Splitter 142 to bypass the third Amplifier 144 and fourth Amplifier 145 such that the split signal from the Splitter 142 is coupled to the output rather than being coupled via the amplifier chain. This may comprise RF switches to bypass the third Amplifier 144 and fourth Amplifier 145 which are under control of the processing unit which establishes the configuration in dependence upon the RF power detected by the RF Detector 143 for example.

[0046] The outputs from the Upper Receiver Processing Circuit 140(1) and Lower Receiver Processing Circuit 140(M) are coupled to Band Combiner 150 and therein to the GNSS Receiver 160. Alternatively, the Band Combiner 150 may have an output coupled to an RF output port of the Hardware Architecture 100 wherein the signals at the RF output port are coupled to a discrete GNSS Receiver or processed-transmitted to a GNSS Receiver etc.

[0047] In operation the Hardware Architecture 100 operates such that the Active BFNs are employed to continuously search for jammers under control of a processing unit forming part of Hardware Architecture 100 (but not shown for clarity) and / or external to the Hardware Architecture 100 (again not shown for clarity). The processing unit executes a sequence of phase and / or amplitude adjustments to direct a null allowing for detection of movement of previously identified jammer(s), compensation for movement of a platform incorporating the Hardware Architecture 100 as well as identification of new jammers, i.e., the processing unit can perform power mapping and tracking.

[0048] Once the processing unit determines that a jammer is detected then the Quiet BFNs are configured such that the appropriate null is added to the antenna radiation pattern to modify it and “null” the jammer. By appropriate design of the Quiet BFNs then the Hardware Architecture 100 can be configured to establish an equivalent radiation pattern comprising R nulls where R is a positive integer.

[0049] Once a jammer is detected the quiet BFN is configured and the resulting modified radiation pattern is established for the receiver. The modified signal will protect both the antenna and the connected GNSS receiver from jamming. RF detectors on each band split by the diplexers, RF Detector 143 in each of the Upper Receiver Processing Circuit 140(1) andLower Receiver Processing Circuit 140(M), are used to determine the superposition of RF power from all antennas.

[0050] Referring to Figure 2, there is depicted a schematic of a Hardware and Calibration Architecture (HCA) 200 for a GNSS Receiver according to an embodiment of the invention. As depicted the HCA 200 comprises RF Front-End 220, Test 210 and Microcontroller Unit (MCU) 230. The RF Front-End 220 as depicted comprises Antenna Array 222, BFN Circuit 226 and RF Detector 224 wherein an exemplary architecture for the RF Front-End 220 being Hardware Architecture 100 in Figure 1. As depicted the RF Front-End 220 receives signals from a Start-Up Procedure 235 within the MCU 230 and provides signals to an Anti -Jamming Algorithm 250 within the MCU 230. Also coupled to the MCU 230 is Sensor Array 290 comprising sensors providing data to the MCU 230. These may include, but not be limited to, an inertial measurement unit (IMU) 292, which may employ one or more of a gyroscope, one or more accelerometers and a magnetometer for example, a temperature sensor (T_Sensor) 294 and a pressure sensor (P_Sensor) 296.

[0051] The IMU 292 provides data to the MCU 230 which is used to monitor the antenna platforms orientation and assist in mapping jammer signals to enable continuous jammer mitigation. The T_Sensor 294 allows for the MCU 230 to dynamically compensate for temperature variation effects on the complex weights required by the quiet BFNs and active BFNs within the BFN Circuit 226 of the RF Front-End 220. The P_Sensor 296 provides data to the MCU 230 to determine altitude which the MCU 240 can employ creating below horizon nulls on start-up for aerial platforms within which the Hardware and Calibration Architecture (HCA) 200 is integrated. Optionally, an external interface may acquire barometric data from one or more external sources to allow for the adjustment of the P_Sensor 296 data in establishing altitude.

[0052] The MCU 230 may be implemented as software, hardware, firmware or a combination thereof. As will become evident the MCU 230 is used to read detector voltages (V_DET) from the RF Front-End 220, implement the Anti -Jamming Algorithm 250 and store data such as null tables and antenna radiation pattern. The Anti-Jamming Algorithm 250 employs the active BFNs within the BFN Circuit 226, , not depicted for clarity but see Hardware Architecture 100 in Figure 1 for example, to sweep a null or nulls, compare the measured V_DET values with a threshold voltage (V_TH) for anti-jamming protection, calculate the complex weights required to establish a null or nulls, set the null or nulls on quiet BFNs within BFN Circuit 226, not depicted for clarity but see Hardware Architecture 100 in Figure 1 for example.

[0053] As noted with respect to the Hardware Architecture 100 in Figure 1 the RF Front-End 220 may include Bypass 146 functionality within the Upper Receiver Processing Circuit 140(1) and Lower Receiver Processing Circuit 140(M). These can be selectively activated by control signals from the MCU 230 discretely or through the Anti-Jamming Algorithm 250 such that the amplification stages (e.g., third Amplifier 144 and fourth Amplifier 145) between the receiver and the combined outputs of the quiet BFN can be selectively bypassed in case of jamming.

[0054] The Test 210 as depicted comprises the following steps:

[0055] First Test Step 212 wherein each branch of the RF Front-End 220 is measured I characterised, e.g., the Lower Processing Circuits 120B(l) to 120B(N) and Upper Processing Circuits 120A(l) to 120A(N) of the Hardware Architecture 100 in Figure 1; and

[0056] Second Test Step 214 wherein a complex weight calculation is executed to establish calibration for each branch of the RF Front-End 220, e.g., the Lower Processing Circuits 120B(l) to 120B(N) and Upper Processing Circuits 120A(l) to 120A(N) of the Hardware Architecture 100 in Figure 1. These may then be initially stored within a Calibration Table 240 by the MCU 230 for an initial execution of the first and second Test Steps 212 and 214 respectively or employed by MCU 230 to update the Calibration Table 240 for subsequent executions of the first and second Test Steps 212 and 214, respectively.

[0057] As depicted the MCU 230 comprises, in addition to the Calibration Table 240, Start- Up Procedure 235 and Anti-Jamming Algorithm 250, the following elements:

[0058] Null Generator 245 which acquires data from the Calibration Table 240, Radiation Pattern Table 260 and Weight State Table 265 in order to calculate the complex weights and equivalent states for the BFNs, e.g. Quiet BFNs 129A in Lower Processing Circuits 120B(l) to 120B(N) and Upper Processing Circuits 120A(l) to 120A(N) as depicted in Hardware Architecture 100 in Figure 1. These complex weights and equivalent states being providing to the Anti-Jamming Algorithm 250 and therein to the Quiet BFNs within the RF Front-End 220 to generate the nulls for two, three or more jammers;

[0059] Radiation Pattern Table 260 which stores measured radiation patterns of the antennas within the RF-Front End 220 and provides data to the Null Generator 245 and the Anti-Jamming Algorithm 250;

[0060] Weight State Table 265 which stores measured complex weights of the BFNs within the RF Front-End 220 versus the BFN state wherein the data within the Weight State Table 265 is accessed by second Test Step 214, Null Generator 245 and Antijamming Algorithm 250;

[0061] Single Null Generator 270 which calculates the complex weights for the BFNs, e.g., Active BFNs 129B in Lower Processing Circuits 120B(l) to 120B(N) and Upper Processing Circuits 120A(l) to 120A(N) as depicted in Hardware Architecture 100 in Figure 1. These complex weights are provided to the Anti -Jamming Algorithm 250 and therein to the Active BFNs within the RF Front-End 220 to generate the states for a single null which are used in the continuous sweeping to determine the presence of jammers. Single Null Generator 270 receives data from the Calibration Table 240, Radiation Pattern Table 260 and Weight State Table 265 and stores the calculated data within Single Null Table 280; and

[0062] Single Null Table 280 which stores the results from Single Null Generator 270.

[0063] Accordingly, within embodiments of the invention the elements of the MCU 230 execute a series of algorithms and routines. Amongst these are the start-up procedure, antijamming routine and power mapping routine. The start-up procedure, e.g., Start-Up Procedure 235 in Figure 2, and as outlined below in respect of Figure 3, gradually increases the power to ensure safe inputs into the receiver. The anti-jamming routine, e.g., Anti-Jamming Algorithm 250 in Figure 2, establishes jammer detection and nulling as outlined below in respect of Figure 4. The power mapping routine determines the jammers relative direction(s) based on sweeping of nulls and measurements of the output of the RF detector(s).

[0064] If one dominant minimum point is detected during the null sweep, i.e., there is one jammer, then data from pre-stored null table, e.g., Single Null Table 280 in Figure 2, is used to null the jammer. If multiple minima are detected during the null sweep, i.e., there are multiple jammers, then the complex weights required to null the jammers are calculated, the BFN states corresponding the complex weights determined and the jammers nulled.

[0065] If no minimum is detected through the null sweeping, but the RF power exceeds a threshold value then it implies that multiple jammers are simultaneously overwhelming the RF detector, using up the dynamic range. If this condition is determined then the null sweeping is updated to sweep two nulls, either simultaneously or moving one then sweeping the other, etc. It would be evident that the null sweeping may subsequently trigger three null sweeping if again no minimum is detected as three or more jammers are saturating the detector. Thisprocess can be repeated until the maximum number of nulls the CRPA can support are exhausted. For example, this may be N-l nulls for a system with N antennas.

[0066] The MCU 230 also executes other routines including null weight compensation for hardware variances through production calibration of all BFN branches (for example Test 210) within the RF Front-End 220. Further, the MCU 230 provides real-time null weight compensation for temperature variations based upon data from the Temperature Sensor 294.

[0067] Further the MCU 230 can employ spoofing detection. For a given GNSS satellite constellation map, the carrier-to-noise ratio (C / No) should drop when a null is placed on the corresponding azimuth and elevation of a GNSS satellite within the constellation. If it does not then that satellite signal may be being spoofed. Accordingly, the satellite C / No can be used to determine the correct origination of a GNSS signal and block a spoofing signal. It may also identify a strong full constellation spoof from a single origin point.

[0068] The MCU 230 also provides for searching (continuous but this may be periodic, random, aperiodic etc. within other embodiments) and / or tracking of jammers after jammer acquisition either as a result of the jammer moving and / or the platform of which at least the RF Front-End 220 forms part.

[0069] Whilst in most deployment scenarios the MCU 230 and RF Front-End 220 are expected to be co-located this does not have to be the case and accordingly the connectivity between the MCU 230 and RF Front-End 200 may be wired or within other instances wireless such that the RF Front-End 220 and MCU 230 are spatially separated and may part of different platforms, e.g. the RF Front-End 220 if implemented as Hardware Architecture 100 in Figure 1 includes the GNSS Receiver so that the platform upon which RF Front-End 220 is installed and operating can establish global positioning data for itself but antenna control is remote.

[0070] Whilst Figure 2 depicts a single MCU 230 in conjunction with a single RF Front-End 220, other embodiments of the invention may support one or more RF Front-Ends 220 with one or more MCUs 230.

[0071] The embodiments of the invention support a range of operational configuration modes including, but not limited to, stationary near ground, aerial slow speed and aerial high speed. Further, the embodiments of the invention may operate with satellites of a single GNSS system or multiple GNSS systems according to the design of the RF Front-End 220. In respect of jamming then embodiments of the invention may operate within slow dynamic RF environments, quiet RF environments, static RF environments or highly dynamic RF environments depending upon location of deployment, deployment platform etc.

[0072] MCU 230 may receive or transmit data in a proprietary format or according to a standard such as National Marine Electronics Association (NMEA) 0183 or NMEA 2000 for example. This may be via one or more wired or wireless interfaces. Similarly, the MCU 230 may exploit one or more wired or wireless interfaces to perform one or more actions including, but not limited to, updating antenna firmware, providing operation status information, providing jammer data to remote systems and configuring operational status. For example, multiple systems may transmit azimuth and elevation data of a jammer together with their location data allowing triangulation of the jammer(s).

[0073] Within embodiments of the invention the MCU 230 may, based upon determining an altitude of the RF Front-End 220 and / or MCU 230, dynamically create one or more pre-emptive nulls below the antenna for aerial platforms or mast / tower based platforms etc.

[0074] Now referring to Figure 3 there is depicted a Start-Up Flow 300 such as may form part of an antenna start-up sequence, such as Start-Up Procedure 235 as executed by MCU 230 in Figure 2. As depicted Start-Up Flow 300 comprises first to seventh steps 310 to 370, respectively. These being:

[0075] First Step 310 wherein the process is initiated upon initial power up or upon restarting an antenna;

[0076] Second Step 320 wherein attenuators within the antenna are set to their maximum setting and phase shifters are set to a nominal phase shift, e.g. zero phase shift;

[0077] Third Step 330 wherein the RF power level is read from the RF detector within the RF Front-End 220;

[0078] Fourth Step 340 wherein a determination is made as to whether the signal from the RF detector (V_Det) is greater than a threshold value (V_Th) or not where if a positive determination is made that V_Det is greater than V_Th then Start-Up Flow 300 progresses to fifth Step 350 and ends as the RF power is sufficient otherwise it proceeds to sixth Step 360;

[0079] Fifth Step 350 wherein the process of Start-Up Flow 300 ends;

[0080] Sixth Step 360 wherein a determination is made as to whether the minimum attenuation of the attenuator has been reached or not where upon a positive determination that the minimum attenuator setting has been reached the process proceeds to fifth Step 350 otherwise it proceeds to seventh Step 370; and

[0081] Seventh Step 370 wherein the attenuation setting of the attenuator is reduced and the process loops back to third Step 330.

[0082] The attenuators within second Step 320 may, for example with reference to Hardware Architecture 100, be the Programmable Attenuators 127 within the Quiet BFN 129 A and Active BFN 129B of the Lower Processing Circuits 120B(l) to 120B(N) and / or Upper Processing Circuits 120A(l) to 120A(N).

[0083] The phase shifters within second Step 320 may, for example with reference to Hardware Architecture 100, be the Programmable Phase Shifter 128 within the Quiet BFN 129 A and Active BFN 129B of the Lower Processing Circuits 120B(l) to 120B(N) and / or Upper Processing Circuits 120A(l) to 120A(N).

[0084] The RF detectors within the third Step 330 may, for example with reference to Hardware Architecture 100, be the Detector 132 within the Upper Active Combiner 130(1) and / or Lower Active Combiner 130(M). It would be evident that the description with respect to Figure 3 for the Start-Up Flow 300 relates to a single RF band, e.g., that associated with the Upper Processing Circuits 120A(l) to 120A(N) or the Lower Processing Circuits 120B(l) to 120B(N). However, it would be obvious to one of skill in the art that a multiple band RF array, such as depicted in Figure 1 with Hardware Architecture 100, may execute Start-Up Flow 300 for each band individually.

[0085] Now referring to Figure 4 there is depicted Anti -Jamming Flow 400 according to an embodiment of the invention such as may form part of an Anti-Jamming process, such as Antijamming Algorithm 250 as executed by MCU 230 in Figure 2. As depicted Anti-Jamming Flow 400 comprises first to seventh Steps 405 to 460 respectively together with first to fourth Tables 465 to 490, respectively. Anti-Jamming Flow 400 relates to continuous scanning with the Active BFNs to identify jammers dynamically during receipt of signals via the Quiet BFNs. The steps of Anti-Jamming Flow 400 being:

[0086] First Step 405 wherein the process starts;

[0087] Second Step 410 wherein a RF detector voltage is read

[0088] Third Step 420 wherein a determination is made as to whether the signal from the RF detector (V_Det) is greater than a threshold value (V_Th) or not where if a positive determination is made that V_Det is greater than V_Th then Anti -Jamming Flow 400 progresses to fourth Step 430 otherwise it proceeds back to second Step 410;

[0089] Fourth Step 430 which is a power mapping routine comprising first to fourth Sub-Steps 432 to 438 which are described and depicted below which employs data from a first Table 465 and provides data to a second Table 470 to establish the locations of one or more jammers for which nulls are to be generated;

[0090] Fourth Step 440 wherein the complex weights for the angle(s) with minimum V_Det are calculated using the data from second Table 470, these angle(s) being those at which nulls are to be generated;

[0091] Fifth Step 450 wherein the attenuator settings and phase shifter settings for the BFNs, namely the Quiet BFNs 129A feeding the Receiver 160 with reference to the Hardware Architecture 100 in Figure 1, are established to generate the complex weights for the angle(s) at which nulls are to be established; and

[0092] Sixth Step 460 where the attenuators and phase shifters within the BFNs are set to the attenuator settings and phase shifter settings established in fifth Step 450.

[0093] The RF detector within Step 410 may, for example with reference to Hardware Architecture 100, be the Detector 132 within the Upper Active Combiner 130(1) and / or Lower Active Combiner 130(M).

[0094] The attenuators within fifth Step 450 may, for example with reference to Hardware Architecture 100, be the Programmable Attenuators 127 within the Quiet BFN 129 A and Active BFN 129B of the Lower Processing Circuits 120B(l) to 120B(N) and / or Upper Processing Circuits 120A(l) to 120A(N).

[0095] The phase shifters within fifth Step 450 may, for example with reference to Hardware Architecture 100, be the Programmable Phase Shifter 128 within the Quiet BFN 129 A and Active BFN 129B of the Lower Processing Circuits 120B(l) to 120B(N) and / or Upper Processing Circuits 120A(l) to 120A(N).

[0096] As noted, fourth Step 430 is a power mapping routine comprising first to fourth SubSteps 432 to 438 respectively, these being:• First Sub-Step 432 wherein location of a null is established based upon data retrieved from first Table 465 retrieved;• Second Sub-Step 434 wherein the attenuation and phase shifter settings for a null are configured;• Third Sub-Step 436 wherein the RF detector output is read and stored in Table 470; and• Fourth Sub-Step 438 wherein a determination is made as to whether all nulls fromTable 465 have been used.

[0097] The first to fourth Tables 465 to 490 being:• First Table 465 which stores single null locations together with the attenuator and phase shifter states of the BFNs to establish the null at the azimuth and elevation of the null location;• Second Table 470 which receives and stores data relating to null location and detector voltages which are then employed to establish locations of jammer(s) based upon detecting minima in detector voltage;• Third Table 480 which stores the hardware calibration parameters; and• Fourth Table 490 which stores the weight State parameters.

[0098] Within the description above the processes, algorithms etc. have been described with respect to employing an output voltage from the RF detectors, such as the Detector 132 within each of the Upper Active Combiner 130(1) and Lower Active Combiner 130(M) within the Hardware Architecture 100 in Figure 1. However, it would be evident that within embodiments of the invention this output voltage may alternatively be digital data such as from an analog- to-digital converter (ADC) for example. Within embodiments of the invention a RF detector may be a root mean square (RMS) detector providing a DC RMS power measurement, a logarithmic detector, a logarithmic RMS detector, a Successive Detection Log Video Amplifiers (SDLVA) or a Vector Power detector.

[0099] As evident from Table 1 each band has a bandwidth within which the GNSS satellites transmit narrowband signals. Further, if a GNSS receiver is intended to operate with multiple GNSS systems discretely or concurrently then bandwidth of each band increases. For example, these bandwidths if meeting International Telecommunications Union - Radiocommunication (ITU-R) maybe l,559MHz-l,610MHz (covering LI, El, and Bl), 1,215-1,300 MHz (covering L2, E6, B3, and L6) and 1,164-1,215 MHz (covering L5, E5, B2, and L3). However, LI GPS satellite signals are at 1, 575.420MHz within this l,559MHz-l,610MHz band and L5 GPS satellite signals are at 1,176.450 within the 1,164-1,215 MHz band. Accordingly, a device may within Hardware Architecture 100 in Figure 1 be jamming the GNSS receiver operating upon GPS signals if its transmitting in the frequency band even if it is not overlapping with the actual GPS frequency.

[0100] Referring to Figure 5 there are depicted first and second Processing Circuits 500A and 500B for deployment within an RF architecture such as Hardware Architecture 100 depicted in Figure 1 to mitigate this. As depicted Hardware Architecture 100 comprises Processing Circuit 120A(l) which is one processing circuit of the Lower Processing Circuits 120B(l) to 120B(N) and Upper Processing Circuits 120A(l) to 120A(N). Processing Circuit120A(l) comprising Quiet BFN 129A and Active BFN 129B. Hardware Architecture 100 comprises Diplexers 170(1) to 170(N) on the N antennas which split the received signals into bands, e.g., L1 / L2, L1 / L5 or L2 / L5 for GPS for example.

[0101] First Processing Circuit 500A provides an alternate design to that employed within Hardware Architecture 100 for the Lower Processing Circuits 120B(l) to 120B(N) and Upper Processing Circuits 120A(l) to 120A(N) respectively. First Processing Circuit 500A comprises a first Stage 510 which mirrors the first five elements of the processing circuits in Hardware Architect 100 and so comprises a filter, amplifier, filter, amplifier and filter sequence, e.g., first Filter 121, first Amplifier 122, second Filter 123, second Amplifier 124 and third Filter 125 depicted in Figure 1. Disposed after the first Stage 510 but before the Splitter 126 which couples to Quiet BFN 129A and Active 129B is a Programmable Filter 520. The Programmable Filter 520 according to embodiments of the invention allowing programmable blocking of a frequency band overlapping a jammer but not the GNSS signal. Second Processing Circuit 500B comprises the same first Stage 510 but now first and second Programmable Filters 520A and 520B are disposed between the Splitter 126 and the Quiet BFN 129A and Active 129B, respectively.

[0102] Use of the programmable filters, Programmable Filter 520 and first and second Programmable Filters 520A and 520B, may, for example, enable jammers to be nulled which would otherwise require broad nulls, i.e. they have large azimuthal and elevational spread (based upon them being close to the system for example), or null jammers when the maximum number of nulls of the system have been reached. Exemplary architectures for Programmable Filter 520 and first and second Programmable Filters 520A and 520B being depicted in Figures 6 to 10, respectively.

[0103] Figure 6 depicts a schematic of a Programmable Filter (P -Filter) 600 according to an embodiment of the invention. As depicted a Band Splitter 620 splits received signals within a first frequency range to a first Signal Processing Circuit (SPC) 600A and within a second frequency range to a second Signal Processing Circuit (SPC) 600B. The outputs of the upper SPC 600A and lower SPC 600B are coupled to a Band Combiner 660 which combines the signals within the first and second frequency ranges to a common output which is coupled to an Amplifier 670. The output of the Amplifier 670 being coupled to receiver processing circuitry which is not depicted for clarity.

[0104] First SPC 600A comprises a first Pre-Amplifier 630A, a first Detector Circuit 640A and a first Signal Processing Element (SPE) 650A. The second SPC 600B comprises a second Pre-Amplifier 630B, a second Detector Circuit 640B and a second Signal Processing Element(SPE) 650B. Each of the first and second SPE 650A and 650B process or pre-process the amplified signals within their respective SPC prior to their being coupled to the Amplifier 670 and the subsequent receiver processing circuitry.

[0105] The first and second Detector Circuits 640A and 640B respectively being coupled to Controller 680. Within embodiments of the invention the Controller 680 may form part of the overall control circuitry of the receiver or it may form part of a control circuit for a receiver front-end comprising the Band Splitter 620, Band Combiner 660 and first and second SPCs 650A and 650B

[0106] Within some embodiments of the invention the first and second SPE 650A and 650B operate solely upon signals within the frequency ranges defined by the Band Splitter 620 for the first and second SPCs 600A and 600B respectively such that the signals coupled from the first SPC 600A to the Band Combiner 660 are within the first frequency range and those coupled from the second SPC 600B to the Band Combiner 660 are within the second frequency range.

[0107] Within other embodiments of the invention the first and second SPE 650A and 650B operate upon signals within the frequency ranges defined by the Band Splitter 620 for the first and second SPCs 600A and 600B respectively such that the signals coupled from the first SPC 600A to the Band Combiner 660 are within a third frequency range and those coupled from the second SPC 600B to the Band Combiner 660 are within a fourth frequency range. Each of the third and fourth frequency ranges may be established by at least one of filtering, mixing and down-conversion.

[0108] Each of the first and second Detector Circuits 640A and 640B respectively may comprise a circuit such as depicted in Figure 9 respectively comprising a signal tap, a power detector and a switch or as depicted in Figure 10 comprising a signal tap, a power detector, a filter and a switch. However, it would be evident that other designs as described and depicted in respect of Figures 9 and 10 or other designs may be implemented for each of the first and second Detector Circuits 640A and 640B respectively to selectively block or pass all of the signals within the respective Signal Processing Circuit or a subset of the signals within the respective Signal Processing Circuit. For example, considering first SPC 600A then the first Detector Circuit 640A may block or pass all signals within the first frequency range or it may block and selectively pass one or more frequency subsets within the first frequency range according to the design and implementation of the first Detector Circuit 640A. Within embodiments of the invention the designs of the first and second Detector Circuits 640A and 640B may be of the same design or they may be of different designs.

[0109] Figure 9 depicts an exemplary Detector Circuit 900 according to an embodiment of the invention and as employed within embodiments of the invention such as described and depicted within Figures 6 to 8 for detector circuits. The Detector Circuit 900 comprises a Tap 910 for coupling a portion of the received signals to a Detector 930 whilst the remaining portion is coupled to Gate 920. The output of the Detector 930 is coupled to Control 940 which is in turn coupled within the Detector Circuit 900 to the Gate 920 and externally to the control circuit , e.g., Controller 680 in Figure 6. Based upon the control signal(s) or decision(s) provided from the external control circuit the Control 940 places the Gate 920 into a first state such the signals are passed through or into a second state wherein the signals are blocked from passing though. Gate 920 may be an electronically controlled 1:1 switch, a N:M switch, or a programmable attenuator within different embodiments of the invention.

[0110] Optionally, within other embodiments of the invention the Control 940 undertakes the determination of whether to block or pass the signals and communicates its decision to the external control circuit , e.g., Controller 680 in Figure 6. Where the Gate 920 is a programmable attenuator the decision from the Control 940 and / or external control circuit may be attenuate the signals by a predetermined amount.

[0111] Accordingly, signals are either passed or blocked by each of the first and second Detector Circuits 640A and 640B respectively, ignoring the scenarios where the signals are attenuated, in dependence upon whether the signal(s) detected either of the first and second Detector Circuits 640A and 640B respectively exceeds a predetermined threshold. Within the exemplary scenario of GNSS receivers the received signals from the GNSS satellites, which may be approximately -120dBm to -125dBm, then interfering signals within the first frequency range will be at higher power levels. Accordingly, for example, signal(s) detected within the first frequency range coupled to the first SPC 600A above a predetermined threshold, e.g. - 115dBm, are likely to be interfering wireless sources such that P-Filter 600 blocks these signals from propagating through the first SPC 600A to Band Combiner 660 and therein Amplifier 670. Similarly, any interfering signals within the second frequency range coupled to the second SPC 600B above a predetermined threshold, e.g. -115dBm, are likely to be interfering wireless sources such that the P-Filter 600 blocks these signals from propagating through the second SPC 600B to Band Combiner 660 and therein Amplifier 670.

[0112] Optionally, the predetermined thresholds for the first and second Detector Circuits 640A and 640B respectively may be the same or they may be different.

[0113] Optionally, the predetermined thresholds are pre-configured into the control circuitry of the Controller 680 and / or the control circuits within the first and second Detector Circuits 640A and 640B.

[0114] Optionally, the predetermined thresholds are configured into the control circuitry of the Controller 680 and / or the control circuits within the first and second Detector Circuits 640A and 640B based upon one or more factors including, but not limited to, the intended GNSS satellite system(s) the system is to be employed with, the location of the GNSS antenna and / or receiver, the accessible GNSS satellite system(s) etc.

[0115] Figure 7 depicts a schematic of a P-Filter 700 according to an embodiment of the invention. The P-Filter 700 processes signals received via first and second Signal Processing Circuits (SPCs) 700A and 700B, respectively. In common with the first SPC 600A in Figure 6 this processes signals within a first frequency range within the upper SPC 700A and signals within a second frequency range within the lower SPC 700B. However, in contrast to P-Filter 600 first and second Amplifiers 710A and 710B are disposed between the first and second SPCs 700A and 700B and the Combiner 660 rather than a single post-combination amplifier. Similarly, the detector circuits, first and second Detector Circuits 640A and 640B in P-Filter 600, within each of the first and second SPCs 700A and 700B are replaced with first and second Detector Circuits 720 A and 720B.

[0116] The first SPC 600A comprises in addition to the first Detector Circuit 720A the first Pre-Amplifier 630A and the first Signal Processing Element (SPE) 650A. The second SPC 600B comprises in addition to the second Detector Circuit 720B the second Pre-Amplifier 630B and the second Signal Processing Element (SPE) 650B. Each of the first and second SPE 650A and 650B process or pre-process the amplified signals within their respective SPC prior to their being coupled to the first and second Amplifiers 710A and 710B, the Combiner 160 and the subsequent receiver processing circuitry.

[0117] Optionally, the first and second Detector Circuits 720A and 720B are similar to first and second Detector Circuits 640A and 640B in Figure 6 and as described and depicted with respect to Figures 9 and 10. However, within other embodiments of the invention it may be appropriate to remove the gate functionality from the detector circuits of Figures 9 and 10 and power down one of the amplifier, i.e. one of the first and second Amplifiers 710A and 710B, to block the signals on that respective path between the Splitter 660 and Combiner 670. This may be determined by one or more factors such as the power down transmission characteristics of the first and second Amplifiers 710A and 710B and the power on time response of the first and second Amplifiers 710A and 710B.

[0118] It would be evident that the Band Splitter 620 and Band Combiner 660 in Figures 6 and 7 are operating upon sub-bands of the band of the signal processing circuit that the P-Filter 600 or P-Filter 700 forms part of, e.g. the band of the Lower Processing Circuits 120B(l) to 120B(N) or the Upper Processing Circuits 120A(l) to 120A(N) respectively as depicted in Figure 1. Similarly, the Splitter 820 and Combiner 840 in Figures 8A and 8B are operating upon sub-bands of the band of the signal processing circuit that the P-Filter 800 or P-Filter 8000 forms part of, e.g. the band of the Lower Processing Circuits 120B(l) to 120B(N) or the Upper Processing Circuits 120A(l) to 120A(N) respectively as depicted in Figure 1.

[0119] The P-Filter designs depicted in Figure 6 can be generalized, as depicted in Figure 8A which depicts P-Filter 800, according to an embodiment of the invention. Accordingly, the received signals are coupled to Splitter 820 which generates N outputs each comprising signals within a defined frequency range. The N outputs of the Splitter 820 being coupled to N Signal Processing Circuits (SPCs) 830(1) to 830(N) respectively whose outputs are coupled to Combiner 840 and therein to Amplifier 850. Disposed within each of the N SPCs 830(1) to 830(N) are Detector Circuits 870(1) to 870(N) which are coupled to Control Circuit 860. Each of the Detector Circuits 870(1) to 870(N) respectively being as described and depicted with respect to Figures 6-7 and 9-10 or as described within this specification according to other embodiments of the invention. Accordingly, the presence of interfering signal source(s) of defined frequency(ies) with power exceeding a defined threshold results in the respective Detector Circuit 870(1) to 870(N) blocking the signals within the frequency range of an SPC 830(1) to 830(N) that includes the interfering signal source(s). Within embodiments of the invention, N may be a positive integer greater than or equal to 1. The frequencies ranges of each Signal Processing Unit of the N SPCs 830(1) to 830(N) within embodiments of the invention may be non-overlapping or may overlap one or more other frequency ranges by defined amounts.

[0120] Similarly, the P-Filter designs depicted in Figure 7 can be generalized, as depicted in Figure 8B which depicts P-Filter 8000, according to an embodiment of the invention. Accordingly, the received signals are coupled to Splitter 820 which generates N outputs each comprising signals within a defined frequency range. The N outputs of the Splitter 820 being coupled to N Signal Processing Circuits (SPCs) 830(1) to 830(N) respectively whose outputs are each coupled to one of N Amplifiers 880(1) to 880(N) and therein to Combiner 840. Disposed within each of the N SPCs 830(1) to 830(N) are Detector Circuits 870(1) to 870(N) which are coupled to Control Circuit 860. Each of the Detector Circuits 870(1) to 870(N) respectively being as described and depicted with respect to Figures 6-7 and 9-10 or asdescribed within this specification according to other embodiments of the invention. Accordingly, the presence of interfering signal source(s) of defined frequency(ies) with power exceeding a defined threshold results in the respective Detector Circuit 870(1) to 870(N) blocking the signals within the frequency range of an SPC 830(1) to 830(N) that includes the interfering signal source(s). Within embodiments of the invention, N may be a positive integer greater than or equal to 1. The frequencies ranges of each Signal Processing Unit of the N SPCs 830(1) to 830(N) within embodiments of the invention may be non-overlapping or may overlap one or more other frequency ranges by defined amounts.

[0121] Within the embodiments described and depicted above in respect of P-Filter 600, 700 and 800 in Figures 6 to 8B employing detector circuits such as described and depicted by Detector Circuit 900 in Figure 9 then signals within a path are blocked or passed by the Gate 920, although where the Detector Circuit 900 employs a programmable attenuator as Gate 920 then the option also exists for the signals within a path to be attenuated. If an interfering signal is not significantly over the predetermined threshold, then it may be attenuated to avoid saturating the subsequent circuit(s) with the potential for recovery of data from the intended signal.

[0122] However, within other embodiments of the invention such as described and depicted with respect to Detector Circuit 1000 in Figure 10 other control and decision methodologies may exist within embodiments of the invention. As depicted in Figure 10 the Detector Circuit 1000 comprises the Tap 910, Gate 920, Detector 930, and Control 940 as described with respect to Figure 9. However, Detector Circuit 1000 now includes a Filter 1010. Within an embodiment of the invention the Filter 1010 may be a tunable notch or bandstop filter of defined characteristics of attenuation versus frequency offset. Accordingly, upon determination of an interfering signal source the Control 940 discretely or in combination with a controller such as Controller 680 in Figures 6-7 or Controller 860 in Figures 8A and 8B may sweep the center frequency of the Filter 1010 to determine whether the interfering source can be filtered out whilst allowing the system to still operate upon that frequency range within which the interfering source is present. Upon a positive determination the system may progress otherwise the Gate 920 may be operated to block the signals upon that path. Filter 1010 may, for example, be a tunable N-path filter, a switchable transmissive filter array, switchable reflective filter array or other filter design as known in the art.

[0123] Within other embodiments of the invention the frequency characteristics of the Filter 1010 may be tunable / configurable so that the system employing embodiments of the invention may seek to mitigate the impact of interfering signal source(s).

[0124] Within other embodiments of the invention a spectrum analyser (SA) may be employed to provide data relating to signals detected, both desired frequencies (e.g., signals from GPS satellites within the LI, L2 and L5 bands) and unwanted (e.g., interfering signal sources). The SA may provide data to the controller(s) of a P-Filter, such as P-Filter 600, 700 and 800 in Figures 6-8, and to configure the filter(s) within the P-Filter to block the interfering sources or limit the P-Filter by turning a gate off etc. and / or system to which the P-Filter provides signals after processing by the Signal Processing Circuits (SPCs) within the P-Filter and amplification.

[0125] A benefit of second Processing Circuit 500B over first Processing Circuit 500A is that the second Programmable Filter 520B can be employed in conjunction with the Active BFN 129B to generate the requisite information with respect to filtering / nulling jammers which is then employed by the first Programmable Filter 520A and Quiet BFN 129A to filter / null jammers and extract the GNSS signals. Accordingly, active scanning can be performed continuously with updates to the signal acquisition portion based upon a change in the location, frequency, etc. of jammers.

[0126] Within Figure 1 there is depicted a Hardware Architecture 100 according to an embodiment of the invention for use in conjunction with a Controlled Reception Pattern Antenna (CRPA). As depicted each GNSS Antenna of a set of GNSS Antennas 110(1) to 110(N) is coupled to a Diplexer of a set of Diplexers 170(1) to 170(N) where each Diplexer separates the input signal into lower and upper GNSS bands, e.g., LI / L2 or L2 / L5 or LI / L5 for example for GPS GNSS systems. The lower GNSS band from each Diplexer is coupled to a Lower Processing Circuit such that Lower Processing Circuits 120B(l) to 120B(N) process the signals from the set of GNSS Antennas 110(1) to 110(N) which are then coupled to the Lower Active Combiner 130(M). The upper GNSS band from each Diplexer is coupled to a Upper Processing Circuit such that Upper Processing Circuits 120A(l) to 120A(N) process the signals from the set of GNSS Antennas 110(1) to 110(N) which are then coupled to the Upper Active Combiner 130(1). Each of the Lower Active Combiner 130(M) and Upper Active Combiner 130(1) comprise a Combiner 131 and Detector 132.

[0127] Each Lower Processing Circuit of the Lower Processing Circuits 120B(l) to 120B(N) and Upper Processing Circuit of the Upper Processing Circuits 120A(l) to 120A(N) as depicted in Figure 1 comprises a first Filter 121, a second Filter 123 and a Third Filter 125. However, the isolation between the upper and lower bands from the diplexers and the chain of filters within each processing circuit for a band may be insufficient to achieve the required isolation of the upper and lower band signals at one or both of the Lower Active Combiner 130(M) andUpper Active Combiner 130(1). For example, rejection of the upper band at the Lower Active Combiner 130(1) may be below the required isolation.

[0128] Accordingly, within other embodiments of the invention additional filtering may be implemented to enhance the isolation of the band being processed from the other band or bands by providing the additional filtering by one or more of:• within the Lower Active Combiner 130(1) and / or the Upper Active Combiner130(M);• between each processing circuit and its associated combiner e.g. between the output of each of the Upper Processing Circuits 120A(l) to 120A(N) and the Upper Band Combiner 130(1) and / or the output of each of the Lower Processing Circuits 120B(l) to 120B(N) and the Lower Band Combiner 130(M); and• after each Active BFN 129B of each of Upper Processing Circuits 120A(l) to120A(N) and / or each Active BFN 129B of each of the Lower Processing Circuit 120B(l) to 120B(N).

[0129] Such additional filtering may comprise a fixed bandpass filter, a tunable bandpass filter, two or more fixed bandpass filters, two or more tunable bandpass filters or a combination of one or more fixed bandpass filters with one or more tunable bandpass filters. Other filtering concepts and filtering devices may be employed within embodiments of the invention without departing from the scope of the invention.

[0130] In addition to considerations of rejection of signals within other bands at each of the Upper Band Combiner 130(1) and the Lower Band Combiner 130(M) a further consideration exists with respect to the signal levels received at each Detector 132 after the Combiner 131 with each of the Upper Band Combiner 130(1) and the Lower Band Combiner 130(M). Accordingly, within embodiments of the invention additional gain may be implemented within Hardware Architecture 100 to improve the signal received at the Detector 132 within one or both of the Upper Band Combiner 130(1) and the Lower Band Combiner 130(M).

[0131] Additional gain may be implemented by one or more:• within the Lower Active Combiner 130(1) and / or the Upper Active Combiner130(M) before the Detector 132;• between each processing circuit and its associated combiner e.g. between the output of each of the Upper Processing Circuits 120A(l) to 120A(N) and the Upper Band Combiner 130(1) and / or the output of each of the Lower Processing Circuits 120B(l) to 120B(N) and the Lower Band Combiner 130(M); and• after each Active BFN 129B of each of Upper Processing Circuits 120A(l) to 120A(N) and / or each Active BFN 129B of each of the Lower Processing Circuit 120B(l) to 120B(N).

[0132] Within other embodiments of the invention additional filter functionality and additional gain may both be implemented either at common locations within the architecture or at different points within the architecture.

[0133] Whilst the description above describes an architecture with two bands, upper and lower, it would be evident that the concepts may be applied to antennas operating on a single band or on multiple bands.

[0134] Further, whilst the description above describes an architecture with fixed bands, e.g. GNSS LI / L2 or L2 / L5 or LI / L5 for example, it would be evident that the architectures may be applied to CRPA on any operating band or operating bands. Further, within other embodiments of the invention with tunable bands the operating band may be dynamically configured.

[0135] Specific details are given in the above description to provide a thorough understanding of the embodiments of the invention. However, it is understood that the embodiments may be practiced without these specific details.

[0136] The foregoing disclosure of the exemplary embodiments of the present invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many variations and modifications of the embodiments described herein will be apparent to one of ordinary skill in the art in light of the above disclosure. The scope of the invention is to be defined only by the claims appended hereto, and by their equivalents.

Claims

CLAIMSWhat is claimed is:

1. A method comprising: providing a first subset of a plurality of RF processing circuits where each RF processing circuit of the first subset of the plurality of RF processing circuits is coupled to a predetermined antenna of a plurality of antennas and processes RF signals within a first frequency range where; each RF processing circuit of the plurality of RF processing circuits comprises an input coupled to predetermined antenna of the plurality of antennas, a first beam forming network (Quiet BFN) comprising a first attenuator and a first phase shifter coupled to the input, a second beam forming network (Active BFN) comprising a second attenuator and a second phase shifter coupled to the input, a first output coupled to the output of the Quiet BFN, and a second output coupled to each Active BFN; providing an RF output port coupled via a combiner to each Quiet BFN of the first subset of the plurality of RF processing circuits via the first outputs of each RF processing circuit of the first subset of the plurality of RF processing circuits; providing an RF detector coupled via another combiner to each Active BFN of the first subset of the plurality of RF processing circuits via the second outputs of each RF processing circuit of the first subset of the plurality of RF processing circuits; and providing a control circuit coupled to the RF detector, each first attenuator and first phase shifter of each Quiet BFN and to each second attenuator and a second phase shifter of each Active BFN; wherein the control circuit executes a sequence comprising: executing an anti -jamming algorithm by establishing a sweep of a null in a radiation pattern of the plurality of antennas in at least one of azimuth and elevation for the RF signals coupled through the Active BFNs of the first subset of the plurality of RF processing circuits; determining in dependence upon the output of the RF detector as the null of the radiation pattern of the plurality of antennas in at least one of azimuth and elevation is swept a location of a jamming signal; and configuring each Quiet BFN of the first subset of the plurality of RF processing circuits to establish the null in the radiation pattern of the plurality of antennas for theRF signals coupled through the Quiet BFNs of the first subset of the plurality of RF processing circuits to reduce the influence of the jamming signal on the RF signals coupled to the RF output port.

2. The method according to claim 1 , wherein the control circuit continuously executes the anti -jamming algorithm but only periodically reconfigures each Quiet BFN of the first subset of the plurality of RF processing circuits to establish the null in the radiation pattern of the plurality of antennas.

3. The method according to claim 1, further comprising providing an inertial measurement unit (IMU) associated with a platform comprising the plurality of antennas which provides data to the control circuit with respect to an orientation of the platform which is employed by the control circuit to map the jamming signal and dynamically re-configure each Quiet BFN of the first subset of the plurality of RF processing circuits to reduce the influence of the jamming signal.

4. The method according to claim 1, further comprising providing at least one: a pressure sensor associated with a platform comprising the plurality of antennas which provides data to the control circuit to determine an altitude of the platform which the control circuit employs to configure one or more below horizon nulls within the radiation pattern of the plurality of antennas; and a temperature sensor associated with another platform comprising the first subset of the plurality of RF processing circuits which provides other data to the control circuit which the control circuit employs to compensate for temperature variations within each Quiet BFN and Active BFN of each RF processing circuit of the plurality of RF processing circuits.

5. The method according to claim 4, wherein upon providing the pressure sensor the control circuit is configured to acquire barometric data from one or more external sources of environmental data associated with a location of the platform.

6. The method according to claim 1, further comprising providing a second subset of the plurality of RF processing circuits where each RF processing circuit of the second subset of the plurality of RF processing circuits is coupled to a predetermined antenna of the plurality of antennas and processes RF signals within a second frequency range; and providing another RF detector coupled via a further other combiner to each Active BFN of the second subset of the plurality of RF processing circuits via the second outputs of each RF processing circuit of the second subset of the plurality of RF processing circuits; wherein the RF output port is coupled via a further combiner to each Quiet BFN of the second subset of the plurality of RF processing circuits via the first outputs of each RF processing circuit of the second subset of the plurality of RF processing circuits; and the sequence executed by the controller further comprises: executing another anti -jamming algorithm by establishing a sweep of another null in another radiation pattern of the plurality of antennas in at least one of azimuth and elevation for the RF signals coupled through the Active BFNs of the second subset of the plurality of RF processing circuits; determining in dependence upon the output of the another RF detector as the another null of the radiation pattern of the plurality of antennas in at least one of azimuth and elevation is swept a location of another jamming signal; configuring each Quiet BFN of the second subset of the plurality of RF processing circuits to establish the another null in the radiation pattern of the plurality of antennas for the RF signals coupled through the Quiet BFNs of the second subset of the plurality of RF processing circuits to reduce the influence of the another jamming signal on the RF signals coupled to the RF output port.

7. The method according to claim 6, wherein the control circuit continuously executes the anti -jamming algorithm but only periodically reconfigures each Quiet BFN of the second subset of the plurality of RF processing circuits to establish the another null in the radiation pattern of the plurality of antennas.

8. The method according to claim 1, wherein each Quiet BFN of each processing circuit of the second subset of the plurality of RF processing circuits and each Active BFN of each processing circuit of the second subset of the plurality of RF processing circuits comprises a filtering module; wherein the filtering module is disposed before other elements of a Quiet BFN or Active BFN the filtering module forms part of and comprises: a band splitter for splitting received signals within the first frequency range into N frequency bands;N filter circuits (FCs) where each FC is coupled to an output of the band splitter for processing received signals within a frequency band of the N frequency bands; and a band splitter for combining the outputs and coupling them to the other elements of a Quiet BFN or Active BFN the filtering module forms part of; each FC comprises a tap for coupling a portion of the signals within the frequency band of the N frequency bands being processed to a detector and a gate such that upon a determination that a signal power measured by the detector exceeds a predetermined threshold the gate is controlled to block the signals within the FC; the gate is controlled by the control circuit or another control circuit; andN is an integer greater than or equal to 2.

9. The method according to claim 1 , wherein the first subset of a plurality of RF processing circuits and the plurality of antenna form part of a system; and the predetermined threshold is established in dependence upon at least one of: a global navigation satellite system (GNSS) receiver the system is intended to operate in conjunction with; a location of the system; and one or more GNSS satellite systems currently having line of sight to the system.

10. The method according to claim 1, wherein each Quiet BFN of each processing circuit of the second subset of the plurality of RF processing circuits and each Active BFN of each processing circuit of the second subset of the plurality of RF processing circuits comprises a filtering module; whereinthe filtering module is disposed before other elements of a Quiet BFN or Active BFN the filtering module forms part of and comprises: a band splitter for splitting received signals within the first frequency range into N frequency bands;N filter circuits (FCs) where each FC is coupled to an output of the band splitter for processing received signals within a frequency band of the N frequency bands; and a band splitter for combining the outputs and coupling them to the other elements of a Quiet BFN or Active BFN the filtering module forms part of; each FC comprises a gate such that upon a determination that a signal power measured by a controller exceeds a predetermined threshold the gate is controlled to block the signals within the FC; the controller is one of the control circuit or another control circuit which receives data from a spectrum analyzer which scans the first frequency range; andN is an integer greater than or equal to 2.

11. A system comprising: a first subset of a plurality of RF processing circuits where each RF processing circuit of the first subset of the plurality of RF processing circuits is coupled to a predetermined antenna of a plurality of antennas and processes RF signals within a first frequency range where; each RF processing circuit of the plurality of RF processing circuits comprises an input coupled to predetermined antenna of the plurality of antennas, a first beam forming network (Quiet BFN) comprising a first attenuator and a first phase shifter coupled to the input, a second beam forming network (Active BFN) comprising a second attenuator and a second phase shifter coupled to the input, a first output coupled to the output of the Quiet BFN, and a second output coupled to each Active BFN; an RF output port coupled via a combiner to each Quiet BFN of the first subset of the plurality of RF processing circuits via the first outputs of each RF processing circuit of the first subset of the plurality of RF processing circuits; an RF detector coupled via another combiner to each Active BFN of the first subset of the plurality of RF processing circuits via the second outputs of each RF processing circuit of the first subset of the plurality of RF processing circuits; anda control circuit coupled to the RF detector, each first attenuator and first phase shifter of each Quiet BFN and to each second attenuator and a second phase shifter of each Active BFN; wherein the control circuit executes a sequence comprising: executing an anti -jamming algorithm by establishing a sweep of a null in a radiation pattern of the plurality of antennas in at least one of azimuth and elevation for the RF signals coupled through the Active BFNs of the first subset of the plurality of RF processing circuits; determining in dependence upon the output of the RF detector as the null of the radiation pattern of the plurality of antennas in at least one of azimuth and elevation is swept a location of a jamming signal; and configuring each Quiet BFN of the first subset of the plurality of RF processing circuits to establish the null in the radiation pattern of the plurality of antennas for the RF signals coupled through the Quiet BFNs of the first subset of the plurality of RF processing circuits to reduce the influence of the jamming signal on the RF signals coupled to the RF output port.

12. A system comprising: a control circuit coupled to an RF detector, each first beam forming network (Quiet BFN) comprising a first attenuator and a first phase shifter and second beam forming network (Active BFN) comprising a second attenuator and a second phase shifter of a processing circuit of a plurality of RF processing circuits; wherein the control circuit executes a sequence comprising: executing an anti -jamming algorithm by establishing a sweep of a null in a radiation pattern of a plurality of antennas in at least one of azimuth and elevation for RF signals coupled through the Active BFNs of a first subset of the plurality of RF processing circuits; determining in dependence upon the output of the RF detector as the null of the radiation pattern of the plurality of antennas in at least one of azimuth and elevation is swept a location of a jamming signal; and configuring each Quiet BFN of the first subset of the plurality of RF processing circuits to establish the null in the radiation pattern of the plurality of antennas for the RF signals coupled through the Quiet BFNs of the first subset of the pluralityof RF processing circuits to reduce the influence of the jamming signal on the RF signals coupled to the RF output port.

13. The system according to claim 12, wherein each RF processing circuit of the first subset of the plurality of RF processing circuits is coupled to a predetermined antenna of a plurality of antennas and processes RF signals within a first frequency range where; each RF processing circuit of the plurality of RF processing circuits comprises an input coupled to predetermined antenna of the plurality of antennas, the Quiet BFN coupled to the input, the Active BFN, a first output coupled to the output of the Quiet BFN, and a second output coupled to each Active BFN; an RF output port coupled via a combiner to each Quiet BFN of the first subset of the plurality of RF processing circuits via the first outputs of each RF processing circuit of the first subset of the plurality of RF processing circuits; and the RF detector is coupled via another combiner to each Active BFN of the first subset of the plurality of RF processing circuits via the second outputs of each RF processing circuit of the first subset of the plurality of RF processing circuits.

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