Display panel and display device

Abstract

The present application provides a display panel and a display device. In the display panel, a light-shielding layer comprises a first light-shielding portion, a first gate layer comprises a first gate electrode of a compensation transistor, the first gate electrode of the compensation transistor is arranged corresponding to an active pattern of the compensation transistor, and the first light-shielding portion is arranged corresponding to an active pattern of a first initialization transistor, thereby ensuring both the yield of display panels and the electrical properties of oxide thin-film transistors.

Description

Display panel and display device

[0001] This application claims priority to Chinese patent application No. 202411222914.2, filed on September 2, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of display technology, and in particular to a display panel and display device. Background Technology

[0003] With the development of display devices, the requirements for power consumption and screen-to-body ratio are becoming increasingly stringent. To reduce power consumption and increase screen-to-body ratio, existing display devices employ Low Temperature Polysilicon Oxide (LTPO) technology. LTPO technology refers to the simultaneous use of low temperature polysilicon thin-film transistors (LTPS) and oxide thin-film transistors (OTCs), allowing the driving circuit to combine the advantages of both LTPS and OTC transistors, thereby reducing power consumption and leakage current. However, existing display devices using LTPO technology have a large number of film layers, requiring a correspondingly large number of photomasks, resulting in a more complex process and higher cost. To reduce the number of photomasks, existing display devices remove some gate layers and insulating layers, but this leads to the absence of the bottom gate of the OTC transistor, degrading the photosensitivity and electrical performance of the thin-film transistor. To improve the electrical performance of the OTC transistor, existing technologies use some film layers to form the bottom gate of the OTC transistor, but these methods also have some problems. For example, some film layers are too far away from the active layer of the OTC transistor, resulting in a weak bottom gate effect; some film layers are too close to the active layer of the OTC transistor, but the limited space of these film layers can easily lead to short-circuit failure.

[0004] Therefore, existing display devices using LTPO technology have a technical problem that cannot balance yield and electrical properties of oxide thin-film transistors. Invention Overview

[0005] This application provides a display panel and a display device to solve the technical problem that existing display devices using LTPO technology cannot simultaneously achieve high yield and good electrical properties of oxide thin-film transistors.

[0006] In a first aspect, embodiments of this application provide a display panel, the display panel including a substrate and a driving circuit layer disposed on one side of the substrate, the driving circuit layer including a pixel driving circuit, the pixel driving circuit including a switching transistor, a driving transistor, a compensation transistor and a first initialization transistor, the switching transistor being connected to the driving transistor at a first node; one electrode of the compensation transistor and one electrode of the first initialization transistor being connected to the driving transistor at a second node, the other electrode of the compensation transistor being connected to the driving transistor at a third node; wherein, the driving circuit layer includes:

[0007] A light-shielding layer, the light-shielding layer including a first light-shielding portion;

[0008] The first active layer is disposed on the side of the light-shielding layer away from the substrate;

[0009] A first gate layer is disposed on the side of the first active layer away from the substrate, and the first gate layer includes the first gate of the compensation transistor;

[0010] The second active layer is disposed on the side of the first gate layer away from the substrate, and the second active layer includes the active pattern of the compensation transistor and the active pattern of the first initialization transistor.

[0011] The first gate of the compensation transistor is configured to correspond to the active pattern of the compensation transistor, and the first light-shielding portion is configured to correspond to the active pattern of the first initialization transistor.

[0012] Secondly, embodiments of this application provide a display device, which includes a display panel as described in any of the above embodiments. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 is a schematic diagram of the first type of contrast display device provided in the embodiments of this application.

[0015] Figure 2 is a schematic diagram of a second type of contrast display device provided in an embodiment of this application.

[0016] Figure 3 is a schematic diagram of a third type of comparison display device provided in an embodiment of this application.

[0017] Figure 4 is a schematic diagram of the film layer of the display panel provided in the embodiment of this application.

[0018] Figure 5 is a circuit diagram of the pixel driving circuit of the display panel provided in an embodiment of this application.

[0019] Figure 6 is a stacked diagram of the various film layers of the display panel provided in the embodiment of this application.

[0020] Figure 7 is an exploded view of the light-shielding layer of the display panel in Figure 6.

[0021] Figure 8 is an exploded view of the first active layer of the display panel in Figure 6.

[0022] Figure 9 is an exploded view of the first gate layer of the display panel in Figure 6.

[0023] Figure 10 is an exploded view of the second active layer of the display panel in Figure 6.

[0024] Figure 11 is an exploded view of the second gate layer of the display panel in Figure 6.

[0025] Figure 12 is an exploded view of the first source-drain layer of the display panel in Figure 6.

[0026] Figure 13 is an exploded view of the second source-drain layer of the display panel in Figure 6.

[0027] Figure 14 is an exploded view of the first via of the display panel in Figure 6.

[0028] Figure 15 is an exploded view of the second via of the display panel in Figure 6.

[0029] Figure 16 is an exploded view of the third via of the display panel in Figure 6.

[0030] Figure 17 is an exploded view of the fourth via of the display panel in Figure 6. Embodiments of the present invention

[0031] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0032] In the description of this application, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0033] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0034] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0035] The following disclosure provides many different embodiments or examples for implementing different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0036] Figure 1 is a schematic diagram of a first type of contrast display device provided in an embodiment of this application. Figure 2 is a schematic diagram of a second type of contrast display device provided in an embodiment of this application. Figure 3 is a schematic diagram of a third type of contrast display device provided in an embodiment of this application.

[0037] As shown in Figures 1 to 3, some contrast display devices are provided as an introduction to the embodiments of this application to illustrate the principle of the technical problem to be solved by the embodiments of this application. As shown in Figure 1, a contrast display device using LTPO technology includes a substrate 101, a light-shielding film 102, a blocking film 103, a buffer film 104, a low-temperature polycrystalline silicon film 105, a first gate insulating film 106, a first gate film 107, a second gate insulating film 108, a second gate film 109, a first interlayer insulating film 111, an oxide semiconductor film 112, a third gate insulating film 113, a third gate film 114, a second interlayer insulating film 115, a first source-drain film 116, a first planarization film 117, a second source-drain film 118, a second planarization film 119, a third source-drain film 121, a third planarization film 122, an anode film 123, a pixel definition film 124, and a support film 125. As can be seen from Figure 1, the contrast display device includes three layers of source and drain films and three layers of gate films, which means that the contrast display device needs to be formed using 16 photomasks, making the process more complex and costly.

[0038] To address the issue of complex manufacturing processes in contrast display devices, another type of contrast display device removes one of the gate film and insulating film layers, as shown in Figure 2. It can be seen that the second gate film 109 and the second gate insulating film 108 are removed in the contrast display device, which can reduce the number of photomasks to 14. However, the problem of a large number of photomasks, complex manufacturing processes, and high costs still exists.

[0039] To further address the complex manufacturing process of contrast display devices, another type of contrast display device removes an additional source / drain film and insulating film, as shown in Figure 3. By removing the third source / drain film 121 and the third planarization film 122, the number of photomasks can be reduced to 13. However, as can be seen from Figures 2 and 3, the oxide semiconductor film 112 is unshielded, resulting in the absence of the bottom gate of the oxide thin-film transistor, which degrades the photosensitivity and electrical properties of the thin-film transistor.

[0040] To address the issue of missing bottom gates in oxide thin-film transistors (OTTs) in some display devices, as shown in Figure 3, some comparative display devices use a light-shielding film to form the bottom gate of the OTTs. This bottom gate transmits signals from the high-potential power supply terminal or the scan lines connected to the OTTs. However, due to the large distance between the light-shielding film and the oxide semiconductor film, the bottom gate effect of the OTTs is weak, resulting in poor electrical performance. In other comparative display devices, a first gate film is used to form the bottom gate of the OTTs. However, in these devices, both the scan lines and gate drive circuit signal lines are formed using the first gate film, resulting in a large number of traces. Adding a bottom gate for the OTTs in this case is difficult. Since the bottom gate of the compensation transistor needs to be connected to the output of the gate drive circuit, this trace is prone to short-circuiting with other signal lines in the first gate film, leading to display failure. Therefore, existing display devices using LTPO technology suffer from a technical problem of not being able to simultaneously achieve high yield and good electrical performance of the OTTs.

[0041] This application provides a display panel and a display device to address the aforementioned technical problems.

[0042] Figure 4 is a schematic diagram of the film layers of the display panel provided in an embodiment of this application. Figure 5 is a circuit diagram of the pixel driving circuit of the display panel provided in an embodiment of this application. Figure 6 is a stack-up diagram of the film layers of the display panel provided in an embodiment of this application. Figure 7 is an exploded view of the light-shielding layer of the display panel in Figure 6. Figure 8 is an exploded view of the first active layer of the display panel in Figure 6. Figure 9 is an exploded view of the first gate layer of the display panel in Figure 6. Figure 10 is an exploded view of the second active layer of the display panel in Figure 6. Figure 11 is an exploded view of the second gate layer of the display panel in Figure 6. Figure 12 is an exploded view of the first source-drain layer of the display panel in Figure 6. Figure 13 is an exploded view of the second source-drain layer of the display panel in Figure 6. Figure 14 is an exploded view of the first via of the display panel in Figure 6. Figure 15 is an exploded view of the second via of the display panel in Figure 6. Figure 16 is an exploded view of the third via of the display panel in Figure 6. Figure 17 is an exploded view of the fourth via of the display panel in Figure 6.

[0043] As shown in Figures 4 to 17, this application embodiment provides a display panel 2, which includes a substrate 201 and a driving circuit layer 22. The driving circuit layer 22 is disposed on one side of the substrate 201 and includes a light-shielding layer 202, a first active layer 205, a first gate layer 207 and a second active layer 209. The light-shielding layer 202 is disposed between the substrate 201 and the first active layer 205, and the first active layer 205 is disposed between the light-shielding layer 202 and the first gate layer 207. The driving circuit layer 22 also includes a pixel driving circuit 31.

[0044] The pixel driving circuit 31 includes a switching transistor T2, a driving transistor T1, a compensation transistor T3, and a first initialization transistor T4. The switching transistor T2 and the driving transistor T1 are connected to a first node A. One electrode of the compensation transistor T3, one electrode of the first initialization transistor T4, and the driving transistor T1 are connected to a second node Q. The other electrode of the compensation transistor T3 and the driving transistor T1 are connected to a third node B.

[0045] The second active layer 209 includes the active pattern T3A of the compensation transistor T3 and the active pattern T4A of the first initialization transistor T4. The light-shielding layer 202 includes a first light-shielding portion 202a. The first gate layer 207 includes a first gate T3Ga of the compensation transistor T3. The first gate T3Ga of the compensation transistor T3 is correspondingly disposed with respect to the active pattern T3A of the compensation transistor T3. The first light-shielding portion 202a is correspondingly disposed with respect to the active pattern of the first initialization transistor T4.

[0046] This application provides a display panel including a substrate and a driving circuit layer. The driving circuit layer includes a light-shielding layer, a first active layer, a first gate layer, and a second active layer. By making the light-shielding layer include a first light-shielding portion and the first gate layer include a first gate of a compensation transistor, such that the first gate of the compensation transistor corresponds to the active pattern of the compensation transistor, and the first light-shielding portion corresponds to the active pattern of the first initialization transistor, the bottom gate of the compensation transistor can be formed using the first gate layer, and the bottom gate of the first initialization transistor can be formed using the light-shielding layer. Since the distance between the first gate layer and the second active layer is small, the electrical performance of the compensation transistor is improved. Since the space of the light-shielding layer is large, there will be no short circuit problem when the bottom gate of the first initialization transistor is set in the light-shielding layer, thereby balancing the yield of the display panel and the electrical performance of the oxide thin film transistor.

[0047] Specifically, in the embodiments of this application, the correspondence between the light-shielding portion and the active pattern of the transistor means that the light-shielding portion is at least corresponding to the channel portion of the transistor. The projection of the light-shielding portion on the substrate overlaps with the projection of the channel portion of the transistor on the substrate. It is understood that the active pattern of each transistor includes a doped portion and a channel portion. The channel portion is susceptible to light, which can cause performance changes. Furthermore, the correspondence between the electrode and the channel portion can improve gate control capability. Therefore, the light-shielding portion can be corresponding to the channel portion of the transistor. Specifically, for example, the correspondence between the first light-shielding portion and the active pattern of the first initialization transistor means that the first light-shielding portion is at least corresponding to the channel portion of the first initialization transistor. Similarly, the correspondence between the first gate of the compensation transistor and the active pattern of the compensation transistor means that the first gate of the compensation transistor is at least corresponding to the channel portion of the compensation transistor.

[0048] Specifically, compared to the contrast display device which uses a light-shielding film to form the bottom gate of the compensation transistor and the bottom gate of the first initialization transistor, and allows the bottom gate of the compensation transistor and the bottom gate of the first initialization transistor to respectively input the corresponding scan signal or input a high-potential power supply signal line, there is a problem that the bottom gate is far apart and its effect is weak. Compared to the contrast display device which uses a first gate film to form the bottom gate of the compensation transistor and the bottom gate of the first initialization transistor, and allows the bottom gate of the compensation transistor and the bottom gate of the first initialization transistor to respectively input the corresponding scan signal, there is a problem that the space of the first gate film is small and difficult to implement, which can easily lead to short circuits. This application embodiment considers that the electrical properties of the compensation transistor have a significant impact on the display panel, specifically affecting characteristics such as image retention, flicker, lifespan, and optical properties. Since the function of the first initialization transistor is to reset the second node Q, the first gate layer forms the bottom gate of the compensation transistor, and the light-shielding layer forms the first light-shielding portion. The first light-shielding portion is positioned corresponding to the active pattern of the first initialization transistor. This approach balances the space constraints of the first gate layer and the light-shielding layer to avoid short circuits, and ensures better electrical properties of the compensation transistor, resulting in better overall display panel characteristics. This balances the yield of the display panel with the electrical properties of the oxide thin-film transistor. Furthermore, to further avoid short circuits caused by excessive traces within each film layer and improve the electrical properties of each trace and electrode, the positions of each trace, connection line, and via are further designed, as detailed in the following embodiment.

[0049] Specifically, as shown in Figure 4, the driving transistor T1 uses a portion of the light-shielding layer for light shielding, the compensation transistor T3 uses a portion of the first gate layer as the bottom gate of the compensation transistor, and the active pattern of the first initialization transistor T4 is set to correspond to a portion of the light-shielding layer.

[0050] Specifically, the light-shielding layer 202 is disposed on one side of the substrate 201, the first active layer 205 is disposed on the side of the light-shielding layer 202 away from the substrate 201, the first gate layer 207 is disposed on the side of the first active layer 205 away from the light-shielding layer 202, and the second active layer 209 is disposed on the side of the first gate layer 207 away from the first active layer 205.

[0051] In some embodiments, as shown in Figures 4 to 8, the driving circuit layer 22 includes a plurality of repeating units 30 arranged in an array. Each repeating unit 30 includes two pixel driving circuits 31 symmetrically arranged. Within each repeating unit 30, the light-shielding layer 202 further includes two second light-shielding portions 202b and a connecting portion 202c symmetrically arranged in corresponding areas of the two pixel driving circuits 31. The connecting portion 202c includes a first connecting portion 321 arranged along a first direction X, a second connecting portion 322 arranged along the first direction X, and a third connecting portion 323 arranged along a second direction Y. The first active layer 205 includes an active pattern T1A of a driving transistor T1, and the second light-shielding portion 202b is correspondingly disposed with respect to the active pattern T1A of the driving transistor T1. The first connecting portion 321 connects to the adjacent first light-shielding portion 202a, the second connecting portion 322 connects to the adjacent second light-shielding portion 202b, one end of the third connecting portion 323 is connected to the first light-shielding portion 202a, and the other end of the third connecting portion 323 is connected to the second light-shielding portion 202b. The angle between the first direction X and the second direction Y is greater than 0 and less than or equal to 90 degrees. By including a second light-shielding portion and a connecting portion in the light-shielding layer, and making the connecting portion include a first connecting portion, a second connecting portion and a third connecting portion, wherein the first connecting portion connects to an adjacent first light-shielding portion, the second connecting portion connects to an adjacent second light-shielding portion, one end of the third connecting portion is connected to the first light-shielding portion, and the other end of the third connecting portion is connected to the second light-shielding portion, the light-shielding layer can be gridded, improving the electrical properties of the light-shielding layer, and the first light-shielding portion can serve as the bottom gate of the first initialization transistor, improving the electrical properties of the first initialization transistor.

[0052] Specifically, it is understood that the display panel will include multiple repeating units arranged in an array, and the pixel driving circuit in each repeating unit can refer to the design of a repeating unit described in the embodiments of this application.

[0053] Specifically, it is understood that in a display panel, adjacent pixel units are symmetrically arranged to increase the aperture ratio. In this embodiment, the light-shielding parts are symmetrically arranged, and the light-shielding parts in each row and column are connected by setting a first connecting part, a second connecting part, and a third connecting part, thereby realizing a mesh structure of the light-shielding layer. This makes the voltage drop of each part of the light-shielding layer similar or even the same when a signal is input, thereby improving the uniformity of the signal and enhancing the display effect.

[0054] Specifically, it is understood that in order to illustrate the specific design of a certain film layer or structure, the various parts of this application will be named separately. However, it is understood that multiple parts of a certain film layer or structure will be formed simultaneously, and when they are connected together, they will transmit the same signal. They belong to multiple parts of the same structure and can actually use the same name. For example, as shown in FIG7, the first light-shielding part 202a, the second light-shielding part 202b, the first connecting part 321, the second connecting part 322, and the third connecting part 323 in the light-shielding layer 202 are actually multiple parts of the same structure. The light-shielding part and the connecting part located in two repeating units are also multiple parts of the same structure, and the various parts are interconnected. Without considering the voltage drop, the multiple parts of this structure transmit the same signal and can use the same name. For example, each part can be named as a part of the light-shielding part. Similarly, for other film layers and other structures, please refer to the above description, which will not be repeated in the following embodiments.

[0055] Specifically, the second light-shielding part can transmit signals from the high-potential power line, and the second light-shielding part can be connected to the high-potential power line.

[0056] Specifically, the first light-shielding part can serve as the bottom gate of the first initialization transistor.

[0057] Specifically, as shown in Figure 7, the second light-shielding part 202b in each repeating unit can be connected by the second connecting part 322, but the first light-shielding part 202a in each repeating unit may not be connected.

[0058] In some embodiments, the light-shielding layer 202 further includes a second light-shielding portion 202b. The first active layer 205 includes an active pattern T1A of a driving transistor T1. The second light-shielding portion 202b is correspondingly disposed to the active pattern T1A of the driving transistor T1, and the first light-shielding portion 202a and the second light-shielding portion 202b are spaced apart. By spaced apart, the first light-shielding portion can transmit the signal line of the scan line connected to the gate of the first initialization transistor, thereby improving the gate control capability of the first initialization transistor.

[0059] Specifically, when the first light-shielding part and the second light-shielding part are provided in the light-shielding layer, the first light-shielding part and the second light-shielding part can be arranged alternately. The first light-shielding part and the second light-shielding part transmit different signals. The first light-shielding part transmits the signal of the scan line connected to the gate of the first initialization transistor. The first light-shielding part serves as the bottom gate of the first initialization transistor to improve the electrical performance of the first initialization transistor. The second light-shielding part shields the active pattern of the driving transistor to prevent the active pattern of the driving transistor from being affected by light.

[0060] Specifically, the first light-shielding part can be connected to the third scanning signal line, and the second light-shielding part can transmit the signal of the high-potential power line and can be connected to the high-potential power line.

[0061] In some embodiments, the driving circuit layer 22 includes a plurality of pixel driving circuits 31 arranged in an array. A first light-shielding portion 202a is disposed along a first direction X in a corresponding area of ​​the pixel driving circuit 31, and a second light-shielding portion 202b is disposed along the first direction X in a corresponding area of ​​the pixel driving circuit 31. Along the first direction X, the first light-shielding portions 202a located in two adjacent pixel driving circuits 31 are connected, and the second light-shielding portions 202b located in two adjacent pixel driving circuits 31 are connected. The driving circuit layer 22 also includes a scan signal line (e.g., a first scan signal line Pscan), and the first direction X is the same as the setting direction of the scan signal line. By arranging the first light-shielding portion along the first direction and connecting the first light-shielding portions in two adjacent pixel driving circuits, and arranging the second light-shielding portion along the first direction and connecting the second light-shielding portions in two adjacent pixel driving circuits, rows of first light-shielding portions and rows of second light-shielding portions can be connected. This reduces the number of connections between the first light-shielding portion and the signal terminal, reduces the number of connections between the second light-shielding portion and the signal terminal, reduces vias in the display panel, and improves the stability of the display panel.

[0062] Specifically, the above embodiments are illustrated using the connection of light-shielding parts in different pixel driving circuits as an example. However, the embodiments of this application are not limited to this. The light-shielding parts in the corresponding areas of different pixel driving circuits can be set independently and are not connected.

[0063] In some embodiments, as shown in FIG5, the gate of the switching transistor T2 is connected to the first scan signal line Pscan, the first electrode of the switching transistor T2 is connected to the data line DATA, and the second electrode of the switching transistor T2 is connected to the first electrode of the driving transistor T1 at the first node A; the gate of the compensation transistor T3 is connected to the second scan signal line Nscan1, the first electrode of the compensation transistor T3 is connected to the gate of the driving transistor T1 at the second node Q, and the second electrode of the compensation transistor T3 is connected to the second electrode of the driving transistor T1; the gate of the first initialization transistor T4 is connected to the third scan signal line Nscan2, the first electrode of the first initialization transistor T4 is connected to the first initialization signal line VI-G, and the second electrode of the first initialization transistor T4 is connected to the gate of the driving transistor T1 at the second node Q; the pixel driving circuit 31 further includes:

[0064] The first light-emitting control transistor T5 has its gate connected to the light-emitting control signal line EM, its first electrode connected to the high-potential power supply line VDD, and its second electrode connected to the first electrode of the driving transistor T1 at the first node A.

[0065] The second light-emitting control transistor T6 has its gate connected to the light-emitting control signal line EM, and its first electrode is connected to the second electrode of the driving transistor T1 at the third node B.

[0066] The second initialization transistor T7 has its gate connected to the fourth scan signal line Pscan2, its first electrode connected to the second initialization signal line VI-ANO, and its second electrode connected to the second electrode of the second light-emitting control transistor T6 at the fourth node C.

[0067] The third initialization transistor T8 has its gate connected to the fourth scan signal line Pscan2, its first electrode connected to the third initialization signal line VI3, and its second electrode connected to the first electrode of the driving transistor T1 at the first node A.

[0068] A storage capacitor Cst, one plate of which is connected to the high-potential power line VDD, and the other plate of which is connected to the gate of the driving transistor T1 at the second node Q;

[0069] A boost capacitor Cboost, one plate of which is connected to the first scan signal line, and the other plate of which is connected to the second electrode of the first initialization transistor.

[0070] Specifically, as shown in Figures 4 and 5, the display panel 2 also includes a light-emitting layer 23, which includes a light-emitting device LED. The light-emitting device LED is connected to the pixel driving circuit. The positive electrode of the light-emitting device LED is connected to the second electrode of the second initialization transistor T7, and the negative electrode of the light-emitting device LED is connected to the low-potential power line VSS.

[0071] In some embodiments, as shown in FIG4, the driving circuit layer 22 further includes a second gate layer 212, a first source-drain layer 214, and a second source-drain layer 216. The second active layer 209 is disposed between the first gate layer 207 and the second gate layer 212, the second gate layer 212 is disposed between the second active layer 209 and the first source-drain layer 214, and the first source-drain layer 214 is disposed between the second gate layer 212 and the second source-drain layer 216. By including the first gate layer, the second gate layer, the first source-drain layer, and the second source-drain layer in the driving circuit layer, the number of process steps in the display panel can be reduced, and the number of photomasks required to form the display panel can be reduced.

[0072] In some embodiments, as shown in Figures 4, 6, and 8, the first active layer 205 includes an active pattern T1A of a driving transistor T1, an active pattern T2A of a switching transistor T2, an active pattern T5A of a first light-emitting control transistor T5, an active pattern T6A of a second light-emitting control transistor T6, an active pattern T7A of a second initialization transistor T7, and an active pattern T8A of a third initialization transistor T8. The active pattern T1A of the driving transistor T1 is disposed along a first direction X, and the active pattern T1A of the driving transistor T1 is connected to the active pattern T2A of the switching transistor T2, the active pattern T5A of the first light-emitting control transistor T5, and the active pattern T6A of the second light-emitting control transistor T6. The active pattern T2A of the switching transistor T2 is connected to the active pattern T6A of the first light-emitting control transistor T7. The active pattern T5A of the body transistor T5 is arranged along the second direction Y. The active pattern T6A of the second light-emitting control transistor T6 and the active pattern T7A of the second initialization transistor T7 are arranged along the second direction Y, and the active pattern T6A of the second light-emitting control transistor T6 and the active pattern T7A of the second initialization transistor T7 are connected. The active pattern T8A of the third initialization transistor T8 is spaced apart from the active pattern T1A of the driving transistor T1, the active pattern T2A of the switching transistor T2, the active pattern T5A of the first light-emitting control transistor T5, the active pattern T6A of the second light-emitting control transistor T6, and the active pattern T7A of the second initialization transistor T7. The angle between the first direction X and the second direction Y is greater than 0 and less than or equal to 90 degrees.

[0073] In some embodiments, as shown in Figures 4 to 6 and Figure 9, the first gate layer 207 includes a first scan signal line Pscan, a first electrode Cst1 of a storage capacitor Cst, a light emission control signal line EM, a fourth scan signal line Pscan2, a first initialization connection line L1, a gate T1G of a driving transistor T1, a gate T2G of a switching transistor T2, a gate T5G of a first light emission control transistor T5, a gate T6G of a second light emission control transistor T6, a gate T7G of a second initialization transistor T7, and a gate T8G of a third initialization transistor T8. The first scan signal line Pscan, the first gate T3Ga of the compensation transistor T3, the first electrode Cst1 of the storage capacitor Cst, the light emission control signal line EM, the fourth scan signal line Pscan2, and the first initialization connection line L1 are sequentially spaced along the second direction Y. By setting the first gate of the compensation transistor in the first gate layer, and placing the first gate of the compensation transistor between the first electrode of the storage capacitor and the first scan signal line, the distance between the first gate of the compensation transistor and other electrodes is larger, avoiding short circuits between the compensation transistor and other electrodes, and improving the yield of the display panel.

[0074] Specifically, as shown in Figure 9, the gate T2G of the switching transistor T2 is part of the first scan signal line Pscan. It can be understood that since the gates T2G of all the switching transistors T2 in a row of pixel units are connected to the same first scan signal line Pscan, when forming the first scan signal line Pscan, the portion of the channel of the switching transistor T2 corresponding to each pixel unit serves as the gate of the switching transistor T2 in that pixel unit. Therefore, the same structure is identified by two labels. Similarly, the gate T1G of the driving transistor T1 serves as both the gate and the storage capacitor Cs. The first plate Cst1 of t has a light emission control signal line EM corresponding to the channel portion of the first light emission control transistor T5 as the gate T5G of the first light emission control transistor T5. The light emission control signal line EM corresponding to the channel portion of the second light emission control transistor T6 is used as the gate T6G of the second light emission control transistor T6. The fourth scan signal line Pscan2 corresponding to the channel portion of the second initialization transistor T7 is used as the gate T7G of the second initialization transistor T7. The fourth scan signal line Pscan2 corresponding to the channel portion of the third initialization transistor T8 is used as the gate T8G of the third initialization transistor T8.

[0075] In some embodiments, as shown in FIG10, the second active layer 209 further includes a second electrode Cst2 of a storage capacitor Cst. The active pattern T3A of the compensation transistor T3 is connected to the active pattern T4A of the first initialization transistor T4. The second electrode Cst2 of the storage capacitor Cst is disposed along a first direction X on one side of the active pattern T3A of the compensation transistor T3, and a through hole 331 is provided on the second electrode Cst2 of the storage capacitor Cst. By forming the second electrode of the storage capacitor in the second active layer, a storage capacitor can be disposed in the pixel driving circuit, and the through hole on the second electrode of the storage capacitor allows the first electrode of the compensation transistor to be normally connected to the gate of the driving transistor.

[0076] Specifically, it can be understood that the second active layer forms the second plate of the storage capacitor. Therefore, it is necessary to make the second plate of the storage capacitor have good electrical properties. This can be achieved by doping the second plate of the storage capacitor to keep the electrical properties of the second plate of the storage capacitor consistent with or even exceed the electrical properties of the doped part of the active pattern, so that the electrical properties of the storage capacitor are good.

[0077] Specifically, by providing a through hole on the second plate of the storage capacitor, the first electrode of the compensation transistor can pass through the second plate of the storage capacitor and connect to the gate of the driving transistor, thus enabling the pixel driving circuit to work normally.

[0078] Specifically, as shown in Figures 9 and 10, the first gate layer 207 further includes the first plate Cboost1 of the boost capacitor Cboost, and the second active layer 209 further includes the second plate Cboost2 of the boost capacitor Cboost. The overlapping portion of the first scan signal line Pscan and the active pattern T4A of the first initialization transistor T4 is the first plate Cboost1 of the boost capacitor Cboost, and the overlapping portion of the active pattern T4A of the first initialization transistor T4 and the first scan signal line Pscan is the second plate Cboost2 of the boost capacitor Cboost.

[0079] In some embodiments, as shown in Figures 4 to 6 and Figure 11, the second gate layer 212 includes a second scan signal line Nscan1, a third scan signal line Nscan2, a second initialization signal line VI-ANO, a second gate T3Gb of a compensation transistor T3, and a gate T4G of a first initialization transistor T4. The third scan signal line Nscan2, the second scan signal line Nscan1, and the second initialization signal line VI-ANO are sequentially arranged along the second direction Y.

[0080] Specifically, the projection of the first light-shielding part on the substrate can overlap with the projection of the third scan signal line on the substrate, thereby reducing the coupling capacitance between the first light-shielding part and other signal lines. Even if the first light-shielding part is coupled to the third scan signal line, since the first light-shielding part is correspondingly set with the active pattern of the first initialization transistor, the potential of the first light-shielding part can be the potential of the third scan signal line, which can improve the gate control capability of the first initialization transistor.

[0081] Specifically, the first light-shielding part can be regarded as the first gate of the first initialization transistor, and correspondingly, the gate of the first initialization transistor located in the second gate layer is the second gate of the first initialization transistor.

[0082] Specifically, the projection of the first gate of the compensation transistor on the substrate can overlap with the projection of the second scan signal line on the substrate, thereby reducing the coupling capacitance between the first gate of the compensation transistor and other signal lines. When the first gate of the compensation transistor is coupled to the second scan signal line, both transmit the drive signal of the gate of the compensation transistor, which can improve the gate control capability of the first initialization transistor.

[0083] In some embodiments, as shown in Figures 4 to 6 and Figure 12, the first source-drain layer 214 includes a first initialization signal line VI-G, a first electrode T4S of the switching transistor T2, a second electrode T2D of the switching transistor T2, a first electrode T3S of the compensation transistor T3, a second electrode T3D of the compensation transistor T3, a first electrode T4S of the first initialization transistor T4, a second electrode T4D of the first initialization transistor T4, a first electrode T5S of the first light-emitting control transistor T5, a second electrode T5D of the first light-emitting control transistor T5, a first electrode T6S of the second light-emitting control transistor T6, a second electrode T6D of the second light-emitting control transistor T6, and a second initialization signal line VI-G. The transistor T7 has a first electrode T7S, a second electrode T7D of the second initialization transistor T7, a first electrode T8S of the third initialization transistor T8, a second electrode T8D of the third initialization transistor T8, a first adapter line L2, a first data connection line L3, a second adapter line L4, and a third initialization signal line VI3. The first adapter line L2 is connected to the first gate T3Ga of the compensation transistor T3 and the second scan signal line Nscan1. The second adapter line L4 is connected to the second initialization signal line VI-ANO and the first electrode T7S of the second initialization transistor T7. The third initialization signal line VI3 is connected to the first initialization connection line L1.

[0084] Specifically, in this embodiment, a first gate of a compensation transistor is formed in a first gate layer, a second scan signal line is formed in a third gate layer, and a first adapter line is formed in a first source-drain layer. By using two short-distance holes, the first adapter line connects the second scan signal line and the first gate, thereby saving space. Furthermore, two sub-pixel units can share the same first adapter line and via, reducing the number of vias, saving space, and increasing pixel density.

[0085] Specifically, by forming a third initialization signal line in the first source-drain layer and connecting the third initialization signal line with the first initialization connection line, a line of third initialization signal lines is connected, eliminating the need for multiple input terminals for signal input.

[0086] Specifically, as shown in Figure 12, it can be understood that since the electrodes of each transistor are connected together, in actual design, to improve the aperture ratio, the electrodes of each transistor will share the same structure. Therefore, in Figure 12, the same structure is identified by multiple labels. For example, one structure serves as both the first electrode T3S of the compensation transistor T3 and the second electrode T4D of the first initialization transistor T4. As can be seen from Figure 5, this is the location where the second node Q is connected. Similarly, other structures will also serve as multiple electrodes, and the positions of each node can be determined accordingly.

[0087] Specifically, since some electrodes and / or signal lines are connected together, a structure may only be labeled with one electrode or one signal line. It is understood that the structure may also be other electrodes or signal lines connected to that electrode or signal line.

[0088] In some embodiments, as shown in Figures 4 to 6 and Figure 13, the driving circuit layer 22 includes a plurality of repeating units 30 arranged in an array. Each repeating unit 30 includes two pixel driving circuits 31 arranged symmetrically. Within the repeating unit 30, the second source-drain layer 216 includes two second data connection lines L5, two data lines DATA, two high-potential power lines VDD, and a second initialization connection line L6. The two second data connection lines L5 are arranged symmetrically and have breaks. The two data lines DATA are arranged symmetrically, and the two high-potential power lines VDD are arranged symmetrically. The second initialization connection line L6 is connected to the second initialization signal line VI-ANO.

[0089] Specifically, by setting a second initialization connection line in the second source-drain layer, and connecting the second initialization signal line to the second initialization connection line, the second initialization signal line can be meshed, thereby reducing the voltage drop of the second initialization signal line.

[0090] Specifically, it is understood that due to the design of some pixel driving circuits within the display area shown in the embodiments of this application, and the connection points of some traces may be located in other pixel driving circuits or outside the display area, some traces may not be connected together. However, in reality, they will be connected. For example, in order to adopt the technology of setting the fanout line in the display area (Fanout In AA, FIAA), the data line DATA will be provided with a first data connection line L3 set along the first direction and a second data connection line L5 set along the second direction, and will be connected to some data lines. However, the embodiments of this application show the design of some pixel driving circuits, so their connection points are not shown, but in reality, they will be connected.

[0091] Specifically, as shown in Figures 6, 10, 12, and 13, the first source-drain layer 214 further includes a first connection terminal K1 and a second connection terminal K2. The high-potential power line VDD is connected to the first connection terminal K1, the first connection terminal K1 is connected to the second connection terminal K2, and the second connection terminal K2 is connected to the second electrode Cst2 of the storage capacitor Cst and the first electrode T5S of the first light-emitting control transistor T5, thereby realizing the connection between the high-potential power line and the second electrode of the storage capacitor and the first electrode of the first light-emitting control transistor. Since the high-potential power line and the first electrode of the first light-emitting control transistor do not overlap, and due to the presence of other signal lines, the high-potential power line cannot be directly connected to the second electrode of the storage capacitor via a hole. This embodiment of the application provides a first connection terminal and a second connection terminal in the first source-drain layer, and connects the high-potential power line and the second electrode of the storage capacitor through the first connection terminal and the second connection terminal respectively, thus realizing the connection between the high-potential power line, the second electrode of the storage capacitor, and the first electrode of the first light-emitting control transistor.

[0092] Specifically, as shown in Figures 5 to 12, the first source-drain layer 214 also includes a third connection terminal K3. The first electrode T3S of the compensation transistor T3 is connected to the gate T1G of the driving transistor T1. Therefore, a third connection terminal K3 can be provided in the first source-drain layer. The third connection terminal K3 passes through the via 331 and is connected to the gate T1G of the driving transistor T1, thereby realizing the connection between the gate of the driving transistor T1 and the first electrode T3S of the compensation transistor T3.

[0093] Specifically, as shown in Figures 5 to 13, the second source-drain layer 216 also includes a fourth connection terminal K4, which connects the second electrode T6D of the second light-emitting control transistor T6 and the first electrode of the light-emitting device.

[0094] Specifically, since the active parts of some transistors are connected together, some nodes and electrodes are not shown in the circuit diagram. For example, the first node A is the connection node of the first electrode of the driving transistor T1, the second electrode of the switching transistor T2, and the second electrode of the first light-emitting control transistor T5. Since the active parts of the driving transistor T1, the switching transistor T2, and the first light-emitting control transistor T5 share the same structure, it is not necessary to separately set the first electrode of the driving transistor T1, the second electrode of the switching transistor T2, and the second electrode of the first light-emitting control transistor T5. Accordingly, the first node A does not exist in the exploded view of each film layer. It can be understood that the first node A is located at the connection point of the active parts of the driving transistor T1, the switching transistor T2, and the first light-emitting control transistor T5.

[0095] In some embodiments, as shown in FIG14, FIG14 illustrates the location of the first via 341, which refers to a via etched from the first source / drain layer to the first active layer or the first gate layer.

[0096] In some embodiments, as shown in FIG15, FIG15 illustrates the location of the second via 342, which refers to a via etched from the first source / drain layer to the second active layer or the second gate layer.

[0097] In some embodiments, as shown in FIG16, FIG16 illustrates the location of the third via 343, which refers to a via etched from the second source-drain layer to the first source-drain layer.

[0098] In some embodiments, as shown in FIG17, FIG17 illustrates the location of the fourth via 344, which refers to the via etched from the anode of the light-emitting layer to the second source-drain layer.

[0099] In some embodiments, the first light-shielding portion is connected to the third scan signal line. By connecting the first light-shielding portion to the third scan signal line, the first light-shielding portion can serve as the bottom gate of the first initialization transistor, thereby improving the electrical performance of the first initialization transistor.

[0100] Specifically, the first light-shielding part and the third scanning signal line can be connected by other connecting lines or by directly drilling holes.

[0101] Specifically, in the above embodiments, when the transistor has a bottom gate and a top gate, the gate of the transistor refers to the first gate and the second gate of the transistor.

[0102] Specifically, as shown in Figure 4, the driving circuit layer 22 also includes a barrier layer 203, a buffer layer 204, a first gate insulating layer 206, a first interlayer insulating layer 208, a second gate insulating layer 211, a second interlayer insulating layer 213, a first planarization layer 215, and a second planarization layer 217.

[0103] Specifically, as shown in Figure 4, the display panel 2 also includes a light-emitting layer 23, which includes a pixel electrode layer 218, a pixel definition layer 219, a light-emitting material layer, a common electrode layer, and a support pillar 221.

[0104] Specifically, in the above embodiments, the first electrode of the transistor is the source and the second electrode is the drain; or in the above embodiments, the first electrode of the transistor is the drain and the second electrode is the source.

[0105] Specifically, the first scan signal line Pscan, the second scan signal line Nscan1, the third scan signal line Nscan2, the fourth scan signal line Pscan2, and the light emission control signal line EM can be connected to different gate driving circuits. Specifically, five sets of gate driving circuits can be used to output signals to the first scan signal line Pscan, the second scan signal line Nscan1, the third scan signal line Nscan2, the fourth scan signal line Pscan2, and the light emission control signal line EM, respectively. Among them, the gate driving circuit connected to the first scan signal line Pscan can use double-sided driving, while the other gate driving circuits use single-sided driving.

[0106] Specifically, the material of the first active layer includes silicon semiconductor materials, specifically low-temperature polycrystalline silicon.

[0107] Specifically, the material of the second active layer includes oxide semiconductor materials, specifically metal oxide semiconductor materials, and more specifically, indium gallium zinc oxide.

[0108] Specifically, the material of the light-shielding layer can include metallic materials.

[0109] Specifically, the driving transistor, the switching transistor, the first light-emitting control transistor, the second light-emitting control transistor, the second initialization transistor, and the third initialization transistor are P-type transistors, while the first initialization transistor and the compensation transistor are N-type transistors.

[0110] Specifically, the above embodiments have provided a detailed description of the display panel from the perspectives of pixel driving circuit, film layer structure, specific structure of each layer, material, and potential. It is understood that when there is no conflict between the embodiments, the embodiments can be combined. For example, the light-shielding layer further includes a second light-shielding part, the first active layer includes an active pattern of a driving transistor, the second light-shielding part is correspondingly disposed with the active pattern of the driving transistor, and the first light-shielding part and the second light-shielding part are spaced apart. The first light-shielding part is connected to the third scanning signal line.

[0111] Meanwhile, this application provides a display device, which includes a display panel as described in any of the above embodiments.

[0112] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0113] The above provides a detailed description of a display panel and display device provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A display panel comprising a substrate and a driving circuit layer disposed on one side of the substrate, the driving circuit layer comprising a pixel driving circuit, the pixel driving circuit comprising a switching transistor, a driving transistor, a compensation transistor, and a first initialization transistor, the switching transistor being connected to the driving transistor at a first node; one electrode of the compensation transistor and one electrode of the first initialization transistor being connected to the driving transistor at a second node, and the other electrode of the compensation transistor being connected to the driving transistor at a third node; wherein, The driving circuit layer includes: A light-shielding layer, the light-shielding layer including a first light-shielding portion; The first active layer is disposed on the side of the light-shielding layer away from the substrate; A first gate layer is disposed on the side of the first active layer away from the substrate, and the first gate layer includes the first gate of the compensation transistor; A second active layer is disposed on the side of the first gate layer away from the substrate, and the second active layer includes the active pattern of the compensation transistor and the active pattern of the first initialization transistor. The first gate of the compensation transistor is configured to correspond to the active pattern of the compensation transistor, and the first light-shielding portion is configured to correspond to the active pattern of the first initialization transistor.

2. The display panel as claimed in claim 1, wherein, The driving circuit layer includes a plurality of repeating units arranged in an array. Each repeating unit includes two pixel driving circuits arranged symmetrically. Within the repeating unit, the light-shielding layer also includes two second light-shielding portions and a connecting portion arranged symmetrically in the corresponding areas of the two pixel driving circuits. The connecting portion includes a first connecting portion arranged along a first direction, a second connecting portion arranged along the first direction, and a third connecting portion arranged along a second direction. The first active layer includes an active pattern of a driving transistor. The second light-shielding portions are arranged corresponding to the active pattern of the driving transistor. The first connecting portion connects to an adjacent first light-shielding portion, and the second connecting portion connects to an adjacent second light-shielding portion. One end of the third connecting portion is connected to the first light-shielding portion, and the other end of the third connecting portion is connected to the second light-shielding portion. The angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees.

3. The display panel as claimed in claim 1, wherein, The light-shielding layer further includes a second light-shielding portion. The first active layer includes an active pattern of a driving transistor. The second light-shielding portion is disposed corresponding to the active pattern of the driving transistor, and the first light-shielding portion and the second light-shielding portion are disposed at a distance.

4. The display panel as claimed in claim 3, wherein, The driving circuit layer includes a plurality of pixel driving circuits arranged in an array. A first light-shielding part is disposed in the corresponding area of ​​the pixel driving circuit along a first direction, and a second light-shielding part is disposed in the corresponding area of ​​the pixel driving circuit along the first direction. In the first direction, the first light-shielding parts located in two adjacent pixel driving circuits are connected, and the second light-shielding parts located in two adjacent pixel driving circuits are connected. The driving circuit layer also includes a scan signal line, and the first direction is the same as the setting direction of the scan signal line.

5. The display panel as claimed in any one of claims 1 to 4, wherein, The gate of the switching transistor is connected to the first scan signal line, the first electrode of the switching transistor is connected to the data line, and the second electrode of the switching transistor is connected to the first electrode of the driving transistor at a first node; the gate of the compensation transistor is connected to the second scan signal line, the first electrode of the compensation transistor is connected to the gate of the driving transistor at a second node, and the second electrode of the compensation transistor is connected to the second electrode of the driving transistor; the gate of the first initialization transistor is connected to the third scan signal line, the first electrode of the first initialization transistor is connected to the first initialization signal line, and the second electrode of the first initialization transistor is connected to the gate of the driving transistor at a second node; The pixel driving circuit also includes: The first light-emitting control transistor has its gate connected to the light-emitting control signal line, its first electrode connected to the high-potential power supply line, and its second electrode connected to the first electrode of the driving transistor at the first node. The second light-emitting control transistor has its gate connected to the light-emitting control signal line, and its first electrode is connected to the second electrode of the driving transistor at the third node. The second initialization transistor has its gate connected to the fourth scan signal line, its first electrode connected to the second initialization signal line, and its second electrode connected to the second light-emitting control transistor at the fourth node. The third initialization transistor has its gate connected to the fourth scan signal line, its first electrode connected to the third initialization signal line, and its second electrode connected to the first electrode of the driving transistor at the first node. A storage capacitor, one plate of which is connected to the high-potential power line, and the other plate of which is connected to the gate of the driving transistor at a second node; A boost capacitor, one plate of which is connected to the first scan signal line, and the other plate of which is connected to the second electrode of the first initialization transistor.

6. The display panel as claimed in claim 5, wherein, The driving circuit layer further includes a second gate layer, a first source-drain layer, and a second source-drain layer. The second active layer is disposed between the first gate layer and the second gate layer. The second gate layer is disposed between the second active layer and the first source-drain layer. The first source-drain layer is disposed between the second gate layer and the second source-drain layer.

7. The display panel as claimed in claim 6, wherein, The first active layer includes the active pattern of the driving transistor, the active pattern of the switching transistor, the active pattern of the first light-emitting control transistor, the active pattern of the second light-emitting control transistor, the active pattern of the second initialization transistor, and the active pattern of the third initialization transistor. The active pattern of the driving transistor is disposed along a first direction and is connected to the active patterns of the switching transistor, the first light-emitting control transistor, and the second light-emitting control transistor. The active patterns of the switching transistor and the first light-emitting control transistor are disposed along a second direction. The active patterns of the second light-emitting control transistor and the second initialization transistor are disposed along the second direction and are connected to each other. The active pattern of the third initialization transistor is spaced apart from the active patterns of the driving transistor, the switching transistor, the first light-emitting control transistor, the second light-emitting control transistor, and the second initialization transistor. The angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees.

8. The display panel as claimed in claim 7, wherein, The first gate layer includes the first scan signal line, the first plate of the storage capacitor, the light emission control signal line, the fourth scan signal line, the first initialization connection line, the gate of the driving transistor, the gate of the switching transistor, the gate of the first light emission control transistor, the gate of the second light emission control transistor, the gate of the second initialization transistor, and the gate of the third initialization transistor; the first scan signal line, the first gate of the compensation transistor, the first plate of the storage capacitor, the light emission control signal line, the fourth scan signal line, and the first initialization connection line are arranged sequentially at intervals along a second direction.

9. The display panel as claimed in claim 8, wherein, The second active layer further includes the second electrode plate of the storage capacitor, the active pattern of the compensation transistor is connected to the active pattern of the first initialization transistor, the second electrode plate of the storage capacitor is disposed on one side of the active pattern of the compensation transistor along the first direction, and the second electrode plate of the storage capacitor is provided with a through hole.

10. The display panel as claimed in claim 9, wherein, The second gate layer includes the second scan signal line, the third scan signal line, the second initialization signal line, the second gate of the compensation transistor, and the gate of the first initialization transistor. The third scan signal line, the second scan signal line, and the second initialization signal line are arranged sequentially along the second direction.

11. The display panel as claimed in claim 10, wherein, The first source-drain layer includes the first initialization signal line, the first electrode of the switching transistor, the second electrode of the switching transistor, the first electrode of the compensation transistor, the second electrode of the compensation transistor, the first electrode of the first initialization transistor, the second electrode of the first initialization transistor, the first electrode of the first light-emitting control transistor, the second electrode of the first light-emitting control transistor, the first electrode of the second light-emitting control transistor, the second electrode of the second light-emitting control transistor, the first electrode of the second initialization transistor, the second electrode of the second initialization transistor, the first electrode of the third initialization transistor, the second electrode of the third initialization transistor, the first adapter line, the first data connection line, the second adapter line, and the third initialization signal line. The first adapter line is connected to the first gate of the compensation transistor and the second scan signal line, the second adapter line is connected to the second initialization signal line and the first electrode of the second initialization transistor, and the third initialization signal line is connected to the first initialization connection line.

12. The display panel as claimed in claim 11, wherein, The driving circuit layer includes multiple repeating units arranged in an array. Each repeating unit includes two pixel driving circuits arranged symmetrically. Within the repeating unit, the second source-drain layer includes two second data connection lines, two data lines, two high-potential power lines, and one second initialization connection line. The two second data connection lines are arranged symmetrically, and the second data connection lines are provided with breaks. The two data lines are arranged symmetrically, the two high-potential power lines are arranged symmetrically, and the second initialization connection line is connected to the second initialization signal line.

13. The display panel as claimed in claim 5, wherein, The first light-shielding part is connected to the third scanning signal line.

14. A display device comprising a display panel, the display panel including a substrate and a driving circuit layer disposed on one side of the substrate, the driving circuit layer including a pixel driving circuit, the pixel driving circuit including a switching transistor, a driving transistor, a compensation transistor, and a first initialization transistor, the switching transistor being connected to the driving transistor at a first node; one electrode of the compensation transistor and one electrode of the first initialization transistor being connected to the driving transistor at a second node, the other electrode of the compensation transistor being connected to the driving transistor at a third node; wherein, The driving circuit layer includes: A light-shielding layer, the light-shielding layer including a first light-shielding portion; The first active layer is disposed on the side of the light-shielding layer away from the substrate; A first gate layer is disposed on the side of the first active layer away from the substrate, and the first gate layer includes the first gate of the compensation transistor; A second active layer is disposed on the side of the first gate layer away from the substrate, and the second active layer includes the active pattern of the compensation transistor and the active pattern of the first initialization transistor. The first gate of the compensation transistor is configured to correspond to the active pattern of the compensation transistor, and the first light-shielding portion is configured to correspond to the active pattern of the first initialization transistor.

15. The display device as claimed in claim 14, wherein, The driving circuit layer includes a plurality of repeating units arranged in an array. Each repeating unit includes two pixel driving circuits arranged symmetrically. Within the repeating unit, the light-shielding layer also includes two second light-shielding portions and a connecting portion arranged symmetrically in the corresponding areas of the two pixel driving circuits. The connecting portion includes a first connecting portion arranged along a first direction, a second connecting portion arranged along the first direction, and a third connecting portion arranged along a second direction. The first active layer includes an active pattern of a driving transistor. The second light-shielding portions are arranged corresponding to the active pattern of the driving transistor. The first connecting portion connects to an adjacent first light-shielding portion, and the second connecting portion connects to an adjacent second light-shielding portion. One end of the third connecting portion is connected to the first light-shielding portion, and the other end of the third connecting portion is connected to the second light-shielding portion. The angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees.

16. The display device as claimed in claim 14, wherein, The light-shielding layer further includes a second light-shielding portion. The first active layer includes an active pattern of a driving transistor. The second light-shielding portion is disposed corresponding to the active pattern of the driving transistor, and the first light-shielding portion and the second light-shielding portion are disposed at a distance.

17. The display device as claimed in claim 16, wherein, The driving circuit layer includes a plurality of pixel driving circuits arranged in an array. A first light-shielding part is disposed in the corresponding area of ​​the pixel driving circuit along a first direction, and a second light-shielding part is disposed in the corresponding area of ​​the pixel driving circuit along the first direction. In the first direction, the first light-shielding parts located in two adjacent pixel driving circuits are connected, and the second light-shielding parts located in two adjacent pixel driving circuits are connected. The driving circuit layer also includes a scan signal line, and the first direction is the same as the setting direction of the scan signal line.

18. The display device according to any one of claims 14 to 17, wherein, The gate of the switching transistor is connected to the first scan signal line, the first electrode of the switching transistor is connected to the data line, and the second electrode of the switching transistor is connected to the first electrode of the driving transistor at a first node; the gate of the compensation transistor is connected to the second scan signal line, the first electrode of the compensation transistor is connected to the gate of the driving transistor at a second node, and the second electrode of the compensation transistor is connected to the second electrode of the driving transistor; the gate of the first initialization transistor is connected to the third scan signal line, the first electrode of the first initialization transistor is connected to the first initialization signal line, and the second electrode of the first initialization transistor is connected to the gate of the driving transistor at a second node; The pixel driving circuit also includes: The first light-emitting control transistor has its gate connected to the light-emitting control signal line, its first electrode connected to the high-potential power supply line, and its second electrode connected to the first electrode of the driving transistor at the first node. The second light-emitting control transistor has its gate connected to the light-emitting control signal line, and its first electrode is connected to the second electrode of the driving transistor at the third node. The second initialization transistor has its gate connected to the fourth scan signal line, its first electrode connected to the second initialization signal line, and its second electrode connected to the second light-emitting control transistor at the fourth node. The third initialization transistor has its gate connected to the fourth scan signal line, its first electrode connected to the third initialization signal line, and its second electrode connected to the first electrode of the driving transistor at the first node. A storage capacitor, one plate of which is connected to the high-potential power line, and the other plate of which is connected to the gate of the driving transistor at a second node; A boost capacitor, one plate of which is connected to the first scan signal line, and the other plate of which is connected to the second electrode of the first initialization transistor.

19. The display device as claimed in claim 18, wherein, The driving circuit layer further includes a second gate layer, a first source-drain layer, and a second source-drain layer. The second active layer is disposed between the first gate layer and the second gate layer. The second gate layer is disposed between the second active layer and the first source-drain layer. The first source-drain layer is disposed between the second gate layer and the second source-drain layer.

20. The display device as claimed in claim 19, wherein, The first active layer includes the active pattern of the driving transistor, the active pattern of the switching transistor, the active pattern of the first light-emitting control transistor, the active pattern of the second light-emitting control transistor, the active pattern of the second initialization transistor, and the active pattern of the third initialization transistor. The active pattern of the driving transistor is disposed along a first direction and is connected to the active patterns of the switching transistor, the first light-emitting control transistor, and the second light-emitting control transistor. The active patterns of the switching transistor and the first light-emitting control transistor are disposed along a second direction. The active patterns of the second light-emitting control transistor and the second initialization transistor are disposed along the second direction and are connected to each other. The active pattern of the third initialization transistor is spaced apart from the active patterns of the driving transistor, the switching transistor, the first light-emitting control transistor, the second light-emitting control transistor, and the second initialization transistor. The angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees.

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