Display system and method for time division multiplexing of control signal

Abstract

The present disclosure relates to a display system and method for time division multiplexing of a control signal. The display system comprises: a main controller, configured to generate clock signals, store initial data, and generate tagged pixel data; pixel display chips all connected to the main controller, and configured to generate pixel driving signals on the basis of the clock signals and the tagged pixel data; and pixel units connected to the pixel display chips, and configured to, on the basis of the pixel driving signals, light up the pixel units corresponding to the pixel driving signals. In the present disclosure, time division multiplexing of pins is used between the main controller and the pixel display chips, so that the number of pins used in the main controller can be greatly reduced, and one main controller can drive a larger number of pixel display chips, or a more economical main controller with a small number of pins is selected, so that the effects that each pixel unit can be driven to be lit up multiple times, the light-up time is long and the refresh rate is high can be achieved with lower economic costs.

Description

Display system and method for time-division multiplexing of control signals

[0001] Related applications

[0002] This disclosure claims priority to Chinese patent application filed on August 27, 2024, application number 2024111780369, entitled "Display System and Method for Time-Division Multiplexing of Control Signals", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of display technology, and in particular to a display system and method for time-division multiplexing control signals. Background Technology

[0004] Large-screen display technology is becoming increasingly widespread in modern applications, especially in large-scale indoor and outdoor advertising, exhibitions, and sporting events. Generally, a large-screen display consists of multiple interconnected display modules, which are mounted to a steel structure via connectors to form the entire display system. Large-screen display technology also includes the driving communication between display modules, signal transmission, and display content management. Driving communication between display modules is fundamental to the normal operation of the display system, ensuring synchronization and consistency among the modules. Simultaneously, the stability and speed of signal transmission are also crucial factors in guaranteeing display quality, requiring appropriate signal transmission methods and technologies.

[0005] In related technologies, the system controls the brightness of each pixel row by row and column by column. After a rapid scan, the state of all pixels will present a complete image.

[0006] However, the aforementioned technologies, lacking a storage structure, only allow each pixel to light up once per frame, resulting in drawbacks such as short duration and low refresh rate. In contrast, large display screens with independent chip control for each pixel and built-in storage allow each pixel to light up multiple times, resulting in longer durations, higher refresh rates, and superior display quality compared to traditional large display screens. However, this approach places high demands on the number of pins on the main controller, leading to high requirements for main controller selection and higher overall system cost. Summary of the Invention

[0007] Based on this, it is necessary to address the aforementioned technical problems by providing a display system, method, apparatus, computer equipment, computer-readable storage medium, and computer program product that can significantly reduce the number of main controller pins by adding 1+j pins to the pixel display chip, enabling one main controller to drive a larger number of pixel display chips, or selecting a more economical main controller with fewer pins. This would allow for time-division multiplexing of control signals to achieve the same large-screen display resolution and refresh rate, as well as the same large-screen display clarity and color saturation, at a lower cost.

[0008] In a first aspect, this disclosure provides a display system for time-division multiplexing control signals, the display system comprising:

[0009] The main controller is used to generate clock signals, store initial data, and generate marker pixel data;

[0010] Pixel display chips, each connected to the main controller, are used to generate pixel drive signals based on the clock signal and the marked pixel data;

[0011] A pixel unit, which is connected to the pixel display chip, is used to light up the pixel unit corresponding to the pixel driving signal based on the pixel driving signal.

[0012] In one embodiment, the pixel display chip includes input pins and output pins, the main controller includes output pins, the input pins of the pixel display chip include clock signal pins and serial data pins, and the output pins of the main controller include clock signal pins and serial data pins;

[0013] The clock signal pin of the pixel display chip is connected to the clock signal pin of the main controller;

[0014] The serial data pin of the pixel display chip is connected to the serial data pin of the main controller;

[0015] The output pins of the pixel display chip are connected to the pixel unit.

[0016] In one embodiment, a first pin number mapping relationship is established between the main controller and the pixel display chip, and the first pin number mapping relationship is as follows:

[0017] When the pixel display chip has a*b units, the main controller provides a+b pins; where a is the number of rows and b is the number of columns.

[0018] In one embodiment, the input pins of the pixel display chip further include row chip select pins and column chip select pins, both of which are connected to the main controller. A second pin number mapping relationship is also established between the main controller and the pixel display chip, the second pin number mapping relationship being:

[0019] With an additional row chip select pin added to each of the pixel display chips, the main controller provides a / 2+b pins;

[0020] With the addition of j column select pins to each pixel display chip, the main controller provides (a / 2 + b / 2)j (Number of pins)

[0021] In one embodiment, each row of pixel display chips has two data transmission methods, which are as follows:

[0022] When the row select pin is connected to a power supply, the pixel display chip samples data when the clock signal is at its rising edge; when the row select pin is grounded, the pixel display chip samples data when the clock signal is at its falling edge; or

[0023] When the row chip select pin is connected to a power supply, the pixel display chip samples data when the clock signal is at a falling edge; when the row chip select pin is grounded, the pixel display chip samples data when the clock signal is at a rising edge.

[0024] In one embodiment, when the row chip select pin of a row of pixel display chips is connected to a power supply, the row chip select pin of the adjacent row of pixel display chips is grounded.

[0025] In one embodiment, when the column select pin of one column of the pixel display chips is connected to a power supply, the column select pin of the pixel display chips in adjacent columns is grounded.

[0026] In one embodiment, the pixel display chip data has two data transmission schemes, which are as follows:

[0027] When the column select pin is connected to a power supply, the pixel units connected to the pixel display chips in odd-numbered columns receive data; when the column select pin is grounded, the pixel units connected to the pixel display chips in even-numbered columns receive data; or

[0028] When the column select pin is connected to a power supply, the pixel unit connected to the even-numbered column pixel display chip receives data; when the column select pin is grounded, the pixel unit connected to the odd-numbered column pixel display chip receives data.

[0029] Secondly, this disclosure provides a display method for time-division multiplexing control signals, applicable to the display system for time-division multiplexing control signals described in any of the above embodiments. The display method includes:

[0030] Generate clock signals, store initial data, and generate marker pixel data;

[0031] A pixel driving signal is generated based on the clock signal and the marked pixel data;

[0032] The pixel unit corresponding to the pixel driving signal is lit based on the pixel driving signal.

[0033] In one embodiment, generating a pixel drive signal based on the clock signal and the marked pixel data includes:

[0034] The target row pixel unit is determined based on the clock signal;

[0035] The target column pixel unit is determined based on the marked pixel data;

[0036] Pixel driving signals are generated based on the target row pixel units and the target column pixel units.

[0037] Thirdly, this disclosure also provides a display device for time-division multiplexing control signals, comprising:

[0038] The control module is used to generate clock signals, store initial data, and generate marker pixel data;

[0039] The signal generation module is used to generate a pixel driving signal based on the clock signal and the marker pixel data;

[0040] The display module is used to illuminate the pixel unit corresponding to the pixel driving signal based on the pixel driving signal.

[0041] Fourthly, this disclosure also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to perform the following steps:

[0042] Generate clock signals, store initial data, and generate marker pixel data;

[0043] A pixel driving signal is generated based on the clock signal and the marked pixel data;

[0044] The pixel unit corresponding to the pixel driving signal is lit based on the pixel driving signal.

[0045] Fifthly, this disclosure also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, performs the following steps:

[0046] Generate clock signals, store initial data, and generate marker pixel data;

[0047] A pixel driving signal is generated based on the clock signal and the marked pixel data;

[0048] The pixel unit corresponding to the pixel driving signal is lit based on the pixel driving signal.

[0049] Sixthly, this disclosure also provides a computer program product, including a computer program that, when executed by a processor, performs the following steps:

[0050] Generate clock signals, store initial data, and generate marker pixel data;

[0051] A pixel driving signal is generated based on the clock signal and the marked pixel data;

[0052] The pixel unit corresponding to the pixel driving signal is lit based on the pixel driving signal.

[0053] The aforementioned display system, method, apparatus, computer equipment, computer-readable storage medium, and computer program product that time-division multiplexes control signals connects a main controller to a pixel display chip. The main controller generates marked pixel data with tagged bits from the raw data stored within it. The pixel display chip then determines the target row pixel unit based on the received clock signal and receives the marked pixel data. Subsequently, it identifies the target column pixel unit by recognizing the tagged bits in the received marked pixel data, thereby enabling the target column pixel unit to receive data in a time-division manner. The pixel display chip drives the target row and column pixel units according to the marked pixel data, achieving the effect of one main controller driving multiple pixel display chips, and enabling multiple illumination times, long illumination durations, and high refresh rates for each pixel unit. Attached Figure Description

[0054] To more clearly illustrate the technical solutions in the embodiments or conventional technologies of this disclosure, the accompanying drawings used in the description of the embodiments or conventional technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on the disclosed drawings without creative effort.

[0055] Figure 1 is a structural block diagram of a display system that uses time-division multiplexing of control signals in one embodiment;

[0056] Figure 2 is a connection diagram of a display system that uses time-division multiplexing of control signals in one embodiment;

[0057] Figure 3 is a schematic diagram of the data structure of a display system that uses time-division multiplexing of control signals in one embodiment;

[0058] Figure 4 is a schematic diagram of the data structure of a display system that uses time-division multiplexing of control signals in another embodiment;

[0059] Figure 5 is a flowchart illustrating a display method for time-division multiplexing of control signals in one embodiment;

[0060] Figure 6 is a structural block diagram of a display device that uses time-division multiplexing of control signals in one embodiment;

[0061] Figure 7 is an internal structure diagram of a computer device in one embodiment.

[0062] Attached image description:

[0063] Data_clk: Clock signal; column_data: Serial data; col_data: Serial data; Row_sel: Row chip select; Column_sel: Column chip select; VDD: Power supply; GND: Ground; R: Drives red LED; G: Drives green LED; B: Drives blue LED. Detailed Implementation

[0064] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0065] In one embodiment, as shown in FIG1, a display system for time-division multiplexing control signals is provided. This display system includes a main controller 102, a pixel display chip 104, and pixel units 106. The main controller 102 is connected to the pixel display chip 104, and the pixel display chip 104 is connected to the pixel units 106. The main controller 102 stores original data and generates new data with marker bits, i.e., marker pixel data, as well as a clock signal. The pixel display chip (i.e., a single-pixel display chip) 104 receives the clock signal and receives the corresponding marker pixel data based on the clock signal. Then, the pixel display chip 104 determines the pixel unit 106 to be driven based on the marker in the marker pixel data and generates the corresponding pixel driving signal. The pixel unit 106, i.e., a single-pixel LED, receives the pixel driving signal transmitted by the pixel display chip and illuminates the corresponding single-pixel LED.

[0066] The main controller is connected to multiple pixel display chips arranged according to certain rules. The main controller can be an FPGA (Field Programmable Gate Array), an IC (Integrated Circuit), or other controllers. There is at least one main controller. The pixel display chips are provided with at least two types, and the number of types is even. The light-emitting material of the pixel unit can be, but is not limited to, liquid crystal, LED (Light Emitting Diode), OLED (Organic Light Emitting Diode), micro LED (Micro LED), and Q-LED (Quantum Dot LED).

[0067] In the aforementioned display system that uses time-division multiplexing of control signals, the main controller is connected to the pixel display chip. The main controller generates marked pixel data with tagged bits based on the raw data stored in it. Then, the pixel display chip determines the target row pixel unit and receives the marked pixel data based on the received clock signal. Subsequently, the target column pixel unit is determined by identifying the tagged bits of the received marked pixel data, thereby enabling the target column pixel unit to receive data in a time-division manner. The pixel display chip drives the target row pixel unit and the target column pixel unit according to the marked pixel data, realizing the effect of one main controller driving multiple pixel display chips, as well as driving each pixel unit to light up multiple times, with long lighting time and high refresh rate.

[0068] In an exemplary embodiment, as shown in FIG2, a connection diagram of a display system with time-division multiplexing of control signals is provided. The pixel display chip in this system includes input pins and output pins. The input pins of the pixel display chip include a clock signal pin (i.e., an input clock pin, as shown in Data_clk) and a serial data pin (as shown in column_data). The main controller in this system includes output pins, which also include a clock signal pin and a serial data pin.

[0069] The clock signal pin of the pixel display chip is connected to the clock signal pin of the master controller, the serial data pin of the pixel display chip is connected to the serial data pin of the master controller, and the output pin of the pixel display chip is connected to the pixel unit.

[0070] In an exemplary embodiment, a first pin number mapping relationship is established between the main controller and the pixel display chip. This first pin data mapping relationship is specifically as follows:

[0071] A main controller is connected to a*b pixel display chips. With each pixel display chip only providing a clock signal pin and a serial data pin, the main controller provides a+b pins.

[0072] Where a is the number of rows and b is the number of columns.

[0073] In an exemplary embodiment, the input pins of the pixel display chip further include row chip select pins and column chip select pins, both of which can be connected to the main controller. Therefore, a second pin number mapping relationship is established between the main controller and the pixel display chip. This second pin number mapping relationship is specifically as follows:

[0074] With an additional row chip select pin added to each pixel display chip, the main controller provides a / 2+b pins;

[0075] With the addition of j column select pins to each pixel display chip, the main controller provides (a / 2 + b / 2) j (Number of pins)

[0076] The row select pin determines whether the pixel display chip receives the marker pixel data output by the main controller on the rising or falling edge of the clock signal, and determines whether odd-numbered or even-numbered row pixel units in the display unit are lit. The column select pin determines whether odd-numbered or even-numbered column pixel units in the display unit are lit. Furthermore, the j column select pins are time-division multiplexed to control 2... j A column pixel unit with a periodicity.

[0077] Based on the functions of row and column chip selection, pixel display chips can be divided into four basic types, as follows:

[0078] The rising edge of the clock signal receives data in odd-numbered rows and columns.

[0079] Even-numbered rows and odd-numbered columns of data are received on the falling edge of the clock signal.

[0080] The rising edge of the clock signal receives data in odd-numbered rows and even-numbered columns.

[0081] The falling edge of the clock signal receives even-numbered rows and even-numbered columns of data.

[0082] In one exemplary embodiment, each row of pixel display chips is provided with two data transmission methods, which are as follows:

[0083] With the row select pin connected to the power supply, the pixel display chip samples data when the clock signal is at the rising edge;

[0084] When the row select pin is grounded, the pixel display chip samples data when the clock signal is at the falling edge.

[0085] Alternatively, the two data transmission methods are as follows:

[0086] With the row select pin connected to the power supply, the pixel display chip samples data when the clock signal is at the falling edge;

[0087] When the row select pin is grounded, the pixel display chip samples data when the clock signal is on the rising edge.

[0088] Furthermore, the pixel display chips of adjacent rows use the same row select clock signal, specifically:

[0089] When the rising edge of the clock signal is used for the odd-numbered row pixel display chip to receive data, the falling edge of the clock signal is used for the even-numbered row pixel display chip to receive data. At the same time, when the row chip select pin of a row pixel display chip is connected to the power supply, the row chip select pin of the adjacent row pixel display chip is grounded, as shown in Figure 2.

[0090] And when the column select pin of a column of pixel display chips is connected to the power supply, the column select pins of the adjacent column of pixel display chips are grounded, as shown in Figure 2.

[0091] In an exemplary embodiment, referring further to FIG2, the pixel display chip data is provided with two data transmission schemes, which are as follows:

[0092] In the first scheme, when the column select pin is connected to the power supply, the pixel unit connected to the odd-numbered column pixel display chip receives data; when the column select pin is grounded, the pixel unit connected to the even-numbered column pixel display chip receives data.

[0093] In the second scheme, when the column select pin is connected to the power supply, the pixel unit connected to the even-numbered column pixel display chip receives data; when the column select pin is grounded, the pixel unit connected to the odd-numbered column pixel display chip receives data.

[0094] In an exemplary embodiment, a display system with time-division multiplexing of control signals controls a large display screen with an m+1-bit grayscale depth. The pixel display chip of this system has a row chip select pin and a column chip select pin, as shown in Figure 3. This provides a schematic diagram of the data structure of a display system with time-division multiplexing of control signals, illustrating the data structure for odd-row and odd-column displays and even-row and odd-column displays, with serial single-bit (byte) transmission. The serial single-byte transmission can send the least significant bit first or the most significant bit first. The `Data_odd_odd flag` represents the flag bit for odd-row and odd-column displays; a value of 1 indicates that the chip for odd-row and odd-column displays is enabled, receiving data and lighting up. The `Data_even_odd flag` represents the flag bit for even-row and odd-column displays; a value of 1 indicates that the chip for even-row and odd-column displays is enabled, receiving data and lighting up.

[0095] Specifically, the sequence is as follows: Data_odd_odd R_bit0 (the 0th bit of the red data for odd-row, odd-column pixels), Data_even_odd R_bit0 (the 0th bit of the red data for even-row, odd-column pixels), Data_odd_odd R_bit1 (the 1st bit of the red data for odd-row, odd-column pixels), Data_even_odd R_bit1 (the 1st bit of the red data for even-row, odd-column pixels), up to Data_odd_odd R_bitm (the mth bit of the red data for odd-row, odd-column pixels), Data_even_odd R_bitm (the mth bit of the red data for even-row, odd-column pixels); then Data_odd_odd G_bit0 (the 0th bit of the green data for odd-row, odd-column pixels), Data_even_odd G_bit0 (the 0th bit of the green data for even-row, odd-column pixels), Data_odd_odd G_bit1 (the 1st bit of the green data for odd-row, odd-column pixels), Data_even_odd... The sequence is as follows: G_bit1 (the first green data bit in even rows and odd columns), up to Data_odd_odd G_bitm (the m-th green data bit in odd rows and odd columns) and Data_even_odd G_bitm (the m-th green data bit in even rows and odd columns); finally, the sequence is as follows: Data_odd_odd B_bit0 (the 0-th blue data bit in odd rows and odd columns), Data_even_odd B_bit0 (the 0-th blue data bit in even rows and odd columns), Data_odd_odd B_bit1 (the first blue data bit in odd rows and odd columns), Data_even_odd B_bit1 (the first blue data bit in even rows and odd columns), up to Data_odd_odd B_bitm (the m-th blue data bit in odd rows and odd columns) and Data_even_odd B_bitm (the m-th blue data bit in even rows and odd columns).

[0096] Following the above sequence, data is transmitted bit by bit. First, each bit of red data is transmitted, then each bit of green data, and finally each bit of blue data. Pixel data in odd-numbered rows and columns, and even-numbered rows and columns, are transmitted alternately in sequence, and the corresponding pixel units receive the data sequentially and illuminate accordingly.

[0097] In an exemplary embodiment, a display system with time-division multiplexing of control signals controls a large display screen with an m+1 bit grayscale depth. The pixel display chip of this display system has a row chip select pin and a column chip select pin. As shown in Figure 4, a data structure diagram of a display system with time-division multiplexing of control signals is provided, showing the data structure of odd rows and even columns, and even rows and even columns. The data is transmitted serially in single bits (bytes). The Data_odd_even flag represents the flag bit of the odd row and even column. 0 indicates that the chip of the odd row and even column is enabled, receiving data and lighting up. The Data_even_even flag represents the flag bit of the even row and even column. 0 indicates that the chip of the even row and even column is enabled, receiving data and lighting up.

[0098] Specifically, the sequence is as follows: Data_odd_even R_bit0 (the 0th bit of the red data for odd-row, even-column pixels), Data_even_even R_bit0 (the 0th bit of the red data for even-row, even-column pixels), Data_odd_even R_bit1 (the 1st bit of the red data for odd-row, even-column pixels), Data_even_even R_bit1 (the 1st bit of the red data for even-row, even-column pixels), up to Data_odd_even R_bitm (the mth bit of the red data for odd-row, even-column pixels), Data_even_even R_bitm (the mth bit of the red data for even-row, even-column pixels); then Data_odd_even G_bit0 (the 0th bit of the green data for odd-row, even-column pixels), Data_even_even G_bit0 (the 0th bit of the green data for even-row, even-column pixels), Data_odd_even G_bit1 (the 1st bit of the green data for odd-row, even-column pixels), Data_even_even The sequence is as follows: G_bit1 (the first green data bit in even-numbered rows and even-numbered columns), up to Data_odd_even G_bitm (the m-th green data bit in odd-numbered rows and even-numbered columns), Data_even_even G_bitm (the m-th green data bit in even-numbered rows and even-numbered columns); finally, the sequence is as follows: Data_odd_even B_bit0 (the 0-th blue data bit in odd-numbered rows and even-numbered columns), Data_even_even B_bit0 (the 0-th blue data bit in even-numbered rows and even-numbered columns), Data_odd_even B_bit1 (the first blue data bit in odd-numbered rows and even-numbered columns), Data_even_even B_bit1 (the first blue data bit in even-numbered rows and even-numbered columns), up to Data_odd_even B_bitm (the m-th blue data bit in odd-numbered rows and even-numbered columns), Data_even_even B_bitm (the m-th blue data bit in even-numbered rows and even-numbered columns).

[0099] The data transmission order is described above. Data is sent bit by bit, first each bit of red data, then each bit of green data, and finally each bit of blue data. Pixel data in odd-numbered rows and even-numbered columns, and vice versa, are sent sequentially.

[0100] In an exemplary embodiment, taking a 1920x1080 pixel display with 8-bit grayscale depth and a pixel chip having one row chip select pin and one column chip select pin as an example, the data structure is as follows: The `Data_odd_odd` flag represents the flag bit for odd-numbered rows and columns; 1 indicates that the chip is enabled for odd-numbered rows and columns, receiving data and lighting up, such as row 1, column 1; row 1, column 3... row 1, column 1919; row 3, column 1; row 3, column 3... row 1079, column 1919. The `Data_even_odd` flag represents the flag bit for even-numbered rows and columns; 1 indicates that the chip is enabled for even-numbered rows and columns, receiving data and lighting up, such as row 2, column 1; row 2, column 3... row 2, column 1919; row 4, column 1; row 4, column 3... row 1080, column 1919. According to `Data_odd_odd R_bit0`, `Data_even_odd`... R_bit0, Data_odd_odd R_bit1, Data_even_odd R_bit1... until Data_odd_odd R_bit7, Data_even_odd R_bit7, then Data_odd_odd G_bit0, Data_even_odd G_bit0, Data_odd_oddG_bit1, Data_even_odd G_bit1... until Data_odd_odd G_bit7, Data_even_odd G_bit7, and finally Data_odd_odd B_bit0, Data_even_odd B_bit0, Data_odd_odd B_bit1, Data_even_odd B_bit1... until Data_odd_odd B_bit7, Data_even_odd B_bit7.

[0101] The data structure is as follows: The `Data_odd_even` flag represents the flag bit for odd-numbered rows and even-numbered columns. A 0 indicates that the chip is enabled for odd-numbered rows and even-numbered columns, receiving data and lighting up the corresponding position. Examples include: row 1, column 2; row 1, column 4... row 1, column 1920; row 3, column 2; row 3, column 4... row 1079, column 1920. The `Data_even_even` flag represents the flag bit for even-numbered rows and even-numbered columns. A 0 indicates that the chip is enabled for even-numbered rows and even-numbered columns, receiving data and lighting up the corresponding position. Examples include: row 2, column 2; row 2, column 4... row 2, column 1920; row 4, column 2; row 4, column 4... row 1080, column 1920. The flag is assigned according to `Data_odd_even R_bit0`, `Data_even_even R_bit0`, `Data_odd_even R_bit1`, `Data_even_even R_bit1`... up to `Data_odd_even R_bit7`, `Data_even_even`... R_bit7, then Data_odd_even G_bit0, Data_even_even G_bit0, Data_odd_even G_bit1, Data_even_even G_bit1... until Data_odd_even G_bit7, Data_even_even G_bit7, and finally Data_odd_even B_bit0, Data_even_even B_bit0, Data_odd_even B_bit1, Data_even_even B_bit1...until Data_odd_even B_bit7, Data_even_even B_bit7.

[0102] The rising edge of the clock signal is used for data transmission in odd-numbered rows, such as row 1, row 3, row 5... row 1079; the falling edge of the clock signal is used for data transmission in even-numbered rows, such as row 2, row 4, row 6... row 1080.

[0103] After receiving the data through this data structure, a corresponding driving signal is generated to light up a single pixel LED, thus completing the large screen display.

[0104] In an exemplary embodiment, as shown in FIG5, a display method for time-division multiplexing of control signals is provided, which is applied to the display system for time-division multiplexing of control signals in FIG1, including the following steps 502 to 506.

[0105] in:

[0106] Step 502: Generate clock signal, store initial data and generate marker pixel data.

[0107] Among them, the marked pixel data is new data with marked bits.

[0108] For example, the main controller stores the original data and generates new data with a tag bit. The main controller generates a clock signal and outputs the clock signal and the new data with the tag bit to the pixel display chip.

[0109] Step 504: Generate a pixel drive signal based on the clock signal and the marked pixel data.

[0110] For example, the pixel display chip is based on a pre-set mapping relationship of received data, specifically:

[0111] When the pixel display chip receives the rising edge of the clock signal, it determines that the odd-numbered row pixel units will receive data; when the corresponding falling edge of the clock signal arrives, it determines that the even-numbered row pixel units will receive data. Or

[0112] When the pixel display chip receives the falling edge of the clock signal, it determines that the odd-numbered row of pixel units will receive data; when the corresponding rising edge of the clock signal is received, it determines that the even-numbered row of pixel units will receive data.

[0113] Based on any of the aforementioned preset mapping relationships, the pixel display chip receives data. Furthermore, the pixel display chip identifies the marker bits in the marked pixel data to determine whether to receive the corresponding data in an odd-numbered or even-numbered sequence.

[0114] Step 506: Light up the pixel unit corresponding to the pixel driving signal based on the pixel driving signal.

[0115] For example, after identifying the marker bit, the pixel display chip generates a driving signal that can drive the target row and target column based on the pixel units of the determined target row and target column, and transmits the driving signal to the corresponding pixel unit, and the pixel unit receiving the data lights up.

[0116] In this embodiment, the main controller is connected to the pixel display chip. The main controller generates marked pixel data with tagged bits based on the raw data stored in it. Then, the pixel display chip determines the target row pixel unit and receives the marked pixel data based on the received clock signal. After that, the target column pixel unit is determined by identifying the tagged bits of the received marked pixel data, so that the target column pixel unit receives data in a time-division manner. The pixel display chip drives the target row pixel unit and the target column pixel unit according to the marked pixel data, realizing the effect of one main controller driving multiple pixel display chips, and achieving the effects of driving each pixel unit to light up multiple times, long lighting time and high refresh rate.

[0117] In one exemplary embodiment, generating a pixel drive signal based on a clock signal and marker pixel data includes:

[0118] The target row pixel unit is determined based on the clock signal; the target column pixel unit is determined based on the marked pixel data; and the pixel driving signal is generated based on the target row pixel unit and the target column pixel unit.

[0119] For example, the pixel display chip is pre-set to receive data on odd or even rows at the rising edge of the clock signal, and correspondingly, the falling edge of the input clock determines whether to receive data on even or odd rows; and a flag bit is pre-set to determine whether to receive data on odd or even columns in a time-division manner.

[0120] By using pre-defined data transmission rules, the pixel display chip receives the marker pixel data of the target row at the rising or falling edge of the clock signal. After receiving the marker pixel data of the target row, the pixel display chip identifies the marker bits in the marker pixel data of the target row, thereby determining the target column. Based on the determined target column and target row, the pixel display chip determines the target pixel unit to be illuminated, and then generates the corresponding pixel driving signal and transmits the pixel driving signal to the target pixel unit.

[0121] In an exemplary embodiment, a display method for time-division multiplexing control signals is provided. When applied to the display system for time-division multiplexing control signals in Figure 1, the method includes the following steps:

[0122] Generate clock signals, store initial data, and generate marker pixel data.

[0123] The target row pixel unit is determined based on the clock signal.

[0124] The target column pixel unit is determined based on the marked pixel data.

[0125] Pixel driving signals are generated based on the target row pixel units and the target column pixel units.

[0126] The pixel unit corresponding to the pixel driving signal is lit based on the pixel driving signal.

[0127] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0128] Based on the same inventive concept, this disclosure also provides a display device for implementing the control signal time-division multiplexing display method described above. The solution provided by this device is similar to the implementation described in the above method; therefore, the specific limitations in one or more control signal time-division multiplexing display device embodiments provided below can be found in the limitations of the control signal time-division multiplexing display method described above, and will not be repeated here.

[0129] In an exemplary embodiment, as shown in FIG6, a display device for time-division multiplexing control signals is provided, including: a control module 602, a data processing module 604, and a driving module 606, wherein:

[0130] The control module 602 is used to generate clock signals, store initial data, and generate marker pixel data.

[0131] The data processing module 604 is used to generate a pixel drive signal based on the clock signal and the marker pixel data.

[0132] The driving module 606 is used to light up the pixel unit corresponding to the pixel driving signal based on the pixel driving signal.

[0133] In an exemplary embodiment, the data processing module 604 is further configured to determine a target row pixel unit based on a clock signal; determine a target column pixel unit based on marker pixel data; and generate a pixel driving signal based on the target row pixel unit and the target column pixel unit.

[0134] The modules in the aforementioned time-division multiplexing display device for control signals can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device, or stored in the memory of a computer device as software, so that the processor can call and execute the operations corresponding to each module.

[0135] In an exemplary embodiment, a computer device is provided, which may be a server, and its internal structure diagram is shown in Figure 7. The computer device includes a processor, memory, input / output interfaces (I / O), and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is connected to the system bus via the I / O interfaces. The processor of the computer device provides computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The database of the computer device stores raw data and marked pixel data. The I / O interfaces of the computer device are used for exchanging information between the processor and external devices. The communication interface of the computer device is used for communicating with external terminals via a network connection. When the computer program is executed by the processor, it implements a display method that uses time-division multiplexing of control signals.

[0136] Those skilled in the art will understand that the structure shown in Figure 7 is merely a block diagram of a portion of the structure related to the present disclosure and does not constitute a limitation on the computer device to which the present disclosure is applied. A specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0137] In one exemplary embodiment, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above-described method embodiments.

[0138] In one exemplary embodiment, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the steps in the above-described method embodiments.

[0139] In one exemplary embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above-described method embodiments.

[0140] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this disclosure are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.

[0141] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the methods described above. Any references to memory, databases, or other media used in the embodiments provided in this disclosure can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this disclosure may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this disclosure may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0142] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0143] The embodiments described above are merely illustrative of several implementations of this disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these all fall within the scope of protection of this disclosure. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A display system for time-division multiplexing control signals, wherein, The display system includes: The main controller is used to generate clock signals, store initial data, and generate marker pixel data; Pixel display chips, each connected to the main controller, are used to generate pixel drive signals based on the clock signal and the marked pixel data; A pixel unit, which is connected to the pixel display chip, is used to light up the pixel unit corresponding to the pixel driving signal based on the pixel driving signal.

2. The display system for time-division multiplexing control signals according to claim 1, wherein, The pixel display chip includes input pins and output pins, and the main controller includes output pins. The input pins of the pixel display chip include clock signal pins and serial data pins, and the output pins of the main controller include clock signal pins and serial data pins. The clock signal pin of the pixel display chip is connected to the clock signal pin of the main controller; The serial data pin of the pixel display chip is connected to the serial data pin of the main controller; The output pins of the pixel display chip are connected to the pixel unit.

3. The display system for time-division multiplexing control signals according to claim 2, wherein, A first pin number mapping relationship is established between the main controller and the pixel display chip, and the first pin number mapping relationship is as follows: When the pixel display chip has a*b units, the main controller provides a+b pins; where a is the number of rows and b is the number of columns.

4. The display system for time-division multiplexing control signals according to claim 3, wherein, The input pins of the pixel display chip further include row chip select pins and column chip select pins, both of which are connected to the main controller. A second pin number mapping relationship is also established between the main controller and the pixel display chip, and this second pin number mapping relationship is as follows: With an additional row chip select pin added to each of the pixel display chips, the main controller provides a / 2+b pins; With the addition of j column select pins to each pixel display chip, the main controller provides (a / 2 + b / 2) j (Number of pins) 5. The display system for time-division multiplexing control signals according to claim 4, wherein, Each row of pixel display chips has two data transmission methods, which are as follows: When the row select pin is connected to a power supply, the pixel display chip samples data when the clock signal is at its rising edge; when the row select pin is grounded, the pixel display chip samples data when the clock signal is at its falling edge; or When the row chip select pin is connected to a power supply, the pixel display chip samples data when the clock signal is at a falling edge; when the row chip select pin is grounded, the pixel display chip samples data when the clock signal is at a rising edge.

6. The display system for time-division multiplexing control signals according to claim 5, wherein, When the row chip select pin of a pixel display chip in one row is connected to a power supply, the row chip select pin of the pixel display chip in the adjacent row is grounded.

7. The display system for time-division multiplexing control signals according to claim 6, wherein, When the column select pin of one column of the pixel display chips is connected to a power supply, the column select pin of the pixel display chips in adjacent columns is grounded.

8. The display system for time-division multiplexing control signals according to claim 7, wherein, The pixel display chip data is provided with two data transmission schemes, which are as follows: When the column select pin is connected to a power supply, the pixel unit connected to the pixel display chip in the odd-numbered column receives data; when the column select pin is grounded, the pixel unit connected to the pixel display chip in the even-numbered column receives data. or When the column select pin is connected to a power supply, the pixel unit connected to the even-numbered column pixel display chip receives data; when the column select pin is grounded, the pixel unit connected to the odd-numbered column pixel display chip receives data.

9. A display method for time-division multiplexing control signals, applicable to the display system for time-division multiplexing control signals as described in any one of claims 1 to 8, wherein, The display method includes: Generate clock signals, store initial data, and generate marker pixel data; A pixel driving signal is generated based on the clock signal and the marked pixel data; The pixel unit corresponding to the pixel driving signal is lit based on the pixel driving signal.

10. The display method for time-division multiplexing control signals according to claim 9, wherein, The generation of pixel driving signals based on the clock signal and the marked pixel data includes: The target row pixel unit is determined based on the clock signal; The target column pixel unit is determined based on the marked pixel data; Pixel driving signals are generated based on the target row pixel units and the target column pixel units.

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