DDR module packaging structure and manufacturing method therefor

Abstract

The present application relates to the technical field of semiconductor device packaging, and in particular to a DDR module packaging structure and a manufacturing method therefor. The DDR module packaging structure provided by the present application comprises: a plurality of DDR chip sets arranged in a same layer, wherein each DDR chip set comprises a plurality of DDR chips that are stacked; a packaging layer, covering the DDR chip sets; an IPD wafer, arranged on one side of the packaging layer, wherein at least an IPD chip is arranged in the IPD wafer; and an IVR chip, arranged on the other side of the packaging layer, wherein the IVR chip is electrically connected to the IPD wafer, some of the DDR chips are electrically connected to the IPD chip, and some of the DDR chips are electrically connected to the IVR chip.

Description

A DDR module packaging structure and its fabrication method

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411204755.3, filed on August 29, 2024, entitled "A DDR Module Packaging Structure and its Preparation Method", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of semiconductor device packaging technology, specifically to a DDR module packaging structure and its fabrication method. Background Technology

[0004] With the rapid development of AI applications in PCs, mobile terminals, and small aircraft, the market demand for smaller, lower-power, and higher-performance memory chips is becoming increasingly urgent. Memory chip operation requires power modules and passive components to provide stable power and pull-up voltages to DDR chips. Commonly, the integrated transmission paths of power modules and passive components are relatively long, and power and signal integrity need further improvement. IPD wafers contain passive components such as IPD chips, resistors, and capacitors, which can be used for pull-up and filtering noise reduction of DDR chip address and control lines. They are also commonly used in DDR chip stacking integration schemes. Shortening the transmission distance between the integrated voltage regulator (IVR) chip, passive components, DDR chips, and IPD chips is an important way to reduce VCC noise, improve crosstalk and return loss, and thus improve power and signal integrity.

[0005] Current DDR chip stacking and integration solutions are mostly board-mount, resulting in low integration between DDR chips, passive components, and IVR chips. This leads to long transmission distances and consequently, issues such as poor signal and power integrity. Specifically, signal transmission is affected by impedance, delay, reflection, and crosstalk in the transmission line, causing deviations from the original amplitude, phase, and waveform characteristics. Power supply is also affected by various factors, resulting in poor current stability and noise inclusion. Furthermore, board-mount DDR module packaging suffers from inflexible substrate design, long process cycles, and high costs. Therefore, a solution is needed to improve the integration of DDR chips with passive components and IVR chips, thereby increasing design flexibility, shortening production cycles, and reducing manufacturing costs. Summary of the Invention

[0006] Therefore, this application provides a DDR module packaging structure and its fabrication method to solve the problems of low integration density of DDR chips, passive devices, and IVRs in existing memory chip integration solutions, and low signal and power integrity due to long transmission distances. Simultaneously, it improves upon the shortcomings of existing integration technologies, such as inflexible substrate design, long process cycles, and high costs.

[0007] This application provides a DDR module packaging structure, including: multiple DDR chipsets arranged on the same layer; each DDR chipset includes multiple DDR chips stacked together; a packaging layer covering each DDR chipset; an IPD wafer disposed on one side of the packaging layer; at least one IPD chip disposed in the IPD wafer; an IVR chip disposed on the other side of the packaging layer; the IVR chip being electrically connected to the IPD wafer; some of the DDR chips being electrically connected to the IPD chip; and some of the DDR chips being electrically connected to the IVR chip.

[0008] Optionally, the DDR module packaging structure further includes a redistribution layer; the redistribution layer includes a metal wiring layer and an insulating isolation layer covering the metal wiring layer; the redistribution layer is located between the IVR chip and the packaging layer; the DDR chip electrically connected to the IVR chip is connected to the IVR chip through the redistribution layer; the IPD chip electrically connected to the IVR chip is connected to the IVR chip through the redistribution layer; the DDR chip electrically connected to the IPD chip is connected to the IPD chip through the redistribution layer.

[0009] Optionally, the DDR chips in the DDR chipset are staggered and stacked, and each DDR chip is directly connected to or connected to the metal wiring layer in the redistribution layer via a connecting line; the IPD chip is connected to the metal wiring layer in the redistribution layer via a connecting line.

[0010] Optionally, in each of the DDR chipsets, each of the DDR chips is identical; each of the DDR chips is directly or indirectly connected to the IVR chip, and each is directly or indirectly connected to the IPD chip.

[0011] Optionally, the DDR module packaging structure further includes: solder balls disposed on the side of the redistribution layer facing away from the packaging layer, connected to the metal wiring layer, and disposed on the same layer as the IVR chip.

[0012] Optionally, the DDR chipset is divided into two groups, with four DDR chips in each group; the IVR chip is located between the two corresponding DDR chipsets.

[0013] This application also provides a method for fabricating a DDR module packaging structure, comprising the following steps: providing an IPD wafer, wherein the IPD wafer is provided with at least one IPD chip; forming multiple DDR chip groups on the IPD wafer; wherein each DDR chip group is disposed on the same layer; wherein connection lines are provided for each DDR chip and connection lines are provided for the IPD chip; forming a packaging layer, wherein the packaging layer covers each DDR chip group and each connection line; and mounting an IVR chip, located on the side of the packaging layer opposite to the IPD wafer, and connected to each connection line.

[0014] Optionally, after forming the encapsulation layer and before mounting the IVR chip, the method further includes: forming a redistribution layer located on the side of the encapsulation layer opposite to the IPD wafer; the redistribution layer includes a metal wiring layer and an insulating isolation layer covering the metal wiring layer; the metal wiring layer is connected to each of the connection lines; the IVR chip is mounted on the side of the redistribution layer opposite to the IPD wafer and connected to the metal wiring layer in the redistribution layer.

[0015] Optionally, the DDR chips in the DDR chipset are staggered and stacked, and each DDR chip is directly connected to or connected to the metal wiring layer in the redistribution layer via a connecting line; the IPD chip is connected to the metal wiring layer in the redistribution layer via a connecting line; in each DDR chipset, at least one DDR chip is connected to the IVR chip, and at least one DDR chip is connected to the IPD chip.

[0016] Optionally, before forming the redistribution layer, the method further includes: thinning the IPD wafer; thinning the packaging layer to expose the pins of the outermost DDR chip and the ends of each of the interconnect lines; before mounting the IVR chip, the method further includes: forming solder balls, the solder balls being formed on the surface of the redistribution layer facing away from the IPD wafer, connecting to the metal wiring layer; and the solder balls reserving a preset mounting area for the IVR chip; the IVR chip being mounted in the preset mounting area.

[0017] The technical solution of this application has the following advantages:

[0018] The DDR module packaging structure provided in this application integrates the DDR chipset, IPD chip, and IVR chip into a single module, improving the overall integration of the module and reducing the transmission distance between components within the module. This improves crosstalk and return loss, reduces PDN impedance, and enhances signal and power integrity. The IVR chip provides a stable and clean power supply to the DDR and IPD chips, while the IPD chip provides pull-up voltages to the address and control lines of the DDR chip. Reducing the interconnection distance between the DDR, IPD, and IVR chips further reduces transmission distance, improves crosstalk and return loss, and reduces PDN impedance, thereby enhancing signal and power integrity.

[0019] The method for fabricating the DDR module packaging structure provided in this application can fabricate the DDR module packaging structure provided in this application. Integrating the DDR chipset, IPD chip, and IVR chip into a single module improves the overall integration of the module, reduces the transmission distance between components within the module, improves crosstalk and return loss, and reduces PDN impedance, thereby improving signal and power integrity. The IVR chip provides a stable and clean power supply to the DDR chip and IPD chip, while the IPD chip provides pull-up voltages to the address and control lines of the DDR chip. Reducing the interconnection distance between the DDR chip, IPD chip, and IVR chip further reduces transmission distance, improves crosstalk and return loss, and reduces PDN impedance, thereby improving signal and power integrity.

[0020] Furthermore, the DDR module packaging structure and manufacturing method provided in this application are based on wafer-level fan-out packaging technology, directly implementing packaging on the IPD (Integrated Passive Device) wafer. Compared with traditional DDR memory modules, no substrate is required, shortening the production cycle and reducing costs. Compared with conventional fan-out packaging technology, the temporary carrier bonding process is eliminated, further simplifying the production process. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0022] Figure 1 is a schematic diagram of the DDR module packaging structure according to an embodiment of this application;

[0023] Figure 2 is a schematic diagram of the system framework of a DDR module packaging structure according to an embodiment of this application;

[0024] Figures 3-11 are schematic diagrams of various states in the specific process of a method for preparing a DDR module packaging structure according to an embodiment of this application.

[0025] Explanation of reference numerals in the attached figures: 100 - IPD wafer; 210, 220 - DDR chipset; 211, 212, 213, 214, 221, 222, 223, 224 - DDR chips; 300 - Package layer; 400 - IVR chip; 500 - Redistribution layer; 600 - Solder ball. Detailed Implementation

[0026] To address the issues of low integration density of DDR chips, passive devices, and IVRs in existing memory chip integration solutions, resulting in low signal and power integrity due to long transmission distances, and to improve the shortcomings of inflexible substrate design, long process cycles, and high costs in existing integration technologies, this application provides a DDR module packaging structure and its fabrication method.

[0027] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In the description of this application, it should be noted that the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0028] Example 1

[0029] Referring to Figures 1 and 2, this embodiment provides a DDR module packaging structure, including:

[0030] Multiple DDR chipsets are arranged on the same layer; for example, in this embodiment, DDR chipsets 210 and 220 are included.

[0031] The DDR chipset includes multiple DDR chips stacked together; for example, in this embodiment, DDR chipset 210 includes multiple DDR chips 211, 212, 213, and 214; DDR chipset 220 includes multiple DDR chips 221, 222, 223, and 224.

[0032] The encapsulation layer covers each of the DDR chipsets; in this embodiment, the encapsulation layer 300 covers the DDR chipsets 210 and 220.

[0033] An IPD wafer is disposed on one side of the packaging layer; the IPD wafer contains at least one IPD chip; in this embodiment, the IPD wafer 100 is disposed on one side of the packaging layer 300, and the IPD wafer 100 contains at least one IPD chip (not shown in the figure). In some embodiments, passive devices such as capacitors and resistors may also be provided (passive devices are not shown in the figure).

[0034] An IVR chip is disposed on the other side of the packaging layer; the IVR chip is electrically connected to the IPD wafer. In this embodiment, the IVR chip 400 is disposed on the other side of the packaging layer 300 and electrically connected to the IPD wafer 100.

[0035] Some of the DDR chips are electrically connected to the IPD chip; some of the DDR chips are electrically connected to the IVR chip. As shown in Figure 1, among the DDR chips 211, 212, 213, 214 and 221, 222, 223, 224, some are electrically connected to the IVR chip 400, and some are electrically connected to the IPD wafer 100, and electrically connected to the IPD chip therein.

[0036] Referring to Figure 2, the system framework diagram of a DDR chipset in this embodiment of the DDR module packaging structure shows that the chips are internally interconnected using a fly-by topology. The IVR chip provides power to the DDR chips and IPD chips. The IPD chip provides pull-up resistors for the address and control lines of the DDR chips, using the DDR protocol. Figure 2 also shows the internal signal grouping of each DDR chip in the DDR chipset according to the fly-by topology.

[0037] The DDR module packaging structure provided in this embodiment integrates the DDR chipset, IPD chip, and IVR chip into a single module, improving the overall integration of the module and reducing the transmission distance between components within the module. This improves crosstalk and return loss, reduces PDN impedance, and enhances signal and power integrity. The IVR chip provides a stable and clean power supply to the DDR and IPD chips, while the IPD chip provides pull-up voltages to the address and control lines of the DDR chip. Reducing the interconnection distance between the DDR, IPD, and IVR chips further reduces transmission distance, improves crosstalk and return loss, and lowers PDN impedance, thereby enhancing signal and power integrity.

[0038] Furthermore, the DDR module packaging structure provided in this embodiment can be directly packaged on the IPD (Integrated Passive Device) wafer based on wafer-level fan-out packaging technology. Compared with traditional DDR memory modules, it eliminates the need for a substrate, shortening the production cycle and reducing costs. Compared with conventional fan-out packaging technology, it eliminates the temporary carrier bonding process, further simplifying the production process.

[0039] Optionally, the DDR module packaging structure in this embodiment further includes:

[0040] A redistribution layer 500 is provided. The redistribution layer 500 includes a metal wiring layer (the black line portion within area 500 in the figure) and an insulating layer covering the metal wiring layer (the portion within area 500 covered by the black line in the figure). The redistribution layer 500 is located between the IVR chip 400 and the packaging layer 300. The DDR chip electrically connected to the IVR chip 400 is connected to the IVR chip 400 through the redistribution layer 500. The IPD chip electrically connected to the IVR chip 400 is connected to the IVR chip 400 through the redistribution layer 500. The DDR chip electrically connected to the IPD chip is connected to the IPD chip through the redistribution layer 500. In other words, the redistribution layer 500 acts as a relay for the connections between the chips, enabling connections between them.

[0041] Optionally, in this embodiment, the DDR chips in the DDR chipset are staggered and stacked, with each DDR chip directly connected to or connected via a connecting wire to the metal wiring layer in the redistribution layer; the IPD chip is connected to the metal wiring layer in the redistribution layer via a connecting wire. As shown in Figure 1, some DDR chips (such as 214, 224) are directly connected to the metal wiring layer in the redistribution layer 500; other DDR chips (such as 211, 212, 213, 221, 222, 223) are connected to the metal wiring layer in the redistribution layer 500 via connecting wires. The IPD chip is connected to the metal wiring layer in the redistribution layer 500 via connecting wires. In some embodiments, these connecting wires are rigid wires made of metal pillars or other conductive materials.

[0042] Optionally, in this embodiment, all DDR chips in each DDR chipset are identical; each DDR chip is directly or indirectly connected to the IVR chip and also directly or indirectly connected to the IPD chip. This ensures that the IVR chip provides a stable and clean power supply to the DDR chip and the IPD chip, while the IPD chip provides pull-up voltages to the address and control lines of the DDR chip.

[0043] Optionally, in this embodiment, the DDR module packaging structure further includes: solder balls 600, disposed on the side of the redistribution layer 500 facing away from the packaging layer 300, connected to the metal wiring layer, and disposed on the same layer as the IVR chip. By placing the IVR chip 400 in the gaps between the solder balls 600, it is separated from the IPD wafer and DDR chipset, while also eliminating the need for a separate placement outside the packaging module, thus shortening the distance between the IVR chip and the DDR chip.

[0044] Specifically, in this embodiment, the DDR chipset consists of two groups, with four DDR chips in each group; the IVR chip is located between the two corresponding DDR chipsets.

[0045] Example 2

[0046] This embodiment provides a method for fabricating a DDR module packaging structure to prepare the DDR module packaging structure provided in Embodiment 1 above. Referring to Figures 3-11, the method includes the following steps:

[0047] Referring to Figure 3, an IPD wafer is provided, wherein the IPD wafer is provided with at least one IPD chip;

[0048] Referring to Figure 4, multiple DDR chipsets are formed on the IPD wafer; each DDR chipset is arranged on the same layer.

[0049] Referring to Figure 5, the connection lines for each DDR chip and the connection lines for the IPD chip are configured.

[0050] Referring to Figure 6, an encapsulation layer is formed, which covers each of the DDR chipsets and each of the interconnect lines;

[0051] Referring to Figure 10, the IVR chip is mounted on the side of the encapsulation layer opposite to the IPD wafer and connected to each of the connection lines.

[0052] Referring to Figure 11, the wafer is finally diced to form a single-chip package structure.

[0053] The method for fabricating the DDR module packaging structure provided in this embodiment can fabricate the DDR module packaging structure provided in this application. Integrating the DDR chipset, IPD chip, and IVR chip into a single module improves the overall integration of the module, reduces the transmission distance between components within the module, improves crosstalk and return loss, and reduces PDN impedance, thereby improving signal and power integrity. The IVR chip provides a stable and clean power supply to the DDR chip and IPD chip, while the IPD chip provides pull-up voltages to the address and control lines of the DDR chip. Reducing the interconnection distance between the DDR chip, IPD chip, and IVR chip further reduces transmission distance, improves crosstalk and return loss, and reduces PDN impedance, thereby enhancing signal and power integrity.

[0054] Furthermore, the DDR module packaging structure fabrication method provided in this embodiment can be implemented directly on the IPD (Integrated Passive Device) wafer based on wafer-level fan-out packaging technology. Compared with traditional DDR memory modules, no substrate is required, shortening the production cycle and reducing costs. Compared with conventional fan-out packaging technology, the temporary carrier bonding process is eliminated, further simplifying the production process.

[0055] Optionally, referring to FIG9, after forming the encapsulation layer and before mounting the IVR chip, the method further includes: forming a redistribution layer located on the side of the encapsulation layer opposite to the IPD wafer; the redistribution layer includes a metal wiring layer and an insulating isolation layer covering the metal wiring layer; the metal wiring layer is connected to each of the connection lines; the IVR chip is mounted on the side of the redistribution layer opposite to the IPD wafer and connected to the metal wiring layer in the redistribution layer.

[0056] Optionally, the DDR chips in the DDR chipset are staggered and stacked, and each DDR chip is directly connected to or connected to the metal wiring layer in the redistribution layer via a connecting line; the IPD chip is connected to the metal wiring layer in the redistribution layer via a connecting line; in each DDR chipset, at least one DDR chip is connected to the IVR chip, and at least one DDR chip is connected to the IPD chip.

[0057] Optionally, referring to Figures 7 and 8, before forming the redistribution layer, the method further includes: thinning the IPD wafer; thinning the packaging layer to expose the pins of the outermost DDR chip and the ends of each of the interconnect lines;

[0058] Referring to Figure 9, before mounting the IVR chip, the process further includes: forming solder balls, which are formed on the surface of the redistribution layer facing away from the IPD wafer and connected to the metal wiring layer; and the solder balls reserve a preset mounting area for the IVR chip; the IVR chip is mounted in the preset mounting area.

[0059] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. A DDR module packaging structure, characterized in that, include: Multiple DDR chipsets are arranged on the same layer; the DDR chipsets include multiple DDR chips stacked on top of each other; The encapsulation layer covers each of the DDR chipsets; An IPD wafer is disposed on one side of the packaging layer; the IPD wafer contains at least one IPD chip. The IVR chip is disposed on the other side of the encapsulation layer; The IVR chip is electrically connected to the IPD wafer; Some of the DDR chips are electrically connected to the IPD chip; some of the DDR chips are electrically connected to the IVR chip.

2. The DDR module packaging structure according to claim 1, characterized in that, It also includes a redistribution layer; the redistribution layer includes a metal wiring layer and an insulating isolation layer covering the metal wiring layer; The rewiring layer is located between the IVR chip and the packaging layer; The DDR chip, which is electrically connected to the IVR chip, is connected to the IVR chip through the redistribution layer; The IPD chip, which is electrically connected to the IVR chip, is connected to the IVR chip through the redistribution layer; The DDR chip, which is electrically connected to the IPD chip, is connected to the IPD chip through the redistribution layer.

3. The DDR module packaging structure according to claim 2, characterized in that, The DDR chips in the DDR chipset are staggered and stacked, and each DDR chip is directly connected to or connected to the metal wiring layer in the redistribution layer through a connecting line. The IPD chip is connected to the metal wiring layer in the redistribution layer via a connection line.

4. The DDR module packaging structure according to claim 3, characterized in that, In each of the DDR chipsets, the DDR chips are identical; each DDR chip is directly or indirectly connected to the IVR chip, and is also directly or indirectly connected to the IPD chip.

5. The DDR module packaging structure according to claim 3, characterized in that, Also includes: Solder balls are disposed on the side of the redistribution layer opposite to the packaging layer, connecting to the metal wiring layer, and are disposed on the same layer as the IVR chip.

6. The DDR module packaging structure according to claim 3, characterized in that, The DDR chipset consists of two groups, with four DDR chips in each group. The IVR chip is located between the two corresponding DDR chipsets.

7. A method for fabricating a DDR module packaging structure, characterized in that, Includes the following steps: An IPD wafer is provided, wherein the IPD wafer is provided with at least one IPD chip; Multiple DDR chipsets are formed on the IPD wafer; All the aforementioned DDR chipsets are arranged on the same layer; Configure the connection lines for each of the DDR chips and the connection lines for the IPD chips; A packaging layer is formed, the packaging layer covering each of the DDR chipsets and each of the interconnect lines; The IVR chip is mounted on the side of the packaging layer opposite to the IPD wafer and connected to each of the connection lines.

8. The method for preparing the DDR module packaging structure according to claim 7, characterized in that, After the encapsulation layer is formed and before the IVR chip is mounted, the process also includes: A redistribution layer is formed on the opposite side of the packaging layer relative to the IPD wafer; the redistribution layer includes a metal wiring layer and an insulating isolation layer covering the metal wiring layer; the metal wiring layer is connected to each of the interconnect lines. The IVR chip is mounted on the side of the redistribution layer facing away from the IPD wafer and is connected to the metal wiring layer in the redistribution layer.

9. The method for preparing the DDR module packaging structure according to claim 8, characterized in that, The DDR chips in the DDR chipset are staggered and stacked, and each DDR chip is directly connected to or connected to the metal wiring layer in the redistribution layer through a connecting line. The IPD chip is connected to the metal wiring layer in the redistribution layer via a connection line; In each of the DDR chipsets, at least one DDR chip is connected to the IVR chip, and at least one DDR chip is connected to the IPD chip.

10. The method for preparing the DDR module packaging structure according to claim 8, characterized in that, Before forming the redistribution layer, the process further includes: thinning the IPD wafer; thinning the packaging layer to expose the pins of the outermost DDR chip and the ends of each of the interconnects; Before mounting the IVR chip, the process further includes: forming solder balls, which are formed on the surface of the redistribution layer facing away from the IPD wafer and connected to the metal wiring layer; and the solder balls reserve a preset mounting area for the IVR chip; the IVR chip is mounted in the preset mounting area.

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