Circuit for implementing power protection and corresponding power amplifier module, and electronic device

Abstract

Disclosed in the present invention are a circuit for implementing power protection and a corresponding power amplifier module, and an electronic device. The power amplifier module comprises a controller unit, a radio frequency power amplifier unit, and a filter unit. The controller unit is used for providing a bias voltage to the radio frequency power amplifier unit. The radio frequency power amplifier unit is used for performing power amplification on a radio frequency signal. The filter unit is used for performing filtering processing on the amplified radio frequency signal. When the input power of the radio frequency signal is increased to a first threshold or reduced to a second threshold, the controller unit generates a corresponding first control signal, second control signal and third control signal, so that an outputted first bias voltage is reduced or increased in steps, and the gain and output power of the power amplifier module are accordingly reduced or increased in steps, thereby improving the reliability of the power amplifier module.

Description

Circuits for power protection and corresponding power amplifier modules and electronic equipment Technical Field

[0001] This invention relates to a circuit for implementing power protection, as well as a corresponding power amplifier module and an electronic device including the power amplifier module, belonging to the field of radio frequency integrated circuit technology. Background Technology

[0002] With the rapid development of 5G communication technology, the mainstream RF front-end architecture has now evolved to Phase 7L (seventh-generation RF front-end solution) and Phase 7LE (an enhanced version of Phase 7L), while Phase 8 (eighth-generation RF front-end solution) is also under planning and discussion. Looking at its evolutionary history, RF front-end solutions have consistently moved towards higher integration and miniaturization.

[0003] In existing technologies, the L-PAMiD solution, with the highest integration level, modularizes power amplifiers, RF switches, analog controllers, low-noise amplifiers, and filters. The advantage of this solution is its high integration level and small footprint on the terminal motherboard. However, a disadvantage is the inherent reliability risk: when the power amplifier is turned on or off under high input power, it is prone to burnout or failure. As is well known, when there is a reliability risk, high integration significantly increases device cost, and this reliability risk can even hinder the evolution of high integration and miniaturization of RF front-end modules. Therefore, how to improve the reliability of power amplifier modules under high input power conditions and meet the development requirements of high integration and miniaturization of RF front-ends remains a very important research topic in this field.

[0004] PCT international application PCT / US2014 / 046043 discloses a power amplifier circuit and an input power limiter circuit. The power amplifier circuit includes an input matching network, a power detector, a directional coupler, a first power amplifier stage, a second power amplifier stage, a control circuit, a hysteresis circuit, an inter-stage matching network, and a switching transistor. The power detector generates a voltage output proportional to the power level of the input signal. The control circuit generates a gain reduction signal based on a comparison between the voltage output from the power detector and a predetermined voltage level corresponding to a specific power level of the input signal. The total gain of the power amplifier circuit is reduced according to the gain reduction signal, which adjusts the configuration of the circuit components. This technical solution uses a directional coupler, a programmable attenuator, an input power detector, and an output power detector to jointly control the bias circuit, resulting in a complex and cumbersome logic process and low fault tolerance. Summary of the Invention

[0005] The primary technical problem to be solved by this invention is to provide a circuit for implementing power protection, specifically including a power detection circuit and a ladder logic control circuit.

[0006] Another technical problem to be solved by the present invention is to provide a power amplifier module including the above-described circuit.

[0007] Another technical problem to be solved by the present invention is to provide an electronic device including the power amplifier module.

[0008] To achieve the above objectives, the present invention adopts the following technical solution:

[0009] According to a first aspect of the present invention, a power detection circuit for a power amplifier module is provided, comprising a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, a second PMOS transistor, a first NPN transistor, and a first operational amplifier, as well as a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, and a seventh resistor, and a first capacitor, a second capacitor, and a third capacitor; wherein,

[0010] The RF signal input terminal is connected to the first terminal of the first capacitor. The second terminal of the first capacitor is connected to the first terminal of the third resistor and the gate of the first NMOS transistor. The source of the first NMOS transistor and the source of the second NMOS transistor are grounded together. The gate of the second NMOS transistor is connected to the second terminal of the third resistor, the first terminal of the first resistor, and the first terminal of the second resistor through a fourth resistor. The second terminal of the first resistor serves as a bias terminal and is connected to the first output terminal of the voltage / current bias generation circuit. The second terminal of the second resistor is grounded. The two terminals of the second capacitor are connected to the source and drain of the first NMOS transistor, and the two terminals of the third capacitor are connected to the source and drain of the second NMOS transistor. The drain of the first NMOS transistor is connected to the power supply voltage terminal through a fifth resistor. The first NMOS transistor is connected to the power supply voltage terminal via a sixth resistor and is also connected to the non-inverting input terminal of the first operational amplifier. The output terminal of the first operational amplifier serves as the output terminal of the power detection circuit and is connected to the base of the first NPN transistor and the input terminal of the voltage hysteresis comparator. The emitter of the first NPN transistor is grounded via a seventh resistor. The collector of the first NPN transistor is connected to the drain of the first PMOS transistor. The gate of the first PMOS transistor is connected to the drain and then to the gate of the second PMOS transistor. The sources of both the first and second PMOS transistors are connected to the power supply voltage terminal.

[0011] Optionally, the first NMOS transistor and the second NMOS transistor, the third resistor and the fourth resistor, the second capacitor and the third capacitor, the fifth resistor and the sixth resistor are symmetrically arranged and have the same electrical parameters.

[0012] Optionally, the first NMOS transistor and the second NMOS transistor operate in the saturation region, and their current and voltage satisfy the square law characteristic.

[0013] The first NPN transistor operates in the amplification region, and its current and voltage satisfy the exponential law characteristic.

[0014] Optionally, the input power of the radio frequency signal generates a current / voltage offset at the inverting input of the first operational amplifier. When the current / voltage offset and the feedback current act together at the inverting input of the first operational amplifier, the output detection voltage and the input power have a logarithmic linear relationship.

[0015] According to a second aspect of the present invention, a ladder logic control circuit for a power amplifier module is provided, comprising a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a seventh inverter, and an eighth inverter, as well as a first AND gate, a second AND gate, and a first OR gate, and a filtering module and a delay module; wherein,

[0016] The first output terminal of the filtering module is connected to the input terminal of the delay module in sequence through the second inverter and the third inverter. The output terminal of the delay module is connected to the first input terminal of the first AND gate and the first input terminal of the first OR gate in sequence through the fourth inverter and the fifth inverter.

[0017] The second output of the filtering module is connected to the second input of the first AND gate and the second input of the first OR gate via the sixth and seventh inverters, respectively. The output of the first AND gate is connected to the first output of the ladder logic control circuit and is also connected to the first input of the second AND gate via the eighth inverter. The output of the first OR gate is connected to the second input of the second AND gate. The output of the second AND gate is the second output of the ladder logic control circuit.

[0018] Optionally, the filtering module is used to filter out glitches or pulses in the inverse signal of the first control signal to avoid false triggering of the protection mechanism due to short-term fluctuations in input power.

[0019] The delay module is used to generate a delay time to ensure that the first bias voltage is maintained at a lower voltage level.

[0020] According to a third aspect of the present invention, a power amplifier module is provided, comprising a controller unit, an RF power amplifier unit, and a filter unit; wherein,

[0021] The radio frequency signal input terminal is connected to the input terminal of the controller unit and the input terminal of the radio frequency power amplifier unit, respectively. The output terminal of the controller unit is connected to the bias of the radio frequency power amplifier unit. The output terminal of the radio frequency power amplifier unit is connected to the input terminal of the filter unit. The output terminal of the filter unit is connected to the radio frequency signal output terminal.

[0022] The controller unit includes the aforementioned power detection circuit or stepped logic control circuit, used to provide bias voltage to the RF power amplifier unit.

[0023] According to a fourth aspect of the present invention, a power amplifier module is provided, comprising a controller unit, an RF power amplifier unit, and a filter unit; wherein,

[0024] The radio frequency signal input terminal is connected to the input terminal of the controller unit and the input terminal of the radio frequency power amplifier unit, respectively. The output terminal of the controller unit is connected to the bias of the radio frequency power amplifier unit. The output terminal of the radio frequency power amplifier unit is connected to the input terminal of the filter unit. The output terminal of the filter unit is connected to the radio frequency signal output terminal.

[0025] The controller unit is used to provide a bias voltage to the RF power amplifier unit, and includes a bandgap reference circuit, a voltage / current bias generation circuit, a voltage hysteresis comparator, a bias power supply circuit, the aforementioned power detection circuit, and a ladder logic control circuit; wherein,

[0026] The bandgap reference circuit is used to generate and output a first reference voltage and a second reference voltage, which respectively provide reference voltages to the voltage / current bias generation circuit and the bias power supply circuit;

[0027] The voltage / current bias generation circuit is used to generate and output a second bias voltage to the power detection circuit, and to generate and output a reference voltage and bias current to the voltage hysteresis comparator.

[0028] The power detection circuit is used to detect the power of the input radio frequency signal, convert it to generate a detection voltage, and output it to the voltage hysteresis comparator.

[0029] The voltage hysteresis comparator is used to compare the detected voltage with the reference voltage to generate the first control signal, and output it to the ladder logic control circuit.

[0030] The ladder logic control circuit is used to generate the second control signal and the third control signal after logical combination of the first control signal, and output them to the bias power supply circuit.

[0031] The bias power supply circuit is used to generate the first bias voltage according to the second control signal and the third control signal, and output it to the RF power amplifier unit to provide it with a bias voltage.

[0032] Optionally, the radio frequency power amplifier unit is used to amplify the radio frequency signal and output the amplified radio frequency signal to the filter unit;

[0033] The filter unit is used to filter the amplified radio frequency signal and output a radio frequency signal in a specific frequency band.

[0034] Optionally, the first output terminal of the bandgap reference circuit is connected to the input terminal of the voltage / current bias generation circuit, and the second output terminal is connected to the first input terminal of the bias power supply circuit; the first output terminal of the voltage / current bias generation circuit is connected to the bias terminal of the power detection circuit, and the second and third output terminals are connected to the reference voltage terminal and the bias terminal of the voltage hysteresis comparator, respectively; the input terminal of the power detection circuit is connected to the RF signal input terminal, and the output terminal is connected to the input terminal of the voltage hysteresis comparator; the output terminal of the voltage hysteresis comparator is connected to the input terminal of the ladder logic control circuit, and is connected to the input terminal of the filter module through a first inverter; the output terminal of the ladder logic control circuit is connected to the second input terminal of the bias power supply circuit, and the output terminal of the bias power supply circuit is connected to the bias terminal of the RF power amplifier unit.

[0035] Optionally, the bias power supply circuit includes an error amplifier, a power transistor, a first transmission gate, a second transmission gate, and a tenth, eleventh, and twelfth resistor. The non-inverting input of the error amplifier is connected to the second output of the bandgap reference circuit. The output of the error amplifier is connected to the gate of the power transistor. The source of the power transistor and the power supply terminal of the error amplifier are both connected to the power supply voltage terminal. The drain of the power transistor serves as the output of the bias power supply circuit and is connected to the first terminal of the tenth resistor. The tenth, eleventh, and twelfth resistors are connected in series, and the second terminal of the tenth resistor is grounded. The junction of the tenth and eleventh resistors is connected to the input of the second transmission gate, and the junction of the eleventh and twelfth resistors is connected to the input of the first transmission gate. The outputs of both the first and second transmission gates are connected to the inverting input of the error amplifier. The control terminal of the first transmission gate is connected to the first output of the ladder logic control circuit, and the control terminal of the second transmission gate is connected to the second output of the ladder logic control circuit.

[0036] Optionally, when the input power of the radio frequency signal increases to a first threshold or decreases to a second threshold, the controller unit generates a corresponding first control signal, a second control signal, and a third control signal to control the first bias voltage output by the controller unit to decrease or increase in a stepwise manner, thereby causing the gain and output power of the power amplifier module to decrease or increase in a stepwise manner; wherein, the first threshold is greater than the second threshold.

[0037] Optionally, when the input power increases to the first threshold, the first control signal output by the voltage hysteresis comparator changes from low to high; at this time, the second control signal output by the ladder logic control circuit changes from high to low; the third control signal changes from low to high, and after a set delay time, the third control signal changes back to low.

[0038] Optionally, when the input power decreases to the second threshold, the first control signal output by the voltage hysteresis comparator changes from high to low; at this time, the third control signal output by the ladder logic control circuit changes from low to high, and after a set delay time, the third control signal changes to low, while the second control signal changes from low to high.

[0039] Optionally, when the input power increases to the first threshold, the first bias voltage output by the bias power supply circuit decreases and drops to zero after a set delay time.

[0040] When the input power decreases to the second threshold, the first bias voltage output by the bias power supply circuit increases, and after a set delay time, it increases to a preset value.

[0041] Optionally, when the input power increases to the first threshold, the gain of the power amplifier module decreases and drops to zero after a set delay time.

[0042] When the input power decreases to the second threshold, the gain of the power amplifier module increases, and after a set delay time, it increases to a preset value.

[0043] Optionally, when the input power increases to the first threshold, the output power of the power amplifier module decreases and drops to zero after a set delay time;

[0044] When the input power decreases to the second threshold, the output power of the power amplifier module increases, and after a set delay time, it increases to a preset value.

[0045] According to a fifth aspect of the present invention, an electronic device is provided, which includes the power amplifier module described above.

[0046] Compared with existing technologies, this invention achieves precise bias control of the RF power amplifier unit through the coordinated operation of the power detection circuit and the stepped logic control circuit in the controller unit. When the input power changes significantly, such as rising to a preset first threshold or falling to a second threshold, the controller unit can generate a corresponding control signal to adjust the bias voltage in a stepped manner. This allows the gain and output power of the power amplifier module to change smoothly, avoiding the risk of device damage caused by sudden power changes. This stepped protection mechanism not only improves the reliability of the power amplifier module under extreme conditions but also helps extend the service life of the equipment and maintain the stability of communication quality. Furthermore, the circuit design of this invention is ingenious and reasonable, with low cost, and is suitable for electronic devices using various communication standards, possessing broad application prospects and market potential. Attached Figure Description

[0047] Figure 1 is a structural block diagram of a power amplifier module provided in an embodiment of the present invention;

[0048] Figure 2 is a timing diagram of each functional unit in the power amplifier module in an embodiment of the present invention;

[0049] Figure 3 is a circuit diagram of the power detection circuit in an embodiment of the present invention;

[0050] Figure 4 is a circuit diagram of the voltage hysteresis comparator in an embodiment of the present invention;

[0051] Figure 5 is a schematic diagram of the first control signal output by the voltage hysteresis comparator in an embodiment of the present invention;

[0052] Figure 6 is a circuit diagram of the ladder logic control circuit in an embodiment of the present invention;

[0053] Figure 7 is a circuit diagram of the bias power supply circuit in an embodiment of the present invention;

[0054] Figure 8 is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0055] The technical content of the present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0056] As shown in Figure 1, the power amplifier module provided in this embodiment of the invention includes at least a controller unit 100, an RF power amplifier unit 200, and a filter unit 300. The RF signal input terminal RFIN is connected to the input terminals of both the controller unit 100 and the RF power amplifier unit 200. The output terminal of the controller unit 100 is connected to the bias terminal of the RF power amplifier unit 200. The output terminal of the RF power amplifier unit 200 is connected to the input terminal of the filter unit 300. The output terminal of the filter unit 300 is connected to the RF signal output terminal RFOUT.

[0057] When the input power of the radio frequency signal increases to the first threshold or decreases to the second threshold, the controller unit 100 generates corresponding first control signal, second control signal and third control signal to control the first bias voltage output by the controller unit 100 to decrease or increase in a stepwise manner, thereby causing the gain and output power of the power amplifier module to decrease or increase in a stepwise manner.

[0058] The controller unit 100 is used to provide a bias voltage to the RF power amplifier unit 200; the controller unit 100 includes a bandgap reference circuit, a voltage / current bias generation circuit, a power detection circuit, a voltage hysteresis comparator, a ladder logic control circuit, and a bias power supply circuit (VBIAS LDO). Specifically, the first output terminal of the bandgap reference circuit is connected to the input terminal of the voltage / current bias generation circuit, and the second output terminal is connected to the first input terminal of the bias power supply circuit; the first output terminal of the voltage / current bias generation circuit is connected to the bias terminal of the power detection circuit, and the second and third output terminals are respectively connected to the reference voltage terminal and the bias terminal of the voltage hysteresis comparator; the input terminal of the power detection circuit (i.e., the input terminal of the controller unit 100) is connected to the RF signal input terminal RFIN, and the output terminal is connected to the input terminal of the voltage hysteresis comparator; the output terminal of the voltage hysteresis comparator is connected to the input terminal of the ladder logic control circuit, the output terminal of the ladder logic control circuit is connected to the second input terminal of the bias power supply circuit, and the output terminal of the bias power supply circuit (i.e., the output terminal of the controller unit 100) is connected to the bias terminal of the RF power amplifier unit 200.

[0059] The bandgap reference circuit is used to generate and output the first reference voltage VBG1 and the second reference voltage VBG2, which provide reference voltages for the voltage / current bias generation circuit and the bias power supply circuit, respectively.

[0060] The voltage / current bias generation circuit is used to generate and output a second bias voltage VG to the power detection circuit, and to generate and output a reference voltage VREF and a bias current IB2 to the voltage hysteresis comparator.

[0061] The power detection circuit is used to detect the power of the input radio frequency signal. After conversion, it generates a detection voltage VDET (in V) that has a logarithmic linear relationship with the input power PIN (in dBm) and outputs it to the voltage hysteresis comparator.

[0062] The voltage hysteresis comparator compares the detected voltage VDET with the reference voltage VREF to generate a first control signal ODP_EN, which is then output to the ladder logic control circuit. When the input power PIN increases and reaches the first threshold Pth1, the first control signal ODP_EN is high; when the input power PIN decreases to the second threshold Pth2, the first control signal ODP_EN is low; wherein the first threshold Pth1 is greater than the second threshold Pth2. The magnitude of the reference voltage VREF can be set according to the required first threshold Pth1. The hysteresis function of the voltage hysteresis comparator allows the set first threshold Pth1 to be slightly greater than the second threshold Pth2, giving the voltage comparator a certain hysteresis width to avoid repeated switching of the protection mechanism due to fluctuations in input power.

[0063] The ladder logic control circuit generates a second control signal HPM_EN and a third control signal LPM_EN_DEL based on the first control signal ODP_EN through logical combination, and outputs them to the bias power supply circuit. The third control signal LPM_EN_DEL is a delayed automatic switching signal.

[0064] The bias power supply circuit generates a first bias voltage VBIAS based on the second control signal HPM_EN and the third control signal LPM_EN_DEL, and outputs it to the RF power amplifier unit 200 to provide it with a bias voltage. The magnitude of the first bias voltage VBIAS determines the DC operating point of the power amplifier circuit and the gain of the power amplifier module, and thus determines the output power POUT. In terms of timing, when the power amplifier module enters or exits the protection mechanism, the bias power supply circuit generates a first bias voltage VBIAS that decreases or increases in a stepped manner according to the control of the second control signal HPM_EN and the third control signal LPM_EN_DEL, thereby controlling the gain and output power of the power amplifier module to decrease or increase in a stepped manner in stages.

[0065] The radio frequency power amplifier unit 200 is used to amplify the radio frequency signal and output the amplified radio frequency signal to the filter unit 300. The radio frequency power amplifier unit 200 includes a power amplifier circuit and a bias circuit. The input terminal of the power amplifier circuit is connected to the radio frequency signal input terminal RFIN, the output terminal is connected to the input terminal of the filter unit 300, and the bias terminal is connected to the output terminal of the bias circuit. The input terminal of the bias circuit is connected to the output terminal of the controller unit 100.

[0066] The filter unit 300 is used to filter the amplified radio frequency signal and output the radio frequency signal of the required specific frequency band. The filter unit 300 includes filters for each frequency band. Its input terminal is connected to the output terminal of the radio frequency power amplifier unit 200, and its output terminal is connected to the radio frequency signal output terminal RFOUT.

[0067] The functional circuits included in the controller unit 100 can be fabricated on one or more control chips, and the functional circuits included in the RF power amplifier unit 200 can also be fabricated on one or more amplifier chips. The timing diagram of each functional unit in the power amplifier module is shown in Figure 2. The circuit structure and working principle of each major functional unit are explained in detail below with reference to the timing diagram.

[0068] In one embodiment of the present invention, as shown in FIG3, the power detection circuit includes a first NMOS transistor M1, a second NMOS transistor M2, a first PMOS transistor M3, a second PMOS transistor M4, a first NPN transistor Q1 and a first operational amplifier A1, as well as a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6 and a seventh resistor R7, and a first capacitor C1, a second capacitor C2 and a third capacitor C3. In this circuit, the RF signal input terminal RFIN is connected to the first capacitor C1. The other end of the first capacitor C1 is connected to the third resistor R3 and the gate of the first NMOS transistor M1. The source of the first NMOS transistor M1 and the source of the second NMOS transistor M2 are both grounded. The gate of the second NMOS transistor M2 is connected to the other end of the third resistor R3, the first resistor R1, and the second resistor R2 through the fourth resistor R4. The other end of the first resistor R1 serves as a bias terminal and is connected to the first output terminal of the voltage / current bias generation circuit. The other end of the second resistor R2 is grounded. The two ends of the second capacitor C2 are connected to the source and drain of the first NMOS transistor M1, respectively. The two ends of the third capacitor C3 are connected to the source and drain of the second NMOS transistor M2, respectively. The drain of the first NMOS transistor M1 is connected to the power supply through the fifth resistor R5. The voltage terminal is connected, and it is also connected to the inverting input terminal of the first operational amplifier A1 and the drain of the second PMOS transistor M4; the drain of the second NMOS transistor M2 is connected to the power supply voltage terminal through the sixth resistor R6, and it is also connected to the non-inverting input terminal of the first operational amplifier A1; the output terminal of the first operational amplifier A1 is connected to the base of the first NPN transistor Q1 as the output terminal of the power detection circuit, and it is also connected to the input terminal of the voltage hysteresis comparator; the emitter of the first NPN transistor Q1 is grounded through the seventh resistor R7, the collector of the first NPN transistor Q1 is connected to the drain of the first PMOS transistor M3, the gate of the first PMOS transistor M3 is connected to the drain and then to the gate of the second PMOS transistor M4, and the sources of the first PMOS transistor M3 and the second PMOS transistor M4 are both connected to the power supply voltage terminal.

[0069] In the power detection circuit, the first NMOS transistor M1 and the second NMOS transistor M2, the third resistor R3 and the fourth resistor R4, the second capacitor C2 and the third capacitor C3, the fifth resistor R5 and the sixth resistor R6 are symmetrically arranged and have the same electrical parameters. The first capacitor C1 is a DC blocking capacitor, and the second capacitor C2 is a filter capacitor. The input power PIN of the RF signal is coupled to the gate of the first NMOS transistor M1 through the first capacitor C1. The second bias voltage VG provided by the voltage / current bias generation circuit provides a DC static operating point for the first NMOS transistor M1 and the second NMOS transistor M2 through the voltage division of the first resistor R1 and the second resistor R2, so that the first NMOS transistor M1 and the second NMOS transistor M2 operate in the saturation region, and their current and voltage satisfy the square law characteristic. The third resistor R3 and the fourth resistor R4 are used to isolate the gates of the first NMOS transistor M1 and the second NMOS transistor M2 to prevent the RF signal coupled to the gate of the first NMOS transistor M1 from affecting the second NMOS transistor M2. The fifth resistor R5 and the sixth resistor R6 serve as the loads of the first NMOS transistor M1 and the second NMOS transistor M2, respectively. The first operational amplifier A1 acts as a bias amplifier. When the input power PIN changes, a corresponding current / voltage offset is generated at the inverting input of the first operational amplifier A1, resulting in a corresponding detection voltage VDET at its output. Simultaneously, the first NPN transistor Q1 converts the change in the detection voltage VDET into a current signal according to an exponential law. This current signal is mirrored as a feedback current IFB through a current mirror structure composed of the first PMOS transistor M3 and the second PMOS transistor M4, and fed back to the inverting input of the first operational amplifier A1. The seventh resistor R7 is used to adjust the DC operating point of the first NPN transistor Q1, ensuring that it operates in the amplification region within the range of input power of interest and satisfies the exponential law characteristics of current and voltage.

[0070] In the power detection circuit, different input power PINs generate different current / voltage offsets at the inverting input of the first operational amplifier A1. Different current / voltage offsets generate different detection voltages VDET, and different detection voltages VDET generate different feedback currents IFB. Since the input power PIN and the current / voltage offset satisfy a square law relationship, while the detection voltage VDET and the feedback current IFB satisfy an exponential law relationship, when the current / voltage offset and the feedback current IFB act together at the inverting input of the first operational amplifier A1, the output detection voltage VDET and the input power PIN exhibit a logarithmic linear relationship.

[0071] In one embodiment of the present invention, as shown in FIG4, the voltage hysteresis comparator circuit includes PMOS transistors 403-406, 411-416, NMOS transistors 401, 402, 407, 408, 409, 410 and inverter 417. The output terminal of the power detection circuit (i.e., the detection voltage VDET signal terminal) is connected to the gates of PMOS transistors 414 and 415 (i.e., the input terminals of the voltage hysteresis comparator). The second output terminal of the voltage / current bias generation circuit (i.e., the reference voltage VREF signal terminal) is connected to the gates of PMOS transistors 411 and 412 (i.e., the reference voltage terminal of the voltage hysteresis comparator). The third output terminal of the voltage / current bias generation circuit (i.e., the bias current IB2 signal terminal) is connected to the drain of NMOS transistor 401 (i.e., the bias terminal of the voltage hysteresis comparator). The drain of PMOS transistor 406, the gate of PMOS transistor 416, and the drain of NMOS transistor 410 are interconnected and serve as the output terminal of the voltage hysteresis comparator, which is connected to the input terminal of the ladder logic control circuit and also connected to the inverter 417.

[0072] The first control signal ODP_EN output by the voltage hysteresis comparator is inverted by inverter 417 to obtain the inverted signal ODP_ENB. As shown in Figure 5, the voltage corresponding to the first threshold Pth1 is the first voltage V1, and the voltage corresponding to the second threshold Pth2 is the second voltage V2, with the first voltage V1 > the second voltage V2. When the detected voltage VDET increases from a low voltage until it reaches the first voltage V1, PMOS transistors 413 and 412 are in the off state, and PMOS transistors 416 and 415 are in the on state. The first control signal ODP_EN output by the voltage hysteresis comparator remains at a low level, and the inverted signal ODP_ENB is at a high level. When the detected voltage VDET decreases from a high voltage until it reaches the second voltage V2, PMOS transistors 413 and 412 are in the on state, and PMOS transistors 416 and 415 are in the off state. The first control signal ODP_EN output by the voltage hysteresis comparator remains at a high level, and the inverted signal ODP_ENB is at a low level. Therefore, the number of input transistors corresponding to the rise and fall of the detection voltage VDET is different, which makes the switching threshold of the voltage comparator different, thus producing a hysteresis effect. Furthermore, the hysteresis width can be changed by adjusting the size of PMOS transistors 411, 412, 414, and 415 to avoid repeated switching of the protection mechanism due to fluctuations in input power.

[0073] In one embodiment of the present invention, as shown in FIG6, the ladder logic control circuit includes a first inverter 501, a second inverter 503, a third inverter 504, a fourth inverter 506, a fifth inverter 507, a sixth inverter 508, a seventh inverter 509, and an eighth inverter 512, as well as a first AND gate 510, a second AND gate 513, and a first OR gate 511, a filter module 502, and a delay module 505. The output terminal of the voltage hysteresis comparator (i.e., the first control signal ODP_EN terminal) is connected to the input terminal of the filter module 502 through the first inverter 501. The first output terminal of the filter module 502 is connected to the input terminal of the delay module 505 sequentially through the second inverter 503 and the third inverter 504. The output terminal of the delay module 505 is connected to the first input terminal of the first AND gate 510 sequentially through the fourth inverter 506 and the fifth inverter 507, and is also connected to the first input terminal of the first OR gate 511. The second output terminal of 502 is connected to the second input terminal of the first AND gate 510 and the second input terminal of the first OR gate 511 through the sixth inverter 508 and the seventh inverter 509 respectively; the output terminal of the first AND gate 510 is connected to the first output terminal of the ladder logic control circuit, and is also connected to the first input terminal of the second AND gate 513 through the eighth inverter 512; the output terminal of the first OR gate 511 is connected to the second input terminal of the second AND gate 513; and the output terminal of the second AND gate 513 is the second output terminal of the ladder logic control circuit.

[0074] In the ladder logic control circuit, the first control signal ODP_EN generates an inverted signal ODP_ENB through the first inverter 501. The filter module 502 is used to filter out short-term glitches or pulses in the inverted signal ODP_ENB to avoid false triggering of the protection mechanism due to short-term jitter of the input power PIN. The delay module 505 uses its generated delay time t to achieve automatic delay switching of the third control signal LPM_EN_DEL. That is, the delay time t determines the duration for which the first bias voltage VBIAS output by the bias power supply circuit remains at the lower voltage VLPM when it changes. Both the filter module 502 and the delay module 505 can be constructed using RC circuits.

[0075] Referring to the timing diagram shown in Figure 2, before the input power PIN increases but before reaching the first threshold Pth1, the first control signal ODP_EN output by the voltage hysteresis comparator is low, and the inverted signal ODP_ENB is high. After passing through the filter module 502, the inverted signal ODP_ENB, on the one hand, passes through the second inverter 503 and the third inverter 504, the delay module 505, and the fourth inverter 506 and the fifth inverter 507, making the first input terminal of the first AND gate 510 high and the first input terminal of the first OR gate 511 high; on the other hand, it passes through the second inverter 503 and the third inverter 504, the delay module 505, the fourth inverter 506, and the fifth inverter 507, making the first input terminal of the first AND gate 510 high and the first input terminal of the first OR gate 511 high. After passing through the sixth inverter 508 and the seventh inverter 509, the second input of the first AND gate 510 and the second input of the first OR gate 511 are both set to a high level. Therefore, the second control signal HPM_EN output by the first AND gate 510 is high. After passing through the eighth inverter 512, the second control signal HPM_EN sets the first input of the second AND gate 513 to a low level. The first OR gate 511 outputs a high level, meaning the second input of the second AND gate 513 is high. Therefore, the third control signal LPM_EN_DEL output by the second AND gate 513 is low.

[0076] When the input power PIN increases to the first threshold Pth1, the first control signal ODP_EN output by the voltage hysteresis comparator changes from low to high, and the inverted signal ODP_ENB becomes low. After passing through the filter module 502, the inverted signal ODP_ENB first passes through the sixth inverter 508 and the seventh inverter 509, making the second input of the first AND gate 510 and the second input of the first OR gate 511 low. Therefore, the second control signal HPM_EN output by the first AND gate 510 changes from high to low. At the same time, the second control signal HPM_EN passes through the eighth inverter 512, making the first input of the second AND gate 513 high. Therefore, the third control signal LPM_EN_DEL output by the second AND gate 513 changes from low to high. After a delay time t, the inverted signal ODP_ENB passes through the second inverter 503, the third inverter 504, the delay module 505, the fourth inverter 506, and the fifth inverter 507, causing the first input terminal of the first AND gate 510 to go low and the first input terminal of the first OR gate 511 to go low. At this time, the second control signal HPM_EN output by the first AND gate 510 remains low, and the output of the first OR gate 511 goes low. Therefore, the third control signal LPM_EN_DEL output by the second AND gate 513 goes low.

[0077] As can be seen from the above analysis, when the input power PIN increases to the first threshold Pth1, the third control signal LPM_EN_DEL changes from the original low level to the high level, maintains a delay time t, and then automatically changes back to the low level. In other words, the third control signal LPM_EN_DEL is a delayed automatic switching signal, and the delay time t it maintains during the transition determines the duration for which the first bias voltage VBIAS output by the bias power supply circuit remains at the lower voltage VLPM.

[0078] When the input power PIN decreases to the second threshold Pth2, the first control signal output by the voltage hysteresis comparator changes from high to low. At this time, the third control signal output by the ladder logic control circuit changes from low to high. After a set delay, the third control signal changes back to low, and simultaneously, the second control signal changes from low to high. The specific changes of each component in the ladder logic control circuit are similar to the above process, and will not be elaborated further here.

[0079] In one embodiment of the present invention, as shown in FIG7, the bias power supply circuit includes an error amplifier 603, a power transistor 604, a first transmission gate 601 and a second transmission gate 602, and a tenth resistor R10, an eleventh resistor R11 and a twelfth resistor R12; wherein, the non-inverting input terminal of the error amplifier 603 (i.e., the first input terminal of the bias power supply circuit) is connected to the second output terminal of the bandgap reference circuit, the output terminal of the error amplifier 603 is connected to the gate of the power transistor 604, the source of the power transistor 604 and the power supply terminal of the error amplifier 603 are both connected to the power supply voltage terminal, and the drain of the power transistor 604 serves as the output terminal of the bias power supply circuit and is connected to the tenth resistor R10. The tenth resistor R10, eleventh resistor R11, and twelfth resistor R12 are connected in series, with the other end of the tenth resistor R12 grounded. The connection point between the tenth and eleventh resistors R10 and R11 is connected to the input of the second transmission gate 602, and the connection point between the eleventh and twelfth resistors R11 and R12 is connected to the input of the first transmission gate 601. The outputs of both the first and second transmission gates 601 and 602 are connected to the inverting input of the error amplifier 603. The control terminal of the first transmission gate 601 is connected to the first output of the ladder logic control circuit, and the control terminal of the second transmission gate 602 is connected to the second output of the ladder logic control circuit. The tenth resistors R10, R11, and R12 constitute a resistive feedback network.

[0080] Under normal operating conditions, the ladder logic control circuit outputs a high level for the second control signal HPM_EN and a low level for the third control signal LPM_EN_DEL. Therefore, the first transmission gate 601 is turned on, the second transmission gate 602 is turned off, and the feedback voltage VBK input to the error amplifier 603 is the voltage across the twelfth resistor R12. At this time, the first bias voltage VBIAS output by the bias power supply circuit is the higher voltage VHPM.

[0081] When the input power PIN increases to the first threshold Pth1, the ladder logic control circuit outputs the second control signal HPM_EN, which changes from high to low. Simultaneously, the third control signal LPM_EN_DEL changes from low to high. Therefore, the first transmission gate 601 is turned off, and the second transmission gate 602 is turned on. The feedback voltage VBK input to the error amplifier 603 is the voltage across the tenth resistor R11 and the tenth resistor R12. As the feedback voltage VBK increases, the first bias voltage VBIAS output by the bias power supply circuit decreases to a lower voltage VLPM. After a delay time t, the third control signal LPM_EN_DEL changes from high to low, and the second transmission gate 602 also turns off. At this time, the feedback voltage VBK input to the error amplifier 603 is zero. Therefore, the first bias voltage VBIAS output by the bias power supply circuit drops to zero volts.

[0082] As can be seen from the above analysis, when the input power PIN increases to the first threshold Pth1, the first bias voltage VBIAS output by the bias power supply circuit decreases in a step-like manner, that is, from a higher voltage VHPM to a lower voltage VLPM, and then decreases to zero voltage after a delay time t. The first bias voltage VBIAS is provided to the RF power amplifier unit 200, causing the operating state of the RF power amplifier unit 200 to change accordingly. When the input power PIN decreases to the second threshold Pth2, the change in the bias power supply circuit is similar to the above process, and will not be described in detail here.

[0083] It should be noted that the values ​​of the lower voltage VLPM and the higher voltage VHPM of the first bias voltage VBIAS output by the bias power supply circuit can be adjusted by changing the values ​​of the series resistors in the resistor feedback network according to specific needs.

[0084] In the power amplifier module provided in this embodiment of the invention, the power detection circuit detects the input power PIN of the input radio frequency signal in real time. Referring to the timing comparison diagram of each functional unit shown in Figure 2, the working process and working principle of the overall stepped protection mechanism of the power amplifier module when the input power PIN changes are described in detail below.

[0085] When the input power PIN of the RF signal increases to the first threshold Pth1, the detection voltage VDET output by the power detection circuit is greater than or equal to the reference voltage VREF. The power amplifier module triggers the stepped protection mechanism. At this time, the first control signal ODP_EN output by the voltage hysteresis comparator changes from low to high; the second control signal HPM_EN output by the stepped logic control circuit changes from high to low; simultaneously, the third control signal LPM_EN_DEL changes from low to high and remains high for the set delay before changing back to low. The bias power supply circuit controls the resistor feedback network coefficient according to the second control signal HPM_EN and the third control signal LPM_EN_DEL, ensuring that the bias... The first bias voltage VBIAS output by the power supply circuit decreases in a step-like manner, from a higher voltage VHPM to a lower voltage VLPM, and then decreases to zero voltage after a set delay time. The RF power amplifier unit establishes a corresponding DC operating point according to the change of the first bias voltage VBIAS, thereby causing the gain of the power amplifier module to decrease in a step-like manner, from a higher gain H_Gain to a lower gain L_Gain, and then decreases to zero gain after a set delay time. The output power POUT decreases in a step-like manner, from a higher power H_Power to a lower power L_Power, and then decreases to zero power after a set delay time.

[0086] When the input power PIN decreases to the second threshold Pth2, the detection voltage VDET output by the power detection circuit is less than the reference voltage VREF. The power amplifier module then exits the stepped protection mechanism. At this time, the first control signal ODP_EN output by the voltage hysteresis comparator changes from high to low; the third control signal LPM_EN_DEL output by the stepped logic control circuit changes from low to high and remains there for a set delay before changing back to low. Simultaneously, the second control signal HPM_EN changes from low to high. The bias power supply circuit controls the resistor feedback network coefficient according to the second control signal HPM_EN and the third control signal LPM_EN_DEL, ensuring that the bias... The first bias voltage VBIAS output by the power supply circuit increases in a step-like manner, that is, from zero voltage to a lower voltage VLPM, and after a set delay time, it increases to a preset higher voltage VHPM. The RF power amplifier unit establishes a corresponding DC operating point according to the change of the first bias voltage VBIAS, so that the gain Gain of the power amplifier module increases in a step-like manner, that is, from zero gain to a lower gain L_Gain, and after a set delay time, it increases to a higher gain H_Gain. The output power POUT increases in a step-like manner, that is, from zero power to a lower power L_Power, and after a set delay time, it increases to a higher power H_Power.

[0087] By employing the aforementioned stepped protection mechanism for power protection, the power amplifier module can avoid the phenomenon of the power amplifier or filter being burned out and failing when the power amplifier suddenly drops from high power to low power or zero power, or from zero power or low power to high power, thereby improving the operational reliability of the power amplifier module.

[0088] This invention further provides an electronic device including the aforementioned power amplifier module, which can serve as an important component of a communication system. The electronic device referred to herein is a computer device that can be used in a mobile environment and supports multiple communication standards such as GSM, EDGE, CDMA, TD-SCDMA, WCDMA, TDD-LTE, FDD-LTE, and NR, including mobile phones, laptops, tablets, and in-vehicle computers. Furthermore, the technical solution provided by this invention is also applicable to other applications of radio frequency integrated circuits, such as communication base stations and intelligent connected vehicles.

[0089] As shown in Figure 8, this electronic device includes at least a processor, a memory, and a communication component. It may further include sensor components, a power supply component, a multimedia component, and input / output interfaces, depending on actual needs. The memory, communication component, sensor component, power supply component, multimedia component, and input / output interface are all connected to the processor. The memory can be a static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, etc. The processor can be a central processing unit (CPU), graphics processing unit (GPU), field-programmable gate array (FPGA), application-specific integrated circuit (ASIC), digital signal processing (DSP) chip, etc. Other communication components, sensor components, power supply components, multimedia components, etc., can be implemented using general-purpose components and will not be specifically described here.

[0090] In summary, compared with existing technologies, this invention achieves precise bias control of the RF power amplifier unit through the coordinated operation of the power detection circuit and the stepped logic control circuit in the controller unit. When the input power changes significantly, such as rising to a preset first threshold or falling to a second threshold, the controller unit can generate corresponding control signals to adjust the bias voltage in a stepped manner. This allows the gain and output power of the power amplifier module to change smoothly, avoiding the risk of device damage due to sudden power changes. This stepped protection mechanism not only improves the reliability of the power amplifier module under extreme conditions but also helps extend the service life of the equipment and maintain the stability of communication quality. Furthermore, the circuit design of this invention is ingenious and reasonable, with low cost, and is suitable for electronic devices using various communication standards, possessing broad application prospects and market potential.

[0091] It should be noted that the above embodiments of multiple functional circuits are merely illustrative examples, and other circuit technical solutions can also be used to achieve the same function, all of which are within the protection scope of this invention.

[0092] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0093] The circuit for power protection and the corresponding power amplifier module and electronic equipment provided by this invention have been described in detail above. Any obvious modifications made by those skilled in the art without departing from the essence of this invention will constitute an infringement of the patent rights of this invention and will incur corresponding legal liability.

Claims

1. A power detection circuit for use in a power amplifier module, characterized in that, It includes a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, a second PMOS transistor, a first NPN transistor, and a first operational amplifier; as well as a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, and a seventh resistor; and a first capacitor, a second capacitor, and a third capacitor; wherein, The RF signal input terminal is connected to the first terminal of the first capacitor. The second terminal of the first capacitor is connected to the first terminal of the third resistor and the gate of the first NMOS transistor. The source of the first NMOS transistor and the source of the second NMOS transistor are both grounded. The gate of the second NMOS transistor is connected to the second terminal of the third resistor, the first terminal of the first resistor, and the first terminal of the second resistor through the fourth resistor. The second terminal of the first resistor serves as a bias terminal and is connected to the first output terminal of the voltage / current bias generation circuit. The second terminal of the second resistor is grounded. The two terminals of the second capacitor are connected to the source and drain of the first NMOS transistor. The two terminals of the third capacitor are connected to the source and drain of the second NMOS transistor. The drain of the first NMOS transistor is connected to the power supply through the fifth resistor. The voltage terminal is connected, and it is also connected to the inverting input terminal of the first operational amplifier and the drain of the second PMOS transistor; the drain of the second NMOS transistor is connected to the power supply voltage terminal through the sixth resistor, and it is also connected to the non-inverting input terminal of the first operational amplifier; the output terminal of the first operational amplifier serves as the output terminal of the power detection circuit and is connected to the base of the first NPN transistor, and it is also connected to the input terminal of the voltage hysteresis comparator; the emitter of the first NPN transistor is grounded through the seventh resistor, the collector of the first NPN transistor is connected to the drain of the first PMOS transistor, the gate of the first PMOS transistor is connected to the drain and then to the gate of the second PMOS transistor, and the sources of both the first PMOS transistor and the second PMOS transistor are connected to the power supply voltage terminal.

2. The power detection circuit as described in claim 1, characterized in that: The first NMOS transistor and the second NMOS transistor, the third resistor and the fourth resistor, the second capacitor and the third capacitor, the fifth resistor and the sixth resistor are symmetrically arranged and have the same electrical parameters.

3. The power detection circuit as described in claim 2, characterized in that: The first NMOS transistor and the second NMOS transistor operate in the saturation region, and their current and voltage satisfy the square law characteristic. The first NPN transistor operates in the amplification region, and its current and voltage satisfy the exponential law characteristic.

4. The power detection circuit as described in claim 3, characterized in that: The input power of the radio frequency signal generates a current / voltage offset at the inverting input terminal of the first operational amplifier. When the current / voltage offset and the feedback current act together at the inverting input terminal of the first operational amplifier, the output detection voltage has a logarithmic linear relationship with the input power.

5. A ladder logic control circuit for a power amplifier module, characterized in that, It includes a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a seventh inverter, and an eighth inverter, as well as a first AND gate, a second AND gate, and a first OR gate, and a filtering module and a delay module; wherein, The first output terminal of the filtering module is connected to the input terminal of the delay module in sequence through the second inverter and the third inverter. The output terminal of the delay module is connected to the first input terminal of the first AND gate in sequence through the fourth inverter and the fifth inverter, and is also connected to the first input terminal of the first OR gate. The second output terminal of the filtering module is connected sequentially to the second input terminal of the first AND gate and the second input terminal of the first OR gate through the sixth inverter and the seventh inverter, respectively; the output terminal of the first AND gate is connected to the first output terminal of the ladder logic control circuit, and is also connected to the first input terminal of the second AND gate through the eighth inverter; the output terminal of the first OR gate is connected to the second input terminal of the second AND gate; and the output terminal of the second AND gate is the second output terminal of the ladder logic control circuit.

6. The ladder logic control circuit as described in claim 5, characterized in that: The filtering module is used to filter out glitches or pulses in the inverse signal of the first control signal, so as to avoid false triggering of the protection mechanism due to short-term fluctuations in input power. The delay module is used to generate a delay time to ensure that the first bias voltage is maintained at a lower voltage level.

7. A power amplifier module, characterized in that, It includes a controller unit, an RF power amplifier unit, and a filter unit; among which, The radio frequency signal input terminal is connected to the input terminal of the controller unit and the input terminal of the radio frequency power amplifier unit, respectively. The output terminal of the controller unit is connected to the bias of the radio frequency power amplifier unit. The output terminal of the radio frequency power amplifier unit is connected to the input terminal of the filter unit. The output terminal of the filter unit is connected to the radio frequency signal output terminal. The controller unit includes the power detection circuit according to any one of claims 1 to 4 or the ladder logic control circuit according to any one of claims 5 to 6, for providing a bias voltage to the radio frequency power amplifier unit.

8. A power amplifier module, characterized in that, It includes a controller unit, an RF power amplifier unit, and a filter unit; among which, The radio frequency signal input terminal is connected to the input terminal of the controller unit and the input terminal of the radio frequency power amplifier unit, respectively. The output terminal of the controller unit is connected to the bias of the radio frequency power amplifier unit. The output terminal of the radio frequency power amplifier unit is connected to the input terminal of the filter unit. The output terminal of the filter unit is connected to the radio frequency signal output terminal. The controller unit is used to provide a bias voltage to the RF power amplifier unit, and includes a bandgap reference circuit, a voltage / current bias generation circuit, a voltage hysteresis comparator, a bias power supply circuit, a power detection circuit as described in any one of claims 1 to 4, and a ladder logic control circuit as described in any one of claims 5 to 6; wherein... The bandgap reference circuit is used to generate and output a first reference voltage and a second reference voltage, which respectively provide reference voltages to the voltage / current bias generation circuit and the bias power supply circuit; The voltage / current bias generation circuit is used to generate and output a second bias voltage to the power detection circuit, and to generate and output a reference voltage and bias current to the voltage hysteresis comparator. The power detection circuit is used to detect the power of the input radio frequency signal, convert it to generate a detection voltage, and output it to the voltage hysteresis comparator. The voltage hysteresis comparator is used to compare the detected voltage with the reference voltage to generate a first control signal, and output it to the ladder logic control circuit. The ladder logic control circuit is used to generate a second control signal and a third control signal after logical combination of the first control signal, and output them to the bias power supply circuit. The bias power supply circuit is used to generate the first bias voltage according to the second control signal and the third control signal, and output it to the RF power amplifier unit to provide it with a bias voltage.

9. The power amplifier module as described in claim 8, characterized in that: The radio frequency power amplifier unit is used to amplify the radio frequency signal and output the amplified radio frequency signal to the filter unit; The filter unit is used to filter the amplified radio frequency signal and output a radio frequency signal in a specific frequency band.

10. The power amplifier module as described in claim 8, characterized in that: The first output terminal of the bandgap reference circuit is connected to the input terminal of the voltage / current bias generation circuit, and the second output terminal is connected to the first input terminal of the bias power supply circuit. The first output terminal of the voltage / current bias generation circuit is connected to the bias terminal of the power detection circuit, and the second and third output terminals are connected to the reference voltage terminal and the bias terminal of the voltage hysteresis comparator. The input terminal of the power detection circuit is connected to the RF signal input terminal, and the output terminal is connected to the input terminal of the voltage hysteresis comparator. The output terminal of the voltage hysteresis comparator is connected to the input terminal of the ladder logic control circuit and is connected to the input terminal of the filter module through a first inverter. The output terminal of the ladder logic control circuit is connected to the second input terminal of the bias power supply circuit, and the output terminal of the bias power supply circuit is connected to the bias terminal of the RF power amplifier unit.

11. The power amplifier module as described in claim 8, characterized in that: The bias power supply circuit includes an error amplifier, a power transistor, a first transmission gate, a second transmission gate, and a tenth, eleventh, and twelfth resistor. The non-inverting input of the error amplifier is connected to the second output of the bandgap reference circuit. The output of the error amplifier is connected to the gate of the power transistor. The source of the power transistor and the power supply terminal of the error amplifier are both connected to the power supply voltage terminal. The drain of the power transistor serves as the output of the bias power supply circuit and is connected to the first terminal of the tenth resistor. The tenth, eleventh, and twelfth resistors are connected in series. The second terminal of the tenth resistor is grounded. The connection point between the tenth and eleventh resistors is connected to the input of the second transmission gate. The connection point between the eleventh and twelfth resistors is connected to the input of the first transmission gate. The outputs of both the first and second transmission gates are connected to the inverting input of the error amplifier. The control terminal of the first transmission gate is connected to the first output of the ladder logic control circuit, and the control terminal of the second transmission gate is connected to the second output of the ladder logic control circuit.

12. The power amplifier module as described in claim 8, characterized in that: When the input power of the radio frequency signal increases to a first threshold or decreases to a second threshold, the controller unit generates a corresponding first control signal, a second control signal, and a third control signal to control the first bias voltage output by the controller unit to decrease or increase in a stepwise manner, thereby causing the gain and output power of the power amplifier module to decrease or increase in a stepwise manner; wherein, the first threshold is greater than the second threshold.

13. The power amplifier module as described in claim 12, characterized in that: When the input power increases to the first threshold, the first control signal output by the voltage hysteresis comparator changes from low to high; at this time, the second control signal output by the ladder logic control circuit changes from high to low; the third control signal changes from low to high, and after a set delay time, the third control signal changes back to low.

14. The power amplifier module as described in claim 12, characterized in that: When the input power decreases to the second threshold, the first control signal output by the voltage hysteresis comparator changes from high to low. At this time, the third control signal output by the ladder logic control circuit changes from low to high. After a set delay time, the third control signal changes to low, and at the same time, the second control signal changes from low to high.

15. The power amplifier module as described in claim 12, characterized in that: When the input power increases to the first threshold, the first bias voltage output by the bias power supply circuit decreases and drops to zero after a set delay time. When the input power decreases to the second threshold, the first bias voltage output by the bias power supply circuit increases, and after a set delay time, it increases to a preset value.

16. The power amplifier module as described in claim 12, characterized in that: When the input power increases to the first threshold, the gain of the power amplifier module decreases and drops to zero after a set delay time. When the input power decreases to the second threshold, the gain of the power amplifier module increases, and after a set delay time, it increases to a preset value.

17. The power amplifier module as described in claim 12, characterized in that: When the input power increases to the first threshold, the output power of the power amplifier module decreases and drops to zero after a set delay time. When the input power decreases to the second threshold, the output power of the power amplifier module increases, and after a set delay time, it increases to a preset value.

18. An electronic device, characterized in that, Includes the power amplifier module as described in claim 7 or any one of claims 8 to 17.

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