Server topology processing method, computer program product, device and medium

Abstract

Provided in the present application are a server topology processing method, a computer program product, a device and a medium. The method comprises: in response to a server system being started, a lower-layer dynamic detection unit generating board topology information of a server board where the lower-layer dynamic detection unit is located; in response to having detected that an upper-layer dynamic detection unit is connected thereto, the lower-layer dynamic detection unit uploading the board topology information to the upper-layer dynamic detection unit; in response to having received the uploaded board topology information, the upper-layer dynamic detection unit updating, on the basis of a preset rule, the board topology information matching the server board; and if the upper-layer dynamic detection unit is arranged in a server motherboard, the upper-layer dynamic detection unit stopping receiving board topology information uploaded by the lower-layer dynamic detection unit and saving board topology information of the latest version after a preset condition is met, such that basic input output system firmware adapts to the current server system. Thus, the difficulty of firmware adaptation is reduced.

Description

Server topology processing methods, computer program products, equipment and media

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411207990.6, filed on August 30, 2024, entitled "Server Topology Processing Method, Computer Program Product, Device and Media", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of server technology, and in particular to a server topology processing method, computer program product, device and medium. Background Technology

[0004] The general server design strategy is to design servers according to specifications. Although boards can be reused, the BIOS (Basic Input Output System) firmware needs to be adapted again, which results in long development time and a cumbersome verification process.

[0005] The common approach to server design involves redesigning the server system and then re-adapting the BIOS to the hardware topology. This approach requires informing the BIOS team of the server design information early in the design process. When designing multiple server systems simultaneously, the complexity of adaptation is reduced by unifying the common parts across each system. However, this method leads to excessively long design times and high manpower costs. Summary of the Invention

[0006] This application provides a server topology processing method, a computer program product, an apparatus, and a medium.

[0007] Firstly, this application provides a server topology processing method, the method comprising:

[0008] In response to the server system startup, the lower-level dynamic detection unit generates the board topology information of the server board where the lower-level dynamic detection unit is located, wherein the lower-level dynamic detection unit is configured based on the interface configuration information within the server board;

[0009] In response to detecting a connection to an upper-layer dynamic detection unit, the lower-layer dynamic detection unit transmits the board topology information to the upper-layer dynamic detection unit.

[0010] The upper-layer dynamic detection unit, in response to receiving the uploaded board topology information, updates the board topology information matching the server board according to preset rules; and

[0011] When the upper-layer dynamic detection unit is located inside the server motherboard, the upper-layer dynamic detection unit stops receiving the board topology information uploaded by the lower-layer dynamic detection unit after meeting preset conditions, and saves the latest version of the board topology information so that the basic input / output system firmware can be adapted to the current server system.

[0012] In some embodiments, the lower-layer dynamic detection unit generates board topology information of the server board where the lower-layer dynamic detection unit is located, including:

[0013] The lower-level dynamic detection unit collects the slot status and bandwidth status of the server board's slots, and sets the board level of the server board to 1; and

[0014] Based on preset protocol rules, the lower-layer dynamic detection unit generates server board topology information that conforms to the protocol rules by taking the board hierarchy, board code, board number, slot number, check code, and the collected slot status and bandwidth status of the server board.

[0015] In some embodiments, the lower-level motion detection unit communicates with the upper-level motion detection unit via clock signal lines and data signal lines.

[0016] Transmitting board topology information to the upper-layer dynamic detection unit includes:

[0017] The lower-level dynamic detection unit transmits the board topology information to the upper-level dynamic detection unit at a preset frequency via clock signal lines and data signal lines.

[0018] In some embodiments, in response to receiving uploaded board topology information, the upper-layer dynamic detection unit updates the board topology information matching the server board according to preset rules, including:

[0019] In response to receiving the uploaded board topology information, add the board hierarchy to the board topology information that matches the board on the server to generate transition board topology information;

[0020] The generated transition board topology information is merged with the uploaded board topology information. Based on the merged transition board topology information and the uploaded board topology information, the board topology information that matches the server board where the upper-layer dynamic detection unit is located is updated.

[0021] In some embodiments, the method includes a method for determining whether a preset condition is met:

[0022] In response to receiving the uploaded board topology information, the upper-layer dynamic detection unit compares the currently received board topology information with the previously received board topology information.

[0023] In response to determining that the currently received board topology information is the same as the previously received board topology information and defining the currently received board topology information as duplicate board topology information, the upper-layer dynamic detection unit obtains the maximum board level among multiple board levels contained in the currently received board topology information; and

[0024] The upper-layer dynamic detection unit determines whether the preset conditions are met based on the highest board level obtained and the number of times the currently received duplicate board topology information is repeated.

[0025] In some embodiments, the upper-layer dynamic detection unit determines whether a preset condition is met based on the acquired board hierarchy and the number of repetitions of the currently received duplicate board topology information, including:

[0026] The preset threshold for matching the highest board level obtained;

[0027] In response to determining that the number of repetitions of the currently received duplicate board topology information is greater than or equal to a preset threshold, the preset condition is determined to be satisfied; and

[0028] If the number of repetitions of the currently received duplicate board topology information is greater than or equal to a preset threshold, then the preset condition is determined not to be met.

[0029] In some embodiments, the method for configuring the lower-layer dynamic detection unit based on the configuration information of the interface within the server board includes:

[0030] Obtain the bandwidth specifications of the interfaces within the server board;

[0031] Obtain the connector specifications that implement the interface's connection functionality;

[0032] Based on the bandwidth specifications of the interface design and the connector specifications for implementing the interface's connection functions, determine the distribution of the dynamic detection units on the server board; and

[0033] Configure the lower-level dynamic detection units on the server board according to their distribution on the server board.

[0034] In some embodiments, the lower-layer dynamic detection unit includes two dynamic detection sub-units. The distribution of the dynamic detection units on the server board is determined based on the bandwidth specifications of the interface design and the connector specifications for implementing the interface's connection functions. This includes:

[0035] In response to determining that the interface bandwidth specification is x16 bandwidth and the connector specification is a first connector, the distribution of the lower-layer dynamic detection unit on the server board is determined to be a first distribution, wherein the first distribution is to set a lower-layer dynamic detection unit that matches the connector, and the lower-layer dynamic detection unit communicates with the slot provided by the server board to receive the slot's presence signal.

[0036] In response to the determination that the interface bandwidth specification is x16 bandwidth and the connector specification is two second connectors, the distribution of the lower-level dynamic detection units on the server board is determined to be a second distribution. This second distribution involves setting up two dynamic detection sub-units, each matched with a connector, and the dynamic detection sub-units communicating with the slots provided by the server board to receive the slot's presence signal.

[0037] In response to the determination that the interface bandwidth specification is x8 bandwidth and the connector specification is a second connector, the distribution of the lower-layer dynamic detection unit on the server board is determined to be the first distribution.

[0038] In some embodiments, determining the distribution of the lower-level dynamic detection units on the server board further includes:

[0039] In response to the determination that the connection function with the interface is realized through the gold fingers, the distribution of the lower-level dynamic detection unit on the server board is determined to be the third distribution situation;

[0040] The third distribution involves setting up a lower-level dynamic detection unit that matches the gold fingers, and the lower-level dynamic detection unit is connected to the slot provided by the server board to receive the slot's presence signal.

[0041] In some embodiments, the method further includes:

[0042] In response to the determination that a disk array card is included among multiple server boards in the server system, an additional dynamic detection unit is set separately in the server board above the disk array card;

[0043] The system receives board topology information generated by the underlying dynamic detection unit within the server board connected to the disk array card via an additional dynamic detection unit; and

[0044] The received board topology information is uploaded to the upper-layer dynamic detection unit in the server board above the disk array card through an additional dynamic detection unit.

[0045] In some embodiments, the method further includes:

[0046] The baseboard management controller reads the latest version of the board topology information stored in the upper-layer dynamic detection unit inside the server motherboard;

[0047] The baseboard management controller parses the board topology information to obtain the bandwidth status and corresponding board number of each server board; and

[0048] The baseboard management controller determines the cable connection status of the server board corresponding to the board number based on the obtained bandwidth status and board number.

[0049] In some embodiments, the baseboard management controller determines the cable connection status of the server board corresponding to the board code based on the acquired bandwidth status and board code, including:

[0050] Compare the bandwidth specifications supported by the server board corresponding to the board code with the obtained bandwidth status;

[0051] In response to the determination that the server board supports a bandwidth specification of x16 bandwidth and the obtained bandwidth status matching the server board is x8 bandwidth, it is determined that the cable connection status of the server board corresponding to the board code is abnormal; and

[0052] If it is determined that the bandwidth specification supported by the server board is x8 bandwidth and no bandwidth status matching the server board is obtained, then it is determined that the cable connection status of the server board corresponding to the board code is abnormal.

[0053] In some embodiments, the method includes:

[0054] The baseboard management controller, in response to detecting an abnormal cable connection status of the server board corresponding to the board code, generates a cable abnormality alarm to prompt the user to repair the abnormal cable; and / or,

[0055] The baseboard management controller generates a cable fault log in response to a detected abnormal cable connection status of the server board corresponding to the board code, so that users can view and repair the abnormal cable.

[0056] In some embodiments, the method further includes:

[0057] The baseboard management controller parses the latest version of the board topology information stored in the upper-layer dynamic detection unit within the server motherboard to obtain the server system topology; and

[0058] The substrate management controller displays the topology in the management interface for users to view.

[0059] In some embodiments, after the baseboard management controller reads the latest version of the board topology information stored in the upper-layer dynamic detection unit within the server motherboard, the method includes:

[0060] Verify the correctness of the board topology information stored in the two dynamic detection sub-units within the dynamic detection unit:

[0061] In response to the detection that there are differences in information other than checksum and bandwidth status in the board topology information stored by the two dynamic detection subunits, it is determined that the board topology information is incorrect and an anomaly alarm is generated to prompt the user to check the upper-layer dynamic detection unit; and

[0062] If the two dynamic detection subunits store different information in the board topology information other than the checksum and bandwidth status, then the board topology information is determined to be correct.

[0063] In some embodiments, the method further includes:

[0064] The basic input / output system acquires and parses the latest version of the board topology information stored in the upper-layer dynamic detection unit within the server motherboard to obtain the server system topology; and

[0065] The Basic Input / Output System (BIOS) adjusts its bandwidth settings to adapt to the current server system based on the bandwidth status of multiple server boards within the server system contained in the parsed board topology information.

[0066] In some embodiments, before the basic input / output system acquires and parses the latest version of the board topology information stored in the upper-layer dynamic detection unit within the server motherboard, the method includes:

[0067] Test the compatibility between the basic input / output system and the server boards included in the server system;

[0068] In response to determining that the Basic Input / Output System (PIS) is compatible with the server boards included in the server system, the operating status of the PIS is verified, including normal and abnormal states; and

[0069] In response to the Elementary Input / Output System (API) being in a normal operating state, the API is triggered to acquire and parse the latest version of the board topology information stored in the upper-layer dynamic detection unit within the server motherboard.

[0070] Secondly, this application provides a computer program product, which, when executed by one or more processors, implements the steps of the following method:

[0071] In response to the server system startup, the lower-level dynamic detection unit generates the board topology information of the server board where the lower-level dynamic detection unit is located, wherein the lower-level dynamic detection unit is configured based on the interface configuration information within the server board;

[0072] In response to detecting a connection to an upper-layer dynamic detection unit, the lower-layer dynamic detection unit transmits the board topology information to the upper-layer dynamic detection unit.

[0073] The upper-layer dynamic detection unit, in response to receiving the uploaded board topology information, updates the board topology information matching the server board according to preset rules; and

[0074] When the upper-layer dynamic detection unit is located inside the server motherboard, the upper-layer dynamic detection unit stops receiving the board topology information uploaded by the lower-layer dynamic detection unit after meeting preset conditions, and saves the latest version of the board topology information so that the basic input / output system firmware can be adapted to the current server system.

[0075] Thirdly, this application provides a server topology processing system, comprising:

[0076] The information generation module is used to respond to the server system startup. The lower-level dynamic detection unit generates the board topology information of the server board where the lower-level dynamic detection unit is located. The lower-level dynamic detection unit is configured based on the interface configuration information within the server board.

[0077] The information transmission module is used to transmit board topology information to the upper-layer dynamic detection unit in response to the detection that the upper-layer dynamic detection unit is connected.

[0078] The information processing module is used by the upper-layer dynamic detection unit to update the board topology information matching the server board according to preset rules in response to the received uploaded board topology information; and

[0079] The information processing module is also used to ensure that, when the upper-layer dynamic detection unit is located inside the server motherboard, the upper-layer dynamic detection unit stops receiving the board topology information uploaded by the lower-layer dynamic detection unit after meeting preset conditions and saves the latest version of the board topology information so that the basic input / output system firmware can be adapted to the current server system.

[0080] Fourthly, this application provides an electronic device, which includes:

[0081] One or more processors;

[0082] and memory associated with one or more processors, the memory being used to store program instructions, which, when read and executed by one or more processors, perform the following operations:

[0083] In response to the server system startup, the lower-level dynamic detection unit generates the board topology information of the server board where the lower-level dynamic detection unit is located, wherein the lower-level dynamic detection unit is configured based on the interface configuration information within the server board;

[0084] In response to detecting a connection to an upper-layer dynamic detection unit, the lower-layer dynamic detection unit transmits the board topology information to the upper-layer dynamic detection unit.

[0085] The upper-layer dynamic detection unit, in response to receiving the uploaded board topology information, updates the board topology information matching the server board according to preset rules; and

[0086] When the upper-layer dynamic detection unit is located inside the server motherboard, the upper-layer dynamic detection unit stops receiving the board topology information uploaded by the lower-layer dynamic detection unit after meeting preset conditions, and saves the latest version of the board topology information so that the basic input / output system firmware can be adapted to the current server system.

[0087] Fifthly, this application also provides a non-volatile computer-readable storage medium on which a computer program is stored, and which, when executed by one or more processors, performs the following operations:

[0088] In response to the server system startup, the lower-level dynamic detection unit generates the board topology information of the server board where the lower-level dynamic detection unit is located, wherein the lower-level dynamic detection unit is configured based on the interface configuration information within the server board;

[0089] In response to detecting a connection to an upper-layer dynamic detection unit, the lower-layer dynamic detection unit transmits the board topology information to the upper-layer dynamic detection unit.

[0090] The upper-layer dynamic detection unit, in response to receiving the uploaded board topology information, updates the board topology information matching the server board according to preset rules; and

[0091] When the upper-layer dynamic detection unit is located inside the server motherboard, the upper-layer dynamic detection unit stops receiving the board topology information uploaded by the lower-layer dynamic detection unit after meeting preset conditions, and saves the latest version of the board topology information so that the basic input / output system firmware can be adapted to the current server system. Attached Figure Description

[0092] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein:

[0093] Figure 1 is a schematic diagram of a server topology processing method provided in an embodiment of this application;

[0094] Figure 2 is a schematic diagram of a transmission provided in an embodiment of this application;

[0095] Figure 3 is a schematic diagram of the first topology scenario provided in the embodiment of this application;

[0096] Figure 4 is a schematic diagram of the second topology scenario provided in the embodiment of this application;

[0097] Figure 5 is a schematic diagram of the third topology scenario provided in the embodiments of this application;

[0098] Figure 6 is a schematic diagram of the fourth topology scenario provided in the embodiments of this application;

[0099] Figure 7 is a schematic diagram of the fifth topology scenario provided in the embodiments of this application;

[0100] Figure 8 is a schematic diagram of the sixth topology scenario provided in the embodiments of this application;

[0101] Figure 9 is an architecture diagram of the server topology processing system provided in an embodiment of this application;

[0102] Figure 10 is a structural diagram of the electronic device provided in an embodiment of this application;

[0103] Figure 11 is a structural diagram of a non-volatile computer storage medium provided in an embodiment of this application;

[0104] Figure 12 is a structural diagram of the computer program product provided in an embodiment of this application. Detailed Implementation

[0105] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0106] It should be understood that, in the description of this application, unless the context explicitly requires it, the words "comprising," "including," and similar terms throughout the specification and claims should be interpreted as encompassing rather than being exclusive or exhaustive; that is, meaning "including but not limited to."

[0107] It should also be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0108] It should be noted that the terms "S1," "S2," etc., are used only for descriptive purposes and do not specifically refer to the order or sequence, nor are they intended to limit this application. They are merely for the convenience of describing the method of this application and should not be construed as indicating the sequential order of the steps. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed in this application.

[0109] As mentioned in the background technology, when designing server systems according to specifications, although circuit boards can be reused, BIOS firmware often needs to be re-adapted, resulting in long development times and cumbersome verification processes. Solutions offered by related technologies require redesigning each system and re-adapting the BIOS to the PCIe (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) topology. Since the system topology is fixed for each system design, the hardware system team needs to inform the BIOS firmware team of the design information in the early stages of development. If several systems are designed simultaneously, the adaptation complexity can be reduced by identifying common parts, but this requires project teams to confirm that design information is synchronized. Therefore, solutions offered by related technologies typically involve adaptation schedules, testing schedules, and firmware modification time, resulting in considerable time consumption for each system design, creating difficulties in streamlining manpower and avoiding repetitive design.

[0110] This application provides a server topology processing method. In some embodiments, the method disclosed in this application is used to re-adapt the server system after redesigning the hardware boards, as shown in Figure 1, including the following:

[0111] S1. In response to the server system startup, the lower-level dynamic detection unit generates the board topology information of the server board where the lower-level dynamic detection unit is located.

[0112] The lower-level dynamic detection unit is configured based on the interface settings within the server board, and the server includes at least one server board. It is understood that the aforementioned lower-level dynamic detection unit and the upper-level dynamic detection unit mentioned below are the same type of dynamic detection unit. When distinguishing between upper and lower levels, dynamic detection units are divided into lower-level dynamic detection units and upper-level dynamic detection units; that is, the current dynamic detection unit is defined as the lower-level dynamic detection unit, and the dynamic detection unit at the next higher level is defined as the upper-level dynamic detection unit. The aforementioned interface can be a PCIe interface or other types of interfaces; this application does not limit its scope.

[0113] In some embodiments, the server hardware includes a motherboard and at least one server board, wherein the server board includes various types of boards, such as self-developed disk array cards, commercially available disk array cards, PCIe slot backplanes, PCIe resource expansion backplanes, RISER (extension) expansion, and NVME (Non-Volatile Memory Express) / SATA (Serial Advanced Technology Attachment) / SAS (Serial Attached SCSI) hard drive backplanes, etc.

[0114] Understandably, in order to achieve awareness of the topology of the hardware boards included in the server system, this application adds a lower-level dynamic detection unit when designing the server hardware; the configuration of this lower-level dynamic detection unit is generally based on the configuration information of the interfaces within the server boards, including:

[0115] The process involves: obtaining the bandwidth specifications of the interfaces within the server board; obtaining the connector specifications that implement the interface connection functions; determining the distribution of the lower-level dynamic detection units on the server board based on the bandwidth specifications of the interface design and the connector specifications that implement the interface connection functions; and configuring the lower-level dynamic detection units on the server board based on the distribution of the dynamic detection units on the server board. The PCIe connection is achieved through two MICOx8 (bandwidth specification x8) or one MCIOx16 (bandwidth specification x16) connectors. In this application, the MICOx16 connector will be referred to as the first connector, and the MCIOx8 connector will be referred to as the second connector.

[0116] In the embodiments of this application, the lower-level dynamic detection unit can be a dynamic detection unit with a bandwidth of x16 composed of two dynamic detection sub-units with a bandwidth specification of x8; the dynamic detection sub-units and dynamic detection units can be implemented by hardware such as CPLD (Complex Programmable Logic Device) or MCU (Complex Programmable Logic Device).

[0117] In the implementation scenario, based on the bandwidth specifications of the interface design and the connector specifications that implement the interface's connection function, the distribution of the lower-level dynamic detection units on the server board is determined. This includes: in response to determining that the interface bandwidth specification is x16 bandwidth and the connector specification is a first connector, the distribution of the dynamic detection units on the server board is determined to be a first distribution. The first distribution involves setting up one lower-level dynamic detection unit that matches the connector, and the lower-level dynamic detection unit has a communication connection with the slot provided by the server board to receive the slot's presence signal for later detection of whether the slot is occupied. Is a card inserted? In response to determining that the interface bandwidth specification is x16 bandwidth and the connector specification is two second connectors, the distribution of the lower-level dynamic detection unit on the server board is determined to be a second distribution, wherein the second distribution consists of setting two dynamic detection sub-units and matching them with the connectors respectively, and the dynamic detection sub-units communicating with the slots provided by the server board to receive the slot's presence signal; in response to determining that the interface bandwidth specification is x8 bandwidth and the connector specification is one second connector, the distribution of the lower-level dynamic detection unit on the server board is determined to be a first distribution.

[0118] S2. The lower-level dynamic detection unit responds to the detection that the lower-level dynamic detection unit is connected to the upper-level dynamic detection unit, and transmits the board topology information to the upper-level dynamic detection unit.

[0119] It is understood that lower-level dynamic detection units are set up in server boards of different levels. These lower-level dynamic detection units collect data that needs to reproduce the topology and transmit it to the upper-level dynamic detection units in the upper-level server boards. In some embodiments, in one implementation scenario, as shown in Figure 2, the lower-level dynamic detection unit communicates with the upper-level dynamic detection unit based on the clock signal line (CLK) and data signal line (DATA), similar to SGPIO hardware and protocol. Transmitting board topology information to the upper-level dynamic detection unit includes: the lower-level dynamic detection unit transmits the board topology information to the upper-level dynamic detection unit at a preset frequency through the clock signal line and data signal line. It is understood that data is transmitted from the lower layer to the upper layer and is sent indefinitely. In some embodiments, the preset frequency is any value between 100KHz and 400KHz, which is determined by those skilled in the art according to the actual scenario, and this application does not limit it. The lower-level dynamic detection unit can also use other transmission protocols to transmit data, and this application does not limit it. Through the above transmission method, the lower-level dynamic detection unit of each service board transmits data upwards in a one-way manner, realizing efficient data transmission between dynamic detection units.

[0120] The lower-level dynamic detection unit generates the board topology information of the server board where it resides. This includes: the lower-level dynamic detection unit collecting the slot status and bandwidth status of the slots provided by the server board, and setting the board level of the server board to 1; based on preset protocol rules, the dynamic detection unit generates the board topology information of the server board that conforms to the protocol rules, using the board level, board code, board number, slot number, checksum, and the collected slot and bandwidth status. The slot status can be directly determined based on the in-situ signal. Generally, the bandwidth status of the server board is determined after the design is completed, and the supported modes are determined by the cable between the connectors connecting the upper-level board and the server board at this level. The lower-level dynamic detection unit can directly obtain the bandwidth configuration (i.e., bandwidth specification) of the current server board.

[0121] In some embodiments, the board topology information generated according to the above-mentioned preset protocol rules is presented in the format shown in Table 1 below. It is understood that the format specified in Table 1 retains some flexibility and can be modified according to actual needs. In this embodiment, Table 1 is mainly for illustrative purposes and does not impose constraints.

[0122] Table 1

[0123] S3. The upper-layer dynamic detection unit responds to the received board topology information by updating the board topology information that matches the server board according to preset rules.

[0124] The aforementioned upper-layer dynamic detection unit, in response to receiving uploaded board topology information, updates the board topology information matching the server board according to preset rules. This includes: in response to receiving uploaded board topology information, adding board hierarchy levels to the board topology information matching the server board to generate transition board topology information; merging the generated transition board topology information with the uploaded board topology information; and updating the board topology information matching the server board where the dynamic detection unit is located based on the merged transition board topology information and the uploaded board topology information. This application collects and generates board topology information conforming to preset protocol rules through the dynamic detection unit, facilitating subsequent reading by the BIOS and BMC, and reproducing the service area board topology structure based on the read board topology information for subsequent operations.

[0125] Understandably, after the server system starts up, the lower-level dynamic detection unit on each layer of the server board will actively collect board topology information. However, at this time, each board initially considers itself to be the lowest-level board. Therefore, when collecting board topology information, the lower-level dynamic detection unit will automatically set the board hierarchy contained in the board topology information to 1. After receiving the topology information transmitted by the dynamic detection unit in the next layer of the board, it will add a board hierarchy, changing it from hierarchy 1 to hierarchy 2. After receiving board topology information from several different boards, it will add a lower-level board hierarchy.

[0126] S4. When the upper-layer dynamic detection unit is located inside the server motherboard, the upper-layer dynamic detection unit stops receiving the board topology information uploaded by the lower-layer dynamic detection unit and saves the latest version of the board topology information after the preset conditions are met, so that the basic input / output system firmware can be adapted to the current server system.

[0127] The method for determining whether the above-mentioned preset conditions are met includes: in response to receiving the uploaded board topology information, the upper-layer dynamic detection unit compares the currently received board topology information with the previously received board topology information; in response to determining that the currently received board topology information is the same as the previously received board topology information and defining the currently received board topology information as duplicate board topology information, the upper-layer dynamic detection unit obtains the maximum board level among the multiple board levels contained in the currently received board topology information; the upper-layer dynamic detection unit determines whether the preset conditions are met based on the obtained maximum board level and the number of repetitions of the currently received duplicate board topology information.

[0128] In some embodiments, the upper-layer dynamic detection unit determines whether a preset condition is met based on the acquired board hierarchy and the number of repetitions of the currently received duplicate board topology information. This includes: querying a preset threshold that matches the acquired maximum board hierarchy; determining that the preset condition is met if the number of repetitions of the currently received duplicate board topology information is greater than or equal to the preset threshold; and determining that the preset condition is not met if the number of repetitions of the currently received duplicate board topology information is greater than or equal to the preset threshold. By setting the above-mentioned judgment logic for the preset condition, the dynamic server in the motherboard stops collecting information after determining that it has received complete server board topology information, thus avoiding resource waste within the motherboard.

[0129] Understandably, since server boards have a hierarchical architecture, the number of application layers may differ in actual applications. Therefore, it is necessary to set preset conditions to determine whether the collection of the entire server board's board topology information is complete. Simply put, it depends on how many times the motherboard's second dynamic detection management unit receives repeated board topology information. That is, it is determined by whether the number of repetitions reaches a preset threshold. The number of repetitions is determined by the topology layer of the server board, which can be determined by the highest board layer in the collected topology information. This correspondence is preset by those skilled in the art based on the actual scenario. For example, if the designed board has five layers, then the preset threshold corresponding to that board layer can be set to any value between 8 and 10.

[0130] This application uses dynamic detection units in each layer of server boards to progressively transmit the collected board topology information upwards, finally reaching the dynamic detection unit on the motherboard. The BIOS can then use the latest version of the topology information stored in the dynamic detection unit on the motherboard to perceive the hardware topology of the server boards. This allows for complete reuse regardless of future changes in integrated circuit groups or other conditions, reducing the complexity of system design.

[0131] In some implementation scenarios, the Basic Input / Output System (BIOS) acquires and parses the latest version of the board topology information stored in the upper-layer dynamic detection unit within the server motherboard to obtain the server system's topology. Based on the bandwidth status of multiple server boards within the server system contained in the parsed board topology information, the BIOS adjusts its bandwidth settings to adapt to the current server system. The BIOS obtains the hardware topology of the entire server system by reading and parsing the latest version of the board topology information stored in the dynamic detection unit within the board.

[0132] Before the Basic Input / Output System (BIOS) acquires and parses the latest version of the board topology information stored in the upper-layer Dynamic Sensing Unit (MSU) within the server motherboard, it also includes: checking the compatibility between the BIOS and the server boards included in the server system; in response to determining that the BIOS is compatible with the server boards included in the server system, verifying the BIOS's operating status, which includes normal and abnormal states; in response to determining that the BIOS is incompatible with the server boards included in the server system, upgrading the BIOS first. After confirming compatibility, the operating status of the BIOS is further determined. In response to the BIOS's operating status being normal, the BIOS is triggered to acquire and parse the latest version of the board topology information stored in the MSU within the server motherboard. This avoids issues such as incompatibility between the BIOS and server boards, or BIOS malfunctions, which could lead to the BIOS being unable to adapt to the server system, thus affecting the development of the entire server system.

[0133] This application can also utilize the BMC (Baseboard Management Controller) to parse the latest board topology information collected within the motherboard, displaying the entire server board topology on the management screen for easy viewing by the design team, factory, maintenance unit, and users. The Baseboard Management Controller parses the latest version of board topology information stored by the dynamic detection unit within the server motherboard to obtain the server system topology; the Baseboard Management Controller then displays the topology on the management interface for user viewing. This application enables remote detection of cable faults within the system during use and maintenance, facilitating rapid service and improving user experience.

[0134] In some embodiments, when the BMC reads information, the information obtained is:

[0135] 55h / Ah / 16h / 82h / 03h / CRC / AA;

[0136] 55h / 3Bh / 28h / 8Ah / CRC / Aah / +55h / 4Ah / 16h / 82h / 03h / CRCh / Aah;

[0137] 55h / 3Eh / 28h / 8Ah / CRC / Aah / +55h / 4Ah / 16h / 82h / 03h / CRCh / AAh;

[0138] According to Table 1, the topology structure shown in Figure 3 can be obtained by parsing: there is a 2nd RISER expansion card (with slot A and a connector card <1st tier>) under this path, the 1st tier PCIE resource expansion card has slot 2 with a connector card, and slot 3 without a connector card. In this way, the dynamic system topology can be obtained, which can be used for display or debugging.

[0139] Furthermore, the BMC can also determine the connection status of some cables (i.e., connector cables) within the current server system based on the parsed board topology information. In some embodiments, the BMC reads the latest version of the board topology information stored in the dynamic detection unit within the server motherboard; the BMC parses the board topology information to obtain the bandwidth status and corresponding board number of each server board; and the BMC determines the cable connection status of the server board corresponding to the board number based on the obtained bandwidth status and board number.

[0140] In one implementation scenario, the baseboard management controller determines the cable connection status of the server board corresponding to the board code based on the acquired bandwidth status and board code. This includes: comparing the bandwidth specifications supported by the server board corresponding to the board code with the acquired bandwidth status; in response to determining that the server board supports a bandwidth specification of x16 bandwidth and the acquired bandwidth status matching the server board is x8 bandwidth, determining that the cable connection status of the server board corresponding to the board code is abnormal; in response to determining that the server board supports a bandwidth specification of x16 bandwidth and the acquired bandwidth status matching the server board is x8 bandwidth, determining that the cable connection status of the server board corresponding to the board code is abnormal; in response to determining that the server board supports a bandwidth specification of x8 bandwidth and no acquired bandwidth status matching the server board is obtained, determining that the cable connection status of the server board corresponding to the board code is abnormal. In this context, it can be understood that the cable for the server board corresponding to the aforementioned board code is the cable that enables the PCIe connection between the server board at this board level and the previous server board.

[0141] The baseboard management controller generates a cable anomaly alarm in response to detecting an abnormal cable connection status of the server board corresponding to the board code, prompting the user to repair the abnormal cable; and / or, the baseboard management controller generates a cable anomaly log in response to detecting an abnormal cable connection status of the server board corresponding to the board code, so that the user can view and repair the abnormal cable. This application also provides more user-friendly functions in production assembly or for end users, making it easy to identify cable assembly omissions or cable detachments, and displaying the overall topology diagram on the control screen; in manufacturing, it also provides faster confirmation of the overall topology settings and faster troubleshooting of cable problems, saving a significant amount of time in production error correction and increasing production efficiency. The abnormal cable can be identified using the cable disconnection or detachment judgment method in the following topology connection scenario.

[0142] The above solution is illustrated below using some topology connection scenarios:

[0143] Topology connection scenario 1, direct connection to RISE expansion card / PCIe slot backplane: PCIe slot - MCIO connector - cable - motherboard, as shown in Figure 4:

[0144] PCIe connectors typically use two MCIOx8 or one MCIOx16 connector. In this scenario, we'll use two MCIOx8 connectors (the second connector) for illustration: the wiring on the slot backplane is designed from the outset to determine whether the PCIe slot supports x8 or x16. Generally, it's designed to support x16, and the cables determine which mode is supported: two cables support x16 (Figure 4 top), one cable supports x8 (Figure 4 bottom). The Dynamic Detection Management Unit (DMU) itself contains parameters indicating whether the slot supports x8 or x16. Upon system startup, the DMU collects information such as whether there's an access card in the PCIe slot and whether MICO H8x / MICO L8x cables are connected (i.e., bandwidth specifications). After processing other necessary data, such as board hierarchy, it generates board topology information and encapsulates it for transmission upwards; in this scenario, it's transmitted to the motherboard's DMU.

[0145] Understandably, the dynamic detection unit and its managed peripheral connections only have bit signals. However, during board design, it's necessary to define whether the relevant interface is x8 or x16. An x16 PCIe slot has two dynamic detection units (H8x / L8x) with bandwidth definitions set to 0111 / 1101 respectively. When the system powers on, the previous dynamic detection unit receives board topology information containing H8x: 1011 / L8x: 1110. In response to confirming that the previous dynamic detection unit has received H8x / L8x bandwidth data, and that the system compares the BIOS data at startup as x8 / x16, the PCIe connection is determined. If an x8 / x16 card has both cables properly connected; and the preceding dynamic detection unit only receives bandwidth data of L8x: 1110, it indicates an H8x cable malfunction, and the PCIe card can only operate in x8 mode: With an x16 card, reduced bandwidth will be observed; with an x8 card, no logical anomaly will be detected, but cable status checks will reveal an H8x cable malfunction; if the preceding dynamic detection unit only receives bandwidth data of H8x: 1011, it indicates an L8x cable malfunction, and the PCIe card should be undetectable (card loss); if the slot only supports x8 mode, and only one dynamic detection unit (L8x) has its bandwidth defined as 1101, the preceding dynamic detection unit will receive bandwidth data of L8x: 1101 after the system is powered on; failure to receive this data indicates a cable malfunction.

[0146] The dynamic detection unit on the motherboard will know the status of all subordinate paths at a certain time. In this scenario, it is: CPU PCIE PORT - cable - PCIE x16 / PCIE x8 slot. After reporting to the BMC, the BMC and BIOS firmware communicate. The BIOS can then know that the PCIE PORT needs to be set to x16 / x8x8 / x8x4x4 / x4x4x8 / x4x4x4x4. The BMC / BIOS also knows what type of card is connected, and completes the link bandwidth setting and terminal PCIE device identification.

[0147] In this scenario, x16 PCI cards are supported by default. If both cables are correctly installed, the motion detection unit will report the x16 bandwidth specification and indicate whether a card is connected. If the MICO H8x cable is found to be disconnected or loose, the motion detection unit will report the x8 bandwidth specification (MCIO L8x is correctly installed). The BIOS will then set this link to x8 and correctly recognize the card. This can be seen from the BMC management interface, where the link is set to x8. The system will then run normally, but the bandwidth of this link will be reduced to x8 (expected to be x16). This helps users or maintenance personnel quickly troubleshoot whether the configuration is correct. Conversely, if the MICO L8x cable is found to be disconnected or loose, the motion detection unit will report the x8 bandwidth specification (MCIO H8x is correctly installed). The BIOS will then set this link to x8 and will not recognize the card. This can be seen from the BMC management interface, where the link is set to x8 and the card is incorrectly identified (it will indicate that a MICO H8x cable is connected). This helps users or maintenance personnel quickly troubleshoot the problem. In response to the determination that there are only cables connected but the slot is not actually used, the action is the same as described above, but the status will be reported: whether there are two cables (MCIO H8x+L8x) or one cable (MCIO H8x, L8x). The connection status can be viewed from the BMC management interface, which effectively improves the overall user experience, prevents system problems caused by production errors or transportation, and reduces maintenance costs.

[0148] Topology connection scenario 2, PCIe resource expansion backplane: PCIe slot - PCIe SW chip - MCIO connector - cable - motherboard, as shown in Figure 5:

[0149] The SW chip on the expansion backplane typically has a single uplink configuration (1 x PCIe x16 resource, two MICO x8 slots) or a dual uplink configuration (2 x PCIe x16 resources, four MICO x8 slots). This scenario demonstrates a single uplink configuration. During the board design phase, it is planned which MCIO connectors will connect to the SW chip and which PCIe slots the SW chip controls. As shown in Figure 5, the two MCIO connectors (J1, J2) on the board are set to x16 mode. The SW chip controls Slots 8 / 9 / 10 / 11, which are all in x16 mode. Therefore, the dynamic detection management unit contains data showing that J1 / J2 are linked to Slots 8 / 9 / 10 / 11 and also contains the board category number.

[0150] When the system boots up, the Dynamic Detection Management Unit (DMU) collects: 1. Whether there is an access card in the PCIe slot, and 2. Whether the MICO H8x / MICO L8x cable is connected. After organizing the data, it sends data packets upwards (in this example, the data is transmitted to the motherboard's DMU). The motherboard's DMU will, over time, know the status of all its subordinate paths: CPU PCIe PORT - cable - PCIe SW chip - PCIe x16 slot. After reporting this to the BMC, the BMC and BIOS firmware communicate. The BIOS then knows that the PCIe PORT needs to be set to x16, and the BMC / BIOS also knows the type of card connected, completing the link bandwidth setting and terminal PCIe device identification. In this example, the default configuration supports x16 PCIe SW chips. If both cables are correctly installed, the DMU will report the x16 configuration and know whether the cards under the SW's management are connected.

[0151] In response to the confirmation that the MICO H8x cable is not connected or is disconnected, the dynamic detection unit will report the bandwidth specification of x8 (MCIO L8x is installed correctly). The BIOS will eventually set this link to x8 and recognize the cards under the SW. This link can be seen from the BMC management interface as x8. At this time, the system will run normally, but the bandwidth of this link will be reduced to x8 (expected to be x16), and the performance of PCIe cards in Slots 8 / 9 / 10 / 11 will be severely insufficient. This helps users or maintenance personnel quickly troubleshoot whether the configuration is correct. In response to the confirmation that the MICO L8x cable is not connected or is disconnected, the dynamic detection unit will report the bandwidth specification of x8 (MCIO H8x is installed correctly). The BIOS will eventually set this link to x8 and will not recognize all cards. This can be seen from the BMC management interface as x8 and the card recognition is incorrect (it will be known that only the MICO H8x cable is connected). This helps users or maintenance personnel quickly troubleshoot problems. In response to the determination that there are only cables connected but the slot is not actually used, the action is the same as described above, but the status will be reported: whether there are two cables (MCIO H8x+L8x) or one cable (MCIO H8x, L8x). The connection status can also be viewed from the BMC management interface, which effectively improves the overall user experience, prevents system problems caused by production errors or transportation, and reduces maintenance costs.

[0152] Topology connection scenario 3, CIE resource expansion card: PCIE slot - PCIE SW chip - MCIO connector - cable - motherboard, as shown in Figure 3:

[0153] This scenario utilizes a PCIe RISE card and a PCIe expansion card. The motherboard connects to the PCIe RISE card, and the PCIe expansion card is connected to the PCIe RISE card. The operating principle is the same as the two connection scenarios mentioned above, and will not be repeated here. The principle of board topology information flow is as follows: information is transmitted from the last layer (the layer where the terminal device is located) upwards. Therefore, at boot time, each layer is unaware of whether a lower layer exists. Thus, each board initially considers itself to be at layer one (LV1). When it receives data from the lower layer, it becomes layer two (LV2). In this way, the motherboard's dynamic detection unit will know that this link has two layers (PCIe RISE card and PCIe expansion card), and how many slots it belongs to, which are used and which are not.

[0154] In the implementation scenario, determining the distribution of dynamic detection units on the server board also includes: when the connection function with the interface is implemented through the gold fingers, the distribution of dynamic detection units on the server board is determined as a third distribution scenario; wherein, the third distribution scenario involves setting up a dynamic detection unit that matches the gold fingers, and the dynamic detection unit communicates with the slot provided by the server board to receive the slot's presence signal. Because the PCIe resource expansion card connects to the PCIe RISER expansion card through the gold fingers, and the x8 / x16 gold fingers are fixed when the card is designed, the PCIe resource expansion card has only one dynamic detection management unit.

[0155] Topology Connection Scenario 4: Direct Connection to PCIe Hard Drive (NVME, E3.S, E1.S, E1.L) Backplane + Direct Connection to RISER Expansion Card: PCIe Hard Drive / PCIe Slot - MCIO Connector - Cable - Motherboard, as shown in Figure 6: This scenario uses a PCIe RISER card and an NVME hard drive backplane. The motherboard connects to both the PCIe RISER card and the NVME hard drive backplane. The operating principle is the same as in the previous examples and will not be repeated. Based on this scenario, the following explains the application style of this solution under different bandwidths: Each interface has a dynamic monitoring and management unit, so the two MCIO connectors on the motherboard are connected to data from the NVME hard drive backplane and the RISER expansion card, respectively. As can be seen from the figure, both cards belong to LV1.

[0156] Topology Connection Scenario 5: Non-Directly Connected PCIe Hard Drive (NVME, E3.S, E1.S, E1.L) Backplane: PCIe Hard Drive - PCIe SW Chip - MCIO Connector - Cable - Motherboard, as shown in Figure 7: This scenario uses a PCIe resource expansion backplane and an NVME hard drive backplane. The operating principle is the same as the previous examples, so it will not be repeated. This scenario mainly explains the style when applying this solution with different bandwidths: The key is the Dynamic Detection Management Unit (DMU) on the PCIe resource expansion backplane (connected to the NVME hard drive backplane). It is connected to the DMU of the MICO L8x because the PCIe SW chip must be configured to x16; otherwise, the performance will be insufficient. Therefore, only the DMU of the MICO L8x needs to be connected here. Under normal circumstances, in response to determining the x16 configuration, only the DMU of the L8x needs to be resolved; the H8x group can be used as verification data.

[0157] Topology Connection Scenario 6: The topology uses a commercially available PCIe RAID card (connected to a non-PCIe device), as shown in Figure 8. In this implementation scenario, in response to the determination that the server system includes a disk array card among multiple server boards, an additional dynamic detection unit is set up separately in the server board above the disk array card. This additional dynamic detection unit receives the board topology information generated by the dynamic detection unit in the server board connected below the disk array card. The additional dynamic detection unit then uploads the received board topology information to the dynamic detection unit in the server board above the disk array card. That is, this scenario demonstrates using a common PCIe RAID card to support SATA / SAS hard drives. Since commercially available RAID cards do not support this dynamic detection scheme, an additional method is needed to supplement the data for the layer above the RAID card (in this example, the PCIe slot backplane), thus compensating for the shortcomings of this solution.

[0158] This application provides a server topology processing method, including: in response to server system startup, a lower-level dynamic detection unit generates board topology information of the server board where the lower-level dynamic detection unit is located; the lower-level dynamic detection unit configures itself based on the interface settings within the server board; in response to detecting a connection to an upper-level dynamic detection unit, the lower-level dynamic detection unit transmits the board topology information to the upper-level dynamic detection unit; in response to receiving the uploaded board topology information, the upper-level dynamic detection unit updates the board topology information matching the server board according to preset rules; when the upper-level dynamic detection unit is located within the server motherboard, after meeting preset conditions, the upper-level dynamic detection unit stops receiving the board topology information uploaded by the lower-level dynamic detection unit and saves the latest version of the board topology information so that the basic input / output system firmware can adapt to the current server system. This provides a general topology processing method, significantly reducing firmware adaptation difficulty and simultaneously troubleshooting the connection status of specific cables, greatly improving server stability; furthermore, the BMC can be used to display the overall topology diagram on the control screen, improving perceptibility.

[0159] As shown in Figure 12, this application embodiment also provides a computer program product, including a computer program, which, when executed by one or more processors, implements the following method steps:

[0160] In response to the server system startup, the lower-level dynamic detection unit generates board topology information of the server board where the lower-level dynamic detection unit is located, and the lower-level dynamic detection unit makes settings based on the interface settings information in the server board;

[0161] The lower-level dynamic detection unit responds to the detection that the lower-level dynamic detection unit is connected to the upper-level dynamic detection unit, and transmits the board topology information to the upper-level dynamic detection unit;

[0162] The upper-layer dynamic detection unit responds to the received board topology information by updating the board topology information that matches the server board according to preset rules;

[0163] When the upper-layer dynamic detection unit is located inside the server motherboard, the upper-layer dynamic detection unit stops receiving the board topology information uploaded by the lower-layer dynamic detection unit after meeting preset conditions, and saves the latest version of the board topology information so that the basic input / output system firmware can be adapted to the current server system.

[0164] As shown in Figure 9, corresponding to the above embodiments, this application also provides a server topology system, including:

[0165] The information generation module 910 is used to generate the board topology information of the server board where the lower-level dynamic detection unit is located in response to the server system startup. The lower-level dynamic detection unit is configured based on the interface configuration information in the server board.

[0166] The information transmission module 920 is used to transmit board topology information to the upper-layer dynamic detection unit in response to the detection that the upper-layer dynamic detection unit is connected.

[0167] Information processing module 930 is used by the upper-layer dynamic detection unit to update the board topology information that matches the server board according to preset rules in response to the received uploaded board topology information;

[0168] The information processing module 930 is also used to, when the upper-layer dynamic detection unit is set in the server motherboard, stop receiving the board topology information uploaded by the lower-layer dynamic detection unit after meeting preset conditions and save the latest version of the board topology information so that the basic input / output system firmware can be adapted to the current server system.

[0169] Corresponding to all the above embodiments, this application provides an electronic device, including: one or more processors; and a memory associated with the one or more processors, the memory being used to store program instructions, which, when read and executed by the one or more processors, perform the following operations:

[0170] In response to the server system startup, the lower-level dynamic detection unit generates the board topology information of the server board where the lower-level dynamic detection unit is located, wherein the lower-level dynamic detection unit is configured based on the interface configuration information within the server board;

[0171] In response to detecting a connection to an upper-layer dynamic detection unit, the lower-layer dynamic detection unit transmits the board topology information to the upper-layer dynamic detection unit.

[0172] The upper-layer dynamic detection unit responds to the received board topology information by updating the board topology information that matches the server board according to preset rules;

[0173] When the upper-layer dynamic detection unit is located inside the server motherboard, the upper-layer dynamic detection unit stops receiving the board topology information uploaded by the lower-layer dynamic detection unit after meeting preset conditions, and saves the latest version of the board topology information so that the basic input / output system firmware can be adapted to the current server system.

[0174] Figure 10 illustrates the architecture of an electronic device, which may include a processor 1010, a video display adapter 1011, a disk drive 1012, an input / output interface 1013, a network interface 1014, and a memory 1020. The processor 1010, video display adapter 1011, disk drive 1012, input / output interface 1013, network interface 1014, and memory 1020 can communicate with each other via a bus 1030.

[0175] The processor 1010 can be implemented using a general-purpose CPU (Central Processing Unit), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solution provided in this application.

[0176] The memory 1020 can be implemented in the form of ROM (Read Only Memory), RAM (Random Access Memory), static storage device, dynamic storage device, etc. The memory 1020 can store the operating system 1021 for controlling the execution of the electronic device 1000, and the basic input / output system (BIOS) 1022 for controlling the low-level operations of the electronic device 1000. Additionally, it can store a web browser 1023, a data storage management system 1024, and an icon font processing system 1025, etc. The aforementioned icon font processing system 1025 can be the application program that implements the aforementioned steps in this embodiment. In summary, when the technical solution provided in this application is implemented through software or firmware, the relevant program code is stored in the memory 1020 and is called and executed by the processor 1010.

[0177] Input / output interface 1013 is used to connect input / output modules to realize information input and output. Input / output modules can be configured as components in the device (not shown in the figure) or externally connected to the device to provide corresponding functions. Input devices may include keyboards, mice, touch screens, microphones, various sensors, etc., and output devices may include displays, speakers, vibrators, indicator lights, etc.

[0178] The network interface 1014 is used to connect the communication module (not shown in the figure) to enable communication and interaction between this device and other devices. The communication module can communicate via wired means (such as USB, Ethernet cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.).

[0179] Bus 1030 includes a pathway for transmitting information between various components of the device (e.g., processor 1010, video display adapter 1011, disk drive 1012, input / output interface 1013, network interface 1014, and memory 1020).

[0180] In addition, the electronic device 1000 can also obtain information on the conditions for receiving virtual resource objects from the database of conditions for receiving information, so as to make condition judgments, etc.

[0181] It should be noted that although the above-described device only shows the processor 1010, video display adapter 1011, disk drive 1012, input / output interface 1013, network interface 1014, memory 1020, bus 1030, etc., in practice, the device may also include other components necessary for normal operation. Furthermore, those skilled in the art will understand that the above-described device may only include the components necessary for implementing the solution of this application, and does not necessarily include all the components shown in the figures.

[0182] As can be seen from the above description of the embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus a general-purpose hardware platform. Based on this understanding, the technical solution of this application, in essence or the part that contributes to the related technology, can be embodied in the form of a software product. This computer software product can be stored in a storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, a cloud server, or a network device, etc.) to execute the methods of various embodiments or some parts of the embodiments of this application.

[0183] Corresponding to all the above embodiments, as shown in FIG11, this application embodiment also provides a non-volatile computer-readable storage medium for storing a computer program, which, when executed by one or more processors, performs the following operations:

[0184] In response to the server system startup, the lower-level dynamic detection unit generates the board topology information of the server board where the lower-level dynamic detection unit is located, wherein the lower-level dynamic detection unit is configured based on the interface configuration information within the server board;

[0185] In response to detecting a connection to an upper-layer dynamic detection unit, the lower-layer dynamic detection unit transmits the board topology information to the upper-layer dynamic detection unit.

[0186] The upper-layer dynamic detection unit responds to the received board topology information by updating the board topology information that matches the server board according to preset rules;

[0187] When the upper-layer dynamic detection unit is located inside the server motherboard, the upper-layer dynamic detection unit stops receiving the board topology information uploaded by the lower-layer dynamic detection unit after meeting preset conditions, and saves the latest version of the board topology information so that the basic input / output system firmware can be adapted to the current server system.

[0188] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for system or system embodiments, since they are basically similar to method embodiments, the description is relatively simple, and relevant parts can be referred to the descriptions in the method embodiments. The systems and system embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0189] The above are merely preferred embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A server topology processing method, characterized in that the method includes: In response to the server system startup, the lower-layer dynamic detection unit generates the board topology information of the server board where the lower-layer dynamic detection unit is located, wherein the lower-layer dynamic detection unit is configured based on the interface configuration information within the server board; In response to detecting a connection to an upper-layer dynamic detection unit, the lower-layer dynamic detection unit transmits the board topology information to the upper-layer dynamic detection unit. The upper-layer dynamic detection unit responds to the received board topology information by updating the board topology information that matches the server board according to preset rules; as well as When the upper-layer dynamic detection unit is located inside the server motherboard, the upper-layer dynamic detection unit stops receiving the board topology information uploaded by the lower-layer dynamic detection unit and saves the latest version of the board topology information after meeting preset conditions, so that the basic input / output system firmware can be adapted to the current server system.

2. The method according to claim 1, characterized in that, The lower-level dynamic detection unit generates the board topology information of the server board where the lower-level dynamic detection unit is located, including: The lower-level dynamic detection unit collects the slot status of the slots provided by the server board and the bandwidth status of the server board, and sets the board level of the server board to 1; and Based on preset protocol rules, the lower-layer dynamic detection unit generates server board topology information that conforms to the protocol rules by taking the board hierarchy, board code, board number, slot number, check code, and the collected slot status and bandwidth status of the server board.

3. The method according to claim 2, characterized in that, The lower-level dynamic detection unit communicates with the upper-level dynamic detection unit via clock signal lines and data signal lines. The step of transmitting the board topology information to the upper-layer dynamic detection unit includes: The lower-level dynamic detection unit transmits the board topology information to the upper-level dynamic detection unit at a preset frequency through the clock signal line and data signal line.

4. The method according to claim 2, characterized in that, The upper-layer dynamic detection unit, in response to receiving the uploaded board topology information, updates the board topology information matching the server board according to preset rules, including: In response to receiving the uploaded board topology information, the system adds a board hierarchy to the board topology information that matches the board on the server, thereby generating transitional board topology information; and The generated transition board topology information is merged with the uploaded board topology information. Based on the merged transition board topology information and the uploaded board topology information, the board topology information matching the server board where the upper-layer dynamic detection unit is located is updated.

5. The method according to claim 1, characterized in that, The method includes a method for determining whether the preset conditions are met: In response to receiving the uploaded board topology information, the upper-layer dynamic detection unit compares the currently received board topology information with the previously received board topology information. In response to determining that the currently received board topology information is the same as the previously received board topology information and defining the currently received board topology information as duplicate board topology information, the upper-layer dynamic detection unit obtains the maximum board level among the multiple board levels contained in the currently received board topology information. as well as The upper-layer dynamic detection unit determines whether the preset condition is met based on the obtained maximum board level and the number of repetitions of the currently received duplicate board topology information.

6. The method according to claim 5, characterized in that, The upper-layer dynamic detection unit determines whether the preset condition is met based on the acquired board hierarchy and the number of repetitions of the currently received duplicate board topology information, including: Query and obtain the preset threshold that matches the maximum board level; In response to determining that the number of repetitions of the currently received duplicate board topology information is greater than or equal to the preset threshold, the preset condition is determined to be satisfied; and In response to determining that the number of repetitions of the currently received duplicate board topology information is greater than or equal to the preset threshold, it is determined that the preset condition is not met.

7. The method according to claim 2, characterized in that, The method for configuring the lower-level dynamic detection unit based on the configuration information of the interface within the server board includes: Obtain the bandwidth specifications of the interfaces within the server board; Obtain the connector specifications that implement the connection function of the interface; Based on the bandwidth specifications of the interface design and the connector specifications for implementing the interface's connection functions, determine the distribution of the lower-layer dynamic detection units on the server board; and Based on the distribution of the lower-level dynamic detection units on the server board, the lower-level dynamic detection units on the server board are configured.

8. The method according to claim 7, characterized in that, The lower-layer dynamic detection unit includes two dynamic detection sub-units. The process of determining the distribution of the lower-layer dynamic detection unit on the server board based on the bandwidth specifications of the interface design and the connector specifications for implementing the interface's connection functions includes: In response to determining that the bandwidth specification of the interface is x16 bandwidth and the connector specification is a first connector, the distribution of the lower-layer dynamic detection unit on the server board is determined to be a first distribution, wherein the first distribution is to set a lower-layer dynamic detection unit that matches the connector, and the lower-layer dynamic detection unit is communicatively connected to the slot provided by the server board to receive the slot's presence signal; In response to determining that the interface bandwidth specification is x16 bandwidth and the connector specification is two second connectors, the distribution of the lower-layer dynamic detection unit on the server board is determined to be a second distribution, wherein the second distribution involves setting two dynamic detection sub-units, each matched with a connector, and the dynamic detection sub-units communicating with slots provided by the server board to receive the slot's presence signal; and In response to determining that the bandwidth specification of the interface is x8 bandwidth and the connector specification is a second connector, the distribution of the lower-layer dynamic detection unit on the server board is determined to be the first distribution.

9. The method according to claim 7, characterized in that, Determining the distribution of the lower-level dynamic detection units on the server board also includes: In response to determining that the connection function with the interface is achieved through the gold fingers, the distribution of the lower-layer dynamic detection unit on the server board is determined to be a third distribution scenario; wherein... The third distribution scenario involves setting up a lower-level dynamic detection unit that matches the gold finger, and the lower-level dynamic detection unit is communicatively connected to the slot provided by the server board to receive the slot's presence signal.

10. The method according to claim 7, characterized in that, The method further includes: In response to determining that a disk array card is included among the multiple server boards in the server system, an additional dynamic detection unit is separately set in the server board above the disk array card; The additional dynamic detection unit receives board topology information generated by the lower-level dynamic detection unit within the server board connected to the disk array card; and The received board topology information is uploaded by the additional dynamic detection unit to the upper-layer dynamic detection unit in the server board above the disk array card.

11. The method according to claim 8, characterized in that, The method further includes: The baseboard management controller reads the latest version of the board topology information stored in the dynamic detection unit inside the server motherboard; The baseboard management controller parses the board topology information to obtain the bandwidth status and corresponding board number of each server board; and The baseboard management controller determines the cable connection status of the server board corresponding to the board number based on the obtained bandwidth status and board number.

12. The method according to claim 11, characterized in that, The baseboard management controller determines the cable connection status of the server board corresponding to the board number based on the acquired bandwidth status and board number, including: Compare the bandwidth specifications supported by the server board corresponding to the board code with the obtained bandwidth status; In response to determining that the server board supports a bandwidth specification of x16 bandwidth and obtaining a bandwidth status matching the server board of x8 bandwidth, it is determined that the cable connection status of the server board corresponding to the board code is abnormal; and In response to determining that the bandwidth specification supported by the server board is x8 bandwidth and that no bandwidth status matching the server board has been obtained, it is determined that the cable connection status of the server board corresponding to the board code is abnormal.

13. The method according to claim 12, characterized in that, The method includes: The baseboard management controller, in response to detecting an abnormal cable connection status of the server board corresponding to the board code, generates a cable abnormality alarm to prompt the user to repair the abnormal cable; and / or, In response to a detected abnormal cable connection status of the server board corresponding to the board code, the baseboard management controller generates a cable abnormality log so that users can view and repair the abnormal cable.

14. The method according to claim 12, characterized in that, The method further includes: The baseboard management controller parses the latest version of the board topology information stored in the upper-layer dynamic detection unit within the server motherboard to obtain the topology of the server system; and The substrate management controller displays the topology in the management interface for user viewing.

15. The method according to claim 11, characterized in that, After the baseboard management controller reads the latest version of the board topology information stored in the upper-layer dynamic detection unit within the server motherboard, the method includes: Verify the correctness of the board topology information stored in the two dynamic detection subunits within the dynamic detection unit: In response to the detection that the board topology information stored by the two dynamic detection subunits differs in information other than checksum and bandwidth status, it is determined that the board topology information is incorrect and an anomaly alarm is generated to prompt the user to check the upper-layer dynamic detection unit; and If the two dynamic detection subunits store different information in the board topology information other than the checksum and bandwidth status, then the board topology information is determined to be correct.

16. The method according to claim 1, characterized in that, The method further includes: The basic input / output system acquires and parses the latest version of the board topology information stored in the upper-layer dynamic detection unit within the server motherboard to obtain the topology of the server system; and The basic input / output system adjusts the bandwidth settings within the basic input / output system to adapt to the current server system based on the bandwidth status of multiple server boards within the server system contained in the parsed board topology information.

17. The method according to claim 16, characterized in that, Before the basic input / output system acquires and parses the latest version of the board topology information stored in the upper-layer dynamic detection unit within the server motherboard, the method includes: Test the compatibility between the basic input / output system and the server boards included in the server system; In response to determining that the basic input / output system is compatible with the server boards included in the server system, the operating state of the basic input / output system is verified, including a normal state and an abnormal state; and In response to the basic input / output system being in a normal operating state, the basic input / output system is triggered to acquire and parse the latest version of the board topology information stored in the upper-layer dynamic detection unit within the server motherboard.

18. A computer program product, comprising a computer program, characterized in that, When executed by one or more processors, the computer program implements the steps of the method described in any of claims 1-17.

19. An electronic device, characterized in that, The electronic device includes: One or more processors; And a memory associated with the one or more processors, the memory being used to store program instructions that, when read and executed by the one or more processors, perform the method of any one of claims 1-17.

20. A non-volatile computer-readable storage medium, characterized in that, It stores a computer program that, when executed by one or more processors, implements the method as described in any one of claims 1-17.

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