Computing chip packaging structure, memory chip packaging structure, memory apparatus, computing apparatus, and resource pooling system

Abstract

Provided in the present disclosure are a computing chip packaging structure, a memory chip packaging structure, a memory apparatus, a computing apparatus, and a resource pooling system. The memory chip package structure comprises: a packaging substrate; an optical interconnection module, which comprises an optoelectronic signal conversion module and a first transceiver chip; a first photonic integrated circuit chip, which is arranged on the packaging substrate; and a memory chip module, which is arranged on the first photonic integrated circuit chip and comprises a first electrical interconnection interface, wherein the first transceiver chip comprises a second electrical interconnection interface, which is electrically connected to the first electrical interconnection interface by means of the first photonic integrated circuit chip; the first transceiver chip converts a first electrical signal, which is from the memory chip module, into a second electrical signal, and converts a third electrical signal, which is from the optoelectronic signal conversion module, into a fourth electrical signal sent to the memory chip module; and the optoelectronic signal conversion module converts the second electrical signal into a first optical signal outputted to the outside, and converts a second optical signal, which is received from the outside, into the third electrical signal.

Description

Computing, memory chip packaging structures and devices, and resource pooling systems

[0001] This application claims priority to Chinese Patent Application No. 202411224030.0, filed on September 2, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure relates to the fields of optoelectronic communication and computing, specifically to memory chip packaging structures, memory devices, computing chip packaging structures, computing devices, and resource pooling systems. Background Technology

[0003] With the explosive growth of generative artificial intelligence, the demand for processor computing speed, as well as memory capacity and bandwidth, is increasing daily. If the data transfer speed of memory cannot keep up with the computing speed of the processor, the processor's computing power will be limited, thus affecting the performance of artificial intelligence applications.

[0004] In conventional packaging technologies, memory chips and computing chips are placed close together within the same package structure, resulting in relatively little space available for accommodating the memory chips. This limits the memory capacity of the memory chips and the outgoing bandwidth density of the computing chips. Consequently, performance improvements in artificial intelligence applications are constrained. Summary of the Invention

[0005] This disclosure provides a computing chip package structure and computing device with high transmission bandwidth density and capable of connecting large-capacity memory, a memory chip package structure and memory device with high transmission bandwidth, and a resource pooling system with large capacity and high transmission bandwidth that can flexibly combine resources.

[0006] According to one aspect of this disclosure, a memory chip packaging structure is provided, comprising: a packaging substrate; an optical interconnect module including a photoelectric signal conversion module and a first transceiver chip; a first photonic integrated circuit chip disposed on the packaging substrate and including the photoelectric signal conversion module; and a memory chip module disposed on the first photonic integrated circuit chip and including a first electrical interconnect interface, wherein the first transceiver chip is disposed on the first photonic integrated circuit chip and includes a second electrical interconnect interface and an electrical signal conversion unit, the first electrical interconnect interface and the second electrical interconnect interface are electrically connected to each other through conductive channels in the first photonic integrated circuit chip, the electrical signal conversion unit is used to convert a first electrical signal from the memory chip module into a second electrical signal, and to convert a third electrical signal from the photoelectric signal conversion module into a fourth electrical signal sent to the memory chip module, and the photoelectric signal conversion module includes an optical signal input port and an optical signal output port, and is used to convert the second electrical signal received from the first transceiver chip into a first optical signal output from the optical signal output port, and to convert the second optical signal received from the optical signal input port into a third electrical signal sent to the first transceiver chip.

[0007] In some embodiments, a power supply interface is arranged on the packaging substrate, which supplies power to the first power receiving chip and the memory chip module through conductive vias in the first photonic integrated circuit chip.

[0008] In some embodiments, the memory chip module and the first transceiver chip are flip-mounted on the surface of the first photonic integrated circuit chip facing away from the packaging substrate, and the first electrical interconnect interface and the second electrical interconnect interface are electrically connected to the conductive channels in the first photonic integrated circuit chip through bumps.

[0009] In some embodiments, the first transceiver chip further includes a switching unit, the memory chip module includes a first memory chip component and a second memory chip component, and the switching unit is used to switchably connect the first memory chip component and the second memory chip component to the electrical signal conversion unit.

[0010] In some embodiments, the photoelectric signal conversion module further includes a light source input port and an optical modulator, wherein the light source input port is used to receive an optical carrier, and the optical modulator is used to modulate the optical carrier into a first optical signal according to a second electrical signal.

[0011] In some embodiments, the photoelectric signal conversion module further includes a photodetector for converting the second optical signal into a third electrical signal.

[0012] In some embodiments, the memory chip module includes at least one memory chip component, each memory chip component including a memory logic chip and one or more memory chips stacked on the memory logic chip.

[0013] In some embodiments, the memory chip is a high-bandwidth memory chip.

[0014] According to one aspect of this disclosure, a memory device is provided, comprising: a printed circuit board; and the aforementioned memory chip package structure mounted on the printed circuit board.

[0015] In some embodiments, the memory device further includes an additional memory chip assembly mounted on a printed circuit board, and the first transceiver chip further includes a third electrical interconnect interface for electrical connection with the additional memory chip assembly.

[0016] According to one aspect of this disclosure, a computing chip packaging structure is provided, comprising: a packaging substrate; a computing chip disposed on the packaging substrate and including a first chip interconnect interface; and an optical interconnect module disposed on the packaging substrate and including a second chip interconnect interface, an optical signal input port, and an optical signal output port, wherein the first chip interconnect interface and the second chip interconnect interface are electrically connected to each other through conductive channels in the packaging substrate, and the optical interconnect module converts a first optical signal received from the optical signal input port into a first electrical signal output to the computing chip, and converts a second electrical signal received from the computing chip into a second optical signal output from the optical signal output port.

[0017] In some embodiments, the optical interconnect module includes a second photonic integrated circuit chip and a second transceiver chip stacked on the second photonic integrated circuit chip. The second transceiver chip is used to convert a third electrical signal from the second photonic integrated circuit chip into a first electrical signal and to convert the second electrical signal into a fourth electrical signal sent to the second photonic integrated circuit chip. The second photonic integrated circuit chip includes an optical signal input port and an optical signal output port, and is used to convert the fourth electrical signal into a second optical signal and the first optical signal into a third electrical signal. The second transceiver chip includes a second chip interconnect interface, which is electrically connected to a conductive channel in the packaging substrate through a conductive via in the second photonic integrated circuit chip.

[0018] In some embodiments, the second photonic integrated circuit chip further includes a light source input port and an optical modulator, wherein the light source input port is used to receive an optical carrier, and the optical modulator is used to modulate the optical carrier into a second optical signal according to a fourth electrical signal.

[0019] In some embodiments, the second photonic integrated circuit chip further includes a photodetector for converting the first optical signal into a third electrical signal.

[0020] In some embodiments, the first chip interconnect interface and the second chip interconnect interface are UCIe interfaces.

[0021] According to one aspect of this disclosure, a computing device is provided, comprising: a printed circuit board; and the aforementioned computing chip package structure mounted on the printed circuit board.

[0022] According to one aspect of this disclosure, a resource pooling system is provided, comprising: a memory resource pool including a plurality of the aforementioned memory devices; a computing resource pool including a plurality of the aforementioned computing devices; and an optical switch optically connected to each memory device in the memory resource pool and each computing device in the computing resource pool, wherein the optical switch is configured to select one or more computing devices from the computing resource pool and one or more memory devices from the memory resource pool for link connection via a reconfigurable optical path, thereby forming a configurable computing system.

[0023] According to embodiments of this disclosure, the bandwidth and connectable memory capacity of a computing device can be increased, the transmission bandwidth and capacity of the memory device can be increased and transmission losses can be reduced, the capability and capacity of a resource pooling system can be improved, and resource pools can be flexibly combined according to workload. Attached Figure Description

[0024] Figure 1A shows a schematic plan view of an example computing chip package structure according to an embodiment of the present disclosure.

[0025] Figure 1B shows a schematic cross-sectional view of an example computing chip package structure according to an embodiment of the present disclosure.

[0026] Figure 2 shows a functional block diagram of an example optical interconnect module of a computing chip package structure according to an embodiment of the present disclosure.

[0027] Figure 3 shows a schematic plan view of an example computing device according to an embodiment of the present disclosure.

[0028] Figure 4A shows a schematic plan view of an example memory chip package structure according to an embodiment of the present disclosure.

[0029] Figure 4B shows a schematic cross-sectional view of an example memory chip package structure according to an embodiment of the present disclosure.

[0030] Figure 5 shows a functional block diagram of an example optical interconnect module of a memory chip package structure according to an embodiment of the present disclosure.

[0031] Figure 6 shows a schematic plan view of an example memory device according to an embodiment of the present disclosure.

[0032] Figure 7 shows a schematic plan view of another example of a memory device according to an embodiment of the present disclosure.

[0033] Figure 8 shows a schematic diagram of an example of a resource pooling system according to an embodiment of the present disclosure. Detailed Implementation

[0034] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0035] It should be noted that the various components or parts described in the various embodiments of this disclosure are merely illustrative. In some cases, some components or parts may be omitted, or some components or parts may be replaced with other components or parts that have the same or similar functions, or additional components or parts may be added.

[0036] Furthermore, the various components or assemblies described in the different embodiments of this disclosure are merely for ease of description and do not imply actual physical separation or combination, nor do they imply that such separation or combination is necessary. Those skilled in the art can arbitrarily disassemble or combine the various components or assemblies according to actual needs.

[0037] Without departing from the inventive concept of this disclosure, any of the above variations or combinations fall within the protection scope of this disclosure.

[0038] Figure 1A shows a schematic plan view of an example of a computing chip package structure 10 according to an embodiment of the present disclosure. Figure 1B shows a schematic cross-sectional view of an example of a computing chip package structure 10 according to an embodiment of the present disclosure. Figure 2 shows a functional block diagram of an example of an optical interconnect module 120 of the computing chip package structure 10 according to an embodiment of the present disclosure.

[0039] Referring to Figures 1A to 2, according to an embodiment of the present disclosure, the computing chip package structure 10 may include a package substrate 180, a computing chip 100, and an optical interconnect module 120. The computing chip 100 is disposed on the package substrate 180 and includes a first chip interconnect interface 101. The optical interconnect module 120 is disposed on the package substrate 180 and includes a second chip interconnect interface 121, an optical signal input port 123, and an optical signal output port 125. The first chip interconnect interface 101 and the second chip interconnect interface 121 can be electrically connected to each other through a conductive channel 181 in the package substrate 180. The optical interconnect module 120 can convert a first optical signal OS11 received from the optical signal input port 123 into a first electrical signal ES11 output to the computing chip 100, and convert a second electrical signal ES12 received from the computing chip 100 into a second optical signal OS12 output from the optical signal output port 125.

[0040] The computing chip 100 can be used to perform calculations and processing on input data and output processed data. The computing chip 100 may include one or more first chip interconnect interfaces 101. For example, FIG1A shows a computing chip 100 including six first chip interconnect interfaces 101, but this disclosure is not limited thereto. The computing chip 100 may have fewer than or more than six first chip interconnect interfaces 101. According to embodiments of this disclosure, the computing chip 100 may include one or more of, for example, a central processing unit (CPU), a graphics processing unit (GPU), a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a neural network processing unit (NPU), a tensor processing unit (TPU), an intelligent processing unit (IPU), and a deep learning processing unit (DPU), but this disclosure is not limited thereto.

[0041] The optical interconnect module 120 can be used to perform photoelectric / electro-optical conversion of signals. The optical interconnect module 120 can communicate with the computing chip 100 via a second chip interconnect interface 121. According to embodiments of this disclosure, one or more optical interconnect modules 120 may be provided on the package substrate 180. According to embodiments of this disclosure, each first chip interconnect interface 101 of the computing chip 100 may be electrically connected to one or more (e.g., two) optical interconnect modules 120.

[0042] According to embodiments of this disclosure, each first chip interconnect interface 101 of the computing chip 100 may include any number of data transmission channels. Each second chip interconnect interface 121 of the optical interconnect module 120 may also include any number of data transmission channels. When each first chip interconnect interface 101 of the computing chip 100 is electrically connected to two optical interconnect modules 120, within the same computing chip package structure 10, the total number of data transmission channels of the first chip interconnect interface 101 and the total number of data transmission channels of the second chip interconnect interface 121 can match (e.g., be equal). For example, as illustrated in FIG1A, each first chip interconnect interface 101 is connected to two corresponding second chip interconnect interfaces 121. In this case, the number of data transmission channels of each first chip interconnect interface 101 and the total number of data transmission channels of the two corresponding second chip interconnect interfaces 121 can match (e.g., be equal) in number, and can be electrically connected via conductive channels 181 in the package substrate 180, respectively. For simplicity, in Figure 1A, only one conductive channel 181 is schematically shown between each second chip interconnect interface 121 and a corresponding first chip interconnect interface 101 to illustrate the connection therebetween. In Figure 1B, however, it is schematically shown that the second chip interconnect interface 121 has four data transmission channels, which are connected to the four data transmission channels of the first chip interconnect interface 101 via four conductive channels 181, respectively. However, it should be understood that Figure 1B does not show all the data transmission channels of the first chip interconnect interface 101. For example, if each first chip interconnect interface 101 is connected to two second chip interconnect interfaces 121 and each second chip interconnect interface 121 has four data transmission channels, each first chip interconnect interface 101 may have eight data transmission channels. However, the correspondence between chip interconnect interfaces 101 and 121 and the number of their respective data transmission channels are not limited thereto.

[0043] According to embodiments of this disclosure, the first chip interconnect interface 101 of the computing chip 100 and the second chip interconnect interface 121 of the optical interconnect module 120 can be Universal Chip Interconnect Express (UCIe) interfaces. UCIe mainly includes a physical layer, an adapter layer, and a protocol layer. The physical layer can be an electrical interface of the encapsulation medium, used to realize parameter exchange and negotiation between chips. The adapter layer can be responsible for link management functions and protocol arbitration and negotiation. The protocol layer can implement one or more UCIe-supported protocols, such as PCI Express, CXL, and / or streaming protocols. The UCIe interface can support high-speed data transmission rates, minimize latency, and dynamically add or remove chips to achieve seamless scalability as workload requirements change. Through the chip interconnect interface, a high-bandwidth, low-latency, seamlessly scalable internal interconnect can be achieved between the computing chip 100 and the optical interconnect module 120.

[0044] According to embodiments of this disclosure, the computing chip 100 and the optical interconnect module 120 can be flip-chip mounted on the packaging substrate 180. At the electrical connection points between the computing chip 100 and the packaging substrate 180, bumps can be provided on the computing chip 100 and / or the packaging substrate 180 to achieve a good electrical connection. At the electrical connection points between the optical interconnect module 120 and the packaging substrate 180, bumps can be provided on the optical interconnect module 120 and / or the packaging substrate 180 to achieve a good electrical connection.

[0045] According to embodiments of this disclosure, the optical interconnect module 120 may include a photonic integrated circuit chip 140 and a transceiver chip 160 stacked on the photonic integrated circuit chip 140. The transceiver chip 160 may be used to convert a third electrical signal ES13 from the photonic integrated circuit chip 140 into a first electrical signal ES11, and to convert a second electrical signal ES12 from the computing chip 100 into a fourth electrical signal ES14 sent to the photonic integrated circuit chip 140. The photonic integrated circuit chip 140 may include an optical signal input port 123 and an optical signal output port 125, and may be used to convert the fourth electrical signal ES14 from the transceiver chip 160 into a second optical signal OS12 output from the optical signal output port 125, and to convert the first optical signal OS11 input from the optical signal input port 123 into the third electrical signal ES13 sent to the transceiver chip 160. The transceiver chip 160 may include a second chip interconnect interface 121, which can be electrically connected to the conductive channel 181 in the package substrate 180 through the conductive via 141 in the photonic integrated circuit chip 140.

[0046] According to embodiments of this disclosure, the first electrical signal ES11 and the second electrical signal ES12 can be transmitted between the transceiver chip 160 and the computing chip 100 of the optical interconnect module 120 through the conductive via 141 in the photonic integrated circuit chip 140 and the conductive channel 181 in the packaging substrate 180. The third electrical signal ES13 and the fourth electrical signal ES14 can be transmitted between the photonic integrated circuit chip 140 and the transceiver chip 160 through a conductive line (not shown) between the photonic integrated circuit chip 140 and the transceiver chip 160. The first optical signal OS11 can be input to the photonic integrated circuit chip 140 through the optical signal input port 123, and the second optical signal OS12 can be output from the photonic integrated circuit chip 140 through the optical signal output port 125.

[0047] According to embodiments of this disclosure, the transceiver chip 160 can be flip-chip mounted on the photonic integrated circuit chip 140. At the electrical connection between the transceiver chip 160 and the photonic integrated circuit chip 140, bumps can be provided on the transceiver chip 160 and / or the photonic integrated circuit chip 140 to achieve a good electrical connection.

[0048] According to embodiments of this disclosure, the materials used to form the photonic integrated circuit chip 140 may include silicon, silicon nitride, indium phosphide, gallium arsenide, lithium niobate, or combinations thereof, but the disclosure is not limited thereto. According to embodiments of this disclosure, the conductive vias 141 in the photonic integrated circuit chip 140 can be formed by etching the photonic integrated circuit chip 140 using an etching process to form through-holes in the photonic integrated circuit chip 140, and then filling the through-holes with conductive material using processes such as physical vapor deposition, chemical vapor deposition, and atomic layer deposition. Similarly, the conductive channels 181 in the packaging substrate 180 can be formed by etching the packaging substrate 180 using an etching process to form trenches in the packaging substrate 180, and then filling the trenches with conductive material using processes such as physical vapor deposition, chemical vapor deposition, and atomic layer deposition. However, the processes for forming the conductive vias 141 and conductive channels 181 are not limited to the processes described above.

[0049] Since the conductive channel 181 in the packaging substrate 180 and the conductive via 141 in the photonic integrated circuit chip 140 can have low signal transmission loss, the chip interconnect interfaces 101 and 121 can have low power consumption and high bandwidth density.

[0050] An example of the optical interconnect module 120 is described in detail below with reference to FIG2.

[0051] According to embodiments of this disclosure, the optical interconnect module 120 may include a photonic integrated circuit chip 140 and a transceiver chip 160. The photonic integrated circuit chip 140 may include an optical signal input port 123 and an optical signal output port 125. The transceiver chip 160 may include a second inter-chip interconnect interface 121. The photonic integrated circuit chip 140 can convert a first optical signal OS11 input from the optical signal input port 123 into a third electrical signal ES13 provided to the transceiver chip 160. The transceiver chip 160 can convert the third electrical signal ES13 back into the first electrical signal ES11 and output the first electrical signal ES11 to the computing chip 100 through the second inter-chip interconnect interface 121. The transceiver chip 160 can receive a second electrical signal ES12 from the computing chip 100 through the second inter-chip interconnect interface 121 and convert the second electrical signal ES12 into a fourth electrical signal ES14 provided to the photonic integrated circuit chip 140. The photonic integrated circuit chip 140 can convert the fourth electrical signal ES14 back into the second optical signal OS12 output from the optical signal output port 125.

[0052] According to embodiments of this disclosure, the photonic integrated circuit chip 140 may further include a light source input port 127 and an optical modulator 143. The light source input port 127 may be used to receive an optical carrier L. The optical modulator 143 may be used to modulate the optical carrier L into a second optical signal OS12 according to a fourth electrical signal ES14.

[0053] The optical carrier L received through the light source input port 127 can be modulated by the optical modulator 143. The optical modulator 143 can modulate the amplitude, phase and other characteristics of the optical carrier L input from the light source input port 127 according to the fourth electrical signal ES4, thereby modulating the information carried in the second electrical signal ES12 onto the optical carrier L to form the second optical signal OS12.

[0054] According to embodiments of this disclosure, the transceiver chip 160 may include a serial-to-parallel / parallel-to-serial conversion circuit, a driver 162, and an amplifier 166. The parallel-to-serial converter 167 in the serial-to-parallel / parallel-to-serial conversion circuit can be used to convert a parallel second electrical signal ES12 from the computing chip 100 into a serial fifth electrical signal ES15 provided to the driver 162. The driver 162 can then send a fourth electrical signal ES14 to the optical modulator 143 based on the fifth electrical signal ES15 to drive the optical modulator 143. The amplifier 166 can amplify a third electrical signal ES13 from the photonic integrated circuit chip 140 to provide it as a sixth electrical signal ES16 to the serial-to-parallel converter 168 in the serial-to-parallel / parallel-to-serial conversion circuit. The serial-to-parallel converter 168 can be used to convert the serial sixth electrical signal ES16 from the amplifier 166 into a parallel first electrical signal ES11 provided to the computing chip 100. In addition, the transceiver chip 160 may also include a controller 164, which can be used to control other components in the transceiver chip 160, such as a serial-to-parallel / parallel-to-serial conversion circuit, a driver 162, an amplifier 166, and other components not shown. It should be noted that the specific structure of the transceiver chip 160 is not limited to the embodiment shown in FIG2, and it can adopt any circuit structure capable of converting electrical signals in accordance with requirements.

[0055] Typical examples of the optical modulator 143 may include integrated photonic modulators based on silicon, indium phosphide, thin-film lithium niobate, or polymers, and structurally may be microring modulators, Mach-Zehnder modulators, or electroabsorption modulators. However, this disclosure is not limited thereto, and the optical modulator 143 may be implemented using any suitable components in the art.

[0056] For example, if the optical modulator 143 is an electroabsorption modulator, the controller 164 can control the driver 162 to drive the switch of the optical modulator 143 so that the optical modulator 143 absorbs the optical carrier to be modulated (e.g., corresponding to output logic "0") or does not absorb the optical carrier to be modulated (e.g., corresponding to output logic "1"). In this way, the intensity and phase of the final output light can be controlled, so that information can be modulated or loaded onto the second optical signal OS12.

[0057] Although Figures 1A and 2 show the optical interconnect module 120 including a light source input port 127 for receiving an optical carrier L, this disclosure is not limited thereto. Optionally, the optical carrier modulated by the optical modulator 143 can be generated internally within the optical interconnect module 120. In this case, the optical interconnect module 120 may not include the light source input port 127, but may instead include an optical transmitter for transmitting the optical carrier to be modulated. For example, the optical transmitter may be disposed in the photonic integrated circuit chip 140.

[0058] According to embodiments of this disclosure, the photonic integrated circuit chip 140 may further include a photodetector 144 for converting the first optical signal OS11 into a third electrical signal ES13 to be transmitted to the transceiver chip 160.

[0059] According to embodiments of this disclosure, the photodetector 144 can be various types of photodiodes, such as photomultiplier tubes (PMTs), avalanche photodiodes (APDs), silicon photomultiplier tubes (SiPMs), etc. The amplifier 166 can be a conventional transimpedance amplifier (TIA), or various types of amplifiers based on similar or other principles. However, this disclosure is not limited thereto, and the photodetector 144 and amplifier 166 can be implemented using any suitable components in the art.

[0060] While some specific configurations of the photonic integrated circuit chip 140 and the transceiver chip 160 have been described above, this disclosure is not limited thereto. At least some of the aforementioned devices may be omitted from the photonic integrated circuit chip 140 and the transceiver chip 160, or additional devices may be included. For example, the transceiver chip 160 may omit the amplifier 166 and / or the serial-to-parallel / parallel-to-serial conversion circuit. As another example, the transceiver chip 160 may additionally include an analog-to-digital / digital-to-analog conversion circuit, in which the digital-to-analog converter can be used to convert digital electrical signals from the parallel-to-serial converter 167 into analog electrical signals provided to the driver 162, and the analog-to-digital converter in the analog-to-digital / digital-to-analog conversion circuit can be used to convert analog electrical signals from the amplifier 166 into digital electrical signals provided to the serial-to-parallel converter 168.

[0061] According to embodiments of this disclosure, the optical interconnect module 120 can communicate optically with devices outside the computing chip package structure 10 via optical fiber 190. According to embodiments of this disclosure, optical fiber 190 can be single-mode optical fiber to reduce transmission loss and transmission dispersion, thereby increasing transmission distance and improving transmission speed. However, this disclosure is not limited thereto, and optical fiber 190 can also be multimode optical fiber.

[0062] Figure 3 shows a schematic plan view of an example of a computing device 30 according to an embodiment of the present disclosure.

[0063] According to embodiments of this disclosure, the computing device 30 may include a printed circuit board (PCB) 300 and a computing chip package structure 10 mounted on the PCB 300. For example, the package substrate 180 of the computing chip package structure 10 may be mounted on the PCB. A power supply circuit may be provided on the PCB to supply power to the computing chip package structure 10.

[0064] Figure 4A shows a schematic plan view of an example of a memory chip package structure 40 according to an embodiment of the present disclosure. Figure 4B shows a schematic cross-sectional view of an example of a memory chip package structure 40 according to an embodiment of the present disclosure. Figure 5 shows a functional block diagram of an example of an optical interconnect module 420 of the memory chip package structure 40 according to an embodiment of the present disclosure.

[0065] Referring to Figures 4A to 5, according to embodiments of the present disclosure, the memory chip package structure 40 may include a package substrate 480, an optical interconnect module 420, a photonic integrated circuit chip 440, and a memory chip module 410. The optical interconnect module 420 may include a photoelectric signal conversion module 430 and a transceiver chip 460. The photonic integrated circuit chip 440 may be disposed on the package substrate 480 and includes the photoelectric signal conversion module 430. The memory chip module 410 may be disposed on the photonic integrated circuit chip 440 and includes a first electrical interconnect interface 401. The transceiver chip 460 may be disposed on the photonic integrated circuit chip 440 and includes a second electrical interconnect interface 461 and an electrical signal conversion unit 469. The first electrical interconnect interface 401 and the second electrical interconnect interface 461 may be electrically connected to each other through a conductive channel 442 in the photonic integrated circuit chip 440. The electrical signal conversion unit 469 of the transceiver chip 460 can be used to convert the first electrical signal ES41 from the memory chip module 410 into a second electrical signal ES42, and to convert the third electrical signal ES43 from the photoelectric signal conversion module 430 into a fourth electrical signal ES44 sent to the memory chip module 410. The photoelectric signal conversion module 430 may include an optical signal input port 423 and an optical signal output port 425, for converting the second electrical signal ES42 received from the transceiver chip 460 into a first optical signal OS41 output from the optical signal output port 425, and converting the second optical signal OS42 received from the optical signal input port 423 into a third electrical signal ES43 sent to the transceiver chip 460.

[0066] According to embodiments of this disclosure, the photonic integrated circuit chip 440 is made of semiconductor materials, such as silicon or group III-IV semiconductors. A photoelectric signal conversion module 430 can be formed in the photonic integrated circuit chip 440, thereby forming an optical interconnect module 420 together with a transceiver chip 460 disposed on the photonic integrated circuit chip 440.

[0067] According to embodiments of this disclosure, similar to the chip interconnect interfaces 101 and 121 in the computing chip package structure 10 described with reference to FIGS. 1A to 2, the electrical interconnect interfaces 401 and 461 in the memory chip package structure 40 can each include any number of data transmission channels. The data transmission channels of each first electrical interconnect interface 401 and the corresponding data transmission channels of a second electrical interconnect interface 461 can be matched in number (e.g., equal) and can be electrically connected via conductive channels 442 in the photonic integrated circuit chip 440, respectively. For simplicity, FIG. 4B schematically shows that both electrical interconnect interfaces 401 and 461 include four data transmission channels, and each data transmission channel is connected to each other via four conductive channels 442, but this is merely an example, and this disclosure is not limited thereto.

[0068] According to embodiments of this disclosure, as shown in Figures 4B and 5, the first electrical signal ES41 and the fourth electrical signal ES44 can be transmitted between the transceiver chip 460 and the memory chip module 410 of the optical interconnect module 420 via the conductive channel 442 in the photonic integrated circuit chip 440. The second electrical signal ES42 and the third electrical signal ES43 can be transmitted between the photoelectric signal conversion module 430 and the transceiver chip 460 via the conductive lines in the photoelectric signal conversion module 430 and the transceiver chip 460. For example, the photoelectric signal conversion module 430 is exposed on the surface of the photonic integrated circuit chip 440 facing the transceiver chip 460, and the transceiver chip 460 can be flip-chip mounted on the photonic integrated circuit chip 440 to face the photoelectric signal conversion module 430. Bumps can be provided at the electrical connection between the photoelectric signal conversion module 430 and the transceiver chip 460, so that the two are electrically connected to each other through the bumps. The first optical signal OS41 can be output from the photoelectric signal conversion module 430 through the optical signal output port 425, and the second optical signal OS42 can be input to the photoelectric signal conversion module 430 through the optical signal input port 423.

[0069] According to embodiments of this disclosure, a power supply interface (not shown) may be arranged on the packaging substrate 480. This power supply interface can supply power to the transceiver chip 460 and the memory chip module 410 through conductive vias 441 in the photonic integrated circuit chip 440. Optionally, in addition to the power supply interface, other circuits may also be arranged on the packaging substrate 480. These circuits can also be electrically connected to the transceiver chip 460 and the memory chip module 410 through conductive vias 441 in the photonic integrated circuit chip 440.

[0070] According to embodiments of the present disclosure, the conductive via 441 in the photonic integrated circuit chip 440 can be formed in a manner similar to that of the conductive via 141 described with reference to FIG1A to FIG2, and the conductive channel 442 in the photonic integrated circuit chip 440 can be formed in a manner similar to that of the conductive channel 181 described with reference to FIG1A to FIG2.

[0071] According to embodiments of this disclosure, the memory chip module 410 and the transceiver chip 460 can be flip-chip mounted on the surface of the photonic integrated circuit chip 440 facing away from the packaging substrate 480. The first electrical interconnect interface 401 of the memory chip module 410 and the second electrical interconnect interface 461 of the transceiver chip 460 can be electrically connected to the conductive channel 442 in the photonic integrated circuit chip 440 via bumps.

[0072] Typically, computing chips have relatively high single-channel bandwidth (e.g., 32 Gb / s), while memory chips have relatively low bandwidth. To match the bandwidth of the computing and memory chips, a large number of connection points (e.g., bumps) are required on the memory chip side. However, since the packaging substrate is usually formed of organic materials, it is difficult to provide a high density of connection points on organic materials, which limits the connection point density configured for memory chips directly mounted on the packaging substrate. According to embodiments of this disclosure, the memory chip module 410 is arranged on the photonic integrated circuit chip 440, thus allowing for a denser configuration of connection points for the memory chip module 410, thereby improving the overall bandwidth of the memory chip module 410. Furthermore, since the conductive vias 441 and conductive paths 442 in the photonic integrated circuit chip 440 can have low signal transmission loss, the electrical interconnects 104 and 461 can have low power consumption and high bandwidth density.

[0073] According to embodiments of this disclosure, the memory chip module 410 may include one or more memory chip components 400, each memory chip component 400 including a first electrical interconnect interface 401. For example, FIG4A shows the memory chip module 410 including two memory chip components 400, but this disclosure is not limited thereto. The memory chip module 410 may include three or more memory chip components 400. When the memory chip module 410 includes multiple memory chip components 400, the transceiver chip 460 may further include a switching unit 470. The switching unit 470 may be used to switchably connect multiple memory chip components 400 to an electrical signal conversion unit 469. For example, the switching unit 470 may select one memory chip component to be electrically connected to the electrical signal conversion unit 469 at a certain point in time according to a control signal from the computing chip.

[0074] By providing a switching unit 470 in the memory chip package structure 40, an optical interconnect module 420 can be connected to multiple memory chip components 400, thereby expanding the memory capacity.

[0075] An example of the optical interconnect module 420 is described in detail below with reference to FIG5.

[0076] According to embodiments of this disclosure, the optical interconnect module 420 may include an optoelectronic signal conversion module 430 and a transceiver chip 460. The optoelectronic signal conversion module 430 may include an optical signal input port 423 and an optical signal output port 425. The transceiver chip 460 may include a second electrical interconnect interface 461 and an electrical signal conversion unit 469. The optoelectronic signal conversion module 430 can convert a second optical signal OS42 input from the optical signal input port 423 into a third electrical signal ES43 provided to the transceiver chip 460. The transceiver chip 460 can convert the third electrical signal ES43 into a fourth electrical signal ES44 through the electrical signal conversion unit 469, and output the fourth electrical signal ES44 to the memory chip module 410 through the second electrical interconnect interface 461. The transceiver chip 460 can receive a first electrical signal ES41 from the memory chip module 410 through the second electrical interconnect interface 461, and convert the first electrical signal ES41 into a second electrical signal ES42 provided to the optoelectronic signal conversion module 430 through the electrical signal conversion unit 469. The photoelectric signal conversion module 430 can convert the second electrical signal ES42 into the first optical signal OS41 output from the optical signal output port 425.

[0077] According to embodiments of this disclosure, the photoelectric signal conversion module 430 may further include a light source input port 427 and an optical modulator 431. The light source input port 427 may be used to receive an optical carrier L, and the optical modulator 431 may be used to modulate the optical carrier L into a first optical signal ES41 according to a second electrical signal ES42.

[0078] The optical modulator 431 of the photoelectric signal conversion module 430 can be substantially the same as the optical modulator 143 of the photonic integrated circuit chip 140 described with reference to Figures 1A to 2, so repeated descriptions are omitted here.

[0079] According to embodiments of this disclosure, the electrical signal conversion unit 469 of the transceiver chip 460 may include a serial-to-parallel / parallel-to-serial conversion circuit, a driver 462, and an amplifier 466. The parallel-to-serial converter 467 in the serial-to-parallel / parallel-to-serial conversion circuit can be used to convert a parallel first electrical signal ES41 from the memory chip module 410 into a serial seventh electrical signal ES47 provided to the driver 462. The driver 462 can then send a second electrical signal ES42 to the optical modulator 431 based on the seventh electrical signal ES47 to drive the optical modulator 431. The amplifier 466 can amplify a third electrical signal ES43 from the photoelectric signal conversion module 430 to provide it as an eighth electrical signal ES48 to the serial-to-parallel converter 468 in the serial-to-parallel / parallel-to-serial conversion circuit. The serial-to-parallel converter 468 can then convert the serial eighth electrical signal ES48 from the amplifier 466 into a parallel fourth electrical signal ES44 provided to the memory chip module 410. Furthermore, the transceiver chip 460 may also include a controller 464, which can be used to control other components in the transceiver chip 460, such as a serial-to-parallel / parallel-to-serial conversion circuit, a driver 462, an amplifier 466, and other components not shown. It should be noted that the specific structure of the transceiver chip 460 is not limited to the embodiment shown in FIG5; it can employ any circuit structure capable of performing the required conversion of electrical signals.

[0080] Although Figures 4A and 5 show the optical interconnect module 420 including a light source input port 427 for receiving an optical carrier L, this disclosure is not limited thereto. Optionally, the optical carrier modulated by the optical modulator 431 can be generated internally within the optical interconnect module 420. In this case, the optical interconnect module 420 may not include the light source input port 427, but may instead include an optical transmitter for transmitting the optical carrier to be modulated. For example, the optical transmitter may be disposed in the photoelectric signal conversion module 430.

[0081] Furthermore, according to embodiments of this disclosure, the photoelectric signal conversion module 430 may also include a photodetector 432 for converting a second optical signal OS42 input from the optical signal input port 423 into a third electrical signal ES43 to be sent to the transceiver chip 460.

[0082] The photodetector 432 and amplifier 466 are substantially the same as the photodetector 144 and amplifier 166 described with reference to Figures 1A to 2, respectively, so repeated descriptions are omitted here.

[0083] While some specific configurations of the transceiver chip 460 and the photoelectric signal conversion module 430 have been described above, this disclosure is not limited thereto. At least some of the aforementioned devices may be omitted from the transceiver chip 460 and the photoelectric signal conversion module 430, or additional devices may be included. For example, the transceiver chip 460 may omit the amplifier 466 and / or the serial-to-parallel / parallel-to-serial conversion circuit. As another example, the electrical signal conversion unit 469 of the transceiver chip 460 may additionally include an analog-to-digital / digital-to-analog conversion circuit, in which a digital-to-analog converter converts the digital electrical signal from the parallel-to-serial converter 467 into an analog electrical signal provided to the driver 462, and an analog-to-digital converter converts the analog electrical signal from the amplifier 466 into a digital electrical signal provided to the serial-to-parallel converter 468.

[0084] According to embodiments of this disclosure, the optical interconnect module 420 can communicate optically with devices outside the memory chip package structure 40 via optical fiber 490. According to embodiments of this disclosure, optical fiber 490 can be single-mode optical fiber to reduce transmission loss and transmission dispersion, thereby increasing transmission distance and improving transmission speed. However, this disclosure is not limited thereto, and optical fiber 490 can also be multimode optical fiber.

[0085] According to embodiments of this disclosure, a memory chip module 410 may include at least one memory chip assembly 400, each memory chip assembly 400 may include a memory logic chip 403 and one or more memory chips 405 stacked on the memory logic chip 403. The memory logic chip 403 may include logic circuitry for logic operation, signal processing, memory control, etc. One or more memory chips 405 may be stacked one on top of another using a flip-chip process.

[0086] According to embodiments of this disclosure, the one or more memory chips 405 in the memory chip module 410 may be HBM chips. The first electrical interconnect interface 401 and the second electrical interconnect interface 461 may be high-bandwidth memory interconnect (HBM) interfaces, such as HBM PHY, thereby supporting high-speed data transfer between chips.

[0087] Figure 6 shows a schematic plan view of an example of a memory device 60 according to an embodiment of the present disclosure.

[0088] According to embodiments of this disclosure, the memory device 60 may include a PCB 600 and a memory chip package structure 40 mounted on the PCB 600. For example, the package substrate 480 of the memory chip package structure 40 may be mounted on the PCB 600.

[0089] Figure 7 shows a schematic plan view of another example of a memory device 60A according to an embodiment of the present disclosure.

[0090] Referring to FIG7, according to an embodiment of the present disclosure, the memory device 60A may include a PCB 600, a memory chip package structure 40A mounted on the PCB 600, and an additional memory chip assembly 465. The memory chip package structure 40A may be the same as the memory chip package structure 40 shown in FIGS. 4A and 4B, except that the memory chip package structure 40A also includes a third electrical interconnect interface 463. Identical elements are indicated by the same reference numerals, therefore repeated descriptions will be omitted below, and the differences will be mainly described.

[0091] The transceiver chip 460A of the memory chip package structure 40A may include a second electrical interconnect interface 461, which is electrically connected to the first electrical interconnect interface 401 of the memory chip module 410. Furthermore, the transceiver chip 460A may also include a third electrical interconnect interface 463 for electrical connection to an additional memory chip assembly 465, thereby enabling the optical interconnect module 420 to convert electrical signals from the additional memory chip assembly 465 into optical signals for transmission through an optical signal output port, and to convert optical signals from the optical signal input port into electrical signals for transmission to the additional memory chip assembly 465.

[0092] According to embodiments of this disclosure, the transceiver chip 460A may include one or more third electrical interconnect interfaces 463, and one or more additional memory chip components 465 may be disposed on the PCB 600. The additional memory chip components 465 may be electrically connected to the third electrical interconnect interfaces 463 via conductive lines (not shown) in the PCB 600, conductive channels (not shown) or conductive vias (not shown) in the package substrate 480, and conductive vias 441 in the photonic integrated circuit chip 440 (see FIG. 4B). The third electrical interconnect interfaces 463 may include any number of data transmission channels, the number of which matches (e.g., is equal to) the number of conductive lines in the PCB 600, such that each data transmission channel is connected to a corresponding conductive line. The number of third electrical interconnect interfaces 463 and additional memory chip components 465 shown in FIG. 7 is merely an example, and this disclosure is not limited thereto.

[0093] For example, the third electrical interconnect interface 463 can be a Double Data Rate (DDR) interface to improve data transfer efficiency. For example, the additional memory chip assembly 465 can be a dual in-line (DIMM) memory module, which can be installed on PCB 600 by inserting it into a slot in PCB 600. However, this disclosure is not limited thereto, and the additional memory chip assembly 465 can have various package types, such as Thin Small Outline Package (TSOP), Ball Grid Array (BGA), Chip Scale Package (CSP), etc.

[0094] By providing a third electrical interconnect interface 463, the memory chip package structure 40A can be connected to external additional memory chip components, thereby expanding the capacity of the memory chip package structure 40A.

[0095] Figure 8 shows a schematic diagram of an example of a resource pooling system 8 according to an embodiment of the present disclosure.

[0096] Referring to FIG8, according to an embodiment of the present disclosure, the resource pooling system 8 may include a memory resource pool, a computing resource pool, and an optical switch 802. The memory resource pool may include multiple memory devices 60 or 60A as described with reference to FIGS. 6 and 7. The computing resource pool may include multiple computing devices 30 as described with reference to FIG3. The optical switch 802 may be optically connected to each memory device 60 or 60A in the memory resource pool and each computing device 30 in the computing resource pool. The optical switch 802 may be configured to select one or more computing devices 30 from the computing resource pool and one or more memory devices 60 or 60A from the memory resource pool for link connection via a reconfigurable optical path, thereby forming a configurable computing system.

[0097] The optical switch 802 may have multiple optical ports (not shown), and is connected to the optical signal input port 423 and optical signal output port 425 of the memory device 60 or 60A in the memory resource pool, and the optical signal input port 123 and optical signal output port 125 of the computing device 30 in the computing resource pool, respectively, via optical fibers 190 and 490, for resource allocation and combination.

[0098] According to embodiments of this disclosure, optical switch 802 can reconstruct optical paths to select one or more computing devices 30 from a computing resource pool and one or more memory devices 60 or 60A from a memory resource pool for link connection. Then, optical switch 802 can transmit optical signals between the selected computing device 30 and the selected memory device 60 or 60A by transmitting optical signals within itself.

[0099] According to embodiments of this disclosure, the optical switch 802 can rearrange the optical path switching bandwidth transmission paths therein to achieve fully reconfigurable interconnection between each pair of computing devices and memory devices in each resource pool.

[0100] According to embodiments of this disclosure, the optical switch 802 can control the optical path based on different physical principles, including piezoelectric, microelectromechanical, and electro-optical. The optical switch 802 can be composed of a series of free-space optical components or a series of integrated optical components.

[0101] Specifically, for example, the optical switch 802 shown in FIG8 can transmit signals between a selected computing device 30 and a selected memory device 60 or 60A by performing the following operations.

[0102] For example, after selecting computing device 30 from the computing resource pool and memory device 60 or 60A from the memory resource pool, optical switch 802 can rearrange internal optical paths to provide optical path links for the selected computing device 30 and the selected memory device 60 or 60A.

[0103] Data A from the selected computing device 30 is first sent from the computing chip 100 to the optical interconnect module 120 via the chip interconnect interface. Then, the optical interconnect module 120 converts the data A in electrical signal form into data A in optical signal form.

[0104] Next, the converted optical signal data A is fed to the corresponding optical port of the optical switch 802 via optical fiber 190. The optical switch 802, through the arranged optical path link, provides the optical signal data A to the optical interconnect module 420 or 420A of the selected memory device 60 or 60A via optical fiber 490 for conversion into electrical signal data A. The converted electrical signal data A is then provided to the memory chip module 410 via the electrical interconnect interface. The memory chip module 410 can then store the electrical signal data A into the corresponding memory chip 405, thereby completing the data A storage operation.

[0105] The above examples illustrate how data is transferred from computing device 30 in the computing resource pool to memory device 60 or 60A in the memory resource pool. It should be noted that the data transfer process in the reverse direction is similar. For example, data B can be transferred from memory device 60 or 60A in the memory resource pool to computing device 30 in the computing resource pool in a similar manner to complete the data reading process. The optical-to-electrical / electrical-to-optical conversion process is similar and will not be repeated here.

[0106] By employing an optical switch 802 in the resource pooling system, signal transmission can be completed within the optical switch 802 without optical-to-electrical or electro-optical conversion. Therefore, compared to electrical switching, all-optical switching eliminates the energy consumption and latency of optical-to-electrical or electro-optical conversion and is unaffected by data modulation rates and formats, enabling more flexible data transmission. Furthermore, optical switches allow for dynamic sharing of resource pools, enabling flexible combinations based on specific workload requirements. Decomposing and combining computing and memory resources can achieve higher performance and efficiency.

[0107] In the foregoing description, embodiments of the present disclosure have been described in conjunction with the accompanying drawings. It should be understood that the above embodiments are merely illustrative, and those skilled in the art should understand that the combination of constituent elements and processes of the present embodiments can be modified in various ways, and such modifications also fall within the scope of the present disclosure.

Claims

1. A memory chip packaging structure, comprising: Packaging substrate; The optical interconnect module includes a photoelectric signal conversion module and a first transceiver chip; A first photonic integrated circuit chip is disposed on the packaging substrate and includes the photoelectric signal conversion module; as well as The memory chip module is disposed on the first photonic integrated circuit chip and includes a first electrical interconnect interface, wherein The first transceiver chip is disposed on the first photonic integrated circuit chip and includes a second electrical interconnect interface and an electrical signal conversion unit. The first electrical interconnect interface and the second electrical interconnect interface are electrically connected to each other through conductive channels in the first photonic integrated circuit chip. The electrical signal conversion unit is used to convert a first electrical signal from the memory chip module into a second electrical signal, and to convert a third electrical signal from the photoelectric signal conversion module into a fourth electrical signal to be sent to the memory chip module. The photoelectric signal conversion module includes an optical signal input port and an optical signal output port, and is used to convert the second electrical signal received from the first transceiver chip into a first optical signal output from the optical signal output port, and to convert the second optical signal received from the optical signal input port into the third electrical signal sent to the first transceiver chip.

2. The memory chip packaging structure according to claim 1, wherein... The packaging substrate is provided with a power supply interface, which supplies power to the first transceiver chip and the memory chip module through conductive vias in the first photonic integrated circuit chip.

3. The memory chip packaging structure according to claim 1, wherein... The memory chip module and the first transceiver chip are flip-chip mounted on the surface of the first photonic integrated circuit chip that is away from the packaging substrate. The first electrical interconnect interface and the second electrical interconnect interface are electrically connected to the conductive channels in the first photonic integrated circuit chip through bumps.

4. The memory chip packaging structure according to claim 1, wherein... The first transceiver chip also includes a switching unit. The memory chip module includes a first memory chip assembly and a second memory chip assembly, and The switching unit is used to switchably connect the first memory chip component and the second memory chip component to the electrical signal conversion unit.

5. The memory chip packaging structure according to claim 1, wherein... The photoelectric signal conversion module also includes a light source input port and a light modulator. The light source input port is used to receive optical carrier waves, and The optical modulator is used to modulate the optical carrier into the first optical signal according to the second electrical signal.

6. The memory chip packaging structure according to claim 1, wherein... The photoelectric signal conversion module further includes a photodetector for converting the second optical signal into the third electrical signal.

7. The memory chip packaging structure according to claim 1, wherein... The memory chip module includes at least one memory chip component, and each memory chip component includes a memory logic chip and one or more memory chips stacked on the memory logic chip.

8. The memory chip packaging structure according to claim 7, wherein... The one or more memory chips are high-bandwidth memory chips.

9. A memory device, comprising: Printed circuit boards; as well as The memory chip packaging structure according to any one of claims 1-8 is mounted on the printed circuit board.

10. The memory device of claim 9, further comprising an additional memory chip assembly mounted on the printed circuit board, wherein... The first transceiver chip also includes a third electrical interconnect interface for electrical connection with the additional memory chip assembly.

11. A computing chip package structure, comprising: Packaging substrate; A computing chip is disposed on the packaging substrate and includes a first chip interconnect interface; as well as An optical interconnect module, disposed on the packaging substrate, includes a second chip interconnect interface, an optical signal input port, and an optical signal output port, wherein... The first and second chip interconnect interfaces are electrically connected to each other through conductive channels in the packaging substrate, and The optical interconnect module converts a first optical signal received from the optical signal input port into a first electrical signal output to the computing chip, and converts a second electrical signal received from the computing chip into a second optical signal output from the optical signal output port.

12. The computing chip packaging structure according to claim 11, wherein... The optical interconnect module includes a second photonic integrated circuit chip and a second transceiver chip stacked on the second photonic integrated circuit chip. The second transceiver chip is used to convert the third electrical signal from the second photonic integrated circuit chip into the first electrical signal, and to convert the second electrical signal into a fourth electrical signal that is sent to the second photonic integrated circuit chip. The second photonic integrated circuit chip includes the optical signal input port and the optical signal output port, and is used to convert the fourth electrical signal into the second optical signal and the first optical signal into the third electrical signal. The second transceiver chip includes a second chip interconnect interface, which is electrically connected to a conductive channel in the packaging substrate through a conductive via in the second photonic integrated circuit chip.

13. The computing chip packaging structure according to claim 12, wherein... The second photonic integrated circuit chip also includes a light source input port and a light modulator. The light source input port is used to receive optical carrier waves, and The optical modulator is used to modulate the optical carrier into the second optical signal according to the fourth electrical signal.

14. The computing chip packaging structure according to claim 12, wherein... The second photonic integrated circuit chip also includes a photodetector for converting the first optical signal into the third electrical signal.

15. The computing chip packaging structure according to claim 11, wherein... The first and second chip interconnect interfaces are UCIe interfaces.

16. A computing device, comprising: Printed circuit boards; as well as The computing chip package structure according to any one of claims 11-15 is mounted on the printed circuit board.

17. A resource pooling system, comprising: A memory resource pool, comprising a plurality of memory devices according to any one of claims 9 and 10; A computing resource pool, comprising a plurality of computing devices as described in claim 16; as well as An optical switch is optically connected to each memory device in the memory resource pool and each computing device in the computing resource pool, wherein... The optical switch is configured to select one or more computing devices from the computing resource pool and one or more memory devices from the memory resource pool for link connection via a reconstructable optical path, thereby forming a configurable computing system.

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