Method and device for predicting errors associated with a package having a plurality of semiconductor components

Abstract

The invention relates to a method for predicting errors associated with a package having a plurality of semiconductor components, comprising: providing (100) a machine learning model which is configured, for example is trainable and / or is trained, to determine one or more errors associated with the package on the basis of individual error probabilities associated with the plurality of semiconductor components; optionally training (102) the model; using the model (104) for example for predicting at least one error associated with the package.

Description

[0001] R.411743

[0002] - 1 -

[0003] Description

[0004] title

[0005] Method and apparatus for predicting faults associated with a package comprising multiple semiconductor components

[0006] State of the art

[0007] The disclosure relates to a method for predicting faults associated with a package comprising several semiconductor components.

[0008] The disclosure further relates to a device for predicting faults associated with a package comprising several semiconductor components.

[0009] Disclosure of the invention

[0010] Some examples refer to a method, such as a computer-implemented method, for predicting errors associated with a package containing multiple semiconductor components, such as chips. This involves providing a machine learning model that is trained (e.g., trainable and / or already trained) to identify one or more errors associated with the package based on the individual error probabilities associated with the multiple semiconductor components. Optionally, the model is trained, and the model is used, for example, to predict at least one error associated with the package, such as an error during a final test. In some examples, this allows for the early detection of potential errors, such as during the final test of the package.

[0011] In some examples, this involves predicting: feeding input data to the model, processing input data using the model, R.411743

[0012] - 2 - where output data is obtained that characterizes whether at least one error associated with the packet is present and / or expected

[0013] For example, the input data contains test information associated with at least one of the several semiconductor components. For example, the test information could be test data from tests of the semiconductor components, e.g., performed at the wafer level, e.g., wafer-level test information.

[0014] In some examples, the method includes: providing test information associated with at least one of the multiple semiconductor components, wherein, for example, providing the test information includes at least one of the following elements: a) receiving the test information, for example from another device, for example a device for performing tests with respect to the multiple semiconductor components at the wafer level, or b) determining the test information, for example locally determining the test information by a device configured to perform at least some aspects according to claim 1, and optionally using the test information, for example using the test information for training the model, and / or, for example, using the test information as input data for the model for predicting at least one defect associated with the package.

[0015] In some examples, the method includes at least one of the following elements: a) modeling, for example, explicit modeling, of a packet failure probability during a final test, for example, of the packet, based on the individual failure probabilities associated with the multiple semiconductor components, or b) providing the model as a multi-component neural network, for example, a multi-component neural network.

[0016] In some examples, the method includes at least one of the following elements: training the multi-component mesh based on a loss term associated with test information of the multiple semiconductor components, or using the multi-component mesh to determine the R.411743

[0017] - 3 -

[0018] Probability of packet failure during a final test, for example, final test, of the packet.

[0019] In some examples, the multi-component network has several subnetworks, where at least one of the several subnetworks is designed, for example trained and / or trainable, to determine an individual fault probability associated with a specific semiconductor component of the several semiconductor components based on test information associated with the specific semiconductor component.

[0020] In some examples, at least one of the several subnetworks is designed as a multilayer perceptron, MLP.

[0021] In some examples, at least one of the multiple subnetworks has an output layer designed to output the individual error probability associated with a specific semiconductor component among the multiple semiconductor components.

[0022] In some examples, the multi-component network is designed, for example trained and / or trainable, to combine the individual error probabilities of the multiple semiconductor components, for example according to and / or in accordance with the following term:

[0023] M

[0024] J“ 1 , where fj is an individual

[0025] The probability of failure of a j-th semiconductor component is characterized, where WLTj characterizes test information associated with the j-th semiconductor component, for example at the wafer level, such as WLT data.

[0026] In some examples, the training points out: using a loss function, for example, according to R.411743

[0027] - 4 - where

[0028] M characterizes a number of subnetworks, where N characterizes the number of tested packages, for example at wafer level, where WLTj.i characterizes the test information of the i-th package associated with the j-th semiconductor component.

[0029] Some examples refer to a device for carrying out the process according to the disclosure.

[0030] Some examples refer to a computer-readable storage medium comprising instructions which, when executed by a computer, cause it to perform the procedure according to the disclosure.

[0031] Some examples relate to a computer program, comprising instructions that, when the program is executed by a computer, cause it to carry out the procedure according to the disclosure.

[0032] Some examples refer to a data carrier signal that transmits and / or characterizes the computer program according to the disclosure.

[0033] Some examples relate to a use of the method according to the disclosure and / or the device according to the disclosure and / or the computer-readable storage medium according to the disclosure and / or the computer program according to the disclosure and / or the data carrier signal according to the disclosure for at least one of the following elements: a) detecting, for example, comparatively early detection, errors relating to the packet, or b) explicitly modeling a or the probability of failure of the packet in a final test, for example, final test, of the packet, or c) enabling a prediction of errors relating to the packet that can be explained in terms of a cause, such as a component responsible for a failure.

[0034] Further features, applications, and advantages will become apparent from the following description of examples illustrated in the figures of the drawing. All described or illustrated features apply to R.411743.

[0035] - 5 - itself or in any combination the subject matter of the disclosure, irrespective of its aggregation in the claims or their cross-reference and irrespective of its formulation or representation in the description or in the drawing.

[0036] The drawing shows:

[0037] Fig. 1 schematically shows a simplified flowchart,

[0038] Fig. 2 schematically shows a simplified block diagram,

[0039] Fig. 3 schematically shows a simplified block diagram,

[0040] Fig. 4 schematically shows a simplified flowchart,

[0041] Fig. 5 schematically shows a simplified flowchart,

[0042] Fig. 6 schematically shows a simplified block diagram,

[0043] Fig. 7 schematically shows a simplified block diagram,

[0044] Fig. 8 schematically shows aspects of uses.

[0045] Some examples, e.g., Fig. 1, 2, refer to a method, for example, a computer-implemented method, for predicting errors 10-F associated with a package, for example, chip package, 10, comprising several semiconductor components, for example, chips, 12a, 12b, ...: providing 100 (Fig. 1) a machine learning model MLM, which is trained, for example, trainable and / or trained, to determine one or more errors 10-F associated with the package 10 based on individual error probabilities associated with the several semiconductor components 12a, 12b, ... optionally training 102 the model MLM, using 104 the model MLM, for example, for predicting 104a at least one error 10-F associated with the package 10, for example, an error in a final test, for example, final test (e.g., "FT"), of the package 10. This enables, in some cases, R.411743

[0046] - 6 -

[0047] Examples include the early detection of potential errors, for instance, during the final testing of the package.

[0048] In some examples, Fig. 1, 3, the prediction 104a involves: feeding 104a1 input data ED to the model MLM, processing 104a2 the input data ED using the model MLM, obtaining output data AD that characterizes whether at least one error 10-F associated with the packet 10 is present and / or expected.

[0049] For example, in Fig. 2, the input data ED includes test information 12a-TD, 12b-TD, ... associated with at least one of the several semiconductor components 12a, 12b, ... . For example, the test information 12a-TD, 12b-TD, ... can be test data from tests of the semiconductor components 12a, 12b, ..., e.g., performed at the wafer level, e.g., wafer level test ("WLT") information.

[0050] In some examples, Fig. 4, the method comprises: providing 110 test information 12a-TD, 12b-TD, ... associated with at least one of the multiple semiconductor components 12a, 21b, ..., wherein, for example, providing 110 the test information 12a-TD, 12b-TD, ... comprises at least one of the following elements: a) receiving 110a the test information, for example from another device 20 (Fig. 2), for example a device 20 for performing tests on the multiple semiconductor components 12a, 12b, ... at the wafer level, or b) determining 110b the test information 12a-TD, 12b-TD, ..., for example local determination of the test information by a device 200 (Fig. 7) configured to perform at least some aspects according to the disclosure, and optionally using 112 (Fig. 4) the test information, for example using 112a the test information for one or the training 102 (Fig.1) of the MLM model, and / or for example using 112b (Fig. 4) of the test information as input data ED for the MLM model for predicting at least one error associated with the package 10-F.

[0051] In some examples, Fig. 5, the method includes at least one of the following elements: a) Modeling 120, for example explicit modeling 120a, of a failure probability 10-PF of package 10 during a final test, for example final test, of package 10, based on R.411743

[0052] - 7 - on the individual error probabilities associated with the multiple semiconductor components, or b) provide 122 the MLM model as a multi-component neural network NN-MC, for example multi-component neural network NN-MC (see also Fig. 6).

[0053] In some examples, Fig. 5, the method includes at least one of the following elements: Training 124 of the multi-component network NN-MC based on a loss term LT (Fig. 2) associated with test information 12a-TD, 12b-TD, ... of the multiple semiconductor components 12a, 12b, ..., or using 126 the multi-component network NN-MC to determine the packet failure probability during a final test, for example, final test, FT, of the packet 10.

[0054] In some examples, Fig. 6, the multi-component network NN-MC has several (e.g., M many) subnetworks TN-1, TN-2, ..., TN-M, wherein at least one of the several subnetworks is configured, for example trained and / or trainable, to determine an individual fault probability associated with a specific semiconductor component 12a, 12b, ... (Fig. 2) of the several semiconductor components, based on test information 12a-TD, 12b-TD, ... associated with the specific semiconductor component. In some examples, the test information can be supplied to the subnetworks TN-1, TN-2, ..., TN-M, for example, as respective input data ED-1, ED-2, ..., ED-M.

[0055] In some examples, at least one of the several subnetworks TN-1 TN-2, ..., TN-M is designed as a multi-layer perceptron, MLP.

[0056] In some examples, at least one of the several subnetworks TN-1 TN-2, ..., TN-M has an output layer OL1 which is configured to output the individual error probability associated with a specific semiconductor component of the several semiconductor components 12a, 12b, ...

[0057] In some examples, Fig. 6, the multi-component network NN-MC is designed, for example trained and / or trainable, to determine the individual error probabilities of the several semiconductor components 12a, 12b, ... to R.411743

[0058] - 8 - combine, for example according to and / or in accordance with the following term: where fj characterizes an individual failure probability of a j-th semiconductor component, and where WLTj characterizes test information associated with the j-th semiconductor component, for example at wafer level, for example WLT data.

[0059] In some examples, Fig. 5, training 124 shows: Using 124a a loss function, for example loss function, according to (also the loss term LT according to Fig. 2), where M characterizes a number of subnetworks, where N characterizes a number of tested packages, for example, wafer-level tests, and where WLTj.i characterizes the test information associated with the j-th semiconductor component of the i-th package. For example, the MLM model can be trained on the basis of this loss function, for example, using a backpropagation method.

[0060] Some examples, Fig. 7, refer to a device 200 for carrying out the method according to the disclosure.

[0061] In further examples, Fig. 7, the device 200 is provided to have: a computing unit ("computer") 202 having at least one computing core 202a, a storage unit 204 associated with the computing unit 202 for at least temporary storage of at least one of the following elements: a) data DAT (e.g., data associated with the model MLM or the information 12a-TD, 12b-TD, ...), b) computer program PRG, for example, for carrying out the method according to the embodiments. R.411743

[0062] - 9 -

[0063] In other examples, the memory device 204 includes volatile memory (e.g., main memory (RAM)) 204a, and / or non-volatile (NVM) memory (e.g., flash EEPROM) 204b, or a combination thereof or with other memory types not explicitly mentioned.

[0064] Further examples relate to a computer-readable storage medium SM, comprising instructions PRG which, when executed by a computer 202, cause it to execute the method according to the embodiments.

[0065] Further examples relate to a computer program PRG, comprising instructions which, when the program PRG is executed by a computer 202, cause it to execute the method according to the embodiments.

[0066] Further examples relate to a data carrier signal DCS, which characterizes and / or transmits the computer program PRG according to the embodiments. The data carrier signal DCS is, for example, interchangeable via an optional data interface 206 of the device 200.

[0067] In some examples, the functionality of device 200 can also be realized by means of, for example, a purely hardware circuit.

[0068] Further examples and aspects are described below, which in some cases can be combined individually or in combination with at least one of the aspects described above as examples.

[0069] The principle according to the disclosure enables continuous training of a machine learning model MLM (for example, trained as a neural network) that predicts, for example, failures or errors of packages, e.g., multi-chip packages, for example, during a final test (FT), e.g., by explicitly modeling the failure probabilities of the individual components (e.g., chips) 12a, 12b, ... of which the package 10 consists or which the package 10 has.

[0070] Some aspects according to the revelation are based on a probabilistic description of how FT failures arise from the failure of individual components (e.g., chips), and can therefore, for example, represent physical limitations of an R.411743

[0071] - 10 -

[0072] Consider the test setup (e.g., that FT failures are due to failures of individual components). In this way, a prediction can be made in some examples that has a simple explanation regarding the components responsible for a failure.

[0073] Some aspects according to the disclosure can provide component-level contributions to an FT failure, for example for all components 12a, 12b, ... involved in the FT failure, which in some examples can be used to optimize a packaging, for example by selecting which chips 12a, 12b, ... are combined into a package 10, for example to minimize FT failures.

[0074] In some examples, the principle, as disclosed, can be used in semiconductor manufacturing to predict package defects, e.g., due to a faulty component, for example during a final inspection (FT), based on wafer-level tests (WLT) of chips 12a, 12b, ..., which are installed in package 10. For example, the WLT can provide the aforementioned test information.

[0075] In some examples, the test information includes several values, for example dozens to hundreds, such as measured values, for example per chip.

[0076] In some semiconductor manufacturing processes, for example, wafer-level tests (WLT) are performed after wafer production. During this procedure, each chip on the wafer is subjected to one or more tests that provide information about the chip's final performance, such as the electrical properties of a MOSFET chip. If the measured WLT values ​​of a chip fall outside predefined limits, the chip is marked as "failed" in some cases and is considered defective.

[0077] In some examples, after the WLT (Wavelength Testing), the wafer is cut into individual chips (so-called "dies"), for example by cutting or sawing ("single-chip processing"). For example, the separated chips that have passed the WLT are packaged, for example together with one or more other chips. R.411743

[0078] - 11 - of the same or a different type, resulting in a package, e.g., package. In some examples, the package is then tested for functionality in a final test (FT), and packages that fail the final test are discarded.

[0079] In some examples, the cost of rejecting chips in later process stages is higher than in earlier stages (e.g., if a package 10 consists of several chips 12a, 12b, ... and one chip 12a is defective, the package 10 fails the final test (FT), and the entire package 10, with a large proportion of potentially good chips 12b, ..., is discarded). Therefore, in some examples, it is important to utilize existing WLT data as much as possible, e.g., to predict FT failures based on the principle as disclosed.

[0080] While there are some processes (e.g., dicing and packaging processes) that can lead to FT failures which, in some examples, cannot be predicted using WLT data, other FT failure types can be predicted using the principle according to the disclosure, e.g., using WLT data.

[0081] In some examples, a set of WLT data, e.g., WLT measurements, for a component (e.g., a chip) "j" can be denoted by WLTj, and it is assumed, for example, that there are M components in package 10 (Fig. 2). Furthermore, "f" denotes a machine learning-based classifier, which in some examples is trained to map the WLT measurements to an identifier, e.g., a label, "y," that characterizes whether an FT passes (e.g., "no fail") or fails (e.g., "fail").

[0082] In some examples, it is suggested to explicitly model the failure probability of an FT using the failure probabilities of the individual components, for example based on R.411743.

[0083] - 12 - , where this term gives a probability that at least one of a total of M components fails, where Xj = 1 if the j-th component fails in the FT, and Xj = 0 otherwise.

[0084] In some examples, the probability of a package failure can be determined using a component-based machine learning model (MLM). (also Fig. 3, 6) can be estimated using the above classifier f, where the probability that at least one of a total of M components fails is, for example, as follows:

[0085] In some examples, a neural network, e.g., element NN-MC according to Fig. 6, is trained, e.g., to optimize the above expression, e.g., by inserting the above failure probability into a conventional binary cross-entropy loss for classification, which yields the following loss term for N many FT packet measurements:

[0086] <V / M M

[0087] — 22 log[l - U(1 - 'CWLT^))] + (1 - y<) 22 1 - fj (WLTj.,)] i=l \ j = lj=l

[0088] In some examples, the multi-component network NN-MC (Fig. 6) is trained continuously on this basis, for example, by applying the individual models or subnetworks TN-1, TN-2, ... to the respective WLT input data ED-1, ED-2, ... and by determining the combined FT error probability from the output data of the subnetworks (see the first output layer OL1), for example, by calculating it, see the arrow COMB in Fig. 6. In some examples, the loss term above can be used to train the individual models or subnetworks TN-1, TN-2, ... using, for example, a single label. R.411743

[0089] - 13 -

[0090] As mentioned above, a multi-component model is a network consisting of independent binary classification blocks (subnetworks TN-1, TN-2, ...) that make "error" or "non-error" predictions for each WLTj input (input data ED-1, ED-2, ...) (see first output layer OL1), and whose predictions are then combined according to Term 1 above, e.g., also Fig. 6. In some examples, end-to-end training using backpropagation is used to train the multi-component network NN-MC.

[0091] Some examples, Fig. 8, relate to a use 300 of the method according to the disclosure and / or the device 200 according to the disclosure and / or the computer-readable storage medium SM according to the disclosure and / or the computer program PRG according to the disclosure and / or the data carrier signal DCS according to the disclosure for at least one of the following elements: a) detecting 301, for example, comparatively early detection, of errors relating to the packet 10, or b) explicitly modeling 302 of a or the probability of failure of the packet 10 during a final test, for example, final test, of the packet, or c) enabling 303 a prediction of errors relating to the packet 10 that can be explained in terms of a cause, such as a component responsible for a failure.

Claims

R.411743 - 14 - Claims 1. Method, for example, a computer-implemented method, for predicting defects associated with a package (10), for example, a chip package, comprising several semiconductor components (12a, 12b, ...), for example, chips, comprising: providing (100) a machine learning model (MLM) that is trained, for example, trainable and / or trained, to identify one or more defects associated with the package (10) based on individual defect probabilities associated with the several semiconductor components (12a, 12b, ...), optionally training (102) the model (MLM), using (104) the model (MLM), for example, for predicting (104a) at least one defect (10-F) associated with the package (10), for example, a defect in a final test, for example, of the package (10).

2. Method according to claim 1, wherein the prediction (104a) comprises: feeding (104a1) input data (ED) to the model (MLM), processing (104a2) the input data (ED) by means of the model (MLM), whereby output data (AD) are obtained that characterize whether at least one error (10-F) associated with the packet (10) is present and / or is to be expected.

3. Method according to claim 2, wherein the input data (ED) includes test information (12a-TD, 12b-TD, ...) associated with at least one of the several semiconductor components (12a, 12b, ...).

4. A method according to at least one of the preceding claims, comprising: providing (110) test information (12a-TD, 12b-TD, ...) associated with at least one of the several semiconductor components (12a, 12b, ...), wherein, for example, the provision (110) of the test information (12a-TD, 12b-TD, ...) comprises at least one of the following elements: a) receiving (110a) the test information (12a-TD, R.411743 - 15 - 12b-TD, ...), for example by another device (20), for example a device (20) for performing tests with respect to the multiple semiconductor components (12a, 12b, ...) at the wafer level, or b) determining (110b) the test information (12a-TD, 12b-TD, ...), for example local determination of the test information (12a-TD, 12b-TD, ...) by a device (200) configured to perform at least some aspects (100, 102, 104) according to claim 1, and optionally using (112) the test information (12a-TD, 12b-TD, ...), for example using (112a) the test information (12a-TD, 12b-TD, ...) for training (102) the model (MLM), and / or for example using (112b) the test information (12a-TD, 12b-TD, ...) as input data (ED) for the model (MLM) for predicting (104a) at least one error (10-F) associated with the package (10).

5. Method according to at least one of the preceding claims, comprising at least one of the following elements: a) modeling (120), for example explicit modeling (120a), a failure probability (10-PF) of the package (10) during a final test, for example final test, of the package (10), based on the individual failure probabilities associated with the multiple semiconductor components (12a, 12b, ...), or b) providing (122) the model (MLM) as a multi-component neural network (NN-MC), for example multi-component network.

6. Method according to claim 5, comprising at least one of the following elements: training (124) the multi-component network (NN-MC) based on a loss term (LT) associated with test information (12a-TD, 12b-TD, ...) of the multiple semiconductor components (12a, 12b, ...), or using (126) the multi-component network (NN-MC) to determine the failure probability (10-PF) of the packet (10) during a final test, for example, final test, of the packet (10).

7. Method according to claim 5 or 6, wherein the multi-component network (NN-MC) comprises several subnetworks (TN-1, TN-2, ..., TN-M), wherein at least one of the several subnetworks (TN-1, TN-2, ..., TN-M) is configured, for example trained and / or trainable, to transmit a signal from a specific semiconductor component (12a, 12b, ...) of the several semiconductor components. R.411743 - 16 - (12a, 12b, ...) to determine the individual probability of failure associated with the specific semiconductor component (126a) based on test information (12a-TD, 12b-TD, ...) associated with the specific semiconductor component (12a, 12b, ...).

8. The method of claim 7, wherein the multi-component network (NN-MC) is configured, for example trained and / or trainable, to combine the individual fault probabilities of the multiple semiconductor components (12a, 12b, ...) (126b; COMB), for example according to and / or in accordance with the following term: M 1 II JL J ( ¥ JL JL JJ J=1 , where fj is an individual The probability of failure of a j-th semiconductor component is characterized, where WLTj characterizes test information associated with the j-th semiconductor component, for example at the wafer level.

9. Method according to claim 7 or 8, wherein the training (124) comprises: using (124a) a loss function, for example loss function, according to where M characterizes a number of subnetworks (TN-1 , TN-2, ..., TN-M), where N characterizes a number of tested packets, for example at wafer level, where WLTj, i characterizes the test information of the i-th packet associated with the j-th semiconductor component.

10. Device (200) for carrying out the method according to at least one of the preceding claims.

11. Computer-readable storage medium (SM) comprising instructions (PRG) which, when executed by a computer (202), cause it to execute the method according to at least one of claims 1 to 9. R.411743 - 17 - 12. Computer program (PRG) comprising instructions which, when the program (PRG) is executed by a computer (202), cause it to execute the method according to at least one of claims 1 to 9.

13. Data carrier signal (DCS) that transmits and / or characterizes the computer program (PRG) according to claim 12.

14. Use of the method according to at least one of claims 1 to 9 and / or the device (200) according to claim 10 and / or the computer-readable storage medium (SM) according to claim 11 and / or the computer program (PRG) according to claim 12 and / or the data carrier signal (DCS) according to claim 13 for at least one of the following elements: a) detecting (301), for example, comparatively early detection, of errors relating to the packet (10), or b) explicitly modeling (302) a or the failure probability (10-PF) of the packet (10) during a final test, for example, final test, of the packet (10), or c) enabling (303) a prediction of errors relating to the packet (10) that can be explained with respect to a cause such as a component responsible for an error.

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