Storage device

Abstract

Provided is a storage device that has a new configuration. The storage device that has a memory cell array and a switch circuit is described. The memory cell array has a first memory cell and a second memory cell, and each of the memory cells is provided with a terminal. The switch circuit has a plurality of terminals and has a function of bringing the terminals into a conductive state or a non-conductive state. The storage device has a first state and a second state and achieves different operation modes in the respective states. In the first state, the first memory cell and the second memory cell operate independently by the switch circuit. Meanwhile, in the second state, the terminals of the memory cell array are connected by the switch circuit, and the first memory cell and the second memory cell operate as one memory cell.

Description

storage device

[0001] This specification describes storage devices and the like.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include a semiconductor device, an imaging device, a display device, a light-emitting device, a power storage device, a memory device, a display system, an electronic device, a lighting device, an input device, an input / output device, a driving method thereof, or a manufacturing method thereof.

[0003] In this specification and the like, a semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, as well as semiconductor circuits, arithmetic devices, and memory devices are all embodiments of semiconductor devices. Display devices (such as liquid crystal display devices and light-emitting display devices), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, and the like may be considered to include semiconductor devices.

[0004] A dynamic random access memory (DRAM) having a three-transistor (3Tr) type gain cell is known (see, for example, Patent Document 1). A DRAM having a 3Tr type gain cell has an advantage of being able to achieve a higher memory density than a static random access memory (SRAM) type memory cell. In addition, an SRAM (static random access memory) type memory cell has advantages such as superior operating speed and no need for refresh processing.

[0005] In order for a central processing unit (CPU) or other arithmetic processing device to efficiently access data stored in a storage device, a hierarchical structure of storage devices is common. A hierarchical configuration of storage devices, i.e., a configuration in which, in descending order of proximity to the CPU, a cache memory configured with SRAM or the like, a main memory configured with DRAM or the like, a flash memory, and auxiliary storage devices such as a hard disk are arranged. Transistor-based memory cells, such as 3Tr gain cells and SRAM memory cells, can be implemented using technology that combines CMOS logic and storage devices on the same silicon die. Note that storage devices integrated into processing devices such as CPUs often have limited capacity for data storage.

[0006] U.S. Patent No. 9,922,696

[0007] Takashi Koida, "High Mobility Transparent Conductive Film," National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Report 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0008] Depending on the required specifications of a circuit, it may be desirable to achieve high-speed access while still requiring a small memory capacity, as in the case of using SRAM. Alternatively, it may be desirable to increase the memory capacity, as in the case of using DRAM with gain cells. When SRAM and DRAM memory cells are integrated according to the required specifications of the circuit, the area of ​​the silicon die increases. Therefore, a circuit configuration that can switch between memory cells with two different characteristics without increasing the area of ​​the silicon die is desirable. Once a memory cell is manufactured using one of the circuit configurations, it is difficult to switch to the other circuit configuration and operate the memory cell. Therefore, it is difficult to integrate memory cells with different characteristics without increasing the area of ​​the silicon die.

[0009] An object of one embodiment of the present invention is to provide a memory device in which the circuit configuration of a memory cell can be switched after manufacturing.Another object of one embodiment of the present invention is to provide a memory device including a memory cell that is less susceptible to variations in electrical characteristics of a transistor.Another object of one embodiment of the present invention is to provide a memory device that has excellent read and write speeds for memory cells.Another object of one embodiment of the present invention is to provide a memory device that is excellent in low power consumption.Another object is to provide a memory device with a novel structure.

[0010] Note that one embodiment of the present invention does not necessarily have to solve all of the above problems, but it is sufficient that it can solve at least one of the problems. Furthermore, the description of the above problems does not preclude the existence of other problems. Problems other than these will become apparent from the description in the specification, claims, drawings, etc., and other problems can be extracted from the description in the specification, claims, drawings, etc.

[0011] (1) One aspect of the present invention is a memory device including a first memory cell, a second memory cell, and a switch circuit. The switch circuit is electrically connected to the first memory cell and the second memory cell. The switch circuit has a function of switching a connection state between the first memory cell and the second memory cell between a first state and a second state. In the first state, the first memory cell and the second memory cell operate as a DRAM consisting of three different transistors. In the second state, the first memory cell and the second memory cell operate as an SRAM consisting of a total of six transistors.

[0012] (2) One embodiment of the present invention is a memory device including a memory cell array and a switch circuit. The memory cell array includes a first memory cell and a second memory cell. The switch circuit includes a first terminal, a second terminal, a third terminal, a fourth terminal, a fifth terminal, a sixth terminal, a seventh terminal, an eighth terminal, a ninth terminal, and a tenth terminal. The first terminal, the third terminal, and the fifth terminal are electrically connected to the first memory cell. The second terminal, the fourth terminal, and the seventh terminal are electrically connected to the second memory cell. The sixth terminal and the ninth terminal are electrically connected to each other. The eighth terminal and the tenth terminal are electrically connected to each other. The switch circuit has a function of establishing a conductive state or a non-conductive state between the first terminal and the second terminal. The switch circuit has a function of establishing a conductive state or a non-conductive state between the third terminal and the fourth terminal. The switch circuit has a function of establishing a conductive state or a non-conductive state between the fifth terminal and the sixth terminal. The switch circuit has a function of establishing a conductive state or a non-conductive state between the seventh terminal and the eighth terminal. The switch circuit has a function of establishing a conductive state or a non-conductive state between the ninth terminal and the tenth terminal. In a first state, the first and second terminals, the third and fourth terminals, the fifth and sixth terminals, and the seventh and eighth terminals are each established in a non-conductive state, and the ninth and tenth terminals are established in a conductive state, and in the first state, the first memory cell and the second memory cell operate as different memory cells. In the second state, the first terminal and the second terminal, the third terminal and the fourth terminal, the fifth terminal and the sixth terminal, and the seventh terminal and the eighth terminal are each in a conductive state, and the ninth terminal and the tenth terminal are in a non-conductive state, and in the second state, the first memory cell and the second memory cell operate together as one memory cell.

[0013] (3) In addition, in (2), the memory device preferably includes a first transistor in the first memory cell and a second transistor in the second memory cell. The gate of the first transistor is electrically connected to the sixth terminal and the ninth terminal. One of the source or drain of the first transistor is electrically connected to the first terminal. The gate of the second transistor is electrically connected to the eighth terminal and the tenth terminal. One of the source or drain of the second transistor is electrically connected to the fourth terminal. The first transistor and the second transistor are each a p-channel transistor. In a first state, the gate of the first transistor and the gate of the second transistor are in a conductive state via the ninth terminal and the tenth terminal. In a second state, the third terminal and the gate of the first transistor are in a conductive state via the fifth terminal and the sixth terminal, and the second terminal and the gate of the second transistor are in a conductive state via the seventh terminal and the eighth terminal.

[0014] (4) Another embodiment of the present invention is a memory device including a first memory cell, a second memory cell, a switch circuit, and first to fourth wirings. The first memory cell includes a first transistor, a second transistor, and a third transistor. The second memory cell includes a fourth transistor, a fifth transistor, and a sixth transistor. The switch circuit includes a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor. One of a source or a drain of the first transistor is electrically connected to a gate of the second transistor. One of a source or a drain of the second transistor is electrically connected to one of a source or a drain of the third transistor. One of a source or a drain of the fourth transistor is electrically connected to a gate of the fifth transistor. One of a source or a drain of the fifth transistor is electrically connected to one of a source or a drain of the sixth transistor. One of a source or a drain of the seventh transistor is electrically connected to one of a source or a drain of the first transistor and the gate of the second transistor. The other of the source or drain of the seventh transistor is electrically connected to one of the source or drain of the fifth transistor and one of the source or drain of the sixth transistor. One of the source or drain of the eighth transistor is electrically connected to one of the source or drain of the second transistor and one of the source or drain of the third transistor. The other of the source or drain of the eighth transistor is electrically connected to one of the source or drain of the fourth transistor and the gate of the fifth transistor. One of the source or drain of the ninth transistor is electrically connected to one of the source or drain of the tenth transistor, the gate of the third transistor, and the second wiring. The other of the source or drain of the ninth transistor is electrically connected to the third wiring. The other of the source or drain of the tenth transistor is electrically connected to one of the source or drain of the first transistor and the gate of the second transistor.One of the source or drain of the eleventh transistor is electrically connected to one of the source or drain of the twelfth transistor, the gate of the sixth transistor, and the third wiring. The other of the source or drain of the eleventh transistor is electrically connected to the fourth wiring. The other of the source or drain of the twelfth transistor is electrically connected to one of the source or drain of the fourth transistor and the gate of the fifth transistor. The gate of the first transistor and the gate of the fourth transistor are electrically connected to the first wiring.

[0015] (5) In the above (4), it is preferable that the third transistor and the sixth transistor are p-channel transistors.

[0016] (6) In the memory device of (4), it is preferable that the memory device has fifth to eighth wirings. The other of the source and the drain of the first transistor is electrically connected to the fifth wiring. The other of the source and the drain of the third transistor is electrically connected to the sixth wiring. The other of the source and the drain of the fourth transistor is electrically connected to the seventh wiring. The other of the source and the drain of the sixth transistor is electrically connected to the eighth wiring.

[0017] (7) In the memory device of (4), it is preferable that the memory device has a ninth wiring and a tenth wiring. The gates of the seventh transistor, the eighth transistor, the tenth transistor, and the twelfth transistor are electrically connected to the ninth wiring. The gates of the ninth transistor and the eleventh transistor are electrically connected to the tenth wiring.

[0018] (8) In (6), each of the seventh to twelfth transistors preferably includes a semiconductor layer having a channel formation region. The semiconductor layer preferably includes an oxide semiconductor.

[0019] (9) In addition, in (8), it is preferable that the seventh transistor is an n-channel transistor, the high-level potential that turns on the seventh transistor is a potential higher than the sum of the power supply potential and the threshold voltage of the seventh transistor, and the power supply potential is a potential applied to the sixth wiring.

[0020] (10) In addition, in (8), it is preferable that the ninth transistor is an n-channel transistor, the high-level potential that turns on the ninth transistor is a potential higher than the sum of the power supply potential and the threshold voltage of the ninth transistor, and the power supply potential is a potential applied to the sixth wiring.

[0021] (11) In (6), the first memory cell and the second memory cell are preferably memory cells arranged adjacent to each other.

[0022] (12) In the memory device of (6), it is preferable that the memory device further includes a third memory cell, the third memory cell being disposed between the first memory cell and the second memory cell.

[0023] (13) In addition, in (4), the memory device preferably includes a first capacitor in the first memory cell and a second capacitor in the second memory cell. A first electrode of the first capacitor is electrically connected to one of the source or drain of the first transistor, the gate of the second transistor, and one of the source or drain of the seventh transistor. A first electrode of the second capacitor is electrically connected to one of the source or drain of the fourth transistor, the gate of the fifth transistor, and the other of the source or drain of the eighth transistor.

[0024] (14) Another embodiment of the present invention is a memory device including a first memory cell, a second memory cell, a switch circuit, and first to fourth wirings. The first memory cell includes a first transistor, a second transistor, and a third transistor. The second memory cell includes a fourth transistor, a fifth transistor, and a sixth transistor. The switch circuit includes a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor. One of a source or a drain of the first transistor is electrically connected to a gate of the second transistor. One of a source or a drain of the second transistor is electrically connected to one of a source or a drain of the third transistor. One of a source or a drain of the fourth transistor is electrically connected to a gate of the fifth transistor. One of a source or a drain of the fifth transistor is electrically connected to one of a source or a drain of the sixth transistor. One of a source or a drain of the seventh transistor is electrically connected to a gate of the third transistor. The other of the source or drain of the seventh transistor is electrically connected to one of the source or drain of the fifth transistor and one of the source or drain of the sixth transistor. One of the source or drain of the eighth transistor is electrically connected to one of the source or drain of the second transistor and one of the source or drain of the third transistor. The other of the source or drain of the eighth transistor is electrically connected to the gate of the sixth transistor. One of the source or drain of the ninth transistor is electrically connected to one of the source or drain of the tenth transistor, the gate of the third transistor, and the second wiring. The other of the source or drain of the ninth transistor is electrically connected to the third wiring. The other of the source or drain of the tenth transistor is electrically connected to one of the source or drain of the first transistor and the gate of the second transistor. One of the source or drain of the eleventh transistor is electrically connected to one of the source or drain of the twelfth transistor, the gate of the sixth transistor, and the third wiring.The other of the source and the drain of the twelfth transistor is electrically connected to the one of the source and the drain of the fourth transistor and the gate of the fifth transistor. The gate of the first transistor and the gate of the fourth transistor are electrically connected to the first wiring.

[0025] (15) In (14), the third transistor and the sixth transistor are preferably p-channel transistors.

[0026] (16) In the memory device (14), it is preferable that the memory device has fifth to eighth wirings. The other of the source and the drain of the first transistor is electrically connected to the fifth wiring. The other of the source and the drain of the third transistor is electrically connected to the sixth wiring. The other of the source and the drain of the fourth transistor is electrically connected to the seventh wiring. The other of the source and the drain of the sixth transistor is electrically connected to the eighth wiring.

[0027] (17) In the memory device of (14), it is preferable that the memory device has a ninth wiring and a tenth wiring. The gates of the seventh transistor, the eighth transistor, the tenth transistor, and the twelfth transistor are electrically connected to the ninth wiring. The gates of the ninth transistor and the eleventh transistor are electrically connected to the tenth wiring.

[0028] (18) In (16), each of the seventh to twelfth transistors preferably includes a semiconductor layer having a channel formation region, and the semiconductor layer preferably includes an oxide semiconductor.

[0029] (19) In addition, in (18), it is preferable that the seventh transistor is an n-channel transistor, the high-level potential that turns on the seventh transistor is a potential higher than the sum of the power supply potential and the threshold voltage of the seventh transistor, and the power supply potential is a potential applied to the sixth wiring.

[0030] (20) In addition, in (18), it is preferable that the ninth transistor is an n-channel transistor, the high-level potential that turns on the ninth transistor is a potential higher than the sum of the power supply potential and the threshold voltage of the ninth transistor, and the power supply potential is a potential applied to the sixth wiring.

[0031] (21) In (16), the first memory cell and the second memory cell are preferably memory cells arranged adjacent to each other.

[0032] (22) In addition, in (16), it is preferable that a third memory cell is included, and the third memory cell is disposed between the first memory cell and the second memory cell.

[0033] (23) Also, in (14), it is preferable that the first memory cell has a first capacitor, the second memory cell has a second capacitor, a first electrode of the first capacitor is electrically connected to one of the source or drain of the first transistor, the gate of the second transistor, and one of the source or drain of the seventh transistor, and a first electrode of the second capacitor is electrically connected to one of the source or drain of the fourth transistor, the gate of the fifth transistor, and the other of the source or drain of the eighth transistor.

[0034] Note that other aspects of the present invention will be described in the following embodiments and in the drawings.

[0035] One embodiment of the present invention can provide a memory device in which the circuit configuration of a memory cell can be switched after manufacturing. Another embodiment of the present invention can provide a memory device having memory cells that are less susceptible to variations in electrical characteristics of transistors. Another embodiment of the present invention can provide a memory device with excellent read and write speeds for memory cells. Another embodiment of the present invention can provide a memory device with excellent low power consumption.

[0036] The description of multiple effects does not preclude the existence of other effects. Furthermore, one embodiment of the present invention does not necessarily have all of the exemplified effects. Furthermore, problems, effects, and novel features of one embodiment of the present invention other than those described above will become apparent from the description and drawings in this specification.

[0037] FIGS. 1A and 1B are diagrams illustrating an example of the configuration of a memory device. FIGS. 2A and 2B are diagrams illustrating an example of the configuration of a memory device. FIGS. 3A, 3B, 3C, and 3D are diagrams illustrating an example of the configuration of a memory device. FIG. 4 is a diagram illustrating an example of the configuration of a memory device. FIGS. 5A and 5B are diagrams illustrating an example of the configuration of a memory device. FIGS. 6A and 6B are diagrams illustrating an example of the configuration of a memory device. FIGS. 7A and 7B are diagrams illustrating an example of the configuration of a memory device. FIGS. 8A and 8B are diagrams illustrating an example of the configuration of a memory device. FIGS. 9A and 9B are diagrams illustrating an example of the configuration of a memory device. FIGS. 10A, 10B, and 10C are diagrams illustrating an example of the configuration of a memory device. FIGS. 11A, 11B, and 11C are diagrams illustrating an example of the configuration of a memory device. FIGS. 12A, 12B, and 12C are diagrams illustrating an example of the configuration of a memory device. FIGS. 13A and 13B are diagrams illustrating the carrier concentration dependence of Hall mobility. FIG. 13C is a cross-sectional view illustrating an indium oxide film. Fig. 14 is a diagram showing various storage devices by hierarchical level. Figs. 15A and 15B are diagrams showing an example of an electronic component. Figs. 16A and 16B are diagrams showing an example of an electronic device. Figs. 17A, 17B, and 17C are diagrams showing an example of an electronic device. Fig. 18 is a diagram showing an example of a mainframe computer.

[0038] Hereinafter, embodiments of the present invention will be described. However, one aspect of the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, one aspect of the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0039] In this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. For example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0040] In the drawings, the same elements or elements having similar functions, elements made of the same material, or elements formed at the same time may be given the same reference numerals, and repeated description thereof may be omitted.

[0041] In this specification, for example, the power supply potential VDD may be abbreviated as potential VDD, VDD, etc. This also applies to other components (for example, signals, voltages, circuits, elements, electrodes, wiring, etc.).

[0042] Furthermore, in this specification and drawings, when the same reference numeral is used for multiple elements, and particularly when it is necessary to distinguish between them, the reference numeral may be accompanied by an identifying symbol such as "A", "b", "_1", "[n]", or "[m, n]". Furthermore, when explaining matters common to multiple elements accompanied by identifying symbols, or when it is not necessary to distinguish between them, the elements may be described without the identifying symbol.

[0043] Embodiment 1 A structure, operation, and the like of a storage device that is one embodiment of the present invention will be described with reference to the drawings.

[0044] In this embodiment, a memory device including a memory cell array and a switch circuit will be described. The memory cell array includes first and second memory cells, each of which has a terminal. The switch circuit includes a plurality of terminals and has a function of establishing a conductive state or a non-conductive state between the terminals. The memory device according to one embodiment of the present invention has a first state and a second state, each of which realizes a different operation mode. In the first state, the first memory cell and the second memory cell operate independently of each other through the switch circuit. In the first state, the first memory cell and the second memory cell can be independently used as a 3Tr gain cell. On the other hand, in the second state, the terminals of the memory cell array are connected by the switch circuit, and the first memory cell and the second memory cell operate as a single memory cell. In the second state, the first memory cell and the second memory cell can be used as a 6Tr SRAM together with two 3Tr gain cells.

[0045] 1A and 1B show a configuration example of a memory device 100. The memory device 100 includes an element layer 10 and an element layer 30 provided over the element layer 10. Note that the element layer is a layer in which a semiconductor element such as a transistor or a capacitor is provided.

[0046] FIG. 1A is a circuit diagram illustrating a memory cell CEL (typically, a memory cell CEL_11 and a memory cell CEL_12), a switch circuit SEL (typically, a switch circuit SEL_1), and a switch circuit 16 (typically, a switch circuit 16_1 and a switch circuit 16_2) according to one embodiment of the present invention. FIG. 1B is a perspective view illustrating a wiring relationship between two (a pair or a set) memory cells CEL (the memory cell CEL_11 and the memory cell CEL_12 shown in FIG. 1A) included in the element layer 10 and a switch circuit SEL (the switch circuit SEL_1 shown in FIG. 1A) included in the element layer 30. Note that in this specification, the memory cell CEL_11, the memory cell CEL_12, the memory cell CEL_21 (shown in FIG. 4 to be described later), and the memory cell CEL_22 (shown in FIG. 4 to be described later) may be collectively referred to as memory cells CEL. Furthermore, the switch circuit SEL_1 and the switch circuit SEL_2 (shown in FIG. 4 to be described later) may be collectively referred to as switch circuits SEL. The switch circuits 16_1 and 16_2 may be collectively referred to as the switch circuits 16.

[0047] As will be described later, the configuration of the memory device 100 shown in FIGS. 3A to 3C can be referred to for the element layer 10, the element layer 30 on the element layer 10, and the switch circuit 16.

[0048] Note that in the following description, the transistor included in the switch circuit SEL is an n-channel transistor, for example. The memory device 100 of one embodiment of the present invention can also use a p-channel transistor. In that case, the potential of a signal applied to the transistor included in the switch circuit SEL can be changed. Note that the n-channel transistor can be in a conductive state (on state) when the gate potential is a high-level potential (H level) and in a non-conductive state (off state) when the gate potential is a low-level potential (L level).

[0049] The following description will be given assuming that the memory cell CEL and the switch circuit 16 have n-channel and p-channel transistors. Note that the p-channel transistor operates in the opposite manner to the n-channel transistor, and can be in a non-conductive state (off state) when the potential of the gate of the p-channel transistor is at a high level potential (H level), and in a conductive state (on state) when the potential is at a low level potential (L level).

[0050] In the memory device 100 of FIG. 1A, memory cells CEL_11 and CEL_12 are shown as examples of memory cells CEL. These memory cells can operate as a single memory cell by being appropriately connected via a switch circuit SEL. Specifically, by combining memory cells CEL_11 and CEL_12, a circuit configuration shown by memory cells CEL_11 and CEL_12 can be achieved. Also, switch circuit SEL_1 is shown as an example of a switch circuit SEL. Memory cell CEL_11 may be referred to as a first memory cell. Memory cell CEL_12 may be referred to as a second memory cell.

[0051] 1A, a plurality of memory cells CEL are arranged in a matrix. Wiring CLA_1 and wiring CLB_1 are each connected to a plurality of memory cells CEL arranged in the column direction. Wiring RLA_1 and wiring RLB_1 are each connected to a plurality of memory cells CEL arranged in the row direction.

[0052] The memory cell CEL_11 has a transistor M13, a transistor M12, and a transistor M16. The memory cell CEL_11 is connected to wirings CLA_1 and CLB_1 arranged in the column direction and wirings RLA_1 and RLB_1 arranged in the row direction. The transistor M13 may be referred to as a first transistor. The transistor M12 may be referred to as a second transistor. The transistor M16 may be referred to as a third transistor.

[0053] The transistors M13, M12, and M16 are connected to the wirings CLA_1, CLB_1, RLA_1, and RLB_1 as shown in FIG. 1A . Specifically, one of the source and drain of the transistor M13 is connected to the gate of the transistor M12. The other of the source and drain of the transistor M13 is connected to the wiring CLA_1. The gate of the transistor M13 is connected to the wiring RLA_1. The one of the source and drain of the transistor M12 is connected to the one of the source and drain of the transistor M16. The other of the source and drain of the transistor M12 is connected to a constant potential line, for example, a ground line. The other of the source and drain of the transistor M16 is connected to the wiring CLB_1. The gate of the transistor M16 is connected to the wiring RLB_1.

[0054] The memory cell CEL_12 includes a transistor M14, a transistor M11, and a transistor M15. The memory cell CEL_12 is connected to wirings CLA_2 and CLB_2 arranged in the column direction and wirings RLA_1 and RLB_1 arranged in the row direction. The transistor M14 may be referred to as a fourth transistor. The transistor M11 may be referred to as a fifth transistor. The transistor M15 may be referred to as a sixth transistor. Note that in this specification, the wirings CLA_1 and CLA_2 may be collectively referred to as wirings CLA. The wirings CLB_1 and CLB_2 may be collectively referred to as wirings CLB. The wirings RLA_1 and RLA_2 (shown in FIG. 4, which will be described later) may be collectively referred to as wirings RLA. The wirings RLB_1 and RLB_2 (shown in FIG. 4, which will be described later) may be collectively referred to as wirings RLB.

[0055] The transistors M14, M11, and M15 are connected to the wirings CLA_2, CLB_2, RLA_1, and RLB_1 as shown in FIG. 1A . Similar to the connection relationship of the transistors M13, M12, and M16 in the memory cell CEL_11, these transistors are connected as follows: One of the source or drain of the transistor M14 is connected to the gate of the transistor M11. The other of the source or drain of the transistor M14 is connected to the wiring CLA_2. The gate of the transistor M14 is connected to the wiring RLA_1. One of the source or drain of the transistor M11 is connected to one of the source or drain of the transistor M15. The other of the source or drain of the transistor M11 is connected to a constant potential line (e.g., a ground line). The other of the source or drain of the transistor M15 is connected to the wiring CLB_2. The gate of the transistor M15 is connected to the wiring RLB_1.

[0056] The switch circuit SEL_1 switches between two signal paths between the memory cells CEL_11 and CEL_12 using six transistors that function as switches. Specifically, by turning on two transistors (transistors M51 and M61 shown in FIG. 1 ) whose gates are connected to the wiring CSB, the circuit configuration can be switched to that of a 3Tr gain cell DRAM, and by turning on four transistors (transistors M52, M53, M62, and M63 shown in FIG. 1 ) whose gates are connected to the wiring CS, the circuit configuration can be switched to that of a standard 6Tr SRAM.

[0057] In one embodiment of the present invention, the switch circuit SEL_1 includes transistors M51 to M53 and transistors M61 to M63. The switch circuit SEL_1 is connected to memory cells CEL_11 and CEL_12 and a wiring RLB_1 arranged in the element layer 10. The switch circuit SEL_1 is connected to wirings CS and CSB arranged to extend in the element layer 30. The transistor M51 may be referred to as a seventh transistor. The transistor M52 may be referred to as an eighth transistor. The transistor M53 may be referred to as a ninth transistor. The transistor M61 may be referred to as a tenth transistor. The transistor M62 may be referred to as an eleventh transistor. The transistor M63 may be referred to as a twelfth transistor.

[0058] The transistors M53 and M63 are connected to the wiring CS, the memory cell CEL_11, and the memory cell CEL_12 as shown in FIGS. 1A and 1B. Specifically, one of the source or drain of the transistor M53 is connected to one of the source or drain of the transistor M14 and the gate of the transistor M11. The other of the source or drain of the transistor M53 is connected to one of the source or drain of the transistor M12 and one of the source or drain of the transistor M16. The gate of the transistor M53 is connected to the wiring CS. The other of the source or drain of the transistor M63 is connected to one of the source or drain of the transistor M13 and the gate of the transistor M12. The other of the source or drain of the transistor M63 is connected to one of the source or drain of the transistor M11 and one of the source or drain of the transistor M15. The gate of the transistor M63 is connected to the wiring CS.

[0059] The transistors M52 and M62 are connected to the wiring CS and the memory cells CEL_11 and CEL_12 as shown in FIGS. 1A and 1B. Specifically, one of the source or drain of the transistor M52 is connected to the gate of the transistor M16 and the wiring RLB_1. The other of the source or drain of the transistor M52 is connected to one of the source or drain of the transistor M13 and the gate of the transistor M12. The gate of the transistor M52 is connected to the wiring CS. The other of the source or drain of the transistor M62 is connected to the gate of the transistor M15 and the wiring RLB_1. The other of the source or drain of the transistor M62 is connected to one of the source or drain of the transistor M14 and the gate of the transistor M11. The gate of the transistor M62 is connected to the wiring CS.

[0060] The transistors M51 and M61 are connected to the wiring CSB and the memory cells CEL_11 and CEL_12 as shown in FIGS. 1A and 1B. Specifically, the sources and drains of the transistors M51 and M61 are connected in series to the wiring RLB_1, respectively. The gates of the transistors M51 and M61 are connected to the wiring CSB. One of the source or drain of the transistor M51 is connected to the gate of the transistor M16 and the wiring RLB_1. One of the source or drain of the transistor M61 is connected to the gate of the transistor M15 and the wiring RLB_1. The other of the source or drain of the transistor M51 and the other of the source or drain of the transistor M61 are connected to the wiring RLB_1.

[0061] 1A and 1B show an example in which the transistors M12, M13, M16, M11, M14, and M15 are n-channel transistors and the transistors M16 and M15 are p-channel transistors.

[0062] By using p-channel transistors as the transistors M16 and M15, they can be used as switches when configuring the memory cell CEL with 3 transistors (specifically, the memory cells CEL_11 and CEL_12 shown in FIG. 1A), and can be used as p-channel transistors of a CMOS inverter when configuring the memory cell CEL with 6 transistors (specifically, the memory cells CEL_11 and CEL_12 shown in FIG. 1A).

[0063] The wirings RLA_1 and RLB_2 each have a function of applying a signal for switching the transistors between a conductive state and a non-conductive state. Specifically, the wiring RLA_1 controls the transistors M13 and M14, and the wiring RLB_1 controls the transistors M16 and M15.

[0064] Here, as an example, the wiring RLB_1 can be expressed as having multiple parts. Specifically, the wiring RLB_1 shown in FIG. 1A includes a wiring RLB_1AA, a wiring RLB_1AB, and a wiring RLB_1AC. A transistor M51 or a transistor M61 functioning as a switch is provided between the multiple parts of the wiring RLB_1. Thus, by connecting the multiple parts using the switches, the wiring RLB_1 can function as a single wiring.

[0065] By turning on the transistors M51 and M61, multiple portions of the wiring RLB_1 can be connected in series via switches. This allows multiple portions of the wiring RLB_1 to be connected together and function as a single wiring to which the same signal is applied. Specifically, the same signal is applied to the gate of the transistor M16 in the memory cell CEL_11 and the gate of the transistor M15 in the memory cell CEL_12. This allows the memory cells CEL_11 and CEL_12 to be used as 3Tr gain cells.

[0066] On the other hand, when the transistors M51 and M61 are turned off, the multiple portions of the wiring RLB_1 are not connected. It can also be said that the wiring RLB_1 does not function as a wiring to which the same signal is applied to the entire wiring. When the transistors M51 and M61 are turned off, the other transistors in the switch circuit SEL_1 are each set to a desired state (for example, the transistors M52, M53, M62, and M63 are turned on), and the memory cells CEL_11 and CEL_12 can be used as a single 6-transistor memory cell (the memory cell CEL_1112 in FIG. 1A ). Furthermore, as shown in FIG. 1A , by using p-channel transistors as the transistors M16 and M15, the memory cell CEL_1112 has a circuit configuration similar to that of a complementary MOS (CMOS) (6-transistor) SRAM.

[0067] The switch circuit 16_1 includes a switch SW101 and a switch SW102. The switch circuit 16_1 is connected to the wiring DL_1, the wiring PL_1, and the wiring CLB_1. One terminal of the switch SW101 is connected to one terminal of the switch SW102 and the wiring CLB_1. The other terminal of the switch SW101 is connected to the wiring DL_1. The other terminal of the switch SW102 is connected to the wiring PL_1. Note that since the other of the source and the drain of the transistor M16 is connected to the wiring CLB_1, an input signal from the wiring DL_1 can be input to the other of the source and the drain of the transistor M16 by turning on the switch SW101 and turning off the switch SW102. Furthermore, an input signal from the wiring PL_1 can be input to the transistor M16 by turning off the switch SW101 and turning on the switch SW102. In this specification, the wirings DL_1 and DL_2 may be collectively referred to as wirings DL, and the wirings PL_1 and PL_2 may be collectively referred to as wirings PL.

[0068] The switch circuit 16_2 includes a switch SW111 and a switch SW112. The switch circuit 16_2 is connected to the wiring DL_2, the wiring PL_2, and the wiring CLB_2. One terminal of the switch SW111 is connected to one terminal of the switch SW112 and the wiring CLB_2. The other terminal of the switch SW111 is connected to the wiring DL_2. The other terminal of the switch SW112 is connected to the wiring PL_2. Note that the other of the source and the drain of the transistor M15 is connected to the wiring CLB_2. Therefore, by turning on the switch SW111 and turning off the switch SW112, an input signal from the wiring DL_2 can be input to the other of the source and the drain of the transistor M15. Furthermore, by turning off the switch SW111 and turning on the switch SW112, an input signal from the wiring PL_2 can be input to the transistor M15.

[0069] 2A and 2B are diagrams illustrating components related to the wiring RLB_1 remaining in the memory cell CEL according to one embodiment of the present invention illustrated in FIGS. 1A and 1B. 2A and 2B are circuit diagrams and perspective views illustrating the wiring relationships among the transistors M16, M15, M51, M61, and the wiring RLB_1 (shown as wiring RLB_1AA, wiring RLB_1AB, and wiring RLB_1AC).

[0070] Note that a memory cell CEL at the end of the memory cell array (typically, memory cell CEL_11 or memory cell CEL_12) may be used as a dummy cell. By turning off transistor M51 or transistor M61 of the dummy cell, it is possible to cut off the input signal from the word line side driver circuit in the memory cell CEL located inside the end of the memory cell array in the row direction.

[0071] When the two transistors whose gates are connected to the wiring CSB are in an on state, the wiring RLB_1 functions as a read word line for reading data from the 3Tr type gain cell DRAM.

[0072] 3A is a schematic diagram illustrating a memory device 100 according to one embodiment of the present invention, which includes peripheral circuits and the like in addition to the memory cell array 11 and the switch circuit 16 described above. FIG. 3B is a block diagram illustrating an example of a configuration of the element layer 10. FIG. 3C is a circuit diagram illustrating an example of a configuration of the switch circuit 16.

[0073] The memory device 100 includes an element layer 10 and an element layer 30 provided to overlap the element layer 10. In the schematic diagram shown in Figure 3A, the element layer 10 and the element layer 30 provided to overlap the element layer 10 are shown separated from each other in order to make the arrangement of each element constituting the memory device 100 easier to understand.

[0074] The element layer 10 includes, for example, a memory cell array 11 including a plurality of memory cells CEL, a bit line side drive circuit 12, a word line side drive circuit 13, a switching drive circuit 14, a control circuit 15, and a plurality of switch circuits 16. The element layer 30 includes a plurality of switch circuits SEL.

[0075] The memory cell CEL has a function of holding an amount of charge corresponding to a data value. The memory cell CEL is connected to a wiring that functions as a bit line or a word line, and data writing or reading is controlled. The memory cell CEL may also be called a memory circuit, a memory cell, a data holding circuit, etc.

[0076] 3B also illustrates the wiring relationship between the memory cell CEL included in the element layer 10 and the switch circuit 16. Note that in the following description, the transistor included in the switch circuit SEL is an n-channel transistor, for example. The memory device 100 of one embodiment of the present invention can also be a p-channel transistor by changing the potential of a signal applied to the transistor included in the switch circuit SEL.

[0077] 3A, in order to explain the arrangement of each component, the Z direction is defined as a direction perpendicular or approximately perpendicular to the surface of the element layer 10 (for example, a surface on which an interlayer insulating layer is provided). For ease of understanding, the Z direction may be referred to as a direction perpendicular to the surface of the element layer 10 in the specification. Note that "approximately perpendicular" refers to a state in which the elements are arranged at an angle of 85 degrees or more and 95 degrees or less.

[0078] In this specification and drawings, the X direction, Y direction, and Z direction may be defined to explain the arrangement of each element. For example, in the schematic diagram shown in Figure 3A, the X direction, Y direction, and Z direction are defined to explain the arrangement of each element constituting the storage device 100. The X direction, Y direction, and Z direction are perpendicular or approximately perpendicular to each other.

[0079] The switch circuit SEL has the function of switching the signal path between two memory cells CEL, the function of switching the signal path within the memory cell CEL, and the function of controlling the conductive or non-conductive state of switches connected to each portion of the wiring RLA and the wiring RLB. The switch circuit SEL has a transistor that functions as a switch. The switch circuit SEL is connected to wiring that controls the conductive or non-conductive state of the transistor that functions as a switch. The switch circuit SEL may also be called a switching circuit, a path holding circuit, etc.

[0080] The bit line side driver circuit 12 is a circuit that writes and reads data to and from the memory cell CEL via wiring that functions as bit lines (wiring CLA and wiring CLB arranged in the column direction) connected to the memory cell CEL. The bit line side driver circuit 12 also switches signals supplied to the wiring that functions as bit lines under the control of the control circuit 15. This configuration allows data to be written and read in accordance with the switching of the circuit configuration in the memory cell CEL. Note that, as will be described later in the explanations of FIGS. 5A and 5B , when the memory cell CEL is used as a 3Tr-type gain cell DRAM, the wiring CLA can be used as a write bit line WBL and the wiring CLB can be used as a read bit line RBL. Also, as will be described later in FIGS. 6A and 6B , when the memory cell CEL is used as a 6Tr-type SRAM, the wiring CLA can be used as a bit line BL and the wiring CLB can be used as an inverted bit line BLB.

[0081] The word line side driver circuit 13 is a circuit that has a function of supplying a word signal or a constant potential to the memory cell CEL via wirings (wirings RLA and RLB arranged in the row direction) that function as word lines connected to the memory cell CEL. The word line side driver circuit 13 has a function of switching between the word signal and the constant potential under the control of the control circuit 15. With this configuration, it is possible to write and read data in accordance with switching the circuit configuration in the memory cell CEL.

[0082] The switching drive circuit 14 has a function of supplying a signal that controls the conductive state or non-conductive state of the transistor in the switch circuit SEL via wiring (wiring CS and wiring CSB) that extends to the upper element layer 30. The switching drive circuit 14 has a function of switching on or off the switch in the switch circuit SEL in accordance with the control of the control circuit 15. With this configuration, it is possible to switch the circuit configuration in the memory cell CEL.

[0083] Note that the high-level potential of the signal supplied to the wiring CS and the wiring CSB is preferably a potential higher than the sum of the power supply potential and the threshold voltage of the transistors of the switch circuit SEL (for example, one or more selected from the transistors M51, M52, M53, M61, M62, and M63 in FIG. 1A). In particular, when the threshold voltages of multiple transistors are different, it is preferable to supply a potential obtained by adding the maximum threshold voltage among them to the power supply potential to the wiring CS and the wiring CSB. This configuration allows the amount of current that flows when the transistor functioning as a switch is switched on to be sufficiently large.

[0084] The low-level potential of the signal supplied to the wirings CS and CSB is preferably low enough to turn off the transistors of the switch circuit SEL. If the transistors of the switch circuit SEL have normally-on characteristics, it is preferable to supply a lower negative potential to the wirings CS and CSB to turn them off.

[0085] When the memory cell CEL is used as a 6Tr SRAM, the wiring PL and the wiring CLB (specifically, the inverted bit line BLB shown in FIG. 6B) are connected via the switch circuit 16, and the wiring CLB is also connected to the memory cell CEL. In this case, the power supply potential VDD can be supplied to the memory cell CEL (in the figure, PL_1 = PL_2 = VDD). When the memory cell CEL is used as a 3Tr gain cell DRAM, the wiring DL and the wiring CLB (specifically, the read bit line RBL shown in FIG. 5B) are connected via the switch circuit 16, and the wiring CLB is also connected to the memory cell CEL. In FIG. 5A, the wiring DL_1 and the wiring DL_2 functioning as the read bit line RBL are illustrated as DL_1 (RBL_1) and DL_2 (RBL_2). In this case, a predetermined potential (a potential between an H level potential and an L level potential) can be supplied to the memory cell CEL.

[0086] The switch circuit 16 includes a transistor M71, a transistor M72, a transistor M73, a wiring CS, and a wiring CSB. For example, the transistors M71 and M73 are p-channel transistors. For example, the transistor M72 is an n-channel transistor. The gate of the transistor M71 is connected to the wiring CS. One of the source or the drain of the transistor M71 is connected to the wiring DL and one of the source or the drain of the transistor M72. The other of the source or the drain of the transistor M71 is connected to one of the source or the drain of the transistor M73 and the wiring CLB. The other of the source or the drain of the transistor M72, and the gates of the transistors M72 and M73, are connected to the wiring CSB. As will be described later in the description of FIG. 7 , the connection between the wiring DL or the wiring PL and the wiring CLB can be switched depending on the state of the potential input to the wiring CS and the wiring CSB.

[0087] The control circuit 15 outputs signals to control the bit line side drive circuit 12, the word line side drive circuit 13, and the switching drive circuit 14 in accordance with switching of the circuit configuration of the memory cell CEL. The circuit configuration of the memory cell CEL can be switched at a timing according to a pre-set setting, such as when the storage device 100 is started up.

[0088] The element layer 10 has a transistor having silicon (Si transistor) in a semiconductor layer having a channel formation region. The element layer 10 is an element layer in which a semiconductor layer having a channel formation region is provided in a silicon substrate, or an element layer in which a silicon semiconductor layer having a channel formation region is bonded to a silicon substrate.

[0089] Although the substrate provided in the element layer 10 is described as a silicon substrate, the present embodiment is not limited to this. The silicon substrate refers to a substrate using silicon as a semiconductor material, for example, a substrate of single crystal silicon. It is to be noted that the silicon substrate is not limited to silicon, and may be Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), SiC (silicon carbide), GaN (gallium nitride), Ga ２ O ３ A material containing gallium oxide or the like may be used for the substrate.

[0090] The Si transistors in the element layer 10 are made of highly crystalline silicon, such as single crystal silicon or polycrystalline silicon. The highly crystalline silicon in the element layer 10 allows for high field-effect mobility and faster operation. Therefore, the element layer 10 can be provided with an integrated memory cell array 11, a bit line side driver circuit 12, a word line side driver circuit 13, a switching driver circuit 14, a control circuit 15, and a switch circuit 16.

[0091] Note that the element layer 10 can also have a configuration including an arithmetic processing circuit that performs arithmetic processing using data stored in the memory cell array 11. In the memory device 100 of one embodiment of the present invention, the circuit configuration of the memory cell array 11 can be switched between SRAM memory cells and DRAM memory cells. By switching the circuit configuration of the memory cell array 11, the storage capacities and access speeds of the main memory and the cache memory can be selectively changed.

[0092] The element layer 30 includes a transistor (OS transistor) having an oxide semiconductor (metal oxide) in a semiconductor layer having a channel formation region.

[0093] An example of an oxide semiconductor used in an OS transistor is indium oxide (also referred to as In oxide or indium oxide). Indium oxide will be described in detail in Embodiment 2. An example of an oxide semiconductor used in an OS transistor is In—Ga—Zn oxide. Examples of the atomic ratio of metal elements in In—Ga—Zn oxide include a composition in which In:Ga:Zn=1:1:1 or thereabouts, a composition in which In:Ga:Zn=1:1:1.2 or thereabouts, a composition in which In:Ga:Zn=2:1:3 or thereabouts, a composition in which In:Ga:Zn=3:1:2 or thereabouts, a composition in which In:Ga:Zn=4:2:3 or thereabouts, a composition in which In:Ga:Zn=4:2:4.1 or thereabouts, a composition in which In:Ga:Zn=5:1:3 or thereabouts, a composition in which In:Ga:Zn=5:1:6 or thereabouts, a composition in which In:Ga:Zn=5:1:7 or thereabouts, a composition in which In:Ga:Zn=5:1:8 or thereabouts, a composition in which In:Ga:Zn=6:1:6 or thereabouts, and a composition in which In:Ga:Zn=5:2:5 or thereabouts.

[0094] The element layer 30 including OS transistors can be stacked over the element layer 10. Providing the element layer 30 over the element layer 10 can increase the transistor density per unit area. Furthermore, OS transistors have extremely low off-state current. Therefore, when the transistors M51 to M53 and the transistors M61 to M63 functioning as switches in the switch circuit SEL are turned off, the current flowing between the source and drain can be made extremely small. Therefore, the power consumption of the memory device 100 of one embodiment of the present invention can be reduced, and the reliability of data held in the memory cell CEL can be improved.

[0095] The element layer 30 including the OS transistor can be manufactured during the wiring process of the element layer 10. That is, the element layer 30 can be manufactured in the back end of line (BEOL). Therefore, the area overhead for providing the OS transistor can be eliminated or made extremely small. Furthermore, the current amount of the OS transistor provided in the element layer 30 can be increased by increasing the transistor size, such as the channel width.

[0096] Next, the operation of the memory cell CEL will be described with reference to Figures 4 to 6A. Figures 4 to 6A show an example in which the memory cell CEL of the memory cell array 11 in the memory device 100 shown in Figure 1A is switched using the switch circuit SEL between a circuit configuration of an SRAM with excellent operating speed and a circuit configuration with a DRAM with excellent storage density.

[0097] 4 illustrates an example of the functions of the memory cell CEL and switch circuit SEL described in FIGS. 1A and 1B. FIG. 4 illustrates a memory device having two rows and two columns of memory cells CEL_11, CEL_12, CEL_21, and CEL_22. The switch circuit SEL has a function of switching signal paths between a set of memory cells CEL, for example, memory cells CEL_11 and CEL_12. FIG. 4 illustrates two switch circuits SEL: a switch circuit SEL_1 that switches the connection state of two paths provided between memory cells CEL_11 and CEL_12, and a switch circuit SEL_2 that switches the connection state of two paths provided between memory cells CEL_21 and CEL_22.

[0098] The switch circuit SEL_1 provided between the memory cell CEL_11 and the memory cell CEL_12 includes a transistor that functions as a switch. In FIG. 4, switches SW51 to SW53 and SW61 to SW63 are illustrated as switches corresponding to the transistors M51 to M53 and the transistors M61 to M63 shown in FIG. 1A. In FIG. 4, the switch circuit SEL_2 provided between the memory cell CEL_21 and the memory cell CEL_22 includes switches SW71 to SW73 and SW81 to SW83.

[0099] 1A , memory cell CEL_11 includes transistors M13, M12, and M16. Memory cell CEL_12 includes transistors M14, M11, and M15. Memory cell CEL_21 includes transistors M23, M22, and M26. Memory cell CEL_22 includes transistors M24, M21, and M25. In memory cells CEL_11 to CEL_22 shown in FIG. 4 , the transistors are connected in the same manner as in FIG. 1A .

[0100] 4 illustrates wirings RLA_1, RLB_1, RLA_2, and RLB_2 as wirings that function as word lines. Also, FIG. 4 illustrates wirings CLA_1, CLB_1, CLA_2, and CLB_2 as wirings that function as bit lines. As shown in FIG. 4, wirings RLA_1 and RLB_1 are connected to transistors included in memory cells CEL_11 and CEL_12. Also, as shown in FIG. 4, wirings RLA_2 and RLB_2 are connected to transistors included in memory cells CEL_21 and CEL_22. Also, as shown in FIG. 4, wirings CLA_1 and CLB_1 are connected to transistors included in memory cells CEL_11 and CEL_21. Also, as shown in FIG. 4, wirings CLA_2 and CLB_2 are connected to transistors included in memory cells CEL_12 and CEL_21.

[0101] 5A is a diagram illustrating a case where the switches (switches SW51, SW61, SW71, and SW81) of switch circuits SEL_1 and SEL_2 are turned on and the switches (switches SW52, SW53, SW62, SW63, SW72, SW73, SW82, and SW83) are turned off in the 2-row, 2-column memory device 100 shown in FIG. 4, and memory cells CEL_11, CEL_12, CEL_21, and CEL_22 are used as a circuit configuration of a 3Tr gain cell. In FIG. 5A, "ON" is added to the reference numerals of switches SW51, SW61, SW71, and SW81 to indicate that they are on. The switching of each switch circuit is performed by the switching drive circuit 14 as described above.

[0102] With this configuration, the memory cells CEL_11 and CEL_12, whose circuit configurations are controlled by the switch circuit SEL_1, can have a circuit configuration in which they are electrically separated by switches that are off (switches SW52, SW53, SW62, and SW63) and switches that are on (switches SW51 and SW61). Similarly, the memory cells CEL_21 and CEL_22, whose circuit configurations are controlled by the switch circuit SEL_2, can have a circuit configuration in which they are electrically separated by switches that are off (switches SW72, SW73, SW82, and SW83) and switches that are on (switches SW71 and SW81).

[0103] At this time, as shown in FIG. 5A, the wiring RLA_1 shown in FIG. 4 functions as a write word line WWL_1 for writing data (shown as RLA_1 (WWL_1) in the figure). As shown in FIG. 5A, the wiring RLB_1 shown in FIG. 4 functions as a read word line RWL_1 for reading data (shown as RLB_1 (RWL_1) in the figure). As shown in FIG. 5A, the wiring CLA_1 shown in FIG. 4 functions as a write bit line WBL_1 for writing data (shown as CLA_1 (WBL_1) in the figure). As shown in FIG. 5A, the wiring CLB_1 shown in FIG. 4 functions as a read bit line RBL_1 for reading data (shown as CLB_1 (RBL_1) in the figure). As shown in FIG. 5A, the wiring RLA_2 shown in FIG. 4 functions as a write word line WWL_2 for writing data (shown as RLA_2 (WWL_2) in the figure). As shown in FIG. 5A, the wiring RLB_2 shown in FIG. 4 functions as a read word line RWL_2 for reading data (shown as RLB_2 (RWL_2) in the figure). As shown in FIG. 5A, the wiring CLA_2 shown in FIG. 4 functions as a write bit line WBL_2 for writing data (shown as CLA_2 (WBL_2) in the figure). As shown in FIG. 5A, the wiring CLB_2 shown in FIG. 4 functions as a read bit line RBL_2 for reading data (shown as CLB_2 (RBL_2) in the figure). Signals on each wiring can be switched by the bit line side driver circuit 12 and the word line side driver circuit 13.

[0104] Note that the wiring CLB can be connected to the wiring DL or the wiring PL via the switch circuit 16 shown in FIG. 3B. The wiring DL functions as a read bit line RBL for reading data. Specifically, as shown in FIG. 5A, it can be used as a read bit line RBL_1 or RBL_2. The wiring PL functions as a wiring that supplies a power supply potential VDD. Specifically, as shown in FIG. 6A, it can be used as PL_1=VDD and PL_2=VDD.

[0105] Next, a configuration example of a circuit that can be used as the switch circuit 16 shown in FIG. 1A and the like will be described. FIGS. 3C and 3D are circuit diagrams showing an example configuration of the switch circuit 16. The wiring DL can be connected to the wiring CLB via a switch (e.g., the switch SW101 and the switch SW111 shown in FIG. 1A). As shown in FIG. 3D, the switch is an analog switch combining a transistor M71 and a transistor M72. The wiring PL can be connected to the wiring CLB via a switch (e.g., the switch SW102 and the switch SW112 shown in FIG. 1A). The connection between the wiring DL or the wiring PL and the wiring CLB can be switched by switching the conduction state of the switch between the wiring DL and the wiring CLB and the switch between the wiring PL and the wiring CLB. The wiring CS and the wiring CSB can be used as the gates of the analog switches and the gates of the p-channel transistors of the switch circuit 16.

[0106] 7A and 7B illustrate the switching operation of the switch circuit 16. In FIGS. 7A and 7B, a cross is superimposed on the symbol of a non-conductive transistor. As shown in FIG. 7A, when a low-level potential is input to the line CS and a high-level potential is input to the line CSB (CS=L, CSB=H in the figure), the line DL and the line CLB can be connected. When a predetermined potential (a potential between H and L) is supplied to the line DL and the line CLB (DL=RBL in the figure), the line DL and the line CLB can be used as the read bit line RBL. As shown in FIG. 7B, when a high-level potential is input to the line CS and a low-level potential is input to the line CSB (CS=H, CSB=L in the figure), the line PL and the line CLB can be connected. In this way, when the power supply potential VDD is supplied from the wiring PL to the wiring CLB (in the figure, PL=VDD), the wiring PL can be used as a wiring for supplying the power supply potential VDD. The connection relationship of the switch circuit 16 shown in Figure 7A is used when the memory cell CEL operates as a 3Tr type gain cell. Also, the connection relationship of the switch circuit 16 shown in Figure 7B is used when the memory cell CEL operates as a 6Tr type SRAM.

[0107] By switching the switch circuit SEL_1 shown in Figure 5A and switching the signals on each wiring, memory cell CEL_11, which has transistors M13, M12, and M16, can be configured as a 3Tr-type gain cell DRAM circuit. This circuit configuration is shown in Figure 5B. Figure 5B illustrates memory cell CEL, which has transistors M13, M12, and M16 and is connected to write word line WWL, read word line RWL, write bit line WBL, and read bit line RBL. Similarly, memory cell CEL_12, which has transistors M14, M11, and M15, can be configured in a similar manner.

[0108] 5A, by switching the switch circuit SEL_2 and the signals on the wiring, a memory cell CEL_21 having transistors M23, M22, and M26 can also be configured as a 3Tr gain cell DRAM circuit. This circuit configuration is also shown in FIG. 5B. Similarly, a similar circuit configuration can be configured for memory cell CEL_22 having transistors M24, M21, and M25.

[0109] 5A and 5B , the memory device 100 of one embodiment of the present invention can be used as a DRAM with a 3Tr gain cell by switching the switch circuit SEL and switching signals of each wiring. The DRAM with a 3Tr gain cell has a higher memory density and requires less energy for rewriting than an SRAM, and can be used as a memory cell.

[0110] 8A and 8B are circuit diagrams illustrating an example of the arrangement of a switch circuit SEL connected to two memory cells CEL. The memory cells CEL and switches (e.g., switches SW51, SW52, and SW53 shown in FIG. 5A) are shown as blocks. A switch circuit (e.g., switch circuit SEL_1 shown in FIG. 5A) is composed of multiple switches. The switch circuit SEL in the diagram is shown enclosed by a two-dot chain line. FIG. 8A is a schematic diagram illustrating a case where two memory cells CEL are used as a 3Tr gain cell, with crosses superimposed on the symbols of switches that are in a non-conductive state (e.g., switches SW52 and SW53 shown in FIG. 5A). FIG. 8B is a schematic diagram illustrating a case where two memory cells CEL are used as a single 6Tr SRAM, with crosses superimposed on the symbols of switches that are in a non-conductive state (e.g., switch SW51 shown in FIG. 6A).

[0111] As shown in FIG. 8A, the wirings RLB_1 and RLB_2 have multiple parts, and switches are provided between each of the multiple parts. The switches between each of the multiple parts can be turned on to function as a single wiring. On the other hand, as shown in FIG. 8B, the switches between each of the multiple parts of the wirings RLB_1 and RLB_2 can be turned off to disconnect each of the multiple parts. Furthermore, the switches can also be provided around the memory cell array 11. This allows the connection between the word line side driver circuit and the memory cell CEL via the wirings RLB_1 and RLB_2 to be disconnected.

[0112] 9A and 9B are schematic diagrams illustrating an example of the arrangement of switch circuits SEL connected to two memory cells CEL. In order to facilitate understanding of the arrangement of an element layer 30 having switch circuits SEL superimposed on an element layer 10 having memory cells CEL illustrated in FIG. 9A, the schematic diagrams are indicated with X, Y, and Z directions. The schematic diagrams of FIGS. 9A and 9B correspond to top views viewed from the Z direction. Furthermore, the memory cells CEL arranged in the rows and columns of the X and Y directions are indicated with column numbers such as the first column, the second column, and the first row, the second row.

[0113] 9A, a switch circuit SEL is provided that is connected to memory cells CEL in the first and second columns of the first row. Similarly, a switch circuit SEL is provided that is connected to memory cells CEL in the third and fourth columns. The same applies to the second row and beyond. In other words, the illustration shows switch circuits SEL that are connected to adjacent memory cells CEL, such as a memory cell CEL in an odd-numbered column and a memory cell CEL in an even-numbered column.

[0114] 9A, by turning off the switches of the switch circuit SEL, eight memory cells CEL arranged in two rows and four columns can be used as a circuit configuration of a 3Tr gain cell DRAM. Also, by turning on the switches of the switch circuit SEL, a combination of four pairs of adjacently arranged memory cells CEL can be used as a circuit configuration of a 6Tr SRAM.

[0115] 9B, a switch circuit SEL is provided that is connected to the memory cells CEL in the first row and the first and third columns. Similarly, a switch circuit SEL is provided that is connected to the memory cells CEL in the second and fourth columns. The same applies to the second row and beyond. In other words, the two memory cells CEL (first memory cell and second memory cell) connected to the switch circuit SEL are arranged with another memory cell (a third memory cell arranged between the first memory cell and the second memory cell) sandwiched between them.

[0116] 9B, by turning off the switches of the switch circuit SEL, eight memory cells CEL arranged in two rows and four columns can be used as a circuit configuration of a 3Tr gain cell DRAM, as in the case of Fig. 9A. Also, in Fig. 9B, by turning on the switches of the switch circuit SEL, a combination of four pairs of adjacently arranged memory cells CEL can be used as a circuit configuration of a 6Tr SRAM, as in the case of Fig. 9A.

[0117] 9B, the circuit configuration of the 6Tr SRAM allows the four transistors to be arranged in a common centroid configuration. In other words, the pass transistors (transistors M13 and M14 in FIG. 6B), the pull-up transistors (transistors M15 and M16 in FIG. 6B), and the pull-down transistors (transistors M11 and M12 in FIG. 6B) of the 6Tr SRAM can be arranged at separate locations, thereby reducing the variation (mismatch) in the characteristics of paired transistors. This allows for a highly reliable memory device.

[0118] 6A is a diagram illustrating a case where the switches (switches SW52, SW53, SW62, and SW63) of switch circuits SEL_1 and SEL_2 are turned on and memory cells CEL_11 to CEL_22 are used as a 6Tr SRAM circuit configuration in the 2-row, 2-column memory device 100 shown in FIG. 4. In FIG. 6A, "ON" is added to the reference symbols of switches SW52, SW53, SW62, and SW63 to indicate that switches SW52, SW53, SW62, and SW63 are on. The switching of each switch circuit can be controlled by a switching drive circuit 14.

[0119] 4 is non-conductive. This is because switches SW51, SW61, SW71, and SW81 are turned off. As a result, the connection between the gate of transistor M16 and the gate of transistor M15, and the connection between the gate of transistor M26 and the gate of transistor M25 are non-conductive.

[0120] With this configuration, memory cells CEL_11 and CEL_12, whose circuit configurations are controlled by switch circuit SEL_1, can have a circuit configuration in which they are connected by on-state switches SW52, SW53, SW62, and SW63. Similarly, memory cells CEL_21 and CEL_22, whose circuit configurations are controlled by switch circuit SEL_2, can have a circuit configuration in which they are connected by on-state switches SW72, SW73, SW82, and SW83.

[0121] In this case, the wiring RLA_1 shown in FIG. 4 functions as the word line WL_1 as shown in FIG. 6A (illustrated as RLA_1(WL_1) in the drawing). The wiring CLA_1 shown in FIG. 4 functions as the bit line BL_1 as shown in FIG. 6A (illustrated as CLA_1(BL_1) in the drawing). The wiring RLA_2 shown in FIG. 4 functions as the word line WL_2 as shown in FIG. 6A (illustrated as RLA_2(WL_2) in the drawing). The wiring CLA_2 shown in FIG. 4 functions as the inverted bit line BLB_1 as shown in FIG. 6A (illustrated as CLA_2(BLB_1) in the drawing). The wiring CLA_2 shown in FIG. 4 functions to supply the power supply potential VDD to the wiring PL_1 as shown in FIG. 6A (illustrated as PL_1=VDD in the drawing). 4 functions as a wiring that supplies the power supply potential VDD to the wiring PL_2 (PL_2=VDD in the drawing), as shown in FIG. 6A. Signals on each wiring can be switched by the bit line side driver circuit 12 and the word line side driver circuit 13.

[0122] By switching the switch circuit SEL_1 shown in Figure 6A and switching the potentials of the wiring, the memory cell CEL_1112 including transistors M13, M12, and M16, as well as transistors M14, M11, and M15, can be configured as a 6-Tr SRAM circuit. Figure 6B shows this circuit configuration. Figure 6B illustrates the memory cell CEL_1112 including transistors M11 to M16 and connected to the word line WL, bit line BL, inverted bit line BLB, and power supply potential VDD.

[0123] Similarly, by switching the switch circuit SEL_2 shown in FIG. 6A and switching the potentials of the wirings, the memory cell CEL_2122 including the transistors M21 to M26 can be changed into the memory cell CEL_1112 having the circuit configuration of a 6Tr SRAM shown in FIG. 6B.

[0124] 6A and 6B , the memory device 100 of one embodiment of the present invention can be used as a 6Tr SRAM by switching the switch circuit SEL and switching the potentials and signals of the wirings. The 6Tr SRAM can be used as a memory cell with a higher operating speed than a DRAM.

[0125] As described above, the memory device 100 of one embodiment of the present invention can be used as either a 3Tr gain cell DRAM or a 6Tr SRAM by switching the switch circuit SEL and switching the potentials and signals of the wirings. Therefore, the memory device 100 can be flexibly changed between a 3Tr gain cell DRAM, which has high memory density, low rewrite energy, and high rewrite endurance, and a 6Tr SRAM, which has excellent operating speed, after manufacturing the memory device 100, depending on the application. Therefore, the memory device 100 can be provided with excellent convenience.

[0126] It is also possible to configure the memory device 100A in FIG. 10A with capacitors C11, C12, C21, and C22. In this case, the circuit configuration can be switched between the 3Tr gain cell of FIG. 10B and the 6Tr SRAM of FIG. 10C by turning on or off the switch circuits SEL_1 and SEL_2 and switching the signals or potentials of the respective wirings. In FIG. 10B, in addition to the connection relationship of FIG. 5B, one electrode of the capacitor C11 is connected to the gate of the transistor M12. The other electrode of the capacitor C11 is connected to one of the source or drain of the transistor M12 and a constant potential line (e.g., ground line). In FIG. 10C, in addition to the connection relationship of FIG. 6B, one electrode of the capacitor C11 is connected to one of the source or drain of the transistor M13. The other electrode of the capacitor C11 is connected to the other of the source or drain of the transistor M13. One electrode of the capacitor C12 is connected to one of the source and drain of the transistor M12, and the other electrode of the capacitor C12 is connected to the other of the source and drain of the transistor M12.

[0127] 11A, when switch SW52 is on, one terminal of switch SW63 is connected to either the source or drain of transistor M13, and the other terminal is connected to either the source or drain of transistor M15 via switch SW52. Similarly, when switch SW72 is on, one terminal of switch SW83 is connected to either the source or drain of transistor M23, and the other terminal is connected to either the source or drain of transistor M25 via switch SW72. As in the case of FIG. 6A, the circuit configuration can be switched between the 3Tr gain cell of FIG. 11B and the 6Tr SRAM of FIG. 11C.

[0128] Furthermore, a back gate may be provided in each memory cell, and a potential may be applied from the back gate to control the electrical characteristics of the transistor included in the memory cell. With this configuration, the electrical characteristics of the transistor can be improved.

[0129] 12A to 12C are cross-sectional schematic diagrams illustrating the arrangement of the switch circuit SEL included in the element layer 10 and the memory cell CEL included in the element layer 30 illustrated in Fig. 1A etc. In Fig. 12A to 12C, in order to facilitate understanding of how the element layer 10 and the element layer 30 illustrated in Fig. 1A are stacked, the cross-sectional schematic diagrams are illustrated with the Z direction, as well as the X direction and Y direction.

[0130] 12A is a diagram showing a configuration example in which an element layer 30 is provided on the element layer 10 shown in FIG. 3A. As described above, the element layer 10 is provided with memory cells CEL, and the element layer 30 is provided with switch circuits SEL connected to two memory cells CEL. The element layer 30 includes a transistor 51 having an oxide semiconductor in a semiconductor layer 52 having a channel formation region. The element layer 10 also includes a transistor 53 having silicon in a semiconductor layer 54 having a channel formation region.

[0131] The switch circuit SEL is configured to be disposed in a different element layer from the memory cells CEL. This configuration allows for a larger memory capacity, i.e., a larger number of memory cells CEL, compared to when the memory cells CEL and the switch circuit SEL are disposed on the same element layer. The switch circuit SEL can be fabricated in the back-end of the line (BEOL). Therefore, there is no area overhead for providing OS transistors. Furthermore, by using OS transistors as the switch circuits SEL connected to two memory cells CEL, the off-state current flowing when the switch circuits SEL are off can be significantly reduced. This configuration allows for a memory device with a smaller circuit area and lower power consumption.

[0132] 12B is a modified example of the cross-sectional schematic diagram shown in FIG. 12A. In FIG. 12B, circuits including a Si transistor 53 are provided in an element layer 10. These circuits include a bit line side driver circuit 12, a word line side driver circuit 13, a switching driver circuit 14, a control circuit 15, and a switch circuit 16. In FIG. 12B, a memory cell CEL including an OS transistor 51 is provided in an element layer 20 above the element layer 10. In FIG. 12B, a switch circuit SEL including an OS transistor 51 is provided in an element layer 30 above the element layer 20.

[0133] By arranging the memory cells CEL and the drive circuits that drive the memory cells CEL and the switch circuits SEL on different element layers, the memory capacity, i.e., the number of memory cells CEL, can be increased compared to when the memory cells CEL and the drive circuits are arranged on the same element layer. Furthermore, by arranging the memory cells CEL and the switch circuits SEL on different element layers, the memory capacity, i.e., the number of memory cells CEL, can be increased compared to when the memory cells CEL and the switch circuits SEL are arranged on the same element layer. In addition, the increase in circuit area associated with adding switch circuits SEL can be suppressed. Furthermore, the transistor structures or semiconductor materials of the semiconductor layers can be different between the element layers 20 and 30. This allows for a memory device that achieves reduced circuit area, lower power consumption, and higher speeds.

[0134] 12B, each transistor included in the memory cell CEL provided in the element layer 20 can be an OS transistor. A storage device including a memory cell having an OS transistor may be referred to as an "OS memory."

[0135] As described above, the off-state current of an OS transistor is extremely low. Therefore, charge corresponding to data written to the memory cell CEL can be held for a long time. That is, data once written to the memory cell CEL can be held for a long time. Therefore, the frequency of data refresh can be reduced, and the power consumption of the memory device 100 of one embodiment of the present invention can be reduced.

[0136] The memory cells having OS transistors described with reference to FIGS. 10A to 10C can be nonvolatile oxide semiconductor random access memories (NOSRAMs). NOSRAMs rewrite data by charging and discharging a capacitor, so in principle, there is no limit to the number of rewrites and they require low energy. Therefore, NOSRAMs can operate at high speed, consume low power, and have high rewrite endurance. Furthermore, NOSRAMs can read written data nondestructively, making them suitable for long-term data retention.

[0137] Fig. 12C is a modified example of the cross-sectional schematic diagram shown in Fig. 12B. In Fig. 12C, an arithmetic processing circuit 17 for performing arithmetic processing and having a transistor 53 that is a Si transistor is provided in the element layer 10. An element layer 20 and an element layer 30 are provided above the element layer 10, similar to Fig. 12B.

[0138] A storage device with a computing function can be realized by arranging the element layer 20 having the memory cell CEL on the element layer 10 provided with the arithmetic processing circuit 17. In the storage device with a computing function, the signal propagation distance between the memory cell CEL functioning as a main memory or cache memory and the arithmetic processing circuit 17 that performs arithmetic processing using the data stored in the memory cell CEL can be shortened. This allows for faster data writing and reading between a memory circuit such as a register in the arithmetic processing circuit 17 and the storage device functioning as a cache memory or main memory. Furthermore, the number of wirings between each circuit can be increased, thereby improving the bandwidth (also referred to as memory bandwidth) of the storage device. Therefore, in the storage device with a computing function, the memory cell CEL can be used for applications such as a high bandwidth memory (HBM).

[0139] As described above, the memory device 100 of one embodiment of the present invention can be used as a DRAM with a 3Tr gain cell or a 6Tr SRAM by switching the switch circuit SEL and switching the potentials and signals of the wirings. Therefore, the memory device 100 can be flexibly changed between a DRAM with a 3Tr gain cell, which has high memory density, low rewrite energy, and high rewrite endurance, and a 6Tr SRAM, which has excellent operating speed, after manufacturing the memory device 100, depending on the application. Therefore, the memory device can be highly convenient.

[0140] The structures, configurations, methods, and the like described in this embodiment can be used in appropriate combination with structures, configurations, methods, and the like described in other embodiments.

[0141] Embodiment 2 In this embodiment, an indium oxide film that can be used for a semiconductor layer of a transistor included in a memory device of one embodiment of the present invention will be described.

[0142] In this specification and the like, indium oxide having at least a crystalline portion or a crystalline region in a film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystalline IO or crystalline IO include single-crystalline indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0143] Indium oxide is a semiconductor material having physical properties that are completely different from those of oxide semiconductors such as In—Ga—Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0144] The carrier concentration dependence of the Hall mobility of indium oxide, silicon, and IGZO will be explained. FIG. 13A shows the Hall mobility of silicon (Si) and indium oxide (InO Ｘ ) and FIG. 13B is a schematic diagram showing the carrier concentration dependence of the hole mobility for IGZO.

[0145] First, IGZO tends to exhibit higher hole mobility as the carrier concentration increases, as shown by the arrows in Figure 13B. On the other hand, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases, as shown by the arrows in Figure 13A (see Non-Patent Document 1). This trend is similar to that of silicon; the lower the dopant (impurity) concentration in the material, the less impurity scattering there is and the higher the hole mobility. In other words, the higher the purity and intrinsic indium oxide, the higher the hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to those of silicon. Note that the characteristics of indium oxide shown in Figure 13A are assumed to be single crystal. Therefore, when indium oxide is non-single crystal (e.g., polycrystalline), the characteristics may differ from those shown in Figure 13A.

[0146] 13A, the range R1 of low carrier concentration has extremely high hole mobility, and therefore can be said to be a range of carrier concentration suitable for, for example, a channel formation region of a transistor. For example, in the case of indium oxide, the range R1 is a range where the carrier concentration value is 1×10 １５ cm −３ The range includes, for example, 1×10 １４ cm −３ That's it, 1 x 10 １８ cm −３ By sufficiently reducing the carrier concentration, the Hall mobility value can be increased to 270 cm ２ It is expected that the resistance can be increased to about / (V·s).

[0147] In addition, in indium oxide, the region where the carrier concentration is in the range R1 may contain an element that lowers the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Examples of elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0148] On the other hand, the range R2 with a high carrier concentration has a low electrical resistance, and can be said to be a range of carrier concentrations suitable for, for example, the source and drain regions of a transistor, a resistor, or a transparent conductive film. ２０ cm −３ The range includes, for example, 1×10 １９ cm −３ That's it, 1 x 10 ２２ cm −３ By increasing the carrier concentration sufficiently, the resistivity can be reduced to 1×10 −４ It is expected that the resistivity can be reduced to Ω·cm or less.

[0149] In the indium oxide, the region having a carrier concentration in the range R2 may contain an element that increases the carrier concentration. For example, it is preferable that the indium oxide contains an element that is common to the source electrode and the drain electrode of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use an element whose oxide has conductive or semiconductive properties.

[0150] In this way, indium oxide uses a region with a low carrier concentration as the channel formation region of a transistor, and a region with a high carrier concentration as the source and drain regions of the transistor. In other words, indium oxide can be said to be an oxide capable of valence electron control. Note that IGZO may experience strain in the source and drain regions due to stress from electrodes in contact with the IGZO, resulting in the formation of n-type regions. On the other hand, unlike IGZO, indium oxide is capable of valence electron control, and therefore does not require strain to be formed in the film as with IGZO. Less strain in the film is expected to improve reliability. For example, by separately creating a region with a carrier concentration in the range R1 shown in FIG. 13A and a region with a carrier concentration in the range R2 in the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Note that valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technical concept that would not normally be conceived.

[0151] By using the above technical concept, the transistor having indium oxide in this specification and the like has two or more, preferably three or more, more preferably four or more, and most preferably five of the following characteristics (1) to (5): (1) high on-current (in other words, high mobility); (2) low off-current; (3) normally-off operation; (4) high reliability; and (5) high cutoff frequency (fT). For example, the transistor having indium oxide in this specification and the like has high mobility, low off-current, and is normally-off operation. The transistor has high mobility and is different from a normally-on transistor.

[0152] Next, an indium oxide film applied to a transistor will be described. The indium oxide film preferably has crystallinity (i.e., has crystal grains). Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains (also called microcrystalline films). In particular, the indium oxide film is preferably a polycrystalline film, and more preferably a single-crystal film. A single-crystal film does not have grain boundaries. Impurities (typically, insulating impurities, insulating oxides, etc.) that hinder carrier flow tend to segregate at grain boundaries. The use of a single-crystal film can suppress carrier scattering at grain boundaries, thereby realizing a transistor exhibiting high field-effect mobility. Furthermore, the use of a single-crystal film has the excellent effect of suppressing variations in transistor characteristics due to the grain boundaries.

[0153] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using a polycrystalline film, it is preferable to use a film with as large a crystal grain size as possible and with few crystal grain boundaries. Note that in a transistor using an indium oxide polycrystalline film, if there is no crystal grain boundary in the channel formation region or no crystal grain boundary is observed, the channel formation region is located within a single crystal region included in the polycrystalline film, and therefore the transistor can be considered to be using single-crystal indium oxide.

[0154] The crystallinity of indium oxide can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0155] In this specification and the like, a semiconductor layer in which no crystal grain boundary is observed in the channel formation region, a semiconductor layer in which the channel formation region is included in one crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions in the channel formation region can be called a single crystal film. Alternatively, a semiconductor layer in which, in the channel formation region, within one crystal grain, the direction of another crystal axis changes continuously around a certain crystal axis or a certain crystal orientation as the axis of rotation can be called a single crystal film.

[0156] The channel formation region refers to a region of the semiconductor layer that overlaps (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, crystal grain boundaries, crystal axes, crystal orientation, etc. in the channel formation region can be confirmed by observing a cross section including the semiconductor layer, the source electrode, and the drain electrode.

[0157] The indium oxide film in the channel formation region preferably has a lower impurity concentration. Impurities in the indium oxide film in the channel formation region can be a scattering source of carriers, which can lead to a decrease in field-effect mobility. These impurities can also hinder the crystal growth of the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The indium oxide film preferably contains these impurities at concentrations of 0.1% or less, and more preferably 0.01% (100 ppm) or less. Carbon, hydrogen, and other elements may be contained in the film-forming gas or precursor during film formation, and may remain in the indium oxide film in greater amounts than the above-mentioned impurities.

[0158] The indium oxide film in the channel formation region may contain an element that can become the same trivalent cation as indium, as long as the crystal maintains a cubic crystal structure (bixbyite type). Examples of such an element include Group 13 elements of the periodic table, such as gallium and aluminum, and Group 3 elements of the periodic table. These elements exist mainly as trivalent cations in oxides, and therefore the carrier concentration of indium oxide can be maintained low.

[0159] By using such an indium oxide film in a transistor, the field effect mobility of the transistor can be increased to 50 cm ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ / (V·s) or more.

[0160] One of the features of an indium oxide film is that it has higher oxygen permeability (diffusibility) than an IGZO film. As shown in FIG. 13C, an indium oxide film (InO Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and becomes oxygen molecules (O ２ ) and is released as water molecules (H ２ O) may be released in the film. Ｏ In the case where an indium oxide film is present, oxygen atoms diffuse to compensate for the oxygen vacancies. Since oxygen diffuses easily in the indium oxide film, it can be said that oxygen vacancies are more easily compensated for in the indium oxide film than in the IGZO film.

[0161] As described above, an indium oxide film can more easily reduce oxygen vacancies in the film than an IGZO film. Therefore, by using such an indium oxide film in a transistor, a transistor with extremely high reliability can be realized.

[0162] Furthermore, as shown in FIG. 13C, the indium oxide film diffuses hydrogen. Hydrogen that diffuses into the indium oxide film from the outside passes through the indium oxide film and becomes hydrogen molecules (H ２ ) or reacts with oxygen contained in the membrane and is released as water molecules.

[0163] A transistor using an indium oxide film is an accumulation-type transistor that uses electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of the electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, for a transistor, the on-state current or field-effect mobility of the transistor can be increased.

[0164] Table 1 shows the results of single crystal indium oxide (here, In ２ O ３ ) and single-crystal silicon (Si). As shown in Table 1, indium oxide is characterized by a small effective mass of electrons and a large effective mass of holes. Indium oxide also has the characteristic that the effective mass of electrons is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in a transistor, a transistor with high field-effect mobility and high frequency characteristics (also called f characteristics) can be realized. Furthermore, since the effective mass of holes is large, a transistor with extremely small off-current can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width can be reduced to 1 fA (1×10) in an environment of 125° C. −１５ A) or less, or 1aA (1 x 10 −１８ A) or less, and under room temperature (25°C) conditions, −１８ A) or less, or 1zA (1 x 10 −２１ Furthermore, as shown in Table 1, indium oxide has a smaller effective mass of electrons and a larger effective mass of holes than silicon, and therefore may be able to realize a transistor with higher field-effect mobility and lower off-state current than a Si transistor.

[0165]

[0166] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. The seed layer is preferably made of a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with indium oxide. This can improve the crystallinity of the indium oxide film. Note that a substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0167] One method for evaluating the degree of lattice mismatch is to use the value of the lattice mismatch shown below. The lattice mismatch Δa [%] of the crystals of the formed film (here, the indium oxide film) with respect to the crystals of the seed layer is expressed as Δa = ((L １ -L ２ ) / L ２ ) × 100, where L １ is the length or lattice constant of the unit lattice vector of the crystal of the formed film, and L ２ is the length of the unit cell vector or the lattice constant of the crystal of the seed layer.

[0168] The smaller the absolute value of the lattice mismatch Δa between the seed layer and the indium oxide film, the more preferable, and it is most preferably 0. For example, Δa can be set to −5% or more and 5% or less, preferably −4% or more and 4% or less, more preferably −3% or more and 3% or less, and even more preferably −2% or more and 2% or less.

[0169] Here, the indium oxide crystal has a cubic crystal structure (bixbyite type). For example, the crystal of yttria-stabilized zirconia (YSZ) can have a cubic crystal structure (fluorite type). The lattice mismatch of the indium oxide crystal with the cubic YSZ crystal is in the range of −2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on the YSZ substrate.

[0170] It should be noted that the crystal structure of the seed layer and the crystal structure of the indium oxide film may not necessarily have the same crystal system or crystal orientation. For example, a film having crystals of a hexagonal or trigonal structure may be used under an indium oxide film having crystals of a cubic structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to the crystal orientation necessary for epitaxial growth can be satisfied. Examples of hexagonal or trigonal crystals include wurtzite structure, YbFe ２ O ４ Type structure, Yb ２ Fe ３ O ７ YbFeFe alloys have the following structures: ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a ZnO-type structure is IGZO.

[0171] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0172] Embodiment 3 In this embodiment, an application example of a memory device according to one embodiment of the present invention will be described.

[0173] <Memory Hierarchy of Memory Devices> Generally, various memory devices are used in semiconductor devices such as computers depending on the application. Figure 14 shows various memory devices by memory hierarchy. The higher the memory device, the faster the access speed is required, while the lower the memory device, the larger the memory capacity and recording density are required. Figure 14 shows, from the top layer, memory integrated as a register in a processing unit such as a CPU, SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), and flash memory.

[0174] The memory embedded as a register in a processing unit such as a CPU is used for temporary storage of calculation results, and is therefore frequently accessed by the processing unit. Therefore, a higher operating speed is required than a larger memory capacity. Registers also have the function of storing setting information for the processing unit.

[0175] SRAM is used, for example, as a cache. A cache has the function of storing a copy of the information stored in the main memory. By storing a copy of frequently used data in the cache, the speed of accessing the data can be increased.

[0176] DRAM is used, for example, as a main memory. The main memory has the function of storing programs or data read from storage. The recording density of DRAM is approximately 0.1 to 0.3 Gbit / mm ２ is.

[0177] 3D NAND memory is used, for example, for storage. Storage has the function of storing data that requires long-term storage or various programs used in processing units. Therefore, storage requires a large memory capacity and a high recording density rather than an operating speed. The recording density of memory devices used for storage is approximately 0.6 to 6.0 Gbit / mm ２ is.

[0178] A storage device according to one embodiment of the present invention is advantageous in that it can switch between a memory cell circuit configuration that can be used as an SRAM with excellent operating speed and a 3Tr-type gain cell circuit configuration that can be used as a DRAM with excellent memory density. The storage device according to one embodiment of the present invention can switch between a memory hierarchy 901 in which a cache memory is located and a memory hierarchy 902 in which a main memory is located. Therefore, the circuit configuration can be switched depending on the memory capacity required for each memory hierarchy.

[0179] Next, electronic components, electronic devices, and large scale computers that can use the memory device described in the above embodiment will be described. The electronic components, electronic devices, and large scale computers that use the memory device of one embodiment of the present invention are effective in achieving high performance, such as low power consumption.

[0180] [Electronic Component] FIG. 15A shows a perspective view of a substrate (mounting substrate 704) on which electronic component 709 is mounted. Electronic component 709 shown in FIG. 15A has memory device 100 inside mold 711. FIG. 15A omits some parts in order to show the interior of electronic component 709. Electronic component 709 has lands 712 on the outside of mold 711. Lands 712 are connected to electrode pads 713, and electrode pads 713 are connected to memory device 100 via wires 714. Electronic component 709 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and connected on printed circuit board 702 to complete mounting substrate 704.

[0181] The memory device 100 includes, as an example, an element layer 10 having an operation core, an element layer 20 having memory cells, and an element layer 30 having a switch circuit SEL. The element layer 20 having memory cells includes a plurality of memory cells (not shown). The stacked structure of the element layer 10 having the operation core, the element layer 20 having memory cells, and the element layer 30 having the switch circuit SEL can be a monolithic stacked structure. In a monolithic stacked structure, the layers can be connected without using through-electrode technology such as TSV (Through Silicon Via) or bonding technology such as Cu-Cu direct bonding. By forming the element layer 10 having the operation core, the element layer 20 having memory cells, and the element layer 30 having the switch circuit SEL in a monolithic stacked structure, for example, a so-called on-chip memory structure can be achieved, in which memory is formed directly on a processor. The on-chip memory structure enables the operation of the interface between the processor and memory to be faster.

[0182] Furthermore, by configuring an on-chip memory, it is possible to reduce the size of connection wiring, etc., compared to technologies that use through electrodes such as TSVs, and therefore it is possible to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).

[0183] Furthermore, it is preferable that the transistors constituting the plurality of memory cells included in the element layer 20 and the plurality of switches included in the element layer 30 are OS transistors. This configuration allows the plurality of memory cells and switch circuits to be monolithically stacked on the element layer 10 having the processor core. By configuring the plurality of memory cell arrays as monolithic stacks, it is possible to improve either or both of the memory bandwidth and the memory access latency. The bandwidth refers to the amount of data transferred per unit time, and the access latency refers to the time from access to the start of data exchange.

[0184] The storage device 100 may also be referred to as a die. In this specification, a die refers to a chip piece obtained during the semiconductor chip manufacturing process by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and dicing it into cubes. Semiconductor materials that can be used for the die include, for example, silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0185] 15B shows a perspective view of an electronic component 730. The electronic component 730 is an example of a SiP (System in Package) or an MCM (Multi-Chip Module). The electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a memory device 735 and a plurality of memory devices 100 provided on the interposer 731.

[0186] For example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used as the package substrate 732. For example, a silicon interposer or a resin interposer can be used as the interposer 731.

[0187] The interposer 731 has multiple wirings and functions to connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In addition, through electrodes may be provided in the interposer 731, and the integrated circuits and the package substrate 732 may be connected using the through electrodes. In addition, with a silicon interposer, a TSV may also be used as the through electrode.

[0188] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0189] Furthermore, in SiPs, MCMs, and the like that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, because the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on an interposer.

[0190] On the other hand, when connecting multiple integrated circuits with different terminal pitches using a silicon interposer, a TSV, or the like, a space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 730, the width of the terminal pitch becomes an issue, and it may be difficult to provide the many wirings necessary to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferable. A composite structure may be formed by combining a memory cell array stacked using TSVs and a monolithically stacked memory cell array.

[0191] A heat sink (heat dissipation plate) may be provided overlapping the electronic component 730. When providing a heat sink, it is preferable to align the height of the integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the height of the memory device 100 and the memory device 735.

[0192] Electrodes 733 may be provided on the bottom of package substrate 732 in order to mount electronic component 730 on another substrate. FIG. 15B shows an example in which electrodes 733 are formed with solder balls. By providing solder balls in a matrix on the bottom of package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, electrodes 733 may be formed with conductive pins. By providing conductive pins in a matrix on the bottom of package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0193] The electronic component 730 can be mounted on other substrates using various mounting methods, including, but not limited to, BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), and a quad flat non-leaded package (QFN).

[0194] [Electronic Device] Fig. 16A is an external view showing an example of a portable electronic device. Fig. 16B is a simplified diagram showing data exchange within the portable electronic device. Portable electronic device 595 has a printed wiring board 596, a speaker 597, a camera 598, a microphone 599, etc.

[0195] In portable electronic device 595, the electronic component 709 can be provided on printed circuit board 596. Portable electronic device 595 can improve user convenience by processing and analyzing multiple pieces of data obtained by speaker 597, camera 598, microphone 599, etc. using electronic component 709. In addition, the portable electronic device 595 can be used in systems that perform voice guidance, image search, etc.

[0196] The electronic component 709 performs arithmetic processing of the obtained image data using a neural network or the like, thereby enabling processing such as increasing the image resolution, reducing image noise, face recognition (for security purposes, etc.), object recognition (for autonomous driving purposes, etc.), image compression, image correction (wide dynamic range), image restoration for lensless image sensors, positioning, character recognition, and reduction of reflected glare.

[0197] 17A includes a housing 1101, a housing 1102, a housing 1103, a display unit 1104, a connection unit 1105, operation keys 1107, and the like. The housings 1101, 1102, and 1103 are detachable. By attaching the connection unit 1105 provided on the housing 1101 to the housing 1108, the video output to the display unit 1104 can be output to another video device. On the other hand, by attaching the housings 1102 and 1103 to the housing 1109, the housings 1102 and 1103 are integrated and function as an operation unit. The electronic component 709 can be incorporated into chips or the like provided on the substrates of the housings 1102 and 1103.

[0198] 17B shows a stick-shaped electronic device 1120 that is connected via a USB. The electronic device 1120 has a housing 1121, a cap 1122, a USB connector 1123, and a board 1124. The board 1124 is housed in the housing 1121. For example, a memory chip 1125 and a controller chip 1126 are attached to the board 1124. The electronic component 709 can be incorporated into the controller chip 1126 of the board 1124, etc.

[0199] 17C shows a humanoid robot 1130. The robot 1130 has sensors 2101 to 2106 and a control circuit 2110. For example, the control circuit 2110 can incorporate the electronic component 709 described above.

[0200] [Mainframe] The electronic component 709 can be used in a system 3000 including a mainframe that communicates with the electronic device, instead of being built into the electronic device. In this case, the electronic device and the mainframe constitute a computing system. Fig. 18 shows an example of the configuration of the system 3000.

[0201] The system 3000 is configured by an electronic device 3001 and a mainframe computer 3002. Communication between the electronic device 3001 and the mainframe computer 3002 can be carried out via an internet line 3003.

[0202] The mainframe 3002 has a plurality of racks 3004. Each rack 3004 is provided with a plurality of circuit boards 3005. The electronic components 709 described in the above embodiment can be mounted on the circuit boards 3005. This allows a neural network to be configured in the mainframe 3002, enabling input data processing. The mainframe 3002 can receive data input from the electronic device 3001 via the Internet line 3003 and perform calculations using the neural network. The results of calculations by the mainframe 3002 can be transmitted to the electronic device 3001 via the Internet line 3003 as necessary. This reduces the calculation load on the electronic device 3001.

[0203] This embodiment mode can be combined with the descriptions of other embodiment modes as appropriate.

[0204] <Additional Notes Regarding the Description of the Present Specification, etc.> The following additional notes are provided regarding the above-described embodiments and the explanations of the respective configurations in the embodiments.

[0205] The configurations shown in each embodiment can be combined with the configurations shown in other embodiments as appropriate to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate.

[0206] In addition, the content (or even a part of the content) described in one embodiment can be applied to, combined with, or replaced with another content (or even a part of the content) described in that embodiment, and / or the content (or even a part of the content) described in one or more other embodiments.

[0207] The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

[0208] Furthermore, a figure (or even a part thereof) described in one embodiment can be combined with another part of that figure, another figure (or even a part thereof) described in that embodiment, and / or a figure (or even a part thereof) described in one or more other embodiments to form even more figures.

[0209] In addition, in the block diagrams in this specification and elsewhere, components are classified by function and shown as independent blocks. However, in actual circuits and the like, it is difficult to separate components by function, and there may be cases where a single circuit is involved in multiple functions, or where a single function is involved across multiple circuits. Therefore, the blocks in the block diagrams are not limited to the components described in the specification and may be rephrased appropriately.

[0210] In addition, in the drawings, the size, layer thickness, or region is shown at an arbitrary size for convenience of explanation. Therefore, it is not necessarily limited to the scale. Note that the drawings are shown schematically for clarity, and are not limited to the shapes or values ​​shown in the drawings. For example, it is possible to include variations in signal, voltage, or current due to noise, or variations in signal, voltage, or current due to timing deviations.

[0211] In this specification and the like, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. This is because the source and drain of a transistor vary depending on the structure or operating conditions of the transistor. Note that the source and drain of a transistor can be appropriately referred to as source (drain) terminal, source (drain) electrode, or the like.

[0212] Furthermore, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where multiple "electrodes" or "wirings" are integrally formed.

[0213] Furthermore, in this specification and the like, the terms voltage and potential can be interchanged as appropriate. Voltage refers to the potential difference from a reference potential. For example, if the reference potential is a ground voltage (earth voltage), then voltage can be interchanged with potential. Ground potential does not necessarily mean 0 V. Note that potential is relative, and the potential applied to wiring, etc. may change depending on the reference potential.

[0214] In this specification and the like, terms such as "film" and "layer" may be interchangeable in some cases. For example, the term "conductive layer" may be changed to the term "conductive film." Or, for example, the term "insulating film" may be changed to the term "insulating layer."

[0215] In this specification, a switch refers to a device that has the function of being in a conductive state (on state) or a non-conductive state (off state) and controlling whether or not a current flows, or a device that has the function of selecting and switching a path for a current to flow.

[0216] Furthermore, in this specification and the like, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc. depending on the circuit configuration, device structure, etc. Furthermore, a terminal, a wiring, etc. can be referred to as a node.

[0217] In this specification and the like, the "on state" of a transistor refers to, for example, a state in which the source and drain of the transistor can be considered to be short-circuited. For example, the "on state" refers to a state in which the voltage between the gate and source of an n-channel transistor is higher than the threshold voltage, or a state in which the voltage between the gate and source of a p-channel transistor is lower than the threshold voltage. Note that the "on state" of a transistor refers to a state in which a current can flow between the source and the drain. Therefore, the "on state" of a transistor may also be referred to as the "conducting state" of the transistor.

[0218] In this specification and the like, the "off state" of a transistor refers to a state in which the source and drain of the transistor can be considered to be cut off. For example, the "off state" refers to a state in which the voltage between the gate and source of an n-channel transistor is lower than the threshold voltage, or a state in which the voltage between the gate and source of a p-channel transistor is higher than the threshold voltage. The "off state" of a transistor may also be referred to as the "non-conducting state" of the transistor.

[0219] In this specification and the like, the voltage between the gate and the source (gate-source) may be referred to as the “gate voltage,” the voltage between the drain and the source (drain-source) may be referred to as the “drain voltage,” and the voltage between the backgate and the source (backgate-source) may be referred to as the “backgate voltage.” Also, the current flowing from the drain to the source may be referred to as the “drain current.”

[0220] In this specification and the like, unless otherwise specified, the "off-state current" of a transistor refers to the drain current when the transistor is in an off state. Note that in this specification and the like, the off-state current and the current flowing from the gate to the source and drain (also referred to as gate leakage current) may also be referred to as leakage current.

[0221] In this specification, "connection" includes, as an example, "electrical connection." Note that the term "electrical connection" is sometimes used to define the connection relationship between circuit elements as an object. Furthermore, "electrical connection" includes "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the intervention of a circuit element (e.g., a transistor, a switch, etc.; note that wiring is not a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected via one or more circuit elements. Note that A and B represent objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0222] For example, assuming that a circuit including A and B is operating, if there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B, then it can be defined that "A and B are indirectly connected" as objects. Note that even if there is a time during the operation of the circuit when no electrical signal is exchanged or an interaction of electrical potential occurs between A and B, it can still be defined that "A and B are indirectly connected" as long as there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B.

[0223] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where it cannot be said that "A and B are indirectly connected" is when an insulator is present in the path from A to B. Specifically, there are cases where a capacitive element is connected between A and B, and cases where a gate insulating film of a transistor is present between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of the transistor are indirectly connected."

[0224] Another example of a case where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between one transistor and another transistor from a power supply, GND, etc.

[0225] BL: bit line, BL_1: bit line, BLB: inverted bit line, BLB_1: inverted bit line, C11: capacitor, C12: capacitor, C21: capacitor, C22: capacitor, CEL: memory cell, CEL_11: memory cell, CEL_12: memory cell, CEL_21: memory cell, CEL_22: memory cell, CEL_1112: memory cell, CEL_2122: memory cell, CLA: wiring, CLA_1: wiring, CLA_2: wiring, CLB: wiring, CLB_1: wiring, CLB_2: wiring, CS: wiring, CSB: wiring, DL: wiring, DL_1: wiring Line, DL_2: Wiring, M11: Transistor, M12: Transistor, M13: Transistor, M14: Transistor, M15: Transistor, M16: Transistor, M21: Transistor, M22: Transistor, M23: Transistor, M24: Transistor, M25: Transistor, M26: Transistor, M51: Transistor, M52: Transistor, M53: Transistor, M61: Transistor, M62: Transistor, M63: Transistor, M71: Transistor, M72: Transistor, M73: Transistor, PL: Wiring, PL _1: wiring, PL_2: wiring, RBL: read bit line, RBL_1: read bit line, RBL_2: read bit line, RLA: wiring, RLA_1: wiring, RLA_2: wiring, RLB: wiring, RLB_1: wiring, RLB_1AA: wiring, RLB_1AB: wiring, RLB_1AC: wiring, RLB_2: wiring, RWL: read word line, RWL_1: read word line, RWL_2: read word line, SEL: switch circuit, SEL_1: switch circuit, SEL_2: switch circuit, SW51: switch, SW52: switch, SW53: switch , SW61: switch, SW62: switch, SW63: switch, SW71: switch, SW72: switch, SW73: switch, SW81: switch, SW82: switch, SW83: switch, SW101: switch, SW102: switch, SW111: switch, SW112: switch, WBL: write bit line, WBL_1: write bit line, WBL_2: write bit line, WL: word line, WL_1: word line, WL_2: word line, WWL: write word line, WWL_1: write word line, WWL_2: write word line,10: element layer, 11: memory cell array, 12: bit line side drive circuit, 13: word line side drive circuit, 14: switching drive circuit, 15: control circuit, 16: switch circuit, 16_1: switch circuit, 16_2: switch circuit, 17: arithmetic processing circuit, 20: element layer, 30: element layer, 51: transistor, 52: semiconductor layer, 53: transistor, 54: semiconductor layer, 100: memory device, 100A: memory device, 100B: memory device, 595: portable electronic device, 596: printed wiring board, 597: speaker, 598: camera, 599: microphone, 702: printed circuit board, 704: mounting board, 709: electronic component, 711: mold, 712: land, 713: electrode pad, 714: wire, 730: electronic part product, 731: interposer, 732: package substrate, 733: electrode, 735: storage device, 901: memory hierarchy, 902: memory hierarchy, 1100: portable game machine, 1101: housing, 1102: housing, 1103: housing, 1104: display unit, 1105: connection unit, 1107: operation keys, 1108: housing, 1109: housing, 1120: electronic device, 1121: housing, 1122: cap, 1123: USB connector, 1124: substrate, 1125: memory chip, 1126: controller chip, 1130: robot, 2101: sensor, 2106: sensor, 2110: control circuit, 3000: system, 3001: electronic device, 3002: mainframe computer, 3003: internet line, 3004: rack, 3005: substrate,

Claims

a first memory cell; a second memory cell; a switch circuit, the switch circuit is electrically connected to the first memory cell and the second memory cell; the switch circuit has a function of switching a connection state between the first memory cell and the second memory cell between a first state and a second state; In the first state, the first memory cell and the second memory cell operate as a DRAM including three different transistors; In the second state, the first memory cell and the second memory cell operate as an SRAM consisting of six transistors in total. storage device. 　 a memory cell array and a switch circuit; the memory cell array includes a first memory cell and a second memory cell; the switch circuit has a first terminal, a second terminal, a third terminal, a fourth terminal, a fifth terminal, a sixth terminal, a seventh terminal, an eighth terminal, a ninth terminal, and a tenth terminal; the first terminal, the third terminal, and the fifth terminal are electrically connected to the first memory cell; the second terminal, the fourth terminal, and the seventh terminal are electrically connected to the second memory cell; the sixth terminal and the ninth terminal are electrically connected to each other, the eighth terminal and the tenth terminal are electrically connected to each other, the switch circuit has a function of establishing a conductive state or a non-conductive state between the first terminal and the second terminal, the switch circuit has a function of establishing a conductive state or a non-conductive state between the third terminal and the fourth terminal, the switch circuit has a function of establishing a conductive state or a non-conductive state between the fifth terminal and the sixth terminal, the switch circuit has a function of establishing a conductive state or a non-conductive state between the seventh terminal and the eighth terminal, the switch circuit has a function of establishing a conductive state or a non-conductive state between the ninth terminal and the tenth terminal, In a first state, the first terminal and the second terminal, the third terminal and the fourth terminal, the fifth terminal and the sixth terminal, and the seventh terminal and the eighth terminal are respectively in a non-conductive state, and the ninth terminal and the tenth terminal are in a conductive state; In the first state, the first memory cell and the second memory cell operate as different memory cells; In the second state, the first terminal and the second terminal, the third terminal and the fourth terminal, the fifth terminal and the sixth terminal, and the seventh terminal and the eighth terminal are respectively brought into a conductive state, and the ninth terminal and the tenth terminal are brought into a non-conductive state; In the second state, the first memory cell and the second memory cell operate as a single memory cell. storage device. 　 In claim 2, the first memory cell has a first transistor; the second memory cell has a second transistor; a gate of the first transistor electrically connected to the sixth terminal and the ninth terminal; one of the source and the drain of the first transistor is electrically connected to the first terminal; a gate of the second transistor electrically connected to the eighth terminal and the tenth terminal; one of the source and the drain of the second transistor is electrically connected to the fourth terminal; the first transistor and the second transistor are each a p-channel transistor; In the first state, a gate of the first transistor and a gate of the second transistor are brought into a conductive state via the ninth terminal and the tenth terminal, In the second state, the third terminal and the gate of the first transistor are brought into a conductive state via the fifth terminal and the sixth terminal, and the second terminal and the gate of the second transistor are brought into a conductive state via the seventh terminal and the eighth terminal. storage device. 　 a first memory cell, a second memory cell, a switch circuit, and first to fourth wirings; the first memory cell includes a first transistor, a second transistor, and a third transistor; the second memory cell includes a fourth transistor, a fifth transistor, and a sixth transistor; the switch circuit includes a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor; one of the source and the drain of the first transistor is electrically connected to the gate of the second transistor; one of the source and the drain of the second transistor is electrically connected to one of the source and the drain of the third transistor; one of the source and the drain of the fourth transistor is electrically connected to the gate of the fifth transistor; one of the source and the drain of the fifth transistor is electrically connected to one of the source and the drain of the sixth transistor; one of the source and the drain of the seventh transistor is electrically connected to one of the source and the drain of the first transistor and the gate of the second transistor; the other of the source or the drain of the seventh transistor is electrically connected to one of the source or the drain of the fifth transistor and one of the source or the drain of the sixth transistor; one of the source or the drain of the eighth transistor is electrically connected to one of the source or the drain of the second transistor and one of the source or the drain of the third transistor; the other of the source or the drain of the eighth transistor is electrically connected to one of the source or the drain of the fourth transistor and the gate of the fifth transistor; one of the source and the drain of the ninth transistor is electrically connected to one of the source and the drain of the tenth transistor, the gate of the third transistor, and the second wiring; the other of the source and the drain of the ninth transistor is electrically connected to the third wiring; the other of the source or the drain of the tenth transistor is electrically connected to the one of the source or the drain of the first transistor and the gate of the second transistor; one of the source and the drain of the eleventh transistor is electrically connected to one of the source and the drain of the twelfth transistor, the gate of the sixth transistor, and the third wiring; the other of the source and the drain of the eleventh transistor is electrically connected to the fourth wiring; the other of the source or the drain of the twelfth transistor is electrically connected to one of the source or the drain of the fourth transistor and the gate of the fifth transistor; a gate of the first transistor and a gate of the fourth transistor are electrically connected to the first wiring; storage device. 　 In claim 4, the third transistor and the sixth transistor are each a p-channel transistor. storage device. 　 In claim 4, The fifth wiring to the eighth wiring are included, the other of the source and the drain of the first transistor is electrically connected to the fifth wiring; the other of the source and the drain of the third transistor is electrically connected to the sixth wiring; the other of the source and the drain of the fourth transistor is electrically connected to the seventh wiring; the other of the source and the drain of the sixth transistor is electrically connected to the eighth wiring; storage device. 　 In claim 4, a ninth wiring and a tenth wiring, a gate of the seventh transistor, a gate of the eighth transistor, a gate of the tenth transistor, and a gate of the twelfth transistor are electrically connected to the ninth wiring; a gate of the ninth transistor and a gate of the eleventh transistor are electrically connected to the tenth wiring; storage device. 　 In claim 6, each of the seventh to twelfth transistors includes a semiconductor layer having a channel formation region; the semiconductor layer includes an oxide semiconductor; storage device. 　 In claim 8, the seventh transistor is an n-channel transistor, the high-level potential that turns on the seventh transistor is a potential higher than the sum of a power supply potential and a threshold voltage of the seventh transistor; the power supply potential is a potential applied to the sixth wiring; storage device. 　 In claim 8, the ninth transistor is an n-channel transistor, the high-level potential that turns on the ninth transistor is a potential higher than the sum of a power supply potential and a threshold voltage of the ninth transistor; the power supply potential is a potential applied to the sixth wiring; storage device. 　 In claim 6, the first memory cell and the second memory cell are memory cells arranged adjacent to each other; storage device. 　 In claim 6, a third memory cell; the third memory cell is disposed between the first memory cell and the second memory cell; storage device. 　 In claim 4, the first memory cell has a first capacitor; the second memory cell has a second capacitor; a first electrode of the first capacitor is electrically connected to one of the source or the drain of the first transistor, the gate of the second transistor, and one of the source or the drain of the seventh transistor; a first electrode of the second capacitor is electrically connected to one of the source and the drain of the fourth transistor, the gate of the fifth transistor, and the other of the source and the drain of the eighth transistor; storage device. 　 a first memory cell, a second memory cell, a switch circuit, and first to fourth wirings; the first memory cell includes a first transistor, a second transistor, and a third transistor; the second memory cell includes a fourth transistor, a fifth transistor, and a sixth transistor; the switch circuit includes a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor; one of the source and the drain of the first transistor is electrically connected to the gate of the second transistor; one of the source and the drain of the second transistor is electrically connected to one of the source and the drain of the third transistor; one of the source and the drain of the fourth transistor is electrically connected to the gate of the fifth transistor; one of the source and the drain of the fifth transistor is electrically connected to one of the source and the drain of the sixth transistor; one of the source and the drain of the seventh transistor is electrically connected to the gate of the third transistor; the other of the source or the drain of the seventh transistor is electrically connected to one of the source or the drain of the fifth transistor and one of the source or the drain of the sixth transistor; one of the source or the drain of the eighth transistor is electrically connected to one of the source or the drain of the second transistor and one of the source or the drain of the third transistor; the other of the source and the drain of the eighth transistor is electrically connected to the gate of the sixth transistor; one of the source and the drain of the ninth transistor is electrically connected to one of the source and the drain of the tenth transistor, the gate of the third transistor, and the second wiring; the other of the source and the drain of the ninth transistor is electrically connected to the third wiring; the other of the source or the drain of the tenth transistor is electrically connected to the one of the source or the drain of the first transistor and the gate of the second transistor; one of the source and the drain of the eleventh transistor is electrically connected to one of the source and the drain of the twelfth transistor, the gate of the sixth transistor, and the third wiring; the other of the source and the drain of the eleventh transistor is electrically connected to the fourth wiring; the other of the source or the drain of the twelfth transistor is electrically connected to one of the source or the drain of the fourth transistor and the gate of the fifth transistor; a gate of the first transistor and a gate of the fourth transistor are electrically connected to the first wiring; storage device. 　 In claim 14, the third transistor and the sixth transistor are each a p-channel transistor. storage device. 　 In claim 14, The fifth wiring to the eighth wiring are included, the other of the source and the drain of the first transistor is electrically connected to the fifth wiring; the other of the source and the drain of the third transistor is electrically connected to the sixth wiring; the other of the source and the drain of the fourth transistor is electrically connected to the seventh wiring; the other of the source and the drain of the sixth transistor is electrically connected to the eighth wiring; storage device. 　 In claim 14, a ninth wiring and a tenth wiring, a gate of the seventh transistor, a gate of the eighth transistor, a gate of the tenth transistor, and a gate of the twelfth transistor are electrically connected to the ninth wiring; a gate of the ninth transistor and a gate of the eleventh transistor are electrically connected to the tenth wiring; storage device. 　 In claim 16, each of the seventh to twelfth transistors includes a semiconductor layer having a channel formation region; the semiconductor layer includes an oxide semiconductor; storage device. 　 In claim 18, the seventh transistor is an n-channel transistor, the high-level potential that turns on the seventh transistor is a potential higher than the sum of a power supply potential and a threshold voltage of the seventh transistor, the power supply potential is a potential applied to the sixth wiring; storage device. 　 In claim 18, the ninth transistor is an n-channel transistor, the high-level potential that turns on the ninth transistor is a potential higher than the sum of a power supply potential and a threshold voltage of the ninth transistor, the power supply potential is a potential applied to the sixth wiring; storage device. 　 In claim 16, the first memory cell and the second memory cell are memory cells arranged adjacent to each other; storage device. 　 In claim 16, a third memory cell; the third memory cell is disposed between the first memory cell and the second memory cell; storage device. 　 In claim 14, the first memory cell has a first capacitor; the second memory cell has a second capacitor; a first electrode of the first capacitor is electrically connected to one of the source or the drain of the first transistor, the gate of the second transistor, and one of the source or the drain of the seventh transistor; a first electrode of the second capacitor is electrically connected to one of the source and the drain of the fourth transistor, the gate of the fifth transistor, and the other of the source and the drain of the eighth transistor; storage device.

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