Substrate processing method and substrate processing system

Abstract

This substrate processing method includes: forming a combined substrate by bonding a second substrate and a first substrate including a device having a first pattern; measuring wrinkles of the combined substrate; performing a wrinkle reduction process on the combined substrate; and forming a first resist film having a second pattern by performing photolithography on the combined substrate on which the wrinkle reduction process has been performed. The wrinkle reduction process includes: determining first stress causing the wrinkles in the combined substrate; determining second stress that relaxes the first stress; and forming a wrinkle correction film that applies the second stress on one surface of the combined substrate.

Description

Substrate processing method and substrate processing system

[0001] The present disclosure relates to a substrate processing method and a substrate processing system.

[0002] Patent document 1 discloses a substrate processing apparatus that applies a coating liquid to the surface of a substrate and develops an exposed coating film on the surface of the substrate, and that, before the exposure process, forms a friction-reducing film on the back surface of the substrate to reduce friction between the back surface of the substrate and a holding surface that holds the back surface of the substrate during the exposure process.

[0003] Patent Document 2 discloses the formation of a wrinkle correction film that reduces wrinkles (OPD) caused by stress applied to a wafer.

[0004] Japanese Patent Application Publication No. 2019-121683 U.S. Patent Application Publication No. 2024 / 0105641

[0005] The technique according to the present disclosure performs exposure processing at an appropriate position in a photolithography process.

[0006] One aspect of the present disclosure is a substrate processing method, comprising: bonding a first substrate including a device having a first pattern and a second substrate to form a laminated substrate; measuring wrinkles in the laminated substrate; performing a wrinkle reduction process on the laminated substrate; and performing photolithography on the laminated substrate that has been subjected to the wrinkle reduction process to form a first resist film having a second pattern, wherein the wrinkle reduction process includes determining a first stress that is causing the wrinkles in the laminated substrate; determining a second stress that relieves the first stress; and forming a wrinkle correction film that applies the second stress on one side of the laminated substrate.

[0007] According to the present disclosure, exposure processing can be performed at an appropriate position in a photolithography process.

[0008] FIG. 10 is a flowchart showing an outline of main steps of a manufacturing method according to the first embodiment. FIG. 11 is an explanatory diagram showing an outline of main steps of a wrinkle reduction treatment according to the first embodiment. FIG. 12 is an explanatory diagram showing an outline of main steps of a wrinkle reduction treatment according to the first embodiment. FIG. 13 is a flowchart showing main steps of a manufacturing method according to the second embodiment. FIG. 14 is an explanatory diagram showing main steps of a wrinkle reduction treatment according to the second embodiment. FIG. 15 is an explanatory diagram showing main steps of a wrinkle reduction treatment according to the third embodiment. FIG. 16 is an explanatory diagram showing main steps of a wrinkle reduction treatment according to the third embodiment. FIG. 17 is an explanatory diagram showing main steps of a wrinkle reduction treatment according to a modified example of the third embodiment. FIG. 18 is an explanatory diagram showing main steps of a wrinkle reduction treatment according to the fourth embodiment. FIG. 19 is a flowchart showing main steps of a manufacturing method according to the fifth embodiment. FIG. 19 is an explanatory diagram showing main steps of a wrinkle reduction treatment according to the fifth embodiment. FIG. 19 is an explanatory diagram showing main steps of a wrinkle reduction treatment according to the sixth embodiment. FIG. 19 is a flowchart showing main steps of a manufacturing method according to the seventh embodiment. FIG. 19 is an explanatory diagram showing main steps of a manufacturing method according to the seventh embodiment. FIG. 19 is a plan view showing an outline of the configuration of a bonding system according to the eighth embodiment.

[0009] First Embodiment The configuration of a semiconductor device manufacturing method according to a first embodiment will be described below with reference to the drawings. In this specification, elements having substantially the same functional configuration will be assigned the same reference numerals to avoid redundant description. Fig. 1 is a flowchart outlining the main steps of the manufacturing method according to this embodiment. Fig. 2 is an explanatory diagram outlining the main steps of the manufacturing method according to this embodiment.

[0010] In the manufacturing method according to this embodiment, first, a first wafer W is prepared as a first substrate (Step 101 in FIGS. 1 and 2 ), and a second wafer S is prepared as a second substrate (Step 102 in FIGS. 1 and 2 ). The preparation of the first wafer W and the preparation of the second wafer S may be performed in parallel. Hereinafter, as shown in FIG. 2 , the surface of the first wafer W that is to be bonded to the second wafer S will be referred to as the front surface Wa, and the surface opposite the front surface Wa will be referred to as the back surface Wb. Similarly, the surface of the second wafer S that is to be bonded to the first wafer W will be referred to as the front surface Sa, and the surface opposite the front surface Sa will be referred to as the back surface Sb.

[0011] The first wafer W prepared in St101 is a semiconductor wafer such as a silicon substrate. In one embodiment, the first wafer W has a substantially circular disk shape. As shown in Fig. 2, a laminated film formed by stacking multiple films is formed on the front surface Wa of the first wafer W. The laminated film includes, in order from the front surface Wa side, a device layer Dw and a bonding surface film Fw.

[0012] The device layer Dw of the first wafer W includes one or more device patterns DP that form at least a portion of a device. The device pattern DP may include desired circuit elements or wiring as a signal network or a power supply network. In one embodiment, the device pattern DP is already formed by a process including photolithography prior to St101. In another embodiment, the device pattern DP is formed by a process including photolithography in St101.

[0013] The second wafer S prepared in St102 is a semiconductor wafer such as a silicon substrate. In one embodiment, the second wafer S has a substantially circular disk shape. As shown in FIG. 2 , a laminated film formed by stacking multiple films is formed on the surface Sa of the second wafer S. The laminated film includes a surface film Fs for bonding.

[0014] The surface film Fw of the first wafer W and the surface film Fs of the second wafer S may be, for example, an oxide film (ThOx film, SiO ２ film, TEOS film), SiC film, SiCN film, adhesive, or the like is used.

[0015] After preparing the first wafer W and the second wafer S as described above, the first wafer W and the second wafer S are bonded together as shown in FIG. 2 to form a laminated wafer T (Step 103 in FIGS. 1 and 2). For example, the bonding of the first wafer W and the second wafer S is performed by modifying the surface films Fw and Fs of the first wafer W and the second wafer S by plasma treatment in a surface modification device (not shown). Furthermore, the surface films are hydrophilized by supplying pure water to the surface films in a surface hydrophilization device (not shown), and then the surface films are bonded together in a bonding device (not shown) by van der Waals forces and hydrogen bonds (intermolecular forces).

[0016] Furthermore, in St103, a measurement is made of wrinkles (distortion) that may occur in the overlapped wafer T. The measurement of wrinkles can be performed, for example, as follows.

[0017] First, before bonding the first wafer W and the second wafer S, a first profile, which is the height distribution (height profile) of the first wafer W, is measured and obtained. The height distribution of the first wafer W can be measured by scanningly measuring the distance between a specified position on a measurement device (not shown) and each portion of the first wafer W to obtain the height over the entire surface of the first wafer W. In one embodiment, the first profile is measured by measuring the back surface Wb side or the front surface Wa side of the first wafer W. In one embodiment, the first profile is measured by measuring both the back surface Wb side and the front surface Wa side of the first wafer W. In one embodiment, the height profile of the second wafer S is measured in the same manner as the measurement of the first profile of the first wafer W.

[0018] Next, after bonding the first wafer W and the second wafer S, a second profile, which is a height distribution of the overlapped wafer T, is measured and acquired. In one embodiment, the measurement of the second profile is performed by measuring the back surface Wb side of the first wafer W in the overlapped wafer T. In one embodiment, the measurement of the second profile is performed by measuring both the back surface Wb side of the first wafer W and the back surface Sb side of the second wafer S.

[0019] Next, a height distribution (difference profile) of the difference between the first profile and the second profile is calculated and obtained. The difference profile can be determined as wrinkles in the laminated wafer T. In one embodiment, measurement of the first profile before lamination may be omitted, and the second profile may be determined as wrinkles in the laminated wafer T.

[0020] The measurement of the first profile may be performed in advance before the start of the manufacturing method according to this embodiment and may be stored in a desired storage medium (not shown). In this case, in St103, the height profile measured in advance may be acquired by reading it from the storage medium. This also applies to other embodiments that require measurement of the height profile.

[0021] Next, a wrinkle reduction process is performed on the overlapped wafer T (St104 in FIGS. 1 and 2). Although details of St104 will be described later, by the wrinkle reduction process, a wrinkle correction film DC is formed as a wrinkle reduction film on the back surface Sb side of the second wafer S of the overlapped wafer T. The wrinkle correction film DC at least partially relieves wrinkles in the overlapped wafer T.

[0022] Next, the back surface Wb of the first wafer W in the overlapped wafer T is thinned (St105 in FIGS. 1 and 2 ). In one embodiment, thinning the back surface Wb of the first wafer W includes grinding the back surface Wb with a grinder and chemical mechanical polishing (CMP). In St105, the back surface Wb of the first wafer W is thinned to a desired thickness.

[0023] Next, a first resist film RL1 is formed on the rear surface Wb (St106 in FIGS. 1 and 2).

[0024] Next, after being transported to an exposure tool, alignment is performed (St107 in FIGS. 1 and 2). In one embodiment, in St107, the position of the device pattern DP on the device layer Dw is measured using an IR measurement device (not shown) provided in the exposure tool. In some cases, due to wrinkles in the overlapped wafer T, the device pattern DP may be shifted from the intended exposure position on a desired mask (not shown). In this case, the intended exposure position may be corrected to cancel out the shift.

[0025] Next, using a desired mask (not shown), the first resist film RL1 is exposed to light so that the first resist film RL1 has a predetermined resist pattern RP (St108 in FIGS. 1 and 2).

[0026] Next, the first resist film RL1 is subjected to a development process (Step 109 in FIGS. 1 and 2). As a result, the first resist film RL1 having the resist pattern RP is formed on the rear surface Wb of the first wafer W.

[0027] Next, the overlay OL between the device pattern DP and the resist pattern RP is measured (St110 in FIGS. 1 and 2 ). The measurement of the overlay OL according to this embodiment includes measuring the amount of misalignment between the device pattern DP and the resist pattern RP. In one embodiment, the amount of misalignment may be the difference between the planned position of the device pattern DP relative to the resist pattern RP and the actual position of the device pattern DP. In one embodiment, the measurement result of the overlay OL in St110 is recorded in, for example, a memory unit of the control unit 70. In this case, the recorded measurement result can be used to minimize errors in stress correction when processing other first wafers W in the next lot or later.

[0028] In one embodiment, the resist pattern RP includes a pattern for forming a backside power delivery network (BSPDN) for the device layer Dw. In this case, the tolerance for the misalignment amount in the overlay OL is not limited to, but is currently, for example, several nanometers. This tolerance is expected to become even stricter with future technological advances. This misalignment amount may be affected by wrinkles in the overlapped wafer T. Therefore, it may be difficult to keep the misalignment amount within the above range simply by adjusting the planned exposure position in St107. The manufacturing method according to this embodiment also includes forming a wrinkle correction film DC in St104 to reduce wrinkles in the overlapped wafer T. This wrinkle reduction process makes it possible to keep the misalignment amount within the above range.

[0029] An example of the configuration of the wrinkle reduction process in St104 according to this embodiment will be described below. Fig. 3 is a flowchart showing an outline of the main steps of the wrinkle reduction process. Fig. 4 is an explanatory diagram showing an outline of the main steps of the wrinkle reduction process.

[0030] First, a silicon nitride film (SiN) is formed as a stress-applying film on the rear surface Sb of the second wafer S of the overlapped wafer T (St151 in FIGS. 3 and 4). The silicon nitride film applies tensile stress or compressive stress (hereinafter simply referred to as "stress") to the overlapped wafer T. Therefore, the silicon nitride film deforms the overlapped wafer T due to this stress. The film thickness or composition ratio (bonding state) of the silicon nitride film can be set so that the stress applied to the overlapped wafer T becomes a desired one. The composition of the silicon nitride film can be adjusted, for example, by adjusting the bonding state in the film to a desired one. As an example, the composition can be adjusted by changing the composition ratio of Si—H bonds, SiN bonds, Si—O bonds, or the like. Note that the film type of the stress-applying film used to form the wrinkle correction film DC is not limited to a silicon nitride film, and a film type that applies stress to the overlapped wafer T can be suitably used. The film type that applies stress to the overlapped wafer T is, for example, SiO ２ Examples of such films include organic films such as photoresists and resists.

[0031] Next, a second resist film RL2 is formed on the silicon nitride film (Step 152 in FIGS. 3 and 4).

[0032] Next, the second resist film RL2 is subjected to maskless exposure (Step 153 in FIGS. 3 and 4). Maskless exposure allows exposure only at a desired position by irradiating the desired position with light or the like. Maskless exposure can be performed by a known process using a known maskless exposure machine such as a DLP (Digital Light Processing) system.

[0033] The exposure pattern for maskless exposure can be determined as follows. First, a first stress distribution is calculated based on the differential profile acquired in St103. The first stress distribution is a distribution of stress estimated to be causing wrinkles in the overlapped wafer T. As an example, the first stress distribution is a stress distribution such that, assuming that a certain overlapped wafer T has a first profile, when stress is applied to the overlapped wafer T, the overlapped wafer T will have a second profile.

[0034] After calculating the first stress distribution, a second stress distribution is calculated, which includes stresses that alleviate, cancel, or reverse at least a portion of the stresses in the first stress distribution. For example, if the first stress distribution includes stresses that deform the overlapped wafer T in a convex direction, the second stress distribution is calculated to include stresses that deform the overlapped wafer T in a concave direction to cancel the stresses.

[0035] After calculating the second stress distribution, an exposure pattern is determined. The exposure pattern is determined so that the wrinkle correction film DC after ion implantation (described later) applies stress of the second stress distribution to the overlapped wafer T. As will be described in detail later, the silicon nitride film into which ions are implanted (dose) has reduced stress. Therefore, the exposure pattern is determined so as to include exposure to a portion corresponding to at least a portion of the silicon nitride film whose stress should be reduced by ion implantation.

[0036] Next, the second resist film RL2 is subjected to a development process (Step 154 ​​in FIGS. 3 and 4).

[0037] Next, ion implantation is performed on the entire surface of the silicon nitride film through the second resist film RL2 (St155 in FIGS. 3 and 4). As a result, ions are not implanted into the portions covered with the second resist film RL2, and ions are implanted into the portions not covered with the second resist film RL2. The silicon nitride film into which ions are implanted loses its crystallinity in those portions, and the stress applied to the overlapped wafer T is reduced. As a result, a wrinkle correction film DC is formed in which ions are partially implanted and the stress is reduced in those portions. The wrinkle correction film DC applies stress of the second stress distribution to the overlapped wafer T.

[0038] The elemental species of ions used in the ion implantation may be, but is not limited to, argon (Ar), phosphorus (P), silicon (Si), carbon (C), boron (B), nitrogen (N), krypton (Kr), indium (In), or boron difluoride (BF ２ ) etc.

[0039] Next, the second resist film RL2 is removed (Step 156 in FIGS. 3 and 4).

[0040] By the above steps including St151 to St156, a wrinkle correction film DC can be formed as a wrinkle reduction film on the back surface Sb side of the second wafer S of the overlapped wafer T. Furthermore, the wrinkle correction film DC formed in this manner applies stress of the second stress distribution to the overlapped wafer T, and alleviates, cancels, or reverses at least a part of the stress in the first stress distribution. Therefore, the overlapped wafer T on which the wrinkle correction film DC is formed approaches the first profile. That is, wrinkles in the overlapped wafer T are reduced.

[0041] In one embodiment, after the wrinkle correction film DC is formed, another wrinkle correction film (not shown) is formed on the wrinkle correction film DC. In another embodiment, before the wrinkle correction film DC is formed, another wrinkle correction film (not shown) is formed below the wrinkle correction film DC. The other wrinkle correction film may be configured to correct wrinkles on the order of, for example, several to 100 times larger than the wrinkles in the laminated wafer T reduced by the wrinkle correction film DC according to this embodiment. Therefore, the wrinkle reduction film according to the present disclosure may include multiple stacked wrinkle correction films, each of which applies stress to the laminated wafer T to correct wrinkles of different orders of magnitude. The other wrinkle correction film may be the same as the wrinkle correction film DC according to this embodiment, or may be any known film that applies stress to the laminated wafer T.

[0042] In one embodiment, after the wrinkle correction film DC is formed, a protective film (not shown) is formed on the wrinkle correction film DC. The wrinkle correction film DC includes a silicon nitride film modified by ion implantation. If, for example, wet cleaning or the like is performed after the wrinkle correction film DC is formed, the modified silicon nitride film may be removed, resulting in a step with the unmodified portion. The protective film protects the modified silicon nitride film from damage and also prevents the removed silicon nitride film from contaminating device components such as the mounting table SG. From this perspective, the protective film is formed to cover all or part of the wrinkle correction film DC.

[0043] Incidentally, when adjusting the stress of a wrinkle correction film DC partially, it is possible to remove the film from that portion. However, when adjusting the film stress by removing the film, a step may occur between the removed portion and the remaining portion. In this case, in the process after the film formation, when the substrate is placed on the mounting table SG so as to contact the film, the step may affect proper placement. For example, in a mounting table SG with a pin chuck, a pin may get stuck in the step. In contrast, in the wrinkle correction film DC of this embodiment, there is no height difference between the portion of the silicon nitride film modified by ion implantation and the other portion. Therefore, the process after the wrinkle correction film DC formation does not affect proper placement on the mounting table SG.

[0044] Second Embodiment A configuration of a semiconductor device manufacturing method according to a second embodiment will be described below with reference to the drawings. Fig. 5 is a flowchart showing the main steps of the manufacturing method according to this embodiment. Fig. 6 is an explanatory diagram showing the main steps of a wrinkle reduction process according to this embodiment.

[0045] In the manufacturing method according to this embodiment, first, a first wafer W is prepared as a first substrate (Step 201 in FIGS. 5 and 6). The configuration of the first wafer W is the same as that of the first embodiment, and Step 201 is the same as Step 101 in the first embodiment.

[0046] Next, a wrinkle reduction process is performed on the back surface Wb of the first wafer W (St202 in FIGS. 5 and 6 ). In the wrinkle reduction process according to this embodiment, a wrinkle correction film DC is formed as a wrinkle reduction film on the back surface Wb of the first wafer W. The wrinkle correction film DC at least partially reduces the wrinkles on the first wafer W.

[0047] In St202, first, the height profile of the first wafer W is measured. The height profile measurement may be performed, for example, on the back surface Wb side of the first wafer W. Next, a wrinkle correction film DC is formed on the back surface Wb of the first wafer W. The formation of the wrinkle correction film DC is similar to St151 to St156 according to the first embodiment.

[0048] In this embodiment, the first stress distribution calculated in St153 according to the first embodiment is calculated based on the height profile of the first wafer W measured as described above. That is, the first stress distribution according to this embodiment is a distribution of stress estimated to be causing wrinkles in the first wafer W. As an example, the first stress distribution is a stress distribution that, assuming that a certain first wafer W has a flat shape, causes the first wafer W to have the height profile described above when stress is applied to the first wafer W.

[0049] By St202, a wrinkle correction film DC can be formed as a wrinkle reduction film on the rear surface Wb of the first wafer W. The wrinkle correction film DC formed in this manner applies stress of the second stress distribution to the first wafer W, and relieves, cancels, or reverses at least a part of the stress in the first stress distribution. Therefore, the first wafer W on which the wrinkle correction film DC is formed approaches a flat shape.

[0050] Here, conventionally, when wrinkles occur in the first wafer W, stress caused by the wrinkles may also cause wrinkles in the overlapped wafer T formed by bonding the first wafer W and the second wafer S. In contrast, the manufacturing method according to the present embodiment can at least suppress the occurrence of wrinkles in the overlapped wafer T. In other words, wrinkles in the overlapped wafer T are reduced.

[0051] In addition to the above, by performing St102 to St110 in the same manner as in the first embodiment, a first resist film RL1 similar to that in the first embodiment can be formed on the back surface Wb of the first wafer W in the overlapped wafer T.

[0052] Third Embodiment The configuration of a semiconductor device manufacturing method according to a third embodiment will be described below with reference to the drawings. Since the main steps of the manufacturing method according to this embodiment are the same as those of the second embodiment except for the wrinkle reduction treatment, reference will be made to FIG. 5. FIG. 7 is an explanatory diagram showing the main steps of the manufacturing method according to this embodiment. FIG. 8 is a flowchart showing the main steps of the wrinkle reduction treatment according to this embodiment.

[0053] In the manufacturing method according to this embodiment, first, a first wafer W is prepared as a first substrate (Step 301 in FIGS. 5 and 7). The configuration of the first wafer W is the same as that of the first embodiment, and Step 301 is the same as Step 101 in the first embodiment.

[0054] Next, wrinkle reduction processing is performed on the front surface Wa of the first wafer W (St302 in FIGS. 5 and 7). The wrinkle reduction processing in St302 according to this embodiment includes the steps shown in FIG.

[0055] First, a height profile of the first wafer W is measured and acquired (Step 351 in FIG. 8). The height profile may be measured on the front surface Wa side of the first wafer W, for example.

[0056] Next, a target processing amount profile is determined from the height profile (Step 352 in FIG. 8 ). The target processing amount profile may be the difference between the height profile of a predetermined target shape of the front surface Wa of the first wafer W in the planarization process described below and the height profile of the first wafer W acquired in Step 351. For convenience, this embodiment will be described assuming that the target shape is a flat shape. However, the target shape may be a flat shape or a desired shape other than a flat shape.

[0057] Next, planarization of the surface Wa of the first wafer W is performed based on the target processing amount profile (Step 353 in FIG. 8 ). The planarization is not particularly limited as long as it can process the first wafer W based on the target processing amount profile. In one embodiment, the planarization includes processing the surface Wa of the first wafer W by partial plasma etching (PPE). In one embodiment, the planarization includes laser processing of the surface Wa of the first wafer W. In one embodiment, the planarization includes processing the surface Wa of the first wafer W by gas cluster beam (GCB).

[0058] The above steps including St351 to St353 enable the first wafer W to have a shape closer to a flat shape. According to the manufacturing method of this embodiment, as in the second embodiment, by making the first wafer W have a shape closer to a flat shape, it is possible to at least suppress the occurrence of wrinkles in the overlapped wafer T when the first wafer W is bonded to the second wafer S, which also has a flat shape. In other words, wrinkles in the overlapped wafer T are reduced.

[0059] The target shape referred to when determining the target processing amount profile in St352 is a shape that allows for appropriate bonding to the second wafer S. That is, if the second wafer S has a flat shape, the target shape of the first wafer W is also set to a flat shape. If the second wafer S has a shape that is not flat, the target shape of the first wafer W is also set to a shape that allows for appropriate bonding to that shape.

[0060] In addition to the above, by performing St102 to St110 in the same manner as in the first embodiment, a first resist film RL1 similar to that in the first embodiment can be formed on the back surface Wb of the first wafer W in the overlapped wafer T.

[0061] The structure of a method for manufacturing a semiconductor device according to a modification of the third embodiment will be described below with reference to the drawings. Figure 9 is an explanatory diagram showing the main steps of the manufacturing method according to this modification.

[0062] In the wrinkle reduction process (St302 in FIG. 5 ) according to this modification, the planarization process (St353 in FIG. 8 ) includes processing the front surface Wa of the first wafer W by PPE. In this modification, prior to the PPE in the planarization process, a sacrificial film SL is formed on the front surface Wa of the first wafer W, as shown in FIG. 9 . The sacrificial film SL is not particularly limited as long as it is a material that is reactive with the etchant used in the PPE and can be removed by the PPE. In one embodiment, an etchant containing fluorine radicals is used in the PPE. In this case, as an example, the sacrificial film SL made of silicon (Si) can be used.

[0063] After the sacrificial film SL is formed, the height profile of the first wafer W is measured (St351 in FIG. 8), the target processing amount profile is determined (St352 in FIG. 8), and the front surface Wa of the first wafer W is planarized (St353 in FIG. 8). As a result, the front surface Wa of the first wafer W including the sacrificial film SL approaches a flat shape, as shown in FIG.

[0064] The wrinkle reduction process according to this modification is preferably used when the material constituting the front surface Wa of the first wafer W does not have sufficient reactivity with the etchant used in the PPE. Even in such a case, the sacrificial film SL according to this modification can be used to suitably process the front surface Wa of the first wafer W by the PPE. This allows the first wafer W to have an approximately flat shape.

[0065] Fourth Embodiment The configuration of a semiconductor device manufacturing method according to a fourth embodiment will be described below with reference to the drawings. Since the main steps of the manufacturing method according to this embodiment are the same as those of the second embodiment except for the wrinkle reduction treatment, reference will be made to Fig. 5. Fig. 10 is an explanatory diagram showing the main steps of the wrinkle reduction treatment according to this embodiment.

[0066] In the manufacturing method according to this embodiment, first, a first wafer W is prepared as a first substrate (Step 401 in FIGS. 5 and 10). The configuration of the first wafer W is the same as that of the first embodiment, and Step 401 is the same as Step 101 in the first embodiment.

[0067] Next, wrinkle reduction processing is performed on the rear surface Wb of the first wafer W (Step 402 in FIGS. 5 and 10). In the wrinkle reduction processing according to this embodiment, a friction reduction film LB is formed on the rear surface Wb of the first wafer W as a wrinkle reduction film.

[0068] The method for forming the friction-reducing film LB is not particularly limited. In one embodiment, the friction-reducing film LB is formed by depositing a gas of a friction-reducing material on the back surface Wb of the first wafer W. In another embodiment, the friction-reducing film LB is formed by applying a liquid of the friction-reducing material to the back surface Wb of the first wafer W.

[0069] In the conventional bonding process, the first wafer W may be attracted and held on the mounting table SG in a state where stress is generated due to friction between the back surface Wb of the first wafer W and the mounting surface SGa of the mounting table SG. In this case, the stress may cause wrinkles in the first wafer W, and wrinkles may also occur in the overlapped wafer T formed by bonding the first wafer W and the second wafer S.

[0070] In contrast, in this embodiment, in St103, when the first wafer W is placed on the mounting table SG provided in the bonding apparatus (not shown), the friction-reducing film LB formed on the back surface Wb of the first wafer W comes into contact with the mounting surface SGa of the mounting table SG. This reduces friction between the back surface Wb and the mounting surface SGa of the first wafer W. As a result, it is possible to at least suppress the occurrence of wrinkles in the first wafer W, and at least suppress the occurrence of wrinkles in the overlapped wafer T. In other words, wrinkles in the overlapped wafer T are reduced.

[0071] The type of the friction-reducing film LB is not particularly limited as long as it reduces friction between the back surface Wb and the mounting surface SGa of the first wafer W, but for example, a fluororesin film is used.

[0072] Fifth Embodiment A configuration of a semiconductor device manufacturing method according to a fifth embodiment will be described below with reference to the drawings. Fig. 11 is a flowchart showing the main steps of the manufacturing method according to this embodiment. Fig. 12 is an explanatory diagram showing the main steps of a wrinkle reduction process according to this embodiment.

[0073] In the manufacturing method of this embodiment, similar to the first embodiment, the first wafer W and the second wafer S are prepared (Steps 101 and 102 in FIG. 11), bonded (Step 103 in FIG. 11 and FIG. 12), and thinned (Step 104 in FIG. 11 and FIG. 12).

[0074] Next, a wrinkle reduction process is performed on the back surface Wb of the first wafer W (St501 in FIGS. 11 and 12 ). In the wrinkle reduction process according to this embodiment, a wrinkle correction film DC is formed as a wrinkle reduction film on the back surface Wb of the first wafer W. The wrinkle correction film DC at least partially reduces the wrinkles on the first wafer W.

[0075] In St501, first, a height profile of the overlapped wafer T is measured. The height profile measurement may be performed, for example, on the back surface Wb side of the first wafer W in the overlapped wafer T. Next, a wrinkle correction film DC is formed on the back surface Sb of the second wafer S in the overlapped wafer T. The formation of the wrinkle correction film DC is similar to St151 to St156 in the first embodiment.

[0076] In this embodiment, the first stress distribution calculated in St153 according to the first embodiment is calculated based on the height profile of the overlapped wafer T measured as described above. That is, the first stress distribution according to this embodiment is a distribution of stress estimated to be causing wrinkles in the overlapped wafer T. As an example, the first stress distribution is a stress distribution that, assuming that a certain overlapped wafer T has a flat shape, causes the overlapped wafer T to have the height profile described above when stress is applied to the overlapped wafer T.

[0077] By St501, a wrinkle correction film DC can be formed as a wrinkle reduction film on the back surface Sb side of the second wafer S of the overlapped wafer T. The wrinkle correction film DC thus formed applies stress of the second stress distribution to the overlapped wafer T, and relieves, cancels, or reverses at least a part of the stress in the first stress distribution. Therefore, the overlapped wafer T on which the wrinkle correction film DC is formed approaches a flat shape. That is, wrinkles in the overlapped wafer T are reduced.

[0078] After St501, by performing St106 to St110 in the same manner as in the first embodiment, a first resist film RL1 similar to that in the first embodiment can be formed on the back surface Wb of the first wafer W in the overlapped wafer T.

[0079] Sixth Embodiment The configuration of a semiconductor device manufacturing method according to a sixth embodiment will be described below with reference to the drawings. Since the main steps of the manufacturing method according to this embodiment are the same as those of the fifth embodiment except for the wrinkle reduction process, reference will be made to Fig. 11. Fig. 13 is an explanatory diagram showing the main steps of the manufacturing method according to this embodiment.

[0080] In the manufacturing method of this embodiment, similarly to the first embodiment, the first wafer W and the second wafer S are prepared (Steps 101 and 102 in FIG. 11), bonded (Step 103 in FIG. 11 and FIG. 13), and thinned (Step 104 in FIG. 11 and FIG. 13).

[0081] Next, wrinkle reduction processing is performed on the back surface Wb of the first wafer W (St601 in FIGS. 11 and 13). The wrinkle reduction processing of St601 according to this embodiment is similar to St302 according to the third embodiment, and the overlapped wafer T is flattened by steps including St351 to St353. This allows the overlapped wafer T to approach a flat shape. That is, wrinkles in the overlapped wafer T are reduced.

[0082] In one embodiment, similar to the wrinkle reduction process of St302 according to the modified example of the third embodiment, a sacrificial film SL is formed on the rear surface Wb of the first wafer W to perform planarization processing. This allows for favorable processing even when the material constituting the rear surface Wb of the first wafer W does not have sufficient reactivity with the etchant used in the PPE.

[0083] Seventh Embodiment A configuration of a semiconductor device manufacturing method according to a seventh embodiment will be described below with reference to the drawings. Fig. 14 is a flowchart showing the main steps of the manufacturing method according to this embodiment. Fig. 15 is an explanatory diagram showing the main steps of a wrinkle reduction process according to this embodiment.

[0084] In the manufacturing method according to this embodiment, first, a first wafer W is prepared (Step 701 in FIGS. 14 and 15 ). Then, a second wafer S is prepared (Step 702 in FIGS. 14 and 15 ). The configuration of the first wafer W is similar to that of the first wafer W according to the first embodiment, and Step 701 is similar to Step 101 in the first embodiment. The configuration of the second wafer S is similar to that of the second wafer S according to the first embodiment, and Step 702 is similar to Step 102 in the first embodiment.

[0085] As shown in FIG. 15 , the device layer Dw of the first wafer W prepared in St701 includes one or more first device patterns DP1 that form at least a portion of a device. In this embodiment, the first device pattern DP1 forms at least a portion of a memory cell array of a DRAM (Dynamic Random Access Memory). In the example shown in FIG. 15 , the first device pattern DP1 includes a conductive layer that forms capacitors, transistors, and word lines in the memory cell array. In one embodiment, the first device pattern DP1 is already formed by a process including photolithography prior to St701. In another embodiment, the first device pattern DP1 is formed by a process including photolithography in St701.

[0086] After preparing the first wafer W and the second wafer S as described above, the first wafer W and the second wafer S are bonded together to form a first overlapping wafer T1 as shown in FIG. 15 (Step 703 in FIGS. 14 and 15 ). The bonding of the first wafer W and the second wafer S in Step 703 is similar to Step 103 in the first embodiment, and the formed first overlapping wafer T1 corresponds to the overlapping wafer T in the first embodiment.

[0087] In St703, wrinkles that may occur in the first overlapped wafer T1 are measured in the same manner as in St103 of the first embodiment, thereby acquiring a first profile, a second profile, and a differential profile for the first overlapped wafer T1.

[0088] Next, wrinkle reduction processing is performed on the first overlapped wafer T1 (Step 704 in FIGS. 14 and 15 ). The wrinkle reduction processing in Step 704 is similar to Step 104 in the first embodiment, and by performing steps including Steps 151 to 156, a wrinkle correction film DC is formed as a wrinkle reduction film on the back surface Wb of the first wafer W. The wrinkle correction film DC reduces wrinkles in the first overlapped wafer T1.

[0089] Next, the back surface Wb of the first wafer W in the first overlapping wafer T1 is thinned (Step 705 in FIGS. 14 and 15). The thinning of the back surface Wb of the first wafer W in Step 705 is similar to Step 105 in the first embodiment.

[0090] Next, a second device pattern DP2 is formed on the back surface Wb of the thinned first wafer W (Step 706 in FIGS. 14 and 15 ). In Step 706, a resist film (not shown) similar to the first resist film RL1 is formed by steps similar to Steps 106 to 109 in the first embodiment. Furthermore, a processing step using this resist film forms the second device pattern DP2. In the example shown in FIG. 15 , the second device pattern DP2 includes a conductive layer that forms a bit line in the memory cell array.

[0091] In one embodiment, an overlay OL between the first device pattern DP1 and the second device pattern DP2 is measured. The measurement of the overlay OL in this embodiment includes measuring the amount of misalignment between the first device pattern DP1 and the second device pattern DP2. The tolerance for this misalignment is not limited to, but is currently, for example, several nanometers, and is expected to become even stricter with future technological advances. The amount of misalignment may be affected by wrinkles in the first overlapped wafer T1. The manufacturing method in this embodiment includes forming a wrinkle correction film DC in St704 to reduce wrinkles in the first overlapped wafer T1. This wrinkle reduction process makes it possible to keep the amount of misalignment within the above-mentioned range.

[0092] In addition, in St706, a surface film Ft1 for bonding is formed on the second device pattern DP2. The surface film Ft1 is the same as the surface film Fw of the first wafer W, for example.

[0093] In the manufacturing method according to this embodiment, a third wafer U is prepared (Step 711 in FIGS. 14 and 15 ). A fourth wafer V is prepared (Step 712 in FIGS. 14 and 15 ). The preparation of the third wafer U and the fourth wafer V may be performed in parallel with the preparation of the first wafer W or the second wafer S. The configuration of the third wafer U is similar to that of the first wafer W according to the first embodiment, and Step 711 is similar to Step 101 in the first embodiment. The configuration of the fourth wafer V is similar to that of the second wafer S according to the first embodiment, and Step 712 is similar to Step 102 in the first embodiment.

[0094] 15 , the device layer Du of the third wafer U prepared in St711 includes one or more third device patterns DP3 that form at least a portion of a device. In this embodiment, the third device pattern DP3 includes at least a portion of a peripheral circuit for controlling the memory cell array. In the example shown in FIG. 15 , the third device pattern DP3 includes a complementary metal-oxide-semiconductor (CMOS) in the peripheral circuit.

[0095] 15, the third wafer U and the fourth wafer V are bonded together to form a second overlapping wafer T2 (Step 713 in FIGS. 1 and 2). The bonding of the third wafer U and the fourth wafer V in Step 713 is similar to Step 103 in the first embodiment, and the formed second overlapping wafer T2 corresponds to the overlapping wafer T in the first embodiment.

[0096] In St713, wrinkles that may occur in the second overlapped wafer T2 are measured in the same manner as in St103 of the first embodiment, thereby acquiring the first profile, the second profile, and the differential profile of the second overlapped wafer T2.

[0097] Next, wrinkle reduction processing is performed on the second overlapping wafer T2 (St714 in FIGS. 14 and 15 ). The wrinkle reduction processing in St714 is similar to St104 in the first embodiment, and by performing steps including St151 to St156, a wrinkle correction film DC is formed as a wrinkle reduction film on the back surface Vb of the fourth wafer V. The wrinkle correction film DC reduces wrinkles in the second overlapping wafer T2.

[0098] Next, the back surface Ub of the third wafer U in the second overlapping wafer T2 is thinned (St714 in FIGS. 14 and 15). The thinning of the back surface Ub of the third wafer U in St714 is similar to St105 in the first embodiment.

[0099] Next, a fourth device pattern DP4 is formed on the back surface Ub of the thinned third wafer U (Step 716 in FIGS. 14 and 15 ). In Step 716, a resist film (not shown) similar to the first resist film RL1 is formed by steps similar to Steps 106 to 109 of the first embodiment. Furthermore, a fourth device pattern DP4 is formed by a processing step using this resist film. In the example shown in FIG. 15 , the fourth device pattern DP4 includes a pattern in which part of the thinned third wafer U is removed and other parts are not removed.

[0100] In one embodiment, the overlay OL between the third device pattern DP3 and the fourth device pattern DP4 is measured. The measurement of the overlay OL in this embodiment includes measuring the amount of misalignment between the third device pattern DP3 and the fourth device pattern DP4. The tolerance for this misalignment is not limited to, but is currently, for example, several nanometers, and is expected to become even stricter with future technological advances. The amount of misalignment may be affected by wrinkles in the second overlapped wafer T2. The manufacturing method in this embodiment includes forming a wrinkle correction film DC in St714 to reduce wrinkles in the second overlapped wafer T2. This wrinkle reduction process makes it possible to keep the amount of misalignment within the above-mentioned range.

[0101] In addition, in St716, a surface film Ft2 for bonding is formed on the fourth device pattern DP4. The surface film Ft2 is the same as the surface film Fw of the first wafer W, for example.

[0102] Next, the first overlapping wafer T1 formed in steps St701 to St706 and the second overlapping wafer T2 formed in steps St711 to St716 are bonded together to form a third overlapping wafer T3 (Step 721 in FIGS. 14 and 15 ). The bonding of the first overlapping wafer T1 and the second overlapping wafer T2 in Step 721 is similar to Step 103 in the first embodiment, and the surface films Ft1 and Ft2 are bonded together. The third overlapping wafer T3 thus formed corresponds to the overlapping wafer T in the first embodiment.

[0103] Next, the back surface Vb of the fourth wafer V in the third overlapping wafer T3 is thinned (Step 722 in FIGS. 14 and 15). The thinning of the back surface Vb of the fourth wafer V in Step 722 is similar to Step 105 in the first embodiment.

[0104] Next, a fifth device pattern DP5 is formed on the back surface Vb of the thinned fourth wafer V (Step 723 in FIGS. 14 and 15 ). In Step 723, a resist film (not shown) similar to the first resist film RL1 is formed by steps similar to Steps 106 to 109 of the first embodiment. Furthermore, the fifth device pattern DP5 is formed by a processing step using this resist film. In the example shown in FIG. 15 , the fifth device pattern DP5 includes a conductive layer serving as a wiring layer electrically connected to the memory cell array and peripheral circuits. In one embodiment, the conductive layer constitutes part of the BSPDN.

[0105] By the steps including St701 to St723 described above, a third overlapped wafer T3 can be obtained in which a memory cell array of a DRAM and peripheral circuits are stacked and a wiring layer is formed.

[0106] In one embodiment, a wrinkle reduction process is performed on the third overlapped wafer T3. In this case, in St721, wrinkles that may occur on the third overlapped wafer T3 are measured in the same manner as in St103 of the first embodiment. As a result, a first profile, a second profile, and a differential profile for the third overlapped wafer T3 are acquired. Thereafter, before St721 is performed, a wrinkle reduction process is performed in the same manner as in St104 of the first embodiment. In one embodiment, in St704, the wrinkle correction film DC already formed on the first overlapped wafer T1 is removed before measuring the wrinkles on the third overlapped wafer T3, and the wrinkles are measured in this state. Thereafter, another wrinkle correction film (not shown) is formed on the second wafer S of the third overlapped wafer T3. In another embodiment, the wrinkle correction film DC already formed on the first overlapped wafer T1 is not removed, and the wrinkles on the third overlapped wafer T3 are measured in this state. Thereafter, another wrinkle correction film (not shown) is formed on the second wafer S of the third overlapped wafer T3. The formation of the other wrinkle correction film can be performed in the same manner as the formation of the wrinkle correction film DC according to this embodiment. This further reduces wrinkles in the third overlapping wafer T3, and makes it possible to further improve the overlay between the first to fourth device patterns DP1 to DP4 and the fifth device pattern DP5.

[0107] The wrinkle reduction process for St704 and St714 according to this embodiment has been described in the case of forming the wrinkle correction film DC similar to that of the first embodiment, but is not limited to this. The wrinkle reduction process may include, for example, the planarization process according to the third embodiment or the formation of the friction reduction film LB according to the fourth embodiment.

[0108] A seventh embodiment of a semiconductor device manufacturing method according to one aspect includes measuring wrinkles in a first laminated substrate formed by bonding a first substrate having a first pattern and a second substrate; performing a wrinkle reduction process on the first laminated substrate; forming a second pattern by performing a process including photolithography on the first laminated substrate that has undergone the wrinkle reduction process; and bonding a second laminated substrate formed by bonding a third substrate having a third pattern and a fourth substrate to the first laminated substrate on which the second pattern has been formed, to form a third laminated substrate.

[0109] Eighth Embodiment The configuration of a bonding system 1 according to an eighth embodiment will be described below with reference to the drawings. Fig. 16 is a plan view showing an outline of the configuration of the bonding system 1 according to this embodiment. In the following, to clarify the positional relationships, the X-axis direction, the Y-axis direction, and the Z-axis direction are defined as being orthogonal to each other, and the positive Z-axis direction is defined as the vertically upward direction.

[0110] The bonding system 1 is configured to be able to bond the first wafer W and the second wafer S to obtain the overlapped wafer T, as described in the manufacturing methods according to the first to seventh embodiments.

[0111] In the following description, it is assumed that the first wafer W is placed on the lower side and the second wafer S is placed on the upper side, but this arrangement is for convenience of explanation and is not limiting.

[0112] As shown in FIG. 16, the bonding system 1 is connected to the outside via a cassette C that can accommodate a plurality of wafers W, S, and a plurality of overlapping wafers T. Ｗ , C Ｓ , C Ｔ The wafer transport system has a configuration in which a loading / unloading station 2 through which wafers W, S and the laminated wafer T are loaded and unloaded is integrally connected to a processing station 3 equipped with various processing devices for performing desired processing on the wafers W, S and the laminated wafer T. In one embodiment, an inspection station is provided adjacent to the processing station 3.

[0113] The carry-in / out station 2 is provided with a cassette mounting table 10. The cassette mounting table 10 is provided with a plurality of, for example, four cassette mounting plates 11. The cassette mounting plates 11 are arranged in a row in the horizontal Y-axis direction (the up-down direction in FIG. 16). These cassette mounting plates 11 are provided with a cassette C Ｗ , C Ｓ , C Ｔ When carrying in or out the cassette C Ｗ , C Ｓ , C ＴIn this way, the loading / unloading station 2 is configured to be able to hold a plurality of first wafers W, a plurality of second wafers S, and a plurality of overlapped wafers T. The number of cassette mounting plates 11 is not limited to that in this embodiment, and can be set arbitrarily. One of the cassettes may also be used to recover abnormal wafers. In other words, it is a cassette that can separate a wafer in which an abnormality has occurred in the bonding between the second wafer S and the first wafer W due to various factors from the other normal overlapped wafers T. In this embodiment, a plurality of cassettes C Ｔ One cassette C Ｔ is used to recover abnormal wafers, and other cassettes C Ｔ is used to accommodate a normal overlapped wafer T.

[0114] The loading / unloading station 2 is provided with a wafer transfer section 20 adjacent to the cassette mounting table 10. The wafer transfer section 20 is provided with a wafer transfer device 22 that is movable on a transfer path 21 extending in the Y-axis direction. The wafer transfer device 22 is also movable in the vertical direction and around the vertical axis (Z-axis) (in the θ direction), and transfers the cassettes C on each cassette mounting plate 11. Ｗ , C Ｓ , C Ｔ and the transition devices 50 and 51 in the third processing block G3 of the processing station 3, which will be described later, can transfer wafers W, S, and overlapping wafer T between them.

[0115] Processing station 3 is provided with multiple processing blocks, e.g., three processing blocks G1, G2, and G3, each equipped with various devices. For example, a first processing block G1 is provided on the front side (negative Y-axis side in FIG. 16 ) of processing station 3, and a second processing block G2 is provided on the rear side (positive Y-axis side in FIG. 16 ) of processing station 3. Furthermore, a third processing block G3 is provided on the loading / unloading station 2 side of processing station 3 (negative X-axis side in FIG. 16 ).

[0116] The first processing block G1 is provided with a surface modification device 30 that modifies, for example, the surfaces Wa and Sa of the wafers W and S. In the surface modification device 30, for example, under a reduced pressure atmosphere, oxygen gas or nitrogen gas serving as a processing gas is excited to be turned into plasma and ionized. The oxygen ions or nitrogen ions are irradiated onto the surfaces Wa and Sa, and the surfaces Wa and Sa are subjected to plasma processing and modified.

[0117] In the second processing block G2, a surface hydrophilization device 40 that hydrophilizes the surfaces Wa, Sa of the wafers W, S using, for example, pure water and cleans the surfaces Wa, Sa, and a bonding device 41 that bonds the wafers W, S are arranged in this order from the loading / unloading station 2 side in the horizontal X-axis direction.

[0118] The bonding apparatus 41 according to this embodiment includes an inspection unit (not shown) configured to measure and acquire the height distribution (height profile) of the wafers W, S or the overlapped wafer T. In one embodiment, the inspection unit is provided outside the bonding apparatus 41, for example, in an inspection station.

[0119] In the surface hydrophilization device 40, pure water is supplied onto the wafers W, S while the wafers W, S are rotated, for example, while being held by a spin chuck. Then, the supplied pure water is diffused over the surfaces Wa, Sa of the wafers W, S, and the surfaces Wa, Sa are hydrophilized.

[0120] In the third processing block G3, transition devices for wafers W, S, and overlapping wafer T are provided in two stages from the bottom.

[0121] 16, a wafer transfer region 60 is formed in an area surrounded by the first processing block G1 to the third processing block G3. A wafer transfer device 61, for example, is disposed in the wafer transfer region 60. The wafer transfer device 61 has a transfer arm that is movable, for example, vertically, horizontally (X-axis direction, Y-axis direction), and around a vertical axis (Z-axis). The wafer transfer device 61 moves within the wafer transfer region 60 and can transfer wafers W, S, and overlapping wafers T to desired devices in the surrounding first processing block G1, second processing block G2, and third processing block G3. The wafer transfer device 61 can also transfer wafers W, S, and overlapping wafers T to the inspection station 4.

[0122] The above-described joint system 1 is provided with at least one control unit 70 as shown in FIG. 16 . The control unit 70 processes computer-executable instructions that cause the joint system 1 to perform the various processes described in this disclosure. The control unit 70 may be configured to control each element of the joint system 1 to perform the various processes described herein. In one embodiment, some or all of the control unit 70 may be included in the joint system 1. The control unit 70 is realized, for example, by a computer. The control unit 70 may be one or more circuits, and may be provided as an integrated unit or partially separated. The control unit 70 may include a processing unit, a memory unit, and a communication interface. The functions performed by the processing unit described in this disclosure may be implemented in circuitry or processing circuitry, including general-purpose processors, application-specific processors, integrated circuits, ASICs (Application Specific Integrated Circuits), CPUs (Central Processing Units), conventional circuitry, and / or combinations thereof, programmed to perform the described functions. A processor is considered to be a circuit or processing circuit including transistors and other circuitry. A processor may also be a programmed processor that executes a program stored in a memory unit. This program (computer program product) may be stored in a memory unit in advance or may be obtained via a medium H when needed. The medium H may be any of various computer-readable storage media, such as a removable storage medium such as a memory card, an optical disc, or a hard disk drive (HDD), and the program may be provided stored on the storage medium. The medium H may also be a communication line connected to the communication interface, and the program may be distributed by a remote server device or the like. The acquired program is stored in the storage unit, and is read from the storage unit and executed by the processing unit.The storage unit may include a storage medium such as a RAM (Random Access Memory), a ROM (Read Only Memory), an EEPROM (Electronically Erasable Programmable Read Only Memory), a HDD (Hard Disk Drive), or an SSD (Solid State Drive), or a combination thereof. The communication interface may communicate with the connection system 1 via a communication line such as a LAN (Local Area Network). In this disclosure, a circuit, unit, or means is hardware programmed to realize the described functions or hardware configured to execute the functions. The hardware may be any hardware described in this disclosure or any hardware known to be programmed to realize or execute the described functions. If the hardware is a processor considered to be a type of circuit, the circuit, means, or unit is a combination of hardware and software used to configure the hardware and / or processor.

[0123] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The above-described embodiments may be omitted, substituted, or modified in various ways without departing from the scope and spirit of the appended claims. For example, the components of the above-described embodiments may be arbitrarily combined. Such an arbitrary combination naturally provides the functions and effects of each of the components involved in the combination, and also provides other functions and effects that are apparent to those skilled in the art from the description of this specification.

[0124] Furthermore, the effects described herein are merely descriptive or exemplary and are not limiting. In other words, the technology according to the present disclosure may achieve other effects that would be apparent to a person skilled in the art from the description of this specification, in addition to or in place of the above-described effects.

[0125] W First wafer S Second wafer T Overlapped wafer RL1 First resist film DC Wrinkle correction film

Claims

1. A substrate processing method comprising: bonding a first substrate including a device having a first pattern to a second substrate to form a laminated substrate; measuring wrinkles in the laminated substrate; performing a wrinkle reduction process on the laminated substrate; and forming a first resist film having a second pattern by performing photolithography on the laminated substrate that has been subjected to the wrinkle reduction process, wherein the wrinkle reduction process comprises: determining a first stress that is causing the wrinkles in the laminated substrate; determining a second stress that relieves the first stress; and forming a wrinkle correction film that applies the second stress on one side of the laminated substrate.

2. The substrate processing method according to claim 1, wherein the wrinkle correction film is formed by a process including: forming a stress-applying film on one surface of the laminated substrate, the stress-applying film applying stress to the laminated substrate; forming a second resist film on the stress-applying film; exposing and developing a position of the second resist film corresponding to the second stress; and injecting ions into the stress-applying film by ion implantation through the developed second resist film, thereby modifying the stress-applying film in the portion not covered by the second resist film.

3. The substrate processing method according to claim 1 or 2, further comprising: after forming the laminated substrate, thinning the rear surface of the first substrate in the laminated substrate; and the wrinkle reduction treatment is performed before thinning the rear surface of the first substrate.

4. The substrate processing method according to claim 1 or 2, further comprising: after forming the laminated substrate, thinning the rear surface of the first substrate in the laminated substrate; and the wrinkle reduction treatment is performed after thinning the rear surface of the first substrate.

5. The substrate processing method according to claim 1 or 2, wherein the wrinkle reduction process includes performing a flattening process so that the laminated substrate approaches a predetermined target shape.

6. The substrate processing method according to claim 5, wherein the planarization process is performed by a process including at least one selected from PPE, laser processing, and GCB.

7. The substrate processing method according to claim 6, wherein the planarization process includes PPE, and further includes forming a sacrificial film on one surface of the laminated substrate before performing the PPE.

8. The substrate processing method according to claim 1 or 2, wherein the wrinkle reduction treatment includes forming a friction-reducing film on one surface of the laminated substrate.

9. A substrate processing method comprising: measuring wrinkles on a first substrate including a device having a first pattern; performing a wrinkle reduction process on the first substrate; bonding the first substrate and a second substrate to form a laminated substrate; and performing photolithography on the laminated substrate to form a first resist film having a second pattern, wherein the wrinkle reduction process comprises: determining a first stress that is causing the wrinkles in the first substrate; determining a second stress that relieves the first stress; and forming a wrinkle correction film that imparts the second stress on one surface of the first substrate.

10. A substrate processing system, comprising: a bonding device that bonds a first substrate including a device having a first pattern to a second substrate to form a laminated substrate; an inspection device that measures wrinkles in the laminated substrate; and a control device, wherein the control device is configured to execute control including: measuring wrinkles in the laminated substrate; performing a wrinkle reduction process on the laminated substrate; and forming a first resist film having a second pattern by performing photolithography on the laminated substrate that has been subjected to the wrinkle reduction process, wherein the wrinkle reduction process includes: determining a first stress that is causing the wrinkles in the laminated substrate; determining a second stress that relieves the first stress; and forming a wrinkle correction film that applies the second stress on one side of the laminated substrate.

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