Semiconductor device and method for driving semiconductor device

Abstract

A semiconductor device according to exemplary embodiments comprises the steps of: outputting a chip scrub file including a plurality of scrub entries by each of a plurality of memory chips, so as to generate an error profile; diagnosing row hammering from the plurality of scrub entries of the error profile; and performing external error correction on at least one of the plurality of memory chips when the row hammering is diagnosed.

Description

Semiconductor devices and methods for driving semiconductor devices

[0001] The present invention relates to a semiconductor device and a semiconductor driving method, and more particularly, to a semiconductor device and a semiconductor driving method capable of improving the reliability and performance of a memory system.

[0002] Meanwhile, the present invention was supported by the following national research and development project.

[0003] Assignment ID: 171193550

[0004] Assignment Number: 2021-0-00863-003

[0005] Ministry of Science and ICT

[0006] Project Management Agency Name: Information and Communications Technology Planning and Evaluation Institute

[0007] Research Project Name: Development of New Concept PIM Semiconductor Technology

[0008] Research Project Title: Development of an Intelligent In-Memory Error Correction Device for High-Reliability Memory

[0009] Project implementation organization name: Seoul National University Industry-Academic Cooperation Foundation

[0010] Research period: January 1, 2023 - December 31, 2023

[0011] Driven by advancements in the electronics industry and user demands, electronic devices are becoming increasingly smaller and more powerful. Consequently, the semiconductor devices used in these devices are also increasingly demanding higher integration and performance.

[0012] In the case of DRAM (Dynamic Random Access Memory), as the gap between word lines narrows due to high integration, the voltage distribution of a single word line has an increasing effect on the charge of memory cells connected to adjacent word lines. Accordingly, when a single word line is accessed intensively, the row hammer phenomenon, in which data stored in memory cells connected to adjacent word lines is changed or lost due to the voltage of the activated state of a single word line, is becoming more severe, and technology to prevent row hammer is required.

[0013] The technical idea of ​​the present invention is to solve a problem by preventing row hammer attacks using a relatively small-sized register / buffer and providing a highly reliable semiconductor device.

[0014] The technical idea of ​​the present invention is to provide a semiconductor device with improved correction performance of an external error correction unit by using row mapping through randomization.

[0015] A method of driving a semiconductor device according to exemplary embodiments may include a step of generating an error profile by outputting a chip scrub file including a plurality of scrub entries for each of a plurality of memory chips, a step of diagnosing a row hammer from the plurality of scrub entries of the error profile, and a step of performing external error correction on at least one of the plurality of memory chips when the chip is diagnosed as a row hammer.

[0016] In addition, the step of generating the error profile may include a step in which each of the plurality of memory chips receives an ECS command of a memory controller, a step in which internal error correction is performed at least once based on the ECS command and the step in which each of the plurality of memory chips outputs a chip scrub file and the step in which the plurality of chip scrub files are merged to generate the error profile.

[0017] Additionally, each of the plurality of scrub entries of the chip scrub file may include address information in which a row address for which internal error correction has been completed is stored and error information in which the number of errors in the row address is stored.

[0018] Additionally, the chip scrub file may further include scrub address information including the row address at which the internal error correction was last performed.

[0019] In addition, the step of generating the chip scrub file includes the step of performing K all-bank refreshes, the step of storing information of M rows on which the all-bank refreshes were performed, respectively, to generate M scrub entries, and the step of generating the scrub address information on which the all-bank refresh is completed, and M may be equal to K / ((number of codewords included in one row) / (number of codewords processed by performing one all-bank refresh)).

[0020] Additionally, the number of errors may be defined as the number of codewords having uncorrectable errors after performing the internal error correction at the row level.

[0021] In addition, the step of diagnosing the low hammer includes the step of comparing the error count value of the error profile with a reference value, and the step of diagnosing the attack as a low hammer attack if the error count value of the error profile is greater than the reference value, and the error count value may be set to the largest value among the error counts of the plurality of scrub entries.

[0022] In addition, the step of performing the external error correction may include a step of generating damaged row address information based on address information corresponding to error information having an error number set as the error count value, a step of generating an external error correction address based on the damaged row address information and transmitting the external error correction address to a plurality of memory chips, and a step of performing external error correction by reading data of rows of the plurality of memory chips.

[0023] In addition, the step of diagnosing the row hammer may include a step of comparing an error count value of the error profile with a reference value, and a step of diagnosing an attack with a row hammer when the error count value of the error profile is greater than the reference value, and the step of setting the error count value may include a step of each of the plurality of memory chips outputting error counts in the plurality of scrub entries and adding them to generate a sum error count, and a step of comparing the sum error counts of the plurality of memory chips and setting a largest value as the error count value.

[0024] In addition, the step of performing the external error correction may include the step of generating damaged row address information based on address information of error information having the highest error count in a memory chip having a total error count set as the error count value, the step of generating an external error correction address based on the damaged row address information and transmitting the external error correction address to a plurality of memory chips, and the step of performing external error correction by reading data of rows of the plurality of memory chips.

[0025] In addition, the step of performing the external error correction may include the step of outputting damaged row address information from the error profile and inputting it to an external error correction unit, the step of generating an external error correction address based on the damaged row address information and transmitting it to a plurality of memory chips, the step of randomizing the external error correction address to generate a modified external error correction address, and the step of performing external error correction by reading data of different rows of the plurality of memory chips.

[0026] Additionally, the above-described modified external error correction address can be randomized using a scrambling function that satisfies condition 1 below.

[0027] [Condition 1]

[0028]

[0029] ( is the physical address of the external error correction address, is a scrambling function, is the inverse scrambling function, is an index that specifies a memory chip, (number of memory chips)

[0030] A method for driving a semiconductor device according to exemplary embodiments includes a step of receiving an ECS command transmitted from a memory controller and generating an ECS control signal, a step of inputting specific units of data from a memory cell array to an internal error correction unit by the ECS control signal, a step of performing internal error correction on the data to generate corrected data and generating a chip scrub file, and a step of inputting the corrected data to memory cell arrays, wherein the step of generating the chip scrub file may include a step of inputting a row address of the data and uncorrectable error data generated after performing the internal error correction into a scrub entry buffer, and a step of inputting the row address into a scrub address information buffer.

[0031] In addition, the method further includes a step of transmitting the chip scrub file to the memory controller to diagnose row hammer, and a step of performing external error correction on a damaged row when diagnosed as row hammer, wherein the chip scrub file includes a plurality of scrub entries and scrub address information, each of which includes address information where a row address for which internal error correction has been performed is stored and error information where the number of errors of the row address is stored, and the step of diagnosing the row hammer can compare the highest number of errors among the scrub entries with a reference value.

[0032] According to exemplary embodiments, a semiconductor device includes a memory controller including an ECS commander, and a plurality of memory cell arrays, an ECS engine unit receiving an ECS command of the ECS commander and transmitting an ECS control signal to the plurality of memory cell arrays, and an internal error correction unit receiving a codeword from the plurality of memory cell arrays based on the ECS control signal, performing internal error correction, and storing the internal error-corrected codeword in the plurality of memory cell arrays, wherein the ECS engine further includes a register for storing a chip scrub file including a plurality of scrub entries including address information storing a row address where internal error correction has been completed and error information storing a number of errors of the row address, and wherein the memory controller can diagnose a row hammer based on an error profile generated based on the chip scrub file of the plurality of memory chips.

[0033] In addition, the error profile is generated by merging chip scrub files of a plurality of memory chips, and the memory controller sets the largest value among the error numbers of a plurality of scrub entries of the error profile as an error count value, and can diagnose the row hammer by comparing the error count value with a reference value.

[0034] Additionally, the memory controller may further include an external error correction unit that generates damaged row address information from the error profile and performs external error correction for a plurality of memory chips.

[0035] According to embodiments of the present invention, the reliability of a semiconductor device can be improved by checking information on uncorrectable errors that occur during periodic internal error correction and performing external error correction in a memory controller.

[0036] By randomizing row mapping information of multiple memory chips, the performance or reliability of a semiconductor device can be improved by increasing the difficulty of targeting a specific damaged row or reducing the probability of occurrence of an uncorrectable error.

[0037] The various advantageous and beneficial effects of the present invention are not limited to the above-described contents, and will be more easily understood in the course of explaining specific embodiments of the present invention.

[0038] FIG. 1 is a schematic diagram of a semiconductor device according to exemplary embodiments.

[0039] Figure 2 is a configuration diagram of a memory controller according to exemplary embodiments.

[0040] Figure 3 is a configuration diagram of a memory chip according to exemplary embodiments.

[0041] Figure 4 is a configuration diagram of an ECS engine unit according to exemplary embodiments.

[0042] Figure 5 is a diagram for explaining the configuration of a semiconductor device and the operating units of an external error correction unit and an internal error correction unit.

[0043] Fig. 6 is a flowchart illustrating a method of driving a semiconductor device according to exemplary embodiments.

[0044] FIG. 7A is a flowchart illustrating an error profile generation step of a method for driving a semiconductor device according to exemplary embodiments.

[0045] FIG. 7b is a drawing for explaining an error profile generation step of a method for driving a semiconductor device according to exemplary embodiments.

[0046] FIG. 8 is a flowchart illustrating a low hammer diagnosis step of a method for driving a semiconductor device according to exemplary embodiments.

[0047] FIG. 9 is a flowchart illustrating an external error correction step of a method for driving a semiconductor device according to exemplary embodiments.

[0048] FIG. 10 is a flowchart illustrating an external error correction step of a method for driving a semiconductor device according to exemplary embodiments.

[0049] The purpose, technical configuration, and resulting operational effects of the present invention will be more clearly understood through the following detailed description based on the drawings attached to the specification of the present invention. Reference will now be made to the accompanying drawings, which will further describe embodiments of the present invention.

[0050] The embodiments disclosed herein should not be construed or used to limit the scope of the present invention. Those skilled in the art will readily appreciate that the descriptions herein, including the embodiments, have a wide range of applications. Therefore, any embodiments described in the detailed description of the present invention are intended to serve as illustrative examples to better illustrate the present invention and are not intended to limit the scope of the present invention to the embodiments.

[0051] The functional blocks depicted in the drawings and described below are merely examples of possible implementations. Other implementations may utilize other functional blocks without departing from the spirit and scope of the detailed description. Furthermore, while one or more functional blocks of the present invention are depicted as individual blocks, one or more of the functional blocks of the present invention may be a combination of various hardware and software configurations that perform the same function.

[0052] Additionally, the expression “including certain components” is an “open” expression, simply indicating the presence of those components, and should not be understood as excluding additional components.

[0053] Furthermore, when it is said that a component is “connected” or “connected” to another component, it should be understood that it may be directly connected or connected to that other component, but there may also be other components in between.

[0054] Hereinafter, various embodiments of the present invention will be described with reference to the accompanying drawings. However, this is not intended to limit the present invention to specific embodiments, and it should be understood that various modifications, equivalents, and / or alternatives of the embodiments of the present invention are included.

[0055]

[0056] Fig. 1 is a configuration diagram of a semiconductor device (1) according to exemplary embodiments.

[0057] Referring to FIG. 1, a semiconductor device (1) according to exemplary embodiments may include a memory controller (10) and a memory device (20).

[0058] The memory controller (10) may be configured to control memory operations such as writing and reading by providing various signals to the memory device (20) through the memory interface. For example, the memory controller (10) may provide a command / address (CA) to the memory device (20) to access data of the memory cell array (211, see FIG. 2). For example, the memory controller (10) may provide access to the memory device (20) through a memory bus. The memory controller (10) may access the memory device (20) at the request of, for example, a central processing unit (CPU), an application processor (AP), or the like.

[0059] The memory controller (10) may include an ECS commander (110) and an external error correction unit (120).

[0060] The ECS commander (110) may be configured to provide an ECS command / address (CA_ECS) that performs an error check and scrub operation to the memory device (20). The error check and scrub operation may be an operation that periodically performs error correction on the memory device (20) using an internal error correction unit (217, see FIG. 3).

[0061] The external error correction unit (120) may be configured to provide an external error correction command / address (CA_ECCO) to the memory device (20). The external error correction unit (120) may perform error correction or error detection for the memory chip (210). Unlike the internal error correction unit (see FIG. 3) built into the memory chip (210) of the memory device (100), the external error correction unit (120) may be configured to correct errors for a plurality of memory chips.

[0062]

[0063] A memory controller (10) may be connected to a memory device (20) via a memory bus. Each of a command / address (CA), data (DQ), an external error correction command / address (CA_ECCO), and an ECS command / address (CA_ECS) may be provided to the memory device (20) via at least one signal line. For example, the command / address (CA) may be transmitted from the memory controller (10) to the memory device (20) via a command / address signal line of the memory bus, and the data (DQ) may be transmitted from the memory controller (10) to the memory device (20) or from the memory device (20) to the memory controller (10) via a data bus composed of bidirectional signal lines of the memory bus. Depending on the embodiments, the external error correction command / address (CA_ECCO) or ECS command / address (CA_ECS) may be transmitted over the same signal line as the command / address (CA).

[0064] A command / address (CA) may include a command. For example, the command may include an active command for normal memory operations such as writing and reading data. The active command may refer to a command for switching the state of the memory cell array (211) to an active state in order to write data to the memory cell array (211) or read data from the memory cell array (211). The command may further include a precharge command for switching the state of the memory cell array (211) to a standby state or a refresh command for performing a refresh operation on the memory cell array (211).

[0065] An external error correction command / address (CA_ECCO) can be transmitted to a memory device (20) via an external error correction command / address signal line of a memory bus. The external error correction command / address (CA_ECCO) can include an external error correction command that corrects errors in data read from a memory cell array (211, see FIG. 2).

[0066] The ECS command / address (CA_ECS) can be transmitted to the memory device (20) via the ECS command / address signal line of the memory bus. The ECS command / address (CA_ECS) can include an ECS command that performs internal error correction on data within the memory cell array (211).

[0067] An access may include at least one of an active command, an external error correction command, a row address, and a column address, and may further include a write command, a read command, or a precharge command, depending on the embodiment.

[0068]

[0069] The memory device (20) may be a storage device based on a semiconductor device. The memory device (20) may include a memory chip (210), and the memory chip (210) may include a volatile memory device. In an exemplary embodiment, the memory device (20) may include at least one of random access memories (RAMs), such as dynamic random access memory (DRAM), synchronous DRAM (SDRAM), static RAM (SRAM), double date rate SDRAM (DDR SDRAM), phase-change RAM (PRAM), magnetic RAM (MRAM), and resistive RAM (RRAM).

[0070] Although only one memory chip is illustrated in FIG. 1, the memory device (20) may include a plurality of memory chips (210), and one command / address (CA), an external error correction command / address (CA_ECCO), or an ECS command / address (CA_ECS) may be transmitted to each of the plurality of memory chips (210).

[0071]

[0072] Figure 2 is a configuration diagram of a memory controller according to exemplary embodiments.

[0073] Referring to FIGS. 1 and 2, the ECS commander (110) may include an ECS command generation circuit (111) and an error profile storage unit (112).

[0074] The ECS command generation circuit (111) can generate an ECS command and transmit the ECS command to the memory device (20). The ECS command can mean at least one refresh command. In an exemplary embodiment, the ECS command can include an All Bank Refresh command. For example, the ECS command can mean a single All Bank Refresh command, but can also mean all refresh commands performed during the refresh window time (tREFW).

[0075] The error profile storage unit (112) can receive a plurality of chip scrub file data (EPFall) from the memory device (20). The error profile storage unit (112) can merge a plurality of chip scrub file data (EPFall) to generate error profile data (EPF) and store the error profile data (EPF). The error profile storage unit (112) can transmit the error profile data (EPF) to an external error correction unit (120). The error profile data (EPF) in the error profile storage unit (112) can be used for row hammer diagnosis as will be described later. According to embodiments of the present invention, a semiconductor device (1) having high reliability can be provided by diagnosing and correcting errors in a row hammer attack using a relatively small-sized error profile storage unit (112).

[0076] The error profile storage unit (112) has been described as an internal configuration of the memory controller, but may operate as an internal configuration of a separate memory chip, and in this case, it may perform the same or similar functions as described above.

[0077] The ECS commander (110) may further include a register (not shown) that stores a period-related value in order to periodically correct errors occurring within a plurality of memory chips (210). According to embodiments of the present invention, the ECS commander (110) generates an ECS command to periodically correct errors occurring within the memory chips, diagnoses errors caused by row hammer attacks, and generates error profile data (EPF) to prevent the errors from worsening into uncorrectable errors, thereby providing a semiconductor device (1) with improved reliability and row hammer prevention performance.

[0078] The external error correction unit (120) can receive error profile data (EPF) from the error profile storage unit (112) to diagnose row hammer, and if it corresponds to row hammer, can generate an external error correction command / address (CA_ECCO) and transmit it to the memory device (20). As described below, the external error correction unit (120) can receive a reference value from an internal register or a specific register of the memory controller (10) and compare the reference value with the error profile to diagnose row hammer. The external error correction unit (120) can generate an external error correction command / address (CA_ECAO) based on damaged row address information diagnosed as row hammer using the error profile.

[0079]

[0080] Figure 3 is a configuration diagram of a memory chip according to exemplary embodiments.

[0081] Referring to FIGS. 1 and 3, each of the plurality of memory chips (210) may include a memory cell array (211), an address buffer (213), a row decoder (214), a column decoder (215), an ECS engine unit (216), an internal error correction unit (217), and an input / output gating circuit (219).

[0082] The memory cell array (211) may include a plurality of memory cells provided in a matrix form arranged in a plurality of rows and columns. The memory cell array (211) may include a plurality of word lines and a plurality of bit lines connected to the plurality of memory cells. The plurality of word lines may be connected to rows of the plurality of memory cells. The rows of the plurality of memory cells may be memory cells connected to specific word lines. The plurality of bit lines may be connected to columns of the plurality of memory cells. The columns of the plurality of memory cells may be memory cells connected to specific bit lines.

[0083] The memory cell array (211) may include a plurality of sub-arrays. Each of the plurality of sub-arrays may include a plurality of word lines, and word lines located in the same row in different sub-arrays may be driven or activated at the same timing.

[0084]

[0085] The address buffer (213) can receive an input address included in a command / address (CA) from the memory controller (10). The input address can include a row address (ROW_ADD) and a column address (COL_ADD). The address buffer (213) can provide the row address (ROW_ADD) to the row decoder (214) and the column address (COL_ADD) to the column decoder (214). Each of the plurality of memory chips (210) can further include a command buffer that receives a command included in the command / address (CA). The command buffer can receive an active command, an external error correction command, etc. and provide them to the row decoder (214). As described below, the ECS engine unit (216) can receive an ECS command, but according to embodiments, the command buffer can also receive the ECS command.

[0086] The row decoder (214) can decode the row address received from the address buffer (213) and select word lines corresponding to the row address among a plurality of word lines. The row decoder (214) can activate the row by applying a voltage (hereinafter, an activation voltage) that turns on the selected word lines, thereby allowing access to the data bits of the memory cells of the selected row. The row decoder (214) can deactivate the row by applying a voltage that turns off the selected word lines, thereby preventing access to the data bits of the memory cells of the selected row.

[0087] The column decoder (215) can select predetermined bit lines among a plurality of bit lines. The column decoder (215) can generate a column selection signal based on a column address received from an address buffer (213) in a burst mode, and connect the bit lines selected by the column selection signal to an input / output gating circuit (219). The burst address can be addresses of column locations that can be accessed in relation to a burst length for a read command and / or a write command.

[0088] The input / output gating circuit (219) may include read data latches for storing read data of bit lines selected by a column select signal and a write driver for writing write data to the memory cell array (211). Data (DQ) may be output to or received from a data bus through the input / output gating circuit (219).

[0089] The ECS engine unit (216) can receive an ECS command / address (CA_ECS) and generate an ECS control signal (ECS) to transmit the ECS control signal to the memory cell array (211). The ECS control signal (ECS) may be a signal configured to read specific units of data from the memory cell array (211) to perform internal error correction. The ECS engine unit (216) can receive the ECS command / address (CA_ECS) and generate the ECS control signal (ECS), and according to embodiments, the ECS control signal (ECS) may be periodically generated using a register within the ECS engine unit (216). The ECS engine unit (216) can receive ECC error information data (EINF) and generate chip scrub file data (EPFi). The ECS engine unit (216) can transmit the chip scrub file data (EPFi) to the memory controller (10).

[0090] In an exemplary embodiment, the ECS engine unit (216) may output multiple ECS control signals (ECS) and input multiple ECC error information data (EINF) in one refresh window time (tREFW). The chip scrub file data (EPFi) may have its internal data value modified / changed each time the ECC error information data (EINF) is input.

[0091] The internal error correction unit (217) can perform internal error correction on specific units of data of the memory cell array (211). The memory cell array (211) can receive an ECS control signal (ECS) and output specific units of data (CW) to the internal error correction unit (217), and the internal error correction unit (217) can perform error correction on the received data (CW). The internal error correction unit (217) can generate corrected data (CW) and store them in the memory cell array (211). The internal error correction unit (217) can generate ECC error information data (EINF) for the data (CW) for which internal error correction is performed. The ECC error information data can include a row address of the data (CW) and information for determining whether an uncorrectable error has occurred after performing internal error correction. In this specification, an “uncorrectable error that occurs after internal error correction is performed” may be interpreted as an error that cannot be corrected by internal error correction, but may be corrected by more powerful external error correction.

[0092] Each of the plurality of memory chips (210) may further include a sense amplifier (212). The sense amplifier (212) may amplify and temporarily store cell data of an activated row.

[0093] In an exemplary embodiment, the memory cell array (211) may include a plurality of sub-arrays, and each of the plurality of memory chips (210) may include a plurality of sense amplifiers (212) corresponding to each of the plurality of sub-arrays.

[0094]

[0095] Figure 4 is a configuration diagram of an ECS engine unit according to exemplary embodiments.

[0096] The ECS engine unit (216) may include an ECS control signal generation circuit (2161) and an ECS register (2162). The ECS control signal generation circuit (2161) may receive an ECS command / address (CA_ECS) and generate an ECS control signal (ECS). The ECS register (2162) may receive and store ECC error information data (EINF) and generate chip scrub file data (EPFi). The ECS register (2162) may include a plurality of scrub entry buffers (SEB<1:M>) and a scrub address information buffer (SAB).

[0097]

[0098] FIG. 5 is a diagram illustrating a configuration of a semiconductor device (1a) according to exemplary embodiments and an operating unit of an external error correction unit and an internal error correction unit.

[0099] Referring to FIG. 5, a semiconductor device (1a) may include one memory controller (10) and two memory devices (20A, 20B) driven by one memory controller (10). Each of the memory devices (20A, 20B) may include nine memory chips (210), and each of the memory chips (210) may include four banks. In this case, one memory chip of each of the memory devices (20A, 20B) may be a chip for external error correction. The bank may correspond to a memory cell array (211), and each bank may include a plurality of sub-arrays. However, depending on the embodiments, the number of memory devices of the semiconductor device (10a), the number of memory chips of the memory device (20), and the number of banks of the memory chip (210) may vary.

[0100] An external error correction unit (120) can perform error correction and detection on a plurality of memory chips (210) within a memory device (20A, 20B). The external error correction unit (120) can perform external error correction on a chunk including a plurality of data read from a plurality of memory chips (210).

[0101] In an exemplary embodiment, the external error correction unit (120) may perform a first external error correction (P1), and the first external error correction (P1) may be performed in units of the memory devices (20A, 20B). For example, the first external error correction (P1) may be an operation of reading data from the first to eighth memory chips of the first memory device (20A) or the ninth to sixteenth memory chips of the second memory device (20B) to perform single-bit error correction and double-bit error detection. For example, the first external error correction (P1) may be error correction using a rank-level error correction code such as SECDED (single Error Correction, Double Error Detection).

[0102] In an exemplary embodiment, the external error correction unit (120) may perform a second external error correction (P2), and the second external error correction (P2) may be performed on all memory chips in the memory devices (20A, 20B) driven by the memory controller (10). For example, the second external error correction (P2) may be an operation of reading data from all of the first to sixteenth memory chips to correct errors in a single chip and detect errors in a double chip. For example, the second external error correction (P2) may be error correction using an error correction code such as a chipkill error correction code.

[0103] Each of the plurality of memory chips (210) may further include an internal error correction unit (217). The internal error correction unit (217) may perform error correction within the memory chip. In an exemplary embodiment, the internal error correction unit (217) may perform internal error correction (P3), and the internal error correction (P3) may perform single-bit error correction using additional parity based on a specific unit of data. The specific unit may vary depending on the data width of the data chips. For example, the internal error correction (P3) may be error correction using on-die ECC logic within the chip.

[0104] Referring to FIGS. 1 to 5, the external error correction unit (120) can transmit an external error correction command / address (CA_ECCO) to the memory device (20). Based on the external error correction address, data can be read from memory cell rows of each of a plurality of memory chips (210) and error correction can be performed. The internal error correction unit (217) can perform error correction on the corresponding memory chip (210) according to an external signal or an internal signal.

[0105]

[0106] Fig. 6 is a flowchart illustrating a method for driving a semiconductor device according to exemplary embodiments. Fig. 7a is a flowchart illustrating an error profile generation step of a method for driving a semiconductor device according to exemplary embodiments. Fig. 7b is a diagram for explaining an error profile generation step of a method for driving a semiconductor device according to exemplary embodiments. Fig. 8 is a flowchart illustrating a low hammer diagnosis step of a method for driving a semiconductor device according to exemplary embodiments. Fig. 9 is a flowchart illustrating an external error correction step of a method for driving a semiconductor device according to exemplary embodiments.

[0107]

[0108] Referring to FIG. 6, a method for driving a semiconductor device may include a step of generating an error profile (S100), a step of diagnosing a low hammer from the error profile (S200), and a step of performing external error correction (S300).

[0109] Referring to FIGS. 6, 7a, and 7b, the step (S100) of generating an error profile may include a step (S110) in which each of a plurality of memory chips (210, see FIG. 1) receives an ECS command / address (CA_ECS, see FIG. 1) of a memory controller (10), a step (S120) in which each of the plurality of memory chips (210) performs internal error correction and generates a chip scrub file (300), and a step (S130) in which the plurality of memory chips (210) output chip scrub file data (EPF<1:N>) to generate an error profile.

[0110] The ECS commander (110) of the memory controller (10) can generate an ECS command / address (CA_ECS) and transmit it to each of a plurality of memory chips (210), and the ECS engine unit (216, see FIG. 3) of the memory chip (210) can receive the ECS command / address (CA_ECS). (S110) The ECS engine unit (216) can receive the ECS command / address (CA_ECS) and generate an ECS control signal (ECS, see FIG. 3).

[0111] By the input ECS control signal (ECS), specific units of data (CW, see FIG. 3) are input from the memory cell array (211) to the internal error correction unit (217, see FIG. 3), internal error correction is performed on the data (CW), and corrected data (CW) can be generated and input to the memory cell array (211).

[0112] The internal error correction unit (217) can store the row addresses of data on which internal error correction has been performed and uncorrectable error data that has occurred after internal error correction in the scrub entry buffer (SEB, see FIG. 4) of the ECS engine unit (216, see FIGS. 3 and 4). The internal error correction unit (217) can store row address information (SA) on which internal error correction has been performed in the scrub address buffer (SAB, see FIG. 4).

[0113] At least one ECS control signal (ECS) can be input to the memory cell array (211) during one refresh window time (tREW). When multiple ECS control signals (ECS) are input during one refresh window time (tREW), errors in at least one row can be corrected.

[0114] In an exemplary embodiment, when K internal corrections are performed in one refresh window time (tREW), and data (CW) corresponding to A codewords are internally corrected by one ECS control signal (ECS), and when there are B codewords in one row, internal error correction can be performed for M rows satisfying the following equation during the refresh window time.

[0115] M = K / (B / A)

[0116] In this case, the ECS engine unit (216) may include M scrub entry buffers (SEB<1:M>) to store data for M rows.

[0117] A chip scrub file (300) may be stored in the ECS register (2162, see FIG. 4) of each of the memory chips (210). The chip scrub file (300) may include a plurality of scrub entries (320<1:M>, 330<1:M>) and scrub address information (310). Each of the plurality of scrub entries (320<1:M>, 330<1:M>) may include address information (320) in which a row address for which internal error correction has been completed is stored, and error information (330) in which the number of errors in the row address is stored. The number of errors may be defined as the number of codewords with uncorrectable errors after performing internal error correction on a row basis. The scrub address information (310) may include a row address for which internal error correction was last performed. That is, the scrub address information (310) can ensure synchronization of the error profile by including the progress row information during the internal error correction process of each of the plurality of memory chips (210). For example, if internal error correction is performed K times during one refresh window time (tREW), the chip scrub file (300) information can be modified or changed as ECC error data (EINF) is input each time the internal error correction is performed. In this case, synchronization for the plurality of memory chips (210) can be ensured by updating the row address information currently undergoing internal correction with the scrub address information (310).

[0118]

[0119] In an exemplary embodiment, a chip scrub file (300) may be generated and modified through the steps of performing K all-bank refreshes, storing information of M rows on which all-bank refreshes were performed, generating M scrub entries (320<1:M>, 330<1:M>), and generating scrub address information (310) on which all-bank refreshes are completed. In this case, M may be as follows.

[0120] M=K / ((Number of codewords contained in one row) / (Number of codewords processed by performing one all-bank refresh))

[0121] Each of the plurality of memory chips (210) may output chip scrub file data (EPFi) including a chip scrub file (300), and the plurality of chip scrub files may be merged to generate an error profile. (S130) The error profile data (EPF) may be stored in the ECS commander (110).

[0122]

[0123] Referring to FIGS. 6 and 8, the step (S200) of diagnosing a row hammer includes a step (S210) of comparing an error count value of an error profile with a reference value stored in a memory controller, and a step (S220) of diagnosing a row hammer attack if the error count value is greater than the reference value.

[0124] The error count value may be a value set from a plurality of scrub entries (320<1:MN>, 330<1:MN>) of the error profile. In one example, the error count value may be set to the largest value among the error numbers in the error information (330<1:MN>) of the plurality of scrub entries (320<1:MN>, 330<1:MN>). In another example, the error count value may be set to the largest value by comparing the sum error numbers for each memory chip. The sum error number may be set by summing the error numbers in the plurality of scrub entries for each of the plurality of memory chips, and for example, in the case of the first memory chip, the sum error number may be set by summing the error numbers of the plurality of error information (330<1:M>).

[0125] Row hammer can be diagnosed by comparing the error count value with the reference value, which is a parameter stored in the memory controller (10). If the error count value is greater than the reference value, it can be diagnosed as row hammer, and if the error count value is less than the reference value, it can be diagnosed as not row hammer.

[0126] According to embodiments of the present invention, errors caused by row hammer attacks can be prevented in advance by periodically detecting errors occurring in a plurality of memory chips (210) using an error check and clean operation in a memory controller (10) and diagnosing row hammers using correction information.

[0127] In an exemplary embodiment, a reference value within the memory controller (10) can be modified by changing a parameter within the memory controller (10). In addition, a plurality of reference values ​​within the memory controller (10) can be set. According to embodiments of the present invention, a semiconductor device (1) with an improved row hammer prevention function can be provided by dynamically and hierarchically diagnosing various row hammer attacks by changing the reference value or setting a plurality of reference values.

[0128]

[0129] Referring to FIGS. 6 and 9, the step (S300) of performing external error correction may include a step (S310) of inputting damaged row address information into an external error correction unit (120, see FIG. 1) when diagnosed as a row hammer, a step (S320) of generating an external error correction address based on the damaged row address information and transmitting it to a memory device (20), and a step (S330) of reading out row data of the memory device (20) to perform external error correction.

[0130] First, when diagnosed with a row hammer, damaged row address information can be generated based on the address information corresponding to the error information (330) having the number of errors set as the error count value. However, in the case of using the total number of errors as described in FIG. 8 according to the embodiments, row address information can be generated based on the address information corresponding to the error information (330) having the highest number of errors in the memory chip having the total number of errors set as the error count value.

[0131] The memory controller (10) can generate an external error correction address based on the damaged row address information and transmit the external error correction command / address to the memory device (20) through at least one signal line. (S320) The external error correction address can be transmitted to a plurality of memory chips (210).

[0132] A plurality of memory chips (210) can perform external error correction on chunks formed by reading data of selected rows based on external error correction addresses. (S330) In this case, the chunks may include data of damaged rows included in a specific memory chip. Efficient error correction can be performed by performing external error correction using an error profile including information on errors that cannot be corrected in internal error correction. In addition, by periodically receiving an error profile, error correction can be performed before an error that cannot be corrected by external error correction occurs, thereby preventing a row hammer attack.

[0133]

[0134] FIG. 10 is a flowchart illustrating an external error correction step of a method for driving a semiconductor device according to exemplary embodiments.

[0135] Referring to FIG. 10, the external error correction step may further include a step (325) of randomizing the external error correction address to generate a modified external error correction address.

[0136] Each of the plurality of memory chips (210) may further include a scrambling processor (not shown) that randomizes the row decoder (214), and the scrambling processor may form a modified external error correction address by randomizing the physical address value (PA) of the external error correction address through a scrambling function (F). The modified external error correction address may have different addresses by randomizing it through different scrambling functions for each of the plurality of memory chips (210).

[0137] A first memory chip can generate a first modified external error correction address (F0(PA)) by randomizing a physical address value (PA) of an external error correction address using a first scrambling function (F0), a second memory chip can generate a second modified external error correction address (F1(PA)) by randomizing a physical address value (PA) of an external error correction address using a second scrambling function (F1), and a third memory chip can generate a third modified external error correction address (F2(PA)) by randomizing a physical address value (PA) of an external error correction address using a third scrambling function (F2).

[0138] An external error correction address can be generated based on a physical address value targeting a specific damaged row to perform error correction of the data of the damaged row. For example, if the damaged row address generated using the error profile is F0(100)+1, which is one of the rows of the first memory chip, the first scrambling inverse function of the first scrambling function F0 is used to target the row. -1 Using the physical address value (PA) F0 -1 It can be specified as {F0(100)+1}.

[0139] In this case, the row mapped from the first memory chip is F0(100)+1 or F0[F0 mapped by the first modified error correction address (F0(PA)). -1 {F0(100)+1}] may be a row at the address (hereinafter, the address is described as the row). Similarly, the row mapped in the second memory chip may be F1[F0] mapped by the second variant address (F1(PA)). -1 {F0(100)+1}], and the row mapped in the third memory chip is F2[F0 mapped by the third variant address (F2(PA)). -1 It could be {F0(100)+1}].

[0140] In an exemplary embodiment, the modified external error correction address may be randomized using a scrambling function that satisfies condition 1 below.

[0141] [Condition 1]

[0142]

[0143] ( is the physical address of the external error correction address, is a scrambling function, is the inverse scrambling function, is an index that specifies a memory chip, (number of memory chips)

[0144] In this case, the step (S330') of performing external error correction can perform external error correction on chunks formed by reading data of rows mapped by a modified external error correction address. The external error correction can be successfully performed if an error below a threshold value occurs within the chunk. By generating different modified external error correction addresses for each memory chip through randomization, the number of errors exceeding the chunk threshold value can be reduced and the performance of error correction can be improved. In other words, by performing external error correction targeting a specific damaged row, the duplication phenomenon between damaged rows can be prevented or improved.

[0145] 1: Semiconductor devices

[0146] 10: Memory controller

[0147] 110: ECS Commander

[0148] 120: External error correction unit

[0149] 20: Memory device

[0150] 210: Memory chip

[0151] 216: ECS Engine

[0152] 217: Internal error correction unit

Claims

1. A step of generating an error profile by outputting a chip scrub file in which each of a plurality of memory chips includes a plurality of scrub entries; A step of diagnosing a low hammer from a plurality of scrub entries of the above error profile; and A method for driving a semiconductor device, comprising the step of performing external error correction on at least one of a plurality of memory chips when diagnosed with the above low hammer.

2. In paragraph 1, The steps for generating the above error profile are: A step in which each of the plurality of memory chips receives an ECS command from a memory controller; A step of performing at least one internal error correction based on the ECS command and generating the chip scrub file; and A method for driving a semiconductor device, comprising the steps of: each of a plurality of memory chips outputting a chip scrub file and merging the plurality of chip scrub files to generate an error profile.

3. In paragraph 2, A method for driving a semiconductor device, wherein each of the plurality of scrub entries of the chip scrub file includes address information where the row address for which the internal error correction has been completed is stored and error information where the number of errors in the row address is stored.

4. In paragraph 3, A method for driving a semiconductor device, wherein the chip scrub file further includes scrub address information including a row address at which the internal error correction was last performed.

5. In paragraph 4, The steps to create the above chip scrub file are Step of performing K all-bank refreshes; A step of generating M scrub entries by storing information of each of M rows for which the above all-bank refresh has been performed; and Including a step of generating the scrub address information for which the above all-bank refresh is completed, A method for driving a semiconductor device in which M=K / ((number of codewords contained in one row) / (number of codewords processed by performing an all-bank refresh at once)).

6. In paragraph 3, A method for driving a semiconductor device, wherein the above error number is defined as the number of codewords having uncorrectable errors after performing the internal error correction at the row level.

7. In paragraph 6, The steps for diagnosing the above low hammer are: A step of comparing the error count value of the above error profile with a reference value; and Including a step of diagnosing an attack with a low hammer when the error count value of the above error profile is greater than the reference value, A method for driving a semiconductor device, wherein the above error count value is set to the largest value among the error counts of the plurality of scrub entries.

8. In paragraph 7, The step of performing the above external error correction comprises the steps of: generating damaged row address information based on address information corresponding to error information having an error number set as the error count value; A step of generating an external error correction address based on the above damage row address information and transmitting the same to a plurality of memory chips; and A method for driving a semiconductor device, comprising a step of performing external error correction by reading data of rows of a plurality of memory chips.

9. In paragraph 6, The steps for diagnosing the above low hammer are: A step of comparing the error count value of the above error profile with a reference value; and Including a step of diagnosing an attack with a low hammer when the error count value of the above error profile is greater than the reference value, The step of setting the above error count value is: A step of each of the plurality of memory chips outputting and summing the error numbers in the plurality of scrub entries to generate a sum error number; and A method for driving a semiconductor device, comprising the step of comparing the total error counts of the plurality of memory chips and setting the largest value as an error count value.

10. In paragraph 9, The step of performing the above external error correction comprises the steps of: generating damaged row address information based on address information of error information having the highest error count in a memory chip having a total error count set as the error count value; A step of generating an external error correction address based on the above damage row address information and transmitting the same to a plurality of memory chips; and A method for driving a semiconductor device, comprising a step of performing external error correction by reading data of rows of a plurality of memory chips.

11. In paragraph 1, The step of performing the above external error correction is: A step of outputting damaged row address information from the above error profile and inputting it into an external error correction unit; A step of generating an external error correction address based on the above damage row address information and transmitting the same to a plurality of memory chips; A step of generating a modified external error correction address by randomizing the external error correction address; and A method for driving a semiconductor device, comprising a step of performing external error correction by reading data of different rows of the plurality of memory chips.

12. In paragraph 11, The above-mentioned modified external error correction address is a method for driving a semiconductor device randomized using a scrambling function that satisfies condition 1 below. [Condition 1] ( is the physical address of the external error correction address, is a scrambling function, is the inverse scrambling function, is an index that specifies a memory chip, (number of memory chips) 13. A step of receiving an ECS command transmitted from a memory controller and generating an ECS control signal; A step in which specific units of data are input from a memory cell array to an internal error correction unit by the ECS control signal; A step of performing internal error correction of the above data to generate corrected data and generate a chip scrub file; and A step of inputting the above corrected data into memory cell arrays is included, The steps for generating the above chip scrub file are: A step of inputting the row address of the above data and the uncorrectable error data that occurred after the internal error correction is performed into the scrub entry buffer; and A method for driving a semiconductor device, comprising the step of inputting the above row address into a scrub address information buffer.

14. In paragraph 13, A step of diagnosing a low hammer by transmitting the chip scrub file to the memory controller; and If diagnosed as a low hammer, further comprising a step of performing external error correction on the damaged row, The chip scrub file includes a plurality of scrub entries and scrub address information, each of which includes address information where a row address for which internal error correction has been performed is stored and error information where the number of errors in the row address is stored. A method of driving a semiconductor device, wherein the step of diagnosing the above low hammer compares the highest error number among scrub entries with a reference value.

15. A memory controller including an ECS commander; and A plurality of memory chips each including a plurality of memory cell arrays, an ECS engine unit that receives an ECS command of the ECS commander and transmits an ECS control signal to the plurality of memory cell arrays, and an internal error correction unit that receives a codeword from the plurality of memory cell arrays based on the ECS control signal, performs internal error correction, and stores the internal error-corrected codeword in the plurality of memory cell arrays, The ECS engine further includes a register for storing a chip scrub file including a plurality of scrub entries including address information where a row address for which internal error correction has been completed is stored and error information where the number of errors in the row address is stored, A semiconductor device in which the memory controller diagnoses a low hammer based on an error profile generated based on the chip scrub file of the plurality of memory chips.

16. In paragraph 15, The above error profile is generated by merging chip scrub files of multiple memory chips, A semiconductor device in which the memory controller sets the largest value among the error counts of a plurality of scrub entries of the error profile as an error count value and diagnoses the row hammer by comparing the error count value with a reference value.

17. In paragraph 15, A semiconductor device wherein the memory controller further includes an external error correction unit that generates damaged row address information from the error profile and performs external error correction for a plurality of memory chips.

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