Display panel and display apparatus

Abstract

A display panel and a display apparatus. The display panel comprises a plurality of data signal lines (Data), a plurality of first pixel circuit columns (10c) and a plurality of first light-emitting element columns (20c), wherein a plurality of first pixel circuits (10), which are arranged in a first direction (X), are electrically connected to the same data signal line (Data); and the plurality of first pixel circuit columns (10c) comprise the plurality of first pixel circuits (10), which are arranged in the first direction (X); the plurality of first light-emitting element columns (20c) comprise light-emitting elements (20), which are arranged in the first direction (X) and emit light of different colors; two types of light-emitting elements (20), which emit light of different colors, are respectively electrically connected to first pixel circuits (10) located in different first pixel circuit columns (10c); and a plurality of first pixel circuits (10) in the same first pixel circuit column (10c) are electrically connected to a plurality of light-emitting elements (20) of the same color.

Description

Display panel and display device

[0001] This application claims priority to the Chinese patent application No. 202411259154.2, filed on September 9, 2024, with the Chinese Patent Office, the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] Embodiments of the present application relate to the display technical field, for example, to a display panel and a display device. BACKGROUND

[0003] To improve the display effect of the display panel, in the related art, there is a case that different color sub-pixels are arranged in a sub-pixel column, and the different color sub-pixels in the sub-pixel column receive data signals transmitted by the same data line. This kind of arrangement mode increases the power consumption of the display controller in the display panel.

[0004] SUMMARY

[0005] Based on the above problems, the present application provides a display panel and a display device, which reduce the power consumption of the display controller and the display panel on the basis of ensuring the display effect.

[0006] In a first aspect, embodiments of the present application provide a display panel, comprising: a plurality of data signal lines, the plurality of data signal lines extend along a first direction and are arranged along a second direction, the first direction and the second direction intersect; a plurality of first pixel circuits, a plurality of the first pixel circuits arranged along the first direction are electrically connected to the same data signal line; a plurality of first pixel circuit columns and a plurality of first light emitting element columns; the first pixel circuit column comprises a plurality of the first pixel circuits arranged along the first direction; the first light emitting element column comprises two light emitting elements with different light emitting colors arranged along the first direction, and the two light emitting elements with different light emitting colors are respectively electrically connected to the first pixel circuits in different first pixel circuit columns, and a plurality of the first pixel circuits in the same first pixel circuit column are electrically connected to a plurality of the light emitting elements of the same color.

[0007] In a second aspect, embodiments of the present application provide a display device, comprising the display panel of the first aspect of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0008] FIG. 1 is a structural schematic diagram of a display panel in the related art according to an embodiment of the present application;

[0009] FIG. 2 is a timing diagram on the data signal line of the display panel shown in FIG. 1;

[0010] FIG. 3 is a structural schematic diagram of a display panel according to an embodiment of the present application;

[0011] FIG. 4 is a schematic diagram of a partial film layer structure of the display panel shown in FIG. 3;

[0012] FIG. 5 is a timing diagram of a data signal line in the display panel shown in FIG. 3;

[0013] FIG. 6 is a schematic diagram of a first pixel circuit according to an embodiment of the present application;

[0014] FIG. 7 is a driving timing diagram of the embodiment shown in FIG. 6;

[0015] FIG. 8 is a schematic diagram of a partial enlarged structure of the display panel shown in FIG. 4;

[0016] FIG. 9 is a schematic diagram of another display panel according to an embodiment of the present application;

[0017] FIG. 10 is a schematic diagram of a cross-sectional structure of the display panel shown in FIG. 9 along the A-A' direction;

[0018] FIG. 11 is a schematic diagram of still another display panel according to an embodiment of the present application;

[0019] FIG. 12 is a schematic diagram of a partial enlarged structure of the display panel shown in FIG. 11;

[0020] FIG. 13 is a schematic diagram of yet another display panel according to an embodiment of the present application;

[0021] FIG. 14 is a schematic diagram of a partial enlarged structure of the display panel shown in FIG. 13;

[0022] FIG. 15 is a schematic diagram of still another display panel according to an embodiment of the present application;

[0023] FIG. 16 is a schematic diagram of a partial enlarged structure of the display panel shown in FIG. 15;

[0024] FIG. 17 is a schematic diagram of yet another display panel according to an embodiment of the present application;

[0025] FIG. 18 is a schematic diagram of still another display panel according to an embodiment of the present application;

[0026] FIG. 19 is a schematic diagram of a cross-sectional structure of a display panel according to an embodiment of the present application;

[0027] FIG. 20 is a schematic diagram of a partial structure of the display panel shown in FIG. 19;

[0028] FIG. 21 is a schematic diagram of another partial structure of the display panel shown in FIG. 19;

[0029] FIG. 22 is a schematic diagram of another partial structure of the display panel shown in FIG. 19;

[0030] FIG. 23 is a schematic diagram of another partial structure of the display panel shown in FIG. 19;

[0031] FIG. 24 is a schematic diagram of another part of the display panel shown in FIG. 19;

[0032] FIG. 25 is a schematic diagram of another part of the display panel shown in FIG. 19;

[0033] FIG. 26 is a schematic diagram of another part of the display panel shown in FIG. 19;

[0034] FIG. 27 is a schematic diagram of another part of the display panel shown in FIG. 19;

[0035] FIG. 28 is a schematic diagram of another part of the display panel shown in FIG. 19;

[0036] FIG. 29 is a schematic diagram of a structure of another display panel provided by an embodiment of the present application;

[0037] FIG. 30 is a schematic diagram of a cross-sectional structure of another display panel provided by an embodiment of the present application;

[0038] FIG. 31 is a schematic diagram of a part of the display panel shown in FIG. 30;

[0039] FIG. 32 is a schematic diagram of another part of the display panel shown in FIG. 30;

[0040] FIG. 33 is a schematic diagram of another part of the display panel shown in FIG. 30;

[0041] FIG. 34 is a schematic diagram of another part of the display panel shown in FIG. 30;

[0042] FIG. 35 is a schematic diagram of another part of the display panel shown in FIG. 30;

[0043] FIG. 36 is a schematic diagram of another part of the display panel shown in FIG. 30;

[0044] FIG. 37 is a schematic diagram of another part of the display panel shown in FIG. 30;

[0045] FIG. 38 is a schematic diagram of another part of the display panel shown in FIG. 30;

[0046] FIG. 39 is a schematic diagram of a structure of a seventh metal layer in a display panel provided by an embodiment of the present application;

[0047] FIG. 40 is a schematic diagram of a structure of an eighth metal layer in a display panel provided by an embodiment of the present application;

[0048] FIG. 41 is a schematic diagram of a structure of an anode layer in a display panel provided by an embodiment of the present application;

[0049] FIG. 42 is a schematic diagram of a part of a film layer stack structure of a display panel provided by an embodiment of the present application;

[0050] FIG. 43 is a structural schematic diagram of an anode of a light emitting element according to an embodiment of the present application;

[0051] FIG. 44 is a structural schematic diagram of an anode of another light emitting element according to an embodiment of the present application;

[0052] FIG. 45 is a structural schematic diagram of a display panel according to an embodiment of the present application;

[0053] FIG. 46 is a structural schematic diagram of another display panel according to an embodiment of the present application;

[0054] FIG. 47 is a structural schematic diagram of another display panel according to an embodiment of the present application;

[0055] FIG. 48 is a structural schematic diagram of a display device according to an embodiment of the present application. DETAILED DESCRIPTION

[0056] The present application will be described in detail below with reference to the drawings and embodiments. It can be understood that the embodiments described herein are only used to explain the present application, but not limit the present application. For ease of description, only parts related to the present application are shown in the drawings, but not all structures.

[0057] It should be noted that "have", "contain", "include" and the like described in the present application are open-ended, that is, when a module is described as "having", "containing" or "including" a first element, a second element and / or a third element, it means that the module includes other elements in addition to the first element, the second element and / or the third element. In addition, the ordinal numbers "first", "second" and "third" in the present application are not intended to limit the order, but only to distinguish the parts. In the present application, when layer A and layer B are described as "disposed in the same layer", it means that layer A and layer B are made of the same material and the same process.

[0058] FIG. 1 is a structural schematic diagram of a display panel in the prior art, and FIG. 2 is a timing diagram of a data signal line in the display panel shown in FIG. 1. Referring to FIG. 1, in the prior art, some columns of sub-pixels include red sub-pixels R and blue sub-pixels B arranged alternately along the column direction, the pixel circuits corresponding to the red sub-pixels R and the blue sub-pixels B in the same column are electrically connected to the same data signal line Data, and the pixel circuits corresponding to the red sub-pixels R and the blue sub-pixels B are respectively provided with data signals by the same data signal line Data. Referring to FIG. 2, because the voltages of the data signals required by the red sub-pixels R and the blue sub-pixels B are different, the voltage of the data signal on the data signal line Data needs to jump between two different voltage values, as shown in FIG. 2. When displaying a picture, for example, a red, blue or white monochrome picture, there is a large voltage fluctuation on the data signal line Data, thereby increasing the power consumption of the display controller (for example, a driving chip).

[0059] Based on the defects of the prior art described above, the present application provides a display panel, FIG. 3 is a structural schematic diagram of a display panel according to an embodiment of the present application, and FIG. 4 is a schematic diagram of a partial film layer structure of the display panel shown in FIG. 3. Referring to FIGS. 3 and 4, the display panel can include: a plurality of data signal lines Data, the plurality of data signal lines Data extend along a first direction X and are arranged along a second direction Y, the first direction X and the second direction Y intersect; a plurality of first pixel circuits 10, the plurality of first pixel circuits 10 arranged along the first direction X are electrically connected to the same data signal line Data; a plurality of first pixel circuit columns 10c and a plurality of first light emitting element columns 20c; the first pixel circuit column 10c includes a plurality of first pixel circuits 10 arranged along the first direction X; the first light emitting element column 20c includes two light emitting elements 20 of different light emitting colors arranged along the first direction X, and the two light emitting elements 20 of different light emitting colors are respectively electrically connected to the first pixel circuits 10 located in different first pixel circuit columns 10c, and the plurality of first pixel circuits 10 in the same first pixel circuit column 10c are electrically connected to a plurality of light emitting elements 20 of the same color.

[0060] As shown in FIG. 3 and FIG. 4, the display panel can include a plurality of data signal lines Data, a plurality of pixel circuits and a plurality of light emitting elements 20. The plurality of pixel circuits include a plurality of first pixel circuits 10, which are arranged in an array along a first direction X and a second direction Y. The first direction X shown in FIG. 3 can be a column direction, and the second direction Y can be a row direction, which is not limited in practice. In the present embodiment, the first direction X is taken as the column direction, and the second direction Y is taken as the row direction as an example for description. The plurality of first pixel circuits 10 arranged along the first direction X form a first pixel circuit column 10c, and the plurality of first pixel circuit columns 10c are arranged along the second direction Y. One data signal line Data is electrically connected to the plurality of first pixel circuits 10 arranged along the first direction X, that is, one data signal line Data is connected to the plurality of first pixel circuits 10 in the same first pixel circuit column 10c, and the plurality of first pixel circuits 10 arranged along the first direction X are transmitted with data signals by the same data signal line Data. FIG. 3 shows a schematic diagram of the electrical connection relationship among the data signal line Data, the first pixel circuit 10 and the light emitting element 20, rather than an actual wiring diagram. In FIG. 3, one data signal line Data is connected to the light emitting element 20 of one color through one column of first pixel circuits 10.

[0061] With continuous reference to FIG. 3 and FIG. 4, the pixel circuit is electrically connected to the light emitting element 20, so as to drive the light emitting element 20 to emit light and realize the display of the display panel. The plurality of light emitting elements 20 include at least two kinds of light emitting elements 20 of different colors, and the light emitting element 20 can be an organic light emitting diode. The plurality of light emitting elements 20 arranged along the first direction X form a first light emitting element column 20c, and the plurality of first light emitting element columns 20c are arranged along the second direction Y. The same first light emitting element column 20c includes at least two kinds of light emitting elements 20 of different colors, that is, the plurality of light emitting elements 20 arranged along the first direction X include light emitting elements 20 of different colors. In FIG. 3, the light emitting elements 20 of different colors are represented by rhombus patterns with different fill patterns. In the present embodiment, the light emitting elements 20 of different colors in the same first light emitting element column 20c are electrically connected to the first pixel circuits 10 in different first pixel circuit columns 10c, and the plurality of first pixel circuits 10 in the same first pixel circuit column 10c are electrically connected to the plurality of light emitting elements 20 of the same color, that is, the same column of first pixel circuits 10 is connected to the light emitting elements 20 of the same color, and the light emitting elements 20 connected by the same column of first pixel circuits 10 are located in different first light emitting element columns 20c. Along the thickness direction of the display panel, the first pixel circuit column 10c can overlap the first light emitting element column 20c, that is, the first pixel circuit column 10c overlaps at least two kinds of light emitting elements 20 of different colors.

[0062] In this arrangement, the plurality of first pixel circuits 10 connected to the same data signal line Data are connected to the same color light emitting elements 20 in different first light emitting element columns 20c, and the data signal line Data provides data signals to the same color light emitting elements 20 in different first light emitting element columns 20c through the plurality of first pixel circuits 10 arranged along the first direction X.

[0063] FIG. 5 is a timing diagram of the data signal line in the display panel shown in FIG. 3. Referring to FIGS. 3-5, since the same data signal line Data is connected to the same color light emitting elements 20, the data signal required by the light emitting elements 20 of one color on the data signal line Data is only one stable data signal, or the data signal line Data no longer needs to provide a data signal with varying voltage values, and there is no problem of voltage jump of the data signal on the data signal line Data, thereby solving the problem of large power consumption of the display controller (driver chip) in the related art, achieving the purpose of reducing the power consumption of the display controller, and further reducing the overall power consumption of the display panel. According to tests, the power consumption of the display controller can be reduced by about 25% using the scheme in the application embodiment. In addition, since there is no need to transmit a varying data signal on the same data signal line Data, the problem of easy coupling of the jumping data signal with other signals can also be avoided, ensuring the stability of signal transmission in the display panel.

[0064] For example, the first light emitting element column 20c can include red light emitting elements and blue light emitting elements arranged along the first direction X, and the red light emitting elements and the blue light emitting elements arranged along the first direction X are connected to different first pixel circuit columns 10, or the red light emitting elements and the blue light emitting elements connected to the same first pixel circuit column 10 are located in different first light emitting element columns 20c. The arrangement of light emitting elements 20 of different colors is more uniform, which is conducive to improving color deviation and jaggedness and improving the display effect of the display panel.

[0065] In the embodiments shown in FIG. 3 and FIG. 4, the two kinds of light emitting elements 20 with different light emitting colors are respectively electrically connected with the first pixel circuits 10 in two columns of the first pixel circuit columns 10c, that is, the multiple light emitting elements 20 with one color in the same first light emitting element column 20c are electrically connected with the multiple first pixel circuits 10 in one column of the first pixel circuit columns 10c, and the multiple light emitting elements 20 with another color are electrically connected with the multiple first pixel circuits 10 in another column of the first pixel circuit columns 10c, which is not limited to this. In other embodiments, the multiple light emitting elements 20 with one color in the same first light emitting element column 20c can be electrically connected with the first pixel circuits 10 in two or more columns of the first pixel circuit columns 10c, and the multiple light emitting elements 20 with another color can be electrically connected with the first pixel circuits 10 in another two or more columns of the first pixel circuit columns 10c, as long as the light emitting elements 20 connected with the first pixel circuits 10 in the same column are of the same color, which is not limited in the embodiments of the present application.

[0066] It should be noted that in FIG. 3 and FIG. 4, the dashed line extending along the first direction and with thick line can be understood as the approximate position of the boundary between the two adjacent columns of pixel circuit columns, and the dashed line extending along the second direction and with thick line can be the approximate position of the boundary between the two adjacent rows of pixel circuit rows.

[0067] The display panel provided by the embodiments of the present application includes multiple data signal lines, multiple first pixel circuit columns and multiple first light emitting element columns. The multiple first pixel circuits arranged along the first direction are electrically connected with the same data signal line. The multiple first pixel circuit columns include multiple first pixel circuits arranged along the first direction, and the multiple first light emitting element columns include light emitting elements with different light emitting colors arranged along the first direction. Two kinds of light emitting elements with different light emitting colors are electrically connected with the first pixel circuits in different first pixel circuit columns, and the multiple first pixel circuits in the same first pixel circuit column are electrically connected with multiple light emitting elements with the same color. By using the above scheme, the multiple first pixel circuits connected with the same data signal line are electrically connected with the light emitting elements with the same color in different first light emitting element columns. Only the data signal required by the light emitting elements with one color can be transmitted on one data signal line, so that stable data signal is transmitted on the data signal, and the data signal voltage on the data signal line does not jump, thereby reducing the power consumption of the display controller and the display panel.

[0068] In addition, in the embodiment of the present application, the light emitting element in the first light emitting element column 20c is connected with the first pixel circuit 10, which can mean that the light emitting element in the first light emitting element column 20c is connected with one node of the first pixel circuit 10. FIG. 6 is a circuit schematic diagram of a first pixel circuit provided in the embodiment of the present application, and FIG. 7 is a driving timing diagram of the embodiment shown in FIG. 6. The setting mode of the first pixel circuit 10 has diversity, and FIG. 6 takes the pixel circuit as an example to illustrate "8T1C", wherein "T" represents a transistor, and "C" represents a capacitor. The embodiment of the present application is only used as an example for illustration, and other pixel circuits, such as "6T1C", "7T1C" pixel circuits, etc. are within the scope of the technical solutions protected in the embodiment of the present application.

[0069] As shown in FIGS. 6 and 7, the pixel circuit can include a first light emitting control transistor T1, a data writing transistor T2, a driving transistor T3, a threshold compensation transistor T4, an initialization transistor T5, a second light emitting control transistor T6, a reset transistor T7, and a storage capacitor Cst. The pixel circuit shown in FIG. 6 further includes a bias transistor T8. For the working process of the pixel circuit, reference is made to FIGS. 6 and 7. The first scan signal line S1 can control the on or off of the initialization transistor T5 of the pixel circuit, and reset the gate potential of the driving transistor T3 when the initialization transistor T5 is turned on, i.e., the initialization signal of the initialization signal line VREF1 is transmitted to the initialization transistor T5, and the connection node (the first node N1) of the driving transistor T3, the initialization transistor T5, the threshold compensation transistor T4, and the storage capacitor Cst is reset. The third scan signal line SP* controls the on or off of the data writing transistor T2 of the pixel circuit, and writes the data signal on the data signal line Data to the gate of the driving transistor T3 when the data writing transistor T2 is turned on. The second scan signal line S2 can control the on or off of the threshold compensation transistor T4, and compensate the threshold voltage of the driving transistor T3 when the threshold compensation transistor T4 is turned on. Meanwhile, the fourth scan signal line SP controls the on or off of the reset transistor T7, and resets the anode of the light emitting element connected to the pixel circuit when the reset transistor T7 is turned on, i.e., the reset signal of the reset signal line VREF2 is transmitted to the anode of the light emitting element. The light emitting control signal line EMIT controls the on or off of the first light emitting control transistor T1 and the second light emitting control transistor T6, and the power signal transmitted by the power signal line PVDD is transmitted to the light emitting element when the first light emitting control transistor T1 and the second light emitting control transistor T6 are controlled to be turned on, so as to realize the display and light emission of the light emitting element. As shown in FIG. 6, the pixel circuit further includes a bias transistor T8. The fourth scan signal line SP controls the on or off of the bias transistor T8, and biases the driving transistor T3 when the bias transistor T8 is turned on, i.e., the bias signal of the bias voltage signal line DVH is transmitted to the bias transistor T8, and the connection node (the second node N2) of the driving transistor T3, the first light emitting control transistor T1, and the data writing transistor T2 is biased, so as to ensure the working stability of the driving transistor T3. It can be understood that the bias transistor T8 can also be electrically connected to the third node N3 (the connection node of the driving transistor T3, the second light emitting control transistor T6, and the threshold compensation transistor T4), or the bias transistor T8 is electrically connected to the second node N2 and the third node N3 at the same time. The bias signal of the bias voltage signal line DVH includes an enabled level and a disabled level. The enabled level can turn on the bias transistor T8; and the disabled level can turn off (or cut off) the bias transistor T8.By setting the bias transistor T8, the first frame brightness during picture display can be improved, the first frame brightness can be prevented from being too low, and the picture display effect consistency is ensured to be good. In addition, under low-frequency driving, the leakage is more obvious, by controlling the bias transistor T8 to be turned on, and by using the bias transistor T8 to write a bias voltage to the source and / or drain of the driving transistor T3, the bias state of the driving transistor T3 can be maintained consistent with the bias state when the data voltage is just written, so that the stability of the working state of the driving transistor T3 is improved, the low-frequency flicker is improved, and the picture display effect of the display panel is improved.

[0070] For example, with reference to FIGS. 6 and 7, the initialization transistor T5 and the threshold compensation transistor T4 in the pixel circuit are N-type transistors, and the other transistors are P-type transistors. An enabled level can turn on a transistor, and a non-enabled level can turn off (or cut off) the transistor. The non-enabled level of the light-emitting control signal EMIT is a high level, and the enabled level is a low level. The enabled level of the signals transmitted by the first scan signal line S1 and the second scan signal line S2 is a high level, and the non-enabled level is a low level. The enabled level of the signals transmitted by the fourth scan signal line SP and the third scan signal line SP* is a low level, and the non-enabled level is a high level. In one driving period Y of the pixel circuit, the gate signal transmitted by the light-emitting control signal line EMIT includes a plurality of non-enabled level stages and a plurality of enabled level stages, and the plurality of non-enabled level stages and the plurality of enabled level stages are arranged alternately. When the light-emitting control signal line EMIT is at the non-enabled level, the first light-emitting control transistor T1 and the second light-emitting control transistor T6 are cut off. When the light-emitting control signal line EMIT is at the enabled level, the first light-emitting control transistor T1 and the second light-emitting control transistor T6 are turned on.

[0071] In one driving period Y of the pixel circuit, the driving period Y includes a data writing stage Y1, a light-emitting stage Y2, and a light-emitting maintaining stage Y3. The data writing stage Y1 includes one non-enabled level stage of the light-emitting control signal EMIT. The light-emitting stage Y2 includes one enabled level stage of the light-emitting control signal EMIT. In the light-emitting maintaining stage Y3, the light-emitting control signal EMIT includes a plurality of non-enabled level stages and at least one enabled level stage (one enabled level stage is taken as an example in FIG. 7 for illustration). Meanwhile, the level of the bias voltage signal line DVH in the data writing stage Y1 and the light-emitting stage Y2 can be the same as or different from the level of the bias voltage signal line DVH in the light-emitting maintaining stage Y3 (as shown in FIG. 7).

[0072] In the data writing stage Y1, a first bias adjusting stage Y11 is included, in which the signal transmitted by the fourth scan signal line SP includes at least one low level period, and the signal transmitted by the second scan signal line S2 includes at least one high level period, in other words, in the first bias adjusting stage Y11, at least the bias transistor T8 and the threshold compensation transistor T4 are turned on, the bias signal of the bias voltage signal line DVH is transmitted to the driving transistor T3 through the bias transistor T8, and is re-transmitted to the gate of the driving transistor T3 through the threshold compensation transistor T4, that is, in the first bias adjusting stage Y11, the bias signal can perform bias adjustment on the first node N1, the second node N2 and the third node N3. The data writing stage Y1 also includes an initialization and second bias adjusting stage Y12, in which the signal transmitted by the second scan signal line S2 includes at least one high level period, and there is also a period in which the signal transmitted by the second scan signal line S2 includes at least one high level period, in other words, in the initialization and second bias adjusting stage Y12, the initialization transistor T5 is turned on, and the threshold compensation transistor T4 is also turned on later, the initialization signal line VREF1 can adjust the gate of the driving transistor T3 through the initialization transistor T5, and the initialization signal line VREF1 can also adjust the third node N3 through the initialization transistor T5 and the threshold compensation transistor T4.

[0073] The data writing stage Y1 also includes a data signal writing stage Y13, in which the signal transmitted by the second scan signal line S2 includes a high level period, and the signal transmitted by the third scan signal line SP* includes at least one low level period, in other words, in the data signal writing stage Y13, the data writing transistor T2 and the threshold compensation transistor T4 are turned on, and the data signal can be transmitted to the gate of the driving transistor T3 through the data writing transistor T2 and the threshold compensation transistor T4. The data writing stage Y1 also includes a third bias adjusting stage Y14, in which the signal transmitted by the fourth scan signal line SP includes at least one low level period, and the second stage N2 can be biased and adjusted again through the bias transistor T8 during this period.

[0074] If a driving period Y of the pixel circuit is a low frequency period, the driving period Y includes the data writing stage Y1, the light emitting stage Y2 and the light emitting maintaining stage Y3, and if a driving period Y of the pixel circuit is a high frequency period, the driving period Y includes the data writing stage Y1 and the light emitting stage Y2.

[0075] Optionally, the types of the transistors in the pixel circuit are diverse. For example, the transistors can all be low temperature poly-silicon (LTPS) transistors, or all be Indium Gallium Zinc Oxide (IGZO) transistors, or part be LTPS transistors and part be IGZO transistors. The LTPS transistors have the advantages of high switching speed, high carrier mobility and small power, and the IGZO transistors have the advantage of small leakage current. The display panel of low temperature polycrystalline oxide (LTPO) combining LTPO and IGZO has the advantages of high resolution, high reaction speed, high brightness, high aperture ratio and small leakage current of the LTPS display panel. For example, the first light-emitting control transistor T1, the data writing transistor T2, the driving transistor T3, the second light-emitting control transistor T6 and the reset transistor T7 can be PMOS transistors; the threshold compensation transistor T4 and the initialization transistor T5 can be at least one PMOS transistor or at least one NMOS transistor. The threshold compensation transistor T4 and the initialization transistor T5 are taken as examples of NMOS transistors in the embodiments of the present application. Based on the type of the display panel, the embodiments of the present application are not limited and can be adjusted according to actual production needs.

[0076] In addition, the threshold compensation transistor T4 and the initialization transistor T5 can be single-gate transistors or double-gate transistors. When double-gate transistors are used, the leakage current of the transistors is reduced and the display effect of the display panel is improved. The threshold compensation transistor T4 and the initialization transistor T5 are taken as examples of top-bottom double-gate transistors in the embodiments of the present application.

[0077] As shown in FIG. 6, the reset transistor T7 and the second light-emitting control transistor T6 are connected to the anode of the light-emitting element, and the connection node of the reset transistor T7, the second light-emitting control transistor T6 and the anode of the light-emitting element is the fourth node N4. The pixel circuit is connected to the anode of the light-emitting element through the fourth node N4. The connection node of the light-emitting element 20 and the first pixel circuit 10 shown in FIG. 4 is the fourth node N4. The anode of the light-emitting element 20 is connected to the fourth node N4 of the corresponding first pixel circuit 10.

[0078] The entire structure of the first pixel circuit 10 is not shown in FIGS. 3 and 4. The first pixel circuit 10 is represented by the fourth node N4, and the first pixel circuit column 10c and the first pixel circuit row 10r are both divided by the fourth node N4.

[0079] Optionally, with reference to FIGS. 3 and 4, in a possible embodiment, the display panel further comprises a plurality of first pixel circuit rows 10r and a plurality of first light emitting element rows 20r; the first pixel circuit row 10r comprises a plurality of first pixel circuits 10 arranged along the second direction Y; the first light emitting element column 20c comprises first color light emitting elements R and second color light emitting elements B arranged alternately along the first direction X, and the first light emitting element row 20r comprises first color light emitting elements R and second color light emitting elements B arranged alternately along the second direction Y; the first color light emitting elements R and the second color light emitting elements B are different in light emitting color; the plurality of first pixel circuits 10 in the same first pixel circuit column 10c are electrically connected with the first color light emitting elements R in at least two first light emitting element columns 20c arranged adjacently along the second direction Y, or are electrically connected with the second color light emitting elements B in at least two first light emitting element columns 20c arranged adjacently along the second direction Y; and the plurality of first pixel circuits 10 in the same first pixel circuit row 10r are electrically connected with the plurality of light emitting elements 20 in the same first light emitting element row 20r.

[0080] As shown in FIGS. 3 and 4, the plurality of first pixel circuits 10 arranged along the second direction Y constitute a first pixel circuit row 10r, and the plurality of first pixel circuit rows 10r are arranged along the first direction X. The light emitting elements 20 different in light emitting color at least comprise first color light emitting elements R and second color light emitting elements B, the first color light emitting elements R and the second color light emitting elements B are arranged alternately in the first light emitting element column 20c, and the first color light emitting elements R and the second color light emitting elements B are arranged alternately in the first light emitting element row 20r, that is, along the first direction X and the second direction Y, the second color light emitting elements B are arranged between any two adjacent first color light emitting elements R, and the second color light emitting elements B are arranged between any two adjacent first color light emitting elements R. This makes the first color light emitting elements R and the second color light emitting elements B uniformly arranged in the display panel, and improves the color mixing effect.

[0081] As shown in FIG. 3 and FIG. 4, the multiple first pixel circuits 10 in the same first pixel circuit column 10c can be electrically connected with the same color light emitting elements 20 in at least two first light emitting element columns 20c arranged adjacent along the second direction Y, that is, the light emitting elements 20 of the same color connected by the multiple first pixel circuits 10 arranged along the first direction X are located in at least two adjacent first light emitting element columns 20c. Thus, the multiple light emitting elements 20 of the same color in the at least two adjacent first light emitting element columns 20c are driven by the first pixel circuit column 10c, and the distance between the light emitting elements 20 connected by the first pixel circuit 10 along the second direction Y is short, which can reduce the length of the connection line between the first pixel circuit 10 and the light emitting element 20 in different columns, and reduce the difficulty of wiring. In addition, in the embodiment, the multiple first pixel circuits 10 arranged along the second direction Y are connected with the multiple light emitting elements in the same first light emitting element row 20r, that is, the multiple first pixel circuits 10 in the same first pixel circuit row 10r are respectively electrically connected with the light emitting elements 20 of different colors in the corresponding first light emitting element row 20r, so that the multiple first pixel circuits 10 in the first pixel circuit row 10r drive the multiple light emitting elements 20 in the corresponding first light emitting element row 20r.

[0082] Referring to FIG. 3 and FIG. 4, when the first light emitting element column 20c includes the first color light emitting element R and the second color light emitting element B, and the first light emitting element row 20r includes the first color light emitting element R and the second color light emitting element B, there are multiple first pixel circuits 10 in part of the first pixel circuit column 10c, which are connected with the first color light emitting element R in the adjacent different first light emitting element column 20c, and there are multiple first pixel circuits 10 in another part of the first pixel circuit column 10c, which are connected with the second color light emitting element B in the adjacent different first light emitting element column 20c, that is, in the same first light emitting element column 20c, the multiple first color light emitting elements R are electrically connected with the first pixel circuits 10 in one first pixel circuit column 10c, and the multiple second color light emitting elements B are electrically connected with the first pixel circuits 10 in another first pixel circuit column 10c. Among the multiple first pixel circuits 10 arranged along the second direction Y (that is, the same first pixel circuit row 10r), there are part of the first pixel circuits 10 connected with the first color light emitting element R, and there are another part of the first pixel circuits 10 connected with the second color light emitting element B.

[0083] For example, in the embodiment shown in FIG. 3 and FIG. 4, along the direction from left to right shown in the figure, the first column of first pixel circuit columns 10c is connected with the multiple first color light emitting elements R in the first column of first light emitting element columns 20c and the second column of first light emitting element columns 20c, and the second column of first pixel circuit columns 10c is connected with the multiple second color light emitting elements B in the first column of first light emitting element columns 20c and the second column of first light emitting element columns 20c.

[0084] Referring back to FIG. 3, the display panel further comprises a plurality of second pixel circuit columns 11c and a plurality of second pixel circuit rows 11r, the second pixel circuit columns 11c comprising a plurality of second pixel circuits 11 arranged along the first direction X, and the second pixel circuit rows 11r comprising a plurality of second pixel circuits 11 arranged along the second direction Y; the second pixel circuit columns 11c are electrically connected to the same data signal line Data; the display panel further comprises a plurality of second light emitting element columns 21c and a plurality of second light emitting element rows 21r, the second light emitting element columns 21c comprising a plurality of third color light emitting elements G arranged along the first direction X, and the second light emitting element rows 21r comprising a plurality of third color light emitting elements G arranged along the second direction Y; the third color light emitting elements G are different from the first color light emitting elements R and the second color light emitting elements B in light emitting color; the plurality of second pixel circuits 11 in the same second pixel circuit column 11c are electrically connected to the plurality of third color light emitting elements G in the same second light emitting element column 21c, and the plurality of second pixel circuits 11 in the same second pixel circuit row 11r are electrically connected to the plurality of third color light emitting elements G in the same second light emitting element row 21r.

[0085] As shown in FIGS. 3 and 4, the pixel circuit further comprises the second pixel circuit 11, which can be arranged in an array along the first direction X and the second direction Y. The plurality of second pixel circuits 11 arranged along the first direction X form the second pixel circuit column 11c, and the plurality of second pixel circuit columns 11c are arranged along the second direction Y. The plurality of second pixel circuits 11 arranged along the second direction Y form the second pixel circuit row 11r, and the plurality of second pixel circuit rows 11r are arranged along the first direction X. The data signal line Data is connected to the plurality of second pixel circuits 11 in the same second pixel circuit column 11c, and the plurality of second pixel circuits 11 arranged along the first direction X are transmitted with data signals by the same data signal line Data.

[0086] Referring back to FIGS. 3 and 4, the light emitting element further comprises the third color light emitting element G, the plurality of third color light emitting elements G arranged along the first direction X form the second light emitting element column 21c, and the plurality of second light emitting element columns 21c are arranged along the second direction Y. The plurality of third color light emitting elements G arranged along the second direction Y form the second light emitting element row 21r, and the plurality of second light emitting element rows 21r are arranged along the second direction Y. When the first color light emitting element R is a red light emitting element, and the second color light emitting element B is a blue light emitting element, the third color light emitting element G can be a green light emitting element, and the combination of the red light emitting element, the blue light emitting element and the green light emitting element realizes full-color display.

[0087] The second pixel circuit column 11c can be arranged corresponding to the second light emitting element column 21c, the plurality of second pixel circuits 11 in the same second pixel circuit column 11c are electrically connected with the plurality of third color light emitting elements G in the same second light emitting element column 21c, and the data signal line Data electrically connected with the second pixel circuit column 11c can only transmit the data signal corresponding to the third color light emitting element G, and there is no voltage jump on the data signal line Data. The second pixel circuit row 11r can be arranged corresponding to the second light emitting element row 21r, so that the plurality of second pixel circuits 11 in the second pixel circuit row 11r drive the plurality of light emitting elements 20 in the corresponding second light emitting element row 21r.

[0088] Continuing to refer to FIG. 3, the first pixel circuit 10 and the second pixel circuit 11 are arranged alternately in the same pixel circuit row. In a row of pixel circuits, the pixel circuit driving the first light emitting element is the first pixel circuit, which constitutes a first pixel circuit row, and the pixel circuit driving the second light emitting element is the second pixel circuit, which constitutes a second pixel circuit row. The first pixel circuit column 10c and the second pixel circuit column 11c are arranged alternately in the second direction, that is, a second pixel circuit column 11c is arranged between two adjacent first pixel circuit columns 10c, and a first pixel circuit column 10c is arranged between two adjacent second pixel circuit columns 11c. The above-mentioned two adjacent first pixel circuit columns 10c can be understood as two first pixel circuit columns 10c with a second pixel circuit column 11c arranged in the middle, rather than two pixel circuit columns directly adjacent to each other.

[0089] Optionally, continuing to refer to FIG. 4, along the first direction X, the first light emitting element row 20r and the second light emitting element row 21r are arranged alternately; along the second direction Y, the first light emitting element column 20c and the second light emitting element column 21c are arranged alternately.

[0090] As shown in FIG. 4, the first light emitting element row 20r and the second light emitting element row 21r are arranged alternately along the first direction X, that is, the second light emitting element row 21r is arranged between two adjacent first light emitting element rows 20r, so that the arrangement of sub-pixels of different colors is more uniform, and the color mixing effect is improved. The first light emitting element column 20c and the second light emitting element column 21c are arranged alternately along the first direction X, that is, the red and blue light emitting element columns and the green light emitting element column are arranged alternately along the second direction Y, which can ensure uniform mixing of red, green and blue light and ensure the image display effect. In the embodiment of the present application, the light emitting elements 20 in at least two first light emitting element columns 20c arranged adjacently do not include the light emitting elements 20 in the second light emitting element column 21c.

[0091] Optionally, with reference back to FIGS. 3 and 4, in some embodiments, a second light emitting element column 21c comprising a plurality of light emitting elements 2 of the same color arranged along the first direction X and different from the light emitting color of the light emitting elements 2 in the first light emitting element column 20c can also be included between any two adjacent first light emitting element columns 20c. For example, the second light emitting element column 21c can comprise a plurality of third color light emitting elements G arranged along the first direction X, with the purpose of making the arrangement of light emitting elements 2 of different colors more uniform and improving the color cast phenomenon.

[0092] FIG. 8 is a partial enlarged structural schematic view of the display panel shown in FIG. 4, which can be combined with reference to FIGS. 3, 4 and 8. At least part of the adjacent first pixel circuit column group 100 and the second pixel circuit column group 101 comprises the ith first pixel circuit column 10c and the (i+1)th first pixel circuit column 10c; at least part of the two adjacent first pixel circuits 10 in the ith first pixel circuit column 10c comprises the ith j first pixel circuit 10i j and the ith (j+1) first pixel circuit 10i (j+1) ; at least part of the two adjacent first pixel circuits 10 in the (i+1)th first pixel circuit column 10c comprises the (i+1)th j first pixel circuit 10(i+1) j and the (i+1)th (j+1) first pixel circuit 10(i+1) (j+1) ; at least part of the two adjacent first light emitting element columns 20c comprises the pth first light emitting element column 20c and the (p+1)th first light emitting element column 20c; at least part of the two adjacent light emitting elements in the pth first light emitting element column 20c comprises the pth q light emitting element 20p q and the pth (q+1) light emitting element 20p (q+1) ; at least part of the two adjacent light emitting elements in the (p+1)th first light emitting element column 20c comprises the (p+1)th q light emitting element 20(p+1) q and the (p+1)th (q+1) light emitting element 20(p+1) (q+1) ; wherein i, j, p and q are positive integers; the ith j first pixel circuit 10i j is electrically connected to the pth q light emitting element 20p q ; the ith (j+1) first pixel circuit 10i (j+1) is electrically connected to the (p+1)th (q+1)the (p+1)th light emitting element 20(p+1) (q+1) the (i+1)th first pixel circuit 10(i+1) j the (p+1)th light emitting element 20(p+1) j the (i+1)th first pixel circuit 10(i+1) q the (p+1)th light emitting element 20(p+1) q the (i+1)th first pixel circuit 10(i+1) (j+1) the (p+1)th light emitting element 20(p+1) (j+1) the (i+1)th first pixel circuit 10(i+1) (q+1) the (p+1)th light emitting element 20p (q+1) the (i+1)th first pixel circuit 10(i+1)

[0093] As shown in FIG. 3 and FIG. 4, the first pixel circuit column 10c in the first pixel circuit column group 100 can be the ith first pixel circuit column 10c, and the first pixel circuit column 10c in the second pixel circuit column group 101 adjacent to the first pixel circuit column group 100 can be the (i+1)th first pixel circuit column 10c. Two adjacent first pixel circuits 10 in the ith first pixel circuit column 10c are the ith j first pixel circuit 10i j and the ith (j+1) first pixel circuit 10i (j+1) Two adjacent first pixel circuits 10 in the (i+1)th first pixel circuit column 10c are the (i+1)th j first pixel circuit 10(i+1) j and the (i+1)th (j+1) first pixel circuit 10(i+1) (j+1) The values of i and j are not limited, and i and j can be equal or not equal. It can be understood that i corresponds to a first pixel circuit column 10c, and j corresponds to a first pixel circuit row 10r. i can be less than the total number of first pixel circuit columns 10c, and j can be less than the total number of first pixel circuit rows 10r.

[0094] Two adjacent first light emitting element columns 20c can be the pth first light emitting element column 20c and the (p+1)th first light emitting element column 20c. Two adjacent light emitting elements in the pth first light emitting element column 20c are the pth q light emitting element 20p q and the pth (q+1) light emitting element 20p (q+1) Two adjacent light emitting elements in the (p+1)th first light emitting element column 20c are the (p+1)th q light emitting element 20(p+1) q and the (p+1)th (q+1) light emitting element 20(p+1) (q+1) The pth q light emitting element 20pq and the (p+1) (q+1) light emitting element (p+1) (q+1) may be a first color light emitting element R, the p (q+1) light emitting element 20p (q+1) and the (p+1) q light emitting element 20(p+1) q may be a second color light emitting element B. The values of p and q are not limited, and p and q can be equal or not equal. p corresponds to a column of first light emitting elements column 20c, and q corresponds to a row of first light emitting elements row 20r. p can be less than the total number of columns of first light emitting elements column 20c, and q can be less than the total number of rows of first light emitting elements row 20r.

[0095] Alternatively, the i-th column of first pixel circuit column 10c can refer to the odd-numbered column of first pixel circuit column 10c of the display panel, the (i+1)-th column of first pixel circuit column 10c can refer to the even-numbered column of first pixel circuit column 10c of the display panel, the j-th row of first pixel circuit row 10r can refer to the odd-numbered row of first pixel circuit row 10r of the display panel, and the (j+1)-th row of first pixel circuit row 10r can refer to the even-numbered row of first pixel circuit row 10r of the display panel. The p-th column of first light emitting element column 20c can refer to the odd-numbered column of first light emitting element column 20c of the display panel, the (p+1)-th column of first light emitting element column 20c can refer to the even-numbered column of first light emitting element column 20c of the display panel, the q-th row of first light emitting element row 20r can refer to the odd-numbered row of first light emitting element row 20r of the display panel, and the (q+1)-th row of first light emitting element row 20r can refer to the even-numbered row of first light emitting element row 20r of the display panel. Alternatively, the i-th column of first pixel circuit column 10c can refer to the even-numbered column of first pixel circuit column 10c of the display panel, the (i+1)-th column of first pixel circuit column 10c can refer to the odd-numbered column of first pixel circuit column 10c of the display panel, the j-th row of first pixel circuit row 10r can refer to the even-numbered row of first pixel circuit row 10r of the display panel, and the (j+1)-th row of first pixel circuit row 10r can refer to the even-numbered row of first pixel circuit row 10r of the display panel. The p-th column of first light emitting element column 20c can refer to the even-numbered column of first light emitting element column 20c of the display panel, the (p+1)-th column of first light emitting element column 20c can refer to the odd-numbered column of first light emitting element column 20c of the display panel, the q-th row of first light emitting element row 20r can refer to the even-numbered row of first light emitting element row 20r of the display panel, and the (q+1)-th row of first light emitting element row 20r can refer to the odd-numbered row of first light emitting element row 20r of the display panel. The embodiments of the present application do not limit whether i, j, p and q are odd or even.

[0096] As shown in FIG. 4 and FIG. 8, the i-th column and j-th first pixel circuit 10 (i.e., the i j th first pixel circuit 10i j ) can be connected to the p-th column and q-th light emitting element (i.e., the p q20p light-emitting elements q Electrical connection; the first pixel circuit 10 of the i-th column (j+1) (i.e., the i-th...) (j+1) The first pixel circuit 10i (j+1) It can be used with the (p+1)th column and (q+1)th light-emitting element (i.e., the (p+1)th... (q+1) 20 (p+1) light-emitting elements (q+1) Electrical connection; the first pixel circuit 10 of the (i+1)th column (j)th pixel (i.e., the (i+1)th pixel) j 10(i+1) first pixel circuits j It can be used with the q-th light-emitting element in the (p+1)-th column (i.e., the (p+1)-th... q 20 (p+1) light-emitting elements q Electrical connection; the first pixel circuit 10 in the (i+1)th column (j+1)th pixel (i.e., the (i+1)th pixel). (j+1) 10(i+1) first pixel circuits (j+1) It can be used with the (q+1)th light-emitting element in the p-th column (i.e., the p-th...) (q+1) 20p light-emitting elements (q+1) Electrical connection. That is, in the first pixel circuit column 10c of the i-th column, part of the first pixel circuit 10 is electrically connected to the first color light-emitting element R in the first light-emitting element column 20c of the p-th column, and another part of the first pixel circuit 10 is electrically connected to the first color light-emitting element R in the first light-emitting element column 20c of the (p+1)-th column. The first pixel circuit 10 connected to the first color light-emitting element R in the first light-emitting element column 20c of the p-th column and the first pixel circuit 10 connected to the first color light-emitting element R in the first light-emitting element column 20c of the (p+1)-th column are arranged alternately along the first direction X. In the (i+1)th column of the first pixel circuit 10c, a portion of the first pixel circuit 10 is electrically connected to the second color light-emitting element B in the pth column of the first light-emitting element 20c, and another portion of the first pixel circuit 10 is electrically connected to the second color light-emitting element B in the (p+1)th column of the first light-emitting element 20c. The first pixel circuit 10 connected to the second color light-emitting element B in the pth column of the first light-emitting element 20c and the first pixel circuit 10 connected to the second color light-emitting element B in the (p+1)th column of the first light-emitting element 20c are arranged alternately along the first direction X. The first color light-emitting elements R in the pth column of the first light-emitting element 20c and the (p+1)th column of the first light-emitting element 20c can be electrically connected to the first pixel circuit 10 in the ith column of the first pixel circuit 10c, and the second color light-emitting elements B in the pth column of the first light-emitting element 20c and the (p+1)th column of the first light-emitting element 20c can be electrically connected to the first pixel circuit 10 in the (i+1)th column of the first pixel circuit 10c.

[0097] For example, when i, j, p and q are equal and all are 1, the first pixel circuit 10 in the first column and the first row can be electrically connected with the first light emitting element (first color light emitting element R) in the first column and the first row, the second pixel circuit 10 in the first column and the second row can be electrically connected with the second light emitting element (first color light emitting element R) in the second column and the second row, the first pixel circuit 10 in the second column and the first row can be electrically connected with the first light emitting element (second color light emitting element B) in the first column and the first row, and the second pixel circuit 10 in the second column and the second row can be electrically connected with the second light emitting element (second color light emitting element B) in the first column and the second row.

[0098] It should be noted that the light emitting elements in the pth column and the (p+1)th column are the light emitting elements in the adjacent first light emitting element column 20c, and do not include the light emitting elements in the second light emitting element column 21c.

[0099] It can be understood that the display panel includes two adjacent first pixel circuit columns (the first alpha pixel circuit column and the first beta pixel circuit column) and two adjacent first light emitting element columns (the first alpha light emitting element column and the first beta light emitting element column), and the first pixel circuit column and the first light emitting element column correspond to each other, and it can also be understood that the first pixel circuit column and the first light emitting element column are overlapped in the thickness direction of the display panel. For example, the first alpha pixel circuit column and the first alpha light emitting element column are overlapped, and the first beta pixel circuit column and the first beta light emitting element column are overlapped. For the first alpha light emitting element column, a part of the light emitting elements in the first alpha light emitting element column are electrically connected with a part of the first pixel circuits in the first alpha pixel circuit column, and another part of the light emitting elements in the first alpha light emitting element column are electrically connected with a part of the first pixel circuits in the first beta pixel circuit column. For the first beta light emitting element column, a part of the light emitting elements in the first beta light emitting element column are electrically connected with another part of the first pixel circuits in the first alpha pixel circuit column, and another part of the light emitting elements in the first beta light emitting element column are electrically connected with another part of the first pixel circuits in the first beta pixel circuit column. For example, the red light emitting elements in the first alpha light emitting element column can be electrically connected with a part of the first pixel circuits in the first alpha pixel circuit column, and the blue light emitting elements in the first alpha light emitting element column are electrically connected with a part of the first pixel circuits in the first beta pixel circuit column; the red light emitting elements in the first beta light emitting element column can be electrically connected with a part of the first pixel circuits in the first alpha pixel circuit column, and the blue light emitting elements in the first beta light emitting element column are electrically connected with another part of the first pixel circuits in the first beta pixel circuit column.

[0100] In other words, for one or several rows of first pixel circuit rows, the light emitting elements thereof are not electrically connected with the pixel circuits directly below, but are electrically connected with other pixel circuits. As can be seen from FIG. 3, the adjacent two light emitting elements in a row of light emitting elements exchange the corresponding first pixel circuits with each other, so that a column of first pixel circuits only drives light emitting elements of one color.

[0101] Fig. 9 is a structural schematic diagram of another display panel provided by the embodiment of the present application, and Fig. 10 is a structural schematic diagram of the section along the A-A' direction of Fig. 9. The luminescent element 20 includes the anode 22, which includes the anode main body part 221 and the anode connecting part 222 connected to each other. The display panel further includes the pixel defining layer 30 and the plurality of pixel openings 31 arranged in the pixel defining layer 30. In the thickness direction Z of the display panel, the anode main body part 221 overlaps the pixel opening 31, and the anode connecting part 222 does not overlap the pixel opening 31. The i (j+1) th first pixel circuit 10i (j+1) is electrically connected to the anode connecting part 222 of the (p+1) (q+1) th luminescent element 20(p+1) (q+1) . The (i+1) (j+1) th first pixel circuit 10(i+1) (j+1) is electrically connected to the anode connecting part 222 of the p (q+1) th luminescent element 20p (q+1) .

[0102] In Fig. 9, only the anode 22 of the luminescent element 20 is shown. The first pixel circuit 10 connected to the luminescent element 20 as indicated in the above embodiment can be the first pixel circuit 10 connected to the anode 22 of the luminescent element 20. Referring to Figs. 8, 9 and 10, the display panel can include the substrate 40, the pixel circuit layer 50, the pixel defining layer 30 and the display functional layer 60. The pixel circuit layer 50 is arranged on one side of the substrate 40, and the above first pixel circuit, the data signal line and the anode 22 of the luminescent element 20 can be located in the pixel circuit layer 50. The pixel defining layer 30 is located on the side of the pixel circuit layer 50 away from the substrate 40, and can be located on the side of the film layer where the anode 22 is located away from the substrate 40. The pixel circuit layer 50 includes the plurality of pixel openings 31, and the pixel openings 31 are arranged correspondingly to the anode 22. In the thickness direction Z of the display panel, the pixel opening 31 overlaps the anode 22 of the luminescent element 20, and the anode 22 can be exposed from the pixel opening 31. The display functional layer 60 can include the hole layer 61, the luminescent layer 62 and the electron layer 63, but is not limited thereto, and the above display functional layer 60 is at least located in the pixel opening 31. The side of the display functional layer 60 away from the film layer where the anode is located can further include the cathode layer (not shown in the figure), which can be arranged integrally or include a plurality of separately arranged cathodes. The cathode layer is arranged to provide electrons to the display functional layer 60, and the anode is arranged to provide holes to the display functional layer 60, and the holes and the electrons combine to emit light.

[0103] With reference back to FIGS. 4, 8-10, the anode 22 can include an anode main portion 221 and an anode connecting portion 222, and the anode main portion 221 is connected with the anode connecting portion 222. The anode main portion 221 overlaps the pixel opening 31 along the display panel thickness direction Z, and the anode connecting portion 222 does not overlap the pixel opening 31, and the anode main portion 221 is electrically connected with the corresponding first pixel circuit 10 through the anode connecting portion 222, so as to realize the electrical connection between the light emitting element and the pixel circuit.

[0104] For example, as shown in FIGS. 8 and 9, the anode main portion 221 of the i j th first pixel circuit 10i j is electrically connected with the anode connecting portion 222 of the p q th light emitting element 20p q , the anode main portion 221 of the i (j+1) th first pixel circuit 10i (j+1) is electrically connected with the anode connecting portion 222 of the (p+1) (q+1) th light emitting element 20(p+1) (q+1) , the anode main portion 221 of the (i+1) j th first pixel circuit 10(i+1) j is electrically connected with the anode connecting portion 222 of the (p+1) q th light emitting element 20(p+1) q , the anode main portion 221 of the (i+1) (j+1) th first pixel circuit 10(i+1) (j+1) is electrically connected with the anode connecting portion 222 of the p (q+1) th light emitting element 20p (q+1) .

[0105] Optionally, as shown in FIGS. 4 and 8, based on the arrangement mode of the pixel circuit and the light emitting element in the display panel, when i and p are equal, and j and q are equal, the distance between the anode main portion 221 of the p q th light emitting element 20p q and the anode main portion 221 of the i j th first pixel circuit 10i j in the plane where the substrate 40 is located (the distance between the two projections in the second direction Y) is less than the distance between the anode main portion 221 of the (p+1) (q+1) th light emitting element 20(p+1) (q+1) and the anode main portion 221 of the i (j+1) th first pixel circuit 10i (j+1) in the plane (the distance between the two projections in the second direction Y). Therefore, the extension length of the anode connecting portion 222 of the p q th light emitting element 20p q in the plane where the substrate 40 is located can be set to be less than the extension length of the anode connecting portion 222 of the (p+1)(q+1) the (p+1)th light emitting element 20(p+1) (q+1) the extension length of the anode connecting portion 222 in the orthogonal projection on the plane where the substrate 40 is located.

[0106] It should be noted that, as shown in FIG. 9 and FIG. 10, the area of the pixel opening 31 in the orthogonal projection on the plane where the substrate 40 is located can be smaller than the area of the anode 22 in the orthogonal projection on the plane, that is, the anode 22 can cover the pixel opening 31 along the thickness direction Z of the display panel. In this arrangement, the projection overlap of the anode 22 and the pixel opening 31, and the part similar to the shape of the pixel opening 31 are all referred to as the anode main portion 221, in other words, in the orthogonal projection pattern on the plane where the substrate 40 is located, the part whose edge surrounds and extends in parallel with the pixel opening 31 can be referred to as the anode main portion 221. The anode connecting portion 222 generally refers to the part connected with the anode main portion 221 and having a width much smaller than that of the anode main portion 221. Taking the anode shown in the figures as an example, the regular rhombus part can be referred to as the anode main portion 221, and the part connected with the edge of the rhombus and extending outward of the edge of the rhombus is the anode connecting portion 222.

[0107] The relative positional relationship between the anode main portion 221 and the anode connecting portion 222 can be designed by those skilled in the art according to actual needs, and the embodiments of the present application do not limit this. Several different design schemes of the anode connecting portion 222 will be introduced below in combination with several embodiments.

[0108] For example, still referring to FIG. 4 and FIG. 9, in some embodiments, the anode connecting portion 222 of the (p+1)th light emitting element 20(p+1) q is located on the side of the anode main portion 221 of the (p+1)th light emitting element 20(p+1) q close to the (i+1)th column of first pixel circuit columns 10c; the anode connecting portion 222 of the pth light emitting element 20p (q+1) is located on the side of the anode main portion 221 of the pth light emitting element 20p (q+1) close to the (i+1)th column of first pixel circuit columns 10c.

[0109] As described in the above embodiments, the anode connecting portion 222 of the (p+1)th light emitting element 20(p+1) q is located on the side of the anode main portion 221 of the (p+1)th light emitting element 20(p+1) q close to the (i+1)th column of first pixel circuit columns 10c; and the anode connecting portion 222 of the pth light emitting element 20p (q+1) is located on the side of the anode main portion 221 of the pth light emitting element 20p (q+1)The second color light emitting element B in the pth first light emitting element column 20c and the (p+1)th first light emitting element column 20c can be electrically connected with the first pixel circuit 10 in the (i+1)th first pixel circuit column 10c. The anode main body part 221 of the second color light emitting element B in the pth first light emitting element column 20c and the (p+1)th first light emitting element column 20c can be located on both sides of the (i+1)th first pixel circuit column 10c along the second direction Y, in other words, the anode main body part 221 of the second color light emitting element B in the pth first light emitting element column 20c and the (p+1)th first light emitting element column 20c is located on both sides of the plurality of fourth nodes N4 in the (i+1)th first pixel circuit column 10c.

[0110] On this basis, as shown in FIG. 4 and FIG. 9, in the embodiment, the anode connecting part 222 of the (p+1)th first light emitting element 20(p+1)q can be located on the side of the anode main body part 221 of the (p+1)th first light emitting element 20(p+1)q close to the (i+1)th first pixel circuit column 10c; the anode connecting part 222 of the pth first light emitting element 20p(q+1) can be located on the side of the anode main body part 221 of the pth first light emitting element 20p(q+1) close to the (i+1)th first pixel circuit column 10c. So that the anode connecting part 222 of the second color light emitting element B in the pth first light emitting element column 20c extends towards the direction close to the (p+1)th first light emitting element column 20c and is connected with the fourth node N4 of the first pixel circuit 10 in the (i+1)th first pixel circuit column 10c; the anode connecting part 222 of the second color light emitting element B in the (p+1)th first light emitting element column 20c extends towards the direction close to the pth first light emitting element column 20c and is connected with the fourth node N4 of the first pixel circuit 10 in the (i+1)th first pixel circuit column 10c. In this arrangement, the fourth node N4 of the (p+1)th first light emitting element 20(p+1) and the (i+1)th first pixel circuit 10(i+1) connected therewith are closer in the second direction Y, the fourth node N4 of the pth first light emitting element 20p and the (i+1)th first pixel circuit 10(i+1) connected therewith are closer in the second direction Y, which can reduce the length of the anode connecting part 222 of the light emitting element, and facilitate the connection of the light emitting element and the corresponding first pixel circuit 10. q q (q+1) (q+1) q q j j (q+1) (q+1) (j+1) (j+1)

[0111] ​​​​​​​​​​​​For example, as shown in Figure 4, along the left-to-right direction in the figure, the anode connection portion 222 of the first light-emitting element in the second column is located on the side of its anode body portion 221 close to the first pixel circuit 10c in the second column and extends to the first pixel circuit 10 in the second column. The anode connection portion 222 of the second light-emitting element in the first column is located on the side of its anode body portion 221 close to the first pixel circuit 10c in the second column and extends to the second pixel circuit 10 in the second column.

[0112] For example, Figure 11 is a schematic diagram of another display panel structure provided in an embodiment of this application, and Figure 12 is a partially enlarged schematic diagram of the display panel shown in Figure 11. Referring to Figures 11 and 12, the (p+1)th... (q+1) 20 (p+1) light-emitting elements (q+1) The anode connection portion 222 is located on the side of its anode body portion 221 near the i-th column of the first pixel circuit column 10c; the p-th column of the first pixel circuit column 10c is located on the side of its anode body portion 221 near the i-th column of the first pixel circuit column 10c. (q+1) 20p light-emitting elements (q+1) The anode connection portion 222 is located on the side of its anode body portion 221 near the (i+1)th column of the first pixel circuit column 10c.

[0113] p (q+1) 20p light-emitting elements (q+1) and (p+1)th (q+1) 20 (p+1) light-emitting elements (q+1) Both are located in the p-th column of the first light-emitting element column 20c, and are two adjacent light-emitting elements 20 in the p-th column of the first light-emitting element column 20c. In the embodiments shown in Figures 11 and 12, the second color light-emitting element B in the first light-emitting element column 20c can be the same as in the embodiments shown in Figures 4 and 8, and will not be described again here. As shown in Figures 11 and 12, in this embodiment, the anode connection portion 222 of the first color light-emitting element R in the (p+1)-th column of the first light-emitting element column 20c is located on the side of its anode body portion 221 close to the i-th column of the first pixel circuit column 10c, that is, the (p+1)-th column. (q+1) 20 (p+1) light-emitting elements (q+1) The anode connection portion 222 is located on the side of its anode main body portion 221 near the i-th column of the first pixel circuit column 10c, (p+1) (q+1) 20 (p+1) light-emitting elements (q+1) Anode connection 222 towards the i-th (j+1) The first pixel circuit 10i (j+1) Extend and with the i-th (j+1) The first pixel circuit 10i (j+1) The fourth node N4 is connected.

[0114] In this configuration, the (p+1)th... (q+1) 20 (p+1) light-emitting elements(q+1) Anode connecting part 222 of the pth light emitting element 20p and the (p+1)th light emitting element 20(p+1) (q+1) Anode connecting part 222 of the pth light emitting element 20p and the (p+1)th light emitting element 20(p+1) (q+1) Anode connecting part 222 of the pth light emitting element 20p and the (p+1)th light emitting element 20(p+1)

[0115] Fig. 13 is a structural schematic diagram of still another display panel provided by an embodiment of the present application, Fig. 14 is a partial enlarged structural schematic diagram of the display panel shown in Fig. 13, Fig. 15 is a structural schematic diagram of yet another display panel provided by an embodiment of the present application, and Fig. 16 is a partial enlarged structural schematic diagram of the display panel shown in Fig. 15. In possible embodiments, as shown in Figs. 13 and 14, the (p+1)th light emitting element 20(p+1) (q+1) Anode connecting part 222 of the pth light emitting element 20p and the (p+1)th light emitting element 20(p+1) (q+1) Anode connecting part 222 of the pth light emitting element 20p and the (p+1)th light emitting element 20(p+1) (j+1) Anode connecting part 222 of the pth light emitting element 20p and the (p+1)th light emitting element 20(p+1) (j+1) Anode connecting part 222 of the pth light emitting element 20p and the (p+1)th light emitting element 20(p+1) (q+1) Anode connecting part 222 of the pth light emitting element 20p and the (p+1)th light emitting element 20(p+1) (q+1) Anode connecting part 222 of the pth light emitting element 20p and the (p+1)th light emitting element 20(p+1) (q+1) Anode connecting part 222 of the pth light emitting element 20p and the (p+1)th light emitting element 20(p+1) (q+1) Anode connecting part 222 of the pth light emitting element 20p and the (p+1)th light emitting element 20(p+1) (q+1) Anode connecting part 222 of the pth light emitting element 20p and the (p+1)th light emitting element 20(p+1) (q+1) Anode connecting part 222 of the pth light emitting element 20p and the (p+1)th light emitting element 20(p+1) (j+1) Anode connecting part 222 of the pth light emitting element 20p and the (p+1)th light emitting element 20(p+1) (j+1) Anode connecting part 222 of the pth light emitting element 20p and the (p+1)th light emitting element 20(p+1) (q+1) Anode connecting part 222 of the pth light emitting element 20p and the (p+1)th light emitting element 20(p+1) (q+1) Anode connecting part 222 of the pth light emitting element 20p and the (p+1)th light emitting element 20(p+1) (q+1) Anode connecting part 222 of the pth light emitting element 20p and the (p+1)th light emitting element 20(p+1) (q+1)The anode connection portion 222 includes a seventh end portion 2227 connected to its anode body portion 221 and an eighth end portion 2228 connected to the first pixel circuit 10. The seventh end portion 2227 is located on the side of its anode body portion 221 away from the (i+1)th column of the first pixel circuit column 10c.

[0116] As described in the above embodiments, the first color light-emitting element R in the (p+1)th column of the first light-emitting element column 20c is connected to the first pixel circuit 10 in the i-th column of the first pixel circuit column 10c, for example, in the (p+1)th column. (q+1) 20 (p+1) light-emitting elements (q+1) With the i-th (j+1) The first pixel circuit 10i (j+1) Connect, p+1th. (q+1) 20 (p+1) light-emitting elements (q+1) The anode connection portion 222 can extend along the second direction Y, and thus connect with the i-th... (j+1) The first pixel circuit 10i (j+1) The fourth node N4 is connected.

[0117] In the embodiments shown in Figures 13 and 14, the (p+1)th... (q+1) 20 (p+1) light-emitting elements (q+1) The anode connection portion 222 includes a first end portion 2221 and a second end portion 2222, wherein the first end portion 2221 is close to the (p+1)th end portion in the direction of the plane where the substrate 40 is located. (q+1) 20 (p+1) light-emitting elements (q+1) The anode body portion 221 is connected to the anode body portion 221; the second end portion 2222 extends towards the i-th (j+1) The first pixel circuit 10i (j+1) The fourth node N4 extends and connects to the fourth node N4. The first end 2221 is located on the side of the anode body 221 away from the i-th column of the first pixel circuit column 10c, that is, the first end 2221 is located on the side of the anode body 221 away from the p-th column of the first pixel circuit column 10c. (q+1) 20p light-emitting elements (q+1) One side can be interpreted as the (p+1)th side. (q+1) 20 (p+1) light-emitting elements (q+1) The anode connection portion 222 first extends a certain length away from the first pixel circuit column 10c via the first end portion 2221, and then connects to the fourth node N4 via the second end portion 2222. (q+1) 20p light-emitting elements (q+1) The anode connection portion 222 includes a third end portion 2223 and a fourth end portion 2224. The third end portion 2223 is close to the anode body portion 221 in the direction of the plane where the substrate 40 is located and is adjacent to the p-th end portion 2224. (q+1) 20p light-emitting elements(q+1) The anode body 221 is connected; the fourth end 2224 is connected to the (i+1)th... (j+1) 10(i+1) first pixel circuits (j+1) The fourth node N4 extends and connects to the fourth node N4. The third end 2223 and the fourth end 2224 can be located on the side of the anode body 221 near the (i+1)th column of the first pixel circuit column 10c.

[0118] In the settings shown in Figures 13 and 14, the p-th (q+1) 20p light-emitting elements (q+1) The connecting end portion of the anode connection portion 222 near the anode body portion 221, and the (p+1)th... (q+1) 20 (p+1) light-emitting elements (q+1) The connecting ends of the anode connection portion 222 near the anode body portion 221 are respectively located on the same side of their respective anode body portions 221 (e.g., the right side in the figure). That is, in the first color light-emitting element R and the second color light-emitting element B adjacent along the second direction Y, the anode connection portions 222 near their respective anode body portions 221 have the same orientation. This avoids the (p+1)th... (q+1) 20 (p+1) light-emitting elements (q+1) The first end 2221 and the pth (q+1) 20p light-emitting elements (q+1) When the second end 2222 is laid between the anode body 221 of the two, the problem of increasing the difficulty of pulling the wire due to limited space is solved, so that both the first end 2221 and the second end 2222 have a large laying space.

[0119] In the embodiments shown in Figures 15 and 16, the (p+1)th... (q+1) 20 (p+1) light-emitting elements (q+1) The anode connection portion 222 includes a fifth end portion 2225 and a sixth end portion 2226, wherein the fifth end portion 2225 is close to the (p+1)th end portion in the direction of the plane where the substrate 40 is located. (q+1) 20 (p+1) light-emitting elements (q+1) The anode body 221 is connected to the anode body 221; the sixth end 2226 is directed towards the i-th (j+1) The first pixel circuit 10i (j+1) The fourth node N4 extends and connects to the fourth node N4. The fifth end 2225 is located on the side of the anode body 221 near the i-th column of the first pixel circuit column 10c, that is, the fifth end 2225 is located on the side of the anode body 221 near the p-th column of the first pixel circuit column 10c. (q+1) 20p light-emitting elements (q+1) One side can be interpreted as the (p+1)th side. (q+1) 20 (p+1) light-emitting elements(q+1) The anode connection portion 222 first extends a certain length towards the side near the first pixel circuit column 10c of the i-th column via the fifth end portion 2225, and then connects to the fourth node N4 via the sixth end portion 2226. (q+1) 20p light-emitting elements (q+1) The anode connection portion 222 includes a seventh end portion 2227 and an eighth end portion 2228. The seventh end portion 2227 is close to and connected to the anode main body portion 221 in the direction of the plane where the substrate 40 is located; the eighth end portion 2228 is connected to the (i+1)th end portion 2228. (j+1) 10(i+1) first pixel circuits (j+1) The fourth node N4 extends and connects to the fourth node N4. The seventh end 2227 may be located on the side of the anode body 221 away from the (i+1)th column of the first pixel circuit column 10c, that is, the seventh end 2227 is located on the side of the anode body 221 away from the (p+1)th column of the first pixel circuit column 10c. (q+1) 20 (p+1) light-emitting elements (q+1) One side of the eighth end 2228. One end of the eighth end 2228 is connected to the seventh end 2227, and the other end of the eighth end 2228 is connected to the (i+1)th end. (j+1) 10(i+1) first pixel circuits (j+1) Extend and connect to the fourth node N4.

[0120] In the settings shown in Figures 15 and 16, the p-th... (q+1) 20p light-emitting elements (q+1) The connecting end portion of the anode connection portion 222 near the anode body portion 221, and the (p+1)th... (q+1) 20 (p+1) light-emitting elements (q+1) In the anode connection portion 222, the connection ends near the anode body portion 221 are located on the same side of their respective anode body portions 221 (e.g., the left side in the figure). In the adjacent first color light-emitting elements R and second color light-emitting elements B along the second direction Y, the orientation of the anode connection portions 222 near their respective anode body portions 221 is the same. This also ensures that both the first end portion 2221 and the second end portion 2222 have ample arrangement space. Furthermore, in the embodiments shown in Figures 15 and 16, the extension lengths of the anode connection portions 222 of the first color light-emitting element R and the second color light-emitting element B in the (p+1)th column of the first light-emitting element column 20c in the second direction Y are close, for example, both greater than or equal to the extension length of the anode body portion 221 of the second color light-emitting element B in the second direction Y. This ensures that the wire lengths between the light-emitting elements of different colors in the same column of the first light-emitting element column 20c and the corresponding first pixel circuit 10 are consistent, and the impedances on the signal lines are relatively close.

[0121] In the embodiments shown in Figures 4, 8, and 11 to 16 above, the connection method between the anode 22 of the plurality of first color light-emitting elements R in the first light-emitting element row 20r of the qth row and the corresponding first pixel circuit 10 can be the same, and the connection method between the anode 22 of the plurality of second color light-emitting elements B in the first light-emitting element row 20r of the qth row and the corresponding first pixel circuit 10 can be the same, and both are the same as in the related art. There is no need to change the connection method between the first color light-emitting elements R and the second color light-emitting elements B in the first light-emitting element row 20r of the qth row and the corresponding first pixel circuit 10, which can simplify the process.

[0122] Referring to Figures 4, 8, and 11-16, the display panel also includes a substrate 40 and a virtual connection structure 223; the orthographic projection of the virtual connection structure 223 onto the plane of the substrate 40 is located at the p-th position. q 20p light-emitting elements q The anode main body 221 is projected onto the side of the plane containing the substrate 40; and / or, the virtual connection structure 223 is projected onto the plane containing the substrate 40 at the (p+1)th position. q 20 (p+1) light-emitting elements q The anode body 221 is on the side of the plane where the substrate 40 is located, as projected.

[0123] Referring again to the embodiments shown in Figures 3, 4, 8, and 11-16, the light-emitting elements 20 in different columns of the first light-emitting element row 20r in the qth row are respectively connected to the first pixel circuits 10 in different columns of the first pixel circuit row 10r in the jth row. When q = j and p = i, the distance between the light-emitting elements 20 in the first light-emitting element row 20r in the qth row and the corresponding connected first pixel circuits 10 in the plane direction of the substrate 40 is small, and the overall extension length of the anode connection portion 222 in the first light-emitting element row 20r in the qth row is small. However, at least some columns of the light-emitting elements 20 in the first light-emitting element row 20r in the (q+1)th row need to be connected to the first pixel circuits 10 in every other column, for example, in the (p+1)th row. (q+1) The light-emitting element 20(p+1)(q+1) and the i-th (j+1) The first pixel circuit 10i (j+1) The connection results in a larger overall extension length of the anode connection portion 222 in the first light-emitting element row 20r of row (q+1).

[0124] When the length of the anode connecting part 222 in the odd row and the even row is different, it can cause the difference of the wire impedance (or RC Loading) of the odd row and the even row, and the difference of the light reflectivity of the anode connecting part 222, thereby affecting the signal transmission and causing the visual effect problem. Based on this, the embodiment of the present application proposes that a virtual connection structure 223 can be added in the display panel, and the orthographic projection of the virtual connection structure 223 on the plane where the substrate 40 is located can be close to the first light emitting element row 20r of the qth row.

[0125] For example, in some embodiments, as shown in FIGS. 3, 4, 8, 11 and 12, the orthographic projection of the virtual connection structure 223 on the plane where the substrate is located is located on one side of the orthographic projection of the anode main part 221 of the pth light emitting element 20p on the plane where the substrate is located, thereby improving the consistency of the wire impedance of the odd row and the even row, and ensuring that the light reflectivity of the anode connecting part 222 of the odd row and the even row is close, avoiding the situation that the display panel display effect is not balanced. q q For example, in some embodiments, as shown in FIGS. 3, 4, 8, 11 and 12, the orthographic projection of the virtual connection structure 223 on the plane where the substrate is located is located on one side of the orthographic projection of the pth light emitting element 20p on the plane where the substrate is located, thereby improving the consistency of the wire impedance of the odd row and the even row, and ensuring that the light reflectivity of the anode connecting part 222 of the odd row and the even row is close, avoiding the situation that the display panel display effect is not balanced.

[0126] For example, in some embodiments, as shown in FIGS. 3, 4, 8, 11 and 12, the orthographic projection of the virtual connection structure 223 on the plane where the substrate is located is located on one side of the orthographic projection of the pth light emitting element 20p on the plane where the substrate is located, thereby improving the consistency of the wire impedance of the odd row and the even row, and ensuring that the light reflectivity of the anode connecting part 222 of the odd row and the even row is close, avoiding the situation that the display panel display effect is not balanced. q q For example, in some embodiments, as shown in FIGS. 3, 4, 8, 11 and 12, the orthographic projection of the virtual connection structure 223 on the plane where the substrate is located is located on one side of the orthographic projection of the pth light emitting element 20p on the plane where the substrate is located, thereby improving the consistency of the wire impedance of the odd row and the even row, and ensuring that the light reflectivity of the anode connecting part 222 of the odd row and the even row is close, avoiding the situation that the display panel display effect is not balanced.

[0127] For example, in some embodiments, as shown in FIGS. 3, 4, 8, 11 and 12, the orthographic projection of the virtual connection structure 223 on the plane where the substrate is located is located on one side of the orthographic projection of the pth light emitting element 20p on the plane where the substrate is located, thereby improving the consistency of the wire impedance of the odd row and the even row, and ensuring that the light reflectivity of the anode connecting part 222 of the odd row and the even row is close, avoiding the situation that the display panel display effect is not balanced. q q For example, in some embodiments, as shown in FIGS. 3, 4, 8, 11 and 12, the orthographic projection of the virtual connection structure 223 on the plane where the substrate is located is located on one side of the orthographic projection of the pth light emitting element 20p on the plane where the substrate is located, thereby improving the consistency of the wire impedance of the odd row and the even row, and ensuring that the light reflectivity of the anode connecting part 222 of the odd row and the even row is close, avoiding the situation that the display panel display effect is not balanced. q q For example, in some embodiments, as shown in FIGS. 3, 4, 8, 11 and 12, the orthographic projection of the virtual connection structure 223 on the plane where the substrate is located is located on one side of the orthographic projection of the pth light emitting element 20p on the plane where the substrate is located, thereby improving the consistency of the wire impedance of the odd row and the even row, and ensuring that the light reflectivity of the anode connecting part 222 of the odd row and the even row is close, avoiding the situation that the display panel display effect is not balanced.

[0128] For example, in some embodiments, as shown in FIGS. 3, 4, 8, 11 and 12, the orthographic projection of the virtual connection structure 223 on the plane where the substrate is located is located on one side of the orthographic projection of the pth light emitting element 20p on the plane where the substrate is located, thereby improving the consistency of the wire impedance of the odd row and the even row, and ensuring that the light reflectivity of the anode connecting part 222 of the odd row and the even row is close, avoiding the situation that the display panel display effect is not balanced. q q For example, in some embodiments, as shown in FIGS. 3, 4, 8, 11 and 12, the orthographic projection of the virtual connection structure 223 on the plane where the substrate is located is located on one side of the orthographic projection of the pth light emitting element 20p on the plane where the substrate is located, thereby improving the consistency of the wire impedance of the odd row and the even row, and ensuring that the light reflectivity of the anode connecting part 222 of the odd row and the even row is close, avoiding the situation that the display panel display effect is not balanced. ​​​​​

[0129] p q There is a break between the orthographic projection of the anode body of each light-emitting element onto the plane of the substrate and the orthographic projection of the virtual connection structure 223 onto the plane of the substrate. This can be understood as the p-th... q The anode body of each light-emitting element is insulated from the virtual connection structure 223; the (p+1)th... q There is a break between the orthographic projection of the anode body of the light-emitting element onto the plane of the substrate and the orthographic projection of the virtual connection structure 223 onto the plane of the substrate, which can be understood as the (p+1)th... q The anode body of each light-emitting element is insulated from the virtual connection structure 223. In this case, the virtual connection structure 223 ensures that the distribution density or coverage area of ​​the metal structure between different rows of pixel circuits is the same, that the light transmittance and reflectance between different rows of pixel circuits are the same or similar, and that the light transmission effect and visual effect of the display panel are the same or similar.

[0130] Referring to Figures 4 and 11, the p-th q The anode body of the first light-emitting element is electrically connected to the virtual connection structure 223; and / or, the (p+1)th... q The anode body of each light-emitting element is electrically connected to the virtual connection structure 223.

[0131] p q The anode body of the first light-emitting element is electrically connected to the virtual connection structure 223, but the virtual connection structure 223 is not electrically connected to the first pixel circuit, thus avoiding the connection of two first pixel circuits to the same anode, which could lead to display abnormalities; at the same time, the (p+1)th... q The anode body of each light-emitting element is electrically connected to the virtual connection structure 223, but the virtual connection structure 223 is not electrically connected to the first pixel circuit, thus avoiding the connection of two first pixel circuits to the same anode, which could lead to display abnormalities. q The anode body of the light-emitting element is electrically connected to the virtual connection structure 223, and / or, the (p+1)th... q The anode body of each light-emitting element is electrically connected to the virtual connection structure 223. This not only ensures that the distribution density or coverage area of ​​the metal structure between different rows of pixel circuits is the same, and that the light transmittance and reflectance between different rows of pixel circuits are the same or similar, and that the light transmission effect and visual effect of the display panel are the same or similar, but also ensures that the trace impedance (or RC Loading) of the anode connection part of the light-emitting elements of the same color in different positions is consistent or nearly consistent, and ensures that the display effect of the light-emitting elements of the same color in different positions is consistent or nearly consistent, avoiding display differences between light-emitting elements of the same color in different positions, and ensuring good overall display balance of the display panel.

[0132] The shape of the virtual connection structure 223 is similar to that of the anode connection part 222, the length of the virtual connection structure 223 is L1, the width is D1, the length of the anode connection part 222 is L2, and the width is D2, wherein |L1-L2| / L1≤20%, |D1-D2| / D1≤20%. As shown in FIGS. 4, 9-12, the virtual connection structure 223 and the anode connection part 222 can be set to have the same or similar shape, length, and width, and the like, to further improve the impedance consistency of the odd and even row pixel wires.

[0133] Optionally, referring to FIGS. 4, 8, 11, and 12, the virtual connection structure 223 and the anode connection part 222 are staggered in the first direction X and / or the second direction Y.

[0134] As shown in FIGS. 4, 8, 11, and 12, the anode connection part 222 of the (p+1) (q+1) th light emitting element 20(p+1) (q+1) (R, first color light emitting element) has a relatively long extension length, and in order to balance the impedance of the anode connection part 222, the virtual connection structure 223 can be set to overlap or have a break with the first color light emitting element R in the qth row of first light emitting element rows 20r. The virtual connection structure 223 and the anode connection part 222 are located in different first light emitting element rows 20r, and thus are staggered along the second direction Y.

[0135] Based on the scheme that the first color light emitting element R and the second color light emitting element B are alternately arranged in the first direction X and the second direction Y, in the qth row of first light emitting element rows 20r, the first color light emitting element R closest to the (p+1) (q+1) th light emitting element 20(p+1) (q+1) is the (p+2) q th light emitting element (the (p+2)th row qth column light emitting element in the figure), and thus the virtual connection structure 223 can be set to overlap the orthographic projection of the (p+2) (q) th light emitting element and have the same shape, length, and width as the anode connection part 222 of the (p+1) (q+1) th light emitting element 20(p+1) (q+1) . Since the (p+2) q th light emitting element and the (p+1) (q+1) th light emitting element 20(p+1) (q+1) are staggered in the first direction X, the virtual connection structure 223 and the anode connection part 222 are staggered in the first direction X. In this way, the virtual connection structure 223 and the anode connection part 222 are evenly distributed in the display panel, which improves the impedance consistency while ensuring the display effect.

[0136] In other words, there is a gap between the orthographic projections of two adjacent anode connection portions 222 on the substrate, and the orthographic projection of the virtual connection structure 223 on the substrate and the gap overlap along the first direction; or, along the first direction, the orthographic projection of the virtual connection structure 223 on the substrate is located between the orthographic projections of two adjacent anode connection portions 222 on the substrate.

[0137] Optionally, in some embodiments, the virtual connection structure 223 and the anode connection portion 222 are disposed in the same layer. In this way, the virtual connection structure 223 and the anode connection portion 222 can be fabricated in the same process, which simplifies the process and ensures the accuracy of the formation position of the virtual connection structure 223 and the anode connection portion 222, thus ensuring the impedance balance effect of the virtual connection structure 223 on the anode connection portion 222.

[0138] In summary, the above embodiments have been described using the example of the first pixel circuit group 100 including one column of first pixel circuit 10c and the second pixel circuit group 101 including one column of first pixel circuit 10c. It can be understood that the first pixel circuit group 100 may also include at least two columns of first pixel circuit 10c, and the second pixel circuit group 101 may also include at least two columns of first pixel circuit 10c. This situation will be described below.

[0139] In some embodiments, as shown in Figures 27 and 37, the virtual connection structure 223 and the anode body are disposed on the same layer.

[0140] In other embodiments, as shown in Figures 39, 41 and 42, the virtual connection structure 223 and the anode body are arranged in different layers.

[0141] Figure 17 is a schematic diagram of another display panel structure provided in an embodiment of this application. Referring to Figure 17, at least partially adjacent first pixel circuit group 100 and second pixel circuit group 101 include the h-th column first pixel circuit group 10c, the (h+1)-th column first pixel circuit group 10c, the (h+2)-th column first pixel circuit group 10c, and the (h+3)-th column first pixel circuit group 10c; at least partially adjacent two first pixel circuits 10 in the h-th column first pixel circuit group 10c include the h-th column first pixel circuit group 10c. k The first pixel circuit 10 and the h-th (k+1) A first pixel circuit 10; two first pixel circuits 10 that are at least partially adjacent in the (h+1)th column of first pixel circuits 10c include the (h+1)th column. k The first pixel circuit 10 and the (h+1)th pixel circuit (k+1) In a first pixel circuit 10, at least two partially adjacent first pixel circuits 10 in the (h+2)th column of the first pixel circuit column 10c include the (h+2)th column. k The first pixel circuit 10 and the (h+2)th pixel circuit(k+1) A first pixel circuit 10; at least two partially adjacent first pixel circuits 10 in the (h+3)th column of first pixel circuits 10c include the (h+3)th column. k The first pixel circuit 10 and the (h+3)th pixel circuit (k+1) A first pixel circuit 10; at least partially adjacent four columns of first light-emitting elements 20c include the m-th column of first light-emitting elements 20c, the (m+1)-th column of first light-emitting elements 20c, the (m+2)-th column of first light-emitting elements 20c, and the (m+3)-th column of first light-emitting elements 20c; at least two partially adjacent light-emitting elements in the m-th column of first light-emitting elements 20c include the m-th... n The first light-emitting element and the mth (n+1) The first light-emitting element; in the (m+1)th column, at least two partially adjacent light-emitting elements in the first light-emitting element column 20c include the (m+1)th light-emitting element. n The (m+1)th light-emitting element and the (m+1)th light-emitting element (n+1) The first light-emitting element in column (m+2) of column 20c consists of at least two partially adjacent light-emitting elements, including the (m+2)th light-emitting element. n The first light-emitting element and the (m+2)th light-emitting element (n+1) The first light-emitting element in column (m+3) of column 20c consists of at least two partially adjacent light-emitting elements, including the (m+3)th light-emitting element. n The first light-emitting element and the (m+3)th light-emitting element (n+1) The h-th light-emitting element; where h, k, m, and n are all positive integers; the h-th... k The first pixel circuit 10 and the mth pixel circuit n The first light-emitting element is electrically connected; the hth (k+1) The first pixel circuit 10 and the (m+1)th pixel circuit (n+1) The first light-emitting element is electrically connected; the (h+1)th... k The first pixel circuit 10 and the (m+1)th pixel circuit n The first light-emitting element is electrically connected; the (h+1)th... (k+1) The first pixel circuit 10 and the mth pixel circuit (n+1) The first light-emitting element is electrically connected; the (h+2)th... k The first pixel circuit 10 and the (m+3)th pixel circuit n The first light-emitting element is electrically connected; the (h+2)th... (k+1) The first pixel circuit 10 and the (m+2)th pixel circuit (n+1) The first light-emitting element is electrically connected; the (h+3)th... k The first pixel circuit 10 and the (m+2)th pixel circuit n The first light-emitting element is electrically connected; the (h+3)th... (k+1) The first pixel circuit 10 and the (m+3)th pixel circuit (n+1) Each light-emitting element is electrically connected.

[0142] As shown in FIG. 17, the hth column of first pixel circuit rows 10c, the (h+1)th column of first pixel circuit rows 10c, the (h+2)th column of first pixel circuit rows 10c, and the (h+3)th column of first pixel circuit rows 10c are arranged along the second direction Y to form a repeating unit. Two adjacent first pixel circuits 10 in the hth column of first pixel circuit rows 10c are the hth first pixel circuit 10 and the (h+1)th first pixel circuit 10, respectively. Two adjacent first pixel circuits 10 in the (h+1)th column of first pixel circuit rows 10c are the (h+1)th first pixel circuit 10 and the (h+2)th first pixel circuit 10, respectively. Two adjacent first pixel circuits 10 in the (h+2)th column of first pixel circuit rows 10c are the (h+2)th first pixel circuit 10 and the (h+3)th first pixel circuit 10, respectively. Two adjacent first pixel circuits 10 in the (h+3)th column of first pixel circuit rows 10c are the (h+3)th first pixel circuit 10 and the (h+4)th first pixel circuit 10, respectively. The values of h and k are not limited, and h and k can be equal or different. It can be understood that h corresponds to a column of first pixel circuit rows 10c, and k corresponds to a row of first pixel circuit rows 10r. h can be less than the total number of columns of first pixel circuit rows 10c, and k can be less than the total number of rows of first pixel circuit rows 10r. k (k+1) k (k+1) k (k+1) k (k+1)

[0143] The four adjacent columns of first light emitting element columns 20c can be the mth column of first light emitting element columns 20c, the (m+1)th column of first light emitting element columns 20c, the (m+2)th column of first light emitting element columns 20c, and the (m+3)th column of first light emitting element columns 20c. Two adjacent light emitting elements in the mth column of first light emitting element columns 20c can be the mth light emitting element and the (m+1)th light emitting element, respectively. Two adjacent light emitting elements in the (m+1)th column of first light emitting element columns 20c can be the (m+1)th light emitting element and the (m+2)th light emitting element, respectively. Two adjacent light emitting elements in the (m+2)th column of first light emitting element columns 20c can be the (m+2)th light emitting element and the (m+3)th light emitting element, respectively. Two adjacent light emitting elements in the (m+3)th column of first light emitting element columns 20c can be the (m+3)th light emitting element and the (m+4)th light emitting element, respectively. n (n+1) n (n+1) n (n+1) n (n+1) ​​​​​​​​​​​​​​​There are 10 light-emitting elements. The values ​​of m and n are not limited and can be equal or unequal. It can be understood that m corresponds to a column 20c of the first light-emitting elements and n corresponds to a row 20r of the first light-emitting elements. m can be less than the total number of columns 20c of the first light-emitting elements and n can be less than the total number of rows 20r of the first light-emitting elements.

[0144] Optionally, the first pixel circuit column 10c in column h and the first pixel circuit column 10c in column (h+2) can refer to the first pixel circuit column 10c in odd-numbered (or even-numbered) columns of the display panel, and the first pixel circuit column 10c in column (h+1) and the first pixel circuit column 10c in column (h+3) can refer to the first pixel circuit column 10c in even-numbered (or odd-numbered) columns of the display panel. The first pixel circuit row 10r in row k can refer to the first pixel circuit row 10r in odd-numbered (or even-numbered) rows of the display panel, and the first pixel circuit row 10r in row (k+1) can refer to the first pixel circuit row 10r in even-numbered (or odd-numbered) rows of the display panel. The first light-emitting element column 20c in column m and column (m+2) can refer to the first light-emitting element column 20c in the odd-numbered (or even-numbered) columns of the display panel; the first light-emitting element column 20c in column (m+1) and column (m+3) can refer to the first light-emitting element column 20c in the even-numbered (or odd-numbered) columns of the display panel; the first light-emitting element row n can refer to the first light-emitting element row 20r in the odd-numbered (or even-numbered) rows of the display panel; and the first light-emitting element row (n+1) can refer to the first light-emitting element row 20r in the even-numbered (or odd-numbered) rows of the display panel.

[0145] As shown in Figure 17, the first pixel circuit 10 in the h-th column and k-th position (i.e., the h-th...) k The first pixel circuit 10) can be connected to the nth light-emitting element in the mth column (i.e., the mth pixel). n (Electrically connected to the light-emitting element); the first pixel circuit 10 of the h-th column (k+1) (i.e., the h-th...) (k+1) The first pixel circuit 10) can be connected to the (m+1)th column and (n+1)th light-emitting element (i.e., the (m+1)th... (n+1) The first pixel circuit 10 (i.e., the (h+1)th pixel) is electrically connected to the (h+1)th light-emitting element; the first pixel circuit 10 in the (h+1)th column is also connected to the (h+1)th pixel. k The first pixel circuit 10 can be connected to the nth light-emitting element in the (m+1)th column (i.e., the (m+1)th... n The first pixel circuit 10 (i.e., the (h+1)th pixel) is electrically connected to the (h+1)th light-emitting element; the first pixel circuit 10 in the (h+1)th column (k+1)th pixel is also connected to the (h+1)th pixel. (k+1) The first pixel circuit 10) can be connected to the (n+1)th light-emitting element in the mth column (i.e., the mth pixel). (n+1) The first pixel circuit 10 (i.e., the (h+2)th column k-th pixel) is electrically connected to the light-emitting element; k The first pixel circuit 10) can be connected to the nth light-emitting element in the (m+3)th column (i.e., the (m+3)th pixel).n The (h+3)th column kth first pixel circuit 10 (i.e., the (h+3)th first pixel circuit 10) can be electrically connected with the (m+2)th column nth light emitting element (i.e., the (m+2)th light emitting element). (k+1) The (h+3)th column kth first pixel circuit 10 (i.e., the (h+3)th first pixel circuit 10) can be electrically connected with the (m+2)th column nth light emitting element (i.e., the (m+2)th light emitting element). (n+1) The (h+3)th column kth first pixel circuit 10 (i.e., the (h+3)th first pixel circuit 10) can be electrically connected with the (m+2)th column nth light emitting element (i.e., the (m+2)th light emitting element). k The (h+3)th column kth first pixel circuit 10 (i.e., the (h+3)th first pixel circuit 10) can be electrically connected with the (m+2)th column nth light emitting element (i.e., the (m+2)th light emitting element). n The (h+3)th column kth first pixel circuit 10 (i.e., the (h+3)th first pixel circuit 10) can be electrically connected with the (m+2)th column nth light emitting element (i.e., the (m+2)th light emitting element). (k+1) The (h+3)th column kth first pixel circuit 10 (i.e., the (h+3)th first pixel circuit 10) can be electrically connected with the (m+2)th column nth light emitting element (i.e., the (m+2)th light emitting element). (n+1) The (h+3)th column kth first pixel circuit 10 (i.e., the (h+3)th first pixel circuit 10) can be electrically connected with the (m+2)th column nth light emitting element (i.e., the (m+2)th light emitting element).

[0146] In the hth column first pixel circuit column 10c, part of the first pixel circuits 10 are electrically connected with the first color light emitting elements R in the mth column first light emitting element column 20c, and another part of the first pixel circuits 10 are electrically connected with the first color light emitting elements R in the (m+1)th column first light emitting element column 20c, and the first pixel circuits 10 electrically connected with the first color light emitting elements R in the mth column first light emitting element column 20c and the first pixel circuits 10 electrically connected with the first color light emitting elements R in the (m+1)th column first light emitting element column 20c are arranged alternately along the first direction X. In the (h+1)th column first pixel circuit column 10c, part of the first pixel circuits 10 are electrically connected with the second color light emitting elements B in the mth column first light emitting element column 20c, and another part of the first pixel circuits 10 are electrically connected with the second color light emitting elements B in the (m+1)th column first light emitting element column 20c, and the first pixel circuits 10 electrically connected with the second color light emitting elements B in the mth column first light emitting element column 20c and the first pixel circuits 10 electrically connected with the second color light emitting elements B in the (m+1)th column first light emitting element column 20c are arranged alternately along the first direction X. The first color light emitting elements R in the mth column first light emitting element column 20c and the (m+1)th column first light emitting element column 20c can be electrically connected with the first pixel circuits 10 in the hth column first pixel circuit column 10c, and the second color light emitting elements B in the mth column first light emitting element column 20c and the (m+1)th column first light emitting element column 20c can be electrically connected with the first pixel circuits 10 in the (h+1)th column first pixel circuit column 10c.

[0147] In the (h+2)th column first pixel circuit row 10c, part of the first pixel circuits 10 are electrically connected with the second color light emitting elements B in the (m+2)th column first light emitting element row 20c, and the other part of the first pixel circuits 10 are electrically connected with the second color light emitting elements B in the (m+3)th column first light emitting element row 20c, and the first pixel circuits 10 electrically connected with the second color light emitting elements B in the (m+2)th column first light emitting element row 20c and the first pixel circuits 10 electrically connected with the second color light emitting elements B in the (m+3)th column first light emitting element row 20c are arranged alternately along the first direction X. In the (h+3)th column first pixel circuit row 10c, part of the first pixel circuits 10 are electrically connected with the first color light emitting elements R in the (m+2)th column first light emitting element row 20c, and the other part of the first pixel circuits 10 are electrically connected with the first color light emitting elements R in the (m+3)th column first light emitting element row 20c, and the first pixel circuits 10 electrically connected with the first color light emitting elements R in the (m+2)th column first light emitting element row 20c and the first pixel circuits 10 electrically connected with the first color light emitting elements R in the (m+3)th column first light emitting element row 20c are arranged alternately along the first direction X. The second color light emitting elements B in the (m+2)th column first light emitting element row 20c and the (m+3)th column first light emitting element row 20c can be electrically connected with the first pixel circuits 10 in the (h+2)th column first pixel circuit row 10c, and the first color light emitting elements R in the (m+2)th column first light emitting element row 20c and the (m+3)th column first light emitting element row 20c can be electrically connected with the first pixel circuits 10 in the (h+3)th column first pixel circuit row 10c.

[0148] For example, when h, k, m and n are equal and each is 1, the first pixel circuit 10 in the first column and the first light emitting element (first color light emitting element R) in the first column can be electrically connected, the second first pixel circuit 10 in the first column and the second light emitting element (first color light emitting element R) in the second column can be electrically connected, the first pixel circuit 10 in the second column and the first light emitting element (second color light emitting element B) in the second column can be electrically connected, and the second first pixel circuit 10 in the second column and the second light emitting element (second color light emitting element B) in the first column can be electrically connected. The first pixel circuit 10 in the third column and the first light emitting element (second color light emitting element B) in the fourth column can be electrically connected, the second first pixel circuit 10 in the third column and the second light emitting element (second color light emitting element B) in the third column can be electrically connected, the first pixel circuit 10 in the fourth column and the first light emitting element (first color light emitting element R) in the third column can be electrically connected, and the second first pixel circuit 10 in the fourth column and the second light emitting element (first color light emitting element R) in the fourth column can be electrically connected.

[0149] It should be noted that the light emitting elements in the mth column, the (m+1)th column, the (m+2)th column and the (m+3)th column in the above description are the light emitting elements in the adjacent first light emitting element column 20c, and do not include the light emitting elements in the second light emitting element column (not shown in the figure).

[0150] Optionally, still referring to FIGS. 9, 10 and 17, the light emitting element 20 includes an anode 22, which includes an anode main body part 221 and an anode connecting part 222 connected to each other; the display panel further includes a pixel defining layer 30 and a plurality of pixel openings 31 arranged in the pixel defining layer 30, along the thickness direction of the display panel, the anode main body part 221 overlaps the pixel opening 31, and the anode connecting part 222 does not overlap the pixel opening 31; the h (k+1) th first pixel circuit 10 is electrically connected to the anode connecting part 222 of the (m+1) (n+1) th light emitting element; the (h+2) k th first pixel circuit 10 is electrically connected to the anode connecting part 222 of the (m+3) n th light emitting element.

[0151] The pixel defining layer 30 is arranged in the same manner as in the above embodiments, and the relative positions of the anode main body part 221 and the anode connecting part 222 to the pixel opening 31 are also the same as in the above embodiments, which will not be described here. Similarly to the above embodiments, in this embodiment, the anode main body part 221 is electrically connected to the corresponding first pixel circuit 10 through the anode connecting part 222, thereby realizing the electrical connection between the light emitting element and the pixel circuit.

[0152] For example, the h k th first pixel circuit 10 is electrically connected to the anode connecting part 222 of the m n th light emitting element, the h (k+1) th first pixel circuit 10 is electrically connected to the anode connecting part 222 of the (m+1) (n+1) th light emitting element; the (h+1) k th first pixel circuit 10 is electrically connected to the anode connecting part 222 of the (m+1) n th light emitting element, the (h+1) (k+1) th first pixel circuit 10 is electrically connected to the anode connecting part 222 of the m (n+1) th light emitting element; the (h+2) k th first pixel circuit 10 is electrically connected to the anode connecting part 222 of the (m+3) n th light emitting element, the (h+2) (k+1) th first pixel circuit 10 is electrically connected to the anode connecting part 222 of the (m+2) (n+1) th light emitting element; the (h+3) k th first pixel circuit 10 is electrically connected to the anode connecting part 222 of the (m+2)n The anode connecting portion 222 of the (m+2)th light emitting element is electrically connected to the fourth node N4 of the (h+3)th first pixel circuit 10. (k+1) The anode connecting portion 222 of the (m+2)th light emitting element is electrically connected to the fourth node N4 of the (h+3)th first pixel circuit 10. (n+1) The anode connecting portion 222 of the (m+2)th light emitting element is electrically connected to the fourth node N4 of the (h+3)th first pixel circuit 10.

[0153] In the embodiment shown in FIG. 17, the corresponding connection relationship between the light emitting elements in the mth column and the (m+1)th column and the first pixel circuits 10 in the hth column and the (h+1)th column is the same as the corresponding connection relationship between the light emitting elements in the pth column and the (p+1)th column and the first pixel circuits 10 in the ith column and the (j+1)th column in the above-described embodiment. Correspondingly, the arrangement mode of the anode connecting portion 222 of the light emitting elements in the mth column and the (m+1)th column, the arrangement mode of the fourth node N4 of the first pixel circuits 10 in the hth column and the (h+1)th column, and the connection mode between the anode connecting portion 222 and the fourth node N4 can refer to the descriptions of the corresponding embodiments in FIGS. 4, 11-16. The embodiment shown in FIG. 17 is different in that the arrangement mode of the anode connecting portion 222 of the light emitting elements in the (m+2)th column and the (m+3)th column, and the arrangement mode of the fourth node N4 of the first pixel circuits 10 in the (h+2)th column and the (h+3)th column.

[0154] As shown in FIG. 17, when h, k, m, and n are equal, in the orthographic projection on the plane where the substrate 40 is located, the distance between the anode main portion 221 of the (m+2)th light emitting element and the fourth node N4 of the (h+3)th first pixel circuit 10 (the distance between the projections of the two on the second direction Y) is less than the distance between the anode main portion 221 of the (m+3)th light emitting element and the fourth node N4 of the (h+2)th first pixel circuit 10 (the distance between the projections of the two on the second direction Y). n The anode main portion 221 of the (m+2)th light emitting element is electrically connected to the fourth node N4 of the (h+3)th first pixel circuit 10. k The anode main portion 221 of the (m+2)th light emitting element is electrically connected to the fourth node N4 of the (h+3)th first pixel circuit 10. n The anode main portion 221 of the (m+2)th light emitting element is electrically connected to the fourth node N4 of the (h+3)th first pixel circuit 10. k The anode main portion 221 of the (m+2)th light emitting element is electrically connected to the fourth node N4 of the (h+3)th first pixel circuit 10. n The anode main portion 221 of the (m+2)th light emitting element is electrically connected to the fourth node N4 of the (h+3)th first pixel circuit 10. n The anode main portion 221 of the (m+2)th light emitting element is electrically connected to the fourth node N4 of the (h+3)th first pixel circuit 10.

[0155] In addition, the anode connecting portion 222 of the (m+2)th light emitting element can be located on the side of the anode main portion 221 of the (m+2)th light emitting element away from the (h+2)th first pixel circuit column 10c, and the anode connecting portion 222 of the (m+3)th light emitting element can be located on the side of the anode main portion 221 of the (m+3)th light emitting element close to the (h+2)th first pixel circuit column 10c. n In addition, the anode connecting portion 222 of the (m+2)th light emitting element can be located on the side of the anode main portion 221 of the (m+2)th light emitting element away from the (h+2)th first pixel circuit column 10c, and the anode connecting portion 222 of the (m+3)th light emitting element can be located on the side of the anode main portion 221 of the (m+3)th light emitting element close to the (h+2)th first pixel circuit column 10c. n In addition, the anode connecting portion 222 of the (m+2)th light emitting element can be located on the side of the anode main portion 221 of the (m+2)th light emitting element away from the (h+2)th first pixel circuit column 10c, and the anode connecting portion 222 of the (m+3)th light emitting element can be located on the side of the anode main portion 221 of the (m+3)th light emitting element close to the (h+2)th first pixel circuit column 10c. (n+1)The anode connecting part 222 of the light emitting element can be located at the side of the anode main part 221 of the light emitting element close to the (h+2)th column of the first pixel circuit column 10c, the (m+3)th column of the first pixel circuit column 10c (n+1) The anode connecting part 222 of the light emitting element can be located at the side of the anode main part 221 of the light emitting element close to the (h+2)th column of the first pixel circuit column 10c, the (m+3)th column of the first pixel circuit column 10c

[0156] It should be noted that in the embodiment shown in FIG. 17, the anode connecting part 222 is arranged in the first light emitting element row 20r of the odd row and the even row, and the distribution of the anode connecting part 222 is relatively uniform. At this time, the virtual connecting structure 223 can no longer be arranged, so as to reduce the number of wirings (shown in FIG. 17); or the virtual connecting structure 223 is arranged on both sides of at least part of the anode connecting part 222 along the first direction X and / or the second direction Y (not shown in FIG. 23), so that the anode connecting part 222 and the virtual connecting structure 223 overlap along the first direction X and / or the second direction Y, and the in-plane impedance is further ensured to be consistent.

[0157] Optionally, in the embodiment of the present application, the anode connecting part 222 is arranged in the same layer as the anode main part 221; or the display panel further comprises a substrate 40, and the film layer in which the anode connecting part 222 is arranged is located between the film layer in which the anode main part 221 is arranged and the film layer in which the substrate 40 is arranged.

[0158] FIG. 18 is a structural schematic diagram of another display panel provided by an embodiment of the present application, FIG. 19 is a structural schematic diagram of a cross section of a display panel provided by an embodiment of the present application, FIG. 20 is a structural schematic diagram of a part of the display panel shown in FIG. 19, FIG. 21 is a structural schematic diagram of another part of the display panel shown in FIG. 19, FIG. 22 is a structural schematic diagram of another part of the display panel shown in FIG. 19, FIG. 23 is a structural schematic diagram of another part of the display panel shown in FIG. 19, FIG. 24 is a structural schematic diagram of another part of the display panel shown in FIG. 19, FIG. 25 is a structural schematic diagram of another part of the display panel shown in FIG. 19, FIG. 26 is a structural schematic diagram of another part of the display panel shown in FIG. 19, FIG. 27 is a structural schematic diagram of another part of the display panel shown in FIG. 19, and FIG. 28 is a structural schematic diagram of another part of the display panel shown in FIG. 19. The display panel is arranged by multiple film layers, FIG. 18 shows a top view of part of the film layers of the display panel, FIG. 19 shows a cross-sectional view of the whole film layer of the display panel, and FIGS. 20-27 show different film layers in the display panel from top to bottom.

[0159] Referring to FIGS. 18-28, taking the LTPO display panel as an example, along the thickness direction Z of the display panel, one side of the substrate 40 can include the buffer layer 70, the first semiconductor layer POLY, the first metal layer M1, the second metal layer MC, the second semiconductor layer IGZO, the fifth metal layer MG, the third metal layer M2, the fourth metal layer M3, the planarization layer PLN, and the anode layer, an insulating layer 80 can be arranged between any two adjacent conductive film layers, the third metal layer M2 can be understood as the first source-drain electrode layer, the fourth metal layer M3 can be understood as the second source-drain electrode layer, and the anode layer RE can be understood as the film layer in which the anode main body part 221 is located. For the film layer arrangement of the display panel, adaptive adjustments can be made according to actual production needs, such as adding or removing some film layers, which are not limited in the embodiments of the present application. FIG. 20 is a structural schematic diagram of the first semiconductor layer POLY in FIG. 19, FIG. 21 is a structural schematic diagram of the first metal layer M1 in FIG. 19, FIG. 22 is a structural schematic diagram of the second metal layer MC in FIG. 19, FIG. 23 is a structural schematic diagram of the second semiconductor layer IGZO in FIG. 19, FIG. 24 is a structural schematic diagram of the fifth metal layer MG in FIG. 19, FIG. 25 is a structural schematic diagram of the third metal layer M2 in FIG. 19, FIG. 26 is a structural schematic diagram of the fourth metal layer M3 in FIG. 19, FIG. 27 is a structural schematic diagram of the anode layer RE in FIG. 19, and FIG. 28 is a structural schematic diagram of the stack of the fourth metal layer M3 and the anode layer RE. In order to clearly show the multi-film layer stack structure diagram, not all film layers are shown in FIG. 18, only the first semiconductor layer POLY, the first metal layer M1, the second metal layer MC, and the third metal layer M2 are shown, and the structures of other film layers can be referred to the corresponding single-film layer schematic diagram.

[0160] Referring to FIGS. 6, 7, 18-28, the fourth node N4 of the first pixel circuit 10 is connected to the second light-emitting control transistor T6, the reset transistor T7, and the anode 22 of the light-emitting element 20, the connection region of the second light-emitting control transistor T6 and the reset transistor T7 can be connected to the anode 22 of the light-emitting element through the connection cross-line of the third metal layer M2 and the fourth metal layer M3, and the fourth node N4 can be regarded as the wiring structure of the projection overlapping position of the connection region and the third metal layer M2 and the fourth metal layer M3. In the embodiment, the anode connection part 222 can be arranged in the same layer as the anode main body part 221, and both are located in the anode layer RE.

[0161] As shown in FIGS. 6, 7, 18-28, the active layers of the first light-emitting control transistor T1, the data writing transistor T2, the driving transistor T3, the second light-emitting control transistor T6, and the reset transistor T7 can be located in the first semiconductor layer POLY, and the active layers of the threshold compensation transistor T4 and the initialization transistor T5 can be located in the second semiconductor layer IGZO. The first metal layer M1 can include the first plate C1 of the storage capacitor Cst, the third scan signal line SP*, and the fourth scan signal line SP. The second metal layer MC can include the first plate C1 of the storage capacitor Cst, the first scan signal line S1-1 extending along the second direction Y, the second scan signal line S2-1, the initialization signal line VREF1, and the reset signal line VREF2, and the portion of the first scan signal line S1-1 overlapping the initialization transistor T5 also serves as the bottom gate of the initialization transistor T5, and the portion of the second scan signal line S2-1 overlapping the threshold compensation transistor T4 also serves as the bottom gate of the threshold compensation transistor T4. The fifth metal layer MG can include the bias voltage signal line DVH, the first scan signal line S1-2, the second scan signal line S2-2, and part of the shielding structure 90, and the portion of the first scan signal line S1-2 overlapping the initialization transistor T5 also serves as the top gate of the initialization transistor T5, and the portion of the second scan signal line S2-2 overlapping the threshold compensation transistor T4 also serves as the top gate of the threshold compensation transistor T4; the shielding structure can be located between the signal line where the signal jumps and the first node, and the shielding structure can be electrically connected to a fixed potential, so that the jump of other signals can be avoided to affect the potential of the first node. The third metal layer M2 can include the data auxiliary line FIAA extending along the second direction Y and part of the connection cross-line, etc. The third metal layer M2 and the planarization layer PLN can further include the fourth metal layer M3, and the fourth metal layer M3 can include the power supply signal line PVDD, the data signal line Data, and the data auxiliary line FIAA extending along the first direction X, and part of the connection cross-line, etc.; the data auxiliary line FIAA can be configured to connect the data signal line Data and the display controller. The connection region of the reset transistor T7 and the second light-emitting control transistor T6 and the portion of the connection cross-line (the connection cross-line in the third metal layer M2 and the fourth metal layer M3) overlapping the projection of the connection region can be regarded as the fourth node N4.

[0162] At least one of the initialization signal line VREF1, the reset signal line VREF2 and the bias voltage signal line DVH can have a grid-like structure, that is, at least one of the initialization signal line VREF1, the reset signal line VREF2 and the bias voltage signal line DVH can include at least two layers of film layer structures with different extension directions. By means of the grid-like structure, the loss of the signal in the transmission process can be reduced, and the signal transmission accuracy can be improved. Referring to FIGS. 18, 22, 24 and 26, the initialization signal line VREF1 can be a single layer of film structure, which is located in the second metal layer MC. The reset signal line VREF2 can include two layers of film layers. The reset signal line VREF2 can include a first reset signal line VREF21 and a second reset signal line VREF22. The first reset signal line VREF21 extends along a first direction and can be located in the fourth metal layer M3. The second reset signal line VREF22 extends along a second direction and can be located in the second metal layer MC. The bias voltage signal line DVH can include two layers of film layers. The bias voltage signal line DVH can include a first bias voltage signal line DVH1 and a second bias voltage signal line DVH2. The first bias voltage signal line DVH1 extends along a first direction and can be located in the fourth metal layer M3. The second bias voltage signal line DVH2 extends along a second direction and can be located in the fifth metal layer MG. In addition, the first reset signal line VREF21 and the first bias voltage signal line DVH1 located in the fourth metal layer M3 can be alternately arranged in the second direction.

[0163] FIG. 29 is a structural schematic diagram of another display panel provided by an embodiment of the present application. FIG. 30 is a schematic diagram of a cross-sectional structure of another display panel provided by an embodiment of the present application. FIG. 31 is a schematic diagram of a part of the structure of the display panel shown in FIG. 30. FIG. 32 is a schematic diagram of another part of the structure of the display panel shown in FIG. 30. FIG. 33 is a schematic diagram of another part of the structure of the display panel shown in FIG. 30. FIG. 34 is a schematic diagram of another part of the structure of the display panel shown in FIG. 30. FIG. 35 is a schematic diagram of another part of the structure of the display panel shown in FIG. 30. FIG. 36 is a schematic diagram of another part of the structure of the display panel shown in FIG. 30. FIG. 37 is a schematic diagram of another part of the structure of the display panel shown in FIG. 30. FIG. 38 is a schematic diagram of another part of the structure of the display panel shown in FIG. 30. FIG. 29 shows a top view of a part of the film layer stack of the display panel. FIG. 30 shows a cross-sectional view of the whole film layer of the display panel. FIGS. 31-38 show different film layers in the display panel from top to bottom.

[0164] Referring to FIGS. 29-40, still taking the LTPO display panel as an example, along the thickness direction Z of the display panel, one side of the substrate 40 can include the buffer layer 70, the first semiconductor layer POLY, the first metal layer M1, the second metal layer MC, the second semiconductor layer IGZO, the fifth metal layer MG, the third metal layer M2, the fourth metal layer M3, the sixth metal layer M4, the planarization layer PLN, and the anode layer RE. An insulating layer 80 can be arranged between any two adjacent conductive film layers. The third metal layer M2 can be understood as a first source-drain electrode layer, the fourth metal layer M3 can be understood as a second source-drain electrode layer, and the sixth metal layer M4 can be understood as a third source-drain metal layer. For the film layer arrangement of the display panel, adaptive adjustments such as adding or removing part of the film layer can be made according to actual production needs, which is not limited in the embodiments of the present application. FIG. 31 is a structural schematic diagram of the first semiconductor layer POLY in FIG. 30, FIG. 32 is a structural schematic diagram of the first metal layer M1 in FIG. 30, FIG. 33 is a structural schematic diagram of the second metal layer MC in FIG. 30, FIG. 34 is a structural schematic diagram of the third metal layer M2 in FIG. 30, FIG. 35 is a structural schematic diagram of the fourth metal layer M3 in FIG. 30, FIG. 36 is a structural schematic diagram of the sixth metal layer M4 in FIG. 30, FIG. 37 is a structural schematic diagram of the anode layer RE in FIG. 30, and FIG. 38 is a structural schematic diagram of the fourth metal layer M3, the sixth metal layer M4, and the anode layer RE in FIG. 30. In order to clearly show the multi-film layer stack structure diagram, not all film layers are shown in FIG. 29, only the first semiconductor layer POLY, the first metal layer M1, the second metal layer MC, and the third metal layer M2 are shown, and the structures of other film layers can be referred to the corresponding single-film layer schematic diagram.

[0165] The structures of the second semiconductor layer IGZO and the fifth metal layer MG in the display panel shown in FIG. 29 are the same as those of the display panel shown in FIG. 18. The second semiconductor layer IGZO can refer to FIG. 23, and the fifth metal layer MG can refer to FIG. 24, which will not be described here.

[0166] The difference between the embodiment shown in FIG. 29 and the embodiment shown in FIG. 18 is the film layer of the display panel and the wiring between the film layers. Compared with the display panel shown in FIG. 18, the display panel shown in FIG. 29 adds a metal layer between the third metal layer M2 and the anode layer RE, and part of the wiring in the fourth metal layer M3 shown in FIG. 18 is arranged in the fourth metal layer M3 and the sixth metal layer M4 shown in FIG. 29, so as to reduce the wiring difficulty. In the embodiment shown in FIG. 29, the connection area of the second light-emitting control transistor T6 and the reset transistor T7 can be connected with the anode 22 of the light-emitting element through the connection cross-line of the third metal layer M2, the fourth metal layer M3 and the sixth metal layer M4, and the fourth node N4 can be regarded as the wiring structure of the projection overlapping position of the connection area and the third metal layer M2, the fourth metal layer M3 and the sixth metal layer M4. In the embodiment, the anode connection part 222 can be arranged in the same layer as the anode main part 221, and both are located in the anode layer RE.

[0167] In the embodiment shown in FIG. 29, the wiring mode in the first semiconductor layer POLY, the first metal layer M1, the second semiconductor layer IGZO and the fifth metal layer MG is the same as that in the embodiment shown in FIG. 18, which will not be described here again. Here, only the differences from the above-mentioned embodiments will be introduced. Referring to FIGS. 29-38, in the display panel shown in FIGS. 29-38, the second metal layer MC can include the first plate C1 of the storage capacitor Cst, the scan signal line S1-1 extending along the second direction Y, the second scan signal line S2-1 and the second reset signal line VREF22, etc. The third metal layer M2 can include the initialization signal line VREF1 extending along the first direction X, the first reset signal line VREF21, the first bias voltage signal line DVH1 and part of the connection cross-line. The first reset signal line VREF21 and the second reset signal line VREF22 are connected to form a grid, and the first bias voltage signal line DVH1 and the second bias voltage signal line DVH2 are connected to form a grid. In the third metal layer M2, the reset signal line VREF2 (the first reset signal line VREF21) and the bias voltage signal line DVH (the first bias voltage signal line DVH1) are arranged alternately along the first direction X and the second direction Y. The fourth metal layer M3 can include the data auxiliary line FIAA extending along the second direction Y, the power signal line PVDD and part of the connection cross-line, etc. The sixth metal layer M4 can include the power signal line PVDD extending along the first direction X, the data signal line Data and the data auxiliary line FIAA, and part of the connection cross-line, etc.

[0168] In the embodiments shown in FIG. 18 and FIG. 28, the anode connecting part 222 connected with the anode is arranged in the same layer as the anode main part 221, and the anode connecting part 222 and the anode main part 221 can be prepared in the same patterning process, without the need for additional punching connection. However, it is necessary to ensure that the anode connecting part 222 of one light emitting element is not connected with the anode (including the anode main part 221 and the anode connecting part 222) of other light emitting elements, so as to avoid short circuit of the anodes of different light emitting elements. For example, as shown in FIG. 28 and FIG. 38, the anode connecting part 222 of part of the light emitting elements can be arranged around part of the anode main part 221 of the light emitting element adjacent thereto, so as to extend to the fourth node N4 of the first pixel circuit connected with the light emitting element.

[0169] FIG. 39 is a structural schematic diagram of a fourth metal layer in a display panel according to an embodiment of the present application, FIG. 40 is a structural schematic diagram of a sixth metal layer in a display panel according to an embodiment of the present application, FIG. 41 is a structural schematic diagram of an anode layer in a display panel according to an embodiment of the present application, and FIG. 42 is a structural schematic diagram of a partial film layer stack in a display panel according to an embodiment of the present application. The overall film layers of the display panel corresponding to FIG. 39 to FIG. 42 can be the same as those shown in the embodiment of FIG. 29, and the wiring manner in the first semiconductor layer POLY, the first metal layer M1, the second metal layer MC, the second semiconductor layer IGZO, the fifth metal layer MG and the third metal layer M2 can also be the same as those shown in the embodiment of FIG. 29, which will not be described herein again.

[0170] In the embodiments shown in FIG. 39 to FIG. 42, the anode main part 221 and the anode connecting part 222 are arranged in different layers, for example, the anode main part 221 is located in the anode layer RE, and the anode connecting part 222 can be located in at least one metal layer between the first semiconductor layer POLY and the anode layer RE. In the drawings, the anode connecting part 222 is taken as an example located in the fourth metal layer M3, and the anode connecting part 222 and the anode main part 221 are connected through a via hole, so that the anode connecting part 222 can be partially arranged in the same layer as the fourth node N4 and connected therewith, and the anode connecting part 222 and the anode main part 221 can be prepared in the same patterning process. The film layer in which the anode connecting part 222 is located is not limited to the fourth metal layer M3 described above, and at least one of the first metal layer M1, the second metal layer MC, the second semiconductor layer IGZO, the fifth metal layer MG, the fourth metal layer M3 and the sixth metal layer M4 can be arranged to form the anode connecting part 222.

[0171] Optionally, referring to FIG. 29, FIG. 39 to FIG. 42, the film layer in which the anode connecting part 222 is located is located between the film layer in which the anode main part 221 is located and the film layer in which the substrate is located; and at least part of the anode connecting part 222 overlaps the anode main part 221 along the thickness direction of the display panel.

[0172] As shown in FIG. 29 and FIG. 39-42, when the anode connecting part 222 is located in at least one conductive film layer between the anode layer RE and the substrate 40, the anode connecting part 222 can be arranged such that the orthogonal projection of the anode connecting part 222 on the plane of the substrate 40 overlaps with the orthogonal projection of the anode main body part 221 on the plane of the substrate 40. In this way, the influence of the anode connecting part 222 on the light transmittance of the display panel can be reduced, and the display effect can be ensured.

[0173] The virtual connecting structure 223 is also shown in FIG. 39-42. The virtual connecting structure 223 can be arranged according to any of the above embodiments, and will not be described here.

[0174] For example, FIG. 43 is a schematic structural diagram of an anode of a light emitting element according to an embodiment of the present application. As shown in FIG. 43, in some embodiments, the anode main body part 221 that overlaps with the anode connecting part 222 in the thickness direction of the display panel includes a first anode main body part 2211; the first anode main body part 2211 includes a first virtual symmetry axis ax1, and the first anode main body part 2211 is symmetrically arranged about the first virtual symmetry axis ax1; in the thickness direction of the display panel, one anode connecting part 222 overlaps with the first anode main body part 2211, and the anode connecting part 222 overlaps with the first virtual symmetry axis ax1.

[0175] As shown in FIG. 43, the anode main body part 221 includes a first anode main body part 2211, and the orthogonal projection of the first anode main body part 2211 on the plane of the substrate 40 is an axisymmetric figure that is symmetric about the first virtual symmetry axis ax1. The extension direction of the first virtual symmetry axis ax1 is not limited, and FIG. 43 is only an example. In actuality, any symmetry axis of the first anode main body part 2211 is the first virtual symmetry axis ax1. In the thickness direction of the display panel, one first anode main body part 2211 overlaps with one anode connecting part 222, and the anode connecting part 222 overlaps with the first virtual symmetry axis ax1, so that the anode connecting part 222 is only possible near the symmetry axis position of the first anode main body part 2211. In the orthogonal projection on the plane of the substrate 40, the anode connecting part 222 is near the axis of the first anode main body part 2211, and the anode connecting part 222 approximately bisects the first anode main body part 2211, so that the two parts of the first anode main body part 2211 divided by the anode connecting part 222 have substantially the same area, the luminance difference of the light emitting element overlapping with the anode connecting part 222 under different observation angles is balanced, and the four-direction color cast problem of the display panel is avoided, thereby improving the display effect.

[0176] For example, FIG. 44 is a schematic structural view of an anode of another light-emitting element provided by embodiments of the present application. As shown in FIG. 44, in some other embodiments, the anode main body portion 221 overlaps with the anode connection portion 222 in the thickness direction of the display panel, and the anode main body portion 221 includes a second anode main body portion 2212. In the thickness direction of the display panel, the two anode connection portions 222 overlap with the second anode main body portion 2212. The second anode main body portion 2212 includes a second virtual symmetry axis ax2, and the portions where the two anode connection portions 222 overlap with the second anode main body portion 2212 are symmetrically arranged in the normal projection of the substrate 40 in the normal projection of the substrate 40 with respect to the second virtual symmetry axis ax2.

[0177] As shown in FIG. 44, the anode main body portion 221 includes the second anode main body portion 2212, and the normal projection of the second anode main body portion 2212 on the substrate 40 is an axisymmetric pattern symmetric with respect to the second virtual symmetry axis ax2. The shapes of the second anode main body portion 2212 and the first anode main body portion 2212 can be the same or different, and the first virtual symmetry axis ax1 and the second virtual symmetry axis ax2 can extend in the same or different directions. FIG. 44 exemplarily shows that the first virtual symmetry axis ax1 and the second virtual symmetry axis ax2 extend in different directions, but the present application is not limited thereto. In the thickness direction of the display panel, one second anode main body portion 2212 overlaps with two anode connection portions 222, and in the normal projection of the substrate on the substrate, the two anode connection portions 222 are symmetric with respect to the second virtual symmetry axis ax2. The two anode connection portions 222 approximately trisect the second anode main body portion 2212, so that the three parts of the second anode main body portion 2212 divided by the two anode connection portions 222 have substantially the same area, thereby avoiding color deviation of the display panel in four directions.

[0178] Optionally, in possible embodiments, the display panel further includes a light-transmitting hole penetrating at least part of the film layers in the display panel; the light-transmitting hole is configured to transmit external light to the photosensitive element; and the anode connection portion does not overlap with the light-transmitting hole in the thickness direction of the display panel.

[0179] The light-transmitting hole can be a region where a hole is dug under the display panel, and the photosensitive element can be arranged therein. The photosensitive element includes but is not limited to a camera, an infrared sensor, and the like. The light-transmitting hole allows external light to pass through, which is then captured by the photosensitive element. In the scheme in which the light-transmitting hole is provided in the display panel, the anode connection portion can be arranged so as not to overlap with the light-transmitting hole in the thickness direction of the display panel, so that the anode connection portion avoids the light-transmitting hole and avoids affecting the light transmittance at the light-transmitting hole, thereby ensuring the photosensitive effect of the photosensitive element.

[0180] Optionally, FIG. 45 is a schematic view of a cross-sectional structure of a display panel provided by an embodiment of the present application. In some embodiments, the anode connecting part 222 is located between the film layer where the anode main part 221 is located and the film layer where the substrate 40 is located; the first pixel circuit 10 includes at least one transistor (for example, T1-T8 in FIG. 6), and the transistor includes a first active layer; the first pixel circuit 10 further includes a storage capacitor Cst, and the storage capacitor Cst includes a first plate C1 and a second plate C2 arranged oppositely, and the second plate C2 is located on the side of the first plate C1 away from the first active layer; the display panel further includes a first semiconductor layer POLY, a first metal layer M1, a second metal layer MC, and a third metal layer M2; the first active layer is located on the first semiconductor layer POLY, the first plate C1 is located on the first metal layer M1, the second plate C2 is located on the second metal layer MC, and the third metal layer M2 is located on the side of the second metal layer MC away from the first active layer; and the anode connecting part 222 is located on at least one of the first metal layer M1, the second metal layer MC, or the third metal layer M2.

[0181] In the present embodiment, the transistor in the first pixel circuit 10 (for example, which can include the above-mentioned T1-T8 transistors) is an LTPS transistor, and an LTPS display panel is formed. In the direction away from the substrate 40, the display panel can include a buffer layer 70, a first semiconductor layer POLY, a first metal layer M1, a second metal layer MC, a third metal layer M2, a fourth metal layer M3, a planarization layer PLN, and an anode layer RE, and an insulating layer 80 is arranged between any two adjacent conductive film layers. The first active layer of the transistor is located on the first semiconductor layer POLY. The first plate C1 of the storage capacitor Cst, the first scan signal line S1, the second scan signal line S2, the light-emitting control signal line EMIT, etc. can be located on the first metal layer M1, and the scan signal line overlaps with the active layer of the transistor to form the gate of the transistor. The second plate C2 of the storage capacitor Cst can be formed on the second metal layer MC. The second metal layer MC can further include signal lines and shielding structures extending in the second direction Y, such as the initialization signal line VREF1 and / or the reset signal line VREF2, etc. extending in the second direction Y. The third metal layer M2 as the first source-drain metal layer can include a connection cross-line between multiple layers of conductive films, etc. The fourth metal layer M3 as the second source-drain metal layer can include the power supply signal line PVDD, the data signal line Data, and the data auxiliary line, etc. extending in the first direction X. The arrangement of the signal lines between the above-mentioned multiple metal layers is only exemplary, and the arrangement of the signal lines in the metal layers can be adjusted according to actual needs. The anode connecting part 222 of the multiple light-emitting elements 22 in the first light-emitting element column 20c can be formed on at least one of the first metal layer M1, the second metal layer MC, and the third metal layer M2, so as to realize flexible arrangement of the anode connecting part 222.

[0182] Optionally, FIG. 46 is a schematic view of a cross-sectional structure of a display panel according to an embodiment of the present application. In combination with FIGS. 4, 6 and 46, in some embodiments, the anode connecting part 222 is located between the film layer where the anode main part 221 is located and the film layer where the substrate 40 is located; the pixel circuit includes at least one transistor, the transistor includes a first active layer; the pixel circuit further includes a storage capacitor Cst, the storage capacitor Cst includes a first plate C1 and a second plate C2 arranged oppositely, the second plate C2 is located on a side of the first plate C1 away from the first active layer; the display panel further includes a first semiconductor layer POLY, a first metal layer M1, a second metal layer MC, a third metal layer M2 and a fourth metal layer M3; the first active layer is located on the first semiconductor layer POLY, the first plate C1 is located on the first metal layer M1, the second plate C2 is located on the second metal layer MC, the third metal layer M2 is located on a side of the second metal layer MC away from the first active layer, and the fourth metal layer M3 is located on a side of the third metal layer M2 away from the first active layer; the anode connecting part 222 is located on at least one of the first metal layer M1, the second metal layer MC, the third metal layer M2 or the fourth metal layer M3.

[0183] In the present embodiment, the transistors in the first pixel circuit 10 (e.g., which can include the above-mentioned T1-T8 transistors) are LTPS transistors, forming an LTPS display panel. In the direction away from the substrate 40, the display panel can include a buffer layer 70, a first semiconductor layer POLY, a first metal layer M1, a second metal layer MC, a third metal layer M2, a fourth metal layer M3, a fifth metal layer M4, a planarization layer PLN and an anode layer RE, and an insulating layer 80 is arranged between any two adjacent conductive film layers. The signal line arrangement in the first semiconductor layer POLY, the first metal layer M1, the second metal layer MC and the third metal layer M2 can be the same as or different from the above-mentioned embodiment corresponding to FIG. 45, which is not limited in the present embodiment. The fourth metal layer M3 can include part of the power supply signal line PVDD and part of the data auxiliary line, as well as a connection cross line between the multiple layers of conductive film layers, etc. The fifth metal layer M5 can include another part of the PVDD, another part of the data auxiliary line FIAA and the data signal line Data, etc. The arrangement of the signal lines between the above-mentioned multiple metal layers is only exemplary, and the arrangement of the signal lines in the metal layers can be adjusted according to actual needs. The anode connecting part 222 of the multiple light emitting elements in the first light emitting element column 20c can be formed in at least one of the first metal layer M1, the second metal layer MC, the third metal layer M2 and the fourth metal layer M3, realizing flexible arrangement of the anode connecting part 222.

[0184] Optionally, referring to FIGS. 4, 8, 18-28, the anode connecting portion 222 is located between the film layer where the anode main body portion 221 is located and the film layer where the substrate 40 is located; the first pixel circuit 10 includes at least one first type transistor and at least one second type transistor, the first type transistor includes a first active layer, and the second type transistor includes a second active layer and a top gate located on a side of the second active layer away from the first active layer; the first pixel circuit 10 further includes a storage capacitor Cst including a first plate C1 and a second plate C2 oppositely arranged, the second plate C2 being located on a side of the first plate C1 away from the first active layer; the display panel further includes a first semiconductor layer POLY, a first metal layer M1, a second metal layer MC, a second semiconductor layer IGZO, a fifth metal layer MG, a third metal layer M2, and a fourth metal layer M3; the first active layer is located on the first semiconductor layer POLY, the first plate C1 is located on the first metal layer M1, the second plate C2 is located on the second metal layer MC, the second active layer is located on the second semiconductor layer IGZO, the top gate is located on the fifth metal layer MG, the third metal layer M2 is located on a side of the fifth metal layer MG away from the first active layer, and the fourth metal layer M3 is located on a side of the third metal layer M2 away from the first active layer POLY; the anode connecting portion 222 is located in at least one of the first metal layer M1, the second metal layer MC, the second semiconductor layer IGZO, the fifth metal layer MG, the third metal layer M2, or the fourth metal layer M3.

[0185] As shown in FIGS. 4, 8, 18-28, the first type transistor can refer to the LTPS transistor described above, and the second type transistor can refer to the IGZO transistor described above, thereby forming an LTPO display panel. The threshold compensation transistor T4 and the initialization transistor T5 can be the second type transistor, and the first light-emitting control transistor T1, the data writing transistor T2, the driving transistor T3, the second light-emitting control transistor T6, and the reset transistor T7 can be the second type transistor. The first type transistor includes a first active layer and a first gate, and the second type transistor can include a second active layer, a top gate, and a bottom gate. The first gate of the first type transistor can be located on the first active layer close to the second active layer, forming a transistor with a top gate structure, or the first gate is located on a side of the first active layer away from the second active layer, forming a transistor with a bottom gate structure. The top gate of the second type transistor is located on a side of the second active layer away from the first active layer, and the bottom gate is located on a side of the second active layer close to the first active layer. Illustratively, the first gate can be located on the first metal layer M1, the bottom gate can be located on the second metal layer MC, and the top gate can be located on the fifth metal layer MG. The arrangement in the first metal layer M1, the second metal layer MC, the fifth metal layer MG, the third metal layer M2, and the fourth metal layer M3 is not limited in a manner, which can be referred to as shown in FIGS. 18-28, and will not be described here.

[0186] The anode connecting portion 222 of the light emitting element 22 can be formed in at least one of the first metal layer M1, the second metal layer MC, the second semiconductor layer IGZO, the fifth metal layer MG, the third metal layer M2, and the fourth metal layer M3, so as to realize flexible arrangement of the anode connecting portion 222. As shown in FIG. 39, the anode connecting portion 222 is arranged in the fourth metal layer M3 as an example.

[0187] Optionally, referring to FIG. 27, the first color light emitting elements R and the second color light emitting elements B form a first virtual quadrilateral Z1, the first color light emitting elements R are located at the first vertexes of the first virtual quadrilateral Z1, the second color light emitting elements B are located at the second vertexes of the first virtual quadrilateral Z1, and the third color light emitting elements G are located inside the first virtual quadrilateral Z1; the third color light emitting elements G form a second virtual quadrilateral Z2, the third color light emitting elements G are located at the vertexes of the second virtual quadrilateral Z2, and the first color light emitting elements R or the second color light emitting elements B are located inside the second virtual quadrilateral Z2; the first color light emitting elements R include one of red light emitting elements and blue light emitting elements, the second color light emitting elements B include the other of the red light emitting elements and the blue light emitting elements; and the third color light emitting elements G include green light emitting elements.

[0188] The first color light emitting elements R and the second color light emitting elements B form a first virtual quadrilateral Z1, two first color light emitting elements R are located at opposite corners of the first virtual quadrilateral Z1, and two second color light emitting elements B are located at the other two opposite corners of the first virtual quadrilateral Z1. The third color light emitting elements G are arranged inside the first virtual quadrilateral Z1. The third color light emitting elements G can also form a second virtual quadrilateral Z2, in which the first color light emitting elements R or the second color light emitting elements B are located.

[0189] The first color, the second color, and the third color correspond to one of red, blue, and green, respectively. Through the above arrangement of the light emitting elements, the rendering effect of the light emitting elements can be better, and the color display effect of the display panel is further ensured.

[0190] FIG. 47 is a structural schematic diagram of another display panel provided by an embodiment of the present application. Referring to FIG. 47, the display panel further includes a display area AA and a non-display area NA surrounding at least part of the display area AA. The display area AA includes a first display area AA1 and a second display area AA2. The second display area AA2 is located at least one side of the first display area AA1 along a second direction Y. The first display area AA1 and the second display area AA2 each include a plurality of data signal lines Data. The non-display area NA includes a fan-out area NA1 located at one side of the display area AA along a first direction X. The fan-out area NA1 includes a plurality of fan-out wires 23. The display panel further includes a data auxiliary line FIAA located at least in the display area AA. The data signal lines Data located in the second display area AA2 are electrically connected to the fan-out wires 23 through the data auxiliary line FIAA.

[0191] The display panel can further include a light emitting element (not shown in the figure), a pixel circuit (not shown in the figure), and a data signal line Data, which are arranged to realize the display function of the display panel. The non-display area NA can include a display controller (not shown in the figure) connected to the data signal line Data, such as a driving chip, etc. The display controller is configured to provide a data signal to the data signal line Data, thereby driving the display panel to realize the display function. The non-display area NA surrounds at least part of the display area AA. The positions of the display area AA and the non-display area NA are not limited in the embodiments of the present application.

[0192] As shown in FIG. 47, in the embodiment, the display area AA can include the first display area AA1 and the second display area AA2. In the figure, the second display area AA2 is exemplarily shown as being located at both sides of the first display area AA1 along the second direction Y, but the present application is not limited thereto. In this arrangement, along the orientation shown in FIG. 47, the second display area AA2 is located between the first display area AA1 and the non-display areas NA on the left and right sides. Along the second direction Y, the first display area AA1 is closer to the center of the display panel, and the second display area AA2 is closer to the edge of the display panel. The non-display area NA includes the fan-out area NA1 located at one side of the display area AA along the first direction X. In the figure, the fan-out area NA1 is exemplarily shown as being located at the lower side. The fan-out area NA1 can be arranged with a plurality of fan-out wires 23 electrically connected to the data signal lines Data, thereby connecting the data signal lines Data to the display controller and ensuring the stable transmission of the data signal.

[0193] Continuing to refer to FIG. 47, a plurality of data signal lines Data are arranged in the first display area AA1 and the second display area AA2. The data signal lines Data arranged in the first display area AA1 are directly electrically connected with the fan-out wires 23, and the data signal lines Data arranged in the second display area AA2 are electrically connected with the fan-out wires 23 through the data auxiliary lines FIAA in the display area AA. In this way, the fan-out wires 23 can be arranged in the fan-out area NA1 below the first display area AA1, thereby reducing the occupied space of the fan-out wires 23, reducing the arrangement area of the fan-out area NA1, effectively reducing the proportion of the non-display area NA, increasing the proportion of the display area AA of the display panel, increasing the display effect of the display panel, and achieving a narrow frame.

[0194] Optionally, in combination with FIGS. 18-28 and 47, the data auxiliary line FIAA includes a first auxiliary part FIAA1, the first auxiliary part FIAA1 extends along the first direction X and is electrically connected with the fan-out wire 23; the light emitting element includes first color light emitting elements R and second color light emitting elements B which are different in light emitting color, the first color light emitting elements R or the second color light emitting elements B include a third virtual symmetry axis ax3, the third virtual symmetry axis ax3 extends along the first direction X; the light emitting element further includes an anode, the anode includes an anode main body part 221; the display panel further includes a pixel definition layer 30 and a plurality of pixel openings 31 arranged in the pixel definition layer 30, along the thickness direction of the display panel, the anode main body part 221 overlaps with the pixel opening 31; and the anode main body part 221 of the first color light emitting element R or the second color light emitting element B is symmetrically arranged about the third virtual symmetry axis ax3; the display panel further includes a substrate 40, the two first auxiliary parts FIAA1 overlapping with the same anode main body part 221 are symmetrically arranged about the third virtual symmetry axis ax3 in the normal projection of the substrate 40 on the plane where the substrate 40 is located.

[0195] As shown in FIGS. 18-28 and 47, the data auxiliary line FIAA can include a first auxiliary part FIAA1 and a second auxiliary part FIAA2, the first auxiliary part FIAA1 extends along the first direction X, and the second auxiliary part FIAA2 extends along the second direction Y, the first auxiliary part FIAA1 can be arranged in the first display area AA1, the first end of the first auxiliary part FIAA1 is connected with the fan-out wire 23, the second end of the first auxiliary part FIAA1 is connected with the first end of the second auxiliary part FIAA2, and the second end of the second auxiliary part FIAA2 extends to the second display area AA2 and is electrically connected with the data signal line Data in the second display area AA2.

[0196] The first auxiliary sub-portion FIAA1 and the second auxiliary sub-portion FIAA2 have different extension directions, and the first auxiliary sub-portion FIAA1 and the second auxiliary sub-portion FIAA2 can be arranged in a manner of penetrating through the film layer to ensure the electrical connection. For example, the first auxiliary sub-portion FIAA1 can be arranged on a side away from the substrate 40 from the second auxiliary sub-portion FIAA2, for example, the first auxiliary sub-portion FIAA1 in FIGS. 18-28 can be arranged on the fourth metal layer M3, and the second auxiliary sub-portion FIAA2 can be arranged on the third metal layer M2.

[0197] With reference to FIGS. 18-28, the first color light emitting element R or the second color light emitting element B includes a third virtual symmetry axis ax3 extending along the first direction X, and the anode main portion 221 of the first color light emitting element R is symmetrical about the third virtual symmetry axis ax3, or the anode main portion 221 of the second color light emitting element B is symmetrical about the third virtual symmetry axis ax3. In the drawings, the anode main portion 221 of the first color light emitting element R and the anode main portion 221 of the second color light emitting element B are both arranged symmetrically about the third virtual symmetry axis ax3, but the present application is not limited thereto.

[0198] As shown in FIGS. 18-28, along the thickness direction of the display panel, at least part of the first auxiliary sub-portion FIAA1 can overlap with the anode main portion 221 of the first color light emitting element R and / or the anode main portion 221 of the second color light emitting element B, and there are at least two first auxiliary sub-portions FIAA1 overlapping with the same anode main portion 221. In the orthographic projection of the plane where the substrate 40 is located, the two first auxiliary sub-portions FIAA1 overlapping with the same anode main portion 221 are symmetrical about the third virtual symmetry axis ax3. As shown in FIGS. 18-28, the data auxiliary line FIAA can be arranged on a side of the anode layer RE close to the substrate 40, the first auxiliary sub-portion FIAA1 is arranged in a film layer below the anode main portion 221, and the two first auxiliary sub-portions FIAA1 are arranged symmetrically about the third virtual symmetry axis ax3, which approximately divides the anode main portion 221 into three equal parts, so that the three parts of the anode main portion 221 divided by the two first auxiliary sub-portions FIAA1 have substantially the same area, thereby avoiding the four-direction color deviation of the display panel. In addition, since the anode main portion 221 can cover part of the first auxiliary sub-portion FIAA1, the metal material first auxiliary sub-portion FIAA1 can avoid changing the transmission direction of light, and the display effect of the display panel can also be ensured.

[0199] Optionally, continuing to refer to FIG. 28, among the two first auxiliary sub-sections FIAA1 and the two data signal lines Data that overlap with the same anode main section 221 in the thickness direction of the display panel, the first auxiliary sub-section FIAA1 and the data signal line Data on the same side of the third virtual axis of symmetry ax3, the data signal line Data is on the side of the first auxiliary sub-section FIAA1 away from the third virtual axis of symmetry ax3.

[0200] Among the two first auxiliary sub-sections FIAA1 and the two data signal lines Data that overlap with the same anode main section 221 in the thickness direction of the display panel, the first auxiliary sub-section FIAA1 and the data signal line Data on the same side of the third virtual axis of symmetry ax3, the data signal line Data is on the side of the first auxiliary sub-section FIAA1 away from the third virtual axis of symmetry ax3.

[0201] Among the two first auxiliary sub-sections FIAA1 and the two data signal lines Data that overlap with the same anode main section 221 in the thickness direction of the display panel, the first auxiliary sub-section FIAA1 and the data signal line Data on the same side of the third virtual axis of symmetry ax3, the data signal line Data is on the side of the first auxiliary sub-section FIAA1 away from the third virtual axis of symmetry ax3.

[0202] Among the two first auxiliary sub-sections FIAA1 and the two data signal lines Data that overlap with the same anode main section 221 in the thickness direction of the display panel, the first auxiliary sub-section FIAA1 and the data signal line Data on the same side of the third virtual axis of symmetry ax3, the data signal line Data is on the side of the first auxiliary sub-section FIAA1 away from the third virtual axis of symmetry ax3.

[0203] Among the two first auxiliary sub-sections FIAA1 and the two data signal lines Data that overlap with the same anode main section 221 in the thickness direction of the display panel, the first auxiliary sub-section FIAA1 and the data signal line Data on the same side of the third virtual axis of symmetry ax3, the data signal line Data is on the side of the first auxiliary sub-section FIAA1 away from the third virtual axis of symmetry ax3.

[0204] In summary, by reasonably setting the overlapping mode of the anode main body part 221 and the first auxiliary part FIAA1 and the data signal line Data, the influence of the first auxiliary part FIAA1 and the data signal line Data at different positions in the display panel on the anode main body part 221 is the same or similar, and the uniformity of display is ensured.

[0205] Optionally, still referring to FIG. 47, in a possible embodiment, the display panel can further include virtual auxiliary lines DF, which include a first virtual auxiliary line DF1 and a second virtual auxiliary line DF2. As shown in FIG. 47, the first virtual auxiliary line DF1 and the second virtual auxiliary line DF2 are both insulated from the data auxiliary line FIAA. The virtual auxiliary line DF can compensate for the length of the data auxiliary line FIAA. For example, the first virtual auxiliary line DF1 can be set to compensate for the first auxiliary part FIAA1, and the second virtual auxiliary line DF2 can be set to compensate for the second auxiliary part FIAA2. That is, by setting the virtual auxiliary line DF, the wiring of the data auxiliary line FIAA setting area is balanced as a whole, the density of the wiring setting in different areas is balanced, and the difference in light reflectivity in different areas of the display panel caused by unbalanced wiring setting is avoided, thereby avoiding the situation that the display effect of the display panel is unbalanced.

[0206] The virtual auxiliary line DF can be electrically connected to the fixed potential end. On the one hand, it can avoid the interference of the display caused by the coupling of the virtual auxiliary line DF with a floating potential to other signals. On the other hand, it can be connected in parallel with the fixed potential end, thereby reducing the resistance on the fixed signal end or the fixed potential signal line, and ensuring that the loss of the fixed potential signal in the transmission process is small.

[0207] Based on the same concept, the embodiment of the present application further provides a display device. FIG. 48 is a structural schematic diagram of a display device provided by an embodiment of the present application. As shown in FIG. 48, the display device includes the display panel 1000 provided by any of the embodiments of the present application, which will not be described here. For example, the display device can be a mobile phone, a computer, a smart wearable device (for example, a smart watch), a vehicle-mounted display device, and the like, and the embodiments of the present application are not limited thereto.

Claims

1. A display panel comprising: a plurality of data signal lines, the plurality of data signal lines extending along a first direction and arranged along a second direction, the first direction and the second direction intersecting; a plurality of first pixel circuits, a plurality of the first pixel circuits arranged along the first direction being electrically connected to a same data signal line; a plurality of first pixel circuit columns and a plurality of first light emitting element columns; the first pixel circuit column comprising a plurality of the first pixel circuits arranged along the first direction; the first light emitting element column comprising two light emitting elements of different light emitting colors arranged along the first direction, and the two light emitting elements of different light emitting colors being electrically connected to the first pixel circuits in different first pixel circuit columns respectively, a plurality of the first pixel circuits in a same first pixel circuit column being electrically connected to a plurality of the light emitting elements of a same color.

2. The display panel of claim 1, further comprising a plurality of first pixel circuit rows and a plurality of first light emitting element rows; the first pixel circuit row comprising a plurality of the first pixel circuits arranged along the second direction; the first light emitting element column comprising a first color light emitting element and a second color light emitting element arranged alternately along the first direction, the first light emitting element row comprising the first color light emitting element and the second color light emitting element arranged alternately along the second direction; the first color light emitting element and the second color light emitting element being different in light emitting color; a plurality of the first pixel circuits in a same first pixel circuit column being electrically connected to the first color light emitting elements in at least two first light emitting element columns arranged adjacently along the second direction, or to the second color light emitting elements in at least two first light emitting element columns arranged adjacently along the second direction; a plurality of the first pixel circuits in a same first pixel circuit row being electrically connected to a plurality of the light emitting elements in a same first light emitting element row.

3. The display panel of claim 2, wherein, at least partially adjacent first pixel circuit columns comprising an ith first pixel circuit column and an (i+1)th first pixel circuit column; At least two first pixel circuits adjacent to each other in the i-th column of first pixel circuit rows include an i-th first pixel circuit and an i-th first pixel circuit. j (j+1) ​​ At least two first pixel circuits adjacent to each other in the (i+1)th column of first pixel circuit rows include a (i+1)th first pixel circuit and a (i+1)th first pixel circuit. j At least two first pixel circuits adjacent to each other in the (i+1)th column of first pixel circuit rows include a (i+1)th first pixel circuit and a (i+1)th first pixel circuit. (j+1) At least two first pixel circuits adjacent to each other in the (i+1)th column of first pixel circuit rows include a at least partially adjacent two first light emitting element columns comprising a pth first light emitting element column and a (p+1)th first light emitting element column; At least two of the light emitting elements in the pth column of the first light emitting element columns include a pth q light emitting element and a pth (q+1) light emitting element. at least partially adjacent The two adjacent light emitting elements include an i q th light emitting element and a (p+1) (q+1) th light emitting element; wherein i, j, p and q are positive integers. The i j The p q The first pixel circuit is electrically connected with the i The i (j+1) The (p+1) (q+1) The (p+1) (q+1) The (p+1) (q+1) The (p+1) (q+1) The (p+1) (q+1) The (p+1) (q+1) The ( The (i+1) j first pixel circuit is electrically connected with the (p+1) q light emitting element. The (i+1) (j+1) first pixel circuit is electrically connected with the p (q+1) th light emitting element.

4. The display panel of claim 3, wherein, the light emitting element comprising an anode, the anode comprising a connected anode main body portion and an anode connection portion; the display panel further comprising a pixel defining layer and a plurality of pixel openings provided in the pixel defining layer, along a thickness direction of the display panel, the anode main body portion overlapping the pixel opening, and the anode connection portion not overlapping the pixel opening. The i-th (j+1) The first pixel circuit and the (p+1)th pixel circuit (q+1) The anode connection portion of each light-emitting element is electrically connected; The (i+1) (j+1) The anode connecting portion of the (i+1) (q+1) The anode connecting portion of the (i+1) th light emitting element is electrically connected.

5. The display panel of claim 4, wherein, The (p+1)th q The anode connection portion of each light-emitting element is located on the side of its anode body portion near the first pixel circuit column of the (i+1)th column; The anode connecting portion of the p (q+1) th light emitting element is located on the side of the anode main portion thereof close to the (i+1)th column of the first pixel circuit column.

6. The display panel of claim 4, wherein, The (p+1)th (q+1) The anode connection portion of each light-emitting element is located on the side of its anode body portion near the first pixel circuit column of the i-th column; The anode connecting portion of the p (q+1) th light emitting element is located on the side of the anode main portion thereof close to the (i+1)th column of the first pixel circuit column.

7. The display panel of claim 4, wherein, The anode connecting portion of the (p+1)th light emitting element includes a first end portion connected to the anode main portion thereof and a second end portion connected to the (i+1)th first pixel circuit, the first end portion being located on the side of the anode main portion thereof away from the (i+1)th column of first pixel circuits; the (i+1)th first pixel circuit is electrically connected to the anode connecting portion of the (p+1)th light emitting element; the anode connecting portion of the (p+1)th light emitting element includes a third end portion connected to the anode main portion thereof and a fourth end portion connected to the (i+1)th first pixel circuit, the third end portion being located on the side of the anode main portion thereof close to the (i+1)th column of first pixel circuits. (q+1) (j+1) (j+1) (q+1) (q+1) (j+1) ​​​​​​ Alternatively, the anode connecting portion of the (p+1)th light emitting element includes a fifth end portion connected to the anode main portion thereof and a sixth end portion connected to the i-th first pixel circuit, the fifth end portion being located at a side of the anode main portion thereof close to the i-th column of first pixel circuits; the (i+1)th first pixel circuit includes a seventh end portion connected to the sixth end portion of the (p+1)th light emitting element and an eighth end portion connected to the (i+1)th light emitting element; and the (i+2)th first pixel circuit includes a ninth end portion connected to the eighth end portion of the (i+1)th light emitting element and a tenth end portion connected to the (i+2)th light emitting element. (q+1) (j+1) (j+1) ​​​ Pixel circuit and the p-th (q+1) The anode connection of the p-th light-emitting element is electrically connected. (q+1) The anode connection portion of the light-emitting element includes a seventh end connected to its anode body portion and an end connected to the (i+1)th... (j+1) The seventh end is located on the side of its anode body away from the (i+1)th column of the first pixel circuit connected to the eighth end of the first pixel circuit.

8. The display panel of claim 4, further comprising a substrate and a dummy connection structure; The virtual connection structure is located on the side of the anode main portion of the pth light emitting element in the orthogonal projection of the plane where the substrate is located. q The virtual connection structure is located on the side of the anode main portion of the pth light emitting element in the orthogonal projection of the plane where the substrate is located. The virtual connection structure is located on the side of the substrate where the anode main portion of the (p+1) q th light emitting element is located. The virtual connection structure is located on the side of the normal projection of the anode main portion of the pth light emitting element on the plane of the substrate, and the virtual connection structure is located on the side of the normal projection of the anode main portion of the (p+1)th light emitting element on the plane of the substrate. q The virtual connection structure is located on the side of the normal projection of the anode main portion of the pth light emitting element on the plane of the substrate, and the virtual connection structure is located on the side of the normal projection of the anode main portion of the (p+1)th light emitting element on the plane of the substrate. q The virtual connection structure is located on the side of the normal projection of the anode main portion of the pth light emitting element on the plane of the substrate, and the virtual connection structure is located on the side of the normal projection of the anode main portion of the (p+1)th light emitting element on the plane of the substrate.

9. The display panel of claim 8, wherein, the dummy connection structure and the anode connection portion being staggered in at least one of the first direction and the second direction.

10. The display panel of claim 8, wherein, the dummy connection structure and the anode connection portion being provided in a same layer.

11. The display panel of claim 8, wherein, the p q th light emitting element is present between the orthographic projection of the anode main portion of the p q th light emitting element and the orthographic projection of the dummy connection structure on the plane on which the substrate lies. or the (p+1) q the anode main portion of the (p+1) th light emitting element has a break between a footprint on a plane where the substrate is located and a footprint on the plane where the substrate is located of the virtual connection structure; or The pth q There is a break between the orthographic projection of the anode body of the light-emitting element onto the plane of the substrate and the orthographic projection of the virtual connection structure onto the plane of the substrate, and the (p+1)th... q There is a break between the orthographic projection of the anode body of the light-emitting element onto the plane of the substrate and the orthographic projection of the virtual connection structure onto the plane of the substrate.

12. The display panel of claim 8, wherein, The pth q The anode body portion of the first light-emitting element and the (p+1)th light-emitting element q At least one of the anode bodies of the light-emitting elements is electrically connected to the virtual connection structure.

13. The display panel of claim 2, wherein, At least part of the first pixel circuit columns adjacent to each other include an hth first pixel circuit column, an (h+1)th first pixel circuit column, an (h+2)th first pixel circuit column, and an (h+3)th first pixel circuit column; The at least partially adjacent two first pixel circuits in the h-th column of the first pixel circuit include the h-th column. k The first pixel circuit and the h-th (k+1) A first pixel circuit; at least two partially adjacent first pixel circuits in the (h+1)th column of the first pixel circuit include the (h+1)th... k The first pixel circuit and the (h+1)th pixel circuit (k+1) A first pixel circuit, wherein at least two partially adjacent first pixel circuits in the (h+2)th column of the first pixel circuit include the (h+2)th column. k The first pixel circuit and the (h+2)th pixel circuit (k+1) A first pixel circuit; at least two partially adjacent first pixel circuits in the (h+3)th column of the first pixel circuit include the (h+3)th column. k The first pixel circuit and the (h+3)th pixel circuit (k+1) The first pixel circuit; At least part of the four first light emitting element columns adjacent to each other include an mth first light emitting element column, an (m+1)th first light emitting element column, an (m+2)th first light emitting element column, and an (m+3)th first light emitting element column; At least two of the light emitting elements adjacent to each other in the mth column of the first light emitting element columns include an mth light emitting element and an (m+1)th light emitting element. n At least two of the light emitting elements adjacent to each other in the mth column of the first light emitting element columns include an mth light emitting element and an (m+1)th light emitting element. (n+1) At least two of the light emitting elements adjacent to each other in the At least two of the light emitting elements in the (m+1)th column of the first light emitting element columns that are adjacent to each other include an (m+1)th light emitting element and an (m+1)th light emitting element. n (n+1) ​​ At least two of the light emitting elements in the (m+2)th column of the first light emitting element columns that are adjacent to each other include an (m+2)th light emitting element and an (m+2)th light emitting element. n (n+1) ​​ In the (m+3)th column of the first light-emitting element column, at least two adjacent light-emitting elements include the (m+3)th light-emitting element. n The first light-emitting element and the (m+3)th light-emitting element (n+1) There are 3 light-emitting elements; where h, k, m, and n are all positive integers; The h k The m n The first pixel circuit is electrically connected with the m The h (k+1) The first h (n+1) The (m+1) th light emitting element is electrically connected with the first pixel circuit. The (h+1) k The (m+1) n The (m+1) The (h+1) (k+1) first pixel circuit is electrically connected with the m (n+1) light emitting element. The (h+2) k The (m+3) n The (m+3) The (h+2) (k+1) The (m+2) (n+1) The (m+2) The (h+3) k The (m+2) n The (m+2) The (h+3) (k+1) The (m+3) (n+1) The (m+3) 14. The display panel of claim 13, wherein, The light emitting element includes an anode, the anode includes a connected anode main body part and an anode connecting part; the display panel further includes a pixel defining layer and a plurality of pixel openings arranged in the pixel defining layer, along the thickness direction of the display panel, the anode main body part overlaps the pixel opening, and the anode connecting part does not overlap the pixel opening; The h (k+1) The first pixel circuit is electrically connected with the anode connecting portion of the (m+1) (n+1) th light emitting element. the (h+2) k first pixel circuit is connected to the anode of the (m+3) n emitting element The connecting part is electrically connected.

15. The display panel of claim 7 or 14, wherein, The anode connecting part is arranged in the same layer as the anode main body part; Alternatively, the display panel further includes a substrate, the film layer where the anode connecting part is located is between the film layer where the anode main body part is located and the film layer where the substrate is located.

16. The display panel of claim 15, wherein, The film layer where the anode connecting part is located is between the film layer where the anode main body part is located and the film layer where the substrate is located; Along the thickness direction of the display panel, at least part of the anode connecting part overlaps the anode main body part.

17. The display panel of claim 16, wherein, Along the thickness direction of the display panel, the anode main body part overlapping the anode connecting part includes a first anode main body part; The first anode main body part includes a first virtual symmetry axis, and the first anode main body part is symmetrically arranged about the first virtual symmetry axis; Along the thickness direction of the display panel, one of the anode connecting parts overlaps the first anode main body part, and the anode connecting part overlaps the first virtual symmetry axis.

18. The display panel of claim 16, wherein, Along the thickness direction of the display panel, the anode main body part overlapping the anode connecting part includes a second anode main body part; Along the thickness direction of the display panel, two of the anode connecting parts overlap the second anode main body part; The second anode main body part includes a second virtual symmetry axis, and the projections of the parts where the two anode connecting parts overlap the second anode main body part on the plane where the substrate is located are symmetrically arranged about the projection of the second virtual symmetry axis on the plane where the substrate is located.

19. The display panel of claim 7 or 14, further comprising a light-transmitting hole, the light-transmitting hole penetrating at least part of the film layers in the display panel; the light-transmitting hole is arranged to transmit external light to a light-sensing element; Along the thickness direction of the display panel, the anode connecting part does not overlap the light-transmitting hole.

20. The display panel of claim 15, wherein, The anode connecting part is located between the film layer where the anode main body part is located and the film layer where the substrate is located; The first pixel circuit includes at least one transistor, and the transistor includes a first active layer; The first pixel circuit further includes a storage capacitor, and the storage capacitor includes a first plate and a second plate arranged opposite to each other, and the second plate is located on the side of the first plate away from the first active layer; The display panel further includes a first semiconductor layer, a first metal layer, a second metal layer, and a third metal The first active layer is located in the first semiconductor layer, the first plate is located in the first metal layer, the second plate is located in the second metal layer, and the third metal layer is located on a side of the second metal layer away from the first active layer. The anode connecting part is located in at least one of the first metal layer, the second metal layer, or the third metal layer.

21. The display panel of claim 15, wherein, The anode connecting part is located between the film layer where the anode main body part is located and the film layer where the substrate is located. The pixel circuit comprises at least one transistor, and the transistor comprises a first active layer. The pixel circuit further comprises a storage capacitor, and the storage capacitor comprises a first plate and a second plate arranged oppositely, and the second plate is located on a side of the first plate away from the first active layer. The display panel further comprises a first semiconductor layer, a first metal layer, a second metal layer, a third metal layer, and a fourth metal layer. The first active layer is located in the first semiconductor layer, the first plate is located in the first metal layer, the second plate is located in the second metal layer, and the third metal layer is located on a side of the second metal layer away from the first active layer. The anode connecting part is located in at least one of the first metal layer, the second metal layer, the third metal layer, or the fourth metal layer.

22. The display panel of claim 15, wherein, The anode connecting part is located between the film layer where the anode main body part is located and the film layer where the substrate is located. The first pixel circuit comprises at least one first-type transistor and at least one second-type transistor, the first-type transistor comprises a first active layer, and the second-type transistor comprises a second active layer and a top gate located on a side of the second active layer away from the first active layer. The first pixel circuit further comprises a storage capacitor, and the storage capacitor comprises a first plate and a second plate arranged oppositely, and the second plate is located on a side of the first plate away from the first active layer. The display panel further comprises a first semiconductor layer, a first metal layer, a second metal layer, a second semiconductor layer, a fifth metal layer, a third metal layer, and a fourth metal layer; the first active layer is located in the first semiconductor layer, the first plate is located in the first metal layer, the second plate is located in the second metal layer, the second active layer is located in the second semiconductor layer, the top gate is located in the fifth metal layer, and the third metal layer is located on a side of the fifth metal layer away from the first active layer. The fourth metal layer is located on a side of the third metal layer away from the first active layer. The anode connecting part is located in at least one of the first metal layer, the second metal layer, the second semiconductor layer, the fifth metal layer, the third metal layer, or the fourth metal layer. 23.The display panel of claim 2, further comprising a plurality of second pixel circuit columns and a plurality of second pixel circuit rows, the second pixel circuit columns comprising a plurality of second pixel circuits arranged along the first direction, and the second pixel circuit rows comprising a plurality of the second pixel circuits arranged along the second direction; the second pixel circuit columns being electrically connected to the same data signal lines. The display panel further comprises a plurality of second light emitting element columns and a plurality of second light emitting element rows, the second light emitting element columns comprising a plurality of third color light emitting elements arranged along the first direction, and the second light emitting element rows comprising a plurality of the third color light emitting elements arranged along the second direction; the third color light emitting elements having a light emitting color different from those of the first color light emitting elements and the second color light emitting elements. The plurality of the second pixel circuits in the same second pixel circuit column are electrically connected to the plurality of the third color light emitting elements in the same second light emitting element column, and the plurality of the second pixel circuits in the same second pixel circuit row are electrically connected to the plurality of the third color light emitting elements in the same second light emitting element row. 24.The display panel of claim 23, wherein Along the first direction, the first light emitting element rows and the second light emitting element rows are arranged alternately. Along the second direction, the first light emitting element columns and the second light emitting element columns are arranged alternately.

25. The display panel of claim 23, wherein, The plurality of the first color light emitting elements and the plurality of the second color light emitting elements form a first virtual quadrilateral, the first color light emitting elements being at first vertices of the first virtual quadrilateral, the second color light emitting elements being at second vertices of the first virtual quadrilateral, and the third color light emitting elements being inside the first virtual quadrilateral. The plurality of the third color light emitting elements form a second virtual quadrilateral, the plurality of the third color light emitting elements being at vertices of the second virtual quadrilateral respectively, and the first color light emitting elements or the second color light emitting elements being inside the second virtual quadrilateral. The first color light emitting elements comprise one of red light emitting elements and blue light emitting elements, and the second color light emitting elements comprise the other of red light emitting elements and blue light emitting elements. The third color light emitting elements comprise green light emitting elements. 26.The display panel of claim 1, further comprising a display area and a non-display area at least partially surrounding the display area, the display area comprising a first display area and a second display area, the second display area being located at least one side of the first display area along the second direction; the first display area and the second display area each comprising a plurality of the data signal lines; and the non-display area comprising a fan-out area located at one side of the display area along the first direction, the fan-out area comprising a plurality of fan-out wirings. The display panel further comprises data auxiliary lines at least in the display area, the data signal lines in the second display area being electrically connected to the fan-out wirings through the data auxiliary lines.

27. The display panel of claim 26, wherein, The data auxiliary lines include a first auxiliary branch extending along the first direction and electrically connected with the fan-out wire; The light emitting elements include first color light emitting elements and second color light emitting elements with different light emitting colors, the first color light emitting elements or the second color light emitting elements include a third virtual symmetry axis extending along the first direction; The light emitting elements further include an anode including an anode main body portion; the display panel further includes a pixel defining layer and a plurality of pixel openings provided in the pixel defining layer, the anode main body portion overlaps with the pixel openings in a thickness direction of the display panel; and the anode main body portion of the first color light emitting elements or the second color light emitting elements is symmetrically arranged about the third virtual symmetry axis of the first color light emitting elements or the second color light emitting elements in which the anode main body portion is located. The display panel further includes a substrate, the two first auxiliary branches overlapping with the same anode main body portion are symmetrically arranged about the third virtual symmetry axis of the first color light emitting elements or the second color light emitting elements in which the same anode main body portion is located in a normal projection of a plane in which the substrate is located.

28. The display panel of claim 27, wherein, In the thickness direction of the display panel, among the two first auxiliary branches and the two data signal lines overlapping with the same anode main body portion, the first auxiliary branch and the data signal line located on the same side of the third virtual symmetry axis, the data signal line is located on the side of the first auxiliary branch close to the third virtual symmetry axis.

29. The display panel of claim 27, wherein, In the thickness direction of the display panel, among the two first auxiliary branches and the two data signal lines overlapping with the same anode main body portion, the first auxiliary branch and the data signal line located on the same side of the third virtual symmetry axis, the data signal line is located on the side of the first auxiliary branch away from the third virtual symmetry axis.

30. A display device comprising the display panel of any one of claims 1-29.

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