Display panel and display apparatus

Abstract

The present application provides a display panel and a display apparatus. The display panel comprises first-type pixels and second-type pixels. Each first-type pixel comprises a first sub-pixel of a first color, and each second-type pixel comprises a second sub-pixel of the first color. The display panel further comprises a substrate, a device layer, and a light regulation layer. The device layer is arranged on a side of the substrate. The light regulation layer is located on the side of the device layer distant from the substrate, and the light regulation layer comprises a plurality of light regulation portions. The first sub-pixel has a first orthographic projection on the substrate, and the second sub-pixel has a second orthographic projection on the substrate. The orthographic projection of a light regulation portion on the substrate at least partially overlaps the first orthographic projection. The ratio of the perimeter to the area corresponding to the first orthographic projection is greater than the ratio of the perimeter to the area corresponding to the second orthographic projection. In embodiments of the present application, a privacy protection effect corresponding to first sub-pixels can be improved.

Description

Display panel and display device

[0001] Cross Reference to Related Applications

[0002] This application claims priority to Chinese Patent Application 202411259179.2, filed September 9, 2024, entitled “Display panel and display device”, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0003] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0004] In order to improve the display effect of the display panel, in the related technology, there is a case that different color sub-pixels receive data signals transmitted by the same data signal line. This kind of setting mode increases the power consumption of the display panel.

[0005] SUMMARY

[0006] The present application provides a display panel and a display device to reduce the power consumption of the display panel while ensuring the display effect.

[0007] According to an aspect of the present application, a display panel is provided, comprising a display area, the display area comprising a plurality of pixel circuits arranged in an array, the plurality of pixel circuits comprising a first pixel circuit, a second pixel circuit and a third pixel circuit;

[0008] The first pixel circuit, the second pixel circuit and the third pixel circuit are respectively connected to different color light emitting elements;

[0009] The display panel further comprises a plurality of data signal lines, the plurality of data signal lines comprising a first data signal line, a second data signal line and a third data signal line;

[0010] The first data signal line is electrically connected to the first pixel circuit, the second data signal line is electrically connected to the second pixel circuit, and the third data signal line is electrically connected to the third pixel circuit.

[0011] According to another aspect of the present application, a display device is provided, comprising the display panel of the first aspect.

[0012] The display panel and the display device provided by the embodiments of the present application make one data signal line only connected to sub-pixels emitting the same color light, so that the data signal line only needs to transmit data signals corresponding to one color sub-pixel, thereby reducing the frequency and amplitude of data signal jump on a single data signal line, and further reducing the power consumption of the integrated circuit (IC) providing the data signals, which is conducive to reducing the overall power consumption of the display panel.

[0013] It is to be understood that the details described in this section are not intended to identify key or critical elements of the embodiments of the application or to limit the scope of the application. Other features of the present application will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments description. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained from these drawings without any creative effort.

[0015] FIG. 1 is a structural schematic diagram of a display panel in the related art;

[0016] FIG. 2 is a data signal timing diagram of a data signal line in the display panel shown in FIG. 1;

[0017] FIG. 3 is a structural schematic diagram of a display panel provided by an embodiment of the present application;

[0018] FIG. 4 is a structural schematic diagram of a pixel circuit provided by an embodiment of the present application;

[0019] FIG. 5 is a sectional structural schematic diagram of a sub-pixel provided by an embodiment of the present application;

[0020] FIG. 6 is a data signal timing diagram of a data signal line provided by an embodiment of the present application;

[0021] FIG. 7 is a structural schematic diagram of another display panel provided by an embodiment of the present application;

[0022] FIG. 8 is a structural schematic diagram of still another display panel provided by an embodiment of the present application;

[0023] FIG. 9 is a structural schematic diagram of still another display panel provided by an embodiment of the present application;

[0024] FIG. 10 is a partial sectional structural schematic diagram of a display panel provided by an embodiment of the present application;

[0025] FIG. 11 is a structural schematic diagram of still another display panel provided by an embodiment of the present application;

[0026] FIG. 12 is a structural schematic diagram of still another display panel provided by an embodiment of the present application;

[0027] FIG. 13 is a partial sectional structural schematic diagram of another display panel provided by an embodiment of the present application;

[0028] FIG. 14 is a partial sectional structural schematic diagram of still another display panel provided by an embodiment of the present application;

[0029] FIG. 15 is a structural schematic diagram of another display panel according to an embodiment of the present application;

[0030] FIG. 16 is a structural schematic diagram of another display panel according to an embodiment of the present application;

[0031] FIG. 17 is a structural schematic diagram of another display panel according to an embodiment of the present application;

[0032] FIG. 18 is a structural schematic diagram of another display panel according to an embodiment of the present application;

[0033] FIG. 19 is a structural schematic diagram of another display panel according to an embodiment of the present application;

[0034] FIG. 20 is a structural schematic diagram of another display panel according to an embodiment of the present application;

[0035] FIG. 21 is a structural schematic diagram of another display panel according to an embodiment of the present application;

[0036] FIG. 22 is a structural schematic diagram of another display panel according to an embodiment of the present application;

[0037] FIG. 23 is a signal timing diagram provided to the pixel circuit shown in FIG. 4 in one driving period according to an embodiment of the present application;

[0038] FIG. 24 is a structural schematic diagram of a film layer of a display panel according to an embodiment of the present application;

[0039] FIG. 25 is a structural schematic diagram of a first semiconductor layer of the display panel shown in FIG. 24;

[0040] FIG. 26 is a structural schematic diagram of a first metal layer of the display panel shown in FIG. 24;

[0041] FIG. 27 is a structural schematic diagram of a second metal layer of the display panel shown in FIG. 24;

[0042] FIG. 28 is a structural schematic diagram of a second semiconductor layer of the display panel shown in FIG. 24;

[0043] FIG. 29 is a structural schematic diagram of a third metal layer of the display panel shown in FIG. 24;

[0044] FIG. 30 is a structural schematic diagram of a fourth metal layer of the display panel shown in FIG. 24;

[0045] FIG. 31 is a structural schematic diagram of a fifth metal layer of the display panel shown in FIG. 24;

[0046] FIG. 32 is a structural schematic diagram of a sixth metal layer of the display panel shown in FIG. 24;

[0047] FIG. 33 is a structural diagram of an anode layer in the display panel shown in FIG. 24;

[0048] FIG. 34 is a structural diagram of a partial film layer in the display panel shown in FIG. 24;

[0049] FIG. 35 is a structural diagram of a complete film layer in the display panel shown in FIG. 24;

[0050] FIG. 36 is a structural diagram of a pixel circuit in the display panel shown in FIG. 24;

[0051] FIG. 37 is a structural diagram of a partial film layer of a pixel circuit in the display panel shown in FIG. 24;

[0052] FIG. 38 is a structural diagram of another display panel according to an embodiment of the present application;

[0053] FIG. 39 is a structural diagram of another display panel according to an embodiment of the present application;

[0054] FIG. 40 is a structural diagram of another display panel according to an embodiment of the present application;

[0055] FIG. 41 is a structural diagram of another display panel according to an embodiment of the present application;

[0056] FIG. 42 is a structural diagram of another display panel according to an embodiment of the present application;

[0057] FIG. 43 is a structural diagram of another display panel according to an embodiment of the present application;

[0058] FIG. 44 is a structural diagram of another display panel according to an embodiment of the present application;

[0059] FIG. 45 is a structural diagram of another partial film layer in the display panel shown in FIG. 24;

[0060] FIG. 46 is a structural diagram of another display panel according to an embodiment of the present application;

[0061] FIG. 47 is a structural diagram of another display panel according to an embodiment of the present application;

[0062] FIG. 48 is a structural diagram of a partial cross-section of another display panel according to an embodiment of the present application;

[0063] FIG. 49 is a structural diagram of a partial cross-section of another display panel according to an embodiment of the present application;

[0064] FIG. 50 is a structural diagram of another display panel according to an embodiment of the present application;

[0065] FIG. 51 is a structural schematic diagram of another display panel according to an embodiment of the present application;

[0066] FIG. 52 is a structural schematic diagram of another display panel according to an embodiment of the present application;

[0067] FIG. 53 is a structural schematic diagram of another display panel according to an embodiment of the present application;

[0068] FIG. 54 is a structural schematic diagram of another display panel according to an embodiment of the present application;

[0069] FIG. 55 is a structural schematic diagram of another display panel according to an embodiment of the present application;

[0070] FIG. 56 is a partial cross-sectional structural schematic diagram of another display panel according to an embodiment of the present application;

[0071] FIG. 57 is a structural schematic diagram of another display panel according to an embodiment of the present application;

[0072] FIG. 58 is a structural schematic diagram of another display panel according to an embodiment of the present application;

[0073] FIG. 59 is a structural schematic diagram of another pixel circuit according to an embodiment of the present application;

[0074] FIG. 60 is a signal timing diagram of the pixel circuit shown in FIG. 59 in one driving period according to an embodiment of the present application;

[0075] FIG. 61 is a structural schematic diagram of a film layer of another display panel according to an embodiment of the present application;

[0076] FIG. 62 is a structural schematic diagram of a first semiconductor layer of the display panel shown in FIG. 61 according to an embodiment of the present application;

[0077] FIG. 63 is a structural schematic diagram of a first metal layer of the display panel shown in FIG. 61 according to an embodiment of the present application;

[0078] FIG. 64 is a structural schematic diagram of a second metal layer of the display panel shown in FIG. 61 according to an embodiment of the present application;

[0079] FIG. 65 is a structural schematic diagram of a fourth metal layer of the display panel shown in FIG. 61 according to an embodiment of the present application;

[0080] FIG. 66 is a structural schematic diagram of a fifth metal layer of the display panel shown in FIG. 61 according to an embodiment of the present application;

[0081] FIG. 67 is a structural schematic diagram of a sixth metal layer of the display panel shown in FIG. 61 according to an embodiment of the present application;

[0082] FIG. 68 is a structural schematic diagram of an anode layer of the display panel shown in FIG. 61 according to an embodiment of the present application;

[0083] Figure 69 is a schematic diagram of a stack structure of all film layers in the display panel shown in Figure 61;

[0084] Figure 70 is a schematic diagram of a film layer structure of a pixel circuit in the display panel shown in Figure 61;

[0085] Figure 71 is a schematic diagram of a partial film layer structure of a pixel circuit in the display panel shown in Figure 61;

[0086] Figure 72 is a schematic diagram of a film layer structure of a pixel circuit provided by an embodiment of the present application;

[0087] Figure 73 is a schematic diagram of a film layer structure of another pixel circuit provided by an embodiment of the present application;

[0088] Figure 74 is a schematic diagram of a structure of yet another display panel provided by an embodiment of the present application;

[0089] Figure 75 is a schematic diagram of a structure of yet another display panel provided by an embodiment of the present application;

[0090] Figure 76 is a schematic diagram of a film layer structure of yet another pixel circuit provided by an embodiment of the present application;

[0091] Figure 77 is a schematic diagram of a structure of yet another display panel provided by an embodiment of the present application;

[0092] Figure 78 is a schematic diagram of a film layer structure of yet another pixel circuit provided by an embodiment of the present application;

[0093] Figure 79 is a schematic diagram of a stack structure of a partial film layer in the display panel shown in Figure 24;

[0094] Figure 80 is a schematic diagram of a stack structure of a partial film layer in the display panel shown in Figure 61;

[0095] Figure 81 is a schematic diagram of an overlapping relationship between a third power signal line and a green light emitting element provided by an embodiment of the present application;

[0096] Figure 82 is a schematic diagram of an overlapping relationship between a first power signal line and a green light emitting element provided by an embodiment of the present application;

[0097] Figure 83 is a schematic diagram of an overlapping relationship between another first power signal line and a green light emitting element provided by an embodiment of the present application;

[0098] Figure 84 is a schematic diagram of a structure of a display device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0099] In order to better understand the technical scheme of the present application, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts should fall within the scope of the present application.

[0100] It should be noted that the terms "first", "second" and the like in the description and claims of the present application and the above drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or a chronological sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device that includes a series of steps or units need not be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0101] FIG. 1 is a structural schematic diagram of a display panel in the related art provided by an embodiment of the present application, and FIG. 2 is a data signal timing diagram of a data signal line in the display panel shown in FIG. 1. As shown in FIG. 1 and FIG. 2, in order to improve the display effect of the display panel, there is a case where different color sub-pixels are located in the same pixel column. In the related art, different color sub-pixels in one sub-pixel column are connected to the same data signal line and receive data signals transmitted by the same data signal line, so that there is a case where different color sub-pixels share the same data signal line.

[0102] For example, as shown in FIG. 1, four columns of sub-pixels are connected to four data signal lines, and the four data signal lines are S1, S2, S3 and S4 in turn. The first column and the third column of sub-pixel columns include red sub-pixels R and blue sub-pixels B, and the red sub-pixels R and the blue sub-pixels B in the first column and the third column of sub-pixel columns are connected to the same data signal line.

[0103] FIG. 2 exemplarily shows a timing diagram of data signals data on the data signal line S1. As shown in FIG. 1 and FIG. 2, the inventors have found through research that, when the display panel is displaying, the data signal line S1 needs to provide corresponding data signals data to the red sub-pixels R and the blue sub-pixels B respectively. Since the corresponding data signals data of the red sub-pixels R and the blue sub-pixels B are usually different, the data signals data on the data signal line S1 will jump between the data signals data corresponding to the red sub-pixels R and the data signals data corresponding to the blue sub-pixels B.

[0104] For example, taking the display of a red picture as an example, when scanning the first row of sub-pixels, the data signal line S1 provides a high-level data signal data to the red sub-pixel R, when scanning the second row of sub-pixels, the data signal line S1 provides a low-level data signal data to the blue sub-pixel B, and so on. In this way, the data signal data on the data signal line S1 will jump between different levels.

[0105] Each jump of the data signal on the data signal line will cause the load capacitance on the data signal line to be charged or discharged, thereby consuming part of the energy, and further causing the integrated circuit (IC) providing the data signal to the data signal line to need to provide a large amount of current to charge or discharge the load capacitance on the data signal line in a short time, greatly increasing the power consumption of the IC.

[0106] Further, the increased power consumption power1 of the IC can satisfy the following formula: power1=Vdd2*Cloading*f;

[0107] Wherein, Vdd is the voltage variation range on the data signal line, Cloading is the load capacitance of the data signal line, and f is the frequency of the rising edge or falling edge of the data signal.

[0108] From the above formula, it can be seen that the voltage jump on the data signal line will increase the power consumption of the IC, and the higher the jump frequency and the larger the jump amplitude, the higher the increased power consumption of the IC.

[0109] Based on the above technical problems, FIG. 3 is a structural schematic diagram of a display panel provided by an embodiment of the present application, and FIG. 4 is a structural schematic diagram of a pixel circuit provided by an embodiment of the present application. As shown in FIGS. 3 and 4, the display panel provided by the embodiment of the present application includes a display area AA, the display area AA includes a plurality of pixel circuits 10 arranged in an array, the plurality of pixel circuits 10 includes a first pixel circuit 101, a second pixel circuit 102 and a third pixel circuit 103, and the first pixel circuit 101, the second pixel circuit 102 and the third pixel circuit 103 are respectively connected to light emitting elements 20 of different colors. The display panel further includes a plurality of data signal lines 30, the plurality of data signal lines 30 includes a first data signal line 301, a second data signal line 302 and a third data signal line 303, the first data signal line 301 is electrically connected to the first pixel circuit 101, the second data signal line 302 is electrically connected to the second pixel circuit 102, and the third data signal line 303 is electrically connected to the third pixel circuit 103.

[0110] Specifically, the display area AA is provided with an array of a plurality of pixel circuits 10 and an array of a plurality of light emitting elements 20, the plurality of pixel circuits 10 and the plurality of light emitting elements 20 are correspondingly electrically connected, the pixel circuit 10 is used to transmit a driving current to the light emitting element 20 under the action of a signal of a signal line (such as a scanning signal line, a data signal line, a power signal line, etc.) on the display panel, so as to drive the light emitting element 20 to emit light. Wherein, the light emitting element 20 and the pixel circuit 10 electrically connected therewith jointly constitute a sub-pixel of the display panel, a plurality of sub-pixels are arranged according to a certain rule, and the display of a complete image can be realized by accurately controlling the brightness of different sub-pixels.

[0111] It should be noted that the arrangement mode of the plurality of pixel circuits 10 and the plurality of light emitting elements 20 can be set according to actual needs, and the present embodiment does not make specific limitation.

[0112] FIG. 5 is a schematic view of a cross-sectional structure of a sub-pixel according to an embodiment of the present application. As shown in FIG. 5, optionally, the pixel circuit 10 can include at least one thin film transistor T, wherein the thin film transistor T can include an active layer 1, a gate 2 and a source-drain electrode 3 arranged in layers.

[0113] The light emitting element 20 can include an organic light emitting diode (OLED), a micro light emitting diode (such as a Micro-LED, a Mini-LED) or other types of light emitting devices, and the present embodiment does not make specific limitation.

[0114] Continuing to refer to FIG. 5, optionally, taking an organic light emitting diode as an example, the light emitting element 20 can include an anode 111, a light emitting layer 112 and a cathode 113 arranged in layers, when the pixel circuit 10 provides a driving current for the light emitting element 20, electrons are injected into the light emitting layer 112 through the cathode 113, and holes are injected into the light emitting layer 112 through the anode 111, the electrons and holes recombine in the light emitting layer 112 to release energy, so that the light emitting layer 112 emits visible light.

[0115] Wherein, by setting different materials of the light emitting layer 112, different colors of visible light can be emitted.

[0116] For example, the light emitting element 20 can include a red light emitting element for emitting red light, a blue light emitting element for emitting blue light and a green light emitting element for emitting green light, to realize color image display, but is not limited thereto, in some embodiments, the light emitting element 20 can also include a white light emitting element for emitting white light, and the present embodiment does not make specific limitation.

[0117] Further, the pixel circuit 10 comprises a first pixel circuit 101, a second pixel circuit 102 and a third pixel circuit 103, wherein the first pixel circuit 101, the second pixel circuit 102 and the third pixel circuit 103 are connected with the light emitting elements 20 of different colors respectively, so as to form sub-pixels emitting light of different colors.

[0118] With continuous reference to FIG. 3 and FIG. 4, the display panel is further provided with a plurality of data signal lines 30, which are used to provide data signals for the pixel circuits 10.

[0119] With continuous reference to FIG. 4, the pixel circuit 10 comprises a driving transistor T3 for providing a driving current for the light emitting element 20, the driving transistor T3 and the light emitting element 20 are connected in series between a first power signal line and a second power signal line, both of which are used to transmit a power voltage, and the power voltage on the first power signal line can be greater than the power voltage on the second power signal line, wherein the driving current is generated by the potential difference between the first power signal line and the second power signal line, so as to drive the light emitting element 20 to emit light.

[0120] The working process of the pixel circuit 10 can comprise a data writing stage, in which the data signal line 30 writes a data signal to the gate of the driving transistor T3, and the driving transistor T3 is turned on according to the voltage of the data signal written to its gate, and the driving current formed by the turn-on of the driving transistor T3 is used to drive the light emitting element 20 to emit light.

[0121] It can be understood that the gate potential of the driving transistor T3 determines the size of the driving current formed by its turn-on, and the size of the driving current can determine the luminance of the light emitting element 20, so that the luminance of the light emitting element 20 can be adjusted by controlling the gate potential of the driving transistor T3 through the data signal, thereby controlling the display gray scale of the sub-pixel.

[0122] Further, the data signal line 30 comprises a first data signal line 301, a second data signal line 302 and a third data signal line 303, wherein the first data signal line 301 is electrically connected with the first pixel circuit 101, the second data signal line 302 is electrically connected with the second pixel circuit 102, and the third data signal line 303 is electrically connected with the third pixel circuit 103. Among them, one data signal line is only connected with the pixel circuits 10 in the sub-pixels emitting light of the same color, so that one data signal line only needs to transmit the data signal corresponding to one color sub-pixel, so that the frequency and amplitude of the data signal jump on a single data signal line can be reduced, thereby reducing the power consumption of the integrated circuit (IC) providing the data signal, and further reducing the overall power consumption of the display panel.

[0123] For example, FIG. 6 is a timing diagram of a data signal on a data signal line according to an embodiment of the present application. For example, FIG. 6 shows a timing diagram of a data signal data on the first data signal line 301. As shown in FIG. 6, the first data signal line 301 provides a data signal for the red sub-pixel. When the display panel displays a red image, the first data signal line 301 only needs to provide a high-level data signal data for the red sub-pixel. In this way, the data signal data on the first data signal line 301 only needs to remain at the same potential and does not need to jump. As a result, the frequency and amplitude of the data signal data on the first data signal line 301 are reduced, and the power consumption of the integrated circuit (IC) that provides the data signal is reduced.

[0124] Similarly, the second data signal line 302 and the third data signal line 303 provide data signals for sub-pixels of other colors except the red sub-pixel. Therefore, when the display panel displays a red image, the second data signal line 302 and the third data signal line 303 only need to provide low-level data signals. In this way, the second data signal line 302 and the third data signal line 303 also only need to remain at the same potential and do not need to jump. As a result, the frequency and amplitude of the data signal on the second data signal line 302 and the third data signal line 303 are reduced, and the power consumption of the integrated circuit (IC) that provides the data signal is reduced.

[0125] According to the test results, Table 1 shows the reduced power consumption of the integrated circuit (IC) when the display panel displays different images according to the scheme provided by the embodiment of the present application.

[0126] Table 1 shows the reduced power consumption of the integrated circuit (IC) when the display panel displays different images according to the scheme provided by the embodiment of the present application.

[0127] As shown in Table 1, according to the scheme provided by the embodiment of the present application, the integrated circuit (IC) can reduce the overall power consumption by about 25% when the display panel displays different images.

[0128] In summary, the display panel provided by the embodiment of the present application has the following advantages. One data signal line is connected to sub-pixels that emit the same color light. As a result, the data signal line only needs to transmit data signals corresponding to sub-pixels of one color. The frequency and amplitude of the data signal on the data signal line are reduced, and the power consumption of the integrated circuit (IC) that provides the data signal is reduced. This is conducive to reducing the overall power consumption of the display panel.

[0129] Continuing to refer to FIG. 3, alternatively, the plurality of pixel circuits 10 form a plurality of first pixel circuit columns Z1, the first pixel circuit columns Z1 comprising the first pixel circuits 101 and the second pixel circuits 102 arranged alternately along the column direction. The plurality of pixel circuits 10 form a plurality of second pixel circuit columns Z2, the second pixel circuit columns Z2 comprising the third pixel circuits 103 arranged along the column direction, the first pixel circuit columns Z1 and the second pixel circuit columns Z2 arranged alternately along the row direction. The plurality of data signal lines 30 extend along the column direction and are arranged along the row direction. The first data signal line 301 is electrically connected to the first pixel circuits 101 in the same first pixel circuit column Z1, the second data signal line 302 is electrically connected to the second pixel circuits 102 in the same first pixel circuit column Z1, and the third data signal line 303 is electrically connected to the third pixel circuits 103 in the same second pixel circuit column Z2.

[0130] Specifically, as shown in FIG. 3, the display area AA is provided with the first pixel circuit columns Z1 and the second pixel circuit columns Z2 arranged alternately along the row direction. In the first pixel circuit columns Z1, the first pixel circuits 101 and the second pixel circuits 102 are arranged alternately along the column direction; in the second pixel circuit columns Z2, the plurality of third pixel circuits 103 are arranged along the column direction in sequence.

[0131] With the above arrangement, each pixel unit can not be composed of a complete red sub-pixel, a green sub-pixel and a blue sub-pixel, but composed of two sub-pixels of different colors, for example, a red sub-pixel and a green sub-pixel adjacent to each other combine to form a pixel unit, or a blue sub-pixel and a green sub-pixel adjacent to each other combine to form a pixel unit. In this way, each pixel unit contains only two sub-pixels instead of three sub-pixels, so that more pixel units can be placed in the same area, achieving higher pixel density, which is conducive to improving the resolution and making the picture display more delicate.

[0132] Further, as shown in FIG. 3, the data signal lines 30 extend along the column direction and are arranged along the row direction, and the data signal lines 30 and the pixel circuit columns are correspondingly arranged, wherein each data signal line 30 can be connected to at least part of the pixel circuits in one column of pixel circuit columns.

[0133] Specifically, as shown in FIG. 3, the first data signal line 301 is electrically connected with the first pixel circuit 101 in the same first pixel circuit column Z1, and thus the first data signal line 301 only needs to provide data signals to the first pixel circuit 101 in the same first pixel circuit column Z1; the second data signal line 302 is electrically connected with the second pixel circuit 102 in the same first pixel circuit column Z1, and thus the second data signal line 302 only needs to provide data signals to the second pixel circuit 102 in the same first pixel circuit column Z1; the third data signal line 303 is electrically connected with the third pixel circuit 103 in the same second pixel circuit column Z2, and thus the third data signal line 303 only needs to provide data signals to the third pixel circuit 103 in the same second pixel circuit column Z2. In this way, one data signal line only transmits data signals corresponding to one color sub-pixel, thereby reducing the frequency and amplitude of data signal transitions on a single data signal line and reducing the power consumption of the integrated circuit (IC) providing the data signals.

[0134] FIG. 7 is a structural schematic diagram of another display panel according to an embodiment of the present application. As shown in FIG. 7, optionally, the plurality of first pixel circuit columns Z1 are divided into a plurality of first pixel circuit column groups G1, and each first pixel circuit column group G1 includes two first pixel circuit columns Z1, which are a first group inner pixel circuit column Z11 and a second group inner pixel circuit column Z12. The first data signal line 301 connected with the first pixel circuit 101 in the first group inner pixel circuit column Z11 is a first group inner data signal line L1, the second data signal line 302 connected with the second pixel circuit 102 in the first group inner pixel circuit column Z11 is a second group inner data signal line L2, the first data signal line 301 connected with the first pixel circuit 101 in the second group inner pixel circuit column Z12 is a third group inner data signal line L3, and the second data signal line 302 connected with the second pixel circuit 102 in the second group inner pixel circuit column Z12 is a fourth group inner data signal line L4. In the first pixel circuit column group G1, the first group inner data signal line L1 and the third group inner data signal line L3 are electrically connected, and the second group inner data signal line L2 and the fourth group inner data signal line L4 are electrically connected. The first pixel circuit 101 connected with the first group inner data signal line L1 and the first pixel circuit 101 connected with the third group inner data signal line L3 are located in different pixel circuit rows, and the second pixel circuit 102 connected with the second group inner data signal line L2 and the second pixel circuit 102 connected with the fourth group inner data signal line L4 are located in different pixel circuit rows.

[0135] Specifically, as shown in FIG. 7, in the display area AA, a plurality of first pixel circuit column groups G1 are arranged along the row direction, wherein the first pixel circuit column group G1 includes a first intra-group pixel circuit column Z11 and a second intra-group pixel circuit column Z12, the first intra-group pixel circuit column Z11 includes first pixel circuits 101 and second pixel circuits 102 arranged alternately along the column direction, and the second intra-group pixel circuit column Z12 includes first pixel circuits 101 and second pixel circuits 102 arranged alternately along the column direction.

[0136] In this embodiment, the first pixel circuits 101 in the first intra-group pixel circuit column Z11 are connected to the first intra-group data signal line L1, and the first pixel circuits 101 in the second intra-group pixel circuit column Z12 are connected to the third intra-group data signal line L3, wherein the first intra-group data signal line L1 and the third intra-group data signal line L3 in the first pixel circuit column group G1 are electrically connected. In this way, the data signals on the first intra-group data signal line L1 and the third intra-group data signal line L3 can be provided by the same pin of the IC, so that the number of pins for providing data signals in the IC can be reduced while ensuring that one data signal line only transmits data signals corresponding to one color sub-pixel, which is conducive to reducing the size and cost of the IC.

[0137] Further, the first pixel circuits 101 connected to the first intra-group data signal line L1 and the first pixel circuits 101 connected to the third intra-group data signal line L3 are located in different pixel circuit rows, so as to avoid the same pin of the IC providing data signals for two first pixel circuits 101 located in different pixel circuit columns at the same time when scanning a certain row of pixel circuits, so that each IC pin only provides data signals for one first pixel circuit 101 when scanning any row of pixel circuits, thereby ensuring that the brightness of the sub-pixel corresponding to each first pixel circuit 101 can be independently controlled in one frame of display image, and further ensuring the display quality of the display panel.

[0138] Continuing to refer to FIG. 7, the second pixel circuits 102 in the first intra-group pixel circuit column Z11 are connected to the second intra-group data signal line L2, and the second pixel circuits 102 in the second intra-group pixel circuit column Z12 are connected to the fourth intra-group data signal line L4, wherein the second intra-group data signal line L2 and the fourth intra-group data signal line L4 in the first pixel circuit column group G1 are electrically connected. In this way, the data signals on the second intra-group data signal line L2 and the fourth intra-group data signal line L4 can be provided by the same pin of the IC, so that the number of pins for providing data signals in the IC can be reduced while ensuring that one data signal line only transmits data signals corresponding to one color sub-pixel, which is conducive to reducing the size and cost of the IC.

[0139] Further, the second pixel circuit 102 connected with the second intra-group data signal line L2 and the second pixel circuit 102 connected with the fourth intra-group data signal line L4 are located in different pixel circuit rows, so as to avoid that the same pin of the IC provides data signals for two second pixel circuits 102 located in different pixel circuit columns when scanning a certain row of pixel circuits, thereby ensuring that each pin of the IC provides data signals for only one second pixel circuit 102 when scanning any row of pixel circuits, and ensuring that the brightness of the sub-pixel corresponding to each second pixel circuit 102 can be independently controlled in a frame of display picture, thereby ensuring the display quality of the display panel.

[0140] With reference back to FIG. 7, alternatively, the first pixel circuits 101 and the second pixel circuits 102 are alternately and spacedly arranged along the row direction, and the first pixel circuit column group G1 includes two adjacent first pixel circuit columns Z1.

[0141] Specifically, as shown in FIG. 7, the first pixel circuits 101 and the second pixel circuits 102 are alternately arranged along the row direction, and the third pixel circuits 103 are arranged between the first pixel circuits 101 and the second pixel circuits 102, so that the arrangement of the first pixel circuits 101 and the second pixel circuits 102 is more dispersed, thereby preventing the display panel from easily generating local bright lines, and being beneficial to improving the display uniformity of the display panel.

[0142] With reference back to FIG. 7, alternatively, the display panel provided by the embodiment of the present application further includes a non-display area NAA located at least one side of the display area AA, in the first pixel circuit column group G1, the first intra-group data signal line L1 and the third intra-group data signal line L3 are electrically connected through a first data connection line L13, and the second intra-group data signal line L2 and the fourth intra-group data signal line L4 are electrically connected through a second data connection line L24, and the first data connection line L13 and the second data connection line L24 are both located in the non-display area NAA.

[0143] Specifically, as shown in FIG. 7, the non-display area NAA can be a lower frame area located at one side of the display area AA along the column direction, but is not limited thereto, and the positional relationship between the display area AA and the non-display area NAA is not specifically limited in the embodiment of the present application.

[0144] In the embodiment, as shown in FIG. 7, the first data connection line L13 extending along the row direction is arranged to electrically connect the first intra-group data signal line L1 and the third intra-group data signal line L3 in the first pixel circuit column group G1 through the first data connection line L13. Further, the second data connection line L24 extending along the row direction is arranged to electrically connect the second intra-group data signal line L2 and the fourth intra-group data signal line L4 in the first pixel circuit column group G1 through the second data connection line L24.

[0145] The first data connection line L13 and the second data connection line L24 are located in the non-display area NAA, so that the first data connection line L13 and the second data connection line L24 can avoid shielding the display area AA, thereby reducing the influence of the first data connection line L13 and the second data connection line L24 on the display effect.

[0146] FIG. 8 is a structural schematic diagram of another display panel provided by the embodiment of the present application. As shown in FIG. 8, in the first pixel circuit column group G1, the first intra-group data signal line L1 and the third intra-group data signal line L3 are electrically connected through the first data connection line L13, and the second intra-group data signal line L2 and the fourth intra-group data signal line L4 are electrically connected through the second data connection line L24. The first data connection line L13 and the second data connection line L24 are located in the display area AA.

[0147] Specifically, as shown in FIG. 8, the first data connection line L13 extending along the row direction is arranged to electrically connect the first intra-group data signal line L1 and the third intra-group data signal line L3 in the first pixel circuit column group G1. In addition, the second data connection line L24 extending along the row direction is arranged to electrically connect the second intra-group data signal line L2 and the fourth intra-group data signal line L4 in the first pixel circuit column group G1.

[0148] The first data connection line L13 and the second data connection line L24 are located in the display area AA, which is different from the scheme of arranging the first data connection line L13 and the second data connection line L24 in the non-display area NAA. The scheme can reduce the number of wirings in the non-display area NAA, thereby facilitating the reduction of the area of the non-display area NAA for wiring, and realizing a narrow frame design.

[0149] Continuing to refer to FIG. 8, the first data connection line L13 and the second data connection line L24 are located between adjacent row pixel circuits 10 in the display area AA, which can avoid the formation of parasitic capacitance between the first data connection line L13 and the second data connection line L24 and each metal film layer in the pixel circuit 10, thereby reducing the influence of the first data connection line L13 and the second data connection line L24 on the performance of the pixel circuit 10, but the present application is not limited thereto.

[0150] In other embodiments, the first data connection line L13 and the second data connection line L24 can also at least partially overlap the pixel circuit 10 in a direction perpendicular to the plane where the display panel is located, so that the first data connection line L13 and the second data connection line L24 do not need to occupy additional space, thereby facilitating the improvement of the pixel density of the display panel. The embodiment of the present application does not make a specific limitation in this regard.

[0151] Fig. 9 is a structural schematic view of another display panel provided by the embodiment of the present application. As shown in Fig. 9, the display panel provided by the embodiment of the present application can further include a plurality of data signal output lines 40 and a plurality of gate-on circuits 50. The data signal output lines 40 include a first data signal output line 401 and a second data signal output line 402. The gate-on circuits 50 include a first gate-on circuit 501 and a second gate-on circuit 502. In the first pixel circuit column group G1, the first intra-group data signal line L1 and the third intra-group data signal line L3 are electrically connected to the same first data signal output line 401 through the first gate-on circuit 501. The first gate-on circuit 501 is configured to transmit the data signal output by the first data signal output line 401 to the first intra-group data signal line L1 and the third intra-group data signal line L3 in time division. In the first pixel circuit column group G1, the second intra-group data signal line L2 and the fourth intra-group data signal line L4 are electrically connected to the same second data signal output line 402 through the second gate-on circuit 502. The second gate-on circuit 502 is configured to transmit the data signal output by the second data signal output line 402 to the second intra-group data signal line L2 and the fourth intra-group data signal line L4 in time division.

[0152] As shown in Figs. 7 and 9, the display panel is provided with a plurality of data signal output lines 40. The data signal output lines 40 are electrically connected to the pins of the integrated circuit IC and the data signal lines 30, respectively. The integrated circuit IC provides the data signal to the data signal lines 30 through the data signal output lines 40.

[0153] Specifically, as shown in Figs. 7 and 9, the data signal output lines 40 include a first data signal output line 401 and a second data signal output line 402. In the first pixel circuit column group G1, the first intra-group data signal line L1 and the third intra-group data signal line L3 are electrically connected to the same first data signal output line 401. At this time, the first data signal output line 401 provides the data signal to the first intra-group data signal line L1 and the third intra-group data signal line L3 simultaneously. Similarly, in the first pixel circuit column group G1, the second intra-group data signal line L2 and the fourth intra-group data signal line L4 are electrically connected to the same second data signal output line 402. At this time, the second data signal output line 402 provides the data signal to the second intra-group data signal line L2 and the fourth intra-group data signal line L4 simultaneously.

[0154] Continuing to refer to FIG. 7, one data signal output line 40 needs to provide data signals to two data signal lines 30 at the same time, wherein each data signal line 30 is connected to a certain number of pixel circuits 10, each of which has its own parasitic capacitance, thus, when one data signal output line 40 provides data signals to two data signal lines 30 at the same time, the capacitive load on the pin of the integrated circuit IC includes the parasitic capacitance of the pixel circuits 10 connected to the two data signal lines 30, which causes a problem of large capacitive load, and the larger the capacitive load is, the more energy is required for charging and discharging, and the power consumption increases.

[0155] Based on the above technical problem, in the present embodiment, as shown in FIG. 9, a plurality of gating circuits 50 are further arranged on the display panel, and the gating circuits 50 are used to transmit data signals from the data signal output line 40 to different data signal lines 30 in time division, so that at the same time point, the gating circuit 50 selectively transmits data signals to one data signal line 30, ensuring that the pin of each integrated circuit IC only provides data signals to one data signal line 30 at any time, so that the capacitive load on the pin of the integrated circuit IC can be effectively reduced, and the power consumption is further reduced.

[0156] Specifically, as shown in FIG. 9, the gating circuit 50 includes a first gating circuit 501 and a second gating circuit 502, in the first pixel circuit column group G1, the first group data signal line L1 and the third group data signal line L3 are electrically connected to the same first data signal output line 401 through the first gating circuit 501, so as to transmit the data signals output by the first data signal output line 401 to the first group data signal line L1 and the third group data signal line L3 in time division through the first gating circuit 501, ensuring that the pin of the integrated circuit IC connected to the first data signal output line 401 only provides data signals to the first group data signal line L1 or the third group data signal line L3 at any time, so as to reduce the capacitive load on the pin of the integrated circuit IC, and further reduce the power consumption.

[0157] Similarly, in the first pixel circuit column group G1, the second group data signal line L2 and the fourth group data signal line L4 are electrically connected to the same second data signal output line 402 through the second gating circuit 502, so as to transmit the data signals output by the second data signal output line 402 to the second group data signal line L2 and the fourth group data signal line L4 in time division through the second gating circuit 502, ensuring that the pin of the integrated circuit IC connected to the second data signal output line 402 only provides data signals to the second group data signal line L2 or the fourth group data signal line L4 at any time, so as to reduce the capacitive load on the pin of the integrated circuit IC, and further reduce the power consumption.

[0158] According to the test result, the power consumption of the integrated circuit IC can be reduced by 10% when the display panel displays a white picture, and the power consumption of the integrated circuit IC can be reduced by about 40% when the display panel displays a red or blue picture.

[0159] Continuing to refer to FIG. 9, optionally, the data signal output line 40, the gate circuit 50 and the integrated circuit IC are all located in the non-display area NAA, so that the data signal output line 40, the gate circuit 50 and the integrated circuit IC can avoid forming an obstruction to the display area AA, thereby reducing the influence of the data signal output line 40, the gate circuit 50 and the integrated circuit IC on the display effect.

[0160] In other embodiments, the integrated circuit IC can also be arranged on a flexible circuit board which is connected to the display panel in a binding manner, so as to facilitate reducing the area of the non-display area NAA and realizing a narrow frame design, and the embodiments of the present application do not make a specific limitation in this regard.

[0161] Continuing to refer to FIG. 9, optionally, the data signal output line 40 extends along the column direction and is arranged along the row direction, so as to facilitate realizing the electrical connection between the data signal output line 40 and the pin of the integrated circuit IC and the data signal line 30, but the present application is not limited thereto, and the embodiments of the present application do not make a specific limitation in this regard.

[0162] Continuing to refer to FIG. 9, optionally, the first gate circuit 501 includes a first switch transistor M1 and a second switch transistor M2, the first switch transistor M1 is connected between the first group of data signal lines L1 and the first data signal output line 401, and the second switch transistor M2 is connected between the third group of data signal lines L3 and the first data signal output line 401. The second gate circuit 502 includes a third switch transistor M3 and a fourth switch transistor M4, the third switch transistor M3 is connected between the second group of data signal lines L2 and the second data signal output line 402, and the fourth switch transistor M4 is connected between the fourth group of data signal lines L4 and the second data signal output line 402. The gate of the first switch transistor M1 and the gate of the fourth switch transistor M4 receive a first switch signal SW1, and the gate of the second switch transistor and the gate of the third switch transistor M3 receive a second switch signal SW2.

[0163] Specifically, as shown in FIG. 9, the first gate circuit 501 is composed of the first switch transistor M1 and the second switch transistor M2, wherein one end of the first switch transistor M1 is connected to the first group of data signal lines L1, and the other end is connected to the first data signal output line 401; one end of the second switch transistor M2 is connected to the third group of data signal lines L3, and the other end is connected to the first data signal output line 401.

[0164] Further, the gate of the first switch transistor M1 receives a first switch signal SW1, which is used to control the first switch transistor M1 to be turned on or turned off. When the first switch transistor M1 is turned on, the first group data signal line L1 and the first data signal output line 401 are connected, and at this time, the first data signal output line 401 provides the data signal to the first group data signal line L1. When the first switch transistor M1 is turned off, the first group data signal line L1 and the first data signal output line 401 are insulated.

[0165] The gate of the second switch transistor M2 receives a second switch signal SW2, which is used to control the second switch transistor M2 to be turned on or turned off. When the second switch transistor M2 is turned on, the third group data signal line L3 and the first data signal output line 401 are connected, and at this time, the first data signal output line 401 provides the data signal to the third group data signal line L3. When the second switch transistor M2 is turned off, the third group data signal line L3 and the first data signal output line 401 are insulated.

[0166] The gate of the first switch transistor M1 and the gate of the second switch transistor M2 receive different first switch signal SW1 and second switch signal SW2, so that the first switch transistor M1 and the second switch transistor M2 are turned on at different times, thereby realizing the time-sharing transmission of the data signal output by the first data signal output line 401 to the first group data signal line L1 and the third group data signal line L3, ensuring that the integrated circuit IC pin connected with the first data signal output line 401 only provides the data signal to the first group data signal line L1 or the third group data signal line L3 at any time, thereby reducing the capacitive load on the integrated circuit IC pin and reducing power consumption.

[0167] Similarly, continuing to refer to FIG. 9, the second gating circuit 502 is composed of a third switch transistor M3 and a fourth switch transistor M4. One end of the third switch transistor M3 is connected to the second group data signal line L2, and the other end is connected to the second data signal output line 402. One end of the fourth switch transistor M4 is connected to the fourth group data signal line L4, and the other end is connected to the second data signal output line 402.

[0168] The gate of the third switch transistor M3 receives the second switch signal SW2, which is used to control the third switch transistor M3 to be turned on or turned off. When the third switch transistor M3 is turned on, the second group data signal line L2 and the second data signal output line 402 are connected, and at this time, the second data signal output line 402 provides the data signal to the second group data signal line L2. When the third switch transistor M3 is turned off, the second group data signal line L2 and the second data signal output line 402 are insulated.

[0169] The gate of the fourth switch transistor M4 receives a first switch signal SW1, which is used to control the fourth switch transistor M4 to be turned on or turned off. When the fourth switch transistor M4 is turned on, the fourth group data signal line L4 and the second data signal output line 402 are connected, and at this time, the second data signal output line 402 provides the data signal to the fourth group data signal line L4. When the fourth switch transistor M4 is turned off, the fourth group data signal line L4 and the second data signal output line 402 are insulated.

[0170] The gate of the third switch transistor M3 and the gate of the fourth switch transistor M4 receive different second switch signals SW2 and first switch signals SW1, so that the third switch transistor M3 and the fourth switch transistor M4 are turned on at different times, thereby realizing the time-sharing transmission of the data signal output by the second data signal output line 402 to the second group data signal line L2 and the fourth group data signal line L4, ensuring that the integrated circuit IC pin connected to the second data signal output line 402 only provides the data signal to the second group data signal line L2 or the fourth group data signal line L4 at any time, thereby reducing the capacitive load on the integrated circuit IC pin and reducing power consumption.

[0171] Further, as shown in FIG. 9, the first pixel circuit 101 connected to the first group data signal line L1 and the second pixel circuit 102 connected to the fourth group data signal line L4 are located in the same pixel circuit row, and therefore, the gate of the first switch transistor M1 and the gate of the fourth switch transistor M4 can be arranged to receive the first switch signal SW1, so that the first switch transistor M1 and the fourth switch transistor M4 are turned on at the same time, ensuring that the first pixel circuit 101 and the second pixel circuit 102 located in the same row receive the data signal at the same time. In this way, the number of switch signals can be reduced, the control logic can be simplified, the number of switch signal lines for transmitting switch signals can be reduced, and the cost can be reduced.

[0172] Similarly, the second pixel circuit 102 connected to the second group data signal line L2 and the first pixel circuit 101 connected to the third group data signal line L3 are located in the same pixel circuit row, and therefore, the gate of the second switch transistor M2 and the gate of the third switch transistor M3 can be arranged to receive the second switch signal SW2, so that the second switch transistor M2 and the third switch transistor M3 are turned on at the same time, ensuring that the first pixel circuit 101 and the second pixel circuit 102 located in the same row receive the data signal at the same time. In this way, the number of switch signals can be reduced, the control logic can be simplified, the number of switch signal lines for transmitting switch signals can be reduced, and the cost can be reduced.

[0173] With reference to FIGS. 7-9, alternatively, the plurality of first pixel circuit columns Z1 is divided into a plurality of first pixel circuit column groups G1, each of which includes two adjacent first pixel circuit columns Z1, i.e., a first group inner pixel circuit column Z11 and a second group inner pixel circuit column Z12. The first data signal line 301 connected to the first pixel circuit 101 in the first group inner pixel circuit column Z11 is a first group inner data signal line L1, the second data signal line 302 connected to the second pixel circuit 102 in the first group inner pixel circuit column Z11 is a second group inner data signal line L2, the first data signal line 301 connected to the first pixel circuit 101 in the second group inner pixel circuit column Z12 is a third group inner data signal line L3, and the second data signal line 302 connected to the second pixel circuit 102 in the second group inner pixel circuit column Z12 is a fourth group inner data signal line L4. In the row direction, the first group inner data signal line L1 and the second group inner data signal line L2 are located on different sides of the first group inner pixel circuit column Z11, and the third group inner data signal line L3 and the fourth group inner data signal line L4 are located on different sides of the second group inner pixel circuit column Z12.

[0174] The structure of the first group inner pixel circuit column Z11 and the second group inner pixel circuit column Z12 in the first pixel circuit column group G1 and the connection structure of the first group inner data signal line L1, the second group inner data signal line L2, the third group inner data signal line L3, and the fourth group inner data signal line L4 can refer to the above embodiments, which will not be described here.

[0175] In this embodiment, as shown in FIGS. 7-9, in the row direction, the first group inner data signal line L1 and the second group inner data signal line L2 are located on different sides of the first group inner pixel circuit column Z11. On the one hand, in the row direction, the first group inner data signal line L1 and the second group inner data signal line L2 are both spaced apart from the first group inner pixel circuit column Z11, which can avoid the formation of parasitic capacitance between the first group inner data signal line L1, the second group inner data signal line L2, and each metal film layer of the pixel circuit 10 in the first group inner pixel circuit column Z11, thereby reducing the influence of the first group inner data signal line L1 and the second group inner data signal line L2 on the performance of the pixel circuit 10. On the other hand, in the row direction, the first group inner data signal line L1 and the second group inner data signal line L2 can have a large spacing therebetween, thereby reducing the mutual interference of data signals between the first group inner data signal line L1 and the second group inner data signal line L2.

[0176] Similarly, in the row direction, the third intra-group data signal line L3 and the fourth intra-group data signal line L4 are located on different sides of the second intra-group pixel circuit column Z12. On the one hand, in the row direction, the third intra-group data signal line L3 and the fourth intra-group data signal line L4 are both spaced apart from the second intra-group pixel circuit column Z12, which can avoid the formation of parasitic capacitance between the third intra-group data signal line L3 and the fourth intra-group data signal line L4 and each metal film layer of the pixel circuit 10 in the second intra-group pixel circuit column Z12, thereby reducing the influence of the third intra-group data signal line L3 and the fourth intra-group data signal line L4 on the performance of the pixel circuit 10. On the other hand, in the row direction, the third intra-group data signal line L3 and the fourth intra-group data signal line L4 can have a large spacing therebetween, thereby reducing the mutual interference of data signals between the third intra-group data signal line L3 and the fourth intra-group data signal line L4.

[0177] With continued reference to FIGS. 7-9, optionally, the plurality of first pixel circuit columns Z1 is divided into a plurality of first pixel circuit column groups G1, each first pixel circuit column group G1 including two adjacent first pixel circuit columns Z1, which are the first intra-group pixel circuit column Z11 and the second intra-group pixel circuit column Z12, respectively. The first data signal line 301 connected to the first pixel circuit 101 in the first intra-group pixel circuit column Z11 is the first intra-group data signal line L1, the second data signal line 302 connected to the second pixel circuit 102 in the first intra-group pixel circuit column Z11 is the second intra-group data signal line L2, the first data signal line 301 connected to the first pixel circuit 101 in the second intra-group pixel circuit column Z12 is the third intra-group data signal line L3, and the second data signal line 302 connected to the second pixel circuit 102 in the second intra-group pixel circuit column Z12 is the fourth intra-group data signal line L4. In the first pixel circuit column group G1, the second intra-group data signal line L2 and the fourth intra-group data signal line L4 are located between the first intra-group data signal line L1 and the third intra-group data signal line L3.

[0178] The structures of the first intra-group pixel circuit column Z11 and the second intra-group pixel circuit column Z12 in the first pixel circuit column group G1, and the connection structures of the first intra-group data signal line L1, the second intra-group data signal line L2, the third intra-group data signal line L3, and the fourth intra-group data signal line L4 can refer to the above embodiments, which will not be described here again.

[0179] In the embodiment, as shown in FIGS. 7-9, the first intra-group data signal lines L1 and the third intra-group data signal lines L3 are connected to the first pixel circuits 101, and the first pixel circuits 101 are located in the same color sub-pixels; the second intra-group data signal lines L2 and the fourth intra-group data signal lines L4 are connected to the second pixel circuits 102, and the second pixel circuits 102 are located in the same color sub-pixels.

[0180] In the first pixel circuit column group G1, the second intra-group data signal lines L2 and the fourth intra-group data signal lines L4 are arranged between the first intra-group data signal lines L1 and the third intra-group data signal lines L3, and in the row direction, the first intra-group data signal lines L1, the second intra-group data signal lines L2, the fourth intra-group data signal lines L4 and the third intra-group data signal lines L3 can be arranged in sequence. In this way, the second intra-group data signal lines L2 and the fourth intra-group data signal lines L4 can be symmetrically distributed relative to the central axis of the first pixel circuit column group G1, and the first intra-group data signal lines L1 and the third intra-group data signal lines L3 can also be symmetrically distributed relative to the central axis of the first pixel circuit column group G1, that is, the data signal lines 30 connected to the same color sub-pixels can be symmetrically distributed relative to the central axis of the first pixel circuit column group G1, which is beneficial to making the color deviation of the display picture have better symmetry, thereby improving the four-orientation color deviation, that is, the consistency and accuracy of the color are improved when the display picture is viewed from any direction, and the display picture can be viewed from a wider angle range without feeling obvious color change, thereby enhancing the user experience.

[0181] It should be noted that the central axis of the first pixel circuit column group G1 is the central axis extending in the column direction.

[0182] Continuing to refer to FIG. 7, optionally, the display panel provided by the embodiment of the present application further includes a non-display area NAA located at least one side of the display area AA. In the first pixel circuit column group G1, the first intra-group data signal lines L1 and the third intra-group data signal lines L3 are electrically connected through the first data connection line L13, and the second intra-group data signal lines L2 and the fourth intra-group data signal lines L4 are electrically connected through the second data connection line L24, the first data connection line L13 and the second data connection line L24 are located in the non-display area NAA, and the second data connection line L24 is located on the side of the first data connection line L13 close to the display area AA.

[0183] The positional relationship between the display area AA and the non-display area NAA, and the connection relationship among the first intra-group data signal lines L1, the second intra-group data signal lines L2, the third intra-group data signal lines L3, the fourth intra-group data signal lines L4, the first data connection line L13 and the second data connection line L24 can be referred to the above-mentioned embodiments, which will not be described here.

[0184] In the embodiment, as shown in FIG. 7, the first data connection line L13 and the second data connection line L24 are both located in the non-display area NAA, which can avoid the first data connection line L13 and the second data connection line L24 from forming an obstruction to the display area AA, thereby reducing the influence of the first data connection line L13 and the second data connection line L24 on the display effect.

[0185] Further, as shown in FIG. 7, the second data connection line L24 is located on the side of the first data connection line L13 close to the display area AA, and thus arranged, in the direction perpendicular to the plane where the display panel is located, the first data connection line L13 and the second group of data signal lines L2 and the fourth group of data signal lines L4 can be avoided from overlapping, thereby reducing the coupling capacitance between the first data connection line L13 and the second group of data signal lines L2 and the fourth group of data signal lines L4, and reducing the mutual interference between the data signal on the first data connection line L13 and the data signal on the second group of data signal lines L2 and the fourth group of data signal lines L4.

[0186] FIG. 10 is a schematic diagram of a partial cross-sectional structure of a display panel provided in an embodiment of the present application. As shown in FIG. 7 and FIG. 10, optionally, the display panel provided in the embodiment of the present application further includes a plurality of data signal output lines 40. The data signal output lines 40 include a first data signal output line 401 and a second data signal output line 402. In the first pixel circuit column group G1, the first data connection line L13 is electrically connected with the first data signal output line 401, and the second data connection line L24 is electrically connected with the second data signal output line 402. The first data connection line L13 and the second data signal output line 402 are located in different film layers.

[0187] The structure of the data signal output lines 40, and the connection relationship between the first data signal output line 401 and the second data signal output line 402 can refer to the above embodiments, which will not be described herein again.

[0188] In the embodiment, as shown in FIG. 7 and FIG. 10, in the direction perpendicular to the plane where the display panel is located, the first data connection line L13 and the second data signal output line 402 overlap, and thus, by arranging the first data connection line L13 and the second data signal output line 402 in different film layers, short circuit between the first data connection line L13 and the second data signal output line 402 can be avoided.

[0189] For example, as shown in FIG. 5 and FIG. 10, the pixel circuit 10 and the light emitting element 20 can be arranged on one side of the substrate 60, wherein the pixel circuit 10 further includes a storage capacitor Cst, and the storage capacitor Cst includes a first plate C1 and a second plate C2 arranged in a stack, and the first plate C1 is located on the side of the second plate C2 close to the substrate 60.

[0190] As shown in FIG. 10, the second data signal output line 402 can be located in the same film layer as the first plate C1 and / or the second plate C2, the data signal line 30 can be located in the same film layer as the source-drain electrode 3, and the first data connection line L13 can be located in the same film layer as the data signal line 30, but the application is not limited thereto.

[0191] It can be understood that, under the condition that the first data connection line L13 and the second data signal output line 402 are located in different film layers, the first data connection line L13 can be arranged in the same layer as the existing metal film layer structure in the pixel circuit 10, so as to reduce the number of metal layers and facilitate the reduction of the thickness of the display panel; meanwhile, the first data connection line L13 can be prepared in the same process as the existing metal film layer structure in the pixel circuit 10, so as to shorten the process time and reduce the manufacturing cost.

[0192] FIG. 11 is a structural schematic diagram of another display panel provided by an embodiment of the application. As shown in FIG. 11, alternatively, the plurality of first pixel circuit columns Z1 are divided into a plurality of first pixel circuit column groups G1, the first pixel circuit column group G1 includes two first pixel circuit columns Z1, which are a first group inner pixel circuit column Z11 and a second group inner pixel circuit column Z12. The first data signal line 301 connected to the first pixel circuit 101 in the first group inner pixel circuit column Z11 is a first group inner data signal line L1, the second data signal line 302 connected to the second pixel circuit 102 in the first group inner pixel circuit column Z11 is a second group inner data signal line L2, the first data signal line 301 connected to the first pixel circuit 101 in the second group inner pixel circuit column Z12 is a third group inner data signal line L3, and the second data signal line 302 connected to the second pixel circuit 102 in the second group inner pixel circuit column Z12 is a fourth group inner data signal line L4. In the first pixel circuit column group G1, the first group inner data signal line L1, the second group inner data signal line L2, the third group inner data signal line L3, and the fourth group inner data signal line L4 are arranged in sequence along the row direction.

[0193] The structure of the first group inner pixel circuit column Z11 and the second group inner pixel circuit column Z12 and the connection structure of the first group inner data signal line L1, the second group inner data signal line L2, the third group inner data signal line L3, and the fourth group inner data signal line L4 in the first pixel circuit column group G1 can refer to the above embodiments, which will not be described herein again.

[0194] In the embodiment, as shown in FIG. 11, the first intra-group data signal lines L1 and the third intra-group data signal lines L3 are connected to the first pixel circuit 101, and the first pixel circuit 101 is located in the same color sub-pixel; the second intra-group data signal lines L2 and the fourth intra-group data signal lines L4 are connected to the second pixel circuit 102, and the second pixel circuit 102 is located in the same color sub-pixel.

[0195] In the embodiment, as shown in FIG. 11, in the first pixel circuit column group G1, the first intra-group data signal lines L1, the second intra-group data signal lines L2, the third intra-group data signal lines L3 and the fourth intra-group data signal lines L4 are arranged in the row direction in sequence, then in the row direction, the first intra-group data signal lines L1 are located on the left side of the first intra-group pixel circuit column Z11, and the third intra-group data signal lines L3 are located on the left side of the second intra-group pixel circuit column Z12; the second intra-group data signal lines L2 are located on the right side of the first intra-group pixel circuit column Z11, and the fourth intra-group data signal lines L4 are located on the right side of the second intra-group pixel circuit column Z12, that is, the data signal lines 30 connected to the same color sub-pixel are located on the same side of the first pixel circuit column Z1 connected thereto, so that the position relationship between the data signal lines 30 connected to the same color sub-pixel and the first pixel circuit column Z1 connected thereto is more consistent, at this time, the parasitic capacitances between the data signal lines 30 connected to the same color sub-pixel and the first pixel circuit column Z1 connected thereto and each metal film layer or signal node are at a similar level, so that even if there is process fluctuation in the process of manufacturing the display panel, the overlapping deviation between the data signal lines 30 connected to the same color sub-pixel and the first pixel circuit column Z1 connected thereto and each metal film layer or signal node has the same trend change, thereby improving the display uniformity of the display panel and avoiding the vertical stripe phenomenon caused by the brightness difference.

[0196] Continuing to refer to FIG. 11, optionally, the display panel provided by the embodiment of the present application further includes a non-display area NAA located on at least one side of the display area AA. In the first pixel circuit column group G1, the first intra-group data signal lines L1 and the third intra-group data signal lines L3 are electrically connected through the first data connection line L13, and the second intra-group data signal lines L2 and the fourth intra-group data signal lines L4 are electrically connected through the second data connection line L24, and the first data connection line L13 and the second data connection line L24 are located in the non-display area NAA.

[0197] The second data connection line L24 is located on the side of the first data connection line L13 close to the display area AA, and the second data connection line L24 and the third intra-group data signal line L3 are located on different film layers.

[0198] Alternatively,

[0199] The first data connection line L13 is located on the side of the second data connection line L24 close to the display area AA, and the first data connection line L13 and the second group data signal line L2 are located in different film layers.

[0200] The positional relationship between the display area AA and the non-display area NAA, the connection relationship among the first group data signal line L1, the second group data signal line L2, the third group data signal line L3, the fourth group data signal line L4, the first data connection line L13 and the second data connection line L24 can refer to the above embodiments, which will not be described here.

[0201] In this embodiment, as shown in FIG. 11, the first data connection line L13 and the second data connection line L24 are both located in the non-display area NAA, which can avoid the first data connection line L13 and the second data connection line L24 from forming an obstruction to the display area AA, thereby reducing the influence of the first data connection line L13 and the second data connection line L24 on the display effect.

[0202] Further, as shown in FIG. 11, the second data connection line L24 can be located on the side of the first data connection line L13 close to the display area AA, at this time, in the direction perpendicular to the plane where the display panel is located, there is an overlap between the second data connection line L24 and the third group data signal line L3. Therefore, in this embodiment, by setting the second data connection line L24 and the third group data signal line L3 to be located in different film layers, short circuit between the first data connection line L13 and the second data signal output line 402 is avoided.

[0203] FIG. 12 is a structural schematic diagram of another display panel provided by an embodiment of the present application, as shown in FIG. 12, optionally, the first data connection line L13 is located on the side of the second data connection line L24 close to the display area AA, at this time, in the direction perpendicular to the plane where the display panel is located, there is an overlap between the first data connection line L13 and the second group data signal line L2. Therefore, in this embodiment, by setting the first data connection line L13 and the second group data signal line L2 to be located in different film layers, short circuit between the first data connection line L13 and the second group data signal line L2 is avoided.

[0204] FIG. 13 is a partial cross-sectional structural schematic diagram of another display panel provided by an embodiment of the present application, as shown in FIG. 12 and FIG. 13, optionally, in the first pixel circuit column group G1, the first group data signal line L1 and the third group data signal line L3 are electrically connected through the first data connection line L13, and the second group data signal line L2 and the fourth group data signal line L4 are electrically connected through the second data connection line L24. The first data connection line L13 and the second data connection line L24 are located in the same film layer, or the first data connection line L13 and the second data connection line L24 are located in different film layers.

[0205] The connection relationship of the first intra-group data signal line L1, the second intra-group data signal line L2, the third intra-group data signal line L3, the fourth intra-group data signal line L4, the first data connection line L13 and the second data connection line L24 can refer to the above embodiment, which will not be described here.

[0206] In the embodiment, as shown in FIG. 12 and FIG. 13, the first data connection line L13 and the second data connection line L24 can be located in different film layers.

[0207] For example, as shown in FIG. 12 and FIG. 13, the data signal output line 40 can be located in the same film layer as the first plate C1, the data signal line 30 can be located in the same film layer as the source-drain electrode 3, the second data connection line L24 can be located in the same film layer as the data signal line 30, and the first data connection line L13 can be located in the same film layer as the second plate C2, but not limited thereto.

[0208] FIG. 14 is a schematic diagram of a partial cross-sectional structure of another display panel provided by the embodiment of the present application. As shown in FIG. 7 and FIG. 14, alternatively, the first data connection line L13 and the second data connection line L24 can be located in the same film layer.

[0209] For example, as shown in FIG. 7 and FIG. 14, the data signal output line 40 can be located in the same film layer as the first plate C1, the data signal line 30 can be located in the same film layer as the source-drain electrode 3, and the second data connection line L24 and the first data connection line L13 can be located in the same film layer as the second plate C2, but not limited thereto.

[0210] It should be noted that, under the condition of ensuring that the first data connection line L13 and the second data connection line L24 do not cause short circuit problem, the first data connection line L13 and the second data connection line L24 can be selected to be located in the same layer as the existing metal film layer structure in the pixel circuit 10, so as to reduce the number of metal layer settings, which is conducive to reducing the thickness of the display panel; at the same time, the first data connection line L13 and the second data connection line L24 can also be prepared in the same process as the existing metal film layer structure in the pixel circuit 10, so as to shorten the process time and reduce the manufacturing cost.

[0211] For example, the first data connection line L13 can be selected to be located in the same film layer as the data signal output line 40 and / or in the same film layer as the data signal line 30, but not limited thereto.

[0212] Similarly, the second data connection line L24 can be selected to be located in the same film layer as the data signal output line 40 and / or in the same film layer as the data signal line 30, but not limited thereto.

[0213] The data signal output line 40 can be located in the same film layer as the first plate C1 and / or the second plate C2, and the data signal line 30 can be located in the same film layer as the source-drain electrode 3, which is not specifically limited in the embodiments of the present application.

[0214] With reference to FIGS. 7-12, the third data signal line 303 includes a first sub-data signal line L5 and a second sub-data signal line L6.

[0215] Specifically, two third data signal lines 303 are arranged in a column of the second pixel circuit column Z2, and the two third data signal lines 303 are respectively the first sub-data signal line L5 and the second sub-data signal line L6.

[0216] As shown in FIGS. 7-12, the first sub-data signal line L5 and the second sub-data signal line L6 are located on different sides of the second pixel circuit column Z2 in the row direction. On the one hand, the first sub-data signal line L5 and the second sub-data signal line L6 are both spaced apart from the second pixel circuit column Z2 in the row direction, which can avoid the formation of parasitic capacitance between the first sub-data signal line L5 and the second sub-data signal line L6 and each metal film layer of the pixel circuit 10 in the second pixel circuit column Z2, thereby reducing the influence of the first sub-data signal line L5 and the second sub-data signal line L6 on the performance of the pixel circuit 10. On the other hand, the first sub-data signal line L5 and the second sub-data signal line L6 can have a large spacing therebetween in the row direction, thereby reducing the mutual interference of data signals between the first sub-data signal line L5 and the second sub-data signal line L6.

[0217] In addition, as shown in FIGS. 7-12, in the embodiments of the present application, the same number of data signal lines 30 are arranged between adjacent first pixel circuit columns Z1 and second pixel circuit columns Z2, for example, two data signal lines 30 are arranged between adjacent first pixel circuit columns Z1 and second pixel circuit columns Z2, so that the data signal lines 30 are more uniformly distributed in the row direction, thereby reducing visual interference caused by uneven reflection of light by the data signal lines 30 and improving the overall visual effect of the display panel.

[0218] With reference to FIGS. 7-12, the third data signal line 303 includes a first sub-data signal line L5 and a second sub-data signal line L6. The first sub-data signal line L5 is electrically connected to odd-numbered rows of third pixel circuits 103 in the second pixel circuit column Z2, and the second sub-data signal line L6 is electrically connected to even-numbered rows of third pixel circuits 103 in the second pixel circuit column Z2.

[0219] The structures of the first sub-data signal line L5 and the second sub-data signal line L6 can refer to the above embodiments, which will not be described herein again.

[0220] In the embodiment, as shown in FIGS. 7-12, by arranging the first sub-data signal line L5 to be electrically connected with the odd-row third pixel circuits 103 in the second pixel circuit column Z2 and the second sub-data signal line L6 to be electrically connected with the even-row third pixel circuits 103 in the second pixel circuit column Z2, the number of the pixel circuits 10 connected by each data signal line 30 (for example, the first intra-group data signal line L1, the second intra-group data signal line L2, the third intra-group data signal line L3, the fourth intra-group data signal line L4, the first sub-data signal line L5 and the second sub-data signal line L6) can be the same, so that the capacitance load on each data signal line 30 is relatively consistent, which is conducive to ensuring that the time and intensity of the data signal received by all the pixel circuits 10 are consistent, thereby helping to improve the display uniformity of the display panel.

[0221] Meanwhile, the number of nodes of the pixel circuits 10 connected by each data signal line 30 is the same, which can make the pattern distribution of the data signal line 30 more uniform, thereby reducing the visual interference caused by the uneven reflection of light by the data signal line 30 and improving the overall visual effect of the display panel.

[0222] FIG. 15 is a structural schematic diagram of another display panel provided by an embodiment of the present application. As shown in FIG. 15, optionally, the third data signal line 303 includes a first sub-data signal line L5 and a second sub-data signal line L6. The first sub-data signal line L5 is electrically connected with all the third pixel circuits 103 in the second pixel circuit column Z2, and the second sub-data signal line L6 is electrically connected with all the third pixel circuits 103 in the second pixel circuit column Z2.

[0223] The structures of the first sub-data signal line L5 and the second sub-data signal line L6 can refer to the above embodiments, which will not be described herein again.

[0224] In the embodiment, as shown in FIG. 15, the first sub-data signal line L5 is electrically connected with all the third pixel circuits 103 in the second pixel circuit column Z2, and the second sub-data signal line L6 is electrically connected with all the third pixel circuits 103 in the second pixel circuit column Z2, so that the data signal can be written into the third pixel circuit 103 by two data signal lines 30 at the same time, which is conducive to reducing the line resistance, thereby reducing the voltage drop on the data signal line 30 and ensuring that the third pixel circuit 103 can receive more stable data signals. Meanwhile, the writing speed of the data signal can be improved, thereby improving the writing efficiency of the data signal.

[0225] Continuing to refer to FIGS. 7-9, 11, 12 and 15, optionally, the first sub-data signal line L5 and the second sub-data signal line L6 connected with the same second pixel circuit column Z2 are electrically connected.

[0226] The first sub-data signal line L5 and the second sub-data signal line L6 connected with the same second pixel circuit column Z2 are electrically connected, so that the data signals on the first sub-data signal line L5 and the second sub-data signal line L6 can be provided by the same pin of the IC, thereby reducing the number of pins of the IC for providing data signals, and facilitating reduction of the size and cost of the IC.

[0227] Continuing to refer to FIGS. 7, 9, 11, 12 and 15, optionally, the display panel provided by the embodiment of the present application further comprises a non-display area NAA located at least one side of the display area AA. The first sub-data signal line L5 and the second sub-data signal line L6 connected with the same second pixel circuit column Z2 are electrically connected through a third data connection line L56, and the third data connection line L56 is located in the non-display area NAA.

[0228] Specifically, as shown in FIGS. 7, 9, 11, 12 and 15, the non-display area NAA can be a lower frame area located at one side of the display area AA in the column direction, but is not limited thereto, and the embodiment of the present application does not specifically limit the positional relationship between the display area AA and the non-display area NAA.

[0229] In the embodiment, as shown in FIGS. 7, 9, 11, 12 and 15, the third data connection line L56 extending in the row direction is provided, so as to realize the electrical connection between the first sub-data signal line L5 and the second sub-data signal line L6 corresponding to the same second pixel circuit column Z2 through the third data connection line L56.

[0230] The third data connection line L56 is located in the non-display area NAA, which can avoid the third data connection line L56 from forming an obstruction to the display area AA, thereby reducing the influence of the third data connection line L56 on the display effect.

[0231] Continuing to refer to FIG. 8, optionally, the first sub-data signal line L5 and the second sub-data signal line L6 connected with the same second pixel circuit column Z2 are electrically connected through a third data connection line L56, and the third data connection line L56 is located in the display area AA.

[0232] Specifically, as shown in FIG. 8, the third data connection line L56 extending in the row direction is provided, so as to realize the electrical connection between the first sub-data signal line L5 and the second sub-data signal line L6 corresponding to the same second pixel circuit column Z2 through the third data connection line L56.

[0233] The third data connection line L56 is located in the display area AA. Different from the scheme of arranging the third data connection line L56 in the non-display area NAA, the number of wirings in the non-display area NAA can be reduced, thereby reducing the area for wiring in the non-display area NAA and realizing a narrow frame design.

[0234] With continuous reference to FIG. 8, optionally, the third data connection line L56 is located between adjacent row pixel circuits 10 in the display area AA, which can avoid the third data connection line L56 from forming a parasitic capacitor with each metal film layer in the pixel circuit 10, thereby reducing the influence of the third data connection line L56 on the performance of the pixel circuit 10, but is not limited thereto.

[0235] In other embodiments, the third data connection line L56 can also at least partially overlap the pixel circuit 10 in a direction perpendicular to the plane where the display panel is located, so that the third data connection line L56 does not need to occupy extra space, which is conducive to improving the pixel density of the display panel, and the embodiments of the present application are not limited thereto.

[0236] With continuous reference to FIGS. 7 and 9, optionally, the plurality of first pixel circuit columns Z1 are divided into a plurality of first pixel circuit column groups G1, the first pixel circuit column group G1 includes two adjacent first pixel circuit columns Z1, and the two adjacent first pixel circuit columns Z1 are respectively a first group inner pixel circuit column Z11 and a second group inner pixel circuit column Z12. The first data signal line 301 connected to the first pixel circuit 101 in the first group inner pixel circuit column Z11 is a first group inner data signal line L1, the second data signal line 302 connected to the second pixel circuit 102 in the first group inner pixel circuit column Z11 is a second group inner data signal line L2, the first data signal line 301 connected to the first pixel circuit 101 in the second group inner pixel circuit column Z12 is a third group inner data signal line L3, and the second data signal line 302 connected to the second pixel circuit 102 in the second group inner pixel circuit column Z12 is a fourth group inner data signal line L4. In the first pixel circuit column group G1, the first group inner data signal line L1 and the third group inner data signal line L3 are electrically connected, and the second group inner data signal line L2 and the fourth group inner data signal line L4 are electrically connected. The first data connection line L13 and the second data connection line L24 are both located in the non-display area NAA, the third data connection line L56 is located on one side of the first data connection line L13 close to the display area AA, and the second data connection line L24 is located between the third data connection line L56 and the first data connection line L13.

[0237] The structures of the pixel circuit columns Z11 and Z12 in the first group and the second group in the first pixel circuit column group G1 and the connection relationship of the first data signal line L1, the second data signal line L2, the third data signal line L3, the fourth data signal line L4, the first data connection line L13 and the second data connection line L24 can refer to the above-mentioned embodiments, and will not be described here again.

[0238] In the embodiment, as shown in FIGS. 7 and 9, the first data connection line L13, the second data connection line L24 and the third data connection line L56 are all located in the non-display area NAA, so that the first data connection line L13, the second data connection line L24 and the third data connection line L56 can avoid shielding the display area AA, thereby reducing the influence of the first data connection line L13, the second data connection line L24 and the third data connection line L56 on the display effect.

[0239] Further, as shown in FIGS. 7 and 9, in the row direction, the third data connection line L56, the second data connection line L24 and the first data connection line L13 are sequentially arranged on one side of the display area AA, so that in the direction perpendicular to the plane where the display panel is located, the first data connection line L13 and the second data signal line L2 and the fourth data signal line L4 can avoid overlapping, and the second data connection line L24 and the third data signal line 303 can avoid overlapping, thereby reducing the coupling capacitance between different data connection lines and data signal lines and reducing the mutual interference between different data signals.

[0240] Continuing to refer to FIGS. 7, 9, 11, 12 and 15, optionally, the display panel provided by the embodiment of the present application further includes a plurality of data signal output lines 40. The data signal output lines 40 include a first data signal output line 401, a second data signal output line 402 and a third data signal output line 403. In the first pixel circuit column group G1, the first data connection line L13 is electrically connected with the first data signal output line 401, the second data connection line L24 is electrically connected with the second data signal output line 402. The third data connection line L56 is electrically connected with the third data signal output line 403. The third data signal output line 403 and the first data connection line L13 are located in different film layers, and the third data signal output line 403 and the second data connection line L24 are located in different film layers.

[0241] As shown in FIGS. 7, 9, 11, 12 and 15, a plurality of data signal output lines 40 are arranged on the display panel, the data signal output lines 40 are respectively electrically connected with the pins of the integrated circuit IC and the data signal lines 30, and the integrated circuit IC provides data signals to the data signal lines 30 through the data signal output lines 40.

[0242] Specifically, as shown in FIG. 7, FIG. 9, FIG. 11, FIG. 12 and FIG. 15, the data signal output line 40 includes a first data signal output line 401, a second data signal output line 402 and a third data signal output line 403. In the first pixel circuit column group G1, the first intra-group data signal line L1 and the third intra-group data signal line L3 are electrically connected to the same first data signal output line 401, and the first data signal output line 401 can provide data signals to the first intra-group data signal line L1 and the third intra-group data signal line L3 at the same time. Similarly, in the first pixel circuit column group G1, the second intra-group data signal line L2 and the fourth intra-group data signal line L4 are electrically connected to the same second data signal output line 402, and the second data signal output line 402 can provide data signals to the second intra-group data signal line L2 and the fourth intra-group data signal line L4 at the same time. In the third data signal line 303 connected to the same second pixel circuit column Z2, the first sub-data signal line L5 and the second sub-data signal line L6 are electrically connected to the same third data signal output line 403, and the third data signal output line 403 can provide data signals to the first sub-data signal line L5 and the second sub-data signal line L6 at the same time.

[0243] In this embodiment, as shown in FIG. 7, FIG. 9, FIG. 11, FIG. 12 and FIG. 15, in the direction perpendicular to the plane where the display panel is located, the third data signal output line 403 and the first data connection line L13 overlap, and the third data signal output line 403 and the second data connection line L24 overlap, so that the third data signal output line 403 and the first data connection line L13 are located in different film layers, and the third data signal output line 403 and the second data connection line L24 are located in different film layers, so as to avoid short circuit between the third data signal output line 403 and the first data connection line L13, and between the third data signal output line 403 and the second data connection line L24.

[0244] It should be noted that, under the condition of ensuring that the third data signal output line 403 and the first data connection line L13 are located in different film layers, the first data connection line L13 can be arranged in the same layer as the existing metal film layer structure in the pixel circuit 10, so as to reduce the number of metal layers, which is conducive to reducing the thickness of the display panel; at the same time, the first data connection line L13 can be prepared in the same process as the existing metal film layer structure in the pixel circuit 10, so as to shorten the process time and reduce the manufacturing cost.

[0245] Similarly, under the condition that the third data signal output line 403 and the second data connection line L24 are located in different film layers, the second data connection line L24 can be set in the same layer as the existing metal film layer structure in the pixel circuit 10, thereby reducing the number of metal layers and helping to reduce the thickness of the display panel; at the same time, the second data connection line L24 can also be prepared in the same process as the existing metal film layer structure in the pixel circuit 10, thereby shortening the process time and reducing the manufacturing cost.

[0246] Optionally, the first data connection line L13, the second data connection line L24, and the third data connection line L56 may be located in the same film layer, or at least two of the first data connection line L13, the second data connection line L24, and the third data connection line L56 may be located in different film layers.

[0247] Provided that the first data connection line L13, the second data connection line L24, and the third data connection line L56 do not experience short circuits, the first data connection line L13, the second data connection line L24, and the third data connection line L56 can be configured in the same layer as the existing metal film layer structure in the pixel circuit 10, thereby reducing the number of metal layers and helping to reduce the thickness of the display panel. At the same time, the first data connection line L13, the second data connection line L24, and the third data connection line L56 can also be fabricated in the same process as the existing metal film layer structure in the pixel circuit 10, thereby shortening the process time and reducing manufacturing costs.

[0248] Referring again to Figure 9, optionally, the display panel provided in this embodiment of the invention further includes multiple data signal output lines 40 and multiple gating circuits 50. The data signal output lines 40 include a third data signal output line 403, and the gating circuits 50 include a third gating circuit 503. In the first sub-data signal line L5 and the second sub-data signal line L6 connected to the same second pixel circuit column Z2, the first sub-data signal line L5 and the second sub-data signal line L6 are electrically connected to the same third data signal output line 403 through the third gating circuit 503. The third gating circuit 503 is used to transmit the data signal output by the third data signal output line 403 to the first sub-data signal line L5 and the second sub-data signal line L6 in a time-division multiplexing manner.

[0249] As shown in Figure 9, the display panel is provided with multiple data signal output lines 40. The data signal output lines 40 are electrically connected to the pins of the integrated circuit IC and the data signal line 30, respectively. The integrated circuit IC provides data signals to the data signal line 30 through the data signal output lines 40.

[0250] The data signal output lines 40 include a third data signal output line 403, in the third data signal line 303 connected to the same second pixel circuit column Z2, the first sub-data signal line L5 and the second sub-data signal line L6 are both electrically connected to the same third data signal output line 403, at this time, the third data signal output line 403 can simultaneously provide data signals to the first sub-data signal line L5 and the second sub-data signal line L6.

[0251] Continuing to refer to FIG. 9, if a third data signal output line 403 needs to simultaneously provide data signals to the first sub-data signal line L5 and the second sub-data signal line L6, the capacitive load on the pins of the integrated circuit IC includes the parasitic capacitance of the pixel circuits 10 connected to the first sub-data signal line L5 and the second sub-data signal line L6, which can cause a large capacitive load, and the larger the capacitive load, the more energy required for charging and discharging, and the power consumption increases.

[0252] Based on the above technical problems, in the embodiment, as shown in FIG. 9, a plurality of gating circuits 50 are further provided on the display panel, the gating circuits 50 are used to time-divisionally transmit data signals from the data signal output lines 40 to different data signal lines 30, so that at the same time point, the gating circuits 50 selectively transmit data signals to a data signal line 30, ensuring that the pins of each integrated circuit IC only provide data signals to one data signal line 30 at any time, thereby effectively reducing the capacitive load on the pins of the integrated circuit IC, and further reducing power consumption.

[0253] Specifically, as shown in FIG. 9, the gating circuit 50 includes a third gating circuit 503, in the first sub-data signal line L5 and the second sub-data signal line L6 connected to the same second pixel circuit column Z2, the first sub-data signal line L5 and the second sub-data signal line L6 are both electrically connected to the same third data signal output line 403 through the third gating circuit 503, so as to time-divisionally transmit the data signals output by the third data signal output line 403 to the first sub-data signal line L5 and the second sub-data signal line L6 through the third gating circuit 503, ensuring that the pins of the integrated circuit IC connected to the third data signal output line 403 only provide data signals to the first sub-data signal line L5 or the second sub-data signal line L6 at any time, thereby reducing the capacitive load on the pins of the integrated circuit IC, and further reducing power consumption.

[0254] Continuing to refer to FIG. 9, optionally, the data signal output lines 40, the gating circuits 50 and the integrated circuit IC are all located in the non-display area NAA, which can avoid the data signal output lines 40, the gating circuits 50 and the integrated circuit IC from forming an obstruction to the display area AA, thereby reducing the influence of the data signal output lines 40, the gating circuits 50 and the integrated circuit IC on the display effect.

[0255] In other embodiments, the integrated circuit IC can also be arranged on a flexible circuit board which is connected to the display panel in a binding manner, so as to reduce the area of the non-display area NAA and achieve a narrow frame design. The embodiments of the present application do not make a specific limitation in this regard.

[0256] With continuous reference to FIG. 9, optionally, the data signal output lines 40 extend along the column direction and are arranged along the row direction, so as to facilitate the electrical connection between the data signal output lines 40 and the data signal lines 30 via the pins of the integrated circuit IC, but the present application is not limited thereto, and the embodiments of the present application do not make a specific limitation in this regard.

[0257] With continuous reference to FIG. 9, optionally, the third gating circuit 503 includes a fifth switch transistor M5 and a sixth switch transistor M6. The fifth switch transistor M5 is connected between the first sub-data signal line L5 and the third data signal output line 403, and the sixth switch transistor M6 is connected between the second sub-data signal line L6 and the third data signal output line 403. The gate of the fifth switch transistor M5 receives a third switch signal, and the gate of the sixth switch transistor M6 receives a fourth switch signal.

[0258] Specifically, as shown in FIG. 9, the third gating circuit 503 is composed of the fifth switch transistor M5 and the sixth switch transistor M6. One end of the fifth switch transistor M5 is connected to the first sub-data signal line L5, and the other end is connected to the third data signal output line 403.

[0259] Further, the gate of the fifth switch transistor M5 receives the third switch signal, which is used to control the fifth switch transistor M5 to be turned on or turned off. When the fifth switch transistor M5 is turned on, the first sub-data signal line L5 and the third data signal output line 403 are connected, and at this time, the third data signal output line 403 provides the data signal to the first sub-data signal line L5. When the fifth switch transistor M5 is turned off, the first sub-data signal line L5 and the third data signal output line 403 are insulated.

[0260] The gate of the sixth switch transistor M6 receives the fourth switch signal, which is used to control the sixth switch transistor M6 to be turned on or turned off. When the sixth switch transistor M6 is turned on, the second sub-data signal line L6 and the third data signal output line 403 are connected, and at this time, the third data signal output line 403 provides the data signal to the second sub-data signal line L6. When the sixth switch transistor M6 is turned off, the second sub-data signal line L6 and the third data signal output line 403 are insulated.

[0261] The gate of the fifth switch transistor M5 and the gate of the sixth switch transistor M6 receive different third switch signals and fourth switch signals, so that the fifth switch transistor M5 and the sixth switch transistor M6 are turned on at different times, thereby realizing the time-sharing transmission of the data signal output by the third data signal output line 403 to the first sub-data signal line L5 and the second sub-data signal line L6, ensuring that the integrated circuit IC pin connected with the third data signal output line 403 only provides data signal to the first sub-data signal line L5 or the second sub-data signal line L6 at any time, thereby reducing the capacitive load on the integrated circuit IC pin and reducing power consumption.

[0262] Further, as shown in FIG. 9, the first pixel circuit 101 connected with the first intra-group data signal line L1, the second pixel circuit 102 connected with the fourth intra-group data signal line L4, and the third data signal line 303 connected with the first sub-data signal line L5 are located in the same pixel circuit row, therefore, the third switch signal received by the gate of the fifth switch transistor M5 and the first switch signal SW1 received by the gate of the first switch transistor M1 and the gate of the fourth switch transistor M4 can be set as the same switch signal, so that the fifth switch transistor M5, the first switch transistor M1 and the fourth switch transistor M4 are turned on at the same time, ensuring that the first pixel circuit 101, the second pixel circuit 102 and the third pixel circuit 103 located in the same row simultaneously receive data signals. In this way, the number of switch signals can be reduced, the control logic is simplified, and the number of switch signal lines for transmitting switch signals is reduced, thereby reducing the cost.

[0263] Similarly, the second pixel circuit 102 connected with the second intra-group data signal line L2, the first pixel circuit 101 connected with the third intra-group data signal line L3, and the third data signal line 303 connected with the second sub-data signal line L6 are located in the same pixel circuit row, therefore, the fourth switch signal received by the gate of the sixth switch transistor M6 and the second switch signal SW2 received by the gate of the second switch transistor M2 and the gate of the third switch transistor M3 can be set as the same switch signal, so that the sixth switch transistor M6, the second switch transistor M2 and the third switch transistor M3 are turned on at the same time, ensuring that the first pixel circuit 101, the second pixel circuit 102 and the third pixel circuit 103 located in the same row simultaneously receive data signals. In this way, the number of switch signals can be reduced, the control logic is simplified, and the number of switch signal lines for transmitting switch signals is reduced, thereby reducing the cost.

[0264] FIG. 16 is a structural schematic diagram of another display panel provided by an embodiment of the present application. As shown in FIG. 16, optionally, the third pixel circuit 103 in the second pixel circuit column Z2 is only electrically connected with one third data signal line 303.

[0265] In the embodiment, as shown in FIG. 16, each second pixel circuit column Z2 corresponds to one third data signal line 303, so that the number of third data signal lines 303 can be reduced, and the light transmittance of the display panel can be improved. Meanwhile, the coverage area of the third data signal line 303 is reduced, and the distance between the third data signal line 303 and other signal lines can be increased, so that the coupling effect between the third data signal line 303 and other signal lines can be reduced, and the mutual interference between the signal lines can be reduced.

[0266] FIG. 17 is a structural schematic diagram of another display panel provided by the embodiment of the present application, and FIG. 18 is a structural schematic diagram of another display panel provided by the embodiment of the present application. As shown in FIG. 17 and FIG. 18, optionally, the plurality of second pixel circuit columns Z2 are divided into a plurality of second pixel circuit column groups G2, and each second pixel circuit column group G2 includes two adjacent second pixel circuit columns Z2, which are a third group inner pixel circuit column Z21 and a fourth group inner pixel circuit column Z22, respectively. The third data signal line 303 connected to the third group inner pixel circuit column Z21 is a fifth group inner data signal line L7, and the third data signal line 303 connected to the fourth group inner pixel circuit column Z22 is a sixth group inner data signal line L8.

[0267] In the second pixel circuit column group G2, the fifth group inner data signal line L7 is located on the side of the third group inner pixel circuit column Z21 away from the fourth group inner pixel circuit column Z22, and the sixth group inner data signal line L8 is located on the side of the fourth group inner pixel circuit column Z22 away from the third group inner pixel circuit column Z21.

[0268] Alternatively,

[0269] In the second pixel circuit column group G2, the fifth group inner data signal line L7 is located on the side of the third group inner pixel circuit column Z21 close to the fourth group inner pixel circuit column Z22, and the sixth group inner data signal line L8 is located on the side of the fourth group inner pixel circuit column Z22 close to the third group inner pixel circuit column Z21.

[0270] Specifically, as shown in FIG. 17 and FIG. 18, in the display area AA, the plurality of second pixel circuit column groups G2 are arranged along the row direction, wherein the second pixel circuit column group G2 includes the third group inner pixel circuit column Z21 and the fourth group inner pixel circuit column Z22 arranged adjacently, the third group inner pixel circuit column Z21 includes the third pixel circuits 103 arranged along the column direction in sequence, and the fourth group inner pixel circuit column Z22 includes the third pixel circuits 103 arranged along the column direction in sequence.

[0271] In this embodiment, the third pixel circuit 103 in the third group of inner pixel circuit columns Z21 is connected to the fifth group of inner data signal lines L7, and the third pixel circuit 103 in the fourth group of inner pixel circuit columns Z22 is connected to the sixth group of inner data signal lines L8.

[0272] As shown in FIG. 17, in the second group of pixel circuit columns G2 along the row direction, the fifth group of inner data signal lines L7 is located on the side of the third group of inner pixel circuit columns Z21 away from the fourth group of inner pixel circuit columns Z22, and the sixth group of inner data signal lines L8 is located on the side of the fourth group of inner pixel circuit columns Z22 away from the third group of inner pixel circuit columns Z21, so the fifth group of inner data signal lines L7 and the sixth group of inner data signal lines L8 are respectively located on opposite sides of the two columns of second pixel circuit columns Z2 in the second group of pixel circuit columns G2. In this way, the fifth group of inner data signal lines L7 and the sixth group of inner data signal lines L8 can be symmetrically distributed relative to the central axis of the second group of pixel circuit columns G2, which is beneficial to making the color shift of the display image have better symmetry, so that the four-orientation color shift can be improved, that is, the consistency and accuracy of the color will be improved no matter from which direction the display image is viewed, and then the display image can be viewed from a wider range of angles without feeling obvious color change, enhancing the user experience.

[0273] As shown in FIG. 18, in the second group of pixel circuit columns G2 along the row direction, the fifth group of inner data signal lines L7 is located on the side of the third group of inner pixel circuit columns Z21 close to the fourth group of inner pixel circuit columns Z22, and the sixth group of inner data signal lines L8 is located on the side of the fourth group of inner pixel circuit columns Z22 close to the third group of inner pixel circuit columns Z21, so the fifth group of inner data signal lines L7 and the sixth group of inner data signal lines L8 are both located between the third group of inner pixel circuit columns Z21 and the fourth group of inner pixel circuit columns Z22. In this way, the fifth group of inner data signal lines L7 and the sixth group of inner data signal lines L8 can be symmetrically distributed relative to the central axis of the second group of pixel circuit columns G2, which is beneficial to making the color shift of the display image have better symmetry, so that the four-orientation color shift can be improved, that is, the consistency and accuracy of the color will be improved no matter from which direction the display image is viewed, and then the display image can be viewed from a wider range of angles without feeling obvious color change, enhancing the user experience.

[0274] It should be noted that the central axis of the second group of pixel circuit columns G2 is the central axis extending along the column direction thereof.

[0275] FIG. 19 is a structural schematic diagram of another display panel according to an embodiment of the present application, and FIG. 20 is a structural schematic diagram of another display panel according to an embodiment of the present application. As shown in FIGS. 19 and 20, optionally, the plurality of second pixel circuit columns Z2 are divided into a plurality of second pixel circuit column groups G2, and each second pixel circuit column group G2 includes two adjacent second pixel circuit columns Z2, which are a third group inner pixel circuit column Z21 and a fourth group inner pixel circuit column Z22, respectively. The third data signal line 303 connected to the third group inner pixel circuit column Z21 is a fifth group inner data signal line L7, and the third data signal line 303 connected to the fourth group inner pixel circuit column Z22 is a sixth group inner data signal line L8.

[0276] In the second pixel circuit column group G2, the fifth group inner data signal line L7 is located on the side of the third group inner pixel circuit column Z21 away from the fourth group inner pixel circuit column Z22, and the sixth group inner data signal line L8 is located on the side of the fourth group inner pixel circuit column Z22 close to the third group inner pixel circuit column Z21.

[0277] Alternatively,

[0278] In the second pixel circuit column group G2, the fifth group inner data signal line L7 is located on the side of the third group inner pixel circuit column Z21 close to the fourth group inner pixel circuit column Z22, and the sixth group inner data signal line L8 is located on the side of the fourth group inner pixel circuit column Z22 away from the third group inner pixel circuit column Z21.

[0279] The structure of the third group inner pixel circuit column Z21 and the fourth group inner pixel circuit column Z22 in the second pixel circuit column group G2 and the connection structure of the fifth group inner data signal line L7 and the sixth group inner data signal line L8 can refer to the above embodiments, and will not be described here again.

[0280] In the present embodiment, as shown in FIG. 19, in the second pixel circuit column group G2, the fifth group inner data signal line L7 is located on the side of the third group inner pixel circuit column Z21 away from the fourth group inner pixel circuit column Z22, and the sixth group inner data signal line L8 is located on the side of the fourth group inner pixel circuit column Z22 close to the third group inner pixel circuit column Z21. Along the row direction, the fifth group inner data signal line L7 is located on the left side of the third group inner pixel circuit column Z21, and the sixth group inner data signal line L8 is located on the left side of the fourth group inner pixel circuit column Z22, that is, the third data signal line 303 is located on the same side of the second pixel circuit column Z2 connected thereto.

[0281] In this way, the positional relationship between the third data signal line 303 and the second pixel circuit column Z2 connected therewith can be more consistent. At this time, the parasitic capacitance between the third data signal line 303 and each metal film layer or signal node in the second pixel circuit column Z2 connected therewith is at a similar level. Even if there is a process fluctuation in the process of manufacturing the display panel, the overlapping deviation between the third data signal line 303 and each metal film layer or signal node in the second pixel circuit column Z2 connected therewith has the same trend change, so that the display uniformity of the display panel can be improved, and the vertical stripe phenomenon caused by the brightness difference can be avoided.

[0282] With reference back to FIG. 20, in the second pixel circuit column group G2, the fifth group data signal line L7 is located at the side of the third group pixel circuit column Z21 close to the fourth group pixel circuit column Z22, and the sixth group data signal line L8 is located at the side of the fourth group pixel circuit column Z22 away from the third group pixel circuit column Z21. In the row direction, the fifth group data signal line L7 is located at the right side of the third group pixel circuit column Z21, and the sixth group data signal line L8 is located at the right side of the fourth group pixel circuit column Z22. That is, the third data signal line 303 is located at the same side of the second pixel circuit column Z2 connected therewith.

[0283] In this way, the positional relationship between the third data signal line 303 and the second pixel circuit column Z2 connected therewith can be more consistent. At this time, the parasitic capacitance between the third data signal line 303 and each metal film layer or signal node in the second pixel circuit column Z2 connected therewith is at a similar level. Even if there is a process fluctuation in the process of manufacturing the display panel, the overlapping deviation between the third data signal line 303 and each metal film layer or signal node in the second pixel circuit column Z2 connected therewith has the same trend change, so that the display uniformity of the display panel can be improved, and the vertical stripe phenomenon caused by the brightness difference can be avoided.

[0284] FIG. 21 is a structural schematic diagram of another display panel provided by an embodiment of the present application. As shown in FIG. 21, optionally, in the direction perpendicular to the plane where the display panel is located, the first data signal line 301 and the second data signal line 302 both overlap the first pixel circuit column Z1, and the third data signal line 303 overlaps the second pixel circuit column Z2.

[0285] Specifically, as shown in FIG. 21, in the direction perpendicular to the plane where the display panel is located, the first data signal line 301 and the second data signal line 302 are arranged to overlap the first pixel circuit column Z1, and the third data signal line 303 overlaps the second pixel circuit column Z2, so that the first data signal line 301, the second data signal line 302 and the third data signal line 303 do not need to occupy extra space, which is conducive to improving the pixel density of the display panel.

[0286] FIG. 22 is a structural schematic diagram of another display panel provided by an embodiment of the present application. As shown in FIG. 22, alternatively, the plurality of first pixel circuit columns Z1 and the plurality of second pixel circuit columns Z2 are divided into a plurality of third pixel circuit column groups G3, and each third pixel circuit column group G3 includes a first pixel circuit column Z1 and a second pixel circuit column Z2 adjacent along the row direction, and the first pixel circuit column Z1 and the second pixel circuit column Z2 are mirror arranged.

[0287] Specifically, as shown in FIG. 22, in the display area AA, the plurality of third pixel circuit column groups G3 are arranged along the row direction, wherein each third pixel circuit column group G3 includes a first pixel circuit column Z1 and a second pixel circuit column Z2 adjacent along the row direction, the first pixel circuit column Z1 includes first pixel circuits 101 and second pixel circuits 102 arranged alternately along the column direction, and the second pixel circuit column Z2 includes third pixel circuits 103 arranged sequentially along the column direction.

[0288] In the third pixel circuit column group G3, the first pixel circuit column Z1 and the second pixel circuit column Z2 adjacent along the row direction are mirror arranged, and in the same row of pixel circuits 10, the pixel circuit 10 in the first pixel circuit column Z1 and the pixel circuit 10 in the second pixel circuit column Z2 are adjacent and mirror arranged. When the two pixel circuits 10 are connected to the partial signal line, the two pixel circuits 10 can share a connection via hole, thereby reducing the number of via holes and helping to improve the transmittance of the display panel, and when the display panel is provided with an optical sensing device such as an under-screen fingerprint recognition module, the use performance of the optical sensing device can be improved.

[0289] For example, the pixel circuit 10 shown in FIG. 4 is taken as an example for description. The pixel circuit 10 can include a first light-emitting control transistor T1, a data writing transistor T2, a driving transistor T3, a threshold compensation transistor T4, an initialization reset transistor T5, a second light-emitting control transistor T6, an anode reset transistor T7, a biasing transistor T8, and a storage capacitor Cst.

[0290] One end of the initialization reset transistor T5 is configured to receive a first reference signal VREF1, and the other end of the initialization reset transistor T5 is connected to the gate of the driving transistor T3 at the first node N1. The gate of the initialization reset transistor T5 receives a first scan signal S1N, and the first scan signal S1N is configured to control the turn-on and turn-off of the initialization reset transistor T5. When the initialization reset transistor T5 is turned on, the first reference signal VREF1 is written to the gate of the driving transistor T3, so as to reset the first node N1.

[0291] One plate of the storage capacitor Cst is used to receive the first power signal, and the other plate of the storage capacitor Cst is connected to the first node N1, so that the storage capacitor Cst can stabilize the voltage of the first node N1.

[0292] The threshold compensation transistor T4 is connected between the gate of the driving transistor T3 (i.e. the first node N1) and the second end of the driving transistor T3 (i.e. the third node N3), and the gate of the threshold compensation transistor T4 receives the second scan signal S2N, which is used to control the turn-on and turn-off of the threshold compensation transistor T4. When the threshold compensation transistor T4 is turned on, the threshold voltage of the driving transistor T3 can be compensated.

[0293] One end of the data write transistor T2 is used to receive the data signal DATA, and the other end of the data write transistor T2 is connected to the first end of the driving transistor T3 (i.e. the second node N2). The gate of the data write transistor T2 is used to receive the third scan signal SP, which is used to control the turn-on and turn-off of the data write transistor T2. When the data write transistor T2 is turned on, the data signal DATA can be written to the gate of the driving transistor T3.

[0294] One end of the anode reset transistor T7 is used to receive the second reference signal VREF2, and the other end of the anode reset transistor T7 is connected to the anode of the light emitting element 20. The gate of the anode reset transistor T7 is used to receive the fourth scan signal SPX, which is used to control the turn-on and turn-off of the anode reset transistor T7. When the anode reset transistor T7 is turned on, the second reference signal VREF2 can be written to the anode of the light emitting element 20.

[0295] One end of the first light emitting control transistor T1 is used to receive the positive power voltage PVDD, and the other end of the first light emitting control transistor T1 is connected to the first end of the driving transistor T3 (i.e. the second node N2). One end of the second light emitting control transistor T6 is used to receive the negative power voltage PVEE, and the other end of the second light emitting control transistor T6 is connected to the second end of the driving transistor T3 (i.e. the third node N3). The gate of the first light emitting control transistor T1 and the gate of the second light emitting control transistor T6 are used to receive the light emitting control signal EM, which is used to control the turn-on and turn-off of the first light emitting control transistor T1 and the second light emitting control transistor T6. When the first light emitting control transistor T1 and the second light emitting control transistor T6 are turned on, the positive power voltage PVDD and the negative power voltage PVEE can both be connected to the light emitting element 20, so that the light emitting element 20 can emit light and display.

[0296] One end of the bias transistor T8 is configured to receive a bias signal DVH, the other end of the bias transistor T8 is connected to the first end (i.e. the second node N2) of the drive transistor T3 or the second end (i.e. the third node N3) of the drive transistor T3, and the gate of the bias transistor T8 is configured to receive a fourth scan signal SPX, the fourth scan signal SPX is configured to control the turn-on and turn-off of the bias transistor T8, and the bias transistor T8 is configured to write the bias signal DVH to the first end (i.e. the second node N2) of the drive transistor T3 and / or the second end (i.e. the third node N3) of the drive transistor T3 when the bias transistor T8 is turned on.

[0297] FIG. 23 is a signal timing diagram provided to the pixel circuit shown in FIG. 4 in one driving period according to an embodiment of the present application. As shown in FIG. 4 and FIG. 23, the working process of the pixel circuit 10 can include a pre-stage t10 and a light emitting stage t20. The pre-stage t10 is a stage in which the light emitting element 20 does not emit light, and the light emitting stage t20 is a stage in which the light emitting element 20 emits light. In some cases, the pre-stage t10 and the light emitting stage t20 can be performed sequentially.

[0298] Specifically, as shown in FIG. 4 and FIG. 23, in the pre-stage t10, the light emitting control signal EM is an invalid pulse, and the first light emitting control transistor T1 and the second light emitting control transistor T6 are turned off under the action of the light emitting control signal EM. At this time, the light emitting element 20 does not emit light. In the light emitting stage t20, the light emitting control signal EM is a valid pulse, and the first light emitting control transistor T1 and the second light emitting control transistor T6 are turned on under the action of the light emitting control signal EM. At this time, the drive current generated by the drive transistor T3 can be transmitted to the light emitting element 20, thereby controlling the light emitting element 02 to enter the light emitting stage and emit light.

[0299] It should be noted that the valid pulse of the light emitting control signal EM can be set according to the channel type of the first light emitting control transistor T1 and the second light emitting control transistor T6.

[0300] Specifically, as shown in FIG. 4 and FIG. 23, when the first light emitting control transistor T1 and the second light emitting control transistor T6 are both PMOS transistors, the invalid pulse of the light emitting control signal EM is high, and the valid pulse of the light emitting control signal EM is low.

[0301] In other embodiments, if the first light emitting control transistor T1 and the second light emitting control transistor T6 are NMOS transistors, the invalid pulse of the light emitting control signal EM is low, and the valid pulse of the light emitting control signal EM is high. The embodiments of the present application do not make specific limitations on this.

[0302] Continuing to refer to FIG. 4 and FIG. 23, optionally, the pre-stage t10 of the pixel circuit 10 can include an initialization stage t11.

[0303] In the initialization stage t11, the fourth scanning signal SPX is a low-level effective pulse, so that the anode reset transistor T7 is turned on, and the second reference signal VREF2 is transmitted to the anode of the light emitting element 20 through the anode reset transistor T7 to initialize the anode of the light emitting element 20, so as to prevent the driving current provided to the anode of the light emitting element 20 in the last frame from affecting the display luminance of the light emitting element 20 in the next frame.

[0304] With continuous reference to FIG. 4 and FIG. 23, the pre-stage t10 of the pixel circuit 10 can further include a reset stage t12.

[0305] In the reset stage t12, the first scanning signal S1N is a high-level effective signal, so that the initialization reset transistor T5 is turned on, and the first reference signal VREF1 is transmitted to the gate (i.e., the first node N1) of the driving transistor T3 through the turned-on initialization reset transistor T5, so as to reset the gate of the driving transistor T3, and at this time, the gate potential of the driving transistor T3 is consistent with the potential of the first reference signal VREF1, so as to avoid the data signal carried on the gate of the driving transistor T3 in the last frame from affecting the writing of the data signal in the next frame.

[0306] With continuous reference to FIG. 4 and FIG. 23, the pre-stage t10 of the pixel circuit 10 can further include a data writing stage t13.

[0307] In the data writing stage t13, the third scanning signal SP is a low-level effective pulse, and the second scanning signal S2N is a high-level effective pulse, so that the data writing transistor T2 and the threshold compensation transistor T4 are turned on, at the same time, the gate potential of the driving transistor T3 is consistent with the first reference signal VREF1, and the driving transistor T3 is also turned on, the data signal passes through the data writing transistor T2, the driving transistor T3 and the threshold compensation transistor T4, and is applied to the gate (i.e., the first node N1) of the driving transistor T3, and the potential of the first node N1 is gradually pulled up until the driving transistor T3 is cut off. When the driving transistor T3 is cut off, the gate potential of the driving transistor T3 is Vdata-|Vth|, wherein Vdata is the voltage of the data signal DATA, and |Vth| is the threshold voltage of the driving transistor T3.

[0308] With continuous reference to FIG. 4 and FIG. 23, the display panel can enter a light emitting stage t20 after the data writing stage t13.

[0309] In the light emitting stage t20, the light emitting control signal EM is a low level effective pulse, the first light emitting control transistor T1 and the second light emitting control transistor T6 are turned on. Due to the turn-on of the first light emitting control transistor T1, the positive power supply voltage PVDD is transmitted to the first end (i.e. the second node N2) of the driving transistor T3, and the voltage difference between the first end (i.e. the second node N2) and the gate (i.e. the first node N1) of the driving transistor T3 is PVDD-(Vdata-|Vth|), so that the driving current generated by the driving transistor T3 is K*(Vdata-PVDD)2, K is a coefficient related to the size and material of the driving transistor T3, and thus the driving current generated by the driving transistor T3 is irrelevant to the threshold voltage |Vth| thereof. The driving current is transmitted to the anode of the light emitting element 20 through the turned-on second light emitting control transistor T6, so that the light emitting element 20 emits light.

[0310] With reference back to FIG. 4 and FIG. 23, the pre-stage t10 of the pixel circuit 10 can also include a bias adjustment stage t14.

[0311] In the bias adjustment stage t14, the fourth scan signal SPX is a low level effective pulse, so that the bias transistor T8 is turned on, and the bias signal DVH is input to the first end (i.e. the second node N2) or the second end (i.e. the third node N3) of the driving transistor T3 through the bias transistor T8, so as to adjust the voltage difference between the gate (i.e. the first node N1) and the first end (i.e. the second node N2) or the second end (i.e. the third node N3) of the driving transistor T3, thereby eliminating the reverse electric field generated inside the driving transistor T3, solving the bias problem, avoiding the threshold voltage of the driving transistor T3 from shifting, and thus facilitating the weakening of the flicker phenomenon.

[0312] With reference back to FIG. 4 and FIG. 23, in the bias adjustment stage t14, the second scan signal S2N can be a high level effective pulse, so that the threshold compensation transistor T4 is turned on. At this time, the bias signal DVH can be transmitted to the gate (i.e. the first node N1) of the driving transistor T3 through the threshold compensation transistor T4, so as to keep the potential of the gate (i.e. the first node N1) and the first end (i.e. the second node N2) or the second end (i.e. the third node N3) of the driving transistor T3 consistent, which can further improve the phenomenon of the threshold voltage shift of the driving transistor T3, and thus weaken the flicker phenomenon.

[0313] The bias adjustment stage t14 can be located before the data writing stage t13 or after the data writing stage t13, which is not specifically limited in the embodiments of the present application.

[0314] It can be understood that the above only exemplarily illustrates the type of each transistor in the pixel circuit 10 and the corresponding driving process. In the embodiment of the present application, when the type of each transistor in the pixel circuit 10 changes, by changing the signal received by the gate of each transistor, the driving process similar to the above can also be achieved, which will not be described herein again.

[0315] Further, the types of the transistors in the pixel circuit 10 can be diverse. For example, the transistors can all be low temperature poly-silicon (LTPS) transistors, or all be oxide (IGZO) transistors, or part be LTPS transistors and part be oxide transistors. The LTPS transistors have the advantages of high switching speed, high carrier mobility and small power, and the oxide transistors have the advantage of small leakage current.

[0316] The display panel of low temperature polycrystalline oxide (LTPO) combining LTPS and oxide has not only the advantages of high resolution, high response speed, high brightness, high aperture ratio and the like of the LTPS display panel, but also the advantage of small leakage current of the oxide.

[0317] For example, FIG. 24 is a schematic diagram of a film layer structure of a display panel provided by the embodiment of the present application. As shown in FIG. 24, taking the LTPO display panel as an example, a first semiconductor layer POLY, a first metal layer GAT, a second metal layer MC, a second semiconductor layer IGZO, a third metal layer MG, a fourth metal layer SD1, a fifth metal layer SD2, a sixth metal layer SD3 and an anode layer RE are stacked on one side of a substrate 60. An insulating layer 70 can be arranged between any two adjacent conductive film layers to avoid short circuit between the two adjacent conductive film layers.

[0318] Specifically, FIG. 25 is a structural schematic diagram of a first semiconductor layer in the display panel shown in FIG. 24; FIG. 26 is a structural schematic diagram of a first metal layer in the display panel shown in FIG. 24; FIG. 27 is a structural schematic diagram of a second metal layer in the display panel shown in FIG. 24; FIG. 28 is a structural schematic diagram of a second semiconductor layer in the display panel shown in FIG. 24; FIG. 29 is a structural schematic diagram of a third metal layer in the display panel shown in FIG. 24; FIG. 30 is a structural schematic diagram of a fourth metal layer in the display panel shown in FIG. 24; FIG. 31 is a structural schematic diagram of a fifth metal layer in the display panel shown in FIG. 24; FIG. 32 is a structural schematic diagram of a sixth metal layer in the display panel shown in FIG. 24; FIG. 33 is a structural schematic diagram of an anode layer in the display panel shown in FIG. 24; FIG. 34 is a structural schematic diagram of a partial layer stack in the display panel shown in FIG. 24, specifically a layer stack from the first semiconductor layer to the sixth metal layer; FIG. 35 is a structural schematic diagram of a complete layer stack in the display panel shown in FIG. 24, specifically a layer stack from the first semiconductor layer to the anode layer; FIG. 36 is a structural schematic diagram of a complete layer stack of a pixel circuit in the display panel shown in FIG. 24; and FIG. 37 is a structural schematic diagram of a partial layer stack of a pixel circuit in the display panel shown in FIG. 24, specifically a layer stack from the first semiconductor layer to the fifth metal layer, for the purpose of clearly showing the structure of the pixel circuit.

[0319] The layer stack shown in FIGS. 24-37 can correspond to the pixel circuit 10 shown in FIG. 4, in which the threshold compensation transistor T4 and the initialization reset transistor T5 are oxide (Indium Gallium Zinc Oxide, IGZO) transistors, and the first light-emitting control transistor T1, the data write transistor T2, the drive transistor T3, the second light-emitting control transistor T6, the anode reset transistor T7, and the bias transistor T8 are low-temperature polysilicon (Low Temperature Poly-Silicon, LTPS) transistors.

[0320] As shown in FIGS. 4, 24-37, for example, the active layers of the first light-emitting control transistor T1, the data write transistor T2, the drive transistor T3, the second light-emitting control transistor T6, the anode reset transistor T7, and the bias transistor T8 can be located in the first semiconductor layer POLY.

[0321] The gates 2G of the first light-emitting control transistor T1, the data write transistor T2, the drive transistor T3, the second light-emitting control transistor T6, the anode reset transistor T7, and the bias transistor T8, and the first plate C1 of the storage capacitor Cst can be located in the first metal layer GAT.

[0322] The first metal layer GAT further includes a third scan signal line sp, a fourth scan signal line spx and an emission control signal line em extending in the row direction. The third scan signal line sp is electrically connected with the gate of the data writing transistor T2 and is used for transmitting the third scan signal SP; the fourth scan signal line spx is electrically connected with the gate of the anode reset transistor T7 and the gate of the biasing transistor T8 and is used for transmitting the fourth scan signal SPX; the emission control signal line em is electrically connected with the gate of the first emission control transistor T1 and the gate of the second emission control transistor T6 and is used for transmitting the emission control signal EM.

[0323] The second metal layer MC can include a second plate C2 of a storage capacitor Cst, a second reference signal line vref2 extending in the row direction, a second scan signal line s2n, a first scan signal line s1n and a first reference signal line vref1. The second reference signal line vref2 is electrically connected with the anode reset transistor T7 and is used for transmitting the second reference signal VREF2; the second scan signal line s2n is electrically connected with the gate of the threshold compensation transistor T4 and is used for transmitting the second scan signal S2N; the first scan signal line s1n is electrically connected with the gate of the initialization reset transistor T5 and is used for transmitting the first scan signal S1N; the first reference signal line vref1 is electrically connected with the initialization reset transistor T5 and is used for transmitting the first reference signal VREF1.

[0324] The second semiconductor layer IGZO can include the active layer of the threshold compensation transistor T4 and the active layer of the initialization reset transistor T5.

[0325] The third metal layer MG can include the gate 2M of the threshold compensation transistor T4 and the initialization reset transistor T5, a bias signal line dvh extending in the row direction, the second scan signal line s2n and the first scan signal line s1n. The bias signal line dvh is electrically connected with the biasing transistor T8 and is used for transmitting the bias signal DVH; the second scan signal line s2n is electrically connected with the gate of the threshold compensation transistor T4 and is used for transmitting the second scan signal S2N; the first scan signal line s1n is electrically connected with the gate of the initialization reset transistor T5 and is used for transmitting the first scan signal S1N.

[0326] It should be noted that the first scan signal line s1n of the second metal layer MC and the first scan signal line s1n of the third metal layer MG are electrically connected and can constitute a double-layer wiring structure, which is conducive to reducing the line resistance and in turn can reduce the voltage drop of the first scan signal S1N and ensure the stability of the first scan signal S1N.

[0327] Similarly, the second scan signal line s2n of the second metal layer MC and the second scan signal line s2n of the third metal layer MG form a double-layer wiring structure, which is conducive to reducing the line resistance, and further reducing the voltage drop of the second scan signal S2N, and ensuring the stability of the second scan signal S2N.

[0328] The fourth metal layer SD1 can include a bias signal line dvh extending in the column direction, wherein the bias signal line dvh extending in the column direction and the bias signal line dvh extending in the row direction in the second metal layer MC are electrically connected, and can form a grid wiring structure, which is conducive to reducing the line resistance, and further reducing the voltage drop of the bias signal DVH, and ensuring the stability of the bias signal DVH.

[0329] The fifth metal layer SD2 can include a data signal line 30 and a third power signal line P3 extending in the column direction, wherein the data signal line 30 is used to transmit a data signal DATA, and the third power signal line P3 is used to transmit a positive power voltage PVDD.

[0330] The sixth metal layer SD3 can include a first power signal line P1 extending in the row direction, wherein the first power signal line P1 extending in the row direction and the first power signal line P1 extending in the column direction in the fifth metal layer SD2 are electrically connected, and can form a grid wiring structure, which is conducive to reducing the line resistance, and further reducing the voltage drop of the positive power voltage PVDD, and ensuring the stability of the positive power voltage PVDD.

[0331] The anode layer RE can include an anode 111 of the light emitting element.

[0332] It should be noted that for the specific film layer arrangement of the display panel, adaptive adjustment can be made according to actual needs, such as adding or removing part of the film layer, and the present embodiment does not make specific limitations.

[0333] Further, as shown in FIGS. 34-37, in the third pixel circuit column group G3, the adjacent first pixel circuit column Z1 and the second pixel circuit column Z2 are mirror arranged, at this time, in the same row of pixel circuits 10, the pixel circuit 10 located in the first pixel circuit column Z1 and the pixel circuit 10 located in the second pixel circuit column Z2 are adjacent and mirror arranged, then when the two pixel circuits 10 are connected with part of the signal lines, the two pixel circuits 10 can share a connection via hole, thereby reducing the number of via holes, which is helpful to improve the transmittance of the display panel, and when the display panel is provided with an optical sensing device such as an under-screen fingerprint recognition module, it is helpful to improve the use performance of the optical sensing device.

[0334] With reference back to FIGS. 22, 34-37, optionally, in the third pixel circuit column group G3, the first data signal line 301 and the second data signal line 302 connected to the first pixel circuit column Z1 are located between the first pixel circuit column Z1 and the second pixel circuit column Z2, and the third data signal line 303 connected to the second pixel circuit column Z2 is also located between the first pixel circuit column Z1 and the second pixel circuit column Z2.

[0335] Specifically, as shown in FIGS. 22, 34-37, in the third pixel circuit column group G3, the first data signal line 301, the second data signal line 302 and the third data signal line 303 are located between the first pixel circuit column Z1 and the second pixel circuit column Z2, so as to concentrate the first data signal line 301, the second data signal line 302 and the third data signal line 303 in the third pixel circuit column group G3, and at this time, the first data signal line 301, the second data signal line 302 and the third data signal line 303 in the third pixel circuit column group G3 have a relatively close distance, so that the parasitic capacitance between the first data signal line 301, the second data signal line 302 and the third data signal line 303 in the third pixel circuit column group G3 and other metal film layers or signal nodes in the pixel circuit 10 in the third pixel circuit column group G3 is at a similar level, which helps to reduce the loss difference between the data signals transmitted on the first data signal line 301, the second data signal line 302 and the third data signal line 303, thereby facilitating to improve the display uniformity.

[0336] It should be noted that the boundary of the pixel circuit column Z can be set as the gate boundary of the driving transistor T3 of the pixel circuit 10 in the pixel circuit column, and then the data signal line 30 in the third pixel circuit column group G3 is located between the first pixel circuit column Z1 and the second pixel circuit column Z2, which can be understood as that, in the row direction, the data signal line 30 is located between the gates of the driving transistors T3 of the pixel circuits 10 in the first pixel circuit column Z1 and the second pixel circuit column Z2.

[0337] With reference back to FIGS. 22, 34 and 35, optionally, in the two adjacent third pixel circuit column groups G3, the arrangement directions of the first data signal line 301 and the second data signal line 302 in different third pixel circuit column groups G3 are the same or opposite.

[0338] Specifically, as shown in FIG. 22, in the two adjacent third pixel circuit column groups G3, the arrangement directions of the first data signal line 301 and the second data signal line 302 in different third pixel circuit column groups G3 are opposite. Then, in the two adjacent third pixel circuit column groups G3, the first data signal line 301, the second data signal line 302, the third data signal line 303, the third data signal line 303, the second data signal line 302, the first data signal line 301, the third data signal line 303, the third data signal line 303 are arranged in the row direction in sequence.

[0339] Alternatively, FIG. 38 is a structural schematic diagram of another display panel provided by an embodiment of the present application. As shown in FIGS. 34, 35 and 38, in the two adjacent third pixel circuit column groups G3, the second data signal line 302, the first data signal line 301, the third data signal line 303, the third data signal line 303, the first data signal line 301, the second data signal line 302, the third data signal line 303, the third data signal line 303 are arranged in the row direction in sequence.

[0340] In another embodiment, in the two adjacent third pixel circuit column groups G3, the first data signal line 301, the third data signal line 303, the second data signal line 302, the third data signal line 303, the second data signal line 302, the third data signal line 303, the first data signal line 301, the third data signal line 303 can also be arranged in the row direction in sequence; or, the second data signal line 302, the third data signal line 303, the first data signal line 301, the third data signal line 303, the first data signal line 301, the third data signal line 303, the second data signal line 302, the third data signal line 303 can also be arranged in the row direction in sequence.

[0341] In yet another embodiment, in the two adjacent third pixel circuit column groups G3, the first data signal line 301, the third data signal line 303, the third data signal line 303, the second data signal line 302, the second data signal line 302, the third data signal line 303, the third data signal line 303, the first data signal line 301 can also be arranged in the row direction in sequence; or, the second data signal line 302, the third data signal line 303, the third data signal line 303, the first data signal line 301, the first data signal line 301, the third data signal line 303, the third data signal line 303, the second data signal line 302 can also be arranged in the row direction in sequence.

[0342] In this way, the first data signal line 301 and the second data signal line 302 in the two adjacent third pixel circuit column groups G3 are symmetrically distributed, which is beneficial to make the color deviation of the display screen have better symmetry, thereby improving the four-orientation color deviation, that is, the consistency and accuracy of the color are improved no matter from which direction the display screen is viewed, and the display screen can be viewed from a wider angle range without obvious color change, thereby enhancing the user experience.

[0343] FIG. 39 is a structural schematic diagram of another display panel provided by an embodiment of the present application, and FIG. 40 is a structural schematic diagram of another display panel provided by an embodiment of the present application. As shown in FIGS. 39 and 40, optionally, in the two adjacent third pixel circuit column groups G3, the arrangement directions of the first data signal line 301 and the second data signal line 302 in different third pixel circuit column groups G3 are the same.

[0344] Specifically, as shown in FIG. 39, in the two adjacent third pixel circuit column groups G3, the first data signal line 301, the second data signal line 302, the third data signal line 303, the third data signal line 303, the first data signal line 301, the second data signal line 302, the third data signal line 303, and the third data signal line 303 are sequentially arranged in the row direction.

[0345] As shown in FIG. 40, optionally, in the two adjacent third pixel circuit column groups G3, the second data signal line 302, the first data signal line 301, the third data signal line 303, the third data signal line 303, the second data signal line 302, the first data signal line 301, the third data signal line 303, and the third data signal line 303 are sequentially arranged in the row direction.

[0346] In another embodiment, in the two adjacent third pixel circuit column groups G3, the first data signal line 301, the third data signal line 303, the second data signal line 302, the third data signal line 303, the first data signal line 301, the third data signal line 303, the second data signal line 302, and the third data signal line 303 can also be sequentially arranged in the row direction; or the second data signal line 302, the third data signal line 303, the first data signal line 301, the third data signal line 303, the second data signal line 302, the third data signal line 303, the first data signal line 301, and the third data signal line 303 can also be sequentially arranged in the row direction.

[0347] In yet another embodiment, in the two adjacent third pixel circuit column groups G3, the first data signal line 301, the third data signal line 303, the third data signal line 303, the second data signal line 302, the first data signal line 301, the third data signal line 303, the third data signal line 303, and the second data signal line 302 are sequentially arranged in the row direction; or the second data signal line 302, the third data signal line 303, the third data signal line 303, the first data signal line 301, the second data signal line 302, the third data signal line 303, the third data signal line 303, and the first data signal line 301 are sequentially arranged in the row direction.

[0348] In this way, the positional relationship between the data signal line 30 connected to the sub-pixel of the same color and the pixel circuit 10 connected thereto is more consistent, and at this time, the parasitic capacitance between the respective metal film layers or signal nodes in the data signal line 30 connected to the sub-pixel of the same color and the pixel circuit 10 connected thereto is at a similar level, so that even if there is process fluctuation in the process of manufacturing the display panel, the overlapping deviation between the respective metal film layers or signal nodes in the data signal line 30 connected to the sub-pixel of the same color and the pixel circuit 10 connected thereto has the same trend change, thereby improving the display uniformity of the display panel and avoiding the vertical stripe phenomenon caused by the difference in brightness.

[0349] FIG. 41 is a structural schematic diagram of yet another display panel provided by an embodiment of the present application, FIG. 42 is a structural schematic diagram of yet another display panel provided by an embodiment of the present application, FIG. 43 is a structural schematic diagram of yet another display panel provided by an embodiment of the present application, and FIG. 44 is a structural schematic diagram of yet another display panel provided by an embodiment of the present application. As shown in FIGS. 41-44, optionally, the present embodiment further includes a plurality of third power signal lines P3, which extend along the column direction and are arranged along the row direction. The plurality of third power signal lines P3 includes a first sub-power signal line P3A, a second sub-power signal line P3B, and a third sub-power signal line P3C, which are sequentially and adjacently arranged along the row direction. The arrangement direction of the first data signal line 301 and the second data signal line 302 between the first sub-power signal line P3A and the second sub-power signal line P3B is the same as or opposite to the arrangement direction of the first data signal line 301 and the second data signal line 302 between the second sub-power signal line P3B and the third sub-power signal line P3C.

[0350] Specifically, as shown in FIGS. 34, 35, and 41-44, every two columns of pixel circuits 10 can correspond to a third power signal line P3 extending along the column direction, and the third power signal line P3 is used to transmit a positive power voltage PVDD.

[0351] In this case, as shown in FIGS. 34, 35, 41, and 42, in the row direction, three third power supply signal lines P3 that are sequentially adjacent are set as a first sub power supply signal line P3A, a second sub power supply signal line P3B, and a third sub power supply signal line P3C, respectively. Then, the arrangement direction of the first data signal line 301 and the second data signal line 302 between the first sub power supply signal line P3A and the second sub power supply signal line P3B can be opposite to the arrangement direction of the first data signal line 301 and the second data signal line 302 between the second sub power supply signal line P3B and the third sub power supply signal line P3C.

[0352] For example, as shown in FIG. 41, between the first sub power supply signal line P3A and the second sub power supply signal line P3B, the first data signal line 301, the second data signal line 302, the third data signal line 303, and the third data signal line 303 are arranged in the row direction in this order; and between the second sub power supply signal line P3B and the third sub power supply signal line P3C, the second data signal line 302, the first data signal line 301, the third data signal line 303, and the third data signal line 303 are arranged in the row direction in this order.

[0353] Alternatively, as shown in FIGS. 34, 35, and 42, between the first sub power supply signal line P3A and the second sub power supply signal line P3B, the second data signal line 302, the first data signal line 301, the third data signal line 303, and the third data signal line 303 are arranged in the row direction in this order; and between the second sub power supply signal line P3B and the third sub power supply signal line P3C, the first data signal line 301, the second data signal line 302, the third data signal line 303, and the third data signal line 303 are arranged in the row direction in this order.

[0354] In another embodiment, between the first sub power supply signal line P3A and the second sub power supply signal line P3B, the first data signal line 301, the third data signal line 303, the second data signal line 302, and the third data signal line 303 can be arranged in the row direction in this order; and between the second sub power supply signal line P3B and the third sub power supply signal line P3C, the second data signal line 302, the third data signal line 303, the first data signal line 301, and the third data signal line 303 can be arranged in the row direction in this order. Alternatively, between the first sub power supply signal line P3A and the second sub power supply signal line P3B, the second data signal line 302, the third data signal line 303, the first data signal line 301, and the third data signal line 303 can be arranged in the row direction in this order; and between the second sub power supply signal line P3B and the third sub power supply signal line P3C, the first data signal line 301, the third data signal line 303, the second data signal line 302, and the third data signal line 303 can be arranged in the row direction in this order.

[0355] In yet another embodiment, the first data signal line 301, the third data signal line 303, the third data signal line 303, and the second data signal line 302 are arranged in sequence in the row direction between the first sub-power signal line P3A and the second sub-power signal line P3B; and the second data signal line 302, the third data signal line 303, the third data signal line 303, and the first data signal line 301 are arranged in sequence in the row direction between the second sub-power signal line P3B and the third sub-power signal line P3C. Alternatively, the second data signal line 302, the third data signal line 303, the third data signal line 303, and the first data signal line 301 are arranged in sequence in the row direction between the first sub-power signal line P3A and the second sub-power signal line P3B; and the first data signal line 301, the third data signal line 303, the third data signal line 303, and the second data signal line 302 are arranged in sequence in the row direction between the second sub-power signal line P3B and the third sub-power signal line P3C.

[0356] In this way, the first data signal line 301 and the second data signal line 302 are symmetrically distributed between the first sub-power signal line P3A and the second sub-power signal line P3B, and between the second sub-power signal line P3B and the third sub-power signal line P3C, which is beneficial to make the color shift of the display image have better symmetry, so that the four-orientation color shift can be improved, that is, the consistency and accuracy of the color will be improved no matter which direction the display image is viewed from, and the display image can be viewed from a wider angle range without feeling obvious color change, thereby enhancing the user experience.

[0357] With continued reference to FIGS. 43 and 44, optionally, the arrangement direction of the first data signal line 301 and the second data signal line 302 between the first sub-power signal line P3A and the second sub-power signal line P3B is the same as the arrangement direction of the first data signal line 301 and the second data signal line 302 between the second sub-power signal line P3B and the third sub-power signal line P3C.

[0358] In this way, the first data signal line 301 and the second data signal line 302 are symmetrically distributed between the first sub-power signal line P3A and the second sub-power signal line P3B, and between the second sub-power signal line P3B and the third sub-power signal line P3C, which is beneficial to make the color shift of the display image have better symmetry, so that the four-orientation color shift can be improved, that is, the consistency and accuracy of the color will be improved no matter which direction the display image is viewed from, and the display image can be viewed from a wider angle range without feeling obvious color change, thereby enhancing the user experience.

[0359] As shown in FIG. 44, alternatively, between the first sub power signal line P3A and the second sub power signal line P3B, the second data signal line 302, the first data signal line 301, the third data signal line 303, and the third data signal line 303 are arranged in sequence in the row direction; and between the second sub power signal line P3B and the third sub power signal line P3C, the second data signal line 302, the first data signal line 301, the third data signal line 303, and the third data signal line 303 are arranged in sequence in the row direction.

[0360] In another embodiment, between the first sub power signal line P3A and the second sub power signal line P3B, the first data signal line 301, the third data signal line 303, the second data signal line 302, and the third data signal line 303 are arranged in sequence in the row direction; and between the second sub power signal line P3B and the third sub power signal line P3C, the first data signal line 301, the third data signal line 303, the second data signal line 302, and the third data signal line 303 are arranged in sequence in the row direction; or, between the first sub power signal line P3A and the second sub power signal line P3B, the second data signal line 302, the third data signal line 303, the first data signal line 301, and the third data signal line 303 are arranged in sequence in the row direction; and between the second sub power signal line P3B and the third sub power signal line P3C, the second data signal line 302, the third data signal line 303, the first data signal line 301, and the third data signal line 303 are arranged in sequence in the row direction.

[0361] In yet another embodiment, between the first sub power signal line P3A and the second sub power signal line P3B, the first data signal line 301, the third data signal line 303, the third data signal line 303, and the second data signal line 302 are arranged in sequence in the row direction; and between the second sub power signal line P3B and the third sub power signal line P3C, the first data signal line 301, the third data signal line 303, the third data signal line 303, and the second data signal line 302 are arranged in sequence in the row direction; or, between the first sub power signal line P3A and the second sub power signal line P3B, the second data signal line 302, the third data signal line 303, the third data signal line 303, and the first data signal line 301 are arranged in sequence in the row direction; and between the second sub power signal line P3B and the third sub power signal line P3C, the third data signal line 303, the third data signal line 303, and the first data signal line 301 are arranged in sequence in the row direction.

[0362] In this way, the positional relationship between the data signal line 30 connected to the sub-pixel of the same color and the pixel circuit 10 connected thereto can be more consistent. At this time, the parasitic capacitance between the respective metal film layers or signal nodes in the data signal line 30 connected to the sub-pixel of the same color and the pixel circuit 10 connected thereto is at a similar level. Therefore, even if there is a process fluctuation during the preparation of the display panel, the overlapping deviation between the respective metal film layers or signal nodes in the data signal line 30 connected to the sub-pixel of the same color and the pixel circuit 10 connected thereto has the same trend change. Thus, the display uniformity of the display panel can be improved, and the vertical stripe phenomenon caused by the brightness difference can be avoided.

[0363] FIG. 45 is a schematic view of the stack structure of another partial film layer in the display panel shown in FIG. 24, specifically, the stack structure of the first semiconductor layer, the first metal layer, the fourth metal layer, and the fifth metal layer. As shown in FIGS. 25, 26, 30, 31, and 45, the pixel circuit 10 can include a data writing transistor T2, and the active layer of the data writing transistor T2 includes a first connection end E1. In the third pixel circuit column group G3, along the row direction, the first connection end E1 of the first pixel circuit 101 is located on the side of the second data signal line 302 close to the first data signal line 301, and the first data signal line 301 and the first connection end E1 of the first pixel circuit 101 form an electrical connection. In the third pixel circuit column group G3, along the row direction, the first connection end E1 of the second pixel circuit 102 is located on the side of the first data signal line 301 close to the second data signal line 302, and the second data signal line 302 and the first connection end E1 of the second pixel circuit 102 form an electrical connection.

[0364] Specifically, as shown in FIGS. 25, 26, 30, 31, and 45, the data writing transistor T2 is configured to write the data signal DATA from the data signal line 30 into the pixel circuit 10.

[0365] In this way, the positional relationship between the data signal line 30 connected to the sub-pixel of the same color and the pixel circuit 10 connected thereto can be more consistent. At this time, the parasitic capacitance between the respective metal film layers or signal nodes in the data signal line 30 connected to the sub-pixel of the same color and the pixel circuit 10 connected thereto is at a similar level. Therefore, even if there is a process fluctuation during the preparation of the display panel, the overlapping deviation between the respective metal film layers or signal nodes in the data signal line 30 connected to the sub-pixel of the same color and the pixel circuit 10 connected thereto has the same trend change. Thus, the display uniformity of the display panel can be improved, and the vertical stripe phenomenon caused by the brightness difference can be avoided.

[0366] Specifically, as shown in FIG. 25, FIG. 26, FIG. 30, FIG. 31 and FIG. 45, in the third pixel circuit column group G3, along the row direction, the first connecting end E1 of the first pixel circuit 101 is located on the side of the second data signal line 302 close to the first data signal line 301, so that the first connecting end E1 of the first pixel circuit 101 is closer to the first data signal line 301 in the row direction, so that the electrical connection between the first connecting end E1 of the first pixel circuit 101 and the first data signal line 301 is easy to realize, and the additional resistance and capacitance that may be introduced in the connection process can be reduced, which is beneficial to improve the transmission efficiency of the data signal.

[0367] Further, in the third pixel circuit column group G3, along the row direction, the first connecting end E1 of the second pixel circuit 102 is located on the side of the first data signal line 301 close to the second data signal line 302, so that the first connecting end E1 of the second pixel circuit 102 is closer to the second data signal line 302 in the row direction, so that the electrical connection between the first connecting end E1 of the second pixel circuit 102 and the second data signal line 302 is easy to realize, and the additional resistance and capacitance that may be introduced in the connection process can be reduced, which is beneficial to improve the transmission efficiency of the data signal.

[0368] Optionally, the active layer of the data writing transistor T2 is located in the first semiconductor layer POLY, and the first data signal line 301 and the second data signal line 302 are located in the fifth metal layer SD2. The electrical connection between the first connecting end E1 of the first pixel circuit 101 and the first data signal line 301, and the electrical connection between the first connecting end E1 of the second pixel circuit 102 and the second data signal line 302 can be realized by punching a hole in the insulating layer 70 between the first semiconductor layer POLY and the fifth metal layer SD2.

[0369] Further, with continued reference to FIGS. 25, 26, 30, 31 and 45, optionally, the fourth metal layer SD1 includes a first connecting portion 71 and a second connecting portion 72, the first connecting end portion E1 of the first pixel circuit 101 and the first data signal line 301 can be electrically connected through the first connecting portion 71, for example, the first connecting portion 71 is punch connected with the first connecting end portion E1 of the first pixel circuit 101, and the first data signal line 301 is punch connected with the first connecting portion 71, so as to reduce the punch depth each time, thereby avoiding the circuit breakage caused by the too large punch depth. Similarly, the first connecting end portion E1 of the second pixel circuit 102 and the second data signal line 302 can be electrically connected through the second connecting portion 72, for example, the second connecting portion 72 is punch connected with the first connecting end portion E1 of the second pixel circuit 102, and the second data signal line 302 is punch connected with the second connecting portion 72, so as to reduce the punch depth each time, thereby avoiding the circuit breakage caused by the too large punch depth.

[0370] With continued reference to FIGS. 25, 26, 30, 31 and 45, optionally, a column of the second pixel circuit column Z2 can correspond to be provided with two third data signal lines 303, one of the third data signal lines 303 is electrically connected with the odd row third pixel circuit 103 in the second pixel circuit column Z2, and the other third data signal line 303 is electrically connected with the even row third pixel circuit 103 in the second pixel circuit column Z2.

[0371] The connection structure between the first connecting end portion E1 of the third pixel circuit 103 and the corresponding third data signal line 303 can refer to the connection structure between the first connecting end portion E1 of the first pixel circuit 101 and the first data signal line 301, and the connection structure between the first connecting end portion E1 of the second pixel circuit 102 and the second data signal line 302, so as to make the connection structure between the first connecting end portion E1 of the third pixel circuit 103 and the corresponding third data signal line 303 symmetrical with the connection structure between the first connecting end portion E1 of the first pixel circuit 101 and the first data signal line 301, and the connection structure between the first connecting end portion E1 of the second pixel circuit 102 and the second data signal line 302, which is beneficial to make the color shift of the display picture have better symmetry, thereby the four-orientation color shift can be improved, which will not be described herein again.

[0372] Fig. 46 is a structural schematic diagram of another display panel according to an embodiment of the present application, and Fig. 47 is a structural schematic diagram of another display panel according to an embodiment of the present application. As shown in Figs. 46 and 47, the display area AA can include a first display area AA1 and a second display area AA2. In the row direction, the first display area AA1 is located at least one side of the second display area AA2. The display panel further includes a plurality of auxiliary signal lines FIAA extending in the column direction and arranged in the row direction. The auxiliary signal lines FIAA are at least partially located in the second display area AA2, and the auxiliary signal lines FIAA are electrically connected with the data signal lines 30 in the first display area AA1. In the third pixel circuit column group G3, the auxiliary signal line FIAA is located between the data signal line 30 connected with the first pixel circuit column Z1 and the data signal line 30 connected with the second pixel circuit column Z2.

[0373] Specifically, as shown in Figs. 46 and 47, the display area AA can include a first display area AA1 and a second display area AA2. In the row direction, the first display area AA1 is located at both sides of the second display area AA2. In the example shown in the figures, the first display area AA1 is located between the second display area AA2 and the non-display areas NAA on the left and right sides. In the row direction, the second display area AA2 is closer to the center of the display panel, and the first display area AA1 is closer to the edge of the display panel. In this arrangement, the non-display area NAA includes a fan-out area NAA1 located on one side of the display area AA in the column direction. In the example shown in the figures, the fan-out area NAA1 is located on the lower side. The fan-out area NAA1 can be provided with a plurality of data signal output lines 40, which are electrically connected with the data signal lines 30 and the integrated circuit IC, respectively, thereby realizing the electrical connection between the integrated circuit IC and the data signal lines 30 and ensuring the stable transmission of data signals. However, the present application is not limited thereto.

[0374] Further, as shown in Figs. 46 and 47, a plurality of data signal lines 30 are provided in the first display area AA1 and the second display area AA2. The data signal lines 30 located in the second display area AA2 can be directly connected with the data signal output lines 40, and the data signal lines 30 located in the first display area AA1 are connected with the data signal output lines 40 through the auxiliary signal lines FIAA at least partially located in the second display area AA2. In this way, the data signal output lines 40 can be concentrated in the fan-out area NAA1 below the second display area AA2, thereby reducing the occupied space of the data signal output lines 40 and further reducing the setting area of the fan-out area NAA1, effectively reducing the area ratio of the non-display area NAA and realizing a narrow frame effect.

[0375] With reference back to FIG. 47, in the third pixel circuit column group G3, the auxiliary signal line FIAA is located between the first data signal line 301 and the second data signal line 302 connected by the first pixel circuit column Z1 and the third data signal line 303 connected by the second pixel circuit column Z2, and since the auxiliary signal line FIAA is also used to transmit data signals, the auxiliary signal line FIAA, the first data signal line 301, the second data signal line 302 and the third data signal line 303 are placed in a centralized manner, at this time, the auxiliary signal line FIAA, the first data signal line 301, the second data signal line 302 and the third data signal line 303 have a close distance, which helps to reduce the parasitic capacitance between the auxiliary signal line FIAA, the first data signal line 301, the second data signal line 302 and the third data signal line 303 and the metal film layer or signal node in the pixel circuit 10, thereby helping to reduce the loss difference between the data signals transmitted by the auxiliary signal line FIAA, the first data signal line 301, the second data signal line 302 and the third data signal line 303, and thereby helping to improve display uniformity.

[0376] Meanwhile, the auxiliary signal line FIAA is located between the data signal line 30 connected by the first pixel circuit column Z1 and the data signal line 30 connected by the second pixel circuit column Z2, which can reduce the influence of the auxiliary signal line FIAA on the connection between the pixel circuit 10 and the data signal line 30 in the first pixel circuit column Z1 and the second pixel circuit column Z2.

[0377] With reference back to FIG. 47, optionally, the auxiliary signal line FIAA corresponding to one third pixel circuit column group G3 is less than or equal to 1.

[0378] Specifically, as shown in FIG. 47, since one first pixel circuit column Z1 is provided with two data signal lines 30 and one second pixel circuit column Z2 is provided with one data signal line 30, at least three data signal lines 30 are provided in the third pixel circuit column group G3, and in this embodiment, by setting the auxiliary signal line FIAA corresponding to one third pixel circuit column group G3 to be less than or equal to 1, it is avoided that the signal lines for transmitting data signals in the third pixel circuit column group G3 are too dense due to too many signal lines for transmitting data signals, thereby ensuring that there is sufficient spacing between the signal lines for transmitting data signals, and thereby reducing the coupling capacitance between the data signal lines 30 and the auxiliary signal line FIAA and reducing the mutual interference between the data signals of the data signal lines 30 and the auxiliary signal line FIAA.

[0379] It should be noted that FIG. 47 only takes one third pixel circuit column group G3 corresponding to one auxiliary signal line FIAA as an example for description, but is not limited thereto.

[0380] Figure 48 is a schematic view of a partial cross-sectional structure of a display panel according to an embodiment of the present application. As shown in Figures 47 and 48, the display area AA can include a first display area AA1 and a second display area AA2, and the first display area AA1 can be located at least on one side of the second display area AA2 along the row direction. The display panel can further include a plurality of auxiliary signal lines FIAA, which extend along the column direction and are arranged along the row direction. The auxiliary signal lines FIAA can be located at least in the second display area AA2, and the auxiliary signal lines FIAA can be electrically connected to the data signal lines 30 in the first display area AA1.

[0381] The auxiliary signal lines FIAA and the data signal lines 30 can be located in different film layers.

[0382] In a direction perpendicular to the plane of the display panel, the auxiliary signal lines FIAA and the data signal lines 30 can at least partially overlap.

[0383] Alternatively,

[0384] In a direction perpendicular to the plane of the display panel, the auxiliary signal lines FIAA and the data signal lines 30 can not overlap.

[0385] The positional relationship between the first display area AA1 and the second display area AA2, the distribution and connection structure of the auxiliary signal lines FIAA can refer to the above embodiments, and will not be described here.

[0386] In this embodiment, as shown in Figures 47 and 48, the auxiliary signal lines FIAA and the data signal lines 30 can be located in different film layers, which can increase the distance between the auxiliary signal lines FIAA and the data signal lines 30, thereby reducing the coupling capacitance between the auxiliary signal lines FIAA and the data signal lines 30, and further reducing the mutual interference of data signals between the auxiliary signal lines FIAA and the data signal lines 30.

[0387] Further, as shown in Figures 47 and 48, and in a direction perpendicular to the plane of the display panel, the auxiliary signal lines FIAA and the data signal lines 30 can not overlap, which can further reduce the coupling capacitance between the auxiliary signal lines FIAA and the data signal lines 30, and further reduce the mutual interference of data signals between the auxiliary signal lines FIAA and the data signal lines 30.

[0388] Figure 49 is a schematic view of a partial cross-sectional structure of a display panel according to an embodiment of the present application. As shown in Figure 49, the auxiliary signal lines FIAA and the data signal lines 30 can at least partially overlap in a direction perpendicular to the plane of the display panel.

[0389] In this way, the total blocking area of the auxiliary signal line FIAA and the data signal line 30 in the thickness direction of the display panel can be reduced, the influence of the auxiliary signal line FIAA and the data signal line 30 on the display effect of the display area AA can be reduced, and the light transmission area of the display panel can be increased.

[0390] Fig. 50 is a structural schematic diagram of another display panel provided by an embodiment of the present application, Fig. 51 is a structural schematic diagram of another display panel provided by an embodiment of the present application, Fig. 52 is a structural schematic diagram of another display panel provided by an embodiment of the present application, and Fig. 53 is a structural schematic diagram of another display panel provided by an embodiment of the present application. As shown in Figs. 50-53, optionally, one column of first pixel circuit columns Z1 corresponds to one auxiliary signal line FIAA, and one column of second pixel circuit columns Z2 corresponds to one auxiliary signal line FIAA.

[0391] In the third pixel circuit column group G3, the auxiliary signal line FIAA corresponding to the first pixel circuit column Z1 is located between the first data signal line 301 and the second data signal line 302 corresponding to the first pixel circuit column Z1, and the auxiliary signal line FIAA corresponding to the second pixel circuit column Z2 is located between the two third data signal lines 303 corresponding to the second pixel circuit column Z2.

[0392] Alternatively,

[0393] In the third pixel circuit column group G3, along the row direction, the auxiliary signal line FIAA corresponding to the first pixel circuit column Z1 is located on the same side of the first data signal line 301 and the second data signal line 302 corresponding to the first pixel circuit column Z1, and the auxiliary signal line FIAA corresponding to the second pixel circuit column Z2 is located on the same side of the two third data signal lines 303 corresponding to the second pixel circuit column Z2.

[0394] Alternatively,

[0395] In the direction perpendicular to the plane where the display panel is located, the auxiliary signal line FIAA corresponding to the first pixel circuit column Z1 at least partially overlaps the data signal line 30 corresponding to the first pixel circuit column Z1, and the auxiliary signal line FIAA corresponding to the second pixel circuit column Z2 at least partially overlaps the data signal line 30 corresponding to the second pixel circuit column Z2.

[0396] Specifically, as shown in Figs. 50-53, one column of first pixel circuit columns Z1 is provided with one auxiliary signal line FIAA, and one column of second pixel circuit columns Z2 is provided with one auxiliary signal line FIAA. Then, one third pixel circuit column group G3 is provided with two auxiliary signal lines FIAA, so as to increase the number of auxiliary signal lines FIAA. In this way, the setting area of the first display area AA1 can be increased, and the narrow frame effect can be achieved.

[0397] As shown in FIG. 50, in the third pixel circuit column group G3, the auxiliary signal line FIAA corresponding to the first pixel circuit column Z1 is located between the first data signal line 301 and the second data signal line 302 corresponding to the first pixel circuit column Z1, so as to place the auxiliary signal line FIAA corresponding to the first pixel circuit column Z1 and the first data signal line 301 and the second data signal line 302 in a centralized manner, so that the auxiliary signal line FIAA corresponding to the first pixel circuit column Z1, the first data signal line 301 and the second data signal line 302 are at a similar level of parasitic capacitance between each metal film layer or signal node in the pixel circuit 10, which helps to reduce the loss difference between the data signals transmitted on the auxiliary signal line FIAA corresponding to the first pixel circuit column Z1 and the first data signal line 301 and the second data signal line 302, thereby facilitating to improve the display uniformity.

[0398] Further, as shown in FIG. 50, in the direction perpendicular to the plane where the display panel is located, there is no overlapping area between the auxiliary signal line FIAA corresponding to the first pixel circuit column Z1 and the first data signal line 301 and the second data signal line 302, which can reduce the coupling capacitance between the auxiliary signal line FIAA corresponding to the first pixel circuit column Z1 and the first data signal line 301 and the second data signal line 302, and further reduce the mutual interference of the data signals between the auxiliary signal line FIAA corresponding to the first pixel circuit column Z1 and the first data signal line 301 and the second data signal line 302.

[0399] Similarly, as shown in FIG. 50, the auxiliary signal line FIAA corresponding to the second pixel circuit column Z2 is located between the two third data signal lines 303 corresponding to the second pixel circuit column Z2, so as to place the auxiliary signal line FIAA corresponding to the second pixel circuit column Z2 and the third data signal line 303 in a centralized manner, so that the auxiliary signal line FIAA corresponding to the second pixel circuit column Z2 and the third data signal line 303 are at a similar level of parasitic capacitance between each metal film layer or signal node in the pixel circuit 10, which helps to reduce the loss difference between the data signals transmitted on the auxiliary signal line FIAA corresponding to the second pixel circuit column Z2 and the third data signal line 303, thereby facilitating to improve the display uniformity.

[0400] Further, as shown in FIG. 50, in the direction perpendicular to the plane where the display panel is located, there is no overlapping area between the auxiliary signal line FIAA corresponding to the second pixel circuit column Z2 and the third data signal line 303, which can reduce the coupling capacitance between the auxiliary signal line FIAA corresponding to the second pixel circuit column Z2 and the third data signal line 303, and further reduce the mutual interference of the data signals between the auxiliary signal line FIAA corresponding to the second pixel circuit column Z2 and the third data signal line 303.

[0401] With reference to FIGS. 51 and 52, optionally, in the third pixel circuit column group G3, along the row direction, the auxiliary signal line FIAA corresponding to the first pixel circuit column Z1 is located on the same side of the first data signal line 301 and the second data signal line 302 corresponding to the first pixel circuit column Z1, and the auxiliary signal line FIAA corresponding to the second pixel circuit column Z2 is located on the same side of the two third data signal lines 303 corresponding to the second pixel circuit column Z2. Wherein, in the direction perpendicular to the plane where the display panel is located, there is no overlapping area between the auxiliary signal line FIAA corresponding to the first pixel circuit column Z1 and the data signal line 30, which can reduce the coupling capacitance between the auxiliary signal line FIAA corresponding to the first pixel circuit column Z1 and the data signal line 30, and further reduce the mutual interference of the data signals between the auxiliary signal line FIAA corresponding to the first pixel circuit column Z1 and the data signal line 30.

[0402] Wherein, FIG. 51 exemplarily shows that the auxiliary signal line FIAA corresponding to the first pixel circuit column Z1 is located on the side of the two data signal lines 30 corresponding to the first pixel circuit column Z1 close to the second pixel circuit column Z2, and the auxiliary signal line FIAA corresponding to the second pixel circuit column Z2 is located on the side of the two third data signal lines 303 corresponding to the second pixel circuit column Z2 close to the first pixel circuit column Z1. FIG. 52 exemplarily shows that the auxiliary signal line FIAA corresponding to the first pixel circuit column Z1 is located on the side of the two data signal lines 30 corresponding to the first pixel circuit column Z1 away from the second pixel circuit column Z2, and the auxiliary signal line FIAA corresponding to the second pixel circuit column Z2 is located on the side of the two third data signal lines 303 corresponding to the second pixel circuit column Z2 away from the first pixel circuit column Z1, but is not limited thereto.

[0403] With reference to FIG. 53, optionally, in the direction perpendicular to the plane where the display panel is located, the auxiliary signal line FIAA corresponding to the first pixel circuit column Z1 and the data signal line 30 corresponding to the first pixel circuit column Z1 at least partially overlap, and the auxiliary signal line FIAA corresponding to the second pixel circuit column Z2 and the data signal line 30 corresponding to the second pixel circuit column Z2 at least partially overlap. In this way, the total shielding area of the auxiliary signal line FIAA and the data signal line 30 in the thickness direction of the display panel can be reduced, so that the light transmission area of the display panel can be increased, and the influence of the auxiliary signal line FIAA and the data signal line 30 on the display effect of the display area AA can be reduced.

[0404] Fig. 54 is a structural schematic view of another display panel provided by the embodiment of the present application. As shown in Fig. 54, optionally, the third pixel circuit column group G3 corresponds to three auxiliary signal lines FIAA. In the third pixel circuit column group G3, along the row direction, the three auxiliary signal lines FIAA are located between the first pixel circuit column Z1 and the second pixel circuit column Z2, and the auxiliary signal lines FIAA are located between two adjacent data signal lines 30.

[0405] Specifically, as shown in Fig. 54, two pixel circuit columns 10 can correspond to three auxiliary signal lines FIAA, at this time, one third pixel circuit column group G3 is provided with three auxiliary signal lines FIAA, so as to increase the number of auxiliary signal lines FIAA, and thus the setting area of the first display area AA1 can be increased, which is beneficial to realizing the narrow frame effect.

[0406] As shown in Fig. 54, in the third pixel circuit column group G3, along the row direction, the three auxiliary signal lines FIAA are located between the first pixel circuit column Z1 and the second pixel circuit column Z2, so as to place the auxiliary signal lines FIAA and the data signal lines 30 together, so that the parasitic capacitances between the auxiliary signal lines FIAA and the data signal lines 30 and the metal film layers or signal nodes in the pixel circuit 10 are at similar levels, which is helpful to reduce the loss difference between the data signals transmitted on the auxiliary signal lines FIAA and the data signal lines 30, and improve the display uniformity.

[0407] Further, as shown in Fig. 54, the three auxiliary signal lines FIAA can be located between two adjacent data signal lines 30 respectively, so that in the direction perpendicular to the plane where the display panel is located, the auxiliary signal lines FIAA can not overlap with the data signal lines 30, and the coupling capacitance between the auxiliary signal lines FIAA and the data signal lines 30 can be further reduced, and thus the mutual interference between the data signals of the auxiliary signal lines FIAA and the data signal lines 30 can be reduced.

[0408] Meanwhile, in the third pixel circuit column group G3, the three auxiliary signal lines FIAA can be uniformly distributed in the gaps between the four data signal lines 30, so as to reduce the visual interference caused by the non-uniform reflection of light by the auxiliary signal lines FIAA, and improve the overall visual effect of the display panel.

[0409] Fig. 55 is a structural schematic view of another display panel provided by the embodiment of the present application. As shown in Fig. 55, optionally, one first pixel circuit column Z1 corresponds to two auxiliary signal lines FIAA, and one second pixel circuit column Z2 corresponds to two auxiliary signal lines FIAA. In the direction perpendicular to the plane where the display panel is located, the auxiliary signal lines FIAA and the data signal lines 30 at least partially overlap.

[0410] Specifically, as shown in FIG. 55, four auxiliary signal lines FIAA can be provided for each column of pixel circuits 10, and four auxiliary signal lines FIAA are provided for each third group G3 of pixel circuit columns, so as to increase the number of auxiliary signal lines FIAA, thereby increasing the area of the first display area AA1 and facilitating the realization of a narrow frame effect.

[0411] Further, as shown in FIG. 55, the auxiliary signal lines FIAA and the data signal lines 30 at least partially overlap in a direction perpendicular to the plane of the display panel, and such an arrangement can reduce the total area of the auxiliary signal lines FIAA and the data signal lines 30 in the thickness direction of the display panel, thereby increasing the light transmission area of the display panel and reducing the impact of the auxiliary signal lines FIAA and the data signal lines 30 on the display effect of the display area AA.

[0412] With continued reference to FIG. 47, optionally, in the third group G3 of pixel circuit columns, the first data signal line 301 connected to the first pixel circuit column Z1 is located on the side of the second data signal line 302 connected to the first pixel circuit column Z1 away from the first pixel circuit column Z1, and the spacing between the auxiliary signal line FIAA and the second data signal line 302 is greater than the spacing between the auxiliary signal line FIAA and the third data signal line 303.

[0413] Alternatively,

[0414] In the third group G3 of pixel circuit columns, the second data signal line 302 connected to the first pixel circuit column Z1 is located on the side of the first data signal line 301 connected to the first pixel circuit column Z1 away from the first pixel circuit column Z1, and the spacing between the auxiliary signal line FIAA and the first data signal line 301 is greater than the spacing between the auxiliary signal line FIAA and the third data signal line 303.

[0415] Specifically, as shown in FIG. 47, one first pixel circuit column Z1 is provided with a first data signal line 301 and a second data signal line 302, and one second pixel circuit column Z2 is provided with a third data signal line 303, so that three data signal lines 30 are provided in one third group G3 of pixel circuit columns.

[0416] As shown in FIG. 47, in the present embodiment, when the first data signal line 301 connected to the first pixel circuit column Z1 is located on the side of the second data signal line 302 connected to the first pixel circuit column Z1 away from the first pixel circuit column Z1, the interval between the auxiliary signal line FIAA and the second data signal line 302 is set to be greater than the interval between the auxiliary signal line FIAA and the third data signal line 303, so that the auxiliary signal line FIAA is arranged away from the center of the third pixel circuit column group G3, at this time, the auxiliary signal line FIAA is located between the first data signal line 301 and the third data signal line 303, and the interval between the auxiliary signal line FIAA and the first data signal line 301 and the interval between the auxiliary signal line FIAA and the third data signal line 303 are more uniform, so that in the third pixel circuit column group G3, the auxiliary signal line FIAA and the data signal line 30 are more uniformly distributed, thereby reducing visual interference caused by uneven reflection of light by the auxiliary signal line FIAA and the data signal line 30, and improving the overall visual effect of the display panel.

[0417] Continuing to refer to FIG. 47, alternatively, when the second data signal line 302 connected to the first pixel circuit column Z1 is located on the side of the first data signal line 301 connected to the first pixel circuit column Z1 away from the first pixel circuit column Z1, the interval between the auxiliary signal line FIAA and the first data signal line 301 is set to be greater than the interval between the auxiliary signal line FIAA and the third data signal line 303, so that the auxiliary signal line FIAA is arranged away from the center of the third pixel circuit column group G3, at this time, the auxiliary signal line FIAA is located between the second data signal line 302 and the third data signal line 303, and the interval between the auxiliary signal line FIAA and the second data signal line 302 and the interval between the auxiliary signal line FIAA and the third data signal line 303 are more uniform, so that in the third pixel circuit column group G3, the auxiliary signal line FIAA and the data signal line 30 are more uniformly distributed, thereby reducing visual interference caused by uneven reflection of light by the auxiliary signal line FIAA and the data signal line 30, and improving the overall visual effect of the display panel.

[0418] Continuing to refer to FIG. 47, alternatively, in the third pixel circuit column group G3, the number of data signal lines 30 connected to the first pixel circuit column Z1 is greater than the number of data signal lines 30 connected to the second pixel circuit column Z2.

[0419] Specifically, as shown in FIG. 27, in the third pixel circuit column group G3, the number of data signal lines 30 connected by the second pixel circuit column Z2 is less than the number of data signal lines 30 connected by the first pixel circuit column Z1, while ensuring the display effect, the number of data signal lines 30 can be reduced, thereby providing sufficient space for the auxiliary signal line FIAA while ensuring the light transmittance, which is conducive to increasing the distance between the auxiliary signal line FIAA and the data signal line 30 and reducing the coupling capacitance between the auxiliary signal line FIAA and the data signal line 30, thereby reducing the mutual interference of the data signals between the auxiliary signal line FIAA and the data signal line 30.

[0420] With reference to FIGS. 46 and 47, optionally, the display area AA includes a first display area AA1 and a second display area AA2, and the first display area AA1 is located at least one side of the second display area AA2 along the row direction. The display panel further includes a plurality of auxiliary signal lines FIAA, which extend along the column direction and are arranged along the row direction. The auxiliary signal lines FIAA are at least partially located in the second display area AA2, and the auxiliary signal lines FIAA are electrically connected with the data signal lines 30 in the first display area AA1. In the third pixel circuit column group G3, the number of data signal lines 30 on both sides of the auxiliary signal line FIAA along the row direction is different.

[0421] The positional relationship between the first display area AA1 and the second display area AA2, the distribution and connection structure of the auxiliary signal line FIAA can refer to the above-mentioned embodiments, which will not be described here.

[0422] In this embodiment, as shown in FIGS. 46 and 47, in the third pixel circuit column group G3, the number of data signal lines 30 on both sides of the auxiliary signal line FIAA along the row direction is different, and when the number of data signal lines 30 in the third pixel circuit column group G3 is odd, the distribution of the auxiliary signal line FIAA and the data signal line 30 can be more uniform, thereby reducing the visual interference caused by the uneven reflection of light by the auxiliary signal line FIAA and the data signal line 30, and improving the overall visual effect of the display panel.

[0423] Optionally, the plurality of data signal lines 30 are located in the same film layer.

[0424] By locating all the data signal lines 30 in the same film layer, the number of film layers can be reduced, thereby facilitating the reduction of the thickness of the display panel and achieving the design of thinness.

[0425] Exemplarily, as shown in FIGS. 24-37, the data signal lines 30 can be all arranged in the fifth metal layer SD2, but are not limited thereto.

[0426] Optionally, the interval between the adjacent data signal lines 30 in the direction parallel to the plane where the display panel is located is greater than or equal to 2.5 μm, so that the signal interference between the adjacent data signal lines 30 can be avoided, and the data signal transmitted on the data signal line 30 is more accurate and stable, but the application is not limited thereto.

[0427] It should be noted that the interval between the adjacent data signal lines 30 can be set according to actual needs, and the embodiments of the application are not limited thereto. It can be understood that the greater the interval between the adjacent data signal lines 30, the smaller the signal interference between the adjacent data signal lines 30; but the smaller the interval between the adjacent data signal lines 30, the more conducive to compressing the size of the pixel circuit 10, thereby helping to improve the pixel density of the display panel.

[0428] FIG. 56 is a schematic view of a partial cross-sectional structure of another display panel according to an embodiment of the application. As shown in FIG. 56, optionally, the at least two data signal lines 30 are located in different film layers, and the data signal lines 30 located in different film layers at least partially overlap in the direction perpendicular to the plane where the display panel is located.

[0429] Specifically, as shown in FIG. 56, by setting the at least two data signal lines 30 in different film layers, the interval between the different data signal lines 30 can be increased, the coupling capacitance between the different data signal lines 30 can be reduced, and the mutual interference of the data signals between the different data signal lines 30 can be reduced.

[0430] Further, as shown in FIG. 56, the data signal lines 30 located in different film layers at least partially overlap in the direction perpendicular to the plane where the display panel is located, which can reduce the overall blocking area of the data signal lines 30 in the thickness direction of the display panel, thereby increasing the light transmission area of the display panel and reducing the influence of the data signal lines 30 on the display effect of the display area AA.

[0431] With reference to FIGS. 35 and 36, optionally, the light emitting element 20 includes a red light emitting element 20R, a blue light emitting element 20B and a green light emitting element 20G, the first pixel circuit 101 is connected to the red light emitting element 20R, the second pixel circuit 102 is connected to the blue light emitting element 20B, and the third pixel circuit 103 is connected to the green light emitting element 20G.

[0432] Specifically, as shown in FIGS. 35 and 36, the light emitting element 20 can include a red light emitting element 20R for emitting red light, a blue light emitting element 20B for emitting blue light and a green light emitting element 20G for emitting green light, so as to realize color image display, but the application is not limited thereto. In some embodiments, the light emitting element 20 can also include a white light emitting element for emitting white light, and the embodiments of the application are not limited thereto.

[0433] With reference back to FIGS. 35 and 36, in the first pixel circuit column Z1, the red light emitting elements 20R connected to the first pixel circuit 101 and the blue light emitting elements 20B connected to the second pixel circuit 102 are arranged alternately in the column direction; in the second pixel circuit column Z2, the green light emitting elements 20G connected to the third pixel circuit 103 are arranged in sequence in the column direction.

[0434] In this way, the number of green light emitting elements 20G can be increased. Since the human eye has the highest sensitivity to green, by setting the number of green light emitting elements 20G to be greater than the number of green light emitting elements 20G or the number of blue light emitting elements 20B, the high sensitivity of the human eye to green can be better met, thereby facilitating improvement of display quality.

[0435] FIG. 57 is a structural schematic diagram of another display panel provided by an embodiment of the present application. As shown in FIGS. 46 and 57, optionally, the display area AA includes a first display area AA1 and a second display area AA2, and the first display area AA1 is located at least one side of the second display area AA2 along the row direction. The display panel further includes a plurality of auxiliary signal lines FIAA, which extend along the column direction and are arranged along the row direction. The auxiliary signal lines FIAA are at least partially located in the second display area AA2, and the auxiliary signal lines FIAA are electrically connected to the data signal lines 30 in the first display area AA1. The plurality of first pixel circuit columns Z1 and the plurality of second pixel circuit columns Z2 are divided into a plurality of third pixel circuit column groups G3, and each third pixel circuit column group G3 includes a first pixel circuit column Z1 and a second pixel circuit column Z2 adjacent along the row direction.

[0436] The third pixel circuit column group G3 corresponds to one auxiliary signal line FIAA, and the second pixel circuit column Z2 corresponds to one third data signal line 303. In the third pixel circuit column group G3, the first data signal line 301 connected to the first pixel circuit column Z1 and the second data signal line 302 connected to the second pixel circuit column Z2 are located at different sides of the first pixel circuit column Z1 and the second pixel circuit column Z2, respectively. In at least one third pixel circuit column group G3 in the second display area AA2, the auxiliary signal line FIAA and the third data signal line 303 connected to the second pixel circuit column Z2 are located at different sides of the second pixel circuit column Z2, respectively.

[0437] The positional relationship between the first display area AA1 and the second display area AA2, the connection structure of the auxiliary signal line FIAA, and the structure of the first pixel circuit column Z1 and the second pixel circuit column Z2 in the third pixel circuit column group G3 can be referred to the above embodiments, which will not be described herein again.

[0438] In the embodiment, as shown in FIG. 46 and FIG. 57, one third pixel circuit column group G3 is correspondingly provided with one auxiliary signal line FIAA, and one second pixel circuit column Z2 is correspondingly connected with one third data signal line 303, so that the auxiliary signal line FIAA can be provided with sufficient setting space while the light transmittance is ensured, which is conducive to increasing the distance between the auxiliary signal line FIAA and the data signal line 30 and reducing the coupling capacitance between the auxiliary signal line FIAA and the data signal line 30, and further reducing the mutual interference of the data signals between the auxiliary signal line FIAA and the data signal line 30.

[0439] Further, as shown in FIG. 46 and FIG. 57, in the third pixel circuit column group G3, the first data signal line 301 and the second data signal line 302 connected by the first pixel circuit column Z1 are respectively located on different sides of the first pixel circuit column Z1. On the one hand, in the row direction, the first data signal line 301 and the second data signal line 302 are both spaced apart from the first pixel circuit column Z1, which can avoid the formation of parasitic capacitance between the first data signal line 301 and the second data signal line 302 and each metal film layer of the pixel circuit 10 in the first pixel circuit column Z1, so as to reduce the influence of the first data signal line 301 and the second data signal line 302 on the performance of the pixel circuit 10. On the other hand, in the row direction, the first data signal line 301 and the second data signal line 302 can have a large distance therebetween, so as to reduce the mutual interference of the data signals between the first data signal line 301 and the second data signal line 302.

[0440] Similarly, in at least one third pixel circuit column group G3, the auxiliary signal line FIAA and the third data signal line 303 connected by the second pixel circuit column Z2 are respectively located on different sides of the second pixel circuit column Z2. On the one hand, in the row direction, the auxiliary signal line FIAA and the third data signal line 303 are both spaced apart from the second pixel circuit column Z2, which can avoid the formation of parasitic capacitance between the auxiliary signal line FIAA and the third data signal line 303 and each metal film layer of the pixel circuit 10 in the second pixel circuit column Z2, so as to reduce the influence of the auxiliary signal line FIAA and the third data signal line 303 on the performance of the pixel circuit 10. On the other hand, in the row direction, the auxiliary signal line FIAA and the third data signal line 303 can have a large distance therebetween, so as to reduce the mutual interference of the data signals between the auxiliary signal line FIAA and the third data signal line 303.

[0441] FIG. 58 is a structural schematic view of another display panel according to an embodiment of the present application. As shown in FIG. 58, in the row direction, the first data signal line 301 connected with the first pixel circuit column Z1 and the second data signal line 302 connected with the second pixel circuit column Z2 are respectively located on opposite sides of the first pixel circuit column Z1. In the row direction, the two third data signal lines 303 connected with the second pixel circuit column Z2 are respectively located on opposite sides of the second pixel circuit column Z2.

[0442] Specifically, as shown in FIG. 58, the first pixel circuit column Z1 is connected with one first data signal line 301 and one second data signal line 302. In the row direction, the first data signal line 301 and the second data signal line 302 are respectively located on opposite sides of the first pixel circuit column Z1. On the one hand, in the row direction, the first data signal line 301 and the second data signal line 302 are both spaced apart from the first pixel circuit column Z1, which can avoid the formation of parasitic capacitance between the first data signal line 301 and the second data signal line 302 and each metal film layer of the pixel circuit 10 in the first pixel circuit column Z1, thereby reducing the influence of the first data signal line 301 and the second data signal line 302 on the performance of the pixel circuit 10. On the other hand, in the row direction, the first data signal line 301 and the second data signal line 302 can have a large spacing therebetween, thereby reducing the mutual interference of the data signals between the first data signal line 301 and the second data signal line 302.

[0443] Similarly, the first pixel circuit column Z1 is connected with two third data signal lines 303. In the row direction, the two third data signal lines 303 are respectively located on opposite sides of the second pixel circuit column Z2. On the one hand, in the row direction, the two third data signal lines 303 are both spaced apart from the second pixel circuit column Z2, which can avoid the formation of parasitic capacitance between the two third data signal lines 303 and each metal film layer of the pixel circuit 10 in the second pixel circuit column Z2, thereby reducing the influence of the auxiliary signal line FIAA and the third data signal line 303 on the performance of the pixel circuit 10. On the other hand, in the row direction, the two third data signal lines 303 can have a large spacing therebetween, thereby reducing the mutual interference of the data signals between the two third data signal lines 303.

[0444] For example, FIG. 59 is a structural schematic view of another pixel circuit according to an embodiment of the present application. As shown in FIG. 59, the pixel circuit 10 can include a first light-emitting control transistor T1, a data writing transistor T2, a driving transistor T3, a threshold compensation transistor T4, an initialization reset transistor T5, a second light-emitting control transistor T6, an anode reset transistor T7, and a storage capacitor Cst.

[0445] The connection relationship and functions of the first light emitting control transistor T1, the data writing transistor T2, the driving transistor T3, the threshold compensation transistor T4, the initialization reset transistor T5, the second light emitting control transistor T6, the anode reset transistor T7, and the storage capacitor Cst can refer to the above embodiments, and will not be described here again.

[0446] FIG. 60 is a signal timing diagram provided to the pixel circuit shown in FIG. 59 in a driving cycle according to an embodiment of the present application. As shown in FIG. 59 and FIG. 60, the working process of the pixel circuit 10 can include a pre-stage t10 and a light emitting stage t20. The pre-stage t10 is a stage in which the light emitting element 20 does not emit light, and the light emitting stage t20 is a stage in which the light emitting element 20 emits light. In some cases, the pre-stage t10 and the light emitting stage t20 can be performed sequentially.

[0447] The specific meanings of the pre-stage t10 and the light emitting stage t20 can refer to the above embodiments, and will not be described here again.

[0448] With reference to FIG. 59 and FIG. 60, the pre-stage t10 of the pixel circuit 10 can include a reset stage t12, optionally.

[0449] In the reset stage t12, the first scan signal S1N is a low-level effective signal, so that the initialization reset transistor T5 is turned on, and the first reference signal VREF1 is transmitted to the gate of the driving transistor T3 (i.e., the first node N1) through the turned-on initialization reset transistor T5, so as to reset the gate of the driving transistor T3. At this time, the gate potential of the driving transistor T3 is consistent with the potential of the first reference signal VREF1, so as to avoid the influence of the data signal carried on the gate of the driving transistor T3 in the last frame on the writing of the data signal in the next frame.

[0450] With reference to FIG. 59 and FIG. 60, the pre-stage t10 of the pixel circuit 10 can further include a data writing stage t13, optionally.

[0451] In the data writing stage t13, the third scan signal SP and the second scan signal S2N are both low-level effective pulses, so that the data writing transistor T2 and the threshold compensation transistor T4 are turned on. At the same time, the gate potential of the driving transistor T3 is consistent with the first reference signal VREF1, and the driving transistor T3 is also turned on. The data signal passes through the data writing transistor T2, the driving transistor T3, and the threshold compensation transistor T4, and is applied to the gate of the driving transistor T3 (i.e., the first node N1). The potential of the first node N1 is gradually pulled up until the driving transistor T3 is cut off. When the driving transistor T3 is cut off, the gate potential of the driving transistor T3 is Vdata-|Vth|, wherein Vdata is the voltage of the data signal DATA, and |Vth| is the threshold voltage of the driving transistor T3.

[0452] Continuing to refer to FIGS. 59 and 60, optionally, after the data writing stage t13, the display panel can enter a light emitting stage t20.

[0453] In the light emitting stage t20, the light emitting control signal EM is a low-level effective pulse, the first light emitting control transistor T1 and the second light emitting control transistor T6 are turned on. Due to the turn-on of the first light emitting control transistor T1, the positive power supply voltage PVDD is transmitted to the first end (i.e., the second node N2) of the driving transistor T3, and the voltage difference between the first end (i.e., the second node N2) and the gate (i.e., the first node N1) of the driving transistor T3 is PVDD-(Vdata-|Vth|), so that the driving current generated by the driving transistor T3 is K*(Vdata-PVDD)2, K is a coefficient related to the size and material of the driving transistor T3, and thus the driving current generated by the driving transistor T3 is independent of the threshold voltage |Vth| thereof. The driving current is transmitted to the anode of the light emitting element 20 through the turned-on second light emitting control transistor T6, so that the light emitting element 20 emits light.

[0454] Continuing to refer to FIGS. 59 and 60, optionally, the pre-stage t10 of the pixel circuit 10 can include an initialization stage t11.

[0455] In the initialization stage t11, the fourth scan signal SPX is a low-level effective pulse, so that the anode reset transistor T7 is turned on, and the second reference signal VREF2 is transmitted to the anode of the light emitting element 20 through the anode reset transistor T7 to initialize the anode of the light emitting element 20, so as to prevent the driving current provided to the anode of the light emitting element 20 in the last frame from affecting the display and light emitting brightness of the light emitting element 20 in the next frame.

[0456] In the pixel circuit 10, the transistors can all be low-temperature poly-silicon (LTPS) transistors. The low-temperature poly-silicon transistor has the advantages of high switching speed, high carrier mobility, and small power consumption. The oxide transistor has the advantage of small leakage current, but is not limited thereto.

[0457] Further, the fourth scan signal SPX, the second scan signal S2N, and the third scan signal SP can be the same scan signal, so as to reduce the number of scan signal lines and reduce the cost.

[0458] It can be understood that the above only exemplarily describes the types of the transistors in the pixel circuit 10 and the corresponding driving processes. In the embodiment of the present application, when the types of the transistors in the pixel circuit 10 change, the driving processes similar to the above can also be achieved by changing the signals received by the gates of the transistors, which will not be described herein again.

[0459] For example, FIG. 61 is a schematic view of a film layer structure of another display panel according to an embodiment of the present application. As shown in FIG. 61, the LTPS display panel is taken as an example for illustration. The first semiconductor layer POLY, the first metal layer GAT, the second metal layer MC, the fourth metal layer SD1, the fifth metal layer SD2, the sixth metal layer SD3 and the anode layer RE are stacked on the substrate 60. An insulating layer 70 can be arranged between any two adjacent conductive film layers to avoid short circuit between the two adjacent conductive film layers.

[0460] FIG. 62 is a schematic view of a structure of a first semiconductor layer in the display panel shown in FIG. 61; FIG. 63 is a schematic view of a structure of a first metal layer in the display panel shown in FIG. 61; FIG. 64 is a schematic view of a structure of a second metal layer in the display panel shown in FIG. 61; FIG. 65 is a schematic view of a structure of a fourth metal layer in the display panel shown in FIG. 61; FIG. 66 is a schematic view of a structure of a fifth metal layer in the display panel shown in FIG. 61; FIG. 67 is a schematic view of a structure of a sixth metal layer in the display panel shown in FIG. 61; FIG. 68 is a schematic view of a structure of an anode layer in the display panel shown in FIG. 61; FIG. 69 is a schematic view of a stack structure of all the film layers in the display panel shown in FIG. 61, specifically, a schematic view of a stack structure from the first semiconductor layer to the anode layer; FIG. 70 is a schematic view of a film layer structure of a pixel circuit in the display panel shown in FIG. 61; and FIG. 71 is a schematic view of a partial film layer structure of a pixel circuit in the display panel shown in FIG. 61, specifically, a schematic view of a stack structure from the first semiconductor layer to the fifth metal layer, for clearly showing the structure of the pixel circuit.

[0461] The film layer structure shown in FIGS. 61-71 can correspond to the pixel circuit 10 shown in FIG. 59. The first light-emitting control transistor T1, the data writing transistor T2, the driving transistor T3, the threshold compensation transistor T4, the initialization reset transistor T5, the second light-emitting control transistor T6 and the anode reset transistor T7 in the pixel circuit 10 are all low-temperature poly-silicon (LTPS) transistors.

[0462] For example, as shown in FIGS. 59-71, the active layers of the first light-emitting control transistor T1, the data writing transistor T2, the driving transistor T3, the threshold compensation transistor T4, the initialization reset transistor T5, the second light-emitting control transistor T6 and the anode reset transistor T7 can be located in the first semiconductor layer POLY.

[0463] The gate 2g of the driving transistor T3, the threshold compensation transistor T4, the initialization reset transistor T5, the second light-emitting control transistor T6 and the anode reset transistor T7, and the first plate C1 of the storage capacitor Cst can be located in the first metal layer GAT.

[0464] The first metal layer GAT can further include a first scan signal line s1n, a third scan signal line sp, a fourth scan signal line spx, a second scan signal line s2n and a light-emitting control signal line em extending in the row direction. The first scan signal line s1n is electrically connected with the gate of the initialization reset transistor T5 and is used for transmitting the first scan signal S1N; the third scan signal line sp is electrically connected with the gate of the data write transistor T2 and is used for transmitting the third scan signal SP; the fourth scan signal line spx is electrically connected with the gate of the anode reset transistor T7 and is used for transmitting the fourth scan signal SPX; the second scan signal line s2n is electrically connected with the gate of the threshold compensation transistor T4 and is used for transmitting the second scan signal S2N; and the light-emitting control signal line em is electrically connected with the gate of the first light-emitting control transistor T1 and the gate of the second light-emitting control transistor T6 and is used for transmitting the light-emitting control signal EM.

[0465] Further, the third scan signal line sp, the fourth scan signal line spx and the second scan signal line s2n can be the same scan signal line, so that the number of scan signal lines can be reduced, which is conducive to improving the light transmission area of the display panel.

[0466] The second metal layer MC can include the second plate C2 of the storage capacitor Cst, and a first reference signal line vref1 and a second reference signal line vref2 extending in the row direction. The first reference signal line vref1 is electrically connected with the initialization reset transistor T5 and is used for transmitting the first reference signal VREF1; and the second reference signal line vref2 is electrically connected with the anode reset transistor T7 and is used for transmitting the second reference signal VREF2.

[0467] The fourth metal layer SD1 can include a third power signal line P3 extending in the column direction, wherein the third power signal line P3 is used for transmitting the positive power voltage PVDD.

[0468] The fifth metal layer SD2 can include a data signal line 30 extending in the column direction, wherein the data signal line 30 is used for transmitting the data signal DATA.

[0469] The sixth metal layer SD3 can include a first power signal line P1 extending in the row direction, wherein the first power signal line P1 extending in the row direction is electrically connected with the third power signal line P3 extending in the column direction in the fourth metal layer SD1, and can constitute a grid wiring structure, which is conducive to reducing the line resistance, and further can reduce the voltage drop of the positive power voltage PVDD, so as to ensure the stability of the positive power voltage PVDD.

[0470] The anode layer RE can include an anode 111 of the light emitting element.

[0471] It should be noted that the specific film layer arrangement of the display panel can be adaptively adjusted according to actual needs, such as adding or removing part of the film layer, and the embodiments of the present application do not specifically limit this.

[0472] Further, as shown in FIGS. 62-71, the first data signal line 301 connected with the first pixel circuit column Z1 and the second data signal line 302 connected with the second pixel circuit column Z2 are respectively located on opposite sides of the first pixel circuit column Z1, and the two third data signal lines 303 connected with the second pixel circuit column Z2 are respectively located on opposite sides of the second pixel circuit column Z2. On the one hand, in the row direction, the data signal line 30 has a certain spacing with the pixel circuit 10, which can avoid the formation of parasitic capacitance between the data signal line 30 and each metal film layer of the pixel circuit 10, thereby reducing the influence of the data signal line 30 on the performance of the pixel circuit 10. On the other hand, in the row direction, the adjacent data signal lines 30 can have a large spacing, thereby reducing the mutual interference of the data signals between the adjacent data signal lines 30.

[0473] FIG. 72 is a schematic diagram of a film layer structure of a pixel circuit according to an embodiment of the present application, and FIG. 73 is a schematic diagram of another film layer structure of a pixel circuit according to an embodiment of the present application. As shown in FIGS. 46, 72 and 73, optionally, the display area AA includes a first display area AA1 and a second display area AA2, and the first display area AA1 is located on at least one side of the second display area AA2 in the row direction. The display panel further includes a plurality of auxiliary signal lines FIAA, which extend in the column direction and are arranged in the row direction. The auxiliary signal lines FIAA are at least partially located in the second display area AA2, and the auxiliary signal lines FIAA are electrically connected with the data signal lines 30 in the first display area AA1.

[0474] The auxiliary signal lines FIAA and the data signal lines 30 are located in different film layers.

[0475] Alternatively,

[0476] The auxiliary signal lines FIAA and the data signal lines 30 are located in the same film layer.

[0477] The positional relationship between the first display area AA1 and the second display area AA2, the distribution and connection structure of the auxiliary signal lines FIAA can refer to the above embodiments, which will not be described here again.

[0478] Further, as shown in FIG. 72, the auxiliary signal line FIAA and the data signal line 30 can be located in the same film layer, so that the number of film layers can be reduced, thereby facilitating the reduction of the thickness of the display panel and the realization of the thin and light design.

[0479] For example, as shown in FIG. 72, the auxiliary signal line FIAA and the data signal line 30 can be located in the sixth metal layer SD3, but are not limited thereto.

[0480] Continuing to refer to FIG. 73, alternatively, the auxiliary signal line FIAA and the data signal line 30 can be located in different film layers, so that the distance between the auxiliary signal line FIAA and the data signal line 30 can be increased, the coupling capacitance between the auxiliary signal line FIAA and the data signal line 30 can be reduced, and the mutual interference of the data signals between the auxiliary signal line FIAA and the data signal line 30 can be reduced.

[0481] For example, as shown in FIG. 73, the data signal line 30 can be located in the sixth metal layer SD3, and the auxiliary signal line FIAA can be located in the fifth metal layer SD2, but are not limited thereto.

[0482] Continuing to refer to FIG. 72, alternatively, the display panel provided by the embodiment of the present application further includes a plurality of third power signal lines P3, which extend along the column direction and are arranged along the row direction. One column of first pixel circuit columns Z1 corresponds to one auxiliary signal line FIAA and one third power signal line P3, and the auxiliary signal line FIAA and the third power signal line P3 are located between the first data signal line 301 and the second data signal line 302 connected by the first pixel circuit column Z1. One column of second pixel circuit columns Z2 corresponds to one auxiliary signal line FIAA and one third power signal line P3, and the auxiliary signal line FIAA and the third power signal line P3 are located between the two third data signal lines 303 connected by the second pixel circuit column Z2.

[0483] Specifically, as shown in FIG. 72, the third power signal lines P3 extend along the column direction and are arranged along the row direction, and are used to transmit a positive power voltage PVDD having a fixed voltage.

[0484] In the embodiment, as shown in FIG. 72, the first data signal line 301 and the second data signal line 302 connected by the first pixel circuit column Z1 have a large distance, so that sufficient setting space can be provided for the auxiliary signal line FIAA.

[0485] In the embodiment, as shown in FIG. 72, the first data signal line 301 and the second data signal line 302 connected by the first pixel circuit column Z1 have a large distance, so that sufficient setting space can be provided for the auxiliary signal line FIAA.

[0486] In the embodiment, the auxiliary signal line FIAA is arranged between the first data signal line 301 and the second data signal line 302 connected by the first pixel circuit column Z1, so as to increase the distance between the auxiliary signal line FIAA and the data signal line 30, reduce the coupling capacitance between the auxiliary signal line FIAA and the data signal line 30, and further reduce the mutual interference of the data signals between the auxiliary signal line FIAA and the data signal line 30.

[0487] Meanwhile, the third power signal line P3 is also arranged between the first data signal line 301 and the second data signal line 302 connected by the first pixel circuit column Z1, the third power signal line P3 can provide a fixed positive power voltage PVDD, so as to serve as a shielding layer to reduce the mutual interference of the data signals between the first data signal line 301 and the second data signal line 302 connected by the first pixel circuit column Z1.

[0488] Continuing to refer to FIG. 72, optionally, one column of the second pixel circuit column Z2 corresponds to one auxiliary signal line FIAA and one third power signal line P3, so as to increase the number of auxiliary signal lines FIAA, and thus increase the setting area of the first display area AA1, which is beneficial to realize the narrow frame effect.

[0489] In the embodiment, the auxiliary signal line FIAA is arranged between the two third data signal lines 303 connected by the second pixel circuit column Z2, so as to increase the distance between the auxiliary signal line FIAA and the third data signal line 303, reduce the coupling capacitance between the auxiliary signal line FIAA and the third data signal line 303, and further reduce the mutual interference of the data signals between the auxiliary signal line FIAA and the third data signal line 303.

[0490] Meanwhile, the third power signal line P3 is also arranged between the two third data signal lines 303 connected by the second pixel circuit column Z2, the third power signal line P3 can provide a fixed positive power voltage PVDD, so as to serve as a shielding layer to reduce the mutual interference of the data signals between the two third data signal lines 303 connected by the second pixel circuit column Z2.

[0491] FIG. 74 is a structural schematic diagram of another display panel provided by the embodiment of the present application, as shown in FIG. 74, optionally, one column of the first pixel circuit column Z1 corresponds to one auxiliary signal line FIAA, and one column of the second pixel circuit column Z2 corresponds to one auxiliary signal line FIAA. The auxiliary signal line FIAA is located between the two data signal lines 30 between the first pixel circuit column Z1 and the second pixel circuit column Z2 arranged adjacently.

[0492] Specifically, as shown in FIG. 74, one column of first pixel circuit columns Z1 corresponds to one auxiliary signal line FIAA, and one column of second pixel circuit columns Z2 corresponds to one auxiliary signal line FIAA, so as to increase the number of auxiliary signal lines FIAA, and thus the setting area of the first display area AA1 can be increased, which is beneficial to realize the narrow frame effect.

[0493] Further, as shown in FIG. 74, the auxiliary signal line FIAA is located between the two data signal lines 30 between the first pixel circuit column Z1 and the second pixel circuit column Z2 arranged adjacent to each other, so that the auxiliary signal line FIAA and the data signal line 30 can be placed in a concentrated manner, so that the parasitic capacitance between the auxiliary signal line FIAA and the data signal line 30 and each metal film layer or signal node in the pixel circuit 10 is at a similar level, which is helpful to reduce the loss difference between the data signals transmitted on the auxiliary signal line FIAA and the data signal line 30, and improve the display uniformity.

[0494] FIG. 75 is a structural schematic diagram of another display panel provided by an embodiment of the present application. As shown in FIG. 75, alternatively, the plurality of first pixel circuit columns Z1 and the plurality of second pixel circuit columns Z2 are divided into a plurality of third pixel circuit column groups G3, the third pixel circuit column group G3 includes the first pixel circuit column Z1 and the second pixel circuit column Z2 adjacent along the row direction, and the third pixel circuit column group G3 corresponds to three auxiliary signal lines FIAA, and the auxiliary signal line FIAA is located between any two adjacent data signal lines 30.

[0495] The structure of the first pixel circuit column Z1 and the second pixel circuit column Z2 in the third pixel circuit column group G3 can refer to the above-mentioned embodiments, which will not be described here again.

[0496] Specifically, as shown in FIG. 75, two columns of pixel circuits 10 can correspond to three auxiliary signal lines FIAA, at this time, one third pixel circuit column group G3 corresponds to three auxiliary signal lines FIAA, so as to increase the number of auxiliary signal lines FIAA, and thus the setting area of the first display area AA1 can be increased, which is beneficial to realize the narrow frame effect.

[0497] Further, as shown in FIG. 75, four data signal lines 30 are correspondingly arranged in the third pixel circuit column group G3, along the row direction, the three auxiliary signal lines FIAA are respectively located between the two adjacent data signal lines 30, then in the direction perpendicular to the plane where the display panel is located, the auxiliary signal line FIAA can not overlap with the data signal line 30, which can further reduce the coupling capacitance between the auxiliary signal line FIAA and the data signal line 30, and thus the mutual interference of the data signals between the auxiliary signal line FIAA and the data signal line 30 can be reduced.

[0498] Meanwhile, in the third pixel circuit column group G3, the three auxiliary signal lines FIAA can be evenly distributed in the gaps between the four data signal lines 30, so that visual interference caused by uneven reflection of light by the auxiliary signal lines FIAA can be reduced, and the overall visual effect of the display panel can be improved.

[0499] FIG. 76 is a schematic diagram of a film layer structure of another pixel circuit provided in an embodiment of the present application. As shown in FIG. 76, one column of first pixel circuit columns Z1 can correspond to one or two auxiliary signal lines FIAA, and one column of second pixel circuit columns Z2 can correspond to one or two auxiliary signal lines FIAA. In the direction perpendicular to the plane in which the display panel lies, the auxiliary signal lines FIAA and the data signal lines 30 at least partially overlap.

[0500] Specifically, as shown in FIG. 76, one column of first pixel circuit columns Z1 can correspond to one or two auxiliary signal lines FIAA, and one column of second pixel circuit columns Z2 can correspond to one or two auxiliary signal lines FIAA, which is conducive to achieving a narrow frame effect.

[0501] Continuing to refer to FIG. 76, the auxiliary signal lines FIAA and the data signal lines 30 are located in different film layers, and in the direction perpendicular to the plane in which the display panel lies, the auxiliary signal lines FIAA and the data signal lines 30 at least partially overlap. In this way, the overall blocking area of the auxiliary signal lines FIAA and the data signal lines 30 in the thickness direction of the display panel can be reduced, so that the light transmission area of the display panel can be increased.

[0502] It should be noted that FIG. 76 only takes one column of first pixel circuit columns Z1 corresponding to two auxiliary signal lines FIAA and one column of second pixel circuit columns Z2 corresponding to two auxiliary signal lines FIAA as an example for illustration, but is not limited thereto.

[0503] In addition, FIG. 76 takes the auxiliary signal lines FIAA and the data signal lines 30 as an example for illustration, but is not limited thereto.

[0504] Continuing to refer to FIG. 46 and FIG. 76, the display area AA can include a first display area AA1 and a second display area AA2, and the first display area AA1 can be located on at least one side of the second display area AA2 in the row direction. The display panel further includes a plurality of auxiliary signal lines FIAA, which extend in the column direction and are arranged in the row direction. The auxiliary signal lines FIAA are at least partially located in the second display area AA2, and the auxiliary signal lines FIAA are electrically connected with the data signal lines 30 in the first display area AA1.

[0505] One column of first pixel circuit columns Z1 can correspond to at least two auxiliary signal lines FIAA, and one column of second pixel circuit columns Z2 can correspond to at least two auxiliary signal lines FIAA.

[0506] The positional relationship between the first display area AA1 and the second display area AA2 and the connection structure of the auxiliary signal line FIAA can refer to the above-mentioned embodiments, which will not be described herein again.

[0507] In this embodiment, as shown in FIG. 46 and FIG. 76, one column of first pixel circuit columns Z1 corresponds to at least two auxiliary signal lines FIAA, and one column of second pixel circuit columns Z2 corresponds to at least two auxiliary signal lines FIAA, so as to increase the number of auxiliary signal lines FIAA, thereby increasing the setting area of the first display area AA1 and facilitating the realization of a narrow frame effect.

[0508] It should be noted that, in FIG. 76, only one column of first pixel circuit columns Z1 corresponds to two auxiliary signal lines FIAA, and one column of second pixel circuit columns Z2 corresponds to two auxiliary signal lines FIAA, but this is not limited thereto.

[0509] In other embodiments, one column of first pixel circuit columns Z1 can also correspond to more auxiliary signal lines FIAA, and one column of second pixel circuit columns Z2 can also correspond to more auxiliary signal lines FIAA, which are not limited in the embodiments of the present application.

[0510] Optionally, the number of auxiliary signal lines FIAA corresponding to one column of first pixel circuit columns Z1 is less than or equal to 4, and the number of auxiliary signal lines FIAA corresponding to one column of second pixel circuit columns Z2 is less than or equal to 4.

[0511] As known from the above-mentioned embodiments, the number of auxiliary signal lines FIAA corresponding to one column of first pixel circuit columns Z1 can be one, two, three or four, and the number of auxiliary signal lines FIAA corresponding to one column of second pixel circuit columns Z2 can be one, two, three or four, so as to realize a narrow frame effect while avoiding too many auxiliary signal lines FIAA, thereby effectively controlling the mutual interference between the auxiliary signal lines FIAA and the data signal lines 30, and also helping to ensure that the display panel has sufficient light transmission area.

[0512] FIG. 77 is a structural schematic diagram of another display panel provided by the embodiments of the present application. As shown in FIG. 77, optionally, the display panel provided by the embodiments of the present application further includes a plurality of third power signal lines P3, which extend along the column direction and are arranged along the row direction. One column of first pixel circuit columns Z1 corresponds to one third power signal line P3, and one column of second pixel circuit columns Z2 corresponds to one third power signal line P3. Along the row direction, the third power signal line P3 is located between the two data signal lines 30 between the first pixel circuit column Z1 and the second pixel circuit column Z2 arranged adjacently.

[0513] Specifically, as shown in FIG. 77, the third power signal line P3 extends in the column direction and is arranged in the row direction, and is used to transmit a positive power voltage PVDD having a fixed voltage.

[0514] In this embodiment, as shown in FIG. 77, the third power signal line P3 is arranged between the two data signal lines 30 between the adjacent first pixel circuit column Z1 and the second pixel circuit column Z2, and the third power signal line P3 can provide a fixed positive power voltage PVDD, thereby serving as a shielding layer to reduce signal interference between the data signal line 30 connected to the first pixel circuit column Z1 and the data signal line 30 connected to the second pixel circuit column Z2.

[0515] With reference to FIGS. 69-71, the third power signal line P3 and the data signal line 30 are located in different film layers in a direction perpendicular to the plane of the display panel, and the third power signal line P3 at least partially overlaps the two data signal lines 30 between the adjacent first pixel circuit column Z1 and the second pixel circuit column Z2.

[0516] Specifically, as shown in FIGS. 69-71, by arranging the third power signal line P3 and the data signal line 30 in different film layers, the arrangement space of the third power signal line P3 is increased, so that the arrangement area of the third power signal line P3 can be increased, which is conducive to reducing the line resistance, thereby reducing the signal voltage drop on the third power signal line P3, and ensuring the stability of the positive power voltage PVDD.

[0517] For example, as shown in FIGS. 69-71, the data signal line 30 can be located in the fifth metal layer SD2, and the third power signal line P3 can be located in the fourth metal layer SD1, but is not limited thereto.

[0518] Further, as shown in FIGS. 69-71, in a direction perpendicular to the plane of the display panel, the third power signal line P3 at least partially overlaps the two data signal lines 30 between the adjacent first pixel circuit column Z1 and the second pixel circuit column Z2, and the third power signal line P3 can provide a fixed positive power voltage PVDD, thereby serving as a shielding layer to reduce signal interference between the data signal line 30 connected to the first pixel circuit column Z1 and the data signal line 30 connected to the second pixel circuit column Z2, and also reduce signal interference between the data signal line 30 and other film layers.

[0519] Fig. 78 is a schematic view of a film structure of another pixel circuit according to an embodiment of the present application. As shown in Fig. 46 and Fig. 78, the display area AA includes a first display area AA1 and a second display area AA2, and the first display area AA1 is located at least one side of the second display area AA2 along the row direction. The display panel further includes a plurality of auxiliary signal lines FIAA extending along the column direction and arranged along the row direction. The auxiliary signal lines FIAA are located at least partially in the second display area AA2, and the auxiliary signal lines FIAA are electrically connected with the data signal lines 30 in the first display area AA1.

[0520] The auxiliary signal lines FIAA and the third power signal lines P3 are located in different film layers.

[0521] The auxiliary signal lines FIAA and the third power signal lines P3 at least partially overlap in the direction perpendicular to the plane of the display panel.

[0522] The positional relationship between the first display area AA1 and the second display area AA2 and the connection structure of the auxiliary signal lines FIAA can refer to the above embodiments, which will not be described here.

[0523] In the embodiment, as shown in Fig. 46 and Fig. 78, by setting the third power signal lines P3 and the auxiliary signal lines FIAA in different film layers, the setting space of the third power signal lines P3 is increased, so that the setting area of the third power signal lines P3 can be increased, the line resistance is reduced, and the signal voltage drop on the third power signal lines P3 is reduced, so that the stability of the positive power voltage PVDD is ensured.

[0524] Further, as shown in Fig. 46 and Fig. 78, the auxiliary signal lines FIAA and the third power signal lines P3 at least partially overlap in the direction perpendicular to the plane of the display panel, and the third power signal lines P3 can provide a fixed positive power voltage PVDD, so as to act as a shielding layer to reduce the signal interference between the auxiliary signal lines FIAA and other film layers.

[0525] With reference to Fig. 69-71, the light emitting elements 20 include red light emitting elements 20R, blue light emitting elements 20B and green light emitting elements 20G, and the red light emitting elements 20R, the green light emitting elements 20G and the blue light emitting elements 20B at least partially overlap with the third power signal lines P3 between the first pixel circuit column Z1 and the second pixel circuit column Z2 arranged adjacently in the direction perpendicular to the plane of the display panel.

[0526] Specifically, the inventors have found that, in the direction perpendicular to the plane where the display panel is located, the existence of the trace with small line width under the light emitting element 20 causes the anode 111 located above the trace to protrude upward, which affects the flatness of the anode 111, and further causes the light emitting layer 112 above the anode 111 to be uneven, thereby causing the brightness of the light emitting layer 112 to be different when the display panel is viewed at the same inclination angle in different directions, resulting in inconsistent color cast in different directions at the same inclination angle, i.e., the problem of inconsistent four-direction color cast, which affects the display effect of the display panel.

[0527] In the present embodiment, since the third power signal line P3 generally has a large line width, the red light emitting element 20R, the green light emitting element 20G and the blue light emitting element 20B are arranged to at least partially overlap with the third power signal line P3 between the first pixel circuit column Z1 and the second pixel circuit column Z2 arranged adjacently, which is beneficial to improve the flatness of the anode 111, and further reduces the brightness difference of the organic light emitting layer when the display panel is viewed at the same inclination angle in different directions, reduces the color cast difference in different directions at the same inclination angle, improves the problem of inconsistent four-direction color cast, and improves the display effect of the display panel.

[0528] With reference to FIGS. 69-71, optionally, the light emitting element 20 includes a red light emitting element 20R, a blue light emitting element 20B and a green light emitting element 20G. In the direction perpendicular to the plane where the display panel is located, the red light emitting element 20R, the green light emitting element 20G and the blue light emitting element 20B at least partially overlap with the data signal line 30 between the first pixel circuit column Z1 and the second pixel circuit column Z2 arranged adjacently.

[0529] Specifically, as shown in FIGS. 69-71, in the direction perpendicular to the plane where the display panel is located, the red light emitting element 20R, the green light emitting element 20G and the blue light emitting element 20B at least partially overlap with the data signal line 30 between the first pixel circuit column Z1 and the second pixel circuit column Z2 arranged adjacently, which can reduce the overall shielding area of the data signal line 30 and the light emitting element 20 in the thickness direction of the display panel, thereby being beneficial to improve the light transmission area of the display panel.

[0530] With reference to FIGS. 59-71, optionally, the pixel circuit 10 further includes a driving transistor T3, a threshold compensation transistor T4 and a shielding layer 80, and the gate of the driving transistor T3 and the threshold compensation transistor T4 are connected to the first node N1. In the direction parallel to the plane where the display panel is located, at least part of the shielding layer 80 is located between the first node N1 and the data signal line 30.

[0531] The connection structure and function of the driving transistor T3 and the threshold compensation transistor T4 can refer to the above embodiment, and the embodiment of the application does not make a specific limitation on this.

[0532] It can be understood that the potential of the gate of the driving transistor T3 (i.e., the first node N1) determines the size of the driving current formed by the conduction of the driving transistor T3, and the size of the driving current can determine the luminance of the light emitting element 20. Therefore, the accuracy and stability of the potential of the first node N1 are crucial to the display effect of the display panel.

[0533] In the embodiment, the shielding layer 80 is arranged between the first node N1 and the data signal line 30 in the direction parallel to the plane where the display panel is located, so as to reduce the signal interference between the first node N1 and the data signal line 30 through the shielding layer 80, improve the accuracy and stability of the potential of the first node N1, and further improve the display effect of the display panel.

[0534] The shape of the shielding layer 80 can be set according to actual needs, and the embodiment of the application does not make a specific limitation on this.

[0535] Continuing to refer to FIGS. 59-71, optionally, in the direction perpendicular to the plane where the display panel is located, the shielding layer 80 is located between the active layer of the driving transistor T3 and the data signal line 30, and the shielding layer 80 and the data signal line 30 at least partially overlap.

[0536] Specifically, as shown in FIGS. 59-71, in the direction perpendicular to the plane where the display panel is located, by arranging the shielding layer 80 between the active layer of the driving transistor T3 and the data signal line 30, and the shielding layer 80 and the data signal line 30 at least partially overlap, the shielding layer 80 can shield in the direction perpendicular to the plane where the display panel is located, thereby further reducing the signal interference between the first node N1 and the data signal line 30, improving the accuracy and stability of the potential of the first node N1, and further improving the display effect of the display panel.

[0537] As shown in FIGS. 59-71, the shielding layer 80 can be arranged in the second metal layer MC, but is not limited to this.

[0538] Optionally, a fixed voltage is applied to the shielding layer 80.

[0539] By applying a fixed voltage to the shielding layer 80, the voltage on the shielding layer 80 is a constant voltage, which can reduce the influence of the shielding layer 80 on the pixel circuit 10.

[0540] Meanwhile, the shielding layer 80 can shield the signal lines and signal nodes having the overlapping area with the shielding layer 80, thereby reducing the mutual interference between the signal lines and signal nodes in the pixel circuit 10 and improving the driving performance of the pixel circuit 10.

[0541] With reference back to FIGS. 59-71 and 78, optionally, the display panel provided by the embodiment of the present application further includes a plurality of third power signal lines P3, the plurality of third power signal lines P3 extend along the second direction Y and are arranged along the first direction X, the first direction X intersects the second direction Y, and the shielding layer 80 and the third power signal lines P3 are electrically connected.

[0542] In this embodiment, the third power signal lines P3 are used to provide a positive power voltage PVDD for the pixel circuit 10, and the positive power voltage PVDD is a direct current signal rather than an alternating current (AC) signal.

[0543] In this embodiment, the shielding layer 80 and the third power signal lines P3 are electrically connected, and the shielding layer 80 can be provided with a constant voltage through the third power signal lines P3, thereby reducing the number of signal lines and improving the light transmittance of the display panel.

[0544] Meanwhile, after the third power signal lines P3 are electrically connected with the shielding layer 80, the line area of the third power signal lines P3 is increased, thereby reducing the resistance of the third power signal lines P3 and the IR drop of the third power signal lines P3, and improving the display uniformity.

[0545] It should be noted that the third power signal lines P3 and the shielding layer 80 can be connected in the display area AA, or can be connected in the non-display area NAA, or can be electrically connected through other lines, and the embodiment of the present application does not make a specific limitation on the electrical connection mode.

[0546] FIG. 79 is a schematic view of a partial layer stack structure of the display panel shown in FIG. 24, specifically, a schematic view of a layer stack structure from the fifth metal layer to the anode layer; FIG. 80 is a schematic view of a partial layer stack structure of the display panel shown in FIG. 61, specifically, a schematic view of a layer stack structure from the fourth metal layer to the anode layer; as shown in FIGS. 24-36, 61-70, 79 and 80, optionally, the display panel provided by the embodiments of the present application further includes a plurality of first power signal lines P1, the plurality of first power signal lines P1 extend along a first direction X and are arranged along a second direction Y, the first direction X intersects the second direction Y. The plurality of first power signal lines P1 includes a first power voltage signal line P11, a second power voltage signal line P12 and a third power voltage signal line P13. The first power voltage signal line P11 is connected to the first pixel circuit 101, the second power voltage signal line P12 is connected to the second pixel circuit 102, and the third power voltage signal line P13 is connected to the third pixel circuit 103. The first power voltage signal line P11 is used to transmit a first power voltage, the second power voltage signal line P12 is used to transmit a second power voltage, and the third power voltage signal line P13 is used to transmit a third power voltage. At least two of the first power voltage, the second power voltage and the third power voltage are different.

[0547] Specifically, as shown in FIG. 4, 24-36, 59, 61-70, 79 and 80, the first power signal line P1 is used to provide a positive power voltage PVDD to the pixel circuit 10, wherein the driving transistor T3 and the light emitting element 20 in the pixel circuit 10 are connected in series between the first power signal line P1 and the second power signal line P2, the first power signal line P1 transmits the positive power voltage PVDD, the second power signal line P2 is used to transmit a negative power voltage PVEE, and the positive power voltage PVDD can be greater than the negative power voltage PVEE, wherein a driving current is generated through the potential difference between the first power signal line P1 and the second power signal line P2, thereby driving the light emitting element 20 to emit light.

[0548] The inventors have found that different materials of the light emitting layer 112 in the light emitting elements 20 emitting different colors of light result in different pixel capacitances of the light emitting elements 20 emitting different colors of light. In the light emitting stage, the anode 111 and the cathode 113 of the light emitting element 20 are connected, and the pixel capacitance of the light emitting element 20 is charged first. At this time, the anode potential of the light emitting element 20 gradually rises. When the pixel capacitance of the light emitting element 20 is fully charged, the cross voltage of the light emitting element 20 reaches the turn-on voltage, and the light emitting element 20 starts to emit light continuously. The smaller the pixel capacitance of the light emitting element 20, the smaller the voltage difference between the anode and the cathode when the pixel capacitance is fully charged, and the smaller the turn-on voltage. Similarly, the larger the pixel capacitance of the light emitting element 20, the larger the voltage difference between the anode and the cathode when the pixel capacitance is fully charged, and the larger the turn-on voltage. It can be understood that the turn-on voltage is the cross voltage when the pixel capacitance is fully charged, and the light emitting element 20 starts to emit light when the cross voltage reaches the turn-on voltage.

[0549] In order to ensure that all driving transistors T3 in all color sub-pixels can work in the saturation region, that is, to ensure that all sub-pixels can reach a sufficient power supply voltage to drive the sub-pixels to reach their maximum brightness, the voltage difference between the positive power supply voltage PVDD and the negative power supply voltage PVEE needs to be able to reach the cross voltage requirement of the light emitting element 20 with the largest turn-on voltage in all color sub-pixels. Therefore, for sub-pixels with a smaller turn-on voltage of the light emitting element 20, there is redundancy in the voltage value of the positive power supply voltage PVDD.

[0550] The power consumption power2 of the sub-pixel can satisfy the following formula: power2=(PVDD-PVEE)×I.

[0551] Wherein, I is the size of the driving current.

[0552] As can be seen from the above formula, the larger the voltage difference between the positive power supply voltage PVDD and the negative power supply voltage PVEE, the higher the power consumption of the sub-pixel. Therefore, when there is redundancy in the voltage value of the positive power supply voltage PVDD, there is unnecessary power loss, thereby increasing the power consumption of the display panel.

[0553] Based on the above technical problems, in the present embodiment, as shown in FIGS. 4, 24-36, 59, 61-70, 79 and 80, a plurality of first power supply signal lines P1 are divided into a first power supply voltage signal line P11, a second power supply voltage signal line P12 and a third power supply voltage signal line P13, wherein the first power supply voltage signal line P11 is connected to the first pixel circuit 101, the second power supply voltage signal line P12 is connected to the second pixel circuit 102, and the third power supply voltage signal line P13 is connected to the third pixel circuit 103, so as to separate the first power supply signal lines P1 connected to different color sub-pixels.

[0554] The first power voltage signal line P11 is used to transmit the first power voltage to the first pixel circuit 101, the second power voltage signal line P12 is used to transmit the second power voltage to the second pixel circuit 102, and the third power voltage signal line P13 is used to transmit the third power voltage to the third pixel circuit 103. At least two of the first power voltage, the second power voltage and the third power voltage are different, so that the voltage amplitude of the positive power voltage PVDD received by the sub-pixels of different colors can be independently set according to the difference in the cross-voltage requirement of the light emitting element 20 in the sub-pixels of different colors, so that the positive power voltage PVDD received by the sub-pixels of different colors is closer to the cross-voltage requirement of the light emitting element 20, thereby reducing the voltage redundancy of the positive power voltage PVDD and reducing the power consumption of the display panel.

[0555] With reference to FIGS. 24-36, 61-70, 79 and 80, the light emitting element 20 can include a red light emitting element 20R, a blue light emitting element 20B and a green light emitting element 20G, which are used to realize color image display, but are not limited thereto. In some embodiments, the light emitting element 20 can also include a white light emitting element, which is not limited in the embodiments of the present application.

[0556] The second power voltage VB is greater than the third power voltage VG, and the third power voltage VG is greater than or equal to the first power voltage VR.

[0557] Alternatively,

[0558] The second power voltage VB is greater than the first power voltage VR, and the first power voltage VR is greater than or equal to the third power voltage VG.

[0559] As shown in FIGS. 24-36, 61-70, 79 and 80, the light emitting element 20 can include a red light emitting element 20R, a blue light emitting element 20B and a green light emitting element 20G, which are used to realize color image display, but are not limited thereto. In some embodiments, the light emitting element 20 can also include a white light emitting element, which is not limited in the embodiments of the present application.

[0560] In the present embodiment, the first pixel circuit 101 is connected to the red light emitting element 20R, and the first pixel circuit 101 and the red light emitting element 20R constitute a red sub-pixel. The positive power voltage PVDD of the red sub-pixel is provided by the first power voltage signal line P11, and the positive power voltage PVDD is the first power voltage VR.

[0561] The second pixel circuit 102 is connected with the blue light emitting element 20B, and the second pixel circuit 102 and the blue light emitting element 20B constitute a blue sub-pixel. A positive power supply voltage PVDD of the blue sub-pixel is provided by the second power supply voltage signal line P12, and the positive power supply voltage PVDD is the second power supply voltage VB.

[0562] The third pixel circuit 103 is connected with the green light emitting element 20G, and the third pixel circuit 103 and the green light emitting element 20G constitute a green sub-pixel. A positive power supply voltage PVDD of the green sub-pixel is provided by the third power supply voltage signal line P13, and the positive power supply voltage PVDD is the third power supply voltage VG.

[0563] The inventors further found that, due to the different materials of the light emitting layer 112 in the red sub-pixel 20R, the blue light emitting element 20B and the green light emitting element 20G, there is a difference in the turn-on voltage of the red sub-pixel 20R, the blue light emitting element 20B and the green light emitting element 20G, and the cross voltage requirements of the red sub-pixel 20R, the blue light emitting element 20B and the green light emitting element 20G are different.

[0564] In some embodiments, the cross voltage requirement value of the blue light emitting element 20B is the largest, the cross voltage requirement value of the red sub-pixel 20R is the smallest, and the cross voltage requirement value of the green light emitting element 20G is between the cross voltage requirement value of the blue light emitting element 20B and the cross voltage requirement value of the red sub-pixel 20R. At this time, the second power supply voltage VB can be greater than the third power supply voltage VG, and the third power supply voltage VG is greater than or equal to the first power supply voltage VR, that is, VB> VG≥ VR. While ensuring the cross voltage requirements of the red sub-pixel 20R, the blue light emitting element 20B and the green light emitting element 20G for normal operation, the voltage redundancy of the positive power supply voltage PVDD can be reduced, and the power consumption of the display panel is further reduced.

[0565] In some other embodiments, the cross voltage requirement value of the blue light emitting element 20B is the largest, the cross voltage requirement value of the green light emitting element 20G is the smallest, and the cross voltage requirement value of the red sub-pixel 20R is between the cross voltage requirement value of the blue light emitting element 20B and the cross voltage requirement value of the green light emitting element 20G. At this time, the second power supply voltage VB can be greater than the first power supply voltage VR, and the first power supply voltage VR is greater than or equal to the third power supply voltage VG, that is, VB> VR≥ VG. While ensuring the cross voltage requirements of the red sub-pixel 20R, the blue light emitting element 20B and the green light emitting element 20G for normal operation, the voltage redundancy of the positive power supply voltage PVDD can be reduced, and the power consumption of the display panel is further reduced.

[0566] It should be noted that the magnitude relationship of the second power supply voltage VB, the third power supply voltage VG and the first power supply voltage VR can be adjusted according to the actual display panel structure and requirements, and is not limited to the above embodiment, and the embodiment of the present application does not make specific limitation thereto.

[0567] With reference to FIGS. 24-36, 61-70, 79 and 80, optionally, the light emitting element 20 includes a red light emitting element 20R, a blue light emitting element 20B and a green light emitting element 20G. The first pixel circuit 101 is connected to the red light emitting element 20R, the second pixel circuit 102 is connected to the blue light emitting element 20B, and the third pixel circuit 103 is connected to the green light emitting element 20G.

[0568] The first power supply voltage signal line P11 and the third power supply voltage signal line P13 are the same signal line.

[0569] The light emitting element 20 and the corresponding pixel circuit 10 can be arranged as described above, and will not be described here.

[0570] In some display panels, the difference in the cross voltage requirements of the red light emitting element 20R and the green light emitting element 20G can not be large, and the red light emitting element 20R and the green light emitting element 20G can use the same positive power supply voltage PVDD.

[0571] Specifically, as shown in FIGS. 24-36, 61-70, 79 and 80, the positive power supply voltage PVDD of the red sub-pixel is provided by the first power supply voltage signal line P11, and the positive power supply voltage PVDD is the first power supply voltage VR; the positive power supply voltage PVDD of the green sub-pixel is provided by the third power supply voltage signal line P13, and the positive power supply voltage PVDD is the third power supply voltage VG. Therefore, the first power supply voltage VR and the third power supply voltage VG can be the same, at this time, the first power supply voltage signal line P11 and the third power supply voltage signal line P13 can be set as the same signal line, so that the red sub-pixel and the green sub-pixel share the same first power supply signal line P1, which can reduce the number of first power supply signal lines P1 while reducing power consumption, thereby facilitating the improvement of the light transmittance of the display panel.

[0572] Optionally, the second power supply voltage VB is greater than the first power supply voltage VR, and the first power supply voltage VR is equal to the third power supply voltage VG.

[0573] The first power voltage signal line P11 and the second power voltage signal line P12 are arranged alternately along the second direction Y, so that the first power voltage signal line P11 and the second power voltage signal line P12 are uniformly distributed along the second direction Y, thereby facilitating the electrical connection between the first power voltage signal line P11 and the second power voltage signal line P12 and the corresponding pixel circuit 10, and ensuring that the pixel circuit 10 corresponding to each color sub-pixel can receive the required positive power voltage PVDD.

[0574] With reference back to FIGS. 24-36, 61-70, 79 and 80, optionally, the first power voltage signal line P11 and the second power voltage signal line P12 are arranged alternately along the second direction Y.

[0575] Specifically, as shown in FIGS. 24-36, 61-70, 79 and 80, by arranging the first power voltage signal line P11 and the second power voltage signal line P12 alternately along the second direction Y, the first power voltage signal line P11 and the second power voltage signal line P12 can be uniformly distributed along the second direction Y, thereby facilitating the electrical connection between the first power voltage signal line P11 and the second power voltage signal line P12 and the corresponding pixel circuit 10, and ensuring that the pixel circuit 10 corresponding to each color sub-pixel can receive the required positive power voltage PVDD.

[0576] With reference back to FIGS. 24-36, 61-70, 79 and 80, optionally, the display panel provided by the embodiment of the present application further includes a plurality of third power signal lines P3, the plurality of third power signal lines P3 extend along the second direction Y and are arranged along the first direction X, and the third power signal lines P3 and the first power signal lines P1 are located in different film layers. The plurality of third power signal lines P3 include a first power connection signal line P31 and a second power connection signal line P32, the first power connection signal line P31 is electrically connected with at least two first power voltage signal lines P11, and the second power connection signal line P32 is electrically connected with at least two second power voltage signal lines P12.

[0577] Specifically, as shown in FIGS. 24-36, 61-70, 79 and 80, the plurality of third power signal lines P3 and the plurality of first power signal lines P1 are located in different film layers and are arranged in a cross manner.

[0578] Further, the plurality of third power signal lines P3 are divided into the first power connection signal line P31 and the second power connection signal line P32.

[0579] The first power connection signal line P31 is electrically connected with at least two first power voltage signal lines P11, so that the first power connection signal line P31 and the first power voltage signal line P11 form a grid wiring structure, which is conducive to reducing the line resistance, thereby reducing the voltage drop of the first power voltage and ensuring the stability of the first power voltage.

[0580] Similarly, the second power connection signal line P32 and the at least two second power voltage signal lines P12 are electrically connected, so that the second power connection signal line P32 and the second power voltage signal line P12 form a mesh wiring structure, which is conducive to reducing the line resistance, and in turn can reduce the voltage drop of the second power voltage, and ensure the stability of the first power voltage.

[0581] With reference to FIGS. 24-36, 61-70, 79 and 80, alternatively, the first power connection signal line P31 and the second power connection signal line P32 are arranged alternately along the first direction X.

[0582] Specifically, as shown in FIGS. 24-36, 61-70, 79 and 80, by arranging the first power connection signal line P31 and the second power connection signal line P32 to be arranged alternately along the first direction X, the first power connection signal line P31 and the second power connection signal line P32 can be uniformly distributed along the first direction X, thereby facilitating the electrical connection between the first power connection signal line P31 and the second power connection signal line P32 and the corresponding first power voltage signal line P11 and second power voltage signal line P12. Meanwhile, when the first power voltage signal line P11 and the second power voltage signal line P12 are arranged alternately along the second direction Y, the first power connection signal line P31 and the second power connection signal line P32 are arranged alternately along the first direction X, which can uniformly distribute the perforated connection positions between the first power signal line P1 and the third power signal line P3, thereby improving the topography uniformity of the display panel, and in turn improving the overall visual effect of the display panel.

[0583] With reference to FIGS. 24-36, 61-70, 79 and 80, alternatively, the third power signal line P3 and the green light emitting element 20G at least partially overlap in a direction perpendicular to the plane of the display panel.

[0584] Among them, since the human eye has the highest sensitivity to green, by arranging the third power signal line P3 and the green light emitting element 20G to at least partially overlap in a direction perpendicular to the plane of the display panel, the large line width of the third power signal line P3 can be used to improve the flatness of the anode 111 of the green light emitting element 20G, thereby reducing the brightness difference of the green light emitting element 20G when viewing the display panel at the same inclination angle in different orientations, reducing the color difference in different orientations at the same inclination angle, improving the four-orientation color deviation, and improving the display effect of the display panel.

[0585] FIG. 81 is a schematic view of an overlapping relationship between a third power supply signal line and a green light emitting element according to an embodiment of the present application. As shown in FIG. 81, in the first direction X, the third power supply signal line P3 includes opposite first and second boundaries B1 and B2, and in the first direction X, the green light emitting element 20G includes opposite third and fourth boundaries B3 and B4. In the first direction X, the first and second boundaries B1 and B2 are both located between the third and fourth boundaries B3 and B4, and the first boundary B1 is located between the second boundary B2 and the third boundary B3. In the first direction X, the distance between the first boundary B1 and the third boundary B3 is d1, and the distance between the second boundary B2 and the fourth boundary B4 is d2, where d1 = d2.

[0586] Specifically, as shown in FIG. 81, when the line width of the third power supply signal line P3 is less than the length of the green light emitting element 20G in the first direction X, the first and second boundaries B1 and B2 of the third power supply signal line P3 can be located between the third and fourth boundaries B3 and B4 of the green light emitting element 20G, and in the first direction X, the distance d1 between the first boundary B1 and the third boundary B3 is equal to the distance d2 between the second boundary B2 and the fourth boundary B4. In this way, in the direction perpendicular to the plane of the display panel, the central axis of the third power supply signal line P3 extending in the first direction X can be aligned with the central axis of the green light emitting element 20G extending in the first direction X, thereby improving the positional symmetry of the third power supply signal line P3 and the green light emitting element 20G, and further reducing the color difference at different azimuths and the same inclination angle, improving the four-azimuth color deviation, and making the color performance of the display panel at different angles more consistent.

[0587] It should be noted that in FIG. 81, the anode 111 boundary of the green light emitting element 20G is used as the boundary of the green light emitting element 20G, but this is not limiting, and in other embodiments, the boundary of the light emitting region of the green light emitting element 20G can also be used as the boundary of the green light emitting element 20G, which is not limited in the embodiments of the present application.

[0588] Continuing to refer to FIG. 79, the third power supply signal line P3 can cover the green light emitting element 20G in the direction perpendicular to the plane of the display panel.

[0589] In this way, by arranging the third power supply signal line P3 to cover the green light emitting element 20G in the direction perpendicular to the plane of the display panel, the flatness of the anode 111 of the green light emitting element 20G can be further improved, thereby further improving the inconsistency of the four-azimuth color deviation and improving the display effect of the display panel.

[0590] With reference to FIGS. 24-36, 61-70, 79 and 80, optionally, the light emitting element 20 includes a red light emitting element 20R, a blue light emitting element 20B and a green light emitting element 20G. The first power supply signal line P1 and the green light emitting element 20G at least partially overlap in a direction perpendicular to the plane on which the display panel lies.

[0591] Among them, since the human eye is most sensitive to green, by setting the first power supply signal line P1 and the green light emitting element 20G at least partially overlap in a direction perpendicular to the plane on which the display panel lies, the larger line width of the first power supply signal line P1 can be utilized to improve the flatness of the anode 111 of the green light emitting element 20G, and thus when the display panel is viewed at different orientations with the same inclination angle, the luminance difference of the green light emitting element 20G can be reduced, the color difference at different orientations with the same inclination angle can be reduced, the four-orientation color cast can be improved, and the display effect of the display panel can be improved.

[0592] FIG. 82 is a schematic diagram of the overlapping relationship between a first power supply signal line and a green light emitting element according to an embodiment of the present application. As shown in FIG. 82, optionally, in the second direction Y, the first power supply signal line P1 includes opposite fifth and sixth boundaries B5 and B6. In the second direction Y, the green light emitting element 20G includes opposite seventh and eighth boundaries B7 and B8. Along the second direction Y, the fifth and sixth boundaries B5 and B6 are both located between the seventh and eighth boundaries B7 and B8, and the fifth boundary B5 is located between the sixth boundary B6 and the seventh boundary B7. Along the second direction Y, the distance between the fifth and seventh boundaries B5 and B7 is d3, and the distance between the sixth and eighth boundaries B6 and B8 is d4, where d3=d4.

[0593] Specifically, as shown in FIG. 82, when the line width of the first power supply signal line P1 is smaller than the length of the green light emitting element 20G in the second direction Y, the fifth and sixth boundaries B5 and B6 of the first power supply signal line P1 can be set to be located between the seventh and eighth boundaries B7 and B8 of the green light emitting element 20G, and in the second direction Y, the distance d3 between the fifth and seventh boundaries B5 and B7 is equal to the distance d4 between the sixth and eighth boundaries B6 and B8. In this way, along a direction perpendicular to the plane on which the display panel lies, the central axis of the first power supply signal line P1 extending in the second direction Y can be aligned with the central axis of the green light emitting element 20G extending in the second direction Y, so that the positional symmetry of the first power supply signal line P1 and the green light emitting element 20G can be improved, the color difference at different orientations with the same inclination angle can be further reduced, the four-orientation color cast can be improved, and the color performance of the display panel at different angles can be made more consistent.

[0594] It is to be noted that the anode 111 of the green light emitting element 20G is taken as the boundary of the green light emitting element 20G in FIG. 82, but is not limited thereto, and in other embodiments, the boundary of the light emitting region of the green light emitting element 20G can also be taken as the boundary of the green light emitting element 20G, and the embodiments of the present application do not make a specific limitation thereon.

[0595] FIG. 83 is a schematic view of the overlapping relationship between another first power signal line and the green light emitting element according to an embodiment of the present application. As shown in FIG. 83, the light emitting element 20 includes a red light emitting element 20R, a blue light emitting element 20B and a green light emitting element 20G. In the direction perpendicular to the plane where the display panel is located, the first power signal line P1 covers the green light emitting element 20G.

[0596] In the direction perpendicular to the plane where the display panel is located, the first power signal line P1 covers the green light emitting element 20G, which can further improve the flatness of the anode 111 of the green light emitting element 20G, thereby further improving the inconsistency of the four-direction color cast and improving the display effect of the display panel.

[0597] It is to be noted that the first direction X is taken as the row direction and the second direction Y is taken as the column direction in FIGS. 24-36, FIGS. 61-70, FIG. 79 and FIG. 80, but is not limited thereto, and the embodiments of the present application do not make a specific limitation thereon.

[0598] With continued reference to FIGS. 33 and 68, the plurality of red light emitting elements 20R and the plurality of blue light emitting elements 20B form a first virtual quadrilateral Z1, the red light emitting element 20R is located at a first vertex of the first virtual quadrilateral Z1, the blue light emitting element 20B is located at a second vertex of the first virtual quadrilateral Z1, the first vertex and the second vertex are alternately and spaced apart, and the green light emitting element 20G is located inside the first virtual quadrilateral Z1; the plurality of green light emitting elements 20G form a second virtual quadrilateral Z2, and the plurality of green light emitting elements 20G are respectively located at the vertices of the second virtual quadrilateral Z2, and the red light emitting element 20R or the blue light emitting element 20B is located inside the second virtual quadrilateral Z2.

[0599] Specifically, as shown in FIGS. 33 and 68, the plurality of red light emitting elements 20R and the plurality of blue light emitting elements 20B form a first virtual quadrilateral Z1, two red light emitting elements 20R are located at opposite corners of the first virtual quadrilateral Z1, and two blue light emitting elements 20B are located at the other two opposite corners of the first virtual quadrilateral Z1. Moreover, the green light emitting element 20G is arranged inside the first virtual quadrilateral Z1.

[0600] The plurality of green light emitting elements 20G can also constitute a second virtual quadrilateral Z2, and in the second virtual quadrilateral Z2, the red light emitting element 20R can be located or the blue light emitting element 20B can be located.

[0601] Through the arrangement mode of the light emitting element described above, the rendering effect of the light emitting element can be ensured to be better, the image edge is more clear, the sawtooth feeling is reduced, and the color display effect of the display panel is further ensured.

[0602] Based on the same inventive concept, the embodiment of the present application also provides a display device, and FIG. 84 is a structural schematic diagram of a display device provided by an embodiment of the present application. As shown in FIG. 84, the display device 90 includes the display panel 91 described in any embodiment of the present application, and therefore the display device 90 provided by the embodiment of the present application has the technical effects of the technical solutions in any of the above embodiments. The same or corresponding structures and explanations of terms are not repeated here.

[0603] The display device 90 provided by the embodiment of the present application can be a mobile phone as shown in FIG. 84, or any electronic product with a display function, including but not limited to the following categories: television, notebook computer, desktop display, tablet computer, digital camera, smart bracelet, smart glasses, vehicle-mounted display, medical equipment, industrial control equipment, touch interaction terminal, etc. The embodiment of the present application does not make special limitations here.

[0604] It should be understood that the various forms of flow shown above can be used to reorder, add or delete steps. For example, each step described in the present application can be executed in parallel, sequentially or in a different order, as long as the desired results of the technical solutions of the present application can be achieved, and the present application does not make limitations here.

[0605] The above specific embodiments do not constitute a limitation on the protection scope of the present application....

Claims

1. A display panel comprising a display area, the display area comprising a plurality of pixel circuits arranged in an array, the plurality of pixel circuits comprising a first pixel circuit, a second pixel circuit and a third pixel circuit; the first pixel circuit, the second pixel circuit and the third pixel circuit are respectively connected with light emitting elements of different colors; the display panel further comprises a plurality of data signal lines, the plurality of data signal lines comprising a first data signal line, a second data signal line and a third data signal line; the first data signal line is electrically connected with the first pixel circuit, the second data signal line is electrically connected with the second pixel circuit, and the third data signal line is electrically connected with the third pixel circuit.

2. The display panel of claim 1, wherein the plurality of pixel circuits form a plurality of columns of first pixel circuit columns, the first pixel circuit columns comprising the first pixel circuits and the second pixel circuits arranged alternately along a column direction; the plurality of pixel circuits form a plurality of columns of second pixel circuit columns, the second pixel circuit columns comprising the third pixel circuits arranged along the column direction; the first pixel circuit columns and the second pixel circuit columns are arranged alternately along a row direction; the plurality of data signal lines extend along the column direction and are arranged along the row direction; the first data signal line is electrically connected with the first pixel circuits in a same first pixel circuit column, the second data signal line is electrically connected with the second pixel circuits in the same first pixel circuit column, and the third data signal line is electrically connected with the third pixel circuits in a same second pixel circuit column.

3. The display panel of claim 2, wherein the plurality of columns of first pixel circuit columns are divided into a plurality of first pixel circuit column groups, the first pixel circuit column groups comprising two columns of first pixel circuit columns, the two columns of first pixel circuit columns being a first group of pixel circuit columns and a second group of pixel circuit columns respectively; the first data signal line to which the first pixel circuits in the first group of pixel circuit columns are connected is a first group of data signal lines; the second data signal line to which the second pixel circuits in the first group of pixel circuit columns are connected is a second group of data signal lines; the first data signal line to which the first pixel circuits in the second group of pixel circuit columns are connected is a third group of data signal lines; and the second data signal line to which the second pixel circuits in the second group of pixel circuit columns are connected is a fourth group of data signal lines; in the first pixel circuit column group, the first group of data signal lines and the third group of data signal lines are electrically connected, and the second group of data signal lines and the fourth group of data signal lines are electrically connected; the first pixel circuits connected with the first group of data signal lines and the first pixel circuits connected with the third group of data signal lines are located in different pixel circuit rows, and the second pixel circuits connected with the second group of data signal lines and the second pixel circuits connected with the fourth group of data signal lines are located in different pixel circuit rows.

4. The display panel of claim 3, wherein ​ The first pixel circuit and the second pixel circuit are arranged alternately and spaced apart along the row direction. The first pixel circuit column group comprises two adjacent first pixel circuit columns. 5.The display panel of claim 3, further comprising a non-display area located at least one side of the display area. In the first pixel circuit column group, the first intra-group data signal line and the third intra-group data signal line are electrically connected by a first data connection line; and the second intra-group data signal line and the fourth intra-group data signal line are electrically connected by a second data connection line. The first data connection line and the second data connection line are located in the non-display area. 6.The display panel of claim 3, wherein, In the first pixel circuit column group, the first intra-group data signal line and the third intra-group data signal line are electrically connected by a first data connection line; and the second intra-group data signal line and the fourth intra-group data signal line are electrically connected by a second data connection line. The first data connection line and the second data connection line are located in the display area. 7.The display panel of claim 3, further comprising a plurality of data signal output lines and a plurality of gating circuits. The data signal output lines comprise a first data signal output line and a second data signal output line. The gating circuits comprise a first gating circuit and a second gating circuit. In the first pixel circuit column group, the first intra-group data signal line and the third intra-group data signal line are electrically connected to the same first data signal output line through the first gating circuit, and the first gating circuit is configured to transmit data signals output by the first data signal output line to the first intra-group data signal line and the third intra-group data signal line in time division manner. In the first pixel circuit column group, the second intra-group data signal line and the fourth intra-group data signal line are electrically connected to the same second data signal output line through the second gating circuit, and the second gating circuit is configured to transmit data signals output by the second data signal output line to the second intra-group data signal line and the fourth intra-group data signal line in time division manner. 8.The display panel of claim 7, wherein, The first gating circuit comprises a first switch transistor and a second switch transistor, the first switch transistor is connected between the first intra-group data signal line and the first data signal output line, and the second switch transistor is connected between the third intra-group data signal line and the first data signal output line. The second gating circuit comprises a third switch transistor and a fourth switch transistor, the third switch transistor is connected between the second intra-group data signal line and the second data signal output line, and the fourth switch transistor is connected between the fourth intra-group data signal line and the second data signal output line. The gate of the first switch transistor and the gate of the fourth switch transistor receive a first switch signal. The gate of the second switch transistor and the gate of the third switch transistor receive a second switch signal. 9.The display panel of claim 2, wherein, The plurality of first pixel circuit columns are divided into a plurality of first pixel circuit column groups, and each first pixel circuit column group comprises two adjacent first pixel circuit columns, which are a first group inner pixel circuit column and a second group inner pixel circuit column respectively; The first data signal line connected to the first pixel circuit in the first group inner pixel circuit column is a first group inner data signal line, the second data signal line connected to the second pixel circuit in the first group inner pixel circuit column is a second group inner data signal line, the first data signal line connected to the first pixel circuit in the second group inner pixel circuit column is a third group inner data signal line, and the second data signal line connected to the second pixel circuit in the second group inner pixel circuit column is a fourth group inner data signal line. In the row direction, the first group inner data signal line and the second group inner data signal line are located on different sides of the first group inner pixel circuit column, and the third group inner data signal line and the fourth group inner data signal line are located on different sides of the second group inner pixel circuit column.

10. The display panel of claim 2, wherein The plurality of first pixel circuit columns are divided into a plurality of first pixel circuit column groups, and each first pixel circuit column group comprises two adjacent first pixel circuit columns, which are a first group inner pixel circuit column and a second group inner pixel circuit column respectively; The first data signal line connected to the first pixel circuit in the first group inner pixel circuit column is a first group inner data signal line, the second data signal line connected to the second pixel circuit in the first group inner pixel circuit column is a second group inner data signal line, the first data signal line connected to the first pixel circuit in the second group inner pixel circuit column is a third group inner data signal line, and the second data signal line connected to the second pixel circuit in the second group inner pixel circuit column is a fourth group inner data signal line. In the first pixel circuit column group, the second group inner data signal line and the fourth group inner data signal line are located between the first group inner data signal line and the third group inner data signal line.

11. The display panel of claim 10, further comprising a non-display area located on at least one side of the display area. In the first pixel circuit column group, the first group inner data signal line and the third group inner data signal line are electrically connected by a first data connection line, and the second group inner data signal line and the fourth group inner data signal line are electrically connected by a second data connection line. The first data connection line and the second data connection line are both located in the non-display area. The second data connection line is located on a side of the first data connection line close to the display area.

12. The display panel of claim 11, further comprising a plurality of data signal output lines. The data signal output lines comprise a first data signal output line and a second data signal output line. ​ In the first pixel circuit column group, the first data connection line is electrically connected with the first data signal output line, and the second data connection line is electrically connected with the second data signal output line. The first data connection line and the second data signal output line are located in different film layers.

13. The display panel of claim 2, wherein, A plurality of the first pixel circuit columns are divided into a plurality of first pixel circuit column groups, and each of the first pixel circuit column groups includes two first pixel circuit columns, which are a first group inner pixel circuit column and a second group inner pixel circuit column, respectively. The first data signal line connected with the first pixel circuit in the first group inner pixel circuit column is a first group inner data signal line, the second data signal line connected with the second pixel circuit in the first group inner pixel circuit column is a second group inner data signal line, the first data signal line connected with the first pixel circuit in the second group inner pixel circuit column is a third group inner data signal line, and the second data signal line connected with the second pixel circuit in the second group inner pixel circuit column is a fourth group inner data signal line. In the first pixel circuit column group, the first group inner data signal line, the second group inner data signal line, the third group inner data signal line, and the fourth group inner data signal line are arranged in sequence along the row direction.

14. The display panel of claim 13, further comprising a non-display area located at least one side of the display area. In the first pixel circuit column group, the first group inner data signal line and the third group inner data signal line are electrically connected by a first data connection line, and the second group inner data signal line and the fourth group inner data signal line are electrically connected by a second data connection line. The first data connection line and the second data connection line are located in the non-display area. The second data connection line is located on a side of the first data connection line close to the display area, and the second data connection line and the third group inner data signal line are located in different film layers. Alternatively, The first data connection line is located on a side of the second data connection line close to the display area, and the first data connection line and the second group inner data signal line are located in different film layers.

15. The display panel of claim 3, wherein, In the first pixel circuit column group, the first group inner data signal line and the third group inner data signal line are electrically connected by a first data connection line. The second group inner data signal line and the fourth group inner data signal line are electrically connected by a second data connection line. The first data connection line and the second data connection line are located in the same film layer, or The first data connection line and the second data connection line are located in different film layers.

16. The display panel of claim 2, wherein, The third data signal line includes a first sub-data signal line and a second sub-data signal line. In the row direction, the first sub-data signal line and the second sub-data signal line are located on different sides of the second pixel circuit column.

17. The display panel of claim 2, wherein, The third data signal line comprises a first sub-data signal line and a second sub-data signal line; The first sub-data signal line and the third pixel circuit in the odd row of the second pixel circuit column are electrically connected; The second sub-data signal line and the third pixel circuit in the even row of the second pixel circuit column are electrically connected.

18. The display panel of claim 2, wherein, The third data signal line comprises a first sub-data signal line and a second sub-data signal line; The first sub-data signal line and all the third pixel circuits in the second pixel circuit column are electrically connected; The second sub-data signal line and all the third pixel circuits in the second pixel circuit column are electrically connected.

19. The display panel of claim 17 or 18, wherein, The first sub-data signal line and the second sub-data signal line connected by the same second pixel circuit column are electrically connected.

20. The display panel of claim 19, further comprising a non-display area located at least one side of the display area; The first sub-data signal line and the second sub-data signal line connected by the same second pixel circuit column are electrically connected by a third data connection line; The third data connection line is located in the non-display area.

21. The display panel of claim 19, wherein, The first sub-data signal line and the second sub-data signal line connected by the same second pixel circuit column are electrically connected by a third data connection line; The third data connection line is located in the display area.

22. The display panel of claim 20, wherein, A plurality of the first pixel circuit columns are divided into a plurality of first pixel circuit column groups, and each first pixel circuit column group comprises two first pixel circuit columns, which are a first group inner pixel circuit column and a second group inner pixel circuit column, respectively; The first data signal line connected by the first pixel circuit in the first group inner pixel circuit column is a first group inner data signal line, the second data signal line connected by the second pixel circuit in the first group inner pixel circuit column is a second group inner data signal line, the first data signal line connected by the first pixel circuit in the second group inner pixel circuit column is a third group inner data signal line, and the second data signal line connected by the second pixel circuit in the second group inner pixel circuit column is a fourth group inner data signal line; In the first pixel circuit column group, the first group inner data signal line and the third group inner data signal line are electrically connected by a first data connection line; The second group inner data signal line and the fourth group inner data signal line are electrically connected by a second data connection line; The first data connection line and the second data connection line are both located in the non-display area; The third data connection line is located on a side of the first data connection line close to the display area, and the second data connection line is located between the third data connection line and the first data connection line.

23. The display panel of claim 22, further comprising a plurality of data signal output lines. The data signal output lines include a first data signal output line, a second data signal output line, and a third data signal output line; In the first pixel circuit column group, the first data connection line is electrically connected with the first data signal output line, and the second data connection line is electrically connected with the second data signal output line; The third data connection line is electrically connected with the third data signal output line; The third data signal output line and the first data connection line are located in different film layers, and the third data signal output line and the second data connection line are located in different film layers.

24. The display panel of claim 16, wherein, Further comprising a plurality of data signal output lines and a plurality of gate-on circuits; The data signal output lines include a third data signal output line; The gate-on circuits include a third gate-on circuit; In the first sub-data signal line and the second sub-data signal line connected with the same second pixel circuit column, the first sub-data signal line and the second sub-data signal line are electrically connected with the same third data signal output line through the third gate-on circuit, and the third gate-on circuit is used for time-division transmission of the data signal output by the third data signal output line to the first sub-data signal line and the second sub-data signal line.

25. The display panel of claim 24, wherein The third gate-on circuit includes a fifth switch transistor and a sixth switch transistor, the fifth switch transistor is connected between the first sub-data signal line and the third data signal output line, and the sixth switch transistor is connected between the second sub-data signal line and the third data signal output line; The gate of the fifth switch transistor receives a third switch signal, and the gate of the sixth switch transistor receives a fourth switch signal.

26. The display panel of claim 2, wherein The third pixel circuit in one of the second pixel circuit columns is electrically connected with only one of the third data signal lines.

27. The display panel of claim 26, wherein A plurality of the second pixel circuit columns are divided into a plurality of second pixel circuit column groups, the second pixel circuit column groups include two adjacent second pixel circuit columns, which are a third group of pixel circuit columns and a fourth group of pixel circuit columns respectively; The third data signal line connected with the third group of pixel circuit columns is a fifth group of data signal lines, and the third data signal line connected with the fourth group of pixel circuit columns is a sixth group of data signal lines; In the second pixel circuit column group, the fifth group of data signal lines is located on the side of the third group of pixel circuit columns away from the fourth group of pixel circuit columns, and the sixth group of data signal lines is located on the side of the fourth group of pixel circuit columns away from the third group of pixel circuit columns; Or, In the second pixel circuit column group, the fifth group of data signal lines is located on the side of the third group of pixel circuit columns close to the fourth group of pixel circuit columns, and the sixth group of data signal lines is located on the side of the fourth group of pixel circuit columns close to the third group of pixel circuit columns. ​ 28. The display panel of claim 26, wherein, a plurality of the second pixel circuit columns are divided into a plurality of second pixel circuit column groups, each of the second pixel circuit column groups comprising two adjacent second pixel circuit columns, the two adjacent second pixel circuit columns being a third group of pixel circuit columns and a fourth group of pixel circuit columns, respectively; the third data signal lines connected to the third group of pixel circuit columns are a fifth group of data signal lines; and the third data signal lines connected to the fourth group of pixel circuit columns are a sixth group of data signal lines. in the second pixel circuit column group, the fifth group of data signal lines are located on a side of the third group of pixel circuit columns away from the fourth group of pixel circuit columns, and the sixth group of data signal lines are located on a side of the fourth group of pixel circuit columns close to the third group of pixel circuit columns. alternatively, in the second pixel circuit column group, the fifth group of data signal lines are located on a side of the third group of pixel circuit columns close to the fourth group of pixel circuit columns, and the sixth group of data signal lines are located on a side of the fourth group of pixel circuit columns away from the third group of pixel circuit columns.

29. The display panel of claim 2, wherein, in a direction perpendicular to a plane on which the display panel is located, the first data signal lines and the second data signal lines both overlap the first pixel circuit columns, and the third data signal lines overlap the second pixel circuit columns.

30. The display panel of claim 2, wherein, a plurality of the first pixel circuit columns and a plurality of the second pixel circuit columns are divided into a plurality of third pixel circuit column groups, each of the third pixel circuit column groups comprising the first pixel circuit column and the second pixel circuit column adjacent to each other along the row direction, the first pixel circuit column and the second pixel circuit column being arranged in a mirror image.

31. The display panel of claim 30, wherein, in the third pixel circuit column group, the first data signal lines and the second data signal lines connected to the first pixel circuit column, and the third data signal lines connected to the second pixel circuit column are all located between the first pixel circuit column and the second pixel circuit column.

32. The display panel of claim 31, wherein, in two adjacent third pixel circuit column groups, the arrangement directions of the first data signal lines and the second data signal lines in different third pixel circuit column groups are the same or opposite.

33. The display panel of claim 31, wherein, a plurality of third power signal lines are further included, the plurality of third power signal lines extending along the column direction and arranged along the row direction; the plurality of third power signal lines comprise a first sub-power signal line, a second sub-power signal line, and a third sub-power signal line arranged adjacent to each other in sequence along the row direction; the arrangement directions of the first data signal lines and the second data signal lines between the first sub-power signal line and the second sub-power signal line are the same as or opposite to the arrangement directions of the first data signal lines and the second data signal lines between the second sub-power signal line and the third sub-power signal line.

34. The display panel of claim 31, wherein, the pixel circuit comprises a data write transistor, an active layer of the data write transistor comprises a first connection end; in the third pixel circuit column group, along the row direction, the first connection end of the first pixel circuit is located on a side of the second data signal line close to the first data signal line, and the first data signal line and the first connection end of the first pixel circuit form an electrical connection; in the third pixel circuit column group, along the row direction, the first connection end of the second pixel circuit is located on a side of the first data signal line close to the second data signal line, and the second data signal line and the first connection end of the second pixel circuit form an electrical connection.

35. The display panel of claim 31, wherein, the display area comprises a first display area and a second display area; along the row direction, the first display area is located on at least one side of the second display area; the display panel further comprises a plurality of auxiliary signal lines, the auxiliary signal lines extend along the column direction and are arranged along the row direction; the auxiliary signal lines are at least partially located in the second display area, and the auxiliary signal lines are electrically connected with the data signal lines in the first display area; in the third pixel circuit column group, the auxiliary signal lines are located between the data signal lines connected by the first pixel circuit column and the data signal lines connected by the second pixel circuit column.

36. The display panel of claim 35, wherein, the auxiliary signal lines corresponding to one of the third pixel circuit column groups are less than or equal to 1.

37. The display panel of claim 31, wherein, the display area comprises a first display area and a second display area; along the row direction, the first display area is located on at least one side of the second display area; the display panel further comprises a plurality of auxiliary signal lines, the auxiliary signal lines extend along the column direction and are arranged along the row direction; the auxiliary signal lines are at least partially located in the second display area, and the auxiliary signal lines are electrically connected with the data signal lines in the first display area; the auxiliary signal lines and the data signal lines are located in different film layers; in a direction perpendicular to a plane in which the display panel is located, the auxiliary signal lines and the data signal lines at least partially overlap; or, in a direction perpendicular to a plane in which the display panel is located, the auxiliary signal lines and the data signal lines do not overlap.

38. The display panel of claim 37, wherein, one of the first pixel circuit columns corresponds to one of the auxiliary signal lines, and one of the second pixel circuit columns corresponds to one of the auxiliary signal lines; in the third pixel circuit column group, the auxiliary signal line corresponding to the first pixel circuit column is located between the first data signal line corresponding to the first pixel circuit column and the second data signal line, and the auxiliary signal line corresponding to the second pixel circuit column is located between the two third data signal lines corresponding to the second pixel circuit column; or, In the third pixel circuit column group, along the row direction, the auxiliary signal line corresponding to the first pixel circuit column is located on the same side of the first data signal line and the second data signal line corresponding to the first pixel circuit column, and the auxiliary signal line corresponding to the second pixel circuit column is located on the same side of the two third data signal lines corresponding to the second pixel circuit column. Alternatively, In the direction perpendicular to the plane where the display panel is located, the auxiliary signal line corresponding to the first pixel circuit column and the data signal line corresponding to the first pixel circuit column at least partially overlap, and the auxiliary signal line corresponding to the second pixel circuit column and the data signal line corresponding to the second pixel circuit column at least partially overlap. The data signal lines at least partially overlap.

39. The display panel of claim 37, wherein The third pixel circuit column group corresponds to three auxiliary signal lines; In the third pixel circuit column group, along the row direction, the three auxiliary signal lines are located between the first pixel circuit column and the second pixel circuit column, and the auxiliary signal lines are located between two adjacent data signal lines.

40. The display panel of claim 37, wherein One column of the first pixel circuit columns corresponds to two auxiliary signal lines, and one column of the second pixel circuit columns corresponds to two auxiliary signal lines; In the direction perpendicular to the plane where the display panel is located, the auxiliary signal lines and the data signal lines at least partially overlap.

41. The display panel of claim 35, wherein In the third pixel circuit column group, the first data signal line connected to the first pixel circuit column is located on the side of the second data signal line connected to the first pixel circuit column away from the first pixel circuit column, and the spacing between the auxiliary signal line and the second data signal line is greater than the spacing between the auxiliary signal line and the third data signal line. Alternatively, In the third pixel circuit column group, the second data signal line connected to the first pixel circuit column is located on the side of the first data signal line connected to the first pixel circuit column away from the first pixel circuit column, and the spacing between the auxiliary signal line and the first data signal line is greater than the spacing between the auxiliary signal line and the third data signal line.

42. The display panel of claim 35, wherein In the third pixel circuit column group, the number of data signal lines connected to the first pixel circuit column is greater than the number of data signal lines connected to the second pixel circuit column.

43. The display panel of claim 30, wherein The display area includes a first display area and a second display area; Along the row direction, the first display area is located on at least one side of the second display area; The display panel further includes a plurality of auxiliary signal lines, the auxiliary signal lines extend along the column direction and are arranged along the row direction; The auxiliary signal lines are at least partially located in the second display area, and the auxiliary signal lines are electrically connected to the data signal lines in the first display area; In the third pixel circuit column group, the number of the data signal lines on the two sides of the auxiliary signal line is different along the row direction.

44. The display panel of claim 1, wherein, The plurality of data signal lines are located in the same film layer.

45. The display panel of claim 1, wherein, At least two of the data signal lines are located in different film layers; In a direction perpendicular to the plane on which the display panel lies, the data signal lines located in different film layers at least partially overlap.

46. The display panel of claim 1 or 2, wherein, The light emitting elements include red light emitting elements, blue light emitting elements, and green light emitting elements; The first pixel circuit is connected to the red light emitting elements; The second pixel circuit is connected to the blue light emitting elements; The third pixel circuit is connected to the green light emitting elements.

47. The display panel of claim 1, wherein, Further comprising a plurality of first power signal lines, the plurality of first power signal lines extending along a first direction and arranged along a second direction, the first direction intersecting the second direction; The plurality of first power signal lines include a first power voltage signal line, a second power voltage signal line, and a third power voltage signal line; The first power voltage signal line is connected to the first pixel circuit, the second power voltage signal line is connected to the second pixel circuit, and the third power voltage signal line is connected to the third pixel circuit; The first power voltage signal line is used to transmit a first power voltage, the second power voltage signal line is used to transmit a second power voltage, and the third power voltage signal line is used to transmit a third power voltage; At least two of the first power voltage, the second power voltage, and the third power voltage are different.

48. The display panel of claim 47, wherein, The light emitting elements include red light emitting elements, blue light emitting elements, and green light emitting elements; The first pixel circuit is connected to the red light emitting elements, the second pixel circuit is connected to the blue light emitting elements, and the third pixel circuit is connected to the green light emitting elements; The second power voltage is greater than the third power voltage, and the third power voltage is greater than or equal to the first power voltage; Or, The second power voltage is greater than the first power voltage, and the first power voltage is greater than or equal to the third power voltage.

49. The display panel of claim 47, wherein, The light emitting elements include red light emitting elements, blue light emitting elements, and green light emitting elements; The first pixel circuit is connected to the red light emitting elements, the second pixel circuit is connected to the blue light emitting elements, and the third pixel circuit is connected to the green light emitting elements; The first power voltage signal line and the third power voltage signal line are the same signal line.

50. The display panel of claim 49, wherein, The second power voltage is greater than the first power voltage, and the first power voltage is equal to the third power voltage.

51. The display panel of claim 49, wherein, The first power voltage signal line and the second power voltage signal line are alternately arranged along the second direction. 52.The display panel of claim 49, wherein, a plurality of third power signal lines extending along the second direction and arranged along the first direction; the third power signal lines and the first power signal lines are located in different film layers; the plurality of third power signal lines include a first power connection signal line and a second power connection signal line; the first power connection signal line is electrically connected to at least two of the first power voltage signal lines, and the second power connection signal line is electrically connected to at least two of the second power voltage signal lines. 53.The display panel of claim 52, wherein, the first power connection signal line and the second power connection signal line are arranged along the first direction alternately. 54.The display panel of claim 52, wherein, in a direction perpendicular to a plane on which the display panel is located, the third power signal lines and the green light emitting elements at least partially overlap. 55.The display panel of claim 54, wherein, in the first direction, the third power signal lines include opposite first and second boundaries; in the first direction, the green light emitting elements include opposite third and fourth boundaries; along the first direction, the first and second boundaries are both located between the third and fourth boundaries, and the first boundary is located between the second boundary and the third boundary; along the first direction, a distance between the first and third boundaries is d1, and a distance between the second and fourth boundaries is d2, where d1=d2. 56.The display panel of claim 54, wherein, in a direction perpendicular to a plane on which the display panel is located, the third power signal lines cover the green light emitting elements. 57.The display panel of claim 47, wherein, the light emitting elements include red, blue, and green light emitting elements; in a direction perpendicular to a plane on which the display panel is located, the first power signal lines and the green light emitting elements at least partially overlap. 58.The display panel of claim 57, wherein, in the second direction, the first power signal lines include opposite fifth and sixth boundaries; in the second direction, the green light emitting elements include opposite seventh and eighth boundaries; along the second direction, the fifth and sixth boundaries are both located between the seventh and eighth boundaries, and the fifth boundary is located between the sixth boundary and the seventh boundary; along the second direction, a distance between the fifth and seventh boundaries is d3, and a distance between the sixth and eighth boundaries is d4, where d3=d4. 59.The display panel of claim 47, wherein, the light emitting elements include red, blue, and green light emitting elements; in a direction perpendicular to a plane on which the display panel is located, the first power signal lines cover the green light emitting elements. 60.The display panel of claim 2, wherein, the display region comprises a first display region and a second display region; in the row direction, the first display region is located at least one side of the second display region; the display panel further comprises a plurality of auxiliary signal lines, the auxiliary signal lines extend in the column direction and are arranged in the row direction; the auxiliary signal lines are at least partially located in the second display region, and the auxiliary signal lines are electrically connected with the data signal lines in the first display region; a plurality of the first pixel circuit columns and a plurality of the second pixel circuit columns are divided into a plurality of third pixel circuit column groups, the third pixel circuit column groups comprise the first pixel circuit columns and the second pixel circuit columns adjacent in the row direction; the third pixel circuit column groups correspond to one of the auxiliary signal lines, and the second pixel circuit columns correspond to one of the third data signal lines; in the third pixel circuit column groups, the first data signal lines and the second data signal lines connected with the first pixel circuit columns are located at different sides of the first pixel circuit columns, respectively; in at least one of the third pixel circuit column groups in the second display region, the auxiliary signal lines and the third data signal lines connected with the second pixel circuit columns are located at different sides of the second pixel circuit columns, respectively. 61.The display panel of claim 2, wherein, in the row direction, the first data signal lines connected with the first pixel circuit columns and the second data signal lines connected with the second pixel circuit columns are located at opposite sides of the first pixel circuit columns, respectively; in the row direction, the two third data signal lines connected with the second pixel circuit columns are located at opposite sides of the second pixel circuit columns, respectively. 62.The display panel of claim 61, wherein, the display region comprises a first display region and a second display region; in the row direction, the first display region is located at least one side of the second display region; the display panel further comprises a plurality of auxiliary signal lines, the auxiliary signal lines extend in the column direction and are arranged in the row direction; the auxiliary signal lines are at least partially located in the second display region, and the auxiliary signal lines are electrically connected with the data signal lines in the first display region; the auxiliary signal lines and the data signal lines are located in different film layers; or, the auxiliary signal lines and the data signal lines are located in the same film layer. 63.The display panel of claim 62, further comprising a plurality of third power signal lines, the plurality of third power signal lines extend in the column direction and are arranged in the row direction; one of the first pixel circuit columns corresponds to one of the auxiliary signal lines and one of the third power signal lines, and the auxiliary signal line and the third power signal line are located between the first data signal line and the second data signal line connected with the first pixel circuit column. A column of the second pixel circuit columns corresponds to one of the auxiliary signal lines and one of the third power signal lines, and the auxiliary signal line and the third power signal line are located between two of the third data signal lines connected by the second pixel circuit column.

64. The display panel of claim 62, wherein, A column of the first pixel circuit columns corresponds to one of the auxiliary signal lines, and a column of the second pixel circuit columns corresponds to one of the auxiliary signal lines. The auxiliary signal line is located between two of the data signal lines between the first pixel circuit column and the second pixel circuit column arranged adjacently.

65. The display panel of claim 62, wherein, A plurality of the first pixel circuit columns and a plurality of the second pixel circuit columns are divided into a plurality of third pixel circuit column groups, the third pixel circuit column groups comprising the first pixel circuit columns and the second pixel circuit columns arranged adjacently along the row direction; The third pixel circuit column groups correspond to three of the auxiliary signal lines; The auxiliary signal lines are located between any two of the data signal lines adjacently.

66. The display panel of claim 62, wherein, A column of the first pixel circuit columns corresponds to one or two of the auxiliary signal lines, and a column of the second pixel circuit columns corresponds to one or two of the auxiliary signal lines. The auxiliary signal lines and the data signal lines at least partially overlap in a direction perpendicular to a plane in which the display panel is located.

67. The display panel of claim 2, wherein, The display area comprises a first display area and a second display area; Along the row direction, the first display area is located on at least one side of the second display area; The display panel further comprises a plurality of auxiliary signal lines, the auxiliary signal lines extending along the column direction and arranged along the row direction; The auxiliary signal lines are at least partially located in the second display area, and the auxiliary signal lines are electrically connected with the data signal lines in the first display area; A column of the first pixel circuit columns corresponds to at least two of the auxiliary signal lines, and a column of the second pixel circuit columns corresponds to at least two of the auxiliary signal lines.

68. The display panel of claim 67, wherein, The number of the auxiliary signal lines corresponding to a column of the first pixel circuit columns is less than or equal to 4, and the number of the auxiliary signal lines corresponding to a column of the second pixel circuit columns is less than or equal to 4.

69. The display panel of claim 61, further comprising a plurality of third power signal lines, the plurality of third power signal lines extending along the column direction and arranged along the row direction; A column of the first pixel circuit columns corresponds to one of the third power signal lines, and a column of the second pixel circuit columns corresponds to one of the third power signal lines; Along the row direction, the third power signal lines are located between two of the data signal lines between the first pixel circuit column and the second pixel circuit column arranged adjacently.

70. The display panel of claim 69, wherein, ​ The third power signal line and the data signal line are located in different film layers in a direction perpendicular to a plane in which the display panel is located, and the third power signal line at least partially overlaps the two data signal lines between the adjacently arranged first pixel circuit column and second pixel circuit column.

71. The display panel of claim 69, wherein, the display region comprises a first display region and a second display region; in the row direction, the first display region is located at least one side of the second display region; the display panel further comprises a plurality of auxiliary signal lines, the auxiliary signal lines extend in the column direction and are arranged in the row direction; the auxiliary signal lines are at least partially located in the second display region, and the auxiliary signal lines are electrically connected with the data signal lines in the first display region; the auxiliary signal lines and the third power signal line are located in different film layers; in a direction perpendicular to a plane in which the display panel is located, the auxiliary signal lines at least partially overlap the third power signal line.

72. The display panel of claim 69, wherein, the light emitting element comprises a red light emitting element, a blue light emitting element and a green light emitting element; in a direction perpendicular to a plane in which the display panel is located, the red light emitting element, the green light emitting element and the blue light emitting element all at least partially overlap the third power signal line between the adjacently arranged first pixel circuit column and second pixel circuit column.

73. The display panel of claim 61, wherein, the light emitting element comprises a red light emitting element, a blue light emitting element and a green light emitting element; in a direction perpendicular to a plane in which the display panel is located, the red light emitting element, the green light emitting element and the blue light emitting element all at least partially overlap the data signal line between the adjacently arranged first pixel circuit column and second pixel circuit column.

74. The display panel of claim 1, wherein, the pixel circuit further comprises a driving transistor, a threshold compensation transistor and a shielding layer, a gate of the driving transistor and the threshold compensation transistor are connected to a first node; in a direction parallel to a plane in which the display panel is located, at least part of the shielding layer is located between the first node and the data signal line.

75. The display panel of claim 74, wherein, in a direction perpendicular to a plane in which the display panel is located, the shielding layer is located between an active layer of the driving transistor and the data signal line, and the shielding layer and the data signal line at least partially overlap.

76. The display panel of claim 74, wherein, a fixed voltage is applied to the shielding layer.

77. The display panel of claim 76, further comprising a plurality of third power signal lines, the plurality of third power signal lines extend in a second direction and are arranged in a first direction, the first direction intersects the second direction; the shielding layer and the third power signal line are electrically connected.

78. A display device comprising the display panel of any one of claims 1-77.

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