Solar cell, manufacturing method, and photovoltaic module

Abstract

A solar cell, a manufacturing method, and a photovoltaic module. In the solar cell, a silicon substrate has a first surface and a second surface, wherein the first surface and the second surface are arranged opposite each other; a first transport layer is provided on at least one of the first surface and the second surface, wherein the first transport layer comprises a polycrystalline silicon layer, the polycrystalline silicon layer of the first transport layer has an amorphous silicon region of the first transport layer, and the amorphous silicon region of the first transport layer is located on at least part of the surface of the polycrystalline silicon layer of the first transport layer that faces away from the silicon substrate; and a carrier collection layer is provided on the first transport layer, wherein at least part of the carrier collection layer is in contact with the amorphous silicon region of the first transport layer. Since an amorphous silicon region can achieve more rational energy band matching, which reduces contact resistance, the solar cell can effectively convert sunlight into electrical energy, thereby improving the photoelectric conversion efficiency of the solar cell.

Description

Solar cell, manufacturing method and photovoltaic module TECHNICAL FIELD

[0001] The present application relates to the technical field of solar photovoltaic technology, in particular to a solar cell, a manufacturing method and a photovoltaic module. BACKGROUND

[0002] The solar cell is a device for directly converting light energy into electrical energy. In the cell, a photo-generated carrier transport layer and a photo-generated carrier collection layer need to be made on the silicon substrate of the cell to guide the carriers out to achieve the purpose of generating electrical energy. Currently, the contact resistance is increased after the polycrystalline silicon in the photo-generated carrier collection layer and the photo-generated carrier transport layer form a contact. Therefore, the existing solar cell still has the defects of large contact resistance and affecting the efficiency of the solar cell. SUMMARY

[0003] Therefore, the present application provides a solar cell, a manufacturing method and a photovoltaic module, which partially or completely solve the technical problem of the existing solar cell having large contact resistance and affecting the efficiency of the solar cell.

[0004] To achieve the above-mentioned purpose, the technical scheme of the present application is as follows:

[0005] In a first aspect, the embodiments of the present application provide a solar cell, which comprises a silicon substrate, a first transport layer and a carrier collection layer. The silicon substrate has a first surface and a second surface, and the first surface and the second surface are oppositely arranged. The first transport layer is arranged on at least one of the first surface and the second surface, and the first transport layer comprises a polycrystalline silicon layer. The polycrystalline silicon layer of the first transport layer has an amorphous silicon region of the first transport layer. The amorphous silicon region of the first transport layer is located on at least part of the surface of the polycrystalline silicon layer of the first transport layer away from the silicon substrate. The carrier collection layer is arranged on the first transport layer, and at least part of the carrier collection layer is in contact with the amorphous silicon region of the first transport layer.

[0006] Optionally, the solar cell further comprises a second transport layer. The first surface of the silicon substrate is respectively provided with the first transport layer and the second transport layer, and the first transport layer and the second transport layer are arranged at intervals.

[0007] Optionally, the solar cell further comprises a second transport layer. The first surface of the silicon substrate is provided with the first transport layer, and the second surface of the silicon substrate is provided with the second transport layer.

[0008] Optionally, in the thickness direction of the solar cell, the thickness of the amorphous silicon region is 3% to 30% of the thickness of the polycrystalline silicon layer.

[0009] Optionally, the thickness of the amorphous silicon region ranges from 2 nm to 30 nm in the thickness direction of the solar cell.

[0010] Optionally, the area of the amorphous silicon region is 10% to 90% of the area of the polysilicon layer in a unit area where the carrier collection layer directly contacts the first transport layer in the thickness direction of the solar cell.

[0011] Optionally, the polysilicon layer of the first transport layer is provided with an etching region away from the surface of the silicon substrate, and the etching region is provided with the amorphous silicon region.

[0012] Optionally, the amorphous silicon region is provided with a first doping element and / or a second doping element, and the polysilicon layer is provided with a first doping element, and the doping concentration of the amorphous silicon region is greater than the doping concentration of the polysilicon layer.

[0013] Optionally, the doping concentration of the amorphous silicon region ranges from 3×10 19 atoms / cm 3 to 7×10 19 atoms / cm 3 .

[0014] Optionally, the amorphous silicon region is provided with particulate matter.

[0015] Optionally, the carrier collection layer further comprises a transparent conductive layer, and the transparent conductive layer is connected to at least part of the surface of the polysilicon layer away from the silicon substrate, at least part of the surface of the amorphous silicon region away from the silicon substrate, and at least part of the surface of the second transport layer away from the silicon substrate.

[0016] Optionally, the end portion of the first transport layer close to the second transport layer and the end portion of the second transport layer close to the first transport layer are stacked to form a stacking portion; the end portion of the first transport layer is located between the end portion of the second transport layer and the first surface; and the carrier collection layer further comprises a transparent conductive layer, and the transparent conductive layer is connected to at least part of the surface of the first transport layer away from the silicon substrate and at least part of the surface of the second transport layer away from the silicon substrate, and the transparent conductive layer has a second opening for breaking the electrical connection between the first transport layer and the second transport layer.

[0017] Optionally, the first transport layer and the second transport layer have an isolation region therebetween; the carrier collection layer further comprises a transparent conductive layer, the transparent conductive layer being connected to at least a portion of the surface of the first transport layer away from the silicon substrate and to at least a portion of the surface of the second transport layer away from the silicon substrate, the transparent conductive layer having a third opening for breaking the electrical connection between the first transport layer and the second transport layer.

[0018] Optionally, the second transport layer comprises a polysilicon layer; the polysilicon layer of the second transport layer has an amorphous silicon region of the second transport layer; the amorphous silicon region of the second transport layer is located on at least a portion of the surface of the polysilicon layer of the second transport layer away from the silicon substrate; the carrier collection layer is disposed on the second transport layer, and at least a portion of the carrier collection layer is in contact with the amorphous silicon region of the second transport layer.

[0019] Optionally, the first transport layer and the end portion of the second transport layer are laminated to form a laminated portion; the end portion of the first transport layer is located between the end portion of the second transport layer and the first surface; the second transport layer comprises a laminated structure of an intrinsic amorphous silicon region and a doped amorphous silicon region; the doped amorphous silicon region covering the end portion of the first transport layer has a hole structure.

[0020] Optionally, the width of the doped amorphous silicon region having the hole structure in the extension direction of the first surface of the silicon substrate is 0.1 um to 20 um.

[0021] Optionally, in the top view of the solar cell, the shape of the hole structure is at least one of a circle, an ellipse, and an irregular figure.

[0022] Optionally, the carrier collection layer is disposed on the first transport layer, and the carrier collection layer is in contact with all the amorphous silicon regions of the first transport layer.

[0023] Optionally, when the carrier collection layer is a laminated structure of a transparent conductive layer and a metal electrode layer, the transparent conductive layer is closer to the silicon substrate than the metal electrode layer, in the thickness direction of the solar cell, the projection of the transparent conductive layer on the surface of the silicon substrate covers all the amorphous silicon regions of the first transport layer, and the projection of the metal electrode layer on the surface of the silicon substrate covers at least a portion of the amorphous silicon regions of the first transport layer; or, when the carrier collection layer is a metal electrode layer, in the thickness direction of the solar cell, the projection of the metal electrode layer on the surface of the silicon substrate covers all the amorphous silicon regions of the first transport layer.

[0024] In a second aspect, the embodiments of the present application provide a method for manufacturing a solar cell. The method comprises the following steps: providing a silicon substrate; the silicon substrate has a first surface and a second surface, the first surface and the second surface are oppositely arranged; forming a first transport layer on at least one of the first surface and the second surface, the first transport layer comprises a polysilicon layer; forming an amorphous silicon region of the first transport layer on at least part of the surface of the polysilicon layer of the first transport layer away from the silicon substrate; forming a carrier collection layer on the first transport layer, at least part of the carrier collection layer is in contact with the amorphous silicon region of the first transport layer.

[0025] In a third aspect, the embodiments of the present application provide a photovoltaic module. The photovoltaic module comprises a cover plate, a back plate, and a solar cell arranged between the cover plate and the back plate; the solar cell comprises the solar cell as described above.

[0026] In the solar cell of the present application, at least part of the carrier collection layer is arranged on the amorphous silicon region and in contact with the amorphous silicon region. Since the difference in work function between the amorphous silicon region and the carrier collection layer is smaller than the difference in work function between the polysilicon layer and the carrier collection layer, that is, the contact potential barrier between the amorphous silicon region and the carrier collection layer is smaller than the contact potential barrier between the polysilicon layer and the carrier collection layer, the contact resistance between the amorphous silicon region and the carrier collection layer is smaller than the contact resistance between the polysilicon layer and the carrier collection layer. The amorphous silicon region can achieve more reasonable band matching, reduce the contact resistance, so that the solar cell can effectively convert sunlight into electrical energy, and improve the photoelectric conversion efficiency of the solar cell.

[0027] The above description is only a summary of the technical solutions of the present application. In order to more clearly understand the technical means of the present application, the following specific embodiments of the present application can be implemented according to the content of the description, and in order to make the above and other purposes, characteristics and advantages of the present application more obvious and easy to understand, the following specific embodiments of the present application are described. BRIEF DESCRIPTION OF DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed in the embodiment description.

[0029] FIGS. 1 to 12 show the structure schematic diagrams of a solar cell in various preparation steps in the embodiments of the present application;

[0030] FIG. 13 is an electrochemical capacitance voltage test schematic diagram of a solar cell in the embodiments of the present application;

[0031] FIG. 14 is a transmission electron microscope test image one of a solar cell in the embodiments of the present application;

[0032] Fig. 15 is a transmission electron microscope (TEM) image of a solar cell according to an embodiment of the present application;

[0033] Fig. 16 is a structural diagram of a solar cell according to an embodiment of the present application;

[0034] Fig. 17 is a structural diagram of a solar cell according to an embodiment of the present application;

[0035] Fig. 18 is a structural diagram of a solar cell according to an embodiment of the present application;

[0036] Fig. 19 is a structural diagram of a solar cell according to an embodiment of the present application.

[0037] Reference Signs: 10 - silicon substrate; 11 - first surface; 12 - second surface; 13 - first region; 14 - second region; 20 - first transport layer; 21 - first passivation layer; 22 - polysilicon layer; 24 - particle; 25 - mask; 26 - amorphous silicon region; 27 - etching region; 30 - second transport layer; 31 - second passivation layer; 32 - second doped layer; 33 - region where hole structure is located; 40 - transparent conductive layer; 50 - stack part; 61 - first electrode; 62 - second electrode; 70 - third passivation layer; 80 - anti-reflection layer; 91 - first opening; 92 - second opening. DETAILED DESCRIPTION

[0038] Exemplary embodiments of the present application will be described in detail with reference to the drawings. Although exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided so that this application will be thorough and complete, and will fully convey the scope of the application to those skilled in the art.

[0039] Referring to FIG. 1 to FIG. 12, which show the schematic diagrams of the solar cell in each preparation step according to the embodiments of the present application, the embodiments of the present application disclose a solar cell, which comprises a silicon substrate 10, a first transport layer 20, and a carrier collection layer. The silicon substrate 10 has a first surface 11 and a second surface 12, and the first surface 11 and the second surface 12 are oppositely arranged. The first transport layer 20 is arranged on at least one of the first surface 11 and the second surface 12, and the first transport layer 20 comprises a polysilicon layer 22. The polysilicon layer 22 of the first transport layer 20 has an amorphous silicon region 26 of the first transport layer 20. The amorphous silicon region 26 of the first transport layer 20 is located on at least part of the surface of the polysilicon layer 22 of the first transport layer 20, which is away from the silicon substrate 10. The carrier collection layer is arranged on the first transport layer 20, and at least part of the carrier collection layer is in contact with the amorphous silicon region 26 of the first transport layer 20.

[0040] Specifically, in the solar cell, one of the first surface 11 and the second surface 12 is the front surface of the silicon substrate 10, and the other of the first surface 11 and the second surface 12 is the back surface of the silicon substrate 10.

[0041] The first transport layer 20 is arranged on at least one of the first surface 11 and the second surface 12, which refers to the following three cases: the first case is that the first transport layer 20 is arranged on the first surface 11; the second case is that the first transport layer 20 is arranged on the second surface 12; and the third case is that the first transport layer 20 is arranged on the first surface 11 and the second surface 12.

[0042] In the embodiments of the present application, at least part of the carrier collection layer is arranged on the amorphous silicon region 26 and is in contact with the amorphous silicon region 26. Since the difference in work function between the amorphous silicon region 26 and the carrier collection layer is smaller than the difference in work function between the polysilicon layer 22 and the carrier collection layer, that is, the contact potential barrier between the amorphous silicon region 26 and the carrier collection layer is smaller than the contact potential barrier between the polysilicon layer 22 and the carrier collection layer, the contact resistance between the amorphous silicon region 26 and the carrier collection layer is smaller than the contact resistance between the polysilicon layer 22 and the carrier collection layer. The amorphous silicon region 26 can realize more reasonable energy band matching, reduce the contact resistance, so that the solar cell can effectively convert sunlight into electrical energy, and improve the photoelectric conversion efficiency of the solar cell.

[0043] Optionally, the amorphous silicon region 26 is formed by converting at least part of the surface of the polysilicon layer 22, which is away from the silicon substrate 10, into amorphous silicon after the laser-acting on the polysilicon layer 22, so as to realize the purpose of improving the photoelectric conversion efficiency of the solar cell through the amorphous silicon region 26.

[0044] Optionally, the carrier collection layer can be set according to the use requirement, for example, the carrier collection layer includes at least one of the transparent conductive layer 40 and the metal electrode layer or a combination of stacked layers.

[0045] Optionally, the metal electrode layer can be set according to the use requirement, for example, the metal electrode layer includes at least one of the conductive paste layer, the metal layer, the metal alloy layer or a combination of stacked layers.

[0046] Optionally, the metal layer can also be set according to the use requirement, for example, the metal layer includes a single layer structure formed by a single metal, a multi-layer structure with the same metal material, or a multi-layer structure with different metal materials.

[0047] Optionally, the solar cell further includes a second transport layer 30; the first surface 11 of the silicon substrate 10 is respectively provided with the first transport layer 20 and the second transport layer 30, and the first transport layer 20 and the second transport layer 30 are arranged at intervals.

[0048] In the above structure of the embodiment, the solar cell is a back contact cell (BC cell), that is, the electrode is arranged on the back surface, and the front surface is free of the electrode. The material of the second transport layer 30 in the solar cell is set according to the use requirement, for example, the second transport layer 30 includes an intrinsic amorphous silicon region and a doped amorphous silicon region, or the second transport layer 30 includes a polycrystalline silicon layer and a passivation layer.

[0049] The first surface 11 of the silicon substrate 10 is respectively provided with the first transport layer 20 and the second transport layer 30, and the first transport layer 20 and the second transport layer 30 are arranged at intervals; the interval arrangement is that, in the plane extension direction of the silicon substrate 10, that is, in the first direction A, the first transport layer 20 and the second transport layer 30 are arranged at intervals alternately on the plane of the silicon substrate 10, and the two are in contact or not in contact in the plane extension direction of the silicon substrate 10. Another is that, in the plane extension direction of the silicon substrate 10, that is, in the first direction A, the first transport layer 20 and the second transport layer 30 are arranged at intervals alternately on the plane of the silicon substrate 10, and the two partially overlap in the thickness direction (the second direction B) of the silicon substrate 10. The first transport layer 20 and the second transport layer 30 are different in type, one of the first transport layer 20 and the second transport layer 30 is an electron transport layer, and the other of the first transport layer 20 and the second transport layer 30 is a hole transport layer.

[0050] Optionally, the solar cell further includes a second transport layer 30; the first surface 11 of the silicon substrate 10 is provided with the first transport layer 20, and the second surface 12 of the silicon substrate 10 is provided with the second transport layer 30.

[0051] In the above structure of the embodiment of the present application, the solar cell is a double-sided solar cell, i.e., electrodes are arranged on both the front and back surfaces. The material of the second transport layer 30 in the solar cell is also arranged according to the use requirement, which is not limited in the embodiment of the present application.

[0052] Optionally, in the thickness direction of the solar cell, the thickness of the amorphous silicon region 26 is 3% to 30% of the thickness of the polysilicon layer 22.

[0053] Referring to FIG. 12, the thickness direction of the solar cell is the second direction B. In the case that the thickness of the amorphous silicon region 26 is 3% to 30% of the thickness of the polysilicon layer 22, the amorphous silicon region 26 can achieve more reasonable band matching and reduce the contact resistance.

[0054] In actual application, the percentage of the thickness of the amorphous silicon region 26 to the thickness of the polysilicon layer 22 is arranged according to the use requirement, for example, the thickness of the amorphous silicon region 26 is any one of 3%, 5%, 7%, 9%, 10%, 11%, 13%, 18%, 20%, 22%, 24%, 26%, 28%, and 30% of the thickness of the polysilicon layer 22.

[0055] Optionally, in the thickness direction of the solar cell, the thickness of the amorphous silicon region 26 ranges from 2 nm to 30 nm. Preferably, the thickness of the amorphous silicon region 26 ranges from 4 nm to 15 um. Further preferably, the thickness of the amorphous silicon region 26 ranges from 5 nm to 10 um. It can be understood that the thickness of the amorphous silicon region 26 in the thickness direction of the solar cell is arranged according to the use requirement, and the thickness of the amorphous silicon region 26 is related to the energy of the laser. For example, the thickness of the amorphous silicon region 26 is 2 nm, 3 nm, 4 nm, 5 nm, 7 nm, 9 nm, 10 nm, 13 nm, 15 nm, 18 nm, 20 nm, 22 nm, 24 nm, 26 nm, 28 nm, and 30 nm.

[0056] Optionally, in the unit area of the first transport layer 20 without other transport layers, the area of the amorphous silicon region 26 is 10% to 90% of the area of the polysilicon layer 22 in the thickness direction perpendicular to the solar cell. Preferably, the area of the amorphous silicon region 26 is 50% to 90% of the area of the polysilicon layer 22. Further preferably, the area of the amorphous silicon region 26 is 70% to 90% of the area of the polysilicon layer 22. In the embodiment of the present application, when the area of the amorphous silicon region 26 is in the above range of the area of the polysilicon layer 22, the amorphous silicon region 26 can effectively reduce the contact resistance, so that the solar cell can effectively convert sunlight into electrical energy, and improve the photoelectric conversion efficiency of the solar cell. The unit area is a test area, which is tested by a test instrument such as TEM. For example, the unit area can be an area with a length of 1 um and a width of 1 um, an area with a length of 500 nm and a width of 500 nm, or an area with a length of 100 nm and a width of 100 nm. The size of the unit area (test area) is not limited specifically, and can be implemented according to actual needs.

[0057] In actual application, the percentage of the area of the amorphous silicon region 26 to the area of the polysilicon layer 22 is set according to the use requirements, for example, the area of the amorphous silicon region 26 is any one of 10%, 15%, 20%, 25%, 30%, 35%, 40%, 45%, 50%, 55%, 60%, 65%, 70%, 75%, 80%, 85%, and 90% of the area of the polysilicon layer 22.

[0058] Optionally, on the first transport layer 20 and in the region for collecting the carriers generated in the first transport layer 20, the polysilicon layer 22 of the first transport layer 20 is provided with an etching region 27 away from the surface of the silicon substrate 10, and the etching region 27 is provided with the amorphous silicon region 26. The etching region 27 is formed when the polysilicon layer 22 is ablated by laser, and the etching region 27 is provided with the amorphous silicon region 26. That is, the polysilicon layer 22 of the first transport layer 20 is provided with the etching region 27 away from the surface of the silicon substrate 10, and the etching region 27 is provided with the amorphous silicon region 26, wherein the etching region 27 is arranged in the region directly contacting with the carrier collection layer in the thickness direction perpendicular to the solar cell.

[0059] Optionally, in the thickness direction perpendicular to the solar cell, the area of the amorphous silicon region 26 is 15% to 95% of the area of the etching region 27. Preferably, the area of the amorphous silicon region 26 is 50% to 95% of the area of the etching region 27. Further preferably, the area of the amorphous silicon region 26 is 85% to 95% of the area of the etching region 27. In the embodiment of the present application, when the area of the amorphous silicon region 26 is in the above range of the area of the etching region 27, the amorphous silicon region 26 can effectively reduce the contact resistance and improve the photoelectric conversion efficiency of the solar cell.

[0060] In practical applications, the area percentage of the amorphous silicon region 26 to the etching region 27 is set according to the use requirements, for example, the area percentage of the amorphous silicon region 26 to the etching region 27 is at least one of 15%, 20%, 25%, 30%, 35%, 40%, 45%, 50%, 55%, 60%, 65%, 70%, 75%, 80%, 85%, 90%, 95%.

[0061] Optionally, the area of the etching region 27 is 90% or less than 90% of the area of the polysilicon layer 22 in the direction perpendicular to the thickness direction of the solar cell. The plane where the etching region 27 is located is used to connect with the transparent conductive layer 40, and when the area of the etching region 27 is in the above range of the area of the polysilicon layer 22, the contact area requirement of the first transport layer 20 and the transparent conductive layer 40 is met.

[0062] Optionally, the plane where the etching region 27 is located is lower than or flush with the plane of the polysilicon layer 22 away from the silicon substrate 10. At this time, the etching region 27 can increase the back reflection of the front transmitted light, thereby improving the light absorption efficiency of the solar cell.

[0063] In the case where the polysilicon layer 22 is provided with the etching region 27, the plane where the etching region 27 is located is lower than the plane of the polysilicon layer 22 away from the silicon substrate 10, which can reduce the parasitic absorption of the polysilicon layer 22 and improve the light absorption efficiency. The plane where the etching region 27 is located is flush with the plane of the first transport layer 20 away from the silicon substrate 10, although it is flush, but the etching region 27 is provided with the amorphous silicon region 26, which can realize more reasonable band matching, reduce the contact resistance, and improve the photoelectric conversion efficiency of the solar cell. Therefore, the solar cell of the embodiment of the present application has the advantage of high light absorption efficiency.

[0064] Optionally, referring to FIG. 19, the plane where the etching region 27 is located has a height difference D with the plane of the polysilicon layer 22 away from the silicon substrate 10, 0nm≤D≤100nm.

[0065] In practical applications, the height difference D of the plane where the etching region 27 is located and the plane of the polysilicon layer 22 away from the silicon substrate 10 can be selected according to the use requirements, for example, D is 0nm, 1nm, 5nm, 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm.

[0066] Optionally, the amorphous silicon region 26 has the first doping element and / or the second doping element, and / or the polycrystalline silicon layer 22 has the first doping element, and the doping concentration of the doping element of the amorphous silicon region 26 is greater than the doping concentration of the doping element of the polycrystalline silicon layer 22. Referring to FIG. 13, the doping concentration of the amorphous silicon region 26 of the first transport layer 20 is greater than the doping concentration of the polycrystalline silicon layer 22, i.e., the doping concentration of the amorphous silicon region 26 formed by laser processing the polycrystalline silicon layer 22 on the first transport layer 20 is greater than the doping concentration of the polycrystalline silicon layer 22 on the first transport layer 20 without laser processing. For example, when the depth is 15 nm, the doping concentration of the amorphous silicon region 26 is 6.5×10 19 atoms / cm 3 greater than the doping concentration 4×10 19 atoms / cm 3 of the polycrystalline silicon layer 22. For another example, when the depth is 30 nm, the doping concentration of the amorphous silicon region 26 is 5.5×10 19 atoms / cm 3 greater than the doping concentration 4×10 19 atoms / cm 3 of the polycrystalline silicon layer 22.

[0067] In the embodiments of the present application, the doping concentration of the amorphous silicon region 26 is greater than the doping concentration of the polycrystalline silicon layer 22, which can improve the doping concentration of the surface of the first transport layer 20 to reduce the contact resistance.

[0068] One of the first doping element and the second doping element includes at least one of nitrogen, phosphorus, arsenic, antimony, etc., and the other of the first doping element and the second doping element includes at least one of boron, aluminum, gallium, indium, etc. When the first doping element includes at least one of nitrogen, phosphorus, arsenic, antimony, etc., the polycrystalline silicon layer 22 is an N-type doped layer. In some solar cells, for example, cells with aluminum oxide and / or silicon nitride as a passivation layer, after the laser forms the carrier collection layer contact opening on the second transport layer 30, the second doping element remains, so that the amorphous silicon region 26 has the second doping element.

[0069] Optionally, the doping concentration of the amorphous silicon region 26 ranges from 3×10 19 atoms / cm 3 to 7×10 19 atoms / cm 3 .

[0070] In actual applications, the doping concentration of the amorphous silicon region 26 is set according to the use requirements, for example, the doping concentration of the amorphous silicon region 26 is 3×10 19 atoms / cm 3 , 3.2×10 19 atoms / cm 33.4 x 10 19 atoms / cm 3 3.6 x 10 19 atoms / cm 3 3.8 x 10 19 atoms / cm 3 4 x 10 19 atoms / cm 3 4.2 x 10 19 atoms / cm 3 4.4 x 10 19 atoms / cm 3 4.6 x 10 19 atoms / cm 3 4.8 x 10 19 atoms / cm 3 5 x 10 19 atoms / cm 3 5.2 x 10 19 atoms / cm 3 5.4 x 10 19 atoms / cm 3 5.6 x 10 19 atoms / cm 3 5.8 x 10 19 atoms / cm 3 6 x 10 19 atoms / cm 3 6.2 x 10 19 atoms / cm 3 6.4 x 10 19 atoms / cm 3 6.6 x 10 19 atoms / cm 3 6.8 x 10 19 atoms / cm 3 7 x 10 19 atoms / cm 3 .

[0071] Optionally, the amorphous silicon region 26 is provided with the particulate matter 24. In the embodiment of the present application, the provision of the particulate matter 24 can increase the back reflection of the front transmitted light, thereby improving the light absorption efficiency of the solar cell.

[0072] The particulate matter 24 is formed by laser treatment.

[0073] Optionally, the maximum length of the particle 24 is less than 50 nm in the top view of the solar cell; preferably, the maximum length of the particle 24 is less than 20 nm; further preferably, the maximum length of the particle 24 is less than 15 nm; further preferably, the maximum length of the particle 24 ranges from 5 nm to 10 nm. When the size of the particle 24 is in the above range, the particle 24 can increase the back reflection of the front transmitted light, thereby improving the light absorption efficiency.

[0074] Further, the maximum length of the particle 24 is less than 50 nm, and the light refraction effect is good. Further, the maximum length of the particle 24 is less than 20 nm, and the light refraction effect is good, and the contact resistance effect is better than that of the particle 24 with the maximum length less than 50 nm. Further, the maximum length of the particle 24 ranges from 5 nm to 10 nm, and the light refraction effect and the contact resistance effect are optimal.

[0075] Further, in the top view of the solar cell, the application does not specifically limit the maximum length of the particle 24, for example, the maximum length of the particle 24 is 5 nm, 5.5 nm, 6 nm, 6.5 nm, 7 nm, 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 15 nm, 16 nm, 17 nm, 18 nm, 19 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, etc.

[0076] Optionally, the amorphous silicon region 26 has a plurality of particles 24; and the area coverage of the particles 24 on the amorphous silicon region 26 ranges from 0.01% to 60% in the direction perpendicular to the thickness of the solar cell. When the area coverage of the particles 24 on the amorphous silicon region 26 is in the above range, the particles 24 can increase the back reflection of the front transmitted light, thereby improving the light absorption efficiency of the solar cell.

[0077] Optionally, the particle 24 includes a silicon element; or the particle 24 includes a silicon element and a second doping element, wherein the type of the second doping element included in the particle 24 is different from the type of the first doping element in the polysilicon layer 22.

[0078] In the application, the laser etching forms the particle 24, and the particle 24 includes a silicon element. Alternatively, the particle 24 includes a silicon element and a second doping element, and the second doping element is at least one of the group V elements. The group V elements include nitrogen, phosphorus, arsenic, antimony, etc. At this time, the first doping element in the polysilicon layer 22 is at least one of the group III elements, and the group III elements include boron, aluminum, gallium, indium, etc. For example, the doping element included in the particle 24 is boron, and the doping element in the polysilicon layer 22 where the particle 24 is located is phosphorus.

[0079] Optionally, the particle 24 comprises molten silicon particles. The particle 24 comprises molten silicon particles including silicon element after the laser ablation of the second doped layer 32 of the second transport layer 30; or the particle 24 comprises molten silicon particles including silicon element and the second doped element.

[0080] Optionally, the particle 24 has at least one of a circular shape, an elliptical shape, and an irregular shape in a top view of the solar cell.

[0081] Further referring to FIG. 17, a structure diagram of the particle 24 having a circular shape is shown. Referring to FIG. 18, a structure diagram of the particle 24 having an elliptical shape is shown.

[0082] Optionally, the particle 24 is embedded in the amorphous silicon region 26; and / or, the particle 24 is embedded in the polysilicon layer 22; and / or, a part of the particle 24 is embedded in the amorphous silicon region 26 and the rest of the particle 24 is embedded in the polysilicon layer 22; and the particle 24 is embedded in the amorphous silicon region 26 at a depth range of 0nm to 200nm away from a plane where a surface of the silicon substrate 10 is located.

[0083] In the embodiments of the present application, the depth of the particle 24 embedded in the amorphous silicon region 26 away from the plane where the surface of the silicon substrate 10 is located is set according to the use requirement, for example, the particle 24 is embedded at a depth of 0nm, 5nm, 10nm, 40nm, 50nm, 80nm, 100nm, 135nm, 150nm, 160nm, 180nm, 200nm.

[0084] Optionally, 10% to 100% of the particle 24 is embedded in the amorphous silicon region 26 away from the plane where the surface of the silicon substrate 10 is located in the thickness direction of the solar cell.

[0085] In the embodiments of the present application, further referring to Fig. 16, from top to bottom, in the first graph, 10% of the particles 24 are buried in the amorphous silicon region 26 away from the plane where the surface of the silicon substrate 10 is located; in the second graph, 25% of the particles 24 are buried in the amorphous silicon region 26 away from the plane where the surface of the silicon substrate 10 is located; in the third graph, 50% of the particles 24 are buried in the amorphous silicon region 26 away from the plane where the surface of the silicon substrate 10 is located; in the fourth graph, 75% of the particles 24 are buried in the amorphous silicon region 26 away from the plane where the surface of the silicon substrate 10 is located; in the fifth graph, 100% of the particles 24 are buried in the amorphous silicon region 26 away from the plane where the surface of the silicon substrate 10 is located; in the sixth graph, all of the particles 24 are buried in the amorphous silicon region 26 away from the plane where the surface of the silicon substrate 10 is located. When 10% to 100% of the particles 24 are buried in the amorphous silicon region 26 away from the plane where the surface of the silicon substrate 10 is located, the particles 24 are buried in the amorphous silicon region 26; or the particles 24 are buried in the polysilicon layer 22; or part of the particles 24 are buried in the amorphous silicon region 26 and the rest are buried in the polysilicon layer 22.

[0086] Optionally, the carrier collection layer further comprises a transparent conductive layer 40, which is connected to at least part of the surface of the polysilicon layer 22 away from the silicon substrate 10, at least part of the surface of the amorphous silicon region 26 away from the silicon substrate 10, and at least part of the surface of the second transport layer 30 away from the silicon substrate 10.

[0087] The transparent conductive layer 40 can fully cover and connect the surface of the polysilicon layer 22 away from the silicon substrate 10, i.e. the amorphous silicon region 26 in the polysilicon layer 22 is also covered and connected by the transparent conductive layer 40; in addition, the transparent conductive layer 40 can also fully cover and connect the surface of the second transport layer 30 away from the silicon substrate 10.

[0088] The transparent conductive layer 40 can also cover and connect part of the surface of the polysilicon layer 22 away from the silicon substrate 10, and part of the surface of the amorphous silicon region 26 away from the silicon substrate 10; in addition, the transparent conductive layer 40 can also cover and connect part of the surface of the second transport layer 30 away from the silicon substrate 10.

[0089] The transparent conductive layer 40 (TCO, Transparent Conductive Oxide) has good transparency and conductivity. The transparent conductive layer 40 directly faces the sunlight, and the main role of the transparent conductive layer 40 is to allow sunlight to pass through and enter the inside of the cell, while providing a good photo-generated carrier collection layer.

[0090] In the embodiment of the present application, the transparent conductive layer 40 is connected to the part of the surface of the amorphous silicon region 26 away from the silicon substrate 10. Since the difference in work function between the amorphous silicon region 26 and the transparent conductive layer 40 is smaller than the difference in work function between the polycrystalline silicon layer 22 and the transparent conductive layer 40, i.e. the contact potential barrier between the amorphous silicon region 26 and the transparent conductive layer 40 is smaller than the contact potential barrier between the polycrystalline silicon layer 22 and the transparent conductive layer 40, the contact resistance between the transparent conductive layer 40 and the amorphous silicon region 26 is smaller than the contact resistance between the transparent conductive layer 40 and the polycrystalline silicon layer 22, the contact resistance can be reduced, and the photoelectric conversion efficiency of the solar cell can be effectively improved.

[0091] Moreover, when the transparent conductive layer 40 is deposited by magnetron sputtering, the amorphous silicon region 26 can improve the ability of the first transport layer 20 to resist damage caused by magnetron sputtering bombardment, avoid damage to the polycrystalline silicon layer 22 caused by magnetron sputtering, and avoid the influence of damage caused by magnetron sputtering bombardment on the photoelectric conversion efficiency of the solar cell.

[0092] Optionally, the end part of the first transport layer 20 close to the second transport layer 30 is arranged in a stacked manner with the end part of the second transport layer 30 close to the first transport layer 20 to form a stacked portion 50; the end part of the first transport layer 20 is located between the opposite end part of the second transport layer 30 and the first surface 11; the carrier collection layer further comprises a transparent conductive layer 40, the transparent conductive layer 40 is connected to at least part of the surface of the first transport layer 20 away from the silicon substrate 10 and at least part of the surface of the second transport layer 30 away from the silicon substrate 10, and the transparent conductive layer 40 has a second opening 92 for breaking the electrical connection between the first transport layer 20 and the second transport layer 30.

[0093] The second opening 92 makes the N region and the P region not connected, and the second opening 92 can be used for insulation of the N region and the P region, and has the advantages of good insulation reliability and insulation effect.

[0094] Optionally, the first transport layer 20 and the second transport layer 30 have an isolation region therebetween, and the carrier collection layer further comprises a transparent conductive layer 40, the transparent conductive layer 40 is connected to at least part of the surface of the first transport layer 20 away from the silicon substrate 10 and at least part of the surface of the second transport layer 30 away from the silicon substrate 10, and the transparent conductive layer 40 has a third opening for breaking the electrical connection between the first transport layer 20 and the second transport layer 30. In the above structure of the present application, the third opening also makes the N region and the P region insulated, and has the advantages of good insulation reliability and insulation effect.

[0095] Optionally, the second transport layer 30 comprises a polysilicon layer; the polysilicon layer of the second transport layer 30 has an amorphous silicon region of the second transport layer 30; the amorphous silicon region of the second transport layer 30 is located on at least part of the surface of the polysilicon layer of the second transport layer 30 away from the silicon substrate 10; and the carrier collection layer is arranged on the second transport layer 30, and at least part of the carrier collection layer is in contact with the amorphous silicon region of the second transport layer 30.

[0096] In the embodiments of the present application, the amorphous silicon region of the first transport layer 20 and the amorphous silicon region of the second transport layer 30 are respectively in contact with the carrier collection layer. Since the difference in work function between the amorphous silicon region 26 and the carrier collection layer is smaller than the difference in work function between the polysilicon layer 22 and the carrier collection layer, that is, the contact barrier between the amorphous silicon region 26 and the carrier collection layer is smaller than the contact barrier between the polysilicon layer 22 and the carrier collection layer, the contact resistance between the amorphous silicon region 26 and the carrier collection layer is smaller than the contact resistance between the polysilicon layer 22 and the carrier collection layer. The amorphous silicon region 26 can achieve more reasonable band matching and reduce the contact resistance, so that the solar cell can effectively convert sunlight into electrical energy and improve the photoelectric conversion efficiency of the solar cell.

[0097] Optionally, the end portion of the first transport layer 20 close to the second transport layer 30 is arranged in a stack with the end portion of the second transport layer 30 close to the first transport layer 20 to form a stacked portion 50; the end portion of the first transport layer 20 is located between the end portion of the second transport layer 30 and the first surface 11; the second transport layer 30 comprises a stack of an intrinsic amorphous silicon region and a doped amorphous silicon region; and the doped amorphous silicon region covering the end portion of the first transport layer 20 has a hole structure.

[0098] In the embodiments of the present application, after the laser acts on the polysilicon layer 22, the doped amorphous silicon region in the heat-affected zone of the laser will be affected by heat to generate holes, and the hole structure of different sizes will be generated inside the doped amorphous silicon region. The hole structure leads to loose structure, enhances the insulation between the polysilicon layer 22 and the doped amorphous silicon region, and thus can reduce the leakage.

[0099] Optionally, the width of the doped amorphous silicon region with the hole structure in the extension direction of the first surface 11 of the silicon substrate 10 is 0.1 um to 20 um (see FIG. 9, which shows a schematic diagram of the region 33 where the hole structure of the doped amorphous silicon region is located). When the width in the embodiments of the present application is in the above range, the electron flow between the first transport layer 20 and the doped amorphous silicon region can be effectively reduced, thereby reducing the leakage.

[0100] It can be understood that the range of the doped amorphous silicon region with the hole structure is set according to the use requirement, for example, the width is 0.1 um, 0.3 um, 0.5 um, 0.7 um, 0.9 um, 1 um, 2 um, 3 um, 5 um, 7 um, 9 um, 10 um, 12 um, 14 um, 15 um, 17 um, 18 um, 20 um.

[0101] Optionally, in the top view of the solar cell, the shape of the hole structure is at least one of a circle, an ellipse, and an irregular figure. When the shape of the hole structure is at least one of a circle, an ellipse, and an irregular figure, the hole structure can enhance insulation and reduce electric leakage.

[0102] Optionally, the carrier collection layer is arranged on the first transport layer 20, and the carrier collection layer is in contact with all the amorphous silicon regions 26 of the first transport layer 20. The carriers in all the amorphous silicon regions 26 can be directly and longitudinally led out through the carrier collection layer, reducing the lateral transmission path of the carriers on the carrier collection layer, reducing the transmission resistance, and improving the current transmission efficiency.

[0103] Optionally, when the carrier collection layer is a transparent conductive layer 40 and a metal electrode layer is laminated, the transparent conductive layer 40 is closer to the silicon substrate 10 than the metal electrode layer, in the thickness direction of the solar cell, the projection of the transparent conductive layer 40 on the surface of the silicon substrate 10 covers all the amorphous silicon regions 26 of the first transport layer 20, and the projection of the metal electrode layer on the surface of the silicon substrate 10 covers at least part of the amorphous silicon regions 26 of the first transport layer 20; or, when the carrier collection layer is a metal electrode layer, in the thickness direction of the solar cell, the projection of the metal electrode layer on the surface of the silicon substrate 10 covers all the amorphous silicon regions 26 of the first transport layer 20.

[0104] Optionally, when the carrier collection layer is a transparent conductive layer 40 and a metal electrode layer is laminated, the transparent conductive layer 40 is closer to the silicon substrate 10; in the thickness direction of the solar cell, the projection of the metal electrode layer on the surface of the silicon substrate 10 covers at least part of the amorphous silicon regions 26 of the first transport layer 20; or, in the thickness direction of the solar cell, the projection of the metal electrode layer on the surface of the silicon substrate 10 covers all the amorphous silicon regions 26 of the first transport layer 20. Or, in the thickness direction of the solar cell, the projection of the transparent conductive layer 40 on the surface of the silicon substrate 10 covers at least part of the amorphous silicon regions 26 of the first transport layer 20; or, in the thickness direction of the solar cell, the projection of the transparent conductive layer 40 on the surface of the silicon substrate 10 covers all the amorphous silicon regions 26 of the first transport layer 20.

[0105] In the embodiment of the present application, in the case that the projection of the metal electrode layer on the surface of the silicon substrate 10 covers at least part of the amorphous silicon region 26 of the first transport layer 20, the carriers in the amorphous silicon region can be directly longitudinally transmitted through the transparent conductive layer 40 and then through the metal electrode layer, reducing the horizontal transmission path of the carriers on the transparent conductive layer 40, reducing the transmission resistance, and improving the current transmission efficiency.

[0106] Further, in the case that the projection of the metal electrode layer on the surface of the silicon substrate 10 covers all the amorphous silicon region 26 of the first transport layer 20, the metal electrode layer covers all the amorphous silicon region, which can further reduce the transmission path of the carriers in the amorphous silicon region.

[0107] Optionally, the metal electrode layer includes at least one of or a combination of a conductive paste layer, a metal layer, and a metal alloy layer. The metal layer can also be set according to the use requirements, for example, the metal layer includes a single metal layer structure, a multi-layer structure with the same metal material, or a multi-layer structure with different metal materials.

[0108] Optionally, referring to FIGS. 1 to 12, the solar cell further includes a first electrode 61 and a second electrode 62. The transparent conductive layer 40 located at the surface of the first transport layer 20 away from the silicon substrate 10 is provided with the first electrode 61, and the transparent conductive layer 40 located at the surface of the second transport layer 30 away from the silicon substrate 10 is provided with the second electrode 62. The first electrode 61 and the transparent conductive layer 40 together form a carrier collection layer of the first transport layer 20. The second electrode 62 and the transparent conductive layer 40 together form a carrier collection layer of the second transport layer 30. At this time, the carriers in the amorphous silicon region on the first transport layer 20 can be directly longitudinally transmitted through the transparent conductive layer 40 and then through the first electrode 61, reducing the horizontal transmission path of the carriers on the transparent conductive layer 40, reducing the transmission resistance, and improving the current transmission efficiency.

[0109] Further, in the case that the projection of the metal electrode layer on the surface of the silicon substrate 10 covers all the amorphous silicon region 26 of the first transport layer 20, the metal electrode layer covers all the amorphous silicon region, which can further reduce the transmission path of the carriers in the amorphous silicon region.

[0110] Further, referring to FIGS. 9 and 12, the first electrode 61 and the second electrode 62 are arranged parallel to the extension direction of the laminated portion 50 and are arranged in a spaced manner in the first direction A.

[0111] Optionally, referring to FIGS. 1 to 12, the solar cell further includes an anti-reflection layer 80 and a third passivation layer 70, which are sequentially laminated on the second surface 12 of the solar cell.

[0112] In the solar cell of the embodiment of the present application, the first transport layer 20 comprises a polycrystalline silicon layer 22 and an amorphous silicon region 26 arranged in a stack; the polycrystalline silicon layer 22 is arranged on the first surface 11 of the silicon substrate 10; the amorphous silicon region 26 is arranged on at least part of the surface of the polycrystalline silicon layer 22 away from the silicon substrate 10, and the amorphous silicon region 26 is formed by laser; the laser forms the amorphous silicon region 26 on at least part of the surface of the polycrystalline silicon layer 22 away from the silicon substrate 10. Since the difference in work function between the amorphous silicon region 26 and the carrier collection layer is smaller than the difference in work function between the polycrystalline silicon layer and the carrier collection layer, i.e., the contact potential barrier between the amorphous silicon region and the carrier collection layer is smaller than the contact potential barrier between the polycrystalline silicon layer and the carrier collection layer, the contact resistance between the amorphous silicon region 26 and the carrier collection layer is smaller than the contact resistance between the polycrystalline silicon layer 22 and the carrier collection layer, the amorphous silicon region 26 can achieve more reasonable band matching, reduce the contact resistance, so that the solar cell can effectively convert sunlight into electrical energy, and the photoelectric conversion efficiency of the solar cell is improved.

[0113] Further, in the solar cell, the advantages of the crystalline silicon-amorphous silicon heterojunction contact are good passivation performance and high open circuit voltage, and it is suitable to be used as the emitter of the solar cell, i.e., the P region. The advantage of the tunneling oxide passivation contact is lower contact resistance, and it is suitable to be used as the back field of the solar cell, i.e., the N region. Therefore, the hybrid solar cell using the crystalline silicon-amorphous silicon heterojunction contact and the tunneling oxide passivation contact has higher potential in photoelectric conversion efficiency. The P region can be understood as an amorphous layer containing boron doping, and the N region can be understood as a polycrystalline layer containing phosphorus doping; when the P region uses the crystalline silicon-amorphous silicon heterojunction contact, a transparent conductive layer 40 (for example, an indium tin oxide material layer, and the transparent conductive layer 40 is a photo-generated carrier collection layer) is generally deposited on the surface of the P region and the N region away from the silicon substrate 10, the transparent conductive layer 40 is in contact with the amorphous silicon region 26 of the N region, which can reduce the contact resistance of the N region from multiple aspects. First, the doping concentration of the doping element of the amorphous silicon region of the N region is greater than the doping concentration of the doping element of the polycrystalline silicon layer of the N region, because the doping concentration is improved, the contact resistance between the transparent conductive layer 40 and the N region is reduced. Second, the polycrystalline silicon layer of the N region has the amorphous silicon region, because the band matching between the transparent conductive layer and the amorphous is more reasonable than the band matching between the transparent conductive layer and the polycrystalline (specifically, since the difference in work function between the amorphous silicon region and the transparent conductive layer is smaller than the difference in work function between the polycrystalline silicon layer and the transparent conductive layer, i.e., the contact potential barrier between the amorphous silicon region and the transparent conductive layer is smaller than the contact potential barrier between the polycrystalline silicon layer and the transparent conductive layer, so that the band matching between the transparent conductive layer and the amorphous is more reasonable than the band matching between the transparent conductive layer and the polycrystalline). Moreover, the transparent conductive layer 40 avoids damaging the polycrystalline silicon layer 22 on the N region by using a magnetron sputtering deposition method. Therefore, the solar cell has the advantage of high photoelectric conversion efficiency.

[0114] The application also provides a manufacturing method of a solar cell, comprising the following steps and referring to FIG. 1 to FIG. 12:

[0115] S01, providing a silicon substrate 10, the silicon substrate 10 has a first surface 11 and a second surface 12, the first surface 11 and the second surface 12 are oppositely arranged.

[0116] In this step, the provided silicon substrate 10 needs to be polished and cleaned, the cutting damage layer of the first surface 11 and the second surface 12 of the silicon substrate 10 is removed, and the polishing morphology of the first surface 11 and the second surface 12 is controlled by controlling the temperature, time and drug concentration of the polishing and cleaning.

[0117] S02, forming a first transport layer 20 on at least one of the first surface 11 and the second surface 12, the first transport layer 20 comprising a polysilicon layer 22.

[0118] In this step, the first transport layer 20 and the second transport layer 30 are arranged on the first surface 11, the end part of the first transport layer 20 close to the second transport layer 30 is laminated with the end part of the second transport layer 30 close to the first transport layer 20 to form a laminated part 50; the end part of the first transport layer 20 is located between the end part of the second transport layer 30 and the first surface 11, and the polysilicon layer 22 is connected with the end part of the second transport layer 30.

[0119] S03, forming an amorphous silicon region of the first transport layer on at least part of the surface of the polysilicon layer of the first transport layer away from the silicon substrate.

[0120] In this step, part of the second transport layer 30 on the polysilicon layer 22 is selectively removed by laser treatment to form a first opening 91, the polysilicon at the first opening 91 is treated by laser, so that the surface layer polysilicon is converted into amorphous silicon to form an amorphous silicon region 26. The laser used in the laser treatment is a picosecond laser.

[0121] S04, forming a carrier collection layer on the first transport layer, at least part of the carrier collection layer is in contact with the amorphous silicon region of the first transport layer.

[0122] Further, in this embodiment, the carrier collection layer is a transparent conductive layer 40.

[0123] The solar cell manufactured by the manufacturing method of the solar cell has a smaller contact resistance between the amorphous silicon region 26 and the carrier collection layer than the contact resistance between the polycrystalline silicon layer 22 and the carrier collection layer, and the amorphous silicon region 26 can achieve a more reasonable energy band matching and reduce the contact resistance, so that the solar cell can effectively convert sunlight into electrical energy and improve the photoelectric conversion efficiency of the solar cell.

[0124] The application further provides a photovoltaic module, which comprises a cover plate, a back plate, and a solar cell arranged between the cover plate and the back plate; the solar cell comprises the solar cell as described above.

[0125] The application does not specifically limit whether the photovoltaic module further comprises other structures. For example, the photovoltaic module can further comprise a first encapsulating adhesive film arranged between the cover plate and the solar cell, and a second encapsulating adhesive film arranged between the back plate and the solar cell.

[0126] In the photovoltaic module, the first transport layer 20 of the solar cell comprises a polycrystalline silicon layer 22 and an amorphous silicon region 26 arranged in a stack; the polycrystalline silicon layer 22 is arranged on the first surface 11 of the silicon substrate 10; the amorphous silicon region 26 is located on at least part of the surface of the polycrystalline silicon layer 22 away from the silicon substrate 10, and the amorphous silicon region 26 is formed by laser; the laser forms the amorphous silicon region 26 on at least part of the surface of the polycrystalline silicon layer 22 away from the silicon substrate 10. Since the contact resistance between the amorphous silicon region 26 and the transparent conductive layer 40 is smaller than the contact resistance between the polycrystalline silicon layer 22 and the transparent conductive layer 40, the amorphous silicon region 26 can achieve a more reasonable energy band matching and reduce the contact resistance, so that the solar cell can effectively convert sunlight into electrical energy and improve the photoelectric conversion efficiency of the solar cell.

[0127] The application will be further described in detail in combination with specific embodiments.

[0128] Embodiment one

[0129] The preparation process of the solar cell is shown in FIGS. 1 to 12, and the preparation process comprises the following steps:

[0130] Step 101, as shown in FIG. 1, polish and clean the silicon substrate 10.

[0131] In this step, the silicon substrate 10 is put into a polishing cleaning machine such as a slot polishing cleaning machine to polish and clean the silicon substrate 10, so as to remove the cutting damage layer of the first surface 11 and the second surface 12 of the silicon substrate 10, and to realize the control of the polishing topography of the first surface 11 and the second surface 12 by controlling the temperature, time and chemical liquid concentration of the polishing and cleaning.

[0132] Step 102, as shown in FIG. 2, the first transport layer 20 is formed on the first surface 11 and the second surface 12 of the silicon substrate 10.

[0133] In this step, the first transport layer 20 is the first passivation layer 21 and the polysilicon layer 22 arranged in a stack, the first passivation layer 21 is connected to the first surface 11 and the polysilicon layer 22, or the first passivation layer 21 is connected to the second surface 12 and the polysilicon layer 22.

[0134] Specifically, a low pressure chemical vapor deposition (LPCVD) equipment can be used to sequentially deposit the first passivation layer 21 and the polysilicon layer 22 on the first surface 11, and sequentially deposit the first passivation layer 21 and the polysilicon layer 22 on the second surface 12. Wherein, the silicon substrate 10 is an N-type silicon substrate, the first passivation layer 21 includes a silicon oxide layer, and the thickness of the silicon oxide layer ranges from 1.4 nm. The polysilicon layer 22 is an intrinsic semiconductor material layer, and the thickness of the polysilicon layer 22 ranges from 150 nm.

[0135] Wherein, in this step, the LPCVD equipment deposition can form the first transport layer 20 on the first surface 11 and the second surface 12 respectively, and the first transport layer 20 on the first surface 11 and the first transport layer 20 on the second surface 12 are symmetrically arranged. The LPCVD equipment deposition can also form the first transport layer 20 only on the first surface 11.

[0136] Step 103, as shown in FIG. 3, the polysilicon layer 22 on the first surface 11 is doped.

[0137] In this step, the polysilicon layer 22 on the first surface 11 is doped with phosphorus by high-temperature diffusion, so that the part of the polysilicon layer 22 on the first surface 11 corresponding to the first region 13 (see FIG. 5) forms a first doped part, and the part corresponding to the second region 14 (see FIG. 5) forms a second doped part. Then, a phosphosilicate glass layer formed after phosphorus diffusion is removed by using a wet etching process and a hydrogen fluoride solution (HF solution). In this step, the change of the polysilicon layer 22 on the second surface 12 can be ignored. After the polysilicon layer 22 on the first surface 11 is doped, an N region is formed.

[0138] Step 104, as shown in FIG. 4, a mask is formed on the surface of the polysilicon layer 22 away from the silicon substrate 10.

[0139] In this step, a first silicon nitride material layer is deposited on the polysilicon layer 22 on the first surface 11 as a mask 25, away from the surface of the silicon substrate 10. The first silicon nitride material layer is formed by a plasma chemical vapor deposition process, and the thickness of the first silicon nitride material layer is 60 nm.

[0140] Step 105, as shown in FIG. 5, the mask on the first region 13 on the first surface 11 is removed.

[0141] In this step, the first silicon nitride material layer on the first region 13 on the first surface 11 is selectively removed by laser treatment. The laser used in the laser treatment is a 532 nm picosecond laser.

[0142] Step 106, as shown in FIG. 6, the first region 13 on the first surface 11 and the second surface 12 are respectively textured.

[0143] In this step, under the action of the first silicon nitride material layer, the first region 13 on the first surface 11 and the second surface 12 of the silicon substrate 10 are textured, and the first region 13 on the first surface 11 and the second surface 12 are textured to improve the solar energy absorption efficiency of the solar cell. Then, the first silicon nitride material layer is removed by using a hydrofluoric acid solution.

[0144] Step 107, as shown in FIG. 7, a second transport layer 30 is formed on the first surface 11 of the silicon substrate 10.

[0145] In this step, a second transport layer 30 is formed on the first surface 11 of the silicon substrate 10. The second transport layer 30 includes a second passivation layer 31 and a second doped layer 32 arranged in a stack, and the second passivation layer 31 is connected between the first surface 11 and the second doped layer 32.

[0146] Specifically, a chemical vapor deposition (CVD, Chemical Vapor Deposition Equipment) device can be used to sequentially deposit the second passivation layer 31 and the second doped layer 32. The second passivation layer 31 includes an intrinsic amorphous silicon region, and the second doped layer 32 includes a P-type amorphous silicon region, and the thickness of the second doped layer 32 is 15 nm.

[0147] Step 108, as shown in FIG. 8, a third passivation layer 70 and an anti-reflection layer 80 are formed on the second surface 12 of the silicon substrate 10.

[0148] In this step, a third passivation layer 70 is deposited on the second surface 12 of the silicon substrate 10 by using a CVD device, the third passivation layer 70 is a layer of intrinsic amorphous silicon material, the thickness of the third passivation layer 70 ranges from 5 nm. A reflection-reducing layer 80 is deposited on the surface of the third passivation layer 70 facing away from the silicon substrate 10, the reflection-reducing layer 80 is a layer of second silicon nitride material, the thickness of the second silicon nitride material layer is 70 nm.

[0149] Step 109, as shown in FIG. 9, the second passivation layer 31 and the second doped layer 32 in the second region 14 of the silicon substrate 10 are removed by using a laser.

[0150] In this step, most or all of the second doped layer 32 and the second passivation layer 31 in the second region 14 of the first surface 11 of the silicon substrate 10 are selectively removed by using a laser treatment to form a first opening 91, the polycrystalline silicon layer 22 in the first opening 91 is treated by the laser, the surface layer polycrystalline silicon is converted into amorphous silicon to form an amorphous silicon region 26, the thickness of the amorphous silicon region 26 is 3% to 30% of the thickness of the polycrystalline silicon layer 22. The laser used in the laser treatment is a 532 nm picosecond laser.

[0151] In this step, when the second doped layer 32 and the second passivation layer 31 in the second region 14 of the first surface 11 of the silicon substrate 10 are selectively removed by laser treatment, the particulate matter 24 remaining on the amorphous silicon region 26 can increase the back reflection of the front transmitted light.

[0152] Step 110, as shown in FIG. 10, a transparent conductive layer 40 is deposited on the side of the silicon substrate 10 provided with the first surface 11.

[0153] In this step, the transparent conductive layer 40 is deposited on the side of the silicon substrate 10 provided with the first surface 11 by using a magnetron sputtering method, the thickness of the transparent conductive layer 40 ranges from 20 nm to 100 nm.

[0154] Referring to FIGS. 14 and 15, test images of the finished solar cell are shown, in which the surface of the polycrystalline silicon layer 22 has an amorphous silicon region 26.

[0155] Step 111, as shown in FIG. 11, at least part of the transparent conductive layer 40 is removed to form a second opening 92.

[0156] In this step, part of the transparent conductive layer 40 between the P region and the N region is removed to form a second opening 92, the second opening 92 completely insulates the P region and the N region. The method of removing part of the transparent conductive layer 40 between the P region and the N region includes at least one of laser ablation, photolithography, and printing of a corrosive paste.

[0157] Step 112, as shown in Fig. 12, a first electrode 61 is prepared on the transparent conductive layer 40 corresponding to the N region by screen printing, and a second electrode 62 is prepared on the transparent conductive layer 40 corresponding to the P region by screen printing.

[0158] In the embodiment, the first electrode 61 and the second electrode 62 are both metal electrodes, for example, the material of the first electrode 61 and the second electrode 62 both includes silver.

[0159] In this step, the low-temperature silver paste is printed on the surface of the N region and the surface of the P region by screen printing, and then cured at 200°C for 30 minutes to form the first electrode 61 and the second electrode 62.

[0160] Example 2

[0161] The difference between the example 2 and the example 1 is that the energy of the laser is different, and the rest is the same as the example 1.

[0162] Comparative Example

[0163] The difference between the comparative example and the example 1 is that there is no amorphous silicon region 26 on the polysilicon layer 22, and the rest is the same as the example 1.

[0164] The performance test is carried out on 1000 solar cells formed in the example 1 and 1000 solar cells formed in the comparative example under the same test conditions, and the test results are shown in Table 1 below.

[0165] Table 1

[0166] In Table 1, the data of the example 1 is the arithmetic mean of the test results of the 1000 solar cells corresponding to the example 1, and the data of the comparative example is the arithmetic mean of the test results of the 1000 solar cells corresponding to the comparative example. In Table 1, J sc The short-circuit current density of the solar cell is represented by V oc The open-circuit voltage of the solar cell is represented by FF, the fill factor of the solar cell is represented by FF, and the photoelectric conversion efficiency of the solar cell is represented by Eff. From the above Table 1, it can be seen that the photoelectric conversion efficiency of the example 1 is higher than that of the comparative example. The main reason is that in the example 1, the laser processing forms an amorphous silicon region 26 on at least part of the surface of the polysilicon layer 22 away from the silicon substrate 10. The amorphous silicon region 26 can reduce the contact resistance between the transparent conductive layer 40 and the polysilicon layer 22, improve the FF, and avoid the damage to the polysilicon layer 22 during the magnetron sputtering deposition of the transparent conductive layer 40, thereby improving the V oc , which is conducive to improving the conversion efficiency of the solar cell.

[0167] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0168] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. For embodiments of devices, electronic devices, computer-readable storage media, and computer program products containing instructions, the descriptions are relatively simple because they are basically similar to the method embodiments; relevant parts can be referred to the descriptions of the method embodiments.

[0169] The above are merely preferred embodiments of this application and are not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application are included within the scope of protection of this application.

Claims

A solar cell characterized by comprising: The solar cell comprises a silicon substrate, a first transport layer, and a carrier collection layer; the silicon substrate has a first surface and a second surface, and the first surface and the second surface are oppositely arranged; The first transport layer is arranged on at least one of the first surface and the second surface, and the first transport layer comprises a polysilicon layer; The polysilicon layer of the first transport layer has an amorphous silicon region of the first transport layer, and the amorphous silicon region of the first transport layer is located on at least part of the surface of the polysilicon layer of the first transport layer away from the silicon substrate; The carrier collection layer is arranged on the first transport layer, and at least part of the carrier collection layer is in contact with the amorphous silicon region of the first transport layer. The solar cell according to claim 1, characterized in that The solar cell further comprises a second transport layer; The first surface of the silicon substrate is respectively provided with the first transport layer and the second transport layer, and the first transport layer and the second transport layer are arranged at intervals. The solar cell according to claim 1, characterized in that The solar cell further comprises a second transport layer; the first surface of the silicon substrate is provided with the first transport layer, and the second surface of the silicon substrate is provided with the second transport layer. The solar cell according to claim 1, characterized in that In the thickness direction of the solar cell, the thickness of the amorphous silicon region is 3% to 30% of the thickness of the polysilicon layer. The solar cell according to claim 1, characterized in that In the thickness direction of the solar cell, the thickness of the amorphous silicon region ranges from 2 nm to 30 nm. The solar cell according to claim 1, characterized in that Perpendicular to the thickness direction of the solar cell, in a unit area where the carrier collection layer is in direct contact with the first transport layer, the area of the amorphous silicon region is 10% to 90% of the area of the polysilicon layer. The solar cell according to claim 1, characterized in that The surface of the polysilicon layer of the first transport layer away from the silicon substrate is provided with an etching region, and the etching region is provided with the amorphous silicon region. The solar cell according to claim 1, characterized in that The amorphous silicon region has a first doping element and / or a second doping element, the polysilicon layer has a first doping element, and the doping concentration of the amorphous silicon region is greater than the doping concentration of the polysilicon layer. The solar cell according to claim 8, characterized in that The doping concentration of the amorphous silicon region ranges from 3 x 1018 to 7 x 1018 atoms / cm3. 19 atoms / cm3 3 atoms / cm3 19 atoms / cm3 3 . The solar cell according to claim 1, characterized in that The amorphous silicon region is provided with particulate matter. The solar cell according to claim 2, characterized in that The carrier collection layer further comprises a transparent conductive layer, and the transparent conductive layer is at least connected to part of the surface of the polysilicon layer away from the silicon substrate, at least connected to part of the surface of the amorphous silicon region away from the silicon substrate, and at least connected to part of the surface of the second transport layer away from the silicon substrate. The solar cell according to claim 2, characterized in that The end portion of the first transport layer close to the second transport layer is arranged in a stack with the end portion of the second transport layer close to the first transport layer to form a stacking portion, and the end portion of the first transport layer is located between the end portion of the second transport layer and the first surface. The carrier collection layer further comprises a transparent conductive layer, and the transparent conductive layer is at least connected to part of the surface of the first transport layer away from the silicon substrate and at least connected to part of the surface of the second transport layer away from the silicon substrate, and the transparent conductive layer has a second opening for breaking the electrical connection between the first transport layer and the second transport layer. The solar cell according to claim 2, characterized in that The first transport layer and the second transport layer have an isolation region therebetween; The carrier collecting layer further comprises a transparent conductive layer connected to at least a part of the surface of the first transport layer away from the silicon substrate and at least a part of the surface of the second transport layer away from the silicon substrate, the transparent conductive layer having a third opening for breaking the electrical connection between the first transport layer and the second transport layer. The solar cell according to claim 2 or 3, characterized in that, The second transport layer comprises a polysilicon layer. The polysilicon layer of the second transport layer has a second transport layer amorphous silicon region, the second transport layer amorphous silicon region being located on at least a part of the surface of the polysilicon layer of the second transport layer away from the silicon substrate. The carrier collecting layer is arranged on the second transport layer, and at least a part of the carrier collecting layer is in contact with the second transport layer amorphous silicon region. The solar cell according to claim 2, characterized in that The first transport layer is arranged in a stack with the end portion of the second transport layer near the end portion of the first transport layer to form a stacked portion, and the end portion of the first transport layer is located between the end portion of the second transport layer and the first surface. The second transport layer comprises a stack of an intrinsic amorphous silicon region and a doped amorphous silicon region. The doped amorphous silicon region covering the end portion of the first transport layer has a hole structure. The solar cell according to claim 15, characterized in that The width of the doped amorphous silicon region with the hole structure in the extension direction of the first surface of the silicon substrate is 0.1 um to 20 um. The solar cell according to claim 15, characterized in that In the top view of the solar cell, the shape of the hole structure is at least one of a circle, an ellipse, and an irregular figure. The solar cell according to claim 1, characterized in that The carrier collecting layer is arranged on the first transport layer, and the carrier collecting layer is in contact with all the amorphous silicon regions of the first transport layer. The solar cell according to claim 1, characterized in that When the carrier collecting layer is a stack of a transparent conductive layer and a metal electrode layer, the transparent conductive layer is closer to the silicon substrate than the metal electrode layer, and in the thickness direction of the solar cell, the projection of the transparent conductive layer on the surface of the silicon substrate covers all the amorphous silicon regions of the first transport layer, and the projection of the metal electrode layer on the surface of the silicon substrate covers at least a part of the amorphous silicon regions of the first transport layer. When the carrier collecting layer is a metal electrode layer, in the thickness direction of the solar cell, the projection of the metal electrode layer on the surface of the silicon substrate covers all the amorphous silicon regions of the first transport layer. A method of manufacturing a solar cell, characterized by, The manufacturing method comprises: providing a silicon substrate, the silicon substrate having a first surface and a second surface arranged opposite to each other; forming a first transport layer on at least one of the first surface and the second surface, the first transport layer comprising a polysilicon layer; forming a first transport layer amorphous silicon region on at least a part of the surface of the polysilicon layer of the first transport layer away from the silicon substrate; forming a carrier collecting layer on the first transport layer, and at least a part of the carrier collecting layer being in contact with the first transport layer amorphous silicon region. A photovoltaic module characterized by The photovoltaic module comprises a cover plate, a back plate, and a solar cell disposed between the cover plate and the back plate; the solar cell comprises the solar cell according to any one of claims 1 to 19.

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