Data processing apparatus and data processing method

Abstract

A data processing apparatus and a data processing method, used to ensure that the bandwidth of the data processing apparatus can meet service requirements when the chip bandwidth is limited. In the present solution, a plurality of chips are disposed in the data processing apparatus, and each chip is connected to each of a plurality of ports of the data processing apparatus via a physical link, such that data entering an arbitrary port of the data processing apparatus can be forwarded by a chip via another port, thereby ensuring that the data processing apparatus can normally perform data exchange. In addition, since a plurality of chips are disposed in a single data processing apparatus, the bandwidth of the data processing apparatus is actually the sum of the bandwidths of the plurality of chips, thereby effectively increasing the bandwidth of the data processing apparatus when the chip bandwidth is fixed, and ensuring that the data processing apparatus can meet service requirements.

Description

Data processing apparatus and data processing method

[0001] The present application claims priority from the Chinese patent application No. 202411245253.5 filed on September 5, 2024, and entitled "A data processing apparatus and data processing method", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the field of communication technology, and in particular to a data processing apparatus and data processing method. BACKGROUND

[0003] In a data center, various types of service data are transmitted through data exchange devices (such as switches) in the data center, so the performance of the data exchange devices in the data center affects the transmission performance of various service data.

[0004] With the large-scale application of artificial intelligence technology, the amount of service data that needs to be interacted between network devices in the data center is increasing, so the bandwidth requirement of the data exchange devices in the data center is also increasing. Generally, a data exchange device includes a switch chip, and the bandwidth of the data exchange device is usually determined by the bandwidth supported by the switch chip in the data exchange device.

[0005] Due to the limitations of technology and cost, the maximum bandwidth of a single switch chip is often limited, for example, the maximum bandwidth of a single switch chip is currently 51.2 terabits per second (Tbps). Therefore, in the case of fixed bandwidth of the switch chip, the bandwidth of the data exchange device is also fixed, which makes it difficult for the current data exchange device to meet the service requirements. SUMMARY

[0006] The present application provides a data processing apparatus and data processing method, which can effectively improve the bandwidth of the data processing apparatus and ensure that the data processing apparatus can meet the service requirements.

[0007] The first aspect provides a data processing apparatus, comprising a first chip, a second chip, a first port and a second port. The first chip is connected to the first port and the second port through a first physical link respectively; the second chip is connected to the first port and the second port through a second physical link respectively.

[0008] Since the first chip and the second chip are connected to the first port and the second port respectively, data entering from any one of the first port and the second port can be directly transmitted from the other port by one of the first chip or the second chip without being transmitted between the first chip and the second chip.

[0009] In the scheme, by arranging multiple chips in the data processing device and connecting each chip to each port of the multiple ports of the data processing device through a physical link, data entering from any one of the ports of the data processing device can be transmitted from the other port by the chip, thereby ensuring that the data processing device can normally perform data exchange. Moreover, since multiple chips are arranged in one data processing device, the bandwidth of the data processing device is actually the sum of the bandwidths of the multiple chips, thereby effectively improving the bandwidth of the data processing device under the condition that the bandwidth of the chip is fixed and ensuring that the data processing device can meet the demand of a service.

[0010] In a possible implementation, there is no physical link connection between the first chip and the second chip. For example, all the physical links connected by the first chip and the second chip are connected to the first port and the second port. That is, the first chip and the second chip do not interact with each other, and the first chip and the second chip do not need to reserve additional bandwidth for the inter-chip link, thereby ensuring that the bandwidth of the first chip and the second chip can be provided to the outside through the ports as much as possible.

[0011] In a possible implementation, the first physical link includes at least two physical sublinks, the first chip is connected to the first port through at least one of the at least two physical sublinks, and is connected to the second port through at least one of the at least two physical sublinks. That is, the number of physical sublinks connected by the first chip to the first port is one or more, and the number of physical sublinks connected by the first chip to the second port is also one or more.

[0012] In a possible implementation, in order to ensure non-blocking exchange of data, the number of physical sublinks connected by the first chip to the first port is the same as the number of physical sublinks connected by the first chip to the second port.

[0013] In the scheme, since the bandwidths of different physical sublinks connected by one chip are often the same, by arranging the number of physical sublinks connected by the chip to different ports to be the same, the chip can ensure that the bandwidth provided for each port is the same, thereby ensuring non-blocking exchange of data and ensuring the efficiency of data transmission.

[0014] In a possible implementation, the first physical link and the second physical link include the same number of physical sublinks. That is, the bandwidth of the first chip is the same as the bandwidth of the second chip, and the first chip and the second chip are both connected to the port through the same number of physical sublinks. The number of physical sublinks connected to the first port and the second port is both the first number, and the number of physical sublinks connected to the port by the first chip and the second chip is both half of the first number.

[0015] In this solution, in the case that the bandwidths of the chips in the data processing apparatus are the same and the bandwidths provided by each port to the outside are also the same, the connection between the chips and the ports can be implemented and the data can be exchanged between any two ports without blocking by connecting the physical sublinks that can be connected by each port to each chip evenly.

[0016] In a possible implementation, the first port and the second port are both physical ports. That is, the first port and the second port are independent pluggable physical ports.

[0017] Alternatively, the first port and the second port are both logical ports divided based on a physical port, and the first port and the second port are used to connect different apparatuses outside the data processing apparatus. That is, the first port and the second port are not independent physical ports, but logical ports divided from a physical port. At this time, other apparatuses of the data processing apparatus are connected to the physical port to which the first port or the second port belongs through optical fibers or cables. Although the first port and the second port are not independent physical ports, the first port and the second port as an independent logical port are still connected to different apparatuses outside the data processing apparatus to ensure the isolation of data forwarding between different apparatuses.

[0018] In a possible implementation, in addition to the first chip, the second chip, the first port and the second port, the data processing apparatus further includes a third chip, wherein the third chip is connected to the first port and the second port through a third physical link.

[0019] That is, the data processing apparatus can include two or more chips. And each chip in the data processing apparatus is connected to each port of the data processing apparatus through a physical link, so as to ensure that the data between any two ports can be forwarded based on the same chip.

[0020] In a possible implementation, there is no physical link connection between the first chip, the second chip and the third chip, that is, there is no physical link connection between all chips in the data processing apparatus. After each chip in the data processing apparatus receives data through a connected port, the chip directly transmits the data out through another connected port, without forwarding the data to another chip. In this way, all chips in the data processing apparatus do not need to reserve additional bandwidth for inter-chip links, ensuring that the bandwidth of the data processing apparatus is the sum of the bandwidths of all chips in the data processing apparatus, thereby maximizing the utilization of the bandwidth of the chips in the data processing apparatus.

[0021] In a possible implementation, the third physical link includes at least two physical sublinks, and the third chip is connected to the first port through at least one of the at least two physical sublinks.

[0022] In a possible implementation, the first physical link, the second physical link and the third physical link include the same number of physical sublinks, the number of physical sublinks connected to the first port and the second port is a second value, and the number of physical sublinks connected to the port by the first chip, the second chip and the third chip is one third of the second value.

[0023] Briefly, in the case where the data processing apparatus includes multiple chips, all physical sublinks connected to each port in the data processing apparatus are evenly connected to each chip in the data processing apparatus, so that the number of physical sublinks connected to the same port by each chip is the same.

[0024] In a possible implementation, the first chip and the second chip are Programmable Logic Device (PLD) chips, Application-Specific Integrated Circuit (ASIC) chips, Networking Processors (NP), Central Processing Units (CPU), Graphics Processing Units (GPU), Neural-network Processing Units (NPU) or Tensor Processing Units (TPU).

[0025] In a possible implementation, the data processing apparatus is a switch, a router, a server, a line card, an optical tributary board or an optical line board.

[0026] In a second aspect, a data processing method is provided, which is applied to a data processing device including a first chip, a second chip, a first port and a second port, the first chip being connected to the first port and the second port through a first physical link respectively, and the second chip being connected to the first port and the second port through a second physical link respectively. The data processing method includes: receiving, by the first chip, first data from the first port through the first physical link; forwarding, by the first chip, the first data from the second port through the first physical link; receiving, by the second chip, second data from the first port through the second physical link; and forwarding, by the second chip, the second data from the second port through the second physical link.

[0027] In a possible implementation, the first chip and the second chip are not connected by a physical link.

[0028] In a possible implementation, the first physical link includes at least two physical sublinks, the first chip is connected to the first port through at least one of the at least two physical sublinks, and the first chip receives the first data from the first port through the at least one physical sublink.

[0029] In a possible implementation, the number of physical sublinks to which the first chip is connected on the first port is the same as the number of physical sublinks to which the first chip is connected on the second port.

[0030] In a possible implementation, the first physical link and the second physical link include the same number of physical sublinks, the number of physical sublinks connected on the first port and the second port is a first value, and the number of physical sublinks to which the first chip and the second chip are connected on one port is half of the first value.

[0031] In a possible implementation, the first port and the second port are both physical ports; or, the first port and the second port are both logical ports divided based on physical ports, and the first port and the second port are used to connect different devices other than the data processing device.

[0032] In a possible implementation, the data processing device further includes a third chip, the third chip being connected to the first port and the second port through a third physical link, the third chip receiving third data from the first port through the third physical link, and the third chip forwarding the third data from the second port through the third physical link.

[0033] In a possible implementation, the first chip, the second chip and the third chip are not connected by a physical link.

[0034] In a possible implementation, the third physical link includes at least two physical sublinks, the third chip being connected to the first port through at least one of the at least two physical sublinks.

[0035] In a possible implementation, the first physical link, the second physical link and the third physical link include the same number of physical sublinks, the number of the physical sublinks connected on the first port and the second port is the second value, and the number of the physical sublinks connected to one port by the first chip, the second chip and the third chip is one third of the second value.

[0036] In a possible implementation, the first chip and the second chip are PLD chips, ASIC chips, NPs, CPUs, GPUs, NPUs or TPUs.

[0037] In a possible implementation, the data processing apparatus is a switch, a router, a server, a line card board, an optical tributary board or an optical line board. BRIEF DESCRIPTION OF DRAWINGS

[0038] Fig. 1 is a structural schematic diagram of a data exchange device provided by the present application;

[0039] Fig. 2 is a structural schematic diagram of a data processing apparatus provided by the present application;

[0040] Fig. 3 is a schematic diagram of a first port and a second port being physical ports provided by the present application;

[0041] Fig. 4 is a schematic diagram of a first port and a second port being logical ports provided by the present application;

[0042] Fig. 5 is a structural schematic diagram of another data processing apparatus provided by the present application;

[0043] Fig. 6 is a schematic diagram of a plurality of chips and a plurality of physical ports connected in a data processing apparatus provided by the present application;

[0044] Fig. 7 is a schematic diagram of a plurality of chips and a plurality of logical ports connected in a data processing apparatus provided by the present application;

[0045] Fig. 8 is a networking schematic diagram of a switch provided by the present application;

[0046] Fig. 9 is a networking schematic diagram of another switch provided by the present application. DETAILED DESCRIPTION

[0047] In order to make the objectives, technical solutions and advantages of the present application clearer, the embodiments of the present application are described below with reference to the drawings, obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments. Those skilled in the art can know that with the appearance of new application scenarios, the technical solutions provided by the embodiments of the present application are also applicable to similar technical problems.

[0048] The terms "first", "second", and the like in the description and claims of the present application and the above drawings are used to distinguish similar objects, and are not necessarily used to describe a particular sequential or chronological order, nor are they used to indicate or imply relative importance. For example, the first chip and the second chip are used to distinguish different chips, and are not used to describe a specific order of the chips, nor can it be understood that the first chip is more important than the second chip. In this application, unless otherwise stated, "at least one" means one or more, and "a plurality" means two or more.

[0049] At present, a switching chip is usually included in a data exchange device, and the bandwidth of the data exchange device is determined by the bandwidth supported by the switching chip in the data exchange device. However, the maximum bandwidth of a single switching chip is often limited, for example, the maximum bandwidth of a single switching chip is currently 51.2Tbps. Therefore, in the case of a fixed bandwidth of the switching chip, the bandwidth of the data exchange device is also fixed, which makes it difficult for the current data exchange device to meet the business requirements.

[0050] Please refer to FIG. 1, which is a structural schematic diagram of a data exchange device provided by the present application. As shown in FIG. 1, in one possible implementation, chip 1 and chip 2 are deployed in the data exchange device, and a link is connected between chip 1 and chip 2, so that data forwarding can be achieved between chip 1 and chip 2. In addition, chip 1 is also connected to port 1, and chip 2 is connected to port 2, and the data exchange device is connected to external network devices through port 1 and port 2. That is, chip 1 and chip 2 jointly provide bandwidth to the outside, and the total bandwidth of the data exchange device is the sum of the bandwidth provided by chip 1 and chip 2 to the outside. Although the implementation shown in FIG. 1 can slightly improve the bandwidth of the data exchange device, since the chips need to have an additional interconnection link, a part of the bandwidth of chip 1 and chip 2 will be provided to the interconnection link between the chips, resulting in that the actual bandwidth provided by chip 1 and chip 2 to the outside is not high.

[0051] Therefore, the present application provides a data processing device, by arranging a plurality of chips in the data processing device, and each chip is connected to each port of a plurality of ports of the data processing device through a physical link, so that the data entering from any port in the data processing device can be directly forwarded by the chip from another port, thereby ensuring that the data processing device can normally perform data exchange. Moreover, since a plurality of chips are arranged in one data processing device, the bandwidth of the data processing device is actually the sum of the bandwidths of the plurality of chips, which effectively improves the bandwidth of the data processing device in the case of a fixed bandwidth of the chip, and ensures that the data processing device can meet the requirements of the business.

[0052] Exemplarily, refer to FIG. 2, which is a structural schematic diagram of a data processing apparatus provided by the present application. As shown in FIG. 2, the data processing apparatus provided by the present application comprises a first chip, a second chip, a first port and a second port. The first chip is connected to the first port and the second port through a first physical link respectively. The second chip is connected to the first port and the second port through a second physical link respectively.

[0053] It should be noted that the first physical link between the first chip and the first port and the second port is actually bidirectional connection, that is, the first chip can send data to the first port and / or the second port through the first physical link, and can also receive data from the first port and / or the second port through the first physical link. Similarly, the second physical link between the second chip and the first port and the second port is also bidirectional connection, the second chip can send data to the first port and / or the second port through the second physical link, and can also receive data from the first port and / or the second port through the second physical link.

[0054] In addition, the first chip and the second chip are provided with a serializer / deserializer (SerDes). The first physical link connected to the first chip is actually connected to the SerDes of the first chip, and the second physical link connected to the second chip is actually connected to the SerDes of the second chip. The SerDes is an interface device for realizing long-distance high-speed communication, which is often used as a physical layer implementation scheme of communication protocols such as peripheral component interconnect express (PCI-Express), gigabit Ethernet and optical fiber communication, and is widely used in high-speed interconnection between chips, between boards and between devices.

[0055] Since the first chip and the second chip are connected to the first port and the second port respectively, the data entering from any one of the first port and the second port can be directly transmitted out from the other port through one of the first chip or the second chip, without the need for forwarding between the first chip and the second chip.

[0056] For example, in the data processing apparatus, the first chip receives first data from the first port through the first physical link, and forwards the first data from the second port through the first physical link. The second chip receives second data from the first port through the second physical link, and forwards the second data from the second port through the second physical link. Of course, the first chip or the second chip can also receive data from the second port, and transmit the data received from the second port from the first port.

[0057] In this way, by connecting the first chip and the second chip in the data processing apparatus to each port on the data processing apparatus, data entering from any port in the data processing apparatus can be directly forwarded by any chip from another port, so that the data processing apparatus can normally perform data exchange. Moreover, since the first chip and the second chip in the data processing apparatus do not need to perform data forwarding, all bandwidths of the first chip and the second chip can be provided externally through the ports, so that the bandwidth of the data processing apparatus is actually the sum of the bandwidths of the first chip and the second chip. For example, when the bandwidths of the first chip and the second chip are both 50 Tbps, the bandwidth of the data processing apparatus is actually 100 Tbps.

[0058] Therefore, when the chips and the ports in the data processing apparatus adopt the connection manner provided in the present application, the bandwidth of the data processing apparatus can be linearly increased with the increase of the number of chips, effectively improving the bandwidth of the data processing apparatus and ensuring that the data processing apparatus can meet the needs of services.

[0059] Optionally, the first chip and the second chip are not connected by a physical link. That is, the first chip and the second chip do not interact with each other, and the first chip and the second chip do not need to reserve additional bandwidth for the link between the chips, so that the bandwidths of the first chip and the second chip can be provided externally through the ports as much as possible, ensuring that the bandwidths of the first chip and the second chip are maximally utilized.

[0060] Of course, the first chip and the second chip can also be connected by a physical link, but the physical link between the first chip and the second chip is not used to forward user service data, but is used to synchronize some control information or configuration information between the first chip and the second chip. Therefore, even if the first chip and the second chip are connected by a physical link, the physical link between the first chip and the second chip will not occupy too much bandwidth of the first chip and the second chip, ensuring that the first chip and the second chip can provide as much bandwidth as possible externally through the ports.

[0061] In specific implementation, the first physical link includes a plurality of physical sub-links, and the first chip connects the first port and the second port through different physical sub-links in the plurality of physical sub-links. The second physical link also includes a plurality of physical sub-links, and the second chip connects the first port and the second port through different physical sub-links.

[0062] Exemplarily, the first physical link includes at least two physical sublinks, the first chip is connected to the first port through at least one of the at least two physical sublinks, and is connected to the second port through at least one of the at least two physical sublinks. And on the first chip, the physical sublink connected to the first port is different from the physical sublink connected to the second port. That is, the first chip is connected to the first port and the second port through different physical sublinks respectively. For example, assuming that the first physical link includes physical sublink 1 and physical sublink 2, the first chip is connected to the first port through the physical sublink 1, and is connected to the second port through the physical sublink 2. For another example, assuming that the first physical link includes physical sublink 1, physical sublink 2, physical sublink 3 and physical sublink 4, the first chip is connected to the first port through the physical sublink 1 and the physical sublink 2, and is connected to the second port through the physical sublink 3 and the physical sublink 4.

[0063] Similarly, the second physical link also includes two or more physical sublinks, the second chip is connected to the first port through at least one of the physical sublinks included in the second physical link, and is connected to the second port through at least one of the other physical sublinks. And on the second chip, the physical sublink connected to the first port is different from the physical sublink connected to the second port. That is, the second chip is connected to the first port and the second port through different physical sublinks respectively. For example, assuming that the second physical link includes physical sublink 1 and physical sublink 2, the second chip is connected to the first port through the physical sublink 1, and is connected to the second port through the physical sublink 2. For another example, assuming that the second physical link includes physical sublink 1, physical sublink 2, physical sublink 3 and physical sublink 4, the second chip is connected to the first port through the physical sublink 1 and the physical sublink 2, and is connected to the second port through the physical sublink 3 and the physical sublink 4.

[0064] In addition, the first physical link and the second physical link can be implemented by a printed circuit board (PCB), a flexible printed circuit (FPC) or a cable. Wherein, as long as the first physical link and the second physical link can ensure that data transmission between the chip and the port can be realized, the implementation manner of the first physical link and the second physical link is not limited in the present application.

[0065] Optionally, in order to ensure non-blocking exchange of data, the number of physical sublinks that the first chip is connected to on the first port is the same as the number of physical sublinks that the first chip is connected to on the second port. Similarly, the number of physical sublinks that the second chip is connected to on the first port is the same as the number of physical sublinks that the second chip is connected to on the second port.

[0066] Generally, the bandwidth of one physical sublink that one chip is connected to on one port is fixed, and the bandwidths of different physical sublinks that one chip is connected to are often the same. Then, if the number of physical sublinks that one chip is connected to on different ports is not the same, the bandwidths that the chip provides for different ports will not be the same. For example, if the number of physical sublinks that the first chip is connected to on the first port is 5, and the number of physical sublinks that the first chip is connected to on the second port is 3, if the first chip receives data from the 5 physical sublinks connected to the first port at the same time, it can often only transmit the data out through the 3 physical sublinks connected to the second port, thus easily leading to blocking of data.

[0067] Therefore, in the present scheme, by setting the number of physical sublinks that the chip is connected to on different ports to be the same, the bandwidths that the chip provides for each port can be ensured to be the same, thus ensuring non-blocking exchange of data and guaranteeing efficiency of data forwarding.

[0068] Optionally, the first physical link that the first chip is connected to and the second physical link that the second chip is connected to include the same number of physical sublinks. That is, the bandwidth of the first chip is the same as the bandwidth of the second chip, and the first chip and the second chip are both connected to the port through the same number of physical sublinks.

[0069] Furthermore, the number of physical sublinks connected on the first port and the second port is a first value, and the number of physical sublinks that the first chip and the second chip are connected to on one port is half of the first value.

[0070] That is, for each port in the data processing device, all of the physical sublinks connected on the port are evenly connected to each chip in the data processing device, thus making the number of physical sublinks that each chip is connected to on the same port the same. For example, in FIG. 2, the first physical link that the first chip is connected to includes 2 physical sublinks, and the second physical link that the second chip is connected to includes 2 physical sublinks. Furthermore, the first chip is connected to the first port through 1 physical sublink, and is connected to the second port through 1 physical sublink. The second chip is also connected to the first port through 1 physical sublink, and is connected to the second port through 1 physical sublink.

[0071] Of course, in some other embodiments, the number of connected physical sublinks between the first chip and the second chip and each port can also be other values. For example, the first chip is connected to the first port through 2 physical sublinks, and is connected to the second port through 2 physical sublinks. The second chip is also connected to the first port through 2 physical sublinks, and is connected to the second port through 2 physical sublinks.

[0072] In general, in the case that the bandwidths of the chips in the data processing apparatus are the same, and the bandwidths provided by each port to the outside are also the same, by connecting the physical sublinks that each chip can connect to each port evenly, the connection between the chips and the ports can be realized, and it is ensured that data can be exchanged between any two ports without blocking.

[0073] In addition, in some possible embodiments, the number of physical sublinks connected by the first chip and the second chip can also be different. For example, the bandwidth of the first chip is half of the bandwidth of the second chip, the first chip is connected to 4 physical sublinks, and the second chip is connected to 8 physical sublinks. At this time, the first chip is connected to the first port through 2 physical sublinks, and is connected to the second port through 2 physical sublinks; and the second chip is connected to the first port through 4 physical sublinks, and is connected to the second port through 4 physical sublinks.

[0074] Optionally, in the above data processing apparatus, the first port and the second port can be implemented in two ways.

[0075] In one possible implementation, the first port and the second port are both physical ports. That is, the first port and the second port are respectively physical ports of independent pluggable optical fibers or cables. Other devices outside the data processing apparatus can realize the connection with the first port or the second port by inserting the connected physical lines such as optical fibers or cables into the first port or the second port.

[0076] Exemplarily, please refer to FIG. 3, which is a schematic diagram of the first port and the second port being physical ports provided by the present application. As shown in FIG. 3, the first port and the second port are both physical ports with a bandwidth of 400 (gigabits per second, Gbps) (referred to as 400G physical ports). Moreover, in the data processing apparatus, the first port and the second port can be connected to 4 lanes, and the bandwidth of each lane is 100 Gbps. Therefore, in FIG. 3, the first chip is connected to the first port through two physical sublinks, and is connected to the second port through another two physical sublinks. The second chip is also connected to the first port through two physical sublinks, and is connected to the second port through another two physical sublinks.

[0077] In another possible implementation, the first port and the second port are both logical ports based on division of a physical port, and the first port and the second port are used to connect different devices outside the data processing device. That is, the first port and the second port are not independent physical ports, but are logical ports divided from a physical port, and a physical port is usually composed of multiple logical ports. In this case, other devices of the data processing device are connected to the physical port to which the first port or the second port belongs through the connected optical fiber or cable. In addition, although the first port and the second port are not independent physical ports, the first port and the second port as an independent logical port are still connected to different devices outside the data processing device to ensure the isolation of data forwarding between different devices.

[0078] Exemplarily, referring to FIG. 4, FIG. 4 is a schematic diagram of a first port and a second port being logical ports provided by the application. As shown in FIG. 4, the first port and the second port are logical ports divided from the same 800G physical port, that is, the first port is a 400G logical port 0, and the second port is a 400G logical port 1. Moreover, the first port and the second port can both connect four links. Therefore, in FIG. 4, the first chip is connected to the first port through two physical sublinks, and is connected to the second port through another two physical sublinks. The second chip is also connected to the first port through two physical sublinks, and is connected to the second port through another two physical sublinks. In this way, for the 800G physical port composed of the first port and the second port, the first chip is actually connected to the 800G physical port through four physical sublinks, and the second chip is also actually connected to the 800G physical port through eight physical sublinks.

[0079] In addition, taking the 800G physical port external optical fiber as an example, in order to realize that different logical ports are connected to different devices outside the data processing device, a light module supporting multiple channels can be used to connect to the 800G physical port of the data processing device. One end of the light module is a pluggable interface inserted into the 800G physical port of the data processing device, and the other end of the light module is connected with two pairs of optical fibers, and the two pairs of optical fibers can be connected to two different devices (for example, two switches with a bandwidth of 400Gbps). Alternatively, when a fiber connector (also known as a fiber jumper) is used to connect the data processing device, one end of the fiber connector is inserted into the 800G physical port of the data processing device, and the other end of the fiber connector is connected with two pairs of optical fibers, and the two pairs of optical fibers can be connected to different devices.

[0080] It should be noted that the above is introduced by taking the bandwidth of the port as 400Gbps and the bandwidth of each link connected by the port as 100Gbps as an example. In actual application, the bandwidth of each link connected by the port can be, for example, 10Gbps, 25Gbps, 56Gbps, 224Gbps, 336Gbps or 448Gbps, and the bandwidth of the port can be 400Gbps, 1.6Tbps or 3.2Tbps, and the present application does not make specific limitation on the bandwidth of the port and the bandwidth of the link on the port. Moreover, the above is introduced by taking 800G physical port divided into two 400G logical ports as an example, and in actual application, one physical port can be divided into two, four or eight logical ports, and the present application does not limit the number of logical ports that can be divided from one physical port.

[0081] The above embodiments introduce that the data processing apparatus includes the first chip and the second chip. In some scenarios, the data processing apparatus can include more than two chips.

[0082] Exemplarily, referring to FIG. 5, FIG. 5 is a structural schematic diagram of another data processing apparatus provided by the present application. As shown in FIG. 5, the data processing apparatus includes a first chip, a second chip and a third chip, and a first port and a second port. The first chip is connected to the first port and the second port through a first physical link respectively, the second chip is connected to the first port and the second port through a second physical link respectively, and the third chip is connected to the first port and the second port through a third physical link respectively.

[0083] The third physical link includes at least two physical sub-links, and the third chip is connected to the first port through at least one of the at least two physical sub-links and connected to the first port through the at least one physical sub-link.

[0084] That is, the data processing apparatus can include two or more chips. Moreover, each chip in the data processing apparatus is connected to each port of the data processing apparatus through a physical link, so as to ensure that the data between any two ports can be forwarded based on the same chip.

[0085] Optionally, there is no physical link connection between the first chip, the second chip and the third chip. That is to say, there is no physical link connection between all the chips in the data processing device. After each chip in the data processing device receives data through one connected port, the chip directly transmits the data out through another connected port without forwarding the data to another chip. In this way, all the chips in the data processing device do not need to reserve additional bandwidth for the inter-chip link, ensuring that the bandwidth of the data processing device is the sum of the bandwidths of all the chips in the data processing device, thereby maximizing the utilization of the bandwidth of the chips in the data processing device.

[0086] Optionally, in the data processing device, the first physical link, the second physical link and the third physical link include the same number of physical sublinks. The number of physical sublinks connected to the first port and the second port is a second value, and the number of physical sublinks connected to the one port by the first chip, the second chip and the third chip is one third of the second value.

[0087] In short, in the case where the data processing device includes multiple chips, all the physical sublinks connected to each chip in the data processing device are evenly connected to each port in the data processing device, so that the number of physical sublinks connected to the same port by each chip is the same. For example, in FIG. 5, the first physical link connected by the first chip, the second physical link connected by the second chip and the third physical link connected by the third chip each include 2 physical sublinks. And the first chip, the second chip and the third chip are connected to the first port through 1 physical sublink and connected to the second port through another 1 physical sublink.

[0088] The above embodiments introduce the case where the data processing device includes 3 chips and 2 ports. In actual applications, the data processing device can include two or more chips and two or more ports, and the number of chips and ports in the data processing device is not limited by the present application.

[0089] It should be noted that no matter how many chips and ports the data processing device includes, each chip needs to be connected to each port through a physical link. In order to ensure that the data between the ports can be exchanged without blocking, the chips in the data processing device need to be connected to the ports in a certain way to ensure that the bandwidth provided by each port is the same.

[0090] Exemplarily, refer to FIG. 6, which is a schematic diagram of the connection between multiple chips and multiple physical ports in a data processing apparatus provided by the present application. As shown in FIG. 6, the data processing apparatus includes n chips (i.e., chip 1-chip n) and y physical ports (i.e., physical port 1-physical port y). Wherein, the number of links that each of the physical port 1-physical port y can connect is m. At this time, in the chip 1-chip n, assuming that the number of links that each chip connects to a physical port is x, then x is the number of links that one physical port can connect divided by the number of chips, i.e., x=m / n. Wherein, x, m and n are positive integers.

[0091] That is to say, in the case that the number of links connected by each chip is the same, the multiple links connected by each chip are evenly distributed to each port, so that the number of links connected between different chips and the same physical port is the same (i.e., m / n).

[0092] Refer to FIG. 7, which is a schematic diagram of the connection between multiple chips and multiple logical ports in a data processing apparatus provided by the present application. As shown in FIG. 7, the data processing apparatus includes n chips (i.e., chip 1-chip n) and y physical ports (i.e., port 1-port y). Wherein, each of the port 1-port y includes z logical ports (i.e., port 1-port z), and the number of links that each physical port can connect is m, and the number of links connected by each logical port in one physical port is the same. At this time, in the chip 1-chip n, assuming that the number of links that each chip connects to a physical port is x, then x is the number of links that one physical port can connect divided by the number of logical ports and the number of chips, i.e., x=m / z / n. Wherein, x, m, z and n are positive integers.

[0093] Briefly, in the case that the number of links connected by each chip is the same and one physical port is divided into multiple logical ports, all the links (such as m links in FIG. 7) connected by one physical port are evenly distributed to each logical port included in the physical port, and the multiple links connected by each chip are evenly distributed to each logical port, so that the number of links connected between different chips and the same logical port is the same (i.e., m / z / n).

[0094] The above introduces the specific structure of the data processing apparatus provided by the present application, and the following introduces the specific scenarios applied by the data processing apparatus.

[0095] Exemplarily, in the data processing apparatus, the first chip and the second chip are Programmable Logic Device (PLD) chips, Application-Specific Integrated Circuit (ASIC) chips, Networking Processors (NPs), Central Processing Units (CPUs), Graphics Processing Units (GPUs), Neural-network Processing Units (NPUs), or Tensor Processing Units (TPUs). Among them, the programmable logic device includes any one or more of the following devices: complex programmable logic device (CPLD), field-programmable gate array (FPGA), and generic array logic (GAL).

[0096] Of course, when the data processing apparatus further includes other chips in addition to the first chip and the second chip, the other chips can also be the devices described above.

[0097] Specifically, taking the first chip as an example, when the first chip is a PLD chip, an ASIC chip, or an NP, the first chip is essentially a data forwarding chip, responsible for forwarding data received from a certain port to another port. When the first chip is a CPU, a GPU, an NPU, or a TPU, the first chip is essentially a computing chip, responsible for computing data received from a certain port and sending the computed data from another port.

[0098] Optionally, the data processing apparatus described above is specifically a switch, a router, a server, a line card, an optical tributary board, or an optical line board. When the data processing apparatus is a switch, a router, or a server, and the chip in the data processing apparatus is a data forwarding chip, the port in the data processing apparatus is a port that provides data forwarding function externally, so all links connected to the chip in the data processing apparatus are connected to the port to provide external bandwidth.

[0099] In the case that the data processing apparatus is a line card board, an optical branch board or an optical line board in a network device, and the chip in the data processing apparatus is a data forwarding chip, the port in the data processing apparatus is also a port providing data forwarding function. However, there can be other line card boards, optical branch boards or optical line boards in the network device, and thus part of the links connected to the chip in the data processing apparatus are connected to the ports providing bandwidth, and the other part of the links are connected to the other line card boards, optical branch boards or optical line boards in the network device.

[0100] In the case that the data processing apparatus is a server, and the chip in the data processing apparatus is a computing chip, the port in the data processing apparatus can be, for example, a port providing externally, i.e., other devices outside the server can access the port through an optical fiber or a cable. At this time, the chip in the data processing apparatus is used to receive data from a certain port, and after performing computation on the data, the chip transmits the computed data from another port.

[0101] In the case that the data processing apparatus is a server, and the chip in the data processing apparatus is a computing chip, the port in the data processing apparatus can also be a port providing internally, e.g., a port connected to an internal data forwarding chip. At this time, the chip in the data processing apparatus is used to receive data from a connected port, and after performing computation on the data, the chip transmits the computed data from any port, so that the chip in the data processing apparatus can complete the processing of data transmitted by the internal data forwarding chip in the server.

[0102] In general, the data processing apparatus provided in the present application can be applied to any data interaction scene, and can realize large-capacity data non-blocking interaction, which is conducive to realizing networking requirements in various scenes by using the data processing apparatus in actual applications.

[0103] Exemplarily, refer to FIG. 8, which is a networking diagram of a switch provided in the present application. As shown in FIG. 8, taking a spine-leaf network architecture as an example, the spine-leaf network architecture is composed of spine switches and leaf switches.

[0104] Among them, the spine layer includes 32 spine switches with a bandwidth of 100 Tbps, and the data processing apparatus provided in the present application is specifically a spine switch. Moreover, one spine switch includes two chips (such as the first chip and the second chip in FIG. 8) and 128 800G physical ports. At this time, the first chip and the second chip are both connected to each of the 128 800G physical ports through 4 physical sub-links, i.e., the bandwidth of each physical sub-link is 100 Gbps.

[0105] In addition, the leaf layer includes 128 leaf switches (e.g., leaf switches 1-leaf switches 128 in FIG. 8). Moreover, each leaf switch has 64 800G physical ports, 32 of which are uplink 800G physical ports respectively connected to the 800G physical ports of the corresponding spine switch, and 32 of which are downlink 800G physical ports respectively connected to network cards. Therefore, since each leaf switch can be connected to 32 network cards, 128 leaf switches can be connected to 4096 network cards with 800Gbps bandwidth, thereby realizing the networking scale of 4096 network cards.

[0106] Exemplarily, referring to FIG. 9, FIG. 9 is a networking schematic diagram of another switch provided by the present application. As shown in FIG. 9, the network architecture in FIG. 9 also includes a spine layer and a leaf layer.

[0107] The spine layer includes 64 spine switches with a bandwidth of 100Tbps, and the data processing apparatus provided by the present application is specifically a spine switch. The spine switch includes a first chip, a second chip and 128 800G physical ports, and each 800G physical port can be divided into two 400G logical ports. At this time, the first chip and the second chip are connected to each of the 256 400G logical ports through 2 physical sublinks.

[0108] In addition, the leaf layer includes 256 leaf switches (e.g., leaf switches 1-leaf switches 256 in FIG. 9). Moreover, each leaf switch has 128 400G physical ports, 64 of which are uplink 400G physical ports respectively connected to the 400G logical ports of the corresponding spine switch, and 64 of which are downlink 400G physical ports respectively connected to network cards with 400Gbps bandwidth. Therefore, since each leaf switch can be connected to 64 network cards, 256 leaf switches can be connected to 16384 network cards, thereby realizing the networking scale of 16384 network cards.

[0109] The above embodiments are only used to illustrate the technical solutions of the present application, but not limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can modify the technical solutions recorded in the foregoing embodiments, or equivalently replace some technical features thereof; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A data processing apparatus, characterized by, Comprising: a first chip, a second chip, a first port and a second port; the first chip is connected to the first port and the second port through a first physical link respectively; the second chip is connected to the first port and the second port through a second physical link respectively.

2. The apparatus of claim 1, wherein, There is no physical link connection between the first chip and the second chip.

3. The apparatus of claim 1 or 2, wherein, The first physical link comprises at least two physical sublinks, and the first chip is connected to the first port through at least one of the at least two physical sublinks.

4. The apparatus according to claim 3, wherein: The number of physical sublinks connected by the first chip to the first port is the same as the number of physical sublinks connected by the first chip to the second port.

5. The apparatus according to any one of claims 1-4, wherein: The first physical link and the second physical link comprise the same number of physical sublinks, the number of physical sublinks connected to the first port and the second port is a first value, and the number of physical sublinks connected by the first chip and the second chip to one port is half of the first value.

6. The apparatus of any one of claims 1-5, wherein, The first port and the second port are both physical ports; Or, the first port and the second port are both logical ports divided based on physical ports, and the first port and the second port are used to connect different apparatuses other than the data processing apparatus.

7. The apparatus of claim 1, wherein, The apparatus further comprises a third chip; The third chip is connected to the first port and the second port through a third physical link respectively.

8. The apparatus of claim 7, wherein, There is no physical link connection between the first chip, the second chip and the third chip.

9. The apparatus of claim 7 or 8, wherein, The third physical link comprises at least two physical sublinks, and the third chip is connected to the first port through at least one of the at least two physical sublinks.

10. The apparatus of any of claims 7-9, wherein, The first physical link, the second physical link and the third physical link comprise the same number of physical sublinks, the number of physical sublinks connected to the first port and the second port is a second value, and the number of physical sublinks connected by the first chip, the second chip and the third chip to one port is one third of the second value.

11. The apparatus of any one of claims 1-10, wherein, The first chip and the second chip are programmable logic device (PLD) chips, application specific integrated circuit (ASIC) chips, network processors (NP), central processing units (CPU), graphics processing units (GPU), neural processing units (NPU) or tensor processing units (TPU).

12. The apparatus of any one of claims 1-11, wherein, The apparatus is a switch, a router, a server, a line card board, an optical tributary board or an optical line board.

13. A data processing method, characterized by, Applied to a data processing apparatus, the data processing apparatus comprises a first chip, a second chip, a first port and a second port, the first chip is connected to the first port and the second port through a first physical link respectively, and the second chip is connected to the first port and the second port through a second physical link respectively; The method comprises: The first chip receives first data from the first port through the first physical link; The first chip forwards the first data from the second port through the first physical link; The second chip receives second data from the first port through the second physical link; The second chip forwards the second data from the second port through the second physical link.

14. The method of claim 13, wherein, There is no physical link connection between the first chip and the second chip.

15. The method according to claim 13 or 14, characterized in that, The first physical link includes at least two physical sublinks, and the first chip is connected to the first port through at least one of the at least two physical sublinks.

16. The method of claim 15, wherein, The number of physical sublinks that the first chip is connected to on the first port is the same as the number of physical sublinks that the first chip is connected to on the second port.

17. The method of any one of claims 13-16, wherein, The first physical link and the second physical link include the same number of physical sublinks, the number of physical sublinks connected on the first port and the second port is a first value, and the number of physical sublinks that the first chip and the second chip are connected to on a port is half of the first value.

18. The method according to any one of claims 13-17, characterized by, The first port and the second port are both physical ports; Or, the first port and the second port are both logical ports divided based on physical ports, and the first port and the second port are used to connect different devices other than the data processing device.

19. The method of claim 13, wherein, The device further includes a third chip; the third chip is connected to the first port and the second port through a third physical link respectively; The method further includes: The third chip receives third data from the first port through a third physical link; The third chip forwards the third data from the second port through the third physical link.

20. The method of claim 19, wherein, There is no physical link connection between the first chip, the second chip and the third chip.

21. The method of claim 19 or 20, wherein, The third physical link includes at least two physical sublinks, and the third chip is connected to the first port through at least one of the at least two physical sublinks.

22. The method of any one of claims 19-21, wherein, The first physical link, the second physical link and the third physical link include the same number of physical sublinks, the number of physical sublinks connected on the first port and the second port is a second value, and the number of physical sublinks that the first chip, the second chip and the third chip are connected to on a port is one third of the second value.

23. The method of any of claims 13-22, wherein, The first chip and the second chip are PLD chips, ASIC chips, NPs, CPUs, GPUs, NPUs or TPUs.

24. The method of any of claims 13-23, wherein, The device is a switch, a router, a server, a line card, an optical branch board or an optical line board.

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