Solar cell and photovoltaic module

Abstract

The present application relates to the technical field of solar cells, and discloses a solar cell and a photovoltaic module, aiming to solve the problem of low efficiency of the solar cell. The solar cell comprises: a semiconductor substrate comprising a first surface and a second surface opposite to each other, and side surfaces connecting the first surface to the second surface. The first surface has edge regions and a middle region, each edge region has a first texture structure, and the middle region has a second texture structure, the size of the first texture structure being greater than that of the second texture structure. By means of the structure, the light-trapping effect of the semiconductor substrate can be improved, and the light absorption rate can be increased, thereby improving the efficiency of the solar cell. The present application further provides a photovoltaic module. The photovoltaic module comprises the described solar cell, and a plurality of solar cells are connected to form a cell string.

Description

A solar cell and a photovoltaic module

[0001] Cross-reference to Related Applications

[0002] This application claims priority to and the benefit of Chinese Patent Application No. 202411259790.5, filed on September 9, 2024, the contents of which are incorporated herein by reference in their entirety. This application claims priority to and the benefit of Chinese Patent Application No. 202510821967.4, filed on June 18, 2025, the contents of which are incorporated herein by reference in their entirety. This application claims priority to and the benefit of Chinese Patent Application No. 202511196991.X, filed on August 25, 2025, the contents of which are incorporated herein by reference in their entirety. TECHNICAL FIELD

[0003] The present application relates to the technical field of solar cells, and in particular to a solar cell and a photovoltaic module. BACKGROUND

[0004] A solar cell is a device that converts solar energy into electricity through the photoelectric effect or photochemical effect.

[0005] Current solar cells mainly include IBC (Interdigitated Back Contact) cells, TOPCON (Tunnel Oxide Passivated Contact) cells, PERC (Passivated Emitter and Rear Cell) cells, heterojunction cells, and bifacial solar cells. At present, there are many improvements in cell structure, however, how to make the photoelectric efficiency of the solar cell reach a high level is still a technical problem to be solved in the current industry. SUMMARY

[0006] The purpose of the present application is to provide a solar cell and a photovoltaic module to improve the efficiency of the solar cell.

[0007] To achieve the above purpose, in a first aspect, the present application provides a solar cell. The solar cell includes a semiconductor substrate, the semiconductor substrate including opposite first and second faces, and a side surface connecting the first and second faces. The first face has an edge region and a middle region, the edge region having a first texture structure, and the middle region having a second texture structure.

[0008] In an implementation, the size of the first texture structure is greater than the size of the second texture structure. By making the size of the first texture structure in the edge region greater than the size of the second texture structure in the middle region, the number of texture structures per unit area in the edge region is less, the surface of the texture structures in the edge region is more regular, and the surface defects formed are less, thereby facilitating improvement of the surface passivation effect of the edge region and further improvement of the efficiency of the solar cell.

[0009] In an implementation, the first texture structures in the edge region are connected to form a first texture structure group, and the edge region further includes a fifth texture structure, and the size of the fifth texture structure is smaller than the size of the first texture structure.

[0010] In an implementation, the fifth texture structure is located between the plurality of first texture structure groups and between the edge of the semiconductor substrate and the first texture structure group.

[0011] In an implementation, the surface of the first texture structure is recessed into the semiconductor substrate relative to the surface of the fifth texture structure.

[0012] In an implementation, the first texture structure and the fifth texture structure are both polishing structures, or the first texture structure is a pyramid structure and the fifth texture structure is a polishing structure.

[0013] In an implementation, when the first texture structure is a pyramid structure, the size of the pyramid of the first texture structure gradually decreases from the edge of the semiconductor substrate to the center.

[0014] In an implementation, when the first texture structure and the fifth texture structure are both polishing structures, the distribution area of the first texture structure gradually increases from the edge of the semiconductor substrate to the middle region.

[0015] In an implementation, the first texture structure is a pyramid structure and the fifth texture structure is a polishing structure; wherein: in the edge region, the distribution density of the polishing structure is greater than the distribution density of the pyramid structure; or, in the edge region, the distribution area of the polishing structure is greater than the distribution area of the pyramid structure; or, in the edge region, the distribution area of the polishing structure gradually decreases from the edge of the semiconductor substrate to the middle region; or, in the edge region, the distribution density of the polishing structure gradually decreases from the edge of the semiconductor substrate to the middle region; or, in the edge region, the distribution density of the pyramid structure gradually increases from the edge of the semiconductor substrate to the middle region.

[0016] In an implementation, the second texture structure of the middle region and the first texture structure of the edge region comprise a pyramid structure; the distribution density of the pyramid structure on the surface of the edge region is less than the distribution density of the pyramid structure on the surface of the middle region.

[0017] In an implementation, there is a transition zone between the first texture structure and the second texture structure, and the surface of the transition zone comprises a flat surface or a concave-convex surface.

[0018] In an implementation, the reflectivity of the middle region is less than the reflectivity of the edge region, and the width of the edge region is less than or equal to 200 μm in the direction from the center to the edge of the front surface of the semiconductor substrate.

[0019] In an implementation, the height of the first texture structure is greater than the height of the second texture structure; and / or, the base width of the first texture structure is greater than the base width of the second texture structure; and / or, the edge length of the first texture structure is greater than the edge length of the second texture structure.

[0020] In the above technical solution, the height of the first texture structure is greater than the height of the second texture structure, or the edge length of the first texture structure is greater than the edge length of the second texture structure, or the base width of the first texture structure is greater than the base width of the second texture structure, so that the number of the first texture structure of the edge region per unit area is less, and the surface defects are also less, thereby facilitating the improvement of the surface passivation effect of the edge region.

[0021] In an implementation, when the first texture structure is a pyramid structure, the height of the first texture structure is greater than or equal to 4 μm and less than or equal to 8 μm; and / or, the base width of the first texture structure is greater than or equal to 5 μm and less than or equal to 9 μm; and / or, the edge length of the first texture structure is less than 10 μm.

[0022] In an implementation, when the second texture structure is a pyramid structure, the height of the second texture structure is greater than or equal to 1 μm and less than 4 μm; and / or, the base width of the second texture structure is greater than or equal to 2 μm and less than 5 μm; and / or, the edge length of the second texture structure is less than 6 μm.

[0023] In the above technical solution, the height of the second texture structure is greater than or equal to 1 μm, which can reduce or avoid the situation that the light trapping effect of the second texture structure is not obvious due to the small height of the second texture structure, thereby ensuring that more light is refracted into the semiconductor substrate through the second texture structure, and further ensuring that the solar cell has a higher photoelectric conversion efficiency.

[0024] In an implementation, the vertex of the first texture structure is farther away from the back light side of the solar cell than the vertex of the second texture structure.

[0025] In an implementation, the surface height difference between the edge region and the middle region is greater than or equal to 1 μm and less than or equal to 10 μm.

[0026] In an implementation, in the front surface of the semiconductor substrate, the surface of the region for connecting the edge region and the middle region is respectively arranged to be inclined with respect to the surface of the edge region and the middle region.

[0027] In an implementation, the width of the edge region is greater than 0 μm and less than or equal to 50 μm; the width direction of the edge region is consistent with the vertical direction of the perpendicular line between the first surface and the second surface.

[0028] In an implementation, the size uniformity of the first texture structure located in the edge region is lower than the size uniformity of the second texture structure located in the middle region.

[0029] In an implementation, the side surface comprises a third texture structure region, the third texture structure region is close to the first surface, and the first surface is the light receiving surface.

[0030] In an implementation, the ratio of the width of the third texture structure region to the width of the side surface is less than 80%, and the width direction of the third texture structure region and the width direction of the side surface are both the vertical direction from the first surface to the second surface.

[0031] In an implementation, the side surface comprises a fourth texture structure region, and the fourth texture structure region comprises a tower base structure; a plurality of tower base structures are arranged along a first straight line, and the first straight line is inclined with respect to the side edge of the side surface.

[0032] In the case of adopting the above technical solution, since the plurality of tower base structures are arranged along the first straight line, and the first straight line is inclined with respect to the side edge of the side surface, the structural strength of the solar cell can be enhanced, the solar cell fragments can be prevented from being broken, and the fragment rate of the solar cell can be reduced.

[0033] In an implementation, the plurality of first straight lines are parallel to each other; and / or, the included angle between the first straight line and the side edge of the side surface is greater than or equal to 15° and less than or equal to 75°; and / or, the length of the first straight line is greater than the thickness of the semiconductor substrate, and the thickness direction of the semiconductor substrate is consistent with the vertical direction from the first surface to the second surface.

[0034] In an implementation, the third texture structure region and the fourth texture structure region are both coated with an amorphous silicon layer.

[0035] In the case of adopting the above technical solution, the side edge recombination of the semiconductor substrate is better reduced through the passivation of the amorphous silicon.

[0036] In an implementation manner, the amorphous silicon layer is laminated on the third textured region.

[0037] In an implementation manner, the fourth textured region is sequentially laminated with a tunneling silicon oxide layer, a doped polysilicon layer and a silicon nitride layer.

[0038] In an implementation manner, the boundary between the edge region and the middle region is a curve.

[0039] In the above technical solution, the first surface stress of the solar cell can be avoided from being too concentrated, and the edge collapse can be reduced.

[0040] In an implementation manner, the solar cell further comprises a first type electrode and a second type electrode; the first type electrode is arranged on the first surface side of the semiconductor substrate, and the second type electrode is arranged on the second surface side of the semiconductor substrate; the first type electrode and the second type electrode are opposite in polarity.

[0041] In an implementation manner, the solar cell further comprises a first type electrode and a second type electrode; the first type electrode and the second type electrode are alternately and spacedly arranged on the second surface of the semiconductor substrate; the first type electrode and the second type electrode are opposite in polarity.

[0042] In an implementation manner, the second surface has a first region and a second region alternately arranged along a first direction; the solar cell further comprises: a first doped semiconductor layer arranged on the first region; a second doped semiconductor layer arranged on the second region and extending to cover part of the first doped semiconductor layer; the second doped semiconductor layer and the first doped semiconductor layer are opposite in conductive type.

[0043] In the above technical solution, the solar cell can be a back contact solar cell or a bifacial solar cell, and is widely applicable.

[0044] In a second aspect, the application further provides a photovoltaic module. The photovoltaic module comprises the solar cell in the above technical solution, and a plurality of solar cells are connected to form a cell string.

[0045] Compared with the prior art, the photovoltaic module provided by the application has the same beneficial effects as the solar cell in the above technical solution, which will not be described herein. Further, since the first textured structure with a large size is formed in the edge region of the semiconductor substrate, more light can be reflected to the surfaces of the solar cells close to each other, thereby improving the light trapping effect of the whole module. BRIEF DESCRIPTION OF DRAWINGS

[0046] The accompanying drawings, which are included to provide a further understanding of the application and constitute a part of this application, illustrate certain illustrative embodiments of the application and are used to explain the application, but do not limit the application. In the drawings:

[0047] Fig. 1 is a schematic diagram of a structure of a semiconductor substrate according to an embodiment of the present application;

[0048] Fig. 2 is a schematic diagram of an enlarged view of a part of the structure of Fig. 1 according to an embodiment of the present application;

[0049] Fig. 3 is a top view of a bottom of a first texture structure and a bottom of a second texture structure according to an embodiment of the present application;

[0050] Fig. 4 is a schematic diagram of a side surface of a semiconductor substrate according to an embodiment of the present application;

[0051] Fig. 5 is a schematic diagram of a side surface of a semiconductor substrate according to an embodiment of the present application;

[0052] Fig. 6 is a schematic diagram of a longitudinal section of a structure of a solar cell according to an embodiment of the present application;

[0053] Fig. 7 is a schematic diagram of a longitudinal section of a structure of a solar cell according to an embodiment of the present application;

[0054] Fig. 8 is an SEM image of a part of an intermediate region of a solar cell according to an embodiment of the present application;

[0055] Fig. 9 is a schematic diagram of a structure of a solar cell according to an embodiment of the present application;

[0056] Fig. 10 is a schematic diagram of a structure of a solar cell according to an embodiment of the present application;

[0057] Fig. 11 is a schematic diagram of a structure of a solar cell according to an embodiment of the present application;

[0058] Fig. 12 is a schematic diagram of a structure of a solar cell according to an embodiment of the present application;

[0059] Fig. 13 is a schematic diagram of a structure of a solar cell according to an embodiment of the present application;

[0060] Fig. 14 is a schematic diagram of a structure of a solar cell according to an embodiment of the present application;

[0061] Fig. 15 is a schematic diagram of a structure of a solar cell according to an embodiment of the present application;

[0062] Fig. 16 is a schematic diagram of a structure of a solar cell according to an embodiment of the present application;

[0063] Fig. 17 is a schematic diagram of a structure of a solar cell according to an embodiment of the present application;

[0064] Fig. 18 is a schematic diagram of a structure of a solar cell according to an embodiment of the present application;

[0065] Fig. 19 is a structural schematic diagram of a solar cell according to an embodiment of the present application;

[0066] Fig. 20 is a structural SEM diagram of a solar cell according to an embodiment of the present application at the junction of the edge region and the middle region;

[0067] Fig. 21 is a structural SEM diagram of a solar cell according to an embodiment of the present application at the junction of the edge region and the middle region;

[0068] Fig. 22 is a structural enlarged schematic diagram of a solar cell according to an embodiment of the present application at a partial edge region;

[0069] Fig. 23 is a structural schematic diagram of a solar cell according to an embodiment of the present application;

[0070] Fig. 24 is a structural enlarged schematic diagram of a solar cell according to an embodiment of the present application at a partial edge region.

[0071] Fig. 19 is a structural schematic diagram of a solar cell according to an embodiment of the present application; Fig. 20 is a structural SEM diagram of a solar cell according to an embodiment of the present application at the junction of the edge region and the middle region; Fig. 21 is a structural SEM diagram of a solar cell according to an embodiment of the present application at the junction of the edge region and the middle region; Fig. 22 is a structural enlarged schematic diagram of a solar cell according to an embodiment of the present application at a partial edge region; Fig. 23 is a structural schematic diagram of a solar cell according to an embodiment of the present application; Fig. 24 is a structural enlarged schematic diagram of a solar cell according to an embodiment of the present application at a partial edge region. DETAILED DESCRIPTION

[0072] In order to make the technical problems to be solved, technical solutions and beneficial effects of the present application clearer, the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and not used to limit the present application.

[0073] It should be noted that when an element is referred to as being "fixed to" or "set on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0074] In addition, the terms "first", "second", "third", etc. are used herein only to describe different instances, and are not used to indicate or imply relative importance or a number of indicated technical features. Thus, features defined with "first", "second", etc. can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise explicitly and specifically limited.

[0075] In the description of the present application, it should be understood that the terms "upper", "lower", "front", "back", "left", "right", etc. indicate the orientation or positional relationship shown in the drawings, and are only used for the convenience of describing the present application and simplifying the description, and thus cannot be understood as limiting the present application, which does not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation.

[0076] In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connection" should be understood broadly, for example, it can be fixed connection, or detachable connection, or integral connection; it can be mechanical connection, or electrical connection; it can be direct connection, or indirect connection through an intermediate medium; it can be the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0077] To solve the above technical problems, in a first aspect, the embodiments of the present application provide a solar cell. The solar cell can be a back contact solar cell, a bifacial solar cell or a hybrid HBC (Hybrid Back Contact) cell, etc. HBC is a back contact heterojunction solar cell, wherein one side of the semiconductor substrate of the hybrid HBC cell is a heterojunction passivation structure, and the other side is a tunneling oxide passivation structure.

[0078] Referring to FIG. 1, the solar cell includes a semiconductor substrate 1, the semiconductor substrate 1 includes opposite first and second surfaces 10 and 11, and a side surface 12 connecting the first and second surfaces 10 and 11. The first surface 10 has an edge region 13 and a middle region 14, the edge region 13 has a first texture structure, and the middle region 14 has a second texture structure, the size of the first texture structure is greater than the size of the second texture structure. For example, the size includes the height of the texture structure (the height from the bottom to the top of the tower), the width of the bottom of the tower, and the length of the edge, etc. For details, please refer to the description later.

[0079] In actual application, the material of the semiconductor substrate is not limited in the embodiments. For example, the semiconductor substrate can be a substrate of any semiconductor material, such as a silicon substrate, a germanium-silicon substrate, a germanium substrate, or a gallium arsenide substrate.

[0080] Compared with the prior art, the first surface 10 has an edge region 13 and a middle region 14, the edge region 13 has a first texture structure, the middle region 14 has a second texture structure, and the size of the first texture structure is greater than the size of the second texture structure. Through this structure, the light trapping effect of the semiconductor substrate 1 can be improved, the light at the edge of the cell is fully utilized, the light absorption rate is increased, and thus the utilization rate of the light by the first surface 10 of the semiconductor substrate 1 is improved, thereby improving the efficiency of the solar cell. Further, by the size of the first texture structure of the edge region being greater than the size of the second texture structure of the middle region, the number of texture structures per unit area of the edge region is less, the surface of the texture structure of the edge region is more regular, and the surface defects formed are also less, thereby facilitating the improvement of the surface passivation effect of the edge region, and further improving the efficiency of the solar cell.

[0081] An interface is formed between the edge region and the middle region. The interface line of the edge region and the middle region is a curve. At this time, the stress of the first surface of the solar cell can be avoided from being too concentrated, and the edge collapse can be reduced.

[0082] As a possible implementation manner, the width W3 of the edge region is greater than 0 microns and less than or equal to 50 microns; the width direction of the edge region is consistent with the vertical direction of the vertical line from the first surface to the second surface. For example, the width W3 of the edge region can be 0.1 microns, 5 microns, 10 microns, 15 microns, 20 microns, 25 microns, 30 microns, 35 microns, 40 microns, 45 microns, or 50 microns, etc.

[0083] Since the width of the edge region is greater than 0 microns, at this time, not only the passivation effect of the solar cell can be improved, thereby improving the cell efficiency of the solar cell, but also the stress of the edge of the solar cell can be reduced, thereby reducing the fragment rate of the solar cell. Further, since the width of the edge region is less than or equal to 50 microns, at this time, the appearance of the solar cell can be avoided from being affected due to the too large edge region, and the antireflection effect of the first surface can be avoided from being affected.

[0084] As a possible implementation manner, the size uniformity of the first texture structure located in the edge region is lower than the size uniformity of the second texture structure located in the middle region. In the case of adopting the above technical solution, the non-uniform first texture structure located in the edge region helps to adjust the stress generated in the silicon wafer cutting process, reduces the risk of micro-cracks caused by stress concentration, and increases the reliability and life of the solar cell.

[0085] The size uniformity can be reflected by a calculation formula: Ra=1 / n∑|Zi|; wherein, Ra is the uniformity degree value, n is the sampling point number, Zi is the height of the i th sampling point, and a unit area can be set for sampling during the sampling process, for example, one square micron, or an electron microscope field of view of a fixed area is taken as the unit area sampling area, and through sampling calculation, the smaller the Ra is, the higher the size uniformity is.

[0086] In an implementation manner, referring to FIG. 1 and FIG. 2, the vertex P of the first texture structure is closer to the light-receiving surface side of the solar cell than the vertex Q of the second texture structure, and the light-receiving surface is the surface of the first surface 10 in FIG. 1 in the direction close to B, that is, the vertex P of the first texture structure is farther away from the back light side of the solar cell than the vertex Q of the second texture structure.

[0087] In the case of the second surface being a plane, the edge region of the semiconductor substrate is thicker than the middle region of the semiconductor substrate, and the anti-fragmentation structure force of the semiconductor substrate can be increased, and the fragmentation rate of the solar cell can be reduced.

[0088] In an implementation manner, referring to FIG. 1 to FIG. 3, the height of the first texture structure is greater than the height of the second texture structure; and / or, the size of the tower bottom 5 of the first texture structure is greater than the size of the tower bottom 6 of the second texture structure (the tower bottom size includes the width of the tower bottom, the side length of the tower bottom, and the diagonal length of the tower bottom); and / or, the edge length of the first texture structure is greater than the edge length of the second texture structure.

[0089] In the case of the above technical solution, because the height of the first texture structure is greater than the height of the second texture structure, or the edge length of the first texture structure is greater than the edge length of the second texture structure, or the width W4 of the tower bottom of the first texture structure is greater than the width W5 of the tower bottom of the second texture structure, the number of the first texture structures in the unit area of the edge region is less, and the surface defects are also less, thereby facilitating the improvement of the surface passivation effect of the edge region.

[0090] The first texture structure can be a pyramid structure, or a lateral prism structure, etc. Hereinafter, the first texture structure and the second texture structure are taken as the pyramid structure as an example for description, and it should be noted that the following description is only for understanding, and is not used for specific limitation.

[0091] As a possible implementation, referring to FIG. 1 and FIG. 2, when the first texture structure is a pyramid structure, the height H1 of the first texture structure is greater than or equal to 4 μm and less than or equal to 8 μm; and / or, the base width W1 of the first texture structure is greater than or equal to 5 μm and less than or equal to 9 μm; and / or, the edge length L1 of the first texture structure is less than 10 μm. Preferably, the edge length L1 of the first texture structure is greater than or equal to 5 μm and less than or equal to 7 μm. For example, the height H1 of the first texture structure can be 4 μm, 4.5 μm, 5 μm, 5.5 μm, 6 μm, 6.5 μm, 7 μm, 7.5 μm or 8 μm, etc.; the base width W1 of the first texture structure can be 5 μm, 5.5 μm, 6 μm, 6.5 μm, 7 μm, 7.5 μm, 8 μm, 8.5 μm or 9 μm, etc.; the edge length L1 of the first texture structure can be 5 μm, 5.5 μm, 6 μm, 6.5 μm, 7 μm, 7.5 μm, 8 μm, 8.5 μm, 9 μm, 9.5 μm or 9.9 μm, etc. Preferably, the edge length L1 of the first texture structure can be 5 μm, 5.5 μm, 6 μm, 6.5 μm or 7 μm, etc. It should be noted that the height of the first texture structure mentioned above refers to the vertical distance from the top of the first texture structure to the bottom of the valley.

[0092] With the above technical solution, the height of the first texture structure is greater than or equal to 4 μm, which can reduce or avoid the situation that the light trapping effect of the first texture structure is not obvious due to the small height of the first texture structure, thereby ensuring that more light is refracted into the semiconductor substrate through the first texture structure, and further ensuring that the solar cell has a high photoelectric conversion efficiency.

[0093] As a possible implementation, referring to FIG. 1 and FIG. 2, when the second texture structure is a pyramid structure, the height H2 of the second texture structure is greater than or equal to 1 μm and less than or equal to 4 μm; and / or, the base width W2 of the second texture structure is greater than or equal to 2 μm and less than or equal to 5 μm; and / or, the edge length L2 of the second texture structure is less than 6 μm. Preferably, the edge length L2 of the second texture structure is greater than or equal to 2 μm and less than or equal to 3 μm. For example, the height H2 of the second texture structure can be 1 μm, 1.1 μm, 1.5 μm, 1.7 μm, 1.9 μm, 2 μm, 2.1 μm, 2.5 μm, 2.7 μm, 2.9 μm, 3 μm, 3.5 μm, 3.8 μm or 4 μm, etc.; the base width W2 of the second texture structure can be 2 μm, 2.1 μm, 2.5 μm, 2.7 μm, 2.9 μm, 3 μm, 3.5 μm, 3.8 μm, 4 μm or 5 μm, etc.; and the edge length L2 of the second texture structure can be 2 μm, 2.1 μm, 2.5 μm, 2.7 μm, 2.9 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm, 5 μm, 5.5 μm or 5.9 μm, etc. Preferably, the edge length L2 of the second texture structure can be 2 μm, 2.1 μm, 2.5 μm, 2.7 μm, 2.9 μm or 3 μm, etc.

[0094] In the case of the above technical solution, the height of the second texture structure is greater than or equal to 1 μm, which can reduce or avoid the situation that the light trapping effect of the second texture structure is not obvious due to the small height of the second texture structure, thereby ensuring that more light is refracted into the semiconductor substrate through the second texture structure, and further ensuring that the solar cell has a high photoelectric conversion efficiency.

[0095] As a possible implementation, referring to FIG. 4, the side surface 12 includes a third texture structure region 15, the third texture structure region is close to the first surface 10, and the texture structure in the third texture structure region is in the shape of an inverted pyramid.

[0096] In an optional manner, the ratio of the width of the third texture structure region 15 to the width of the side surface 12 is less than 80%, for example, the ratio of the width of the third texture structure region 15 to the width of the side surface 12 is 10%, 20%, 30%, 40%, 50%, 60%, 70% or 80%. The width direction of the third texture structure region and the width direction of the side surface are both perpendicular directions from the first surface to the second surface.

[0097] As a possible implementation, referring to FIG. 4 and FIG. 5, the side surface 12 comprises a fourth textured region 4, and the fourth textured region comprises a plurality of tower base structures 16, the plurality of tower base structures 16 are arranged along a first straight line L3, and the first straight line L3 is inclined relative to a side edge of the side surface 12, the side edge being a side edge formed between the side surface 12 and the first surface 10, or a side edge formed between the side surface 12 and the second surface 11.

[0098] In the case of the above technical solution, since the plurality of tower base structures 16 are arranged along the first straight line, and the first straight line is inclined relative to the side edge of the side surface 12, the structural strength of the solar cell can be enhanced, and the solar cell fragment can be prevented from breaking, so as to reduce the fragment rate of the solar cell.

[0099] In an optional manner, the plurality of first straight lines are parallel to each other; and / or, referring to FIG. 5, an included angle A between the first straight line and the side edge of the side surface 12 is greater than or equal to 15° and less than or equal to 75°; for example, 15°, 20°, 30°, 45°, 60° or 75°, etc. And / or, the length of the first straight line is greater than the thickness of the semiconductor substrate 1, and the thickness direction of the semiconductor substrate 1 is consistent with the vertical direction of the first surface 10 to the second surface 11.

[0100] For example, referring to FIG. 4, the above-mentioned side surface 12 can simultaneously comprise the third textured region 15 and the fourth textured region, and the ratio of the width of the third textured region 15 to the width of the side surface 12 is less than 80%, and the width direction W6 of the third textured region is the vertical direction from the first surface to the second surface. The above-mentioned third textured region 15 is close to the first surface of the semiconductor substrate 1, or, referring to FIG. 5, the side surface 12 only comprises the fourth textured region; or, the side surface comprises the third textured region, and the ratio of the width of the third textured region to the width of the side surface is less than 80%, and the remaining side surface can be a plane.

[0101] In an optional manner, the sum of the width of the third textured region and the width of the fourth textured region in the direction from the first surface to the second surface is equal to the total width of the side surface.

[0102] As a possible implementation, the side surface is at least sequentially stacked with a tunneling silicon oxide layer, an N-type doped polysilicon layer and a silicon nitride layer; or, the side surface is sequentially stacked with a tunneling silicon oxide layer, an N-type doped polysilicon layer, a silicon nitride layer, an intrinsic polysilicon layer and a doped microcrystalline silicon layer. In the case of the above technical solution, the composite passivation of the composite stack better reduces the side edge recombination of the semiconductor substrate.

[0103] As a possible implementation, the third textured region is sequentially stacked with an amorphous silicon layer.

[0104] As a possible implementation manner, the fourth textured structure region is sequentially stacked with a tunneling silicon oxide layer, a doped polysilicon layer and a silicon nitride layer.

[0105] As a possible implementation manner, the third textured structure region and the fourth textured structure region are both coated with an amorphous silicon layer, that is, the fourth textured structure region is sequentially stacked with a tunneling silicon oxide layer, a doped polysilicon layer, a silicon nitride layer and an amorphous silicon layer.

[0106] As a possible implementation manner, the first textured structures on the edge region are connected to form a first textured structure group, and the edge region further includes a fifth textured structure, and the size of the fifth textured structure is smaller than that of the first textured structure. Specifically, the edge region has a plurality of first textured structure groups, and the plurality of first textured structure groups have the fifth textured structure therebetween, and the size of the fifth textured structure is smaller than that of the first textured structure. Through the above scheme, the first textured structure region can provide light trapping effect, and the fifth textured structure can provide the toughness of the cell piece, further improving the anti-fragmentation capability.

[0107] In combination with the foregoing description, when the solar cell is a back contact solar cell, referring to FIG. 1, the second surface 11 has the first regions 17 and the second regions 18 alternately distributed along the first direction B, and the solar cell further includes: the first doped semiconductor layer 2 arranged on the first regions 17; the second doped semiconductor layer 3 arranged on the second regions 18 and extending to cover part of the first doped semiconductor layer 2; and the conductive type of the second doped semiconductor layer 3 is opposite to that of the first doped semiconductor layer 2.

[0108] When the solar cell is a bifacial solar cell, the solar cell further includes: the first doped semiconductor layer formed on the first surface; and the second doped semiconductor layer formed on the second surface, and the conductive type of the second doped semiconductor layer is opposite to that of the first doped semiconductor layer.

[0109] In summary, when the solar cell is in a working state, the first doped semiconductor layer and the second doped semiconductor layer can effectively shunt carriers, which is conducive to forming a photoelectric current. Further, the solar cell can be a back contact solar cell or a bifacial solar cell, and is widely applicable.

[0110] In a second aspect, the embodiments of the present application further provide a photovoltaic module. The photovoltaic module includes the solar cell described in the above technical solution, and a plurality of solar cells form a cell string.

[0111] The photovoltaic module provided by the embodiment of the present application adopts the above-mentioned solar cell structure, and multiple solar cells are connected to form a cell string through connection. When the first texture structure with a large size is formed at the edge region of the semiconductor substrate, more light can be reflected to the surfaces of the solar cells close to each other, a "conjugate effect" is formed, and the light trapping effect of the whole module is improved.

[0112] The following describes the solar cell by taking several possible cases as examples. It should be understood that the following description is only for understanding and is not used for specific definition.

[0113] Embodiment 1

[0114] When the first texture structure is a pyramid structure, the tower height H1 of the first texture structure is 4 μm, the tower base width W1 of the first texture structure is 5 μm, and the edge length L1 of the first texture structure is 9.9 μm. When the second texture structure is a pyramid structure, the tower height H2 of the second texture structure is 1 μm, the tower base width W2 of the second texture structure is 2 μm, and the edge length L2 of the second texture structure is 5.9 μm.

[0115] Embodiment 2

[0116] When the first texture structure is a pyramid structure, the tower height H1 of the first texture structure is 6 μm, the tower base width W1 of the first texture structure is 7 μm, and the edge length L1 of the first texture structure is 5.9 μm. When the second texture structure is a pyramid structure, the tower height H2 of the second texture structure is 2.5 μm, the tower base width W2 of the second texture structure is 3 μm, and the edge length L2 of the second texture structure is 3.9 μm.

[0117] Embodiment 3

[0118] When the first texture structure is a pyramid structure, the tower height H1 of the first texture structure is 8 μm, the tower base width W1 of the first texture structure is 9 μm, and the edge length L1 of the first texture structure is 5 μm. When the second texture structure is a pyramid structure, the tower height H2 of the second texture structure is 4 μm, the tower base width W2 of the second texture structure is 5 μm, and the edge length L2 of the second texture structure is 2 μm.

[0119] Embodiment 4

[0120] The semiconductor substrate of the embodiment is specifically as follows, and the others are the same as those in Embodiment 1.

[0121] The side surface of the semiconductor substrate comprises a tower base structure of a pyramid; the multiple tower base structures are arranged along a first straight line, and the included angle between the first straight line and the side edge of the side surface is equal to 15°.

[0122] Embodiment 5

[0123] The semiconductor substrate of this example is as follows, and the other aspects are the same as those of Example 1.

[0124] The side surface of the semiconductor substrate includes a base structure of a pyramid; and a plurality of the base structures are arranged along a first straight line, and an angle between the first straight line and a side of the side surface is equal to 45°.

[0125] Example 6

[0126] The semiconductor substrate of this example is as follows, and the other aspects are the same as those of Example 1.

[0127] The side surface of the semiconductor substrate includes a base structure of a pyramid; and a plurality of the base structures are arranged along a first straight line, and an angle between the first straight line and a side of the side surface is equal to 60°.

[0128] Example 7

[0129] The semiconductor substrate of this example is as follows, and the other aspects are the same as those of Example 1.

[0130] The side surface of the semiconductor substrate includes a base structure of a pyramid; and a plurality of the base structures are arranged along a first straight line, and an angle between the first straight line and a side of the side surface is equal to 75°.

[0131] Example 8

[0132] The semiconductor substrate of this example is as follows, and the other aspects are the same as those of Example 1.

[0133] The width of the edge region is 1 μm, and the width direction of the edge region is coincident with the vertical direction of the perpendicular line from the first surface to the second surface.

[0134] Example 9

[0135] The semiconductor substrate of this example is as follows, and the other aspects are the same as those of Example 1.

[0136] The width of the edge region is 10 μm, and the width direction of the edge region is coincident with the vertical direction of the perpendicular line from the first surface to the second surface.

[0137] Example 10

[0138] The semiconductor substrate of this example is as follows, and the other aspects are the same as those of Example 1.

[0139] The width of the edge region is 50 μm, and the width direction of the edge region is coincident with the vertical direction of the perpendicular line from the first surface to the second surface.

[0140] Example 11

[0141] The semiconductor substrate of this example is as follows, and the other conditions are the same as in Example 1. The ratio of the width of the third textured region to the width of the side surface is 20%.

[0142] Example 12

[0143] The semiconductor substrate of this example is as follows, and the other conditions are the same as in Example 1. The ratio of the width of the third textured region to the width of the side surface is 10%.

[0144] Example 13

[0145] The semiconductor substrate of this example is as follows, and the other conditions are the same as in Example 1. The ratio of the width of the third textured region to the width of the side surface is 1%.

[0146] Comparative Example 1

[0147] When the first textured structure is a pyramid structure, the height of the first textured structure is less than 4 μm, the width of the base of the first textured structure is less than 5 μm, and the length of the edge of the first textured structure is less than 9.9 μm. When the second textured structure is a pyramid structure, the height of the second textured structure is less than 1 μm, the width of the base of the second textured structure is less than 2 μm, and the length of the edge of the second textured structure is less than 5.9 μm.

[0148] Comparative Example 2

[0149] When the first textured structure is a pyramid structure, the height of the first textured structure is greater than 8 μm, the width of the base of the first textured structure is greater than 9 μm, and the length of the edge of the first textured structure is greater than 5 μm. When the second textured structure is a pyramid structure, the height of the second textured structure is greater than 4 μm, the width of the base of the second textured structure is greater than 5 μm, and the length of the edge of the second textured structure is greater than 2 μm.

[0150] Comparative Example 3

[0151] The semiconductor substrate of this example is as follows, and the other conditions are the same as in Example 1.

[0152] The side surface of the semiconductor substrate includes a base structure of a pyramid; a plurality of base structures of the pyramid are arranged along a first straight line, and the angle between the first straight line and a side of the side surface is less than 15°.

[0153] Comparative Example 4

[0154] The semiconductor substrate of this example is as follows, and the other conditions are the same as in Example 1.

[0155] The side surface of the semiconductor substrate includes a base structure of a pyramid; a plurality of base structures of the pyramid are arranged along a first straight line, and the angle between the first straight line and a side of the side surface is greater than 75°.

[0156] Comparative Example 5

[0157] The semiconductor substrate of the present embodiment is specifically as follows, and the others are the same as those of Embodiment 1.

[0158] The width of the edge region is greater than 50 microns, and the width direction of the edge region is consistent with the vertical direction of the vertical line between the first surface and the second surface.

[0159] Comparative Example 6

[0160] The semiconductor substrate of the present embodiment is specifically as follows, and the others are the same as those of Embodiment 1, and the ratio of the width of the third textured region to the width of the side surface is greater than 80%.

[0161] Embodiment 14

[0162] The solar cells according to Comparative Examples 1-6 are respectively formed into photovoltaic modules, and the rated power formed according to the cell efficiency is increased by less than 0.5% after the modules are formed.

[0163] Table 1 Test parameter table of solar cells manufactured in Embodiments 1-6 and Comparative Examples 6

[0164] The existing solar cells can include double-sided contact cells (such as TOPCON cells) and back contact cells. Among them, the TOPCON cell is a cell including a passivation contact structure on the back surface and having boron diffusion on the front surface. The passivation contact structure is a structure including a tunneling silicon oxide and a phosphorus-doped polysilicon layer formed on the back surface of the semiconductor substrate. By providing the passivation contact structure, the recombination on the back surface of the cell can be reduced. However, in the actual manufacturing process, the passivation contact structure on the back surface will be plated to the front surface during deposition, causing short circuit between the front and back surfaces. The back contact cell refers to a solar cell in which the light-receiving surface of the cell piece has no electrode, and the positive and negative electrodes are both arranged on the light-irradiated side of the cell piece, so that the shading of the cell piece by the electrodes can be reduced, the short-circuit current of the cell piece can be increased, and the energy conversion efficiency of the cell piece can be improved. Specifically, the existing back contact cell includes a semiconductor substrate, and a first semiconductor layer and a second semiconductor layer arranged on the same surface of the semiconductor substrate and having opposite conduction types. In the actual manufacturing process, when the first semiconductor layer is manufactured on the back surface of the semiconductor substrate, the first semiconductor layer arranged on the whole layer needs to be selectively etched under the protection of a mask layer, so as to facilitate the subsequent formation of the second semiconductor layer. Moreover, after the selective etching, the front surface of the semiconductor substrate needs to be textured to improve the light trapping effect of the front surface of the back contact cell and improve the light utilization rate of the back contact cell.

[0165] However, when the first semiconductor layer and the mask layer are formed on the back side of the semiconductor substrate, the first semiconductor layer and the mask layer are also formed on the side surface of the semiconductor substrate and at least part of the front surface of the semiconductor substrate due to the existence of the wrap-around plating. In order to make the front surface of the semiconductor substrate have a larger refractive index, the existing manufacturing method removes all the mask layer on the front surface of the semiconductor substrate before the texturing operation, so that the surface of each part of the front surface of the semiconductor substrate is exposed during the subsequent texturing operation, and the texture structure with uniform distribution and substantially the same morphology can be formed thereon. Due to the influence of etching precision or high-temperature etching agent, the mask layer wrapped around to the side surface of the semiconductor substrate (especially the part near the front surface of the side surface) is over-etched, which causes the first semiconductor layer wrapped around to at least part of the area on the side surface of the semiconductor substrate to be etched due to the lack of protection of the mask layer during the texturing operation, and further causes the passivation effect of the side surface of the semiconductor substrate to be poor, which is not conducive to improving the conversion efficiency of the back contact cell.

[0166] To solve the above technical problems, in a third aspect, the embodiments of the present application provide a solar cell. The solar cell can be a dual-sided contact cell. For example, as shown in FIG. 23, the solar cell can include a first type electrode and a second type electrode (not shown in the figure). The first type electrode is arranged on the front surface side of the semiconductor substrate 1, and the second type electrode is arranged on the back surface side of the semiconductor substrate 1; the first type electrode and the second type electrode are opposite in polarity.

[0167] Alternatively, the solar cell provided by the embodiments of the present application can also be a back contact cell. For example, as shown in FIG. 6, the solar cell can include a first type electrode and a second type electrode (not shown in the figure). The first type electrode and the second type electrode are alternately and spacedly arranged on the back surface opposite to the front surface of the semiconductor substrate 1. The first type electrode and the second type electrode are opposite in polarity. In this way, the light utilization rate on the front surface side of the cell can be improved.

[0168] As shown in FIG. 6 and FIG. 23, the solar cell provided by the embodiment of the present application comprises a semiconductor substrate 1. The front surface of the semiconductor substrate 1, i.e. the first surface, comprises an edge region 13 at the edge and an intermediate region 14 inside the edge region 13 and adjacent to the edge region 13. In the priority application, the edge region is the first region and the intermediate region is the second region. It is to be noted that the first region and the second region in the priority application are different from the first region and the second region in the present application. In the front surface of the semiconductor substrate 1, the surface of the edge region 13 comprises a polishing structure 105 and the surface of the intermediate region 14 comprises a pyramid structure 104. In the solar cell provided by the embodiment of the present application, the semiconductor substrate 1 is used to absorb photons and generate photo-generated carriers, and the first semiconductor layer 19 and the second semiconductor layer 20 are used to split and collect the carriers. The surface of the intermediate region 14 comprises the pyramid structure 104, which can make the surface of the intermediate region 14 have a higher light trapping effect and improve the light utilization rate of the semiconductor substrate 1. By providing the edge region 13 on the front surface of the semiconductor substrate 1, the surface of the edge region 13 comprises the polishing structure 105, i.e. the surface of the edge region 13 is relatively flat. First, this structure is conducive to reducing the physical defects of the edge of the semiconductor substrate 1 and reducing the carrier recombination rate of the edge of the semiconductor substrate 1. At the same time, the edge region structure is neat, which can also reduce the breakage rate. Ultimately, the optical absorption performance of the cell itself is high, which ensures the high conversion efficiency and production yield of the solar cell.

[0169] From the structural aspect, the semiconductor substrate included in the solar cell is used to absorb photons and generate photo-generated carriers. In some cases, as shown in FIG. 6 and FIG. 23, the solar cell further comprises a first semiconductor layer 19 and a second semiconductor layer 20 having opposite conductive types, for splitting and collecting the carriers.

[0170] Specifically, the specific conductive types of the first semiconductor layer and the second semiconductor layer can be set according to actual needs. For example, the conductive type of the first semiconductor layer can be N type and the conductive type of the second semiconductor layer can be P type. Alternatively, the conductive type of the first semiconductor layer can be P type and the conductive type of the second semiconductor layer can be N type.

[0171] The embodiment of the present application does not specifically limit the forming range of the first semiconductor layer and the second semiconductor layer, which can be set according to the device type of the solar cell and actual needs.

[0172] For example, as shown in FIG. 23, in the case of a double-sided contact cell, the first semiconductor layer 19 can be arranged on at least the intermediate region 14 of the front surface of the semiconductor substrate 1. The second semiconductor layer 20 is arranged on at least a part of the back surface of the semiconductor substrate 1, i.e. the second surface.

[0173] For example, as shown in FIG. 6, in the case of a back contact solar cell, the first semiconductor layer 19 can be provided only on the back surface and the side surface of the semiconductor substrate 1. Alternatively, in some cases, as shown in FIG. 6, the first semiconductor layer 19 can also be extended to cover the edge region 13 from the side surface of the semiconductor substrate 1. The second semiconductor layer 20 can be provided only on the back surface of the semiconductor substrate 1. Alternatively, in some cases, as shown in FIG. 6, the second semiconductor layer 20 can also be provided on the side surface of the semiconductor substrate 1, and on the side surface of the semiconductor substrate 1, the first semiconductor layer 19 and the second semiconductor layer 20 are electrically isolated. In this case, the side surface of the semiconductor substrate 1 is not only provided with the first semiconductor layer 19, but also provided with the second semiconductor layer 20 and the anti-reflection layer 21 for isolating the first semiconductor layer 19 and the second semiconductor layer 20 of opposite conductivity types, so as to improve the passivation effect, reduce the side surface carrier recombination rate, and at the same time, the first semiconductor layer 19, the anti-reflection layer 21 and the second semiconductor layer 20 can also provide strong physical protection for the side surface of the semiconductor substrate 1, thereby improving the service life of the solar cell.

[0174] From the aspect of the setting range, in the case of a back contact solar cell, on the back surface side of the semiconductor substrate, the first semiconductor layer and the second semiconductor layer can be spaced apart along a direction parallel to the back surface of the semiconductor substrate.

[0175] Alternatively, as shown in FIG. 6, the back surface of the semiconductor substrate 1 has a third region 22 located at the edge, and a fourth region 23 located inside the third region 22 and adjacent to the third region 22. The width of the third region 22 in the direction from the center to the edge of the back surface of the semiconductor substrate 1 can be set according to actual needs, which is not specifically limited here. On the fourth region 23, the second semiconductor layer 20 also extends to cover part of the first semiconductor layer 19; in this case, on the fourth region 23, the part where the first semiconductor layer 19 and the second semiconductor layer 20 are stacked can be in electrical contact, so as to reduce the risk of hot spots of the solar cell; or an insulating layer (such as a silicon oxide layer, a silicon nitride layer or an aluminum oxide layer) can also be provided between the first semiconductor layer and the second semiconductor layer, so as to improve the conversion efficiency of the solar cell in the forward voltage region. On the third region 22, only one of the first semiconductor layer and the second semiconductor layer can be provided, or the first semiconductor layer 19 and the second semiconductor layer 20 can be sequentially stacked in the direction away from the semiconductor substrate 1. In this case, on the third region 22 located at the edge of the back surface of the semiconductor substrate 1, the first semiconductor layer 19 and the second semiconductor layer 20 are stacked, which are two film layers having passivation effect, so as to facilitate reducing the number of defects on the surface of the third region 22 and reducing the carrier recombination rate.

[0176] In terms of structure and material, the first semiconductor layer can only include the first doped semiconductor layer directly disposed on the semiconductor substrate. Alternatively, as shown in FIG. 6 and FIG. 23, the first semiconductor layer 19 can also include the first doped semiconductor layer 2 and a first interface passivation layer 25 disposed between the semiconductor substrate 1 and the first doped semiconductor layer 2. In this way, selective collection of carriers can be achieved, and the carrier recombination rate of the corresponding region surface of the first surface or the second surface of the semiconductor substrate 1 is reduced, further improving the photoelectric conversion efficiency of the solar cell.

[0177] In terms of material, the material of the first doped semiconductor layer included in the first semiconductor layer can include any one of a semiconductor material such as silicon, silicon-germanium, germanium, or gallium arsenide. In terms of the arrangement form of the substance, the crystal phase of the first semiconductor layer and / or the second semiconductor layer can be amorphous, microcrystalline, nanocrystalline, single crystal, or polycrystalline, etc.

[0178] When the first semiconductor layer further includes the first interface passivation layer, the material and thickness of the first interface passivation layer can be set according to the material of the first doped semiconductor layer and actual needs, which are not specifically limited here. For example, when the material of the first doped semiconductor layer is doped polysilicon, the first interface passivation layer is a tunneling passivation layer. For another example, when the material of the first doped semiconductor layer includes at least one of doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon, the first interface passivation layer is an intrinsic amorphous silicon layer, an intrinsic microcrystalline silicon layer, an intrinsic nanocrystalline silicon layer, or a mixed layer of the above three.

[0179] Optionally, the first semiconductor layer includes a tunneling oxide layer and a doped crystalline silicon layer stacked in sequence in a direction away from the semiconductor substrate.

[0180] As for the second semiconductor layer, the second semiconductor layer can only include the second doped semiconductor layer disposed on the semiconductor substrate (the second doped semiconductor layer can also cover part of the first semiconductor layer). Alternatively, as shown in FIG. 6 and FIG. 23, the second semiconductor layer 20 can also include the second doped semiconductor layer 3 and a second interface passivation layer 27 disposed between the semiconductor substrate 1 and the second doped semiconductor layer 3 (when the second doped semiconductor layer 3 can also cover part of the first semiconductor layer 19, the second interface passivation layer 27 is also disposed between the first semiconductor layer 19 and the second doped semiconductor layer 3). In this way, selective collection of carriers can be achieved, and the carrier recombination rate of the corresponding region surface of the second surface of the semiconductor substrate 1 is reduced, further improving the photoelectric conversion efficiency of the solar cell.

[0181] The selection of the material of the second doped semiconductor layer and the second interface passivation layer can refer to the selection of the material of the first doped semiconductor layer and the first interface passivation layer in the foregoing, which will not be repeated here.

[0182] The material of the first doped semiconductor layer included in the first semiconductor layer and the material of the second doped semiconductor layer included in the second semiconductor layer can be the same or different. For example, the material of the first doped semiconductor layer included in the first semiconductor layer and the material of the second doped semiconductor layer included in the second semiconductor layer can both include amorphous silicon. For another example, the material of the first doped semiconductor layer included in the first semiconductor layer can include polycrystalline silicon, and the material of the second doped semiconductor layer included in the second semiconductor layer can include amorphous silicon.

[0183] As the first semiconductor layer includes the first interface passivation layer, and the second semiconductor layer also includes the second interface passivation layer, the materials of the two can be the same or different, which are determined according to the material of the first doped semiconductor layer included in the first semiconductor layer and the material of the second doped semiconductor layer included in the second semiconductor layer respectively.

[0184] Optionally, the second semiconductor layer can include an intrinsic semiconductor passivation layer and a doped silicon layer which are sequentially stacked in a direction away from the semiconductor substrate. The intrinsic semiconductor passivation layer can include an intrinsic amorphous silicon layer, an intrinsic microcrystalline silicon layer, an intrinsic nanocrystalline silicon layer, or a mixed layer of the above three. The doped silicon layer can include a doped amorphous silicon layer, a doped microcrystalline silicon layer, a doped nanocrystalline silicon layer, or a mixed layer of the above three.

[0185] In addition, the thickness of the first semiconductor layer and the second semiconductor layer is not limited in the embodiments of the present application.

[0186] For example, as shown in FIG. 6, the solar cell can further include an anti-reflection layer 21. The anti-reflection layer 21 is arranged on the front surface of the semiconductor substrate 1, or the anti-reflection layer 21 can be arranged on the side surface of the semiconductor substrate 1 in addition to the front surface of the semiconductor substrate 1.

[0187] Specifically, as shown in FIG. 6, the anti-reflection layer 21 is arranged on the side of the first semiconductor layer 19 away from the semiconductor substrate 1. When the first semiconductor layer 19, the second semiconductor layer 20, and the anti-reflection layer 21 are arranged on the side surface of the semiconductor substrate 1, the first semiconductor layer 19, the anti-reflection layer 21, and the second semiconductor layer 20 are sequentially stacked in a direction away from the semiconductor substrate 1 on the side surface of the semiconductor substrate 1. At this time, the first semiconductor layer 19 and the second semiconductor layer 20 arranged on the side surface of the semiconductor substrate 1 and having opposite conductive types can be isolated by the anti-reflection layer 21, preventing short circuit caused by electric leakage, without the need of forming other insulating layers, which is conducive to simplifying the structure of the cell and reducing the manufacturing cost of the cell.

[0188] The structure and material of the anti-reflection layer can be arranged according to actual needs.

[0189] Exemplarily, the antireflection layer can include, in sequence from the direction away from the semiconductor substrate, an aluminum oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer. In this case, the antireflection layer has good passivation and antireflection effects, which is conducive to improving the conversion efficiency of the solar cell.

[0190] Optionally, the solar cell can further include an aluminum oxide layer and a silicon nitride layer, and the aluminum oxide layer and the silicon nitride layer are arranged on at least the front surface of the semiconductor substrate. In this way, the carrier recombination rate on the front surface side of the solar cell is reduced, and the reflectivity on the front surface side is reduced, thereby improving the working performance of the solar cell.

[0191] Optionally, the solar cell can further include an aluminum oxide layer and a polysilicon layer (which can be part of the first semiconductor layer plated on the edge region and the side surface of the semiconductor substrate). The aluminum oxide layer is arranged on at least the front surface of the semiconductor substrate; the polysilicon layer is arranged between the aluminum oxide layer and the part of the edge region of the front surface of the semiconductor substrate, and the polysilicon layer is arranged on at least part of the side surface of the semiconductor substrate. In this way, the edge region of the front surface of the semiconductor substrate not only has the aluminum oxide layer, but also has the polysilicon layer, which is conducive to further reducing the carrier recombination rate of the edge region of the front surface of the semiconductor substrate under the combined passivation effect of the two. Secondly, the polysilicon layer is arranged on the side surface of the semiconductor substrate, which not only passivates the side surface of the semiconductor substrate, but also has a high physical protection effect on the side surface of the semiconductor substrate. The presence of the polysilicon layer can isolate the side surface of the semiconductor substrate from the external environment, reduce the risk of damage such as scratches on the side surface of the semiconductor substrate due to extrusion, collision, and other factors after transportation or packaging. At the same time, it can also reduce the risk of water vapor and other substances entering the battery from the side surface of the battery, thereby improving the service life of the solar cell.

[0192] From the aspect of surface topography, as shown in FIG. 6, the surface reflectivity of the middle region 14 in the front surface of the semiconductor substrate 1 can be less than the surface reflectivity of the edge region 13. In this case, the texture structure of the surface of the edge region 13 can be different from the topography of the texture structure of the surface of the middle region 14. In this case, it is conducive to making the surface of the middle region 14 in the middle region of the front surface of the semiconductor substrate have a smaller reflectivity, which is conducive to improving the light utilization rate of the semiconductor substrate.

[0193] As for the edge region in the front surface of the semiconductor substrate, the surface reflectivity of the edge region is relatively large, which will affect the light absorption of the front surface of the semiconductor substrate. In addition, Figs. 9 to 19 show a possible manufacturing process of the solar cell provided in the embodiments of the present application. In the actual manufacturing process, as shown in Figs. 12 and 13, the surface of the semiconductor substrate 1 can be subjected to a preliminary polishing treatment before the first semiconductor layer 19 is formed. The polishing structure 105 has the same morphology as that of the polishing structure 105 in the edge region 13 of the front surface of the semiconductor substrate 1. At this time, the surface reflectivity of the semiconductor substrate 1 is relatively large, the specific surface is small, and the surface is relatively flat, which is beneficial to improve the formation quality and field passivation effect of the first semiconductor layer 19 on the semiconductor substrate 1. In addition, a mask layer 28 having a protective effect can be covered on the surface of the edge region 13 when the texturing treatment is performed to make the front surface of the semiconductor substrate 1 have the pyramid structure 104. The etching solution of the texturing treatment is difficult or unable to contact the edge region 13 of the front surface of the semiconductor substrate 1, so that the surface reflectivity of the edge region 13 is greater than that of the middle region 14 (the surface reflectivity of the middle region 14 subjected to the texturing treatment is relatively low, which can meet the light trapping requirement). The mask layer 28 can play a protective role in the patterning treatment of the first semiconductor layer 19. Due to the existence of the plating, the first semiconductor layer 19 and the mask layer 28, which are originally formed on the back surface of the semiconductor substrate 1, are also formed on the side surface and at least part of the front surface of the semiconductor substrate 1. The mask layer 28 on the front surface of the semiconductor substrate 1 needs to be selectively etched before the texturing treatment to reduce the proportion of the edge region 13 with relatively large surface reflectivity in the first surface. However, if the mask layer 28 on the front surface is completely removed, the mask layer 28 on the side surface of the semiconductor substrate 1 will be excessively etched, which will affect the passivation of the first semiconductor layer 19 to the side surface of the semiconductor substrate 1.

[0194] Alternatively, as shown in Fig. 23, the front surface of the semiconductor substrate 1 can be subjected to the texturing treatment before the first semiconductor layer 19 is formed. The pyramid structure 104 has the same morphology as that of the pyramid structure 104 in the middle region 14 of the front surface of the semiconductor substrate 1. At this time, the surface reflectivity of the semiconductor substrate 1 is relatively small, the specific surface is large, and the surface light trapping effect is good. However, the front surface is relatively rough, and after the first semiconductor layer 19 is formed, the edge region on the side surface and even the back surface of the semiconductor substrate 1 also has the first semiconductor layer 19. At this time, the de-plating treatment needs to be performed under the protection of the corresponding mask layer. And the polishing treatment is performed on the surface of the edge region 13 on the front surface to make the surface of the edge region 13 relatively flat, which is beneficial to improve the formation quality and field passivation effect of the surface passivation layer on the semiconductor substrate 1.

[0195] It can be seen that the proportion of the edge region in the first surface can be determined according to the light trapping requirements for the front surface of the semiconductor substrate and the passivation requirements for the side surface of the semiconductor substrate in the actual application scenario.

[0196] For example, the width of the edge region can be less than or equal to 200 μm in the direction from the center of the front surface of the semiconductor substrate to the edge. For example, the width of the edge region can be 200 μm, 180 μm, 150 μm, 120 μm, 100 μm, 80 μm, 50 μm, 40 μm, 30 μm, 20 μm, or 10 μm, etc.

[0197] Optionally, the width of the edge region can be less than or equal to 30 μm.

[0198] It is worth noting that in the case of a back contact solar cell, because the surface reflectivity of the edge region and the middle region is different (at this time the topography of the texture structure on the surface of the two regions is different), the surface of the edge region still has the above-mentioned mask layer during the texturing process. This case can indicate that after the etching process for removing part of the mask layer around the front surface, the mask layer around the semiconductor substrate side is at least partially retained, so that the mask layer can fully protect the first semiconductor layer around the semiconductor substrate at least partially on the side of each region during the texturing operation, so that the first semiconductor layer on the side surface of the semiconductor substrate is at least partially retained, so that the first semiconductor layer has a high passivation effect on the side surface of the semiconductor substrate, reduces the carrier recombination rate, and helps to improve the conversion efficiency of the solar cell. At the same time, the first semiconductor layer also has a high physical protection effect on the side surface of the semiconductor substrate, which can isolate the side surface of the semiconductor substrate from the external environment, reduce the risk of damage such as scratches on the side surface of the semiconductor substrate due to extrusion, collision, etc. after transportation or packaging. At the same time, it can also reduce the risk of water vapor and other factors entering the battery from the side surface of the battery, thereby improving the service life of the solar cell.

[0199] In the case of a double-sided contact solar cell, because the surface reflectivity of the edge region and the middle region is different (at this time the topography of the texture structure on the surface of the two regions is different), when the edge region surface has a polishing structure, it means that during the process of removing the first semiconductor layer, the first semiconductor layer on the side surface and the back surface is completely removed, which can reduce the risk of electric leakage.

[0200] In addition, although the surface reflectivity of the edge region in the front surface of the semiconductor substrate is relatively high, the width of the edge region is less than or equal to 200 μm, i.e., the area ratio of the edge region in the front surface of the semiconductor substrate is relatively small, and thus the edge region has a relatively small effect on the light absorption of the front surface of the semiconductor substrate. Therefore, the presence of the middle region with a relatively large area ratio in the front surface of the semiconductor substrate makes the front surface of the semiconductor substrate have a relatively high optical absorption performance, which is beneficial to improving the conversion efficiency of the solar cell. In addition, the surface reflectivity of the edge region located at the edge in the front surface of the semiconductor substrate is relatively high, and the specific surface area of the edge region is relatively small, i.e., the surface of the edge region is relatively flat, which is beneficial to reducing the physical defects of the edge region of the semiconductor substrate, reducing the carrier recombination rate and the fragment rate of the edge region of the semiconductor substrate.

[0201] It should be noted that the widths of different parts of the edge region can be the same or different along the length extension direction of the edge of the front surface of the semiconductor substrate.

[0202] As described above, the surface reflectivity of the edge region is greater than that of the middle region can be that the edge region and the middle region have different morphologies of the texture structure. The surface of the edge region has a texture structure with a morphology different from that of the surface of the middle region can mean that the texture structure located in the edge region is different from the texture structure located in the middle region in type, or that the texture structure located in the edge region is the same as the texture structure located in the middle region in type but different in size. The specific type and size of the texture structure located in the edge region and the texture structure located in the middle region can be determined according to the requirements of the surface reflectivity of the edge region and the middle region in the actual application scenario.

[0203] For example, as shown in FIG. 6, the surface of the middle region 14 has a pyramid-shaped structure 104, and the surface of the edge region 13 has a polished structure 105. In this case, the surface of the middle region 14 provided with the pyramid-shaped texture structure has a relatively high light trapping effect, which is beneficial to making more light refract into the semiconductor substrate 1 through the middle region 14 of the front surface and be utilized by the semiconductor substrate 1, thereby improving the light utilization rate of the solar cell. In addition, compared with the part of the middle region 14 corresponding to the semiconductor substrate 1, the part of the edge region 13 located at the edge corresponding to the semiconductor substrate 1 has more defects. Moreover, compared with the pyramid-shaped structure 104, the polished structure 105 does not have a relatively sharp top, and thus the surface of the edge region 13 provided with the polished structure 105 is relatively flat, which is beneficial to improving the formation quality of the first semiconductor layer 19 deposited around the edge region 13, and / or the film layer such as the surface passivation layer provided on the edge region 13, improving the passivation effect of the first semiconductor layer 19 and / or the surface passivation layer on the edge region 13, and reducing the carrier recombination rate of the edge region 13 of the edge of the semiconductor substrate 1, thereby improving the conversion efficiency of the solar cell.

[0204] The pyramid structure can be a regular pyramid structure, or can be an irregular pyramid structure with a pentagonal, hexagonal or other non-quadrilateral bottom surface.

[0205] The polishing structure is a surface formed after the semiconductor substrate is etched by an etching solution, and the pyramid structure is removed, and the semiconductor substrate is slightly concave. The polishing structure can be surrounded by a side surface and a polygonal bottom surface, which can be a regular or irregular polygonal bottom surface (such as a quadrilateral bottom surface, a pentagonal bottom surface, a hexagonal bottom surface, or an octagonal bottom surface; the polygon can be a regular polygon with equal side lengths, or a polygon with different side lengths), and the corners of the polygonal bottom surface can be sharp corners or chamfered corners with smooth transitions.

[0206] For example, the surface of the edge region and the surface of the middle region can each include pyramid structures. In this case, the distribution density of the pyramid structures on the surface of the edge region can be less than the distribution density of the pyramid structures on the surface of the middle region; and / or, the degree of smoothness of the pyramid structures on the surface of the edge region can be greater than the degree of smoothness of the pyramid structures on the surface of the middle region; and / or, the bottom of the pyramid structures on the surface of the edge region can be circular (for example, a regular or irregular circle, a regular or irregular ellipse, etc.), and the bottom of the pyramid structures on the surface of the middle region can be rectangular (for example, a regular or irregular rectangle, a regular or irregular square, etc.). In this application, the distribution density on the surface of the edge region refers to the number of pyramid structures or polishing structures in a square region, and the length of the side of the square region is the width of the edge region.

[0207] It is worth noting that in the case where the surfaces of the edge region and the middle region each include pyramid structures, the distribution density of the pyramid structures on the surface of the edge region is less than the distribution density of the pyramid structures on the surface of the middle region. At this time, the surface of the middle region, which is provided with a larger number of pyramid structures, has a greater roughness and a larger specific surface area, which is beneficial to increasing the light absorption area of the surface of the middle region and enhancing the light trapping effect of the surface of the middle region. The surface of the edge region, which is provided with a smaller number of pyramid structures, is relatively flat, which is beneficial to improving the formation quality of the film layer, such as the surface passivation layer, provided on the edge region, improving the passivation effect of the surface passivation layer on the edge region, and reducing the carrier recombination rate of the edge region of the semiconductor substrate, thereby improving the conversion efficiency of the solar cell. In this case, the difference in the distribution density of the pyramid structures on the surface of the edge region and the surface of the middle region can be determined according to the reflectivity of the two region surfaces, which is not specifically limited here.

[0208] As to the smoothness of the pyramid structures on the surface of the edge region, the smoothness of the pyramid structures on the surface of the edge region is greater than the smoothness of the pyramid structures on the surface of the middle region; and / or, the base of the pyramid structures on the surface of the edge region is circular, and the base of the pyramid structures on the surface of the middle region is rectangular; and / or, the distribution area of the pyramid structures on the surface of the edge region is less than the distribution area of the pyramid structures on the surface of the middle region. The application principle of the beneficial effect of the above can refer to the application principle of the beneficial effect of the distribution density of the pyramid structures on the surface of the edge region being less than the distribution density of the pyramid structures on the surface of the middle region, which will not be repeated here.

[0209] In some cases, when the textured structure on the surface of the edge region includes pyramid structures, the textured structure on the surface of the edge region can also include polishing structures. In this case, compared with the pyramid structures, the polishing structures do not have relatively sharp tower tops, so when the surface of the edge region also has a tower base-like textured structure, the surface of the edge region is relatively flat.

[0210] As to the distribution of the polishing structures and the pyramid structures on the surface of the edge region, it can be determined according to the reflectivity requirements of the surface of the edge region in the actual application scenario, which is not specifically limited here.

[0211] For example, as shown in FIG. 22, in the edge region, the distribution density of the polishing structures can be greater than the distribution density of the pyramid structures; or, in the edge region, the distribution area of the polishing structures is greater than the distribution area of the pyramid structures. In this way, the polishing structures have a greater setting proportion in the edge region, so that most of the surface of the edge region is relatively flat, which is beneficial to improve the passivation effect of the surface passivation layer and other film layers on the edge region, and is beneficial to reduce the carrier recombination rate of the edge region of the semiconductor substrate edge. In addition, part of the surface of the edge region also has pyramid structures, which is beneficial to reduce the reflectivity of the edge region, improve the light absorption rate of the front surface of the solar cell, and balance the passivation effect and light absorption rate of the surface of the edge region, and improve the working performance of the solar cell.

[0212] For example, as shown in FIG. 22, the surface of the edge region has a texture structure further comprising a polishing structure; in the edge region, the distribution density of the polishing structure gradually decreases from the edge of the semiconductor substrate to the middle region, or, in the edge region, the distribution density of the pyramid structure gradually increases from the edge of the semiconductor substrate to the middle region. In this way, after the edge of the semiconductor substrate is subjected to stress, the edge stress impact gradually spreads to the internal region of the semiconductor substrate, having a certain impact buffering effect. In addition, the gradual decrease in the distribution density of the polishing structure from the edge of the semiconductor substrate to the middle region of the semiconductor interior can cause the reflectivity to decrease linearly, avoiding a large span in reflectivity between the edge region and the middle region, which affects the power generation efficiency of the battery. The distribution density in the edge region in the embodiments of the present application refers to the number of pyramid structures or polishing structures in a square region, and the length of the side of the square region is the width value of the edge region.

[0213] In actual application, as shown in FIGS. 19 and 23, the surfaces of the edge region can be flush. Alternatively, for example, as shown in FIGS. 22 and 24, the edge region can include a recessed area and a non-recessed area. In the thickness direction of the semiconductor substrate, the surface of the recessed area is recessed into the semiconductor substrate relative to the surface of the non-recessed area. In this way, the presence of the recessed area allows the edge surface of the edge region to reflect incident light at different angles, reducing the reflectivity of the edge surface of the edge region provided with the polishing structure, which is beneficial to improving the light utilization rate of the semiconductor substrate. At the same time, it can also make the reflection spectrum wavelength of the edge surface of the edge region different, which can reduce the color reflection effect of the edge surface of the edge region caused by the excessive concentration of a single wavelength color spectrum, improve the consistency of the front color of the solar cell, and improve the aesthetics.

[0214] The surface of the recessed area can be provided with a texture structure, such as a pyramid structure or a polishing structure. The distribution of the recessed area in the edge region can be set according to the distribution of the texture structure on the surface of the edge region and actual needs. For example, when the edge region surface is also provided with a pyramid structure, the pyramid structure can be located in the recessed area of the edge region.

[0215] It should be noted that the division of the recessed area and the non-recessed area of the edge region is based on the height of the surface of different regions in the edge region. The height of different regions in the surface of the edge region is based on the height of the bottom surface of the texture structure provided on the surface of the edge region (for example, the height of the bottom surface of the recessed area and the bottom surface of the non-recessed area relative to the semiconductor substrate, respectively).

[0216] In addition, as shown in FIG. 6 and FIG. 23, the surface of the edge region 13 and the surface of the middle region 14 can be staggered along the direction from the back surface to the front surface of the semiconductor substrate 1. In this case, which of the surface of the edge region 13 and the surface of the middle region 14 is farther away from the semiconductor substrate 1 can be determined according to the type of the solar cell and the manufacturing process, and is not specifically limited herein.

[0217] For example, as shown in FIG. 6, the surface of the edge region 13 is farther away from the semiconductor substrate 1 than the surface of the middle region 14 along the direction from the back surface to the front surface of the semiconductor substrate 1. In this embodiment, the height of the surface of the edge region 13 is greater than the height of the surface of the middle region 14, where the height refers to the height between the bottom of the pyramid structure on the back surface of the semiconductor substrate 1 and the bottom of the pyramid on the front surface of the semiconductor substrate 1, or the height between the top of the pyramid structure on the back surface of the semiconductor substrate 1 and the top of the pyramid structure on the front surface of the semiconductor substrate 1. In this case, the surface of the edge region 13 and the surface of the middle region 14 can be staggered along the thickness direction of the semiconductor substrate 1, and a side surface for connection is arranged between the edge region 13 and the middle region 14. The light reflected by the surface of the middle region 14 can be refracted into the semiconductor substrate 1 through the side surface, so that the transmission path of the light is changed under the joint action of the surface of the middle region 14 and the side surface, the antireflection effect of the front surface of the semiconductor substrate 1 is improved, the light utilization rate is improved, and the conversion efficiency of the solar cell is improved. At the same time, the presence of the side surface can increase the contact area between the surface passivation layer and the semiconductor substrate 1, and improve the passivation effect of the surface passivation layer.

[0218] Alternatively, as shown in FIG. 23, the surface of the middle region 14 can be farther away from the semiconductor substrate 1 than the surface of the edge region 13 along the direction from the back surface to the front surface of the semiconductor substrate 1. In this case, the surface passivation layer is completely removed from the portions of the first semiconductor layer 19 located on the side surface and the back surface of the semiconductor substrate 1 in the process of removing the passivation layer, thereby reducing the risk of electric leakage.

[0219] Specifically, in the front surface of the semiconductor substrate, the intermediate region is defined to include the inner region and a transition region located outside the inner region and adjacent to the inner region. The transition region is used to connect the edge region and the intermediate region. Based on this, the surface of the transition region can be arranged perpendicularly relative to the surfaces of the edge region and the inner region. Alternatively, as shown in FIG. 6, FIG. 20 and FIG. 21, the surface of the transition region 29 can also be arranged obliquely relative to the surfaces of the edge region 13 and the inner region 30, respectively, to form a bevel, which includes a flat surface or a concave-convex surface, to improve the internal reflectivity of the incident light and thus improve the photoelectric conversion efficiency of the solar cell. The bevel is also conducive to improving the deposition of the passivation layer, so that the passivation layer deposited on the first surface is denser, thereby forming a good passivation effect on the semiconductor substrate 1. In this case, the height variation trend at the boundary between the edge region 13 and the inner region 30 can be made more gentle, which is conducive to improving the formation quality and passivation effect of the surface passivation layer at the boundary between the edge region 13 and the inner region 30, and reducing the carrier recombination rate.

[0220] The surface height difference between the edge region and the intermediate region can be set according to actual needs.

[0221] For example, the surface height difference between the edge region and the intermediate region can be 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm or 10 μm, etc. In this case, the surface height difference between the edge region and the intermediate region is within the above range, which is conducive to preventing the poor antireflection effect caused by the side surface arranged between the edge region and the intermediate region due to the too small surface height difference between the edge region and the intermediate region, and improving the light utilization rate of the semiconductor substrate. It can also prevent the thickness of the part of the semiconductor substrate corresponding to the intermediate region from being too small due to the too large surface height difference between the edge region and the intermediate region, so that the part of the semiconductor substrate corresponding to the intermediate region also has a large light absorption depth, thereby improving the light utilization rate of the semiconductor substrate; and improving the mechanical load resistance of the part of the semiconductor substrate corresponding to the intermediate region.

[0222] As for the surface of the intermediate region, the topography and one-dimensional size of the texture structure of different parts of the surface of the intermediate region can be substantially the same, so as to improve the uniformity of the distribution of the texture structure on different parts of the intermediate region and improve the formation quality and passivation effect of the surface passivation layer.

[0223] Alternatively, in the case where the intermediate region includes the inner region and the transition region, the size of the texture structure in the transition region can be different from the size of the texture structure in the inner region.

[0224] For example, as shown in FIGS. 20 and 21, in the case where the texture structure on the surface of the middle region 14 comprises pyramid structures 104, the height of the pyramid structures 104 located in the transition region 29 can gradually decrease in the direction from the edge region 13 to the middle region 14. In this way, the degree of fluctuation of the pyramid structures 104 in the direction from the edge region 13 to the middle region 14 also gradually decreases, i.e. the closer to the edge region 13, the smoother the surface of the transition region 29, which is conducive to improving the formation quality and passivation effect of the surface passivation layer at the boundary between the edge region 13 and the inner region 30, and reducing the carrier recombination rate.

[0225] For example, as shown in FIGS. 20 and 21, the average length of the side edges of the pyramid structures 104 located in the transition region 29 can be greater than the average length of the side edges of the pyramid structures 104 located in the inner region 30. In this way, it can be understood that the side edges of the pyramid structures 104 are relatively flat compared with the sharp apex of the pyramid structures 104, and therefore when the average length of the side edges of the pyramid structures 104 located in the transition region 29 is greater than the average length of the side edges of the pyramid structures 104 located in the inner region 30, it is conducive to improving the smoothness of the surface of the transition region 29, and also conducive to improving the formation quality and passivation effect of the surface passivation layer at the boundary between the edge region 13 and the inner region 30.

[0226] The difference in the size of the texture structure between the transition region and the inner region can be set according to actual requirements, and is not specifically limited here.

[0227] In addition, the one-dimensional size of the texture structure of different parts of the inner region can be the same or different.

[0228] As shown in FIG. 7 and FIG. 8, the intermediate region 14 includes first sub-regions 106 and second sub-regions 107 which can be alternately arranged, and third sub-regions 108 between the first sub-regions 106 and the second sub-regions 107. In the direction from the back surface to the front surface of the semiconductor substrate 1, the surface of the second sub-region 107 can have a greater surface height than the surface of the first sub-region 106. The surface of the third sub-region 108 has a one-dimensional size of the texture structure which is greater than the one-dimensional size of the texture structure of the surfaces of the first sub-region 106 and the second sub-region 107. In this case, compared with the case where the first sub-regions 106 and the second sub-regions 107 are arranged in the same level in the intermediate region 14, when the first sub-regions 106 and the second sub-regions 107 are arranged in the thickness direction of the semiconductor substrate 1, the surface of the intermediate region 14 can additionally have the third sub-regions 108 which are connected between the first sub-regions 106 and the second sub-regions 107, thereby increasing the passivation contact area of the surface passivation layer and the intermediate region 14. Secondly, the surface of the third sub-region 108 has a greater one-dimensional size of the texture structure, so that the specific surface area of the third sub-region 108 is greater, which is conducive to improving the light trapping effect of the surface of the intermediate region 14. While the first sub-region 106 and the second sub-region 107 have a smaller one-dimensional size of the texture structure, which is conducive to improving the formation quality and passivation effect of the surface passivation layer on the first sub-region 106 and the second sub-region 107, so that the light trapping effect and the passivation effect of the intermediate region 14 can be considered, and the working performance of the solar cell can be improved. Furthermore, the one-dimensional size of the texture structure itself and the matching with the corresponding light trapping wavelength have certain matching, and when the third sub-region 108 of the intermediate region 14 has a greater one-dimensional size of the texture structure than the first sub-region 106 and the second sub-region 107, the surface of the intermediate region 14 has a higher light trapping effect on light of different wavelengths, thereby improving the light absorption rate of the semiconductor substrate 1.

[0229] The first sub-region, the second sub-region and the third sub-region are located in the inner region included in the intermediate region. The surface of the third sub-region can be arranged perpendicularly relative to the surfaces of the first sub-region and the second sub-region. Alternatively, as shown in FIG. 7 and FIG. 8, the surface of the third sub-region 108 can be arranged obliquely relative to the surfaces of the first sub-region 106 and the second sub-region 107. In this way, the degree of height change between the first sub-region 106 and the second sub-region 107 is relatively gentle, which is conducive to improving the formation quality and passivation effect of the surface passivation layer at the junction of the first sub-region 106 and the second sub-region 107.

[0230] The angle between the surface of the third sub-region and the surface of the first sub-region can be arranged according to actual needs.

[0231] For example, the included angle between the surface of the third sub-region and the surface of the first sub-region can be greater than or equal to 120° and less than or equal to 170°. For example, the included angle can be 120°, 125°, 130°, 135°, 140°, 145°, 150°, 155°, 160° or 170°, etc. In this case, the included angle between the surface of the third sub-region and the surface of the first sub-region is within the above range, which is beneficial to prevent the height variation of the first sub-region and the second sub-region from being too large due to the too small included angle, that is, the inclination of the surface of the third sub-region is too large, which is beneficial to improve the coating of the surface passivation layer on the third sub-region and improve the passivation effect of the surface passivation layer on the third sub-region. In addition, it can also prevent the surface of the third sub-region from being too flat due to the too large included angle, so that the one-dimensional size of the pyramid structure arranged on the third sub-region is too small compared with the one-dimensional size of the pyramid structure on the first sub-region and the second sub-region, which is beneficial to make the surface of the third sub-region have a higher light trapping effect.

[0232] As for the width of the third sub-region, for example, along the arrangement direction of the first sub-region and the second sub-region, the width of the third sub-region can be greater than or equal to 1 μm and less than or equal to 50 μm. For example, the width of the third sub-region can be 1 μm, 5 μm, 10 μm, 15 μm, 20 μm, 30 μm, 40 μm or 50 μm, etc. In this case, the width of the third sub-region is within the above range, which is beneficial to prevent the light absorption area of the intermediate region from being too small due to the too small width of the third sub-region, and the number of pyramid structures with large one-dimensional size arranged is too small, which is beneficial to improve the light trapping effect of the intermediate region. It can also prevent the surface roughness of the intermediate region from being too large due to the too large width of the third sub-region, which increases the number of pyramid structures with large one-dimensional size in the intermediate region, and improves the passivation effect of the surface passivation layer on the intermediate region.

[0233] Of course, according to the size of the semiconductor substrate and / or actual needs, the width of the third sub-region can also be set to other appropriate values.

[0234] As for the one-dimensional size of the texture structure arranged on the first sub-region, the second sub-region and the third sub-region respectively, it can be determined according to the type of the texture structure and the reflectivity requirement of the surface of the intermediate region in the actual application scenario, which is not limited here.

[0235] For example, the ratio of the one-dimensional size of the texture structure on the surface of the third sub-region to the one-dimensional size of the texture structure on the surface of the first sub-region and / or the second sub-region can be greater than or equal to 1.5 times and less than or equal to 3 times. For example, the ratio can be 1.5 times, 1.8 times, 2 times, 2.2 times, 2.5 times, 2.8 times or 3 times, etc. In this case, it can be prevented that the one-dimensional size of the texture structure on the surface of the third sub-region is too small compared with the one-dimensional size of the texture structure on the surface of the first sub-region and / or the second sub-region, so that the surface roughness of the third sub-region is too small and / or the surface roughness of the first sub-region and / or the second sub-region is too large, which is beneficial to make the third sub-region have a higher light trapping effect and the surface passivation layer have a higher passivation effect on the first sub-region and the second sub-region. In addition, it can also be prevented that the ratio is too large (i.e., the one-dimensional size of the texture structure on the surface of the third sub-region is too large and / or the one-dimensional size of the texture structure on the surface of the first sub-region and / or the second sub-region is too small), so that the forming quality of the surface passivation layer on the third sub-region is too poor and the surface roughness of the first sub-region and / or the second sub-region is too small, which improves the passivation effect of the surface passivation layer on the third sub-region and makes the first sub-region and the second sub-region have a good light trapping capability.

[0236] For example, the difference between the one-dimensional sizes of the texture structures of the first sub-region and the second sub-region can be greater than or equal to 0.9 and less than or equal to 1.1. At this time, the sizes of the texture structures of the first sub-region and the second sub-region are basically the same, so that the distribution of the texture structures on the first sub-region and the second sub-region is more uniform, which is beneficial to improve the forming quality and passivation effect of the surface passivation layer on the first sub-region and the second sub-region.

[0237] The one-dimensional size of the texture structure of the first sub-region, the second sub-region and the third sub-region can be determined according to the type of the texture structure. For example, in the case where the texture structure includes a pyramid-like structure, the one-dimensional size of the texture structure of the first sub-region, the second sub-region and the third sub-region can be the height, the side edge length, the bottom surface edge length, the bottom surface diagonal length or the bottom surface perimeter length of the pyramid-like structure.

[0238] The surface height difference between the first sub-region and the second sub-region can be determined according to the requirements for the width of the third sub-region and the one-dimensional size of the texture structure arranged on the third sub-region in the actual application scenario, which is not specifically limited.

[0239] Exemplarily, the surface height difference between the first sub-region and the second sub-region can be greater than or equal to 1 μm and less than or equal to 7 μm. For example, the surface height difference between the first sub-region and the second sub-region can be 1 μm, 1.5 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm or 7 μm, etc. In this case, the surface height difference between the first sub-region and the second sub-region is within the above range, which can prevent the area of the third sub-region from being too small due to the too small height difference between the first sub-region and the second sub-region, so that the middle region has a larger passivation contact area and light absorption area due to the additional third sub-region, and the number of pyramid structures with a larger one-dimensional size arranged on the third sub-region is larger, thereby further improving the light trapping effect. In addition, it can also prevent the thinning amount of the portion of the semiconductor substrate corresponding to the first sub-region from being too large due to the too large surface height difference between the first sub-region and the second sub-region, so that the portion of the semiconductor substrate corresponding to the first sub-region also has a larger light absorption depth, thereby improving the light utilization rate of the semiconductor substrate, and improving the mechanical load resistance of the portion of the semiconductor substrate corresponding to the first sub-region.

[0240] For the side surface of the semiconductor substrate, the side surface of the semiconductor substrate can also have a texture structure, and the topography of the texture structure can be set according to actual needs.

[0241] Exemplarily, the texture structure on the surface of the edge region can be integrally continuous with the texture structure on the side surface of the semiconductor substrate. In this case, integrally continuous means that the texture structure on the surface of the edge region and the texture structure on the side surface of the semiconductor substrate are formed at the same time by using the same process in the same operation step, so as to simplify the manufacturing process of the solar cell, make the side surface of the semiconductor substrate more flat, improve the coating and forming quality of the first semiconductor layer on the side surface, and facilitate the structure of the solar cell to be more complete, thereby improving the toughness of the cell and reducing the fragment rate.

[0242] For example, the texture structures on the surface of the edge region and the side surface of the semiconductor substrate both include polishing structures, and the topography of the polishing structures on the surface of the edge region and the side surface of the semiconductor substrate is the same.

[0243] For another example, the side surface of the semiconductor substrate includes a polishing structure, and the back surface of the semiconductor substrate includes a polishing structure, and the polishing structures on the edge region, the side surface of the semiconductor substrate and the back surface of the semiconductor substrate are the same.

[0244] In a fourth aspect, an embodiment of the present application provides a photovoltaic module, which comprises: a cell string and an encapsulation layer. The cell string is formed by electrically connecting a plurality of solar cells as provided in the third aspect and various implementation manners thereof; and the encapsulation layer covers the surface of the cell string.

[0245] The beneficial effects of the fourth aspect and various implementation manners thereof in the embodiments of the present application can be referred to the beneficial effect analysis of the third aspect and various implementation manners thereof, which will not be repeated here.

[0246] The solar cell is described below by way of example in several possible cases, and it should be understood that the following description is only for understanding and does not serve to specifically limit.

[0247] The present application provides a solar cell, as shown in FIG. 1, comprising a semiconductor substrate 1, the semiconductor substrate 1 comprising opposite first and second faces 10 and 11, and a side face 12 connecting the first and second faces 10 and 11. The first face 10 has an edge region 13 and a middle region 14, the edge region 13 having a first texture structure, and the middle region 14 having a second texture structure.

[0248] As a possible implementation manner, the size of the first texture structure is greater than the size of the second texture structure.

[0249] As a possible implementation manner, the first texture structures on the edge region are connected to each other to form a first texture structure group, and the edge region further comprises a fifth texture structure, the size of the fifth texture structure being smaller than the size of the first texture structure. As shown in FIG. 22, the first texture structure is a pyramid structure 104, and the fifth texture structure is a polishing structure 105, which provides a more gentle surface compared to the first texture structure on the edge region, reduces the lattice defects of the surface, and is beneficial to the passivation quality of the edge region, improves the conversion efficiency of the solar cell, and the size of the fifth texture structure is smaller than the size of the first texture structure, where the size includes the height of the texture structure (the distance from the bottom of the pyramid to the top of the pyramid, and the distance between the lowest point of the polishing structure and the highest point of the polishing structure).

[0250] As a possible implementation manner, the fifth texture structure is located between the first texture structure groups and between the edge of the semiconductor substrate and the first texture structure groups. As shown in FIG. 22, the smaller fifth texture structure provides a more gentle surface compared to the first texture structure on the edge region, reduces the lattice defects of the surface, and is beneficial to the passivation quality of the edge region; at the same time, the smaller fifth texture structure on the edge region is close to the edge of the cell, so that the edge structure is neat and flat, and the chip rate can also be reduced, so that the optical absorption performance of the cell itself is higher, and the high conversion efficiency and production yield of the solar cell are ensured.

[0251] As a possible implementation, the surface of the first texture structure is recessed into the semiconductor substrate relative to the surface of the fifth texture structure. The recess of the surface of the first texture structure into the semiconductor substrate allows the surface in the edge region to reflect incident light rays at different angles, reduces the reflectivity of the surface in the edge region, and facilitates the improvement of the light utilization of the semiconductor substrate. Meanwhile, the reflection spectrum wavelength of the surface in the edge region can be different, which can reduce the color reflection effect caused by the excessive concentration of the spectrum of a single wavelength color on the surface in the edge region, improve the consistency of the front color of the solar cell, and improve the appearance.

[0252] As a possible implementation, the first texture structure and the fifth texture structure are both polishing structures, as shown in FIG. 24, or the first texture structure is a pyramid structure and the fifth texture structure is a polishing structure, as shown in FIG. 22, wherein the polishing structure is the polishing structure in the priority application. The polishing surface of the first texture structure and the surface of the fifth texture structure are distributed in the edge region, and when the polishing surface of the first texture structure is recessed into the semiconductor substrate, the surface in the edge region can reflect incident light rays at different angles, reducing the reflectivity of the surface in the edge region, and facilitating the improvement of the light utilization of the semiconductor substrate. Meanwhile, the reflection spectrum wavelength of the surface in the edge region can be different, which can reduce the color reflection effect caused by the excessive concentration of the spectrum of a single wavelength color on the surface in the edge region, improve the consistency of the front color of the solar cell, and improve the appearance.

[0253] As a possible implementation, as shown in FIG. 2, when the first texture structure is a pyramid structure, the size of the pyramid of the first texture structure gradually decreases from the edge of the semiconductor substrate to the center. By gradually reducing the size of the pyramid from the edge to the center, the difference in size of the larger pyramid can be avoided, the reflection angle of light in the edge region can be reduced, the obvious glare effect of the battery can be avoided, and the appearance consistency of the surface of the battery can be improved.

[0254] As a possible implementation, when the first texture structure and the fifth texture structure are both polishing structures, the distribution area of the first texture structure gradually increases from the edge of the semiconductor substrate to the middle region, as shown in FIG. 24.

[0255] As a possible implementation, as shown in FIG. 22, the first texture structure is a pyramid structure, and the fifth texture structure is a polishing structure; wherein: in the edge region, the distribution density of the polishing structure is greater than the distribution density of the pyramid structure; or, in the edge region, the distribution area of the polishing structure is greater than the distribution area of the pyramid structure. In this way, the polishing structure has a greater setting proportion in the edge region, so that most of the surface of the edge region is relatively flat, which helps to improve the passivation effect of the surface passivation layer and other film layers on the edge region, and helps to reduce the carrier recombination rate of the edge region of the semiconductor substrate edge. In addition, part of the surface of the edge region also has a pyramid structure, which helps to reduce the reflectivity of the edge region, improve the light absorption rate of the front surface of the solar cell, and help to balance the passivation effect and light absorption rate of the surface of the edge region, and improve the working performance of the solar cell.

[0256] As a possible implementation, as shown in FIG. 22, the first texture structure is a pyramid structure, and the fifth texture structure is a polishing structure; wherein: in the edge region, the distribution area of the polishing structure gradually decreases from the edge of the semiconductor substrate to the middle region; or, in the edge region, the distribution density of the polishing structure gradually decreases from the edge of the semiconductor substrate to the middle region; or, in the edge region, the distribution density of the pyramid structure gradually increases from the edge of the semiconductor substrate to the middle region. In the case of the above technical solution, after the edge of the semiconductor substrate is subjected to stress, the edge stress impact gradually transmits to the internal region of the semiconductor substrate, having a certain impact buffering effect. In addition, the distribution density of the polishing structure gradually decreases from the edge of the semiconductor substrate to the middle region of the semiconductor, which can make the flatness of the surface of the edge region gradually increase from the middle region to the edge of the semiconductor substrate, which helps to linearly reduce the reflectivity, and avoid a large span of reflectivity between the edge region and the middle region, which affects the power generation efficiency of the cell. The distribution area of the polishing structure gradually decreases from the edge of the semiconductor substrate to the middle region; or, in the edge region, the distribution density of the pyramid structure gradually increases from the edge of the semiconductor substrate to the middle region, which has the same technical effect as the above gradually decreasing distribution density of the polishing structure from the edge of the semiconductor substrate to the middle region of the semiconductor, and will not be repeated here.

[0257] As a possible implementation manner, the second texture structure of the middle region and the first texture structure of the edge region comprise pyramid structures; the distribution density of the pyramid structures on the surface of the edge region is less than the distribution density of the pyramid structures on the surface of the middle region. At this time, more pyramid structures are arranged on the surface of the middle region, so that the surface roughness of the middle region is greater, the specific surface is greater, the light absorption area of the surface of the middle region is increased, and the light trapping effect of the surface of the middle region is enhanced. The surface roughness of the edge region with fewer pyramid structures is smaller, the surface is relatively flat, the forming quality of the film layer such as the surface passivation layer arranged on the edge region is improved, the passivation effect of the film layer such as the surface passivation layer on the edge region is improved, the carrier recombination rate of the edge region of the edge of the semiconductor substrate is reduced, and the conversion efficiency of the solar cell is improved.

[0258] As a possible implementation manner, there is a transition region between the first texture structure and the second texture structure, and the surface of the transition region comprises a flat surface or a concave-convex surface. In this way, the process difficulty of forming the transition region is reduced, and the yield of the solar cell is improved.

[0259] As a possible implementation manner, the reflectivity of the middle region is less than the reflectivity of the edge region, and the width of the edge region is less than or equal to 200 μm in the direction from the center to the edge of the front surface of the semiconductor substrate. In this case, the surface of the middle region with a large area ratio in the front surface of the semiconductor substrate has a smaller reflectivity, and the light utilization rate of the semiconductor substrate is improved.

[0260] As a possible implementation manner, the height of the first texture structure is greater than the height of the second texture structure; and / or, the base width of the first texture structure is greater than the base width of the second texture structure; and / or, the edge length of the first texture structure is greater than the edge length of the second texture structure.

[0261] As a possible implementation manner, when the first texture structure is a pyramid structure, the height of the first texture structure is greater than or equal to 4 μm and less than or equal to 8 μm; and / or, the base width of the first texture structure is greater than or equal to 5 μm and less than or equal to 9 μm; and / or, the edge length of the first texture structure is less than 10 μm.

[0262] As a possible implementation manner, when the second texture structure is a pyramid structure, the height of the second texture structure is greater than or equal to 1 μm and less than 4 μm; and / or, the base width of the second texture structure is greater than or equal to 2 μm and less than 5 μm; and / or, the edge length of the second texture structure is less than 6 μm.

[0263] As a possible implementation manner, the vertex of the first texture structure is farther away from the back surface side of the solar cell than the vertex of the second texture structure.

[0264] As a possible implementation manner, the surface height difference between the edge region and the middle region is greater than or equal to 1 μm and less than or equal to 10 μm.

[0265] As a possible implementation manner, in the front surface of the semiconductor substrate, the surface of the region for connecting the edge region and the middle region is respectively arranged to be inclined with respect to the surfaces of the edge region and the middle region.

[0266] As a possible implementation manner, the width of the edge region is greater than 0 μm and less than or equal to 50 μm; the width direction of the edge region is consistent with the vertical direction of the vertical line between the first surface and the second surface.

[0267] As a possible implementation manner, the size uniformity of the first texture structure located in the edge region is lower than the size uniformity of the second texture structure located in the middle region.

[0268] As a possible implementation manner, the side surface comprises a third texture structure region, and the third texture structure region is close to the first surface.

[0269] As a possible implementation manner, the ratio of the width of the third texture structure region to the width of the side surface is less than 80%, and the width direction of the third texture structure region and the width direction of the side surface are both the vertical direction from the first surface to the second surface.

[0270] As a possible implementation manner, the side surface comprises a fourth texture structure region, and the fourth texture structure region comprises a tower base structure; a plurality of tower base structures are arranged along a first straight line, and the first straight line is inclined with respect to the side edge of the side surface.

[0271] As a possible implementation manner, the plurality of first straight lines are parallel to each other; and / or, the included angle between the first straight line and the side edge of the side surface is greater than or equal to 15° and less than or equal to 75°; and / or, the length of the first straight line is greater than the thickness of the semiconductor substrate, and the thickness direction of the semiconductor substrate is consistent with the vertical direction from the first surface to the second surface.

[0272] As a possible implementation manner, an amorphous silicon layer is formed on the third texture structure region.

[0273] As a possible implementation manner, a tunneling silicon oxide layer, a doped polysilicon layer and a silicon nitride layer are sequentially stacked on the fourth texture structure region.

[0274] As a possible implementation manner, an amorphous silicon layer is coated on the third texture structure region and the fourth texture structure region.

[0275] As a possible implementation manner, the boundary line between the edge region and the middle region is a curve.

[0276] As a possible implementation, the solar cell further comprises a first type electrode and a second type electrode; the first type electrode is arranged on the first side of the semiconductor substrate, and the second type electrode is arranged on the second side of the semiconductor substrate; the first type electrode and the second type electrode are opposite in polarity.

[0277] As a possible implementation, the solar cell further comprises a first type electrode and a second type electrode; the first type electrode and the second type electrode are alternately and spacedly arranged on the second side of the semiconductor substrate; the first type electrode and the second type electrode are opposite in polarity.

[0278] As a possible implementation, the second side has a first region and a second region alternately arranged along the first direction; the solar cell further comprises: a first doped semiconductor layer arranged on the first region; a second doped semiconductor layer arranged on the second region and extending to cover part of the first doped semiconductor layer; the second doped semiconductor layer and the first doped semiconductor layer are opposite in conductive type.

[0279] In the description of the above embodiments, specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0280] The above describes only specific embodiments of the present application, but the protection scope of the present application is not limited thereto, any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A solar cell, characterized by, Comprise: a semiconductor substrate comprising a first face and a second face opposite to each other, and a side face connecting the first face and the second face; the first face has an edge region and a middle region, the edge region has a first texture structure, and the middle region has a second texture structure.

2. The solar cell according to claim 1, characterized in that, The size of the first texture structure is greater than the size of the second texture structure.

3. The solar cell according to claim 2, characterized in that, The first texture structures on the edge region are connected to each other to form a first texture structure group, and the edge region further comprises a fifth texture structure, and the size of the fifth texture structure is smaller than the size of the first texture structure.

4. The solar cell according to claim 3, characterized in that, The fifth texture structure is located between a plurality of the first texture structure groups and between the edge of the semiconductor substrate and the first texture structure group.

5. The solar cell according to claim 3, wherein The surface of the first texture structure is recessed into the semiconductor substrate relative to the surface of the fifth texture structure.

6. The solar cell of claim 1, wherein The edge region further comprises a fifth texture structure; wherein the first texture structure and the fifth texture structure are both polishing structures, Or, the first texture structure is a pyramid structure, and the fifth texture structure is a polishing structure.

7. The solar cell according to claim 6, characterized in that, When the first texture structure is a pyramid structure, the size of the pyramid of the first texture structure gradually decreases from the edge of the semiconductor substrate to the center.

8. The solar cell of claim 6, wherein, When the first texture structure and the fifth texture structure are both polishing structures, the distribution area of the first texture structure gradually increases from the edge of the semiconductor substrate to the middle region.

9. The solar cell of claim 6, wherein, The first texture structure is a pyramid structure, and the fifth texture structure is a polishing structure; Wherein, in the edge region, the distribution density of the polishing structure is greater than the distribution density of the pyramid structure; Or, in the edge region, the distribution area of the polishing structure is greater than the distribution area of the pyramid structure; Or, in the edge region, the distribution area of the polishing structure gradually decreases from the edge of the semiconductor substrate to the middle region; Or, in the edge region, the distribution density of the polishing structure gradually decreases from the edge of the semiconductor substrate to the middle region; Or, in the edge region, the distribution density of the pyramid structure gradually increases from the edge of the semiconductor substrate to the middle region.

10. The solar cell of claim 1, wherein, The second texture structure of the middle region and the first texture structure of the edge region comprise pyramid structures; The distribution density of the pyramid structure on the surface of the edge region is less than the distribution density of the pyramid structure on the surface of the middle region.

11. The solar cell of claim 1, wherein, There is a transition zone between the first texture structure and the second texture structure, and the surface of the transition zone comprises a flat surface or a concave-convex surface.

12. The solar cell of claim 1, wherein, The reflectivity of the middle region is less than the reflectivity of the edge region, and the width of the edge region is less than or equal to 200μm along the direction from the center to the edge of the front face of the semiconductor substrate.

13. The solar cell of claim 2, wherein, The height of the first texture structure is greater than the height of the second texture structure; and / or, the base width of the first texture structure is greater than the base width of the second texture structure; and / or, the edge length of the first texture structure is greater than the edge length of the second texture structure.

14. The solar cell of claim 2, wherein, When the first texture structure is a pyramid structure, a height of the pyramid structure is greater than or equal to 4 μm and less than or equal to 8 μm; and / or, a base width of the pyramid structure is greater than or equal to 5 μm and less than or equal to 9 μm; and / or, a length of a ridge of the pyramid structure is less than 10 μm.

15. The solar cell of claim 2, wherein, When the second texture structure is a pyramid structure, a height of the pyramid structure is greater than or equal to 1 μm and less than 4 μm; and / or, a base width of the pyramid structure is greater than or equal to 2 μm and less than 5 μm; and / or, a length of a ridge of the pyramid structure is less than 6 μm.

16. The solar cell of claim 2, wherein, A vertex of the first texture structure is farther away from the back side of the solar cell than a vertex of the second texture structure; and / or, a surface height difference between the edge region and the middle region is greater than or equal to 1 μm and less than or equal to 10 μm; and / or, in the front side of the semiconductor substrate, a surface of a region for connecting the edge region and the middle region is arranged to be inclined with respect to the surfaces of the edge region and the middle region, respectively.

17. The solar cell of claim 2, wherein, The width of the edge region is greater than 0 μm and less than or equal to 50 μm; the width direction of the edge region is consistent with the vertical direction of the vertical line between the first face and the second face.

18. The solar cell of claim 2, wherein, The size uniformity of the first texture structure located in the edge region is lower than the size uniformity of the second texture structure located in the middle region.

19. The solar cell of claim 2, wherein, The side face includes a third texture structure region, which is close to the first face.

20. The solar cell of claim 19, wherein, The ratio of the width of the third texture structure region to the width of the side face is less than 80%; the width direction of the third texture structure region and the width direction of the side face are both the vertical direction from the first face to the second face.

21. The solar cell of claim 19, wherein, The side face includes a fourth texture structure region, which includes a tower base structure; a plurality of the tower base structures are arranged along a first straight line, which is inclined with respect to a side edge of the side face.

22. The solar cell of claim 21, wherein, The plurality of first straight lines are parallel to each other; and / or, the included angle between the first straight line and the side edge of the side face is greater than or equal to 15° and less than or equal to 75°; and / or, the length of the first straight line is greater than the thickness of the semiconductor substrate, and the thickness direction of the semiconductor substrate is consistent with the vertical direction of the vertical line between the first face and the second face.

23. The solar cell of claim 19, wherein, An amorphous silicon layer is formed on the third texture structure region.

24. The solar cell of claim 21, wherein, A tunneling silicon oxide layer, a doped polysilicon layer and a silicon nitride layer are sequentially stacked on the fourth texture structure region.

25. The solar cell of claim 21, wherein, An amorphous silicon layer is coated on both the third texture structure region and the fourth texture structure region.

26. The solar cell of claim 2, wherein, The boundary line between the edge region and the middle region is a curve.

27. The solar cell according to any one of claims 1 to 26, further comprising a first type electrode and a second type electrode; the first type electrode is arranged on the first face side of the semiconductor substrate, and the second type electrode is arranged on the second face side of the semiconductor substrate; the first type electrode and the second type electrode are opposite in polarity.

28. The solar cell according to any one of claims 1 to 26, wherein The solar cell further comprises a first type electrode and a second type electrode; the first type electrode and the second type electrode are alternately and spacedly arranged on the second surface of the semiconductor substrate; the first type electrode and the second type electrode are opposite in polarity.

29. The solar cell of claim 28, wherein, The second surface has a first region and a second region alternately arranged along a first direction; the solar cell further comprises a first doped semiconductor layer arranged on the first region; a second doped semiconductor layer arranged on the second region and extending to cover part of the first doped semiconductor layer; the second doped semiconductor layer and the first doped semiconductor layer are opposite in conductive type.

30. A photovoltaic module comprising the solar cell of any one of claims 1 to 29, characterized in that, A plurality of the solar cells are connected to form a cell string.

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