Optoelectronic device with enhanced charge carrier injection

Abstract

The invention concerns an optoelectronic device based on a p-type down configuration that achieves enhanced hole injection into the active region through a combination of lateral hole injection and alignment of polarization dipoles in the active region with the depletion field, allowing reduction of efficiency droop and achievement of lower forward bias. The alignment of the polarization field with the depletion field in the active region reduces the electrostatic barrier for electron and hole injection, compared to conventional p-up LEDs.

Description

2024PF00153OPTOELECTRONIC DEVICE WITH ENHANCED CHARGE CARRIER INJECTIONThe present application claims priority from German patent application DE 10 2024 125 849 . 7 dated September 09 , 2024 , the disclosure of which is incorporated herein by reference in its entirety . The present invention concerns an optoelectronic device configured to achieve improved inj ection of charge carriers , in particular , holes into the active region . A manufacturing method allowing the achievement of the desired enhancement of hole inj ection within the device is also described .BACKGROUNDConventional light emitting diodes (LEDs ) are typically based on a common epitaxial structure where an active region is sandwiched between a p-doped layer and an n-doped layer to form a p-n j unction . The active region is commonly configured as a multi-quantum well (MQW) structure , comprising quantum well layers sandwiched between quantum barrier layers , with the materials selected such that the barrier layers are characterized by a wider bandgap than the quantum well layers .This structure results in challenges to carrier within the active region, particularly in nitride-based semiconductor devices . The carriers of each type , that is , electrons and holes , must diffuse from the n-doped and p-doped layers respectively into the active region, with the diffusion taking place from one quantum well to the next sequentially . The barrier layers between the quantum wells obstruct diffusion due to the wider bandgap . For electron inj ection, a higher mobility allows effective diffusion through multiple barrier layers within the active region, ensuring efficient distribution of electrons within the MQW structure . The mobility of holes in nitride-based semiconductors is however significantly lower than that of the electrons , with some materials exhibiting up to 20 times lower hole mobility in comparison with electron mobility . As a result , diffusion of holes into quantum wells farther away from the p-doped layer is hindered by successive barrier layers , such that , in some devices , holes are only inj ected in the one or two quantum wells directly adj acent to the p-doped layer . Recombination of holes therefore2024PF00153 primarily takes place m these quantum wells closest to the p-doped layer before the holes are able to diffuse further into the MQW structure .An existing approach to improving hole inj ection into the active region of LEDs involves use of v-pits to achieve lateral inj ection . V-pits are typically formed during epitaxial growth of semiconductor material , originating from threading dislocations in the semiconductor substrate which propagate through subsequent deposited layers , and potentially forming cavities in the form of inverted pyramids , particularly during the growth of the MQW structure . The v-pits extend through the active region and are transferred to subsequent layers deposited above the active region . V-pits , which extend through the MQW active region and facilitate lateral hole inj ection into QWs . Sometimes V-pits are overgrown .The presence of v-pits in the epitaxial structure can be exploited to improve carrier inj ection, as holes can be transported via the semi- polar facets of the v-pit , which are characterized by thinner quantum well and quantum barrier layers , into the deeper quantum wells . However, the size , density, and location of v-pits follow a statistically random distribution . For small-area LEDs , in particular , pLEDs , individual devices may randomly contain none or few v-pits , which can affect performance .Alternative lateral current inj ection designs have been proposed involving etching of MQW stacks and regrowth with p- and n-doped regions to form lateral p-n j unctions , for example , as reported by D . Schiavon et al . in "Lateral carri er inj ecti on for the uniform pumping of several quantum wells in InGaN / GaN light-emi tting di odes" ( doi : 10 . 1364 / OE . 411449 ) . The spacing between p- and n-regions is in the order of hole diffusion length, which is a few micrometers . The suggested approaches for lateral current inj ection provide a theoretically viable solution . However, technical realization of the proposed design is challenging , particularly in commercially viable quantities .2024PF00153In smaller LEDs , m particular, ]iLEDs , which are characterized by lateral dimensions in the range between 1 ]im and 100 ]im, an increase in the perimeter-to-area ratio with decreasing dimensions further contributes to a reduction in efficiency with reducing size . This is in part as a result of effects of surface recombination and sidewall damage becoming more pronounced with increasing perimeter-to-area ratio . Additional post-etch surface treatment increases the complexity and cost of processing , leading to a need for alternative approaches to processing of pLEDs which avoid introduction of surface defects to device sidewalls .It is an obj ect of the present application to introduce a manufacturing approach that achieves improved efficiency of hole inj ection into MQW structures of optoelectronic devices , in particular , by addressing the aforementioned challenges arising from barriers to hole inj ection within the active region .SUMMARY OF THE INVENTIONThis and other obj ects are addressed by the subj ect matter of the independent claims . Features and further aspects of the proposed principles are outlined in the dependent claims .The efficiency of nitride LEDs at high currents is often limited by Auger recombination . To reduce the concentration of carriers in the quantum wells , and thus minimize Auger recombination, the number of quantum wells needs to be increased . However , in nitride semiconductors , holes have up to 20 times lower mobility than electrons , thus holes are generally inj ected only in the one to two quantum wells next to the p-doped layer in conventional LEDs .Approaches involving lateral inj ection of holes into the active region, thus accessing quantum wells located further away from the p-doped layers have been proposed in US8026117B2 , US2022 / 0367751A1 , US2023 / 0110324A1 and US2023 / 0163238A1 . While achieving an improvement in rates of charge carrier inj ection, such approaches still face limitations arising from conventional epitaxial growth of semiconductor devices .2024PF00153Typical epitaxial growth of Il l-nitride LEDs involves deposition of semiconductor layers beginning with an n-type layer followed subsequently by an active region and p-type layers , with epitaxial growth oriented along the

[0001] direction with Il l-polarity, in particular , with Ga- , In- or Al- polarity . In such conventional devices , that is , n-type down semiconductor devices epitaxially grown on I ll-polar surfaces , polarization dipoles within the quantum well are oriented in opposite directions to the inherent depletion field, resulting in formation of electrostatic depletion barriers on both sides of the quantum well . These depletion barriers block both electron and hole inj ection into the quantum well causing a spatial separation between electron and hole wave functions , and a corresponding efficiency droop .While attempts have been made to address this challenge by growing semiconductor material on N-polar substrates , additional challenges arise when this approach is taken . In particular , N-polar semiconductor nitrides have been observed to have undesirable characteristics for epitaxial growth of optoelectronic devices including but not limited to lower chemical stability in comparison to I ll-polar nitrides , poor p-type doping due to lower Mg incorporation, and a rough hexagonal pyramidal surface morphology, which results in increased surface defects during epitaxial growth .Additionally, LEDs with smaller lateral dimensions , in particular , pLEDs are particularly susceptible to nonradiative recombination at the sidewalls , with the effect magnified by the high surface-area to volume ratio . The efficiency of pLEDs has thus been observed to drop with reducing lateral size . Surface defects introduced during manufacturing processes , in particular , during mesa structuring, which is typically conducted by wet and / or dry etching, serve as nonradiative recombination centers .The inventors propose an optoelectronic device with combined lateral and vertical hole inj ection and an inverted p-down structure2024PF00153 epitaxially grown along a I ll-polar direction of a II I-nitride semiconductor compound .While the description herein focuses on GaN-based pLED devices , the proposed approach is not restricted thereto , and can be applied to devices based on other I II-Nitride compounds .In some aspects , the proposed optoelectronic device comprises a first p-doped semiconductor layer comprising at least one recess . A semiconductor stack comprising a second p-doped layer , an active layer and an n-doped layer is arranged within the at least one recess , that is , the semiconductor stack is deposited in an epitaxial growth process on a I ll-polar surface of the underlying first p-doped semiconductor layer .The first p-doped semiconductor layer comprises a I II-nitride material , in particular, GaN . In some aspects , the first p-doped layer comprises a substantially uniform material with substantially constant dopant concentration . In other aspects , the first p-doped layer comprises a plurality of sublayers , with at least some of the plurality of sublayers comprising different materials and / or dopant concentration . In some aspects , at least one of the plurality of sublayers comprises undoped semiconductor material . In some aspects , the first p-doped layer comprises a dopant concentration gradient , in particular, with a p- dopant concentration changing with increasing vertical distance from the at least one recess .In some aspects , at least one intermediate p-doped layer is embedded within the first p-doped layer , such that the at least one intermediate p-doped layer is sandwiched between material of the first p-doped layer . The at least one intermediate p-doped layer comprises , in some aspects , a ternary or quaternary nitride , in particular, AlGaN and / or AlInGaN, and may alternatively or further comprise a dopant concentration different from the first p-doped layer, in particular , a higher dopant concentration . In other aspects , the at least one intermediate p-doped layer may comprise a plurality of sublayers , in particular , a superlattice structure comprising alternating sublayers2024PF00153 of a ternary or quaternary nitride and a second I II-nrtrrde material of different composition . The at least one intermediate p-doped layer enhances hole inj ection and improves reproducibility during the manufacturing process . The at least one intermediate p-doped layer comprises a thickness between 2 nm and 100 nm . In some aspects comprising a plurality of intermediate p-doped layers , the intermediate p-doped layers comprise substantially equal thicknesses . In other aspects , intermediate p-doped layers comprise different thicknesses . In some aspects , the thickness of the at least one intermediate p- doped layer is smaller than the thickness of each of the adj acent first p-doped layers on either side of the intermediate p-doped layer . In some aspects , at least one p-doped intermediate layer is positioned such that a bottom surface of the first p-doped semiconductor layer is covered by at least one intermediate p-doped layer . In some aspects comprising a plurality of intermediate p-doped layers , a vertical spacing between subsequent intermediate p-doped layers is uniform within the first p-doped layer . In other aspects , the spacing between subsequent intermediate p-doped layers is varied . In particular, in some aspects , the spacing between intermediate p-doped layers intersecting with the at least one recess in the first p-doped layer is smaller than the spacing between intermediate p-doped layers located vertically below the at least one recess in the first p-doped layer . n some aspects , the first p-doped layer comprises a heavily p-doped contact layer . In some workflows , the p-contact layer can be formed after the formation of the cavity by epitaxial overgrowth or by diffusion . In some other aspects , a heavily p-doped contact layer is epitaxially grown on the first p-doped layer prior to formation of the at least one recess . The heavily p-doped contact layer comprises a dopant concentration particularly of Mg between 5+10 19 cm-3to approximately 8 * 10 21 cm-3. The heavily p-doped contact layer facilitates improved ohmic contact to the p-doped layer of the optoelectronic device .The at least one recess in the first p-doped semiconductor layer is in some aspects formed through a photolithographic process , wherein a patterned mask comprising openings in the form of circles , hexagons ,2024PF00153 squares , or any other preferred shape is deposited on the first p- doped layer followed by dry or wet etching . The patterned mask may comprise any suitable dielectric material including but not limited to SiO2and / or SiNx. The lateral dimensions of the at least one recess are configured to be less than or equal to hole diffusion length within the material of the active region . In some aspects , the lateral dimensions of the at least one recess are less than 10]im, and, in particular , less than 5 ]im . The depth of the recess is such that a bottom surface of the recess comprises material of the first p-doped semiconductor layer , in some cases , the bottom of the recess can be formed by an undoped or insulating material to facilitate only lateral hole inj ection . The depth of the at least one recess is in some aspects between 50 nm and 500 nm, in particular , between 100 nm and 500 nm, in particular , between 100 nm and 300 nm. In some aspects , the at least one recess is formed such that sidewalls of the at least one recess at least partially comprise material of at least one intermediate p-doped layer .Within the at least one recess , a second p-doped layer is arranged in contact with the first p-doped layer . In particular, the second p- doped layer is arranged to cover the bottom surface and sidewalls of the at least one recess . In some aspects , the sidewalls of the second p-doped layer are deposited to form an inclined surface . In particular , the inclination of the sidewalls of the second p-doped layer is such that a lateral distance between the sidewalls of the second p-doped layer and the sidewalls of the at least one recess decreases with increasing distance from the bottom surface of the at least one recess . The angle of inclination can be configured through selection of process parameters during deposition of the second p-doped layer, in particular , to form sidewalls along semipolar facets of the semiconductor material , which are characteristically stable and slow- growing . In other aspects , the desired angle of inclination is formed by a wet and / or dry etching process subsequent to epitaxial growth of the second p-doped layer . In other aspects , the second doped layer comprises substantially perpendicular sidewalls at a lateral distance from the sidewalls of the at least one recess . In some aspects , the second p-doped layer comprises GaN . In other aspects , the second p-2024PF00153 doped layer comprises any binary or ternary I II-mtride , m particular but not limited to InGaN and / or AlGaN . In some aspects , the p-type doping of the second p-type layer can be higher or lower . Typically, Mg dopant concentration is in the range of l* 10 18 cm-3to 5 * 10 19 cm"3, and approximately 2 *10 20 cm-3for the contact layers . .The active layer is arranged on a Il l-polar surface of the second p- doped semiconductor layer facing away from the first p-doped semiconductor layer, in particular , within the at least one recess , such that the active layer comprises a bottom surface substantially parallel to the bottom of the at least one recess , and inclined sidewalls aligned along semipolar facets of the semiconductor material . The epitaxial growth of the active layer on a Il l-polar surface of a p-doped semiconductor layer results in a common orientation of polarization dipoles within the active layer and the depletion field, thereby reducing forward bias , allowing for enhanced carrier inj ection and reducing efficiency droop .The active layer comprises a multi-quantum well structure , wherein quantum well layers are arranged between quantum barrier layers , with the quantum barrier layers comprising a material with a wider bandgap than the quantum well layers . In some aspects , the active layer comprises alternating layers of GaN and at least one ternary and / or quaternary nitride . In other aspects , the active layer comprises alternating layers of ternary and / or quaternary nitrides with varying proportions of the II I-group elements . Quantum well and quantum barrier layers comprise smaller thickness along the inclined sidewalls than along substantially horizontal planes . In particular, the thickness of the quantum well and quantum barrier layers within the MQW structure decreases as the angle of inclination approaches the perpendicular .Hole inj ection into the active layer from the adj acent second p-doped layer occurs both laterally through the inclined sidewalls and vertically through the bottom surface of the active layer . Laterally inj ected holes diffuse parallel to the quantum barriers , allowing efficient diffusion into most or all quantum wells , including those further away from the p-doped layer . As a result , uniform pumping of2024PF00153 many quantum wells is achieved . The reduced thickness of the quantum barriers along the inclined sidewalls results in a lower potential barrier and a correspondingly lower resistance and shorter current path . This may lead to a prevalence of lateral hole inj ection in some aspects . In other aspects , suitable design of the first p-doped layer and the intermediate p-doped layers allows for control of the balance between lateral and vertical inj ection .The n-doped layer is deposited on the active layer within the at least one recess . In some aspects , an upper surface of the n-doped layer is substantially coplanar with an upper surface of the first p-doped layer . In some such aspects , the semiconductor stack is thereby epitaxially grown and formed into a mesa structure within the at least one recess without requiring an etching process to define the sidewalls of the optoelectronic device . Etching-related defects which may serve as non-radiative recombination centres can thereby be avoided, resulting in increased quantum efficiency .In other aspects , the structured mas k used during formation of the at least one recess is removed after etching of the holes , and the inverted p-down semiconductor stack comprising the second p-doped layer , the active layer and the n-doped layer is grown over the entire surface of the first p-doped layer , filling in the at least one recess and extending laterally beyond the recess . In some such aspects , a subsequent etch is used to form at least one protruding mesa structure aligned to the at least one recess , such that an upper surface of the n-doped layer protrudes vertically above the upper surface of the first p-doped layer . In some such aspects , the cross-sectional area of the at least one protruding mesa structure is smaller than or equal to the cross-sectional area of the at least one recess . Where the cross- sectional area of the at least one protruding mesa structure is smaller than the cross-sectional area of the at least one recess , the base of the at least one protruding mesa structure is laterally surrounded by material of the second p-doped layer . In aspects wherein the crosssection of the at least one protruding mesa structure is equal to the cross-sectional area of the at least one recess , the thickness of the second p-doped layer may be configured to extend vertically beyond the2024PF00153 top of the at least one recess , such that the sidewalls of the at least one protruding mesa structure comprise material of the second p-doped layer at a horizontal plane corresponding to the upper surface of the first p-doped layer . In other aspects , a passivation layer is deposited on the sidewalls of the mesa structure , preventing the active layer and / or the n-doped layer from contacting the first p-doped layer .The sidewalls of the mesa structure are in some aspects subj ected to surface treatment to mitigate defects arising from the mesa structuring process , such surface treatment including but not limited to regrowth processes , sidewall passivation and / or annealing . In some such aspects post-growth diffusion of p-dopant , in particular , Mg , into the first p-doped layer is required to improve ohmic characteristics .In other aspects of the proposed invention wherein deposition of the semiconductor layer stack is performed over the entire surface of the first p-doped layer rather than confined to the at least one recess , no growth enhancement occurs due to selective growth, and the epitaxial growth process is independent of pixel size and pitch . The chip manufacturing process is however more complicated, and the etching process used for mesa structuring may result in damage to the upper surface of the first p-doped layer , thereby reducing concentration of p-dopant at the surface and increasing ohmic resistance of the upper layer .In other aspects , subsequent to deposition of the semiconductor layer stack on the upper surface of the first p-doped layer, the epitaxially grown layers are planarized to expose the upper surface of the first p-doped layer , such that an upper surface of the n-doped layer is coplanar with the upper surface of the first p-doped layer . The sidewalls of the resultant optoelectronic device , in particular, the sidewalls of the active layer , are thereby confined within the recess in the first p-doped layer, avoiding etching-related defects on the sidewalls of the device which contribute to non-radiative recombination and a corresponding reduction in quantum efficiency of the optoelectronic device .2024PF00153At least one first contact element is m some aspects deposited laterally adj acent to the at least one recess , allowing realization of an electric connection to the second p-doped layer . The first contact element may be arranged on an upper surface of the first p-doped layer or the heavily p-doped contact layer . In other aspects , the first contact element is deposited on a bottom surface of the first p-doped layer, resulting in a vertical LED configuration . A via comprising electrically conductive material may be arranged between the at least one first contact element and the second p-doped layer . In some such aspects , the upper surface of the first p-doped layer laterally adj acent to the at least one recess comprises a dielectric layer .Additionally, at least one second contact element is deposited to form an electrical connection to the n-doped layer . In some aspects , each of the at least one second contact element corresponds to one semiconductor mesa stack arranged in the at least one recess , allowing for independent operation and / or control of each optoelectronic device . In other aspects , at least some optoelectronic devices may be connected to form monolithically integrated arrays , wherein each array comprises at least one first contact element and at least one second contact element .Some aspects of the proposed invention relate to a method of processing an optoelectronic device in accordance with the proposed principle . In an initial step , a growth substrate is provided . The growth substrate may comprise any suitable material including but not limited to silicon, sapphire and / or bulk GaN . In some aspects , the growth substrate is subj ected to surface preparation processes prior to epitaxial growth of the proposed optoelectronic device . Such surface preparation processes include but are not limited to planarization, polishing, structuring and / or annealing . In some aspects , the step of providing a growth substrate further comprises a step of depositing a buffer layer, which is in this description considered to be part of the growth substrate . Such a buffer layer may comprise doped or undoped semiconductor material , and may in some aspects provide a growth template for subsequent epitaxial growth .2024PF00153In a subsequent step, a first p-doped semiconductor layer is deposited on the growth substrate , optionally including a buffer layer . The first p-doped semiconductor layer is epitaxially grown on a Il l-polar surface of the growth substrate , such that subsequent layers are also grown on I l l-polar surfaces . The first p-doped layer in some aspects comprises GaN, or any other binary or ternary semiconductor nitride . In some aspects , at least one intermediate p-doped layer is deposited within the first p-doped layer such that the at least one intermediate p- doped layer is sandwiched between material of the p-doped layer . The at least one intermediate p-doped layer comprises a ternary or quaternary semiconductor nitride , in particular , AlGaN and / or AlInGaN . In some aspects , a heavily p-doped contact layer is deposited on the upper surface of the first p-doped layer . The heavily p-doped contact layer comprises a concentration of p-dopant greater than the first , second and intermediate p-doped layer , in particular , a dopant concentration than the range of 10 20 cm-3, with an order of magnitude n both direction .Thereafter , a patterned dielectric mas k, in particular , a Si02 mask, is deposited on the first p-doped semiconductor layer or the optional heavily p-doped contact layer . The patterning in the dielectric mas k may comprise at least one circular , hexagonal or square opening with lateral dimensions smaller than 10 pm, in particular, smaller than 5 pm . At least one recess is etched into the first p-doped semiconductor layer to a depth of between 100 nm and 500 nm, in particular , between 100 nm and 300 nm.In a subsequent step , a second p-doped semiconductor layer is deposited on the first p-doped semiconductor layer, in particular, within the at least one recess . The process parameters during the deposition process are in some aspects configured to produce growth along semipolar facets , resulting in inclined sidewalls . In other aspects , the epitaxial growth is conducted to form substantially perpendicular sidewalls . Alternatively or additionally, a post-growth etching process may be conducted on the deposited second p-doped layer to achieve the desired angle of inclination along the sidewalls . However, it is more2024PF00153 common m some aspects to control the inclination of the facets during the etching of the cavity or during regrowth .An active layer is then deposited on the second p-doped layer, said active layer comprising a multi-quantum well structure . The active layer may comprise one or several binary, ternary and / or quaternary nitrides . In some aspects the quantum well and quantum barrier layers respectively comprise different material copositions . In other aspects , material composition varies across quantum well layers and / or quantum barrier layers . The active layer comprises sidewalls with an inclination angle substantially equal to the inclination angle of the sidewalls of the second p-doped layer . In some aspects comprising sidewalls , the thickness of the quantum well and quantum barrier layers along the vertical or inclined sidewalls is smaller than the thickness of corresponding quantum well and quantum barrier layers along substantially horizontal planes .Thereafter , an n-doped layer is deposited on the active layer . In some aspects , an upper surface of the n-doped layer is coplanar with or vertically below the upper surface of the first p-doped layer or the heavily p-doped contact layer, such that the semiconductor stack lies entirely within the at least one recess . In such aspects , the sidewalls of the semiconductor stack require no further processing, in particular , surface treatment for mitigation of sidewall defects .Additional processing steps include removal of the dielectric mas k and deposition of at least one first and at least one second contact element , providing electrical connection to the p-doped layer and the n-doped layer respectively . The at least one first contact element is in some aspects deposited on an upper side of the first p-doped layer or on the heavily p-doped layer laterally adj acent to the at least one recess . In other aspects , the growth substrate and the buffer layers are removed in further processing steps , such that a bottom surface of the optoelectronic device comprises material of at least of the first p-doped layer or at least one intermediate p-doped layer . In some such aspects , the at least one first contact element may be deposited on the bottom p-doped surface . An optional via comprising an electrically2024PF00153 conductive material is arranged between the first contact element and the second p-doped layer in some such aspects . In other aspects , a protective layer , in particular, a dielectric layer, is deposited on the bottom surface .In other aspects related to processing of the proposed optoelectronic device , subsequent to etching of the at least one recess in the first p-doped layer, the dielectric mask is removed . Thereafter, the second p-doped layer, the active layer and the n-doped layer are sequentially deposited all over the surface of the first p-doped layer , extending laterally beyond the at least one recess . In a subsequent step , the semiconductor layers are structured to expose the upper surface of the first p-doped layer and form at least one mesa stack . In some aspects , the at least one mesa stack is structured by etching away material laterally adj acent to the at least one recess in the first p-doped layer . In some such aspects , the resultant mesa stack protrudes vertically above the upper surface of the first p-doped layer . In other aspects , a planarization process is carried out to expose the first p- doped layer such that the active region is contained within the at least one recess and an upper surface of the n-doped layer is coplanar with the upper surface of the first p-doped layer . Additional processing steps include but are not limited to post-growth deposition of additional p-dopant into the upper surface of the first p-doped layer, removal of the growth substrate and buffer layers , depositing at least one first and at least one second contact element , wherein the at least one first contact element is electrically connected to the second p-doped layer and the at least one second contact element is electrically connected to the n-doped layer . In some aspects , the first contact element is deposited on the upper surface of the first p-doped layer, laterally adj acent to the at least one recess . In other aspects , the first contact element is deposited on the bottom surface of the first p-doped layer , and optionally connected to the second p- doped layer through a connecting via within the first p-doped layer .SHORT DESCRIPTION OF THE DRAWINGSFurther aspects and embodiments in accordance with the proposed principle will become apparent in relation to the various embodiments2024PF00153 and examples described m detail m connection with the accompanying drawings in whichFigure 1 graphically illustrates the relationship between polarization and inherent depletion barriers in semiconductor device layers as commonly implemented in conventional approaches ;Figures 2A to 2C illustrate steps in a method for manufacturing an optoelectronic device in accordance with some aspects of the proposed principle ;Figures 3A to 3C illustrate alternative steps in a method for manufacturing an optoelectronic device in accordance with some aspects of the proposed principle ;Figure 4 illustrates an optoelectronic device during an intermediate processing step in accordance with some aspects of the proposed principle .DETAILED DESCRIPTIONThe following embodiments and examples disclose various aspects and their combinations according to the proposed principle . The embodiments and examples are not always to scale . Likewise , different elements can be displayed enlarged or reduced in size to emphasize individual aspects . It goes without saying that the individual aspects of the embodiments and examples shown in the figures can be combined with each other without further ado , without this contradicting the principle according to the invention . Some aspects show a regular structure or form . It should be noted that in practice slight differences and deviations from the ideal form may occur without , however , contradicting the inventive idea .In addition, the individual figures and aspects are not necessarily shown in the correct size , nor do the proportions between individual elements have to be essentially correct . Some aspects are highlighted by showing them enlarged . However , terms such as "above" , "over" ,2024PF00153 16"below", "under" "larger", "smaller" and the I ke are correctly represented with regard to the elements in the figures. So it is possible to deduce such relations between the elements based on the figures .Figure 1 illustrates the effect of polarization dipoles within quantum wells in conventional LEDs, as reported by Keller et al. (2014) , "Recent progress in metal-organic chemical vapor deposition of (0001) N-polar group-III nitrides", (doi : 10.1088 / 0268-1242 / 29 / 11 / 113001) . Semiconductor devices epitaxially grown on GaN substrates typically use Ga-polar substrates, thereby resulting in epitaxial growth along the

[0001] crystal direction, as illustrated in Figure 1 (a) . The implementation of an n-type down, p-type up structure, wherein epitaxial growth involves sequentially growing an n-doped semiconductor layer on a growth substrate, subsequently followed by an active region and a p-doped semiconductor layer. The inherent polarization dipole EPof the semiconductor stack is oriented in opposition to the depletion field Eblcreated by the p-n junction. As a result, depletion barriers are formed on both sides of the quantum well, opposing both electron and hole injection into the quantum well.A previously proposed solution is presented in Figure 1 (b) , involving use of an N-polar substrate, resulting in epitaxial growth along a [000-1] crystal direction. This results in a reversal of the orientation of polarization dipoles in the active region such that the internal polarization field EPis oriented along the same direction as the depletion field Eblcreated by the p-n junction. The depletion barriers formed at the boundaries of the quantum well are consequently reduced in comparison to similar semiconductor stacks grown on Ga- polar substrates . The reduction in electrostatic barriers enables lower turn-on voltage and more efficient current injection into the active region, in particular, more efficient hole injection. Figure 1 (c) shows the internal polarization field and the depletion field Eblcreated by the p-n junction for an epitaxial growth along a

[0001] crystal direction .2024PF00153The implementation of an n-type down, p-up structure on N-polar substrate faces challenges related to the structural characteristics of N-polar semiconductor material . In particular , N-polar substrates are characterized by lower chemical stability, poor p-type doping due to lower Mg incorporation, and rough hexagonal pyramidal surface morphology . Any enhancements in quantum efficiency resulting from the matching of the orientation of the polarization dipoles to the depletion field through use of an N-polar substrate therefore has to be weighed against more complex and costlier pre-processing steps required to prepare the surface of the substrate for epitaxial growth, and measures to counteract inefficiencies during doping of the p-type layer .In this regard, the proposed invention achieves the desired matching orientation of polarization dipoles to the depletion field in the active region of the optoelectronic device while taking advantage of the superior structural qualities of Ga-polar GaN substrates by reversing the order of epitaxial growth such that the depletion field is reversed while the epitaxial sructure is grown along the

[0001] direction .A first step in a manufacturing method according to the proposed principle , illustrated in Figure 2A, involves providing a first p- doped semiconductor layer ( 10 ) comprising a I ll-nitride . In some aspects , the first p-doped semiconductor layer ( 10 ) is deposited on a growth substrate ( not shown ) , in particular , on a Ga-polar surface of a growth substrate . In some aspects , the growth substrate comprises silicon or sapphire . In other aspects , the growth substrate comprises bulk GaN, which may be undoped or lightly doped . In some aspects , a heavily p-doped contact layer ( 12 ) is deposited on the first p-doped semiconductor layer . The heavily p-doped contact layer ( 12 ) is in some aspects produced by introducing material comprising a p-dopant , such as Mg onto the surface of the first p-doped semiconductor layer, and configuring process parameters to achieve a desired thickness with the required concentration of p-dopant to facilitate electrical contact .2024PF00153 18In a subsequent step, a patterned mask (40) is deposited on the first p-doped layer (10) and optional contact layer (12) , the patterned mask comprising at least one opening. The opening may be circular, hexagonal, square or any other suitable shape desired for the optoelectronic device. A subsequent etching process is conducted to form at least one recess (20) in the first p-doped semiconductor layer (10) . The lateral dimensions of the recess are selected to be smaller than the hole diffusion length, and are in some aspects less than 10 ]im, and, in particular, less than 5 m. In some aspects the depth of the at least one recess is in the range between 100 nm and 500 nm, and in particular, between 100 nm and 300 nm.Figure 2B shows a subsequent step, wherein a semiconductor layer stack is deposited within the at least one recess (20) in the first p-doped semiconductor layer. A second p-doped layer (22) is deposited within the at least one recess (20) such that the bottom and sidewalls of the recess comprise p-doped material. The second p-doped layer (22) comprises, in some aspects, different material and / or dopant concentration from the first p-doped layer (10) . In some aspects, the second p-doped layer comprises inclined sidewalls, such that a lateral distance from the sidewalls of the at least one recess (20) and the sidewalls of the second p-doped layer (22) decreases with increasing distance from the bottom of the at least one recess. In other aspects, the second p-doped layer comprises substantially perpendicular sidewalls .Thereafter, an active layer (23) is deposited on a surface of the second p-doped layer (22) facing away from the first p-doped layer (10) , such that an upper surface and the sidewalls of the second p- doped layer are covered by material of the active layer. The active layer comprises a multi-quantum well (MQW) structure, wherein quantum well layers are sandwiched between quantum barrier layers comprising a material with a wider bandgap than the adjacent quantum well layers.The actilayer may comprise binary, ternary and / or quaternary nitrides in different combinations, or with different material compositi ns . In some aspects, the active layer comprises a binary2024PF00153 19 nitride alternating with a ternary or quaternary nitride . In other aspects , the active layer comprises alternating layers of ternary and / or quaternary nitrides with different composition in terms of the II I-group elements .The surface profile of the active layer follows the underlying second p-doped layer ( 22 ) . Where the second p-doped layer comprises inclined sidewalls , quantum well and quantum barrier layers within the MQW structure comprise a thinner thickness along the inclined sidewalls and a different material composition in terms of II I-group elements but with a wider bandgap as compared to the portions on the horizontal c-plane as compared to deposits along substantially horizontal planes , with the thickness of the layers decreasing with increase in inclination angle up to 90 ° . Where the second p-doped layer comprises substantially perpendicular sidewalls , the active layer is deposited substantially along a substantially horizontal plane , bounded by the sidewalls of the p-doped layer . The quantum well structure will also grow on the vertical sidewalls , but it will be significantly thinner .The deposition of the active layer within a recess in the p-doped second layer ( 23 ) allows both vertical and lateral inj ection of holes from the second p-doped layer ( 22 ) into quantum wells in the active layer ( 23 ) , with vertical inj ection taking place vertically upwards from the underlying p-doped layer, and lateral inj ection taking place from the sidewalls of the p-doped layer . Where the p-doped layer is inclined, the thinner quantum barrier layers in the MQW structure offer less obstruction to hole mobility, resulting in more efficient inj ection of holes into quantum wells farther away from the p-doped layer .In some aspects , the inclination angle of the sidewalls of the second p-doped layer ( 22 ) is achieved through suitable configuration of growth parameters during the deposition process . This allows formation of device sidewalls free of etching-related damage , thereby improving quantum efficiency of the optoelectronic device . In other aspects , the desired angle of inclination is achieved by etching the second p-doped layer ( 23 ) prior to deposition of the active layer . Subsequent regrowth2024PF00153 20 or other surface treatment may be performed to mrtrgate formation of etch-related defects during structuring of the second p-doped layer to achieve a desired sidewall morphology.In a subsequent step, an n-doped semiconductor layer (24) is deposited on a surface of the active layer facing away from the p-doped layers . The n-doped layer (24) is configured to have a substantially horizontal upper surface (241) . In some aspects, the upper surface (241) of the n-doped layer is co-planar with an upper surface of one of the first p-doped layer (10) or the heavily p-doped contact layer (12) , such that the n-doped layer does not extend vertically or laterally beyond the at least one recess (20) .Such a geometry is quite advantageous for processing due to the planarized surface.Thereafter, as shown in Figure 2C, electrical contact surfaces comprising at least one first contact element (31) and at least one second contact element (32) are deposited to provide electrical connection to the p-doped and n-doped layers respectively. The exemplary embodiment illustrated herein comprises contact surfaces arranged on surfaces of the optoelectronic device facing away from a bottom surface of the first p-doped semiconductor layer (10) to form a horizontal pLED. In other aspects, not herein illustrated, at least one first contact surface is arranged on a surface of the first p- doped layer (20) facing away from the n-doped layer, and, optionally connected to the second p-doped layer (22) through a connecting channel formed within the first p-doped layer (10) . The upper surface of the p-doped layer is in some such aspects covered by a protective dielectric layer .Alternative steps in a method of processing an optoelectronic device according to some aspects of the proposed principle are illustrated in Figures 3A to 3C. In an initial step, a first p-doped layer (10) is provided, and at least one recess (20) is etched into the first p- doped layer. In a subsequent step, illustrated in Figure 3B, a second p-doped layer (22) is deposited on an upper surface of the first p- doped layer (10) such that a continuous layer is formed within the at least one recess, extending laterally to cover surfaces of the first2024PF00153 21 p-doped layer (10) surrounding the at least one recess. In some aspects, growth parameters during the epitaxial growth process are configured to produce inclined sidewalls on the second p-doped layer (22) within the at least one recess. In other aspects, inclined sidewalls are produced through an etching process subsequent to deposition of the second p-doped layer (22) .Thereafter, an active layer (23) is deposited on the second p-doped layer (22) , such that material of the active layer (23) within the at least one recess comprises a substantially horizontal bottom surface and inclined sidewalls. Material of the active layer (23) further extends laterally to surround the at least one recess. In a next step, an n-doped layer (24) is deposited on a surface of the active layer (23) facing away from the second p-doped layer (22) .A subsequent step, illustrated in Figure 3C, involves a mesa structuring process, wherein deposited material surrounding the at least one recess is removed to expose an upper surface (14) of the first p-doped layer (10) , from which a semiconductor mesa stack (25) corresponding to the at least one recess protrudes vertically above the first p-doped layer (10) . In particular, an upper surface (241) of the n-doped layer protrudes vertically above the upper surface (14) of the first p-doped layer (10) . In some aspects the lateral dimensions of the protruding semiconductor stack (25) are smaller than the lateral dimensions of the at least one recess, such that the protruding mesa stack (25) is laterally surrounded by material of the second p-doped layer (22) for a lateral distance. In other aspects, the lateral dimensions of the protruding semiconductor mesa stack are substantially equal to the lateral dimensions of the at least one recess, such that the mesa stack is laterally surrounded by material of the first p- doped layer (10) . The mesa structuring process may involve wet and / or dry etching processes, and is in some aspects followed by at least one surface treatment process including but not limited to passivation, regrowth and / or annealing processes.At least one first contact element (31) and at least one second contact element (32) are connected to the first p-doped layer (10) and the n-2024PF00153 doped layer (25) respectively, providing electrical connection to the optoelectronic device. In some aspects, a heavily p-doped contact layer is arranged on an upper surface of the first p-doped layer (10) prior to arranging the first contact element (31) . In other aspects, the dopant concentration of the upper surface of the first p-doped layer (10) is increased in a subsequent deposition process through which p- dopant material, in particular, material comprising Mg, is deposited on the upper surface of the first p-doped layer (10) . The post-growth diffusion of p-dopant into the first p-doped layer improves the ohmic contact between the first contact element (31) and the first p-doped layer (10) , mitigating any etching-induced damage developed during the mesa structuring process .Figure 4 shows an optoelectronic device at an intermediate step in a manufacturing process in accordance with some aspects of the proposed principle. A growth substrate (50) is provided. The growth substrate comprises any suitable material for growth of Ill-nitride semiconductor materials, including but not limited to silicon, sapphire and / or bulk Ill-nitride substrates, in particular, comprising binary Ill-nitride compounds. The growth substrate is in some aspects subjected to surface preparation processes including but not limited to polishing, structuring and / or annealing. In some aspects, the material composition of the growth substrate is substantially homogeneous. In other aspects, the growth substrate comprises a plurality of sublayers comprising different material compositions. In some aspects, the growth substrate (50) comprises a buffer layer (52) deposited on the surface of the growth substrate. The buffer layer (52) is deposited along a Ga-polar surface of the growth substrate, and may comprise undoped, lightly doped or p-doped material.The optoelectronic device further comprises a first p-doped layer (10) deposited on the growth substrate (50) and optional buffer layer (52) . The first p-doped layer (10) comprises, in some aspects, a substantially uniform material composition and / or dopant concentration. In other aspects, the first p-doped layer comprises different material composition and / or dopant concentration. The first p-doped layer comprises any suitable binary, ternary or quaternary III-2024PF00153 nitride. In particular, the first p-doped layer may comprise GaN. At least one recess is formed in the first p-doped layer (11) . A semiconductor layer stack comprising a second p-doped layer (22) , an active layer (23) and an n-doped layer (24) is deposited in the at least one recess. The second p-doped layer (22) and the active layer (23) in some aspects comprise inclined sidewalls, wherein quantum wells and quantum barrier layers comprising the active layer are characterized by a smaller thickness along the inclined sidewalls as compared to along substantially horizontal planes. This allows for enhanced lateral hole injection due to a reduction in the obstruction to hole mobility by the thinner quantum barrier layers, it may also happen during growth that Ga-content (for AlGaN) and In-content (for InGaN or AlInGaN) is lower as compared to horizontal planes.In some aspects, at least one intermediate p-doped layer (11) comprising a material and / or dopant concentration different from the first p-doped layer (10) is deposited during deposition of the first p-doped layer, such that the at least one intermediate p-doped layer (11) is sandwiched between sublayers comprising the first p-doped layer (10) . In some aspects, the at least one intermediate p-doped layer may comprise a ternary or quaternary nitride, in particular AlGaN, InGaN and / or AlInGaN. In some aspects, a plurality of intermediate p-doped layers (11) are sandwiched between a plurality of sublayers comprising the first p-doped layer (10) . The plurality of intermediate p-doped layers (11) may comprise the same material composition and dopant concentration. In other aspects, the material composition and dopant concentration of the plurality of intermediate p-doped layers (11) varies within the epitaxial structure. In some aspects, the dopant concentration in the plurality of intermediate p-doped layers (11) is configured to produce a concentration gradient.Some aspects of the optoelectronic device further comprise a heavily p-doped layer (12) arranged on a surface of the first p-doped layer (10) adjacent to the at least one recess formed in the first p-doped layer. In some aspects, the second p-doped layer (22) partially extends laterally beyond the at least one recess. In other aspects, the second p-doped layer is confined within the at least one recess, extending to2024PF00153 24 vertically cover the sidewalls of the at least one recess, thereby preventing contact between the heavily p-doped layer (12) and the active layer (23) and / or the n-doped layer (24) . In other aspects, sidewalls of the semiconductor mesa stack extending beyond the upper 5 surface of the first p-doped layer (10) are passivated, in particular, by depositing a dielectric material thereon.2024PF00153LIST OF REFERENCES10 first p-doped layer11 intermediate p-doped layer12 heavily doped p-contact layer14 upper surface of first p-doped layer20 recess22 second p-doped layer23 active layer24 n-doped layer25 semiconductor mesa structure241 upper surface of n-dope layer31 first contact element32 second contact element40 structured dielectric mas k50 growth substrate52 buffer layer

Claims

2024PF00153CLAIMS1 . Optoelectronic device comprising :A first p-doped semiconductor layer ( 10 ) ;At least one recess ( 20 ) within the first p-doped semiconductor layer ( 10 ) ;A semiconductor layer stack arranged within the at least one recess in the first p-doped semiconductor layer, said semiconductor layer stack comprising :A second p-doped semiconductor layer ( 22 ) arranged in contact with the first p-doped semiconductor layer , wherein the second p-doped semiconductor layer comprises a binary, ternary or quaternary I l l-nitride compound, and wherein the second p-doped semiconductor layer is arranged on a Il l-Polar surface of the first p-doped semiconductor layer;An active region ( 23 ) arranged on a surface of the second p- doped semiconductor layer facing away from the first p-doped semiconductor layer ;An n-doped semiconductor layer ( 24 ) arranged on a surface of the active region; wherein the active region is characterized by polarization dipoles in the same direction as a depletion field therein .2 . Device according to claim 1 , wherein the second p-doped semiconductor layer comprises sidewalls which are at least partially laterally distanced from the sidewalls of the at least one recess , and wherein the lateral distance between the sidewalls of the second p-doped semiconductor layer and the first p-doped semiconductor layer decreases with increasing distance from a bottom surface of the at least one recess .3 . Device according to claim 1 , wherein the second p-doped semiconductor layer comprises substantially perpendicular sidewalls .2024PF001534 . Device according to any of the preceding claims , further comprising a heavily doped p-contact layer ( 12 ) arranged on a surface of the first p-doped semiconductor layer laterally adj acent to and surrounding the at least one recess , and comprising a p-dopant concentration greater than or equal to 10 20 cm-3.5 . Device according to claims 1 to 4 , wherein an upper surface ( 241 ) of the n-doped semiconductor layer facing away from the active region is substantially flush with an upper surface of one of the heavily doped p-contact layer and the first p-doped semiconductor layer ; and / or wherein an upper surface of the active region is below an upper surface of the first p-type layer .6 . Device according to any of claims 1 to 4 , wherein an upper surface ( 241 ) of the n-doped semiconductor layer facing away from the active region protrudes above an upper surface of the first p-doped layer .7 . Device according to claim 6 , wherein sidewalls of the semiconductor stack extending vertically above the upper surface of the first p- doped semiconductor layer and / or the heavily p-doped contact layer comprise a passivation layer .8 . Device according to any of the preceding claims wherein the first p-doped semiconductor layer comprises GaN .9 . Device according to any of the preceding claims , further comprising at least one intermediate p-doped layer ( 11 ) embedded within material of the first p-doped semiconductor layer .10 . Device according to claim 9 , wherein the at least one intermediate p-doped layer comprises a thickness between 2 nm and 100 nm.11 . Device according to any of claims 9 or 10 , wherein the at least one intermediate p-doped layer comprises a ternary or quaternary GaN compound, in particular , AlGaN and / or AlInGaN .12 . Device according to any of the preceding claims , further comprising at least one first contact element electrically connected to the p-2024PF00153 28 doped semiconductor layer and at least one second contact element electrically connected to the n-doped semiconductor layer .13 . Device according to claim 12 , wherein the first contact element is arranged on a surface of the first p-doped semiconductor layer laterally adj acent to the at least one recess .14 . Device according to claim 12 , wherein the first contact element is arranged on a surface of the first p-doped semiconductor layer facing away from the n-doped semiconductor layer .15 . Device according to claim 14 , further comprising a dielectric layer on an upper surface of the p-doped material laterally surrounding the semiconductor layer stack .16 . Device according to any of the preceding claims , wherein the at least one recess comprises at least one of the following in plan view : a circle a hexagon; a rectangle , a square ; and a triangle .17 . Device according to any of the preceding claims , wherein the at least one recess is characterized by lateral dimensions between 1 ]im and 10 m.18 . Device according to any of the preceding claims , wherein a depth of the at least one recess is between 100 nm and 500 nm, in particular , between 100 nm and 300 nm .19 . Device according to any of the preceding claims , wherein a concentration profile of p-dopant within at least one of the first p-doped semiconductor layer , the intermediate p-doped layers and / or the p-doped semiconductor layer in the semiconductor stack varies along the direction of epitaxial growth .20 . Method of processing an optoelectronic device , comprising the steps :Providing a growth substrate ( 50 ) ;2024PF00153 29Depositing a first p-doped semiconductor layer ( 10 ) on the growth substrate ;Etching at least one recess into the first p-doped semiconductor layer ;Depositing a semiconductor stack into the at least one recess , said semiconductor stack comprising a second p-doped semiconductor layer ( 22 ) , an active layer ( 23 ) and an n-doped layer ( 24 ) respectively arranged sequentially within the at least one recess ;Arranging at least one n-contact element ( 32 ) on a surface of the n-doped semiconductor layer ( 24 ) facing away from the active layer ( 23 ) .21 . Method according to claim 20 , wherein the step of depositing a semiconductor stack is such that the semiconductor layers additionally extend vertically and laterally beyond the at least one recess .22 . Method according to claim 21 , further comprising a step of patterning and etching the semiconductor stack to form at least one mesa structure corresponding to the at least one recess and protruding above an upper surface of the first p-doped semiconductor layer .23 . Method according to claim 21 , further comprising a step of planarizing the deposited semiconductor material such that an upper surface of the first p-doped layer is exposed, and wherein an upper surface of the n-doped layer is coplanar with the exposed upper surface of the first p-doped layer .24 . Method according to any of claims 20 to 23 wherein the step of providing a growth substrate further comprises a step of depositing at least one buffer layer ( 52 ) on a surface of the growth substrate .25 . Method according to any of claims 20 to 24 , wherein the step of depositing a semiconductor stack is configured such that the p- doped layer, the active layer and at least part of the n-doped layer2024PF00153 within the at least one recess comprise inclined sidewalls facing away from the sidewalls of the at least one recess .26 . Method according to any of claims 20 to 25 , further comprising a5 step of depositing a heavily p-doped contact layer ( 12 ) on a surface of the first p-doped semiconductor layer laterally adj acent to and surrounding the at least one recess .27 . Method according to any of claims 20 to 26 , further comprising a0 step of arranging a p-contact element on one of :A surface of the first p-doped semiconductor layer or the heavily doped p-contact layer laterally adj acent to the at least one recess , orA surface of the first p-doped semiconductor layer facing5 away from the active layer .28 . Method according to any of claims 20 to 27 , further comprising a step of introducing additional p-dopant into the first p-doped semiconductor layer subsequent to the step of depositing a0 semiconductor stack within the at least one recess .

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