Information processing device, encoding processing method, and program

Abstract

One aspect of the present invention is an information processing device comprising: a control symbol imparting function unit that imparts a control symbol, which is information pertaining to a frame, to a received packet; a header determination function unit that decomposes the received packet and determines header data indicating a data vector or a control vector on the basis of the result of the decomposing; a buffer function unit that buffers the header data and the packet to which the control symbol has been imparted, and sends the buffered data; and a header imparting function unit that receives the buffered data sent from the buffer function unit, and imparts a header determined by the header determination function unit to the packet to which the control symbol has been imparted. When the control symbol imparting function unit, the header determination function unit, and the buffer function unit perform sequential processing, the header imparting function unit performs parallel processing to encode the received packet.

Description

Information processing device, encoding method and program

[0001] The present invention relates to an information processing device, an encoding method, and a program technology.

[0002] Various encoding methods have been proposed for communications. For example, the technology described in Non-Patent Document 1 has the functions of packet reception, control symbol assignment, and 2-bit header determination and assignment. Packet reception is a function for receiving packets. Control symbol assignment is a function for assigning control symbols to received packets to determine the start and end positions of a frame. 2-bit header determination is a function for decomposing received packets and determining a 2-bit header indicating whether it is a data vector or a control vector. 2-bit header assignment is a function for assigning the determined 2-bit header by 2-bit header determination.

[0003] Marek Hajduczenia, "64b / 66b line code", ZTE Corporation, <https: / / www.ieee802.org / 3 / epoc / email / pdfQyrtvJB0Vn.pdf>, Internet search 2024.8.15

[0004] However, while the conventional technology can be easily implemented in hardware that is suitable for bit-wise operations, when implemented in software that performs byte-wise operations, the 2-bit header addition operation requires sequential bit shift operations, which increases the amount of calculation and takes time for the operation. In view of the above circumstances, the present invention aims to provide a technology that can process encoding at high speed.

[0005] One aspect of the present invention is an information processing device comprising: a control symbol assignment functional unit that assigns control symbols to received packets to determine the start and end positions of a frame; a header determination functional unit that disassembles the received packets and determines header data indicating whether the header is a data vector or a control vector based on the disassembly results; a buffer functional unit that buffers the packets to which the control symbols have been assigned and the header data and sends the buffered data; and a header assignment functional unit that receives the buffered data sent from the buffer functional unit and assigns a header determined by the header determination functional unit to the packets to which the control symbols have been assigned, wherein the control symbol assignment functional unit, the header determination functional unit, and the buffer functional unit perform sequential processing while the header assignment functional unit performs parallel processing, thereby encoding the received packets.

[0006] One aspect of the present invention is an encoding method for an information processing device, in which a control symbol assignment function unit assigns a control symbol, which is information about a frame, to a received packet, a header determination function unit disassembles the received packet and determines header data indicating whether it is a data vector or a control vector based on the disassembly results, a buffer function unit buffers the packet to which the control symbol has been assigned and the header data and sends the buffered data, a header assignment function unit receives the buffered data sent from the buffer function unit and assigns a header determined by the header determination function unit to the packet to which the control symbol has been assigned, and the control symbol assignment function unit, the header determination function unit, and the buffer function unit perform sequential processing while the header assignment function unit performs parallel processing, thereby encoding the received packet.

[0007] One aspect of the present invention is a program that causes a computer to function as the information processing device described above.

[0008] The present invention enables high-speed encoding processing.

[0009] Fig. 1 is a diagram illustrating an example of the configuration of an information processing device according to an embodiment; Fig. 2 is a diagram illustrating an outline of an example of the hardware configuration of an information processing device applied to an embodiment; Fig. 3 is a diagram illustrating an example of the configuration of an encoding unit according to an embodiment and an example of processing performed in encoding; Fig. 4 is a diagram illustrating an example of processing when the processing of an embodiment is applied to 64b / 66b encoding; Fig. 5 is a diagram illustrating the relationship between input data and generated data with a 2-bit header added in 64b / 66b encoding, and the behavior of parallel execution of bit shifts.

[0010] An embodiment of the present invention will be described in detail with reference to the drawings. Fig. 1 is a diagram showing an example of the configuration of an information processing device according to this embodiment. As shown in Fig. 1, the information processing device 1 includes, for example, a receiving unit 11, a processing unit 12, and a transmitting unit 15. The processing unit 12 includes, for example, an encoding unit 13 and a preamble adding unit 14.

[0011] The information processing device 1 is, for example, a server, a computer, etc. The information processing device 1 receives, for example, a first protocol signal from a transmitting device 2 via a network 4. The information processing device 1 also transmits, for example, a second protocol signal to a receiving device 3 via the network 4. The transmitting device 2 and the receiving device 3 are devices configured using information devices such as smartphones, tablets, personal computers, and dedicated devices. The network 4 may be a network using wireless communication or a network using wired communication. The network 4 may be configured using, for example, the Internet or a local area network (LAN). The network 4 may be configured by combining multiple networks.

[0012] The receiving unit 11 is, for example, an interface card, and receives a first protocol signal.

[0013] The processing unit 12 is composed of a processor such as a CPU (Central Processing Unit) and software. The processor executes the software to perform processing such as encoding. The processing unit 12 functions as an encoding unit 13 and a preamble adding unit 14 when the processor executes the software. A preamble is a synchronization signal added to packet data. The encoding unit 13 encodes the first protocol signal received by the receiving unit 11. The preamble adding unit 14 adds a preamble to the encoded signal and converts it to a second protocol. The software may be stored in a storage unit or may be executed on a cloud. The processing unit 12 may also include an internal storage unit or may be connected to an external storage unit.

[0014] The transmitter 15 is, for example, an interface card, and outputs a second protocol signal.

[0015] Note that all or part of the functions of the processing unit 12 may be realized using hardware such as an ASIC (Application Specific Integrated Circuit), a PLD (Programmable Logic Device), or an FPGA (Field Programmable Gate Array). The above program may be recorded on a computer-readable recording medium. Examples of computer-readable recording media include portable media such as flexible disks, magneto-optical disks, ROMs, CD-ROMs, and semiconductor storage devices (e.g., SSDs: Solid State Drives), as well as storage devices such as hard disks and semiconductor storage devices built into computer systems. The above program may be transmitted via a telecommunications line.

[0016] FIG. 2 is a diagram illustrating an example of the hardware configuration of an information processing device applied to this embodiment. As illustrated in FIG. 2 , the information processing device 1 includes, for example, a processor 101, a main memory device 102, a communication interface 103, an auxiliary memory device 104, an input / output interface 105, and an internal bus 106. The processor 101, the main memory device 102, the communication interface 103, the auxiliary memory device 104, and the input / output interface 105 are communicably connected to each other via the internal bus 106. The information processing device 1 may be applied to, for example, a transmitting device 2 and a receiving device 3. Furthermore, for example, the receiving unit 11 and the transmitting unit 15 may be configured using the communication interface 103 or the input / output interface 105. For example, the processing unit 12 may be configured using the processor 101, the main memory device 102, and the auxiliary memory device 104.

[0017] Next, a configuration example of the encoder 13 and an example of the processing performed in the encoding will be described. Fig. 3 is a diagram showing a configuration example of the encoder of this embodiment and an example of the processing performed in the encoding. As shown in Fig. 3, the encoder 13 includes, for example, a control symbol assigning function unit 131, a header determining function unit 132, a buffer function unit 133, and a header assigning function unit 134.

[0018] The receiving unit 11 receives a packet of the first protocol and outputs the received packet to the processing unit 12 (step S1).

[0019] The control symbol assigning function unit 131 assigns control symbols to the received packet to obtain the start and end positions of the frame (step S2). The control symbols are information about the frame, such as data indicating the start position of the packet, data indicating the end position of the packet, data indicating that the packet is error data, etc.

[0020] The header determination function unit 132 decomposes the received packet and determines the header indicating whether it is a data vector or a control vector based on the result of the decomposition (step S3).

[0021] The buffer function unit 133 buffers the packets with the control symbols added and the header data, and sends the packets with the control symbols added and the header data to the header adding function unit 134, which performs parallel processing (step S4).

[0022] The header adding function unit 134 adds the determined header to the packet data to which the control symbol has been added (step S5).

[0023] In this embodiment, control symbols are assigned to received packets and header determination is performed, and the packets with the control symbols assigned and the header data are buffered in a sequential process (g10). That is, the control symbol assignment function unit 131, the header determination function unit 132, and the buffer function unit 133 perform sequential processes. In parallel with the above process, the header assignment function unit 134 assigns headers in parallel based on the generated header data (g12).

[0024] In the conventional technology, a control symbol is added to a received packet to determine the start and end positions of the frame, and the received packet is decomposed and a header indicating whether it is a data vector or a control vector is determined based on the decomposition result. Then, in the conventional technology, a header is added based on the determined result. In the conventional technology, all of these processes are performed sequentially.

[0025] In contrast to this, in this embodiment, a part of the serial processing (for example, header addition) that was performed in the conventional technology is performed in parallel, thereby realizing high-speed software implementation. In other words, according to this embodiment, encoding can be performed at a higher speed than in the conventional technology.

[0026] The coding can be applied to block coding such as 64b / 66b coding.

[0027] <Example> Next, a processing example when the processing of this embodiment is applied to 64b / 66b encoding will be described with reference to Fig. 4 and Fig. 5. Fig. 4 is a diagram showing a processing example when the processing of this embodiment is applied to 64b / 66b encoding. Fig. 5 is a diagram showing the relationship between input data and generated data with a 2-bit header added in 64b / 66b encoding, and the behavior of parallel execution of bit shifts.

[0028] The receiving unit 11 receives a packet of the first protocol and outputs the received packet to the processing unit 12 (step S21).

[0029] The control symbol assigning function unit 131 assigns control symbols to the received packet to obtain the start and end positions of the frame (step S22, g40 in FIG. 5). Note that in FIG. 5, S" in symbol g41 is a control symbol indicating the start position of the packet, and "T" in symbol g42 is a control symbol indicating the end position of the packet (see Non-Patent Document 1).

[0030] The header determination function unit 132 decomposes the received packet and determines the 2-bit header data (g30 in FIG. 5) indicating whether the packet is a data vector or a control vector based on the decomposition result (step S23). The 2-bit header data is, for example, "10."

[0031] The buffer function unit 133 buffers the packets with the control symbols and the header data, and passes the data to parallel processing after buffering a certain amount of data or a predetermined time (step S24). Note that the predetermined time is a time set in advance by a designer through simulation, for example.

[0032] The header adding function unit 134 adds the determined 2-bit header to the packet to which the control symbol has been added (step S5, g50 in FIG. 5).

[0033] In this way, in this embodiment, packets with control symbols added and header data are buffered and then transferred to parallel processing units, which makes it possible to achieve parallel 2-bit header addition, unlike conventional techniques. As a result, this embodiment also enables faster processing than conventional techniques.

[0034] In an information processing device configured in this manner, packets with control symbols and header data are buffered and passed to parallel processing units, thereby enabling parallel header assignment, thereby enabling faster processing than before.

[0035] (Modification) In the embodiment, 64b / 66b coding has been used as an example of coding, but the coding is not limited to this and may be other block coding.

[0036] In the embodiment, the example has been described in which, during 64b / 66b encoding, packets with control symbols and header data are buffered, and the data is passed to parallel processing after buffering a certain amount or a predetermined time, but this is not limiting. The buffer function unit 133 may also pass data to parallel processing after buffering a certain amount or a predetermined time during other encoding.

[0037] Although an embodiment of the present invention has been described above in detail with reference to the drawings, the specific configuration is not limited to this embodiment, and includes designs within the scope of the gist of the present invention.

[0038] The present invention is applicable to information processing devices, encoding devices, signal processing devices, servers, and the like.

[0039] 1...information processing device, 11...receiving unit, 12...processing unit, 13...encoding unit, 14...preamble adding unit, 15...transmitting unit, 131...control symbol adding function unit, 132...header determining function unit, 133...buffer function unit, 134...header adding function unit, 101...processor, 102...main memory device, 103...communication interface, 104...auxiliary memory device, 105...input / output interface, 106...internal bus

Claims

1. An information processing device comprising: a control symbol assignment function unit that assigns control symbols, which are information about frames, to received packets; a header determination function unit that disassembles the received packets and determines header data indicating whether they are data vectors or control vectors based on the disassembly results; a buffer function unit that buffers the packets to which the control symbols have been assigned and the header data and sends the buffered data; and a header assignment function unit that receives the buffered data sent from the buffer function unit and assigns headers determined by the header determination function unit to the packets to which the control symbols have been assigned, wherein the control symbol assignment function unit, the header determination function unit, and the buffer function unit perform sequential processing while the header assignment function unit performs parallel processing, thereby encoding the received packets.

2. The information processing device according to claim 1, wherein the buffer function unit buffers the packet to which the control symbol is added and a certain amount of the header data, and then sends the buffered data to the header addition function unit.

3. The information processing device according to claim 1, wherein the buffer function unit buffers the packet to which the control symbol is added and the header data for a predetermined time, and then sends the buffered data to the header adding function unit.

4. An encoding method for an information processing device, in which a control symbol assignment function unit assigns a control symbol, which is information about a frame, to a received packet; a header determination function unit disassembles the received packet and determines header data indicating whether it is a data vector or a control vector based on the disassembly results; a buffer function unit buffers the packet to which the control symbol has been assigned and the header data, and sends the buffered data; a header assignment function unit receives the buffered data sent from the buffer function unit and assigns a header determined by the header determination function unit to the packet to which the control symbol has been assigned; and an encoding method in which the header assignment function unit performs parallel processing while the control symbol assignment function unit, the header determination function unit, and the buffer function unit perform sequential processing, thereby encoding the received packet.

5. A program that causes a computer to function as the information processing device according to claim 4.

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