Quantum bit array, quantum information processing device, and quantum bit readout method

Abstract

A quantum bit array according to the present invention comprises: a first gate electrode; a second gate electrode; a first barrier gate electrode and a second barrier gate electrode which are adjacent to the second gate electrode; a third barrier gate electrode which is adjacent to the first gate electrode; a semiconductor layer; and a charge sensor which reads out, as an output current, the number of electrons stored in the semiconductor layer below the second gate electrode. The quantum bit array reads, with the charge sensor, an output current that reflects the state of electrons in the semiconductor layer below the second gate electrode when movement of electrons stored in the semiconductor layer below the first gate electrode and the second gate electrode is controlled between the first gate electrode and the second gate electrode, and reads the spin state of electrons stored in the semiconductor layer below the first gate electrode on the basis of the output current.

Description

Quantum bit array, quantum information processing device, and quantum bit readout method

[0001] The present disclosure relates to a quantum bit array, a quantum information processing device, and a quantum bit readout method.

[0002] There is great interest in building quantum computers that can perform at high speeds and in a cost-effective manner. Quantum computers use superconducting logic-based devices, which are typically cooled to cryogenic temperatures to function in a superconducting state. Patent Document 1 (JP 2021-523572 A) discloses a system including at least two sets of superconducting logic devices, a cooling apparatus adapted to cool the logic devices to a first operating temperature, and an interconnect that couples the superconducting logic devices.

[0003] Special table 2021-523572 publication Special table 2019-537239 publication

[0004] Stephan GJ Philips, “Universal control of a six-qubit quantum processor in silicon”, Nature volume 609, pp.919-924 (2022)

[0005] Previously, quantum semiconductors have demonstrated quantum operation on the order of 1 to 100 qubits in an absolute zero atmosphere achieved using dilution refrigerators and other devices. However, systems with a medium number of qubits do not provide sufficient computational resources for analyzing complex phenomena. On the other hand, to secure sufficient computational resources by further increasing the number of qubits, it is important to highly integrate the semiconductor elements that make up the qubits. To achieve this, it is desirable to construct qubit elements using advanced micro-semiconductor processes. However, fabricating semiconductor elements using micro-processes is extremely difficult, and the layout dimensions of semiconductor elements that can be fabricated are sometimes limited by the performance of the exposure equipment.

[0006] Patent Document 2 (JP 2019-537239 A) and Non-Patent Document 1 disclose two-qubit and six-qubit device structures fabricated using advanced microsemiconductor processes. In the method disclosed in Patent Document 2, electron supply points called reservoirs are provided at both ends of two qubits, and the spin information of the qubits can be determined using the Elsermann readout method. On the other hand, in the six-qubit structure disclosed in Non-Patent Document 1, there are only two charge meters for reading out spin information for six qubits. Therefore, one charge meter corresponds to three qubits, and considering the Pauli exclusion principle, it is difficult to individually determine all the spin information of three qubits. In other words, there is a problem that the effective number of qubits is significantly reduced.

[0007] In view of the above background, when there are three or more quantum dots to be read out in one charge meter SET, if electrons are stored in all of the quantum dots, it becomes difficult to distinguish the spin states of the three electrons (read out the quantum bit states) in one charge meter SET. The present invention has been made to solve the above problem. That is, one object of the present disclosure is to provide a quantum bit array, a quantum information processing device, and a quantum bit reading method that can read out the spin states of multiple electrons stored in a quantum bit row with high accuracy.

[0008] In order to solve the above problems, the quantum bit array of the present disclosure is a quantum bit array including a first gate electrode, a second gate electrode, a semiconductor layer, and a charge sensor that reads the number of electrons stored in the semiconductor layer below the second gate electrode as an output current, wherein the output current reflects the state of the electrons in the semiconductor layer below the second gate electrode when movement of electrons stored in the semiconductor layer below the first gate electrode and the second gate electrode is controlled between the first gate electrode and the second gate electrode, and the quantum bit array reads the spin state of the electrons stored in the semiconductor layer below the first gate electrode based on the output current.

[0009] The quantum information processing device of the present disclosure is a quantum information processing device including a quantum bit array and a control device that controls the quantum bit array, wherein the quantum bit array includes a first gate electrode, a second gate electrode, a semiconductor layer, and a charge sensor that reads the number of electrons stored in the semiconductor layer below the second gate electrode as an output current, and the output current reflects the state of the electrons in the semiconductor layer below the second gate electrode when movement of electrons stored in the semiconductor layer below the first gate electrode and the second gate electrode is controlled between the first gate electrode and the second gate electrode, and the spin state of the electrons stored in the semiconductor layer below the first gate electrode is read by the charge sensor, and based on the output current,

[0010] The quantum bit reading method disclosed herein is a quantum bit reading method using a quantum bit array including a first gate electrode, a second gate electrode, a semiconductor layer, and a charge sensor that reads the number of electrons stored in the semiconductor layer below the second gate electrode as an output current, wherein the output current reflects the state of the electrons in the semiconductor layer below the second gate electrode when movement of electrons stored in the semiconductor layer below the first gate electrode and the second gate electrode is controlled between the first gate electrode and the second gate electrode, and the spin state of the electrons stored in the semiconductor layer below the first gate electrode is read based on the output current.

[0011] According to the present disclosure, it is possible to read out the spin states of multiple electrons stored in a quantum bit row with high accuracy. Note that the effects described herein are not necessarily limited to those described herein, and may be any of the effects described in the present disclosure.

[0012] FIG. 1 is a quantum computer operation flow diagram according to an embodiment. FIG. 2A is a wiring diagram of a quantum bit array group according to an embodiment. FIG. 2B is a wiring structure diagram of a quantum bit array according to an embodiment. FIG. 2C is a wiring structure diagram of a quantum bit array according to an embodiment. FIG. 2D is a wiring structure diagram of a quantum bit array according to an embodiment. FIG. 2E is a wiring structure diagram of a quantum bit array according to an embodiment. FIG. 3 is a layout diagram of a quantum bit array group according to an embodiment. FIG. 4 is a first step diagram of readout method 1 according to an embodiment. FIG. 5 is a second step diagram of readout method 1 according to an embodiment. FIG. 6A is a third step diagram of readout method 1 according to an embodiment. FIG. 6B is a diagram for explaining a modified example of readout method 1 according to an embodiment. FIG. 7 is a wiring diagram of a quantum bit array group according to an embodiment. FIG. 8 is a first step diagram of readout method 2 according to an embodiment. FIG. 9 is a second step diagram of readout method 2 according to an embodiment. FIG. 10 is a third step diagram of readout method 2 according to an embodiment. FIG. 11 is a wiring diagram of a quantum bit array unit according to an embodiment. FIG. 12 is a block diagram of a comparison circuit and a voltage conversion detection circuit according to an embodiment. 13 is a block diagram of a quantum computer according to an embodiment. FIG. 14 is a diagram of a quantum computer according to an embodiment.

[0013] In the following embodiments, when necessary for convenience, the description will be divided into multiple sections or embodiments, but unless otherwise specified, they are not unrelated to each other, and one is a partial or complete modification, detail, supplementary explanation, etc. of the other. Furthermore, in the following embodiments, when the number of elements, etc. (including the number, numerical value, amount, range, etc.) is mentioned, it is not limited to that specific number, and may be more or less than the number of characteristics, unless otherwise specified or when it is clearly limited to a specific number in principle.

[0014] Furthermore, in the following embodiments, it goes without saying that the components (including element steps, etc.) are not necessarily essential unless otherwise specified or considered to be clearly essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of components, etc., it is intended to include those that are substantially similar or similar to the shape, etc., unless otherwise specified or considered to be clearly not essential in principle. The same applies to the above numerical values ​​and ranges.

[0015] When describing elements of the same type without distinguishing between them, the common portion (the portion excluding the branch number) of the reference symbol including the branch number may be used. When describing elements of the same type while distinguishing between them, the reference symbol including the branch number may be used. For example, taking the quantum bit transistor wiring shown in FIG. 2 as an example, when describing individual quantum bit transistor wirings without distinguishing between them, they may be referred to as "quantum bit transistor wiring PG." When describing individual quantum bit transistor wirings while distinguishing between them, they may be referred to as "quantum bit transistor wiring PG0," "quantum bit transistor wiring PG1," etc. In addition, in the following description, components may be described using only reference symbols. For example, "barrier gate BG0" may be referred to as "BG0." <<Example 1>> A quantum semiconductor (quantum bit array) readout method, its circuit configuration, and element structure according to this embodiment will be described using FIGS. 1 to 14.

[0016] Figure 1 shows the quantum system flow (state transition diagram) of this embodiment. The numbers used in the explanation (e.g., (1)) refer to the numbers attached to the states in Figure 1. First, the dilution refrigerator and measuring device (1) that have been opened in the system are powered on (2), and the soundness of the connections between the devices is confirmed (3). If a connection failure is determined due to a measuring device malfunction (4), the relevant device is identified, the problem is resolved, and then the power is turned on again (2). If there are no problems with the system hardware or software, the qubit chip is initialized (5). Initialization is performed by checking the current-voltage characteristics of the qubit, such as the Coulomb diamond pattern and charge stability diagram, as well as the Larmor frequency and Rabi oscillation frequency. If the expected characteristic value (specified value) of the installed qubit is exceeded, the bit is determined to be defective (6). The specified values ​​for all bits are checked, and if the defect rate is within the specified value, the system transitions to the idle monitor status (7). If it is outside the specified value, initialization is performed again. If the quantum bit failure rate exceeds a specified value after multiple initializations, the quantum bit chip is considered to have a major failure and measures such as chip replacement are taken (4). After completing initialization, a good quantum bit chip transitions to an idle state (7) and then accepts quantum computation requests (8) and (9) from the user. Upon receiving a request, the chip automatically transitions to the quantum computation status (7), executes the computation (10), and returns the results to the user's GUI (9). The period during which quantum computations can be accepted is set at approximately five hours (assuming half of 10 hours, given that calibration every few hours is essential). After five hours, calibration is performed to check whether the control voltage or high-frequency signal for quantum operations exceeds the specified values ​​(11). Calibration is completed within approximately five minutes, after which the chip returns to the quantum computation status (10). If the quantum bit current-voltage characteristics exceed the specified value during this calibration and are determined to be defective, the chip is treated as having a major failure, quantum computation operation is suspended, and the sequence from system startup to initialization is repeated. This is the assumed general quantum system flow. For example, when a quantum system such as the one described above is constructed, the quantum computation amount varies greatly depending on the number of physical quantum bits that can be prepared.The more quantum bits that are quantum-coupled, the greater the amount of calculation required. However, even in the case of multiple bits, the ability to accurately read the spin state of each individual quantum bit is a minimum requirement that must be met for a computer system.

[0017] Figure 2A shows a wiring diagram of a quantum bit array group according to this embodiment. Figures 2B, 2C, 2D, and 2E show examples of wiring structure diagrams for forming quantum bit array groups. Symbols in the figure represent a diffusion layer OD, which is a transistor active layer, a polysilicon wiring layer PO, a contact layer LCNT electrically connecting the diffusion layer OD and the metal wiring layer M0, a contact layer MP electrically connecting the polysilicon wiring layer PO and the metal wiring layer M0, a metal wiring layer M0, a metal wiring layer M1, a via layer V10 electrically connecting the metal wiring layer M0 and the metal wiring layer M1, a metal wiring layer M2, a via layer V21 electrically connecting the metal wiring layer M1 and the metal wiring layer M2, a metal wiring layer M3, and a via layer V32 electrically connecting the metal wiring layer M2 and the metal wiring layer M3. Note that reference symbols BG0-BG16, PG0-PG7, and DPG0-DPG7 indicating each gate (gate electrode) are written at positions corresponding to the gates of the transistor symbols in Figure 2A (the same applies to Figures 7 and 11). In the example of Figure 2B, it is recommended to lay out the wiring layers in a crossing direction from the lower layer to the upper layer. This has the advantage of reducing defects caused by incorrectly connecting wiring layers. On the other hand, if the wiring structure is complex, it goes without saying that, for example, metal wiring layers M1 and M2 may be arranged in the same direction. Figures 2D and 2E show an example in which metal wiring layers M1, M2, and M3 are arranged in the same direction. Regarding metal wiring layer M2, an example is shown in which wiring can be laid out in the same direction as metal wiring layer M0 to electrically connect with the underlying metal wiring layer M1 and to change its connection position. This allows for a wiring layout with the desired pitch even when the wiring structure is complex due to the large number of control wirings. The wiring diagram in Figure 2A is based on the wiring structure of Figures 2D and 2E.

[0018] The quantum bit array shown in Figure 2A consists of four series-connected rows: quantum bit row L1 (including BG, PG, and DPG), charge meter row L2 (including charge meter SET and charge barrier gate SEB), and two dummy transistor rows L3. The dummy transistors in dummy transistor row L3 in Figure 2A are used to prevent the shapes of quantum bit row L1 and charge meter row L2 from being distorted during the lithography process in semiconductor LSI fabrication. As shown in the figure, two dummy transistor rows L3 (the hatched transistor rows in Figure 2A) are arranged at both ends, and quantum bit row L1 and charge meter row L2 are arranged in the two central rows. A reservoir voltage RESW (e.g., 1 mV) is supplied to quantum bit row L1 from the left edge of the figure, and a source voltage RESE (0 mV) is supplied to the right edge. The quantum bit row L1 has a basic structure consisting of three units: quantum bit storage gates PG for storing quantum bits (Qbits), flanked by barrier gates BG for controlling the electrons stored in the storage gates PG. In this embodiment, a readout gate DPG is provided for every other storage gate PG to intentionally store electrons in the down spin state. That is, the configuration is BG0-PG0-BG1-DPG0-BG2-PG1-BG3. As will be described later, down spin electrons are intentionally stored in the DPG, quantum operations are performed between the DPG and the spin of the storage gate PG, and the results are read out by a charge meter SET located opposite the readout gate DPG (Rbit) to determine the spin state of the electrons in the storage gate PG. In the example of Figure 2A, there are eight quantum bits, Qbit00 to Qbit07.

[0019] The charge meter row L2 is connected to the ground level potential VSSA from the left and right edges of the drawing. A charge meter unit consists of three transistors: a charge meter SET and charge meter barrier gates SEB arranged on either side. These charge meter units are logically connected in the row direction, but are electrically isolated from each other by the placement of isolation transistors DGT. Each charge meter unit has a charge meter drain SD and a charge meter source SS connected to the diffusion layer node of the charge meter barrier transistor. When the charge meter SET and quantum bit unit are laid out so that the charge meter SET and readout gate DPG are directly opposite each other, the distance to the readout gate is shortest, making it ideal for detecting differences in the state of the quantum bit stored in the readout gate.

[0020] Figure 3 shows an enlarged planar layout of a portion of the quantum bit group. The wiring layers are, from the base, a diffusion layer OD, a polysilicon wiring layer PO, a contact layer LCNT that electrically connects the diffusion layer OD and the metal wiring layer M0, a contact layer MP that electrically connects the polysilicon wiring layer PO and the metal wiring layer M0, a metal wiring layer M0, a metal wiring layer M1, a via layer V10 that electrically connects M0 and M1, a metal wiring layer M2, a via layer V21 that electrically connects the metal wiring layer M1 and the metal wiring layer M2, a metal wiring layer M3, and a via layer V32 that electrically connects the metal wiring layer M2 and the metal wiring layer M3.

[0021] The quantum bit Qbit00 is located at the intersection of the storage gate PG0 and the diffusion layer OD of the quantum bit row. A potential difference of approximately 1 mV is applied between the reservoirs RESW and RESE, and a desired voltage is applied to the gate electrodes of the barrier gates BG0 and BG1 on either side of the storage gate PG0 to store one electron at the Qbit00 position. Voltages and currents are applied to the polysilicon wiring layer PO that constitutes the storage gate PG, barrier gate BG0, and barrier gate BG1 through the metal wiring layer M1, via layer V10, metal wiring layer M0, and contact layer MP. To avoid cluttering the drawing, some of the metal wiring layers in the quantum bit Qbit00 and readout bit Rbit00 regions are omitted. However, the wiring structure near the quantum bit Qbit00 and readout bit Rbit00 has the same connection relationship as the wiring structure near the quantum bits Qbit01 and Rbit00.

[0022] The barrier gate BG and readout gate DPG have a hierarchical wiring layout structure utilizing metal wiring layer M1. The storage gate PG has a hierarchical wiring layout structure utilizing metal wiring layer M2. By using metal wiring layers M1 and M2 that pass above and parallel to the polysilicon wiring layer PO to form multilayer wiring for control gate signals, it has the advantage of easily realizing the connection relationships of a so-called NISQ quantum computer in which groups of quantum bit arrays are laid out in parallel in multiple columns. Note that Figure 3 shows a cut polysilicon mask layer CPO for physically cutting the polysilicon wiring layer PO of the charge meter unit and the polysilicon wiring layer PO of the storage gate PG.

[0023] Next, we will explain the layout of the charge meter. Charge meter SET00 is located at the intersection of the polysilicon wiring layer PO and the diffusion layer OD of the SET row. Charge meter barrier gates SEB000 and SEB001 are located on either side of charge meter SET00. The charge meter barrier gates are arranged to selectively pass the charge meter SET readout current to the adjacent charge meter drain SD and charge meter source SS. Charge meter SET00 detects whether one or two electrons are stored in the readout gate Rbit00 as a result of the quantum bit operation, and outputs a readout current reflecting the spin state between the charge meter drain SD and charge meter source SS, which are connected to the outside of the charge meter barrier gates SEB000 and SEB001. To achieve this readout operation, charge meter SETs are arranged opposite each readout bit Rbit in a one-to-one ratio. Charge meter SET00 and charge meter SET01 are constructed using separate control wiring in the polysilicon wiring layer PO, allowing selective operation of the charge meter. Because the polysilicon wiring layer PO, which is the control wiring layer for the charge meter SET, is laid out individually, the charge meter drain SD and charge meter source SS, which are the output current paths, are shared and connected in each charge meter SET using the metal wiring layer M0, contact layer MP, diffusion layer OD, and contact layer LCNT. Connecting in this manner reduces the number of wiring layers and allows the wiring to pass over the dummy row. In other words, since there is no need to pass the charge meter drain SD or charge meter source SS wiring between the charge meter SET and the quantum bit Qbit, there is an advantage in that the physical distance between the quantum bit and the charge meter can be placed close enough for quantum operation.

[0024] To avoid cluttering the drawing, some of the metal wiring layers near the charge meter SET00, charge meter barrier gate SEB000, and charge meter SEB001 are omitted, but the connections are the same as those near the charge meter SET01, charge meter barrier gate SEB002, and charge meter barrier gate SEB003. Charge meter SET01 has a hierarchical wiring layout structure utilizing metal wiring layer M2. Charge meter barrier gate SEB002 and charge meter barrier gate SEB003 have a hierarchical wiring layout structure utilizing metal wiring layer M3. The hierarchical wiring for the storage gate PG and barrier gate BG utilizes metal wiring layers M1 and M2, while the charge meter SET and charge meter barrier gate SEB utilizes metal wiring layers M2 and M3. This structure allows the layout of each gate element (PG, BG, SET, SEB, DPG) at a distance that allows appropriate quantum operations between adjacent quantum bits without making the pitch of each wiring layer unnecessarily wide. In the drawing, inactive means that a VSSA potential, for example, 0V, is supplied to the polysilicon wiring layer PO, and VSSA is written near the corresponding polysilicon wiring layer PO.

[0025] The spin readout method of this embodiment will be described using Figures 4 to 6B. In the example of Figure 4, the storage gates PG0, PG1, PG2, and PG3 store no qubits, down spin qubits, up spin qubits, and both up spin and down spin qubits, respectively. In this embodiment, the readout bit Rbit and charge meter SET are each used individually to output a readout current. As mentioned above, this is because the charge meter drain SD and charge meter source SS are electrically connected as the final output node using the metal wiring layer M0 common to the qubit row. Despite this premise, for simplicity's sake, Figures 4 to 6B will describe a series of steps assuming that the spin states of these four qubits are read out simultaneously.

[0026] In the initial state, for example, 1.05 V is applied to the barrier gate BG, and 1.545 V is applied to the storage gate PG and readout gate DPG. The spin state of the stored quantum bit is maintained in the semiconductor layer below each transistor element. With this potential relationship, the electron potential distribution assumes a sinusoidal shape, as shown in Figure 4, and the quantum bit is stably stored in its designated position within the coherence time. Although not shown, the charge meter SET and charge meter barrier gate are also applied with desired gate potentials, entering a standby state in which the number of electrons in the opposing readout gate DPG is read as the magnitude of the output current. A potential difference of 1 mV is applied between the source SS and drain SD of each charge meter, so that a certain readout current ISET flows at step 0 in Figure 4. From this standby state, in step 1 of the readout phase, the reference down spin previously stored in the readout gate DPG is transferred to the storage gate PG by tunneling the electron potential.

[0027] This method is shown in Figure 5. To transfer the reference down spins held in the readout gate DPG shown in Figure 4 to the adjacent storage gates PG on the left, the applied voltages of the even-numbered barrier gates BG (excluding the zero-numbered barrier gate) can be reduced by, for example, 10 mV to 1.04 V. In this case, the electron potential of the even-numbered barrier gates rises, transitioning to the state shown by the dashed lines in Figure 5. Controlling in this manner also causes the electron potential of each readout gate DPG to rise slightly due to the influence of the potential of the adjacent barrier gate to the left. The degree of this slight rise is controlled to, for example, about 100 μV. In the case of silicon quantum bits, the level difference between the up spins and the down spins is Zeeman-separated by applying a static magnetic field. In a 100 mK environment, the difference is approximately 80 μV. Therefore, by controlling the potential rise to a similar level, approximately 100 μV, the reference down spins in each readout gate DPG will be transferred to each storage gate PG via the odd-numbered barrier gates. At this time, due to the Pauli exclusion principle, the reference down spin cannot move to storage gates PG1 and PG3, where down spins are originally stored. As a result, the reference down spins remain in readout gates DPG1 and DPG3. On the other hand, the reference down spins stored in the even-numbered readout gates DPG0 and DPG2 are moved because no down spins are stored in the destination storage gates PG0 and PG2. Therefore, the readout current ISET in the step 1 phase increases in STEP 1 for charge meters SET01 and SET03 (a decrease of 1 charged particle), while the current remains unchanged in STEP 1 for charge meters SET02 and SET04 (no increase or decrease in charged particles: 0), as shown in Figure 5.

[0028] Next, step 2 of FIG. 6A will be described. The same control as in FIG. 5 is performed. In step 2, the corresponding storage gate PG is set to, for example, 1.535 V, a shallower voltage of about 10 mV. This control slightly increases the electron potential of the storage gate, resulting in a potential distribution that facilitates transfer to the adjacent readout gate DPG via the odd-numbered barrier gates. As a result, unlike FIG. 5, the spins in each storage gate PG0, PG1, PG2, and PG3 transfer to the adjacent readout gates DPG0, DPG1, DPG2, and DPG3 on the right. Here, if down spins are stored in the readout gate DPG due to the Pauli exclusion principle, as in FIG. 5, the down spins in the storage gate cannot transfer to the readout gate and remain in the storage gate PG. In the example of FIG. 6A, down spins remain in storage gates PG1 and PG3. As a result, the increase or decrease in the number of electrons stored in the readout gate DPG in step 1 and step 2 is as shown in FIG. 6A : readout gate DPG0 stores one electron in each step, readout gate DPG1 stores zero electrons in each step, readout gate DPG2 stores one electron in step 1 and two electrons in step 2, and readout gate DPG3 stores zero electrons in step 1 and one electron in step 2. By outputting the readout current of the charge meter SET in three steps in this way, a unique readout current pattern corresponding to the spin state can be generated. By interpreting this unique readout current pattern, it can be determined whether the spins secured in the storage gates PG0, PG1, PG2, and PG3 are no qubits, down spin, up spin, or both up spin and down spin.

[0029] FIG. 6B shows an example in which the reference down spin is transferred only between the read gate DPG1 and the storage gate PG1. The gate potentials of the barrier gates other than the barrier gate BG3 are transitioned to 1.04 V, raising the electron potentials other than the storage gate PG1 and the read gate DPG1. This facilitates the transfer of electrons stored in the read gate DPG1 to the storage gate PG1 via the adjacent barrier gate BG3. Note that in this example, since down spins are stored in the storage gate PG1, the reference down spins in the read gate DPG1 do not transfer. Next, as in FIG. 6A, the gate potential of the storage gate PG1 is transitioned to 1.535 V, making it easier for electrons stored in the storage gate PG1 to transfer to the read gate DPG1. Controlling in this manner results in the same number of electrons entering and leaving the read gate DPG1 in FIGS. 4, 5, and 6A and the read gate DPG1 shown in FIG. 6B. In other words, the stored spin state can be detected only at the corresponding storage gate address. In addition, since the electron count increase or decrease in each storage gate other than the storage gate PG1 and the readout gate DPG1 is zero, no change occurs in the readout gate current at each step. Therefore, the address to which the desired gate potential is applied is stored, the quantum bit to be read is selected, and the quantum bit state at the corresponding address is detected. <<Example 2>> Figure 7 is a wiring diagram of a quantum bit array group according to a second example (Example 2). The difference from Figure 2 is that no reference spin bit is stored in the semiconductor layer below the readout gate DPG. The remaining wiring configuration from the base to the top is the same as that in Figure 2, and therefore will not be described here.

[0030] The spin readout method of this embodiment will be described using Figures 8 to 10. In the example of Figure 8, the storage gates PG0, PG1, PG2, and PG3 store no qubits, down spin, up spin, and both up spin and down spin, respectively. In this embodiment, the readout bit Rbit and charge meter SET are each used individually to output a readout current. As mentioned above, this is because the charge meter drain SD and charge meter source SS are electrically connected as the final output node using the metal wiring layer M0 common to the qubit row. Despite this premise, for simplicity's sake, Figures 8 to 10 will describe a series of steps assuming that the spin states of these four qubits are read out simultaneously.

[0031] In the initial state, for example, 1.05 V is applied to the barrier gate BG, and 1.545 V is applied to the storage gate PG and readout gate DPG. The spin state of the stored quantum bit is maintained in the semiconductor layer below each transistor element. With this potential relationship, the electron potential distribution assumes a sinusoidal shape, as shown in Figure 8, and the quantum bit is stably stored in a predetermined position within the coherence time. Although not shown, the charge meter SET and charge meter barrier gate are also applied with desired gate potentials, entering a standby state in which the number of electrons in the opposing readout gate DPG is read as the magnitude of the output current. A potential difference of 1 mV is applied between the source SS and drain SD of each charge meter, so that a certain readout current ISET flows at step 0 in Figure 8. From this standby state, in step 1 of the readout phase, the quantum bit previously stored in the storage gate PG is moved to the readout gate DPG by tunneling the electron potential.

[0032] This method is shown in Figure 9. To transfer the quantum spins held in the storage gates shown in Figure 8 to the adjacent readout gates DPG on the right, the applied voltage to the even-numbered barrier gates BG can be reduced by, for example, 10 mV to 1.04 V. In this case, the electron potential of the even-numbered barrier gates rises, transitioning to the state shown by the dashed lines in Figure 9. Controlling in this manner also causes the electron potentials of the storage gates PG0, PG1, PG2, and PG3 to rise slightly due to the influence of the potential of the barrier gates to their left. The degree of this slight rise is controlled to, for example, about 40 μV. In the case of silicon quantum bits, the level difference between up and down spins is Zeeman-separated by applying a static magnetic field. In a 100 mK environment, the difference is approximately 80 μV. Therefore, by controlling the potential rise to about half that amount, approximately 40 μV, only the up spins in each storage gate can be transferred to each readout gate DPG via the odd-numbered barrier gates while maintaining their spin state. In the example of Figure 9, the up spins stored in PG2 and the up spins stored in PG3 are moved to DPG. One electron is added to the read gate DPG, so the read currents of the charge meters SET03 and SET04 change. This example shows an increase in electrons and a decrease in the read current. By controlling in this way, the current value changes in step 1 of Figure 9.

[0033] Next, step 2 of FIG. 10 will be described. The same control as in FIG. 9 is performed. Specifically, the even-numbered barrier gates BG are transitioned to a shallower potential, for example, 1.03 V, approximately 10 mV shallower, to increase their electron potential. The same effect can be achieved by transitioning each storage gate potential from 1.545 V to 1.535 V. By performing this control, the down spins secured in the storage gates in step 2 are transferred to the readout gate DPG via the odd-numbered barrier gates while maintaining their spin state. In the example of FIG. 10, the down spins in storage gates PG1 and PG3 are transferred to the readout gate DPG. Therefore, in step 2, the readout currents of charge meters SET02 and SET03 change. By outputting the readout current of charge meter SET in three steps, electrons corresponding to the spin state can be transferred one by one, generating a unique readout current pattern. By reading this unique read current pattern, it is possible to determine whether the spins stored in the storage gates PG0, PG1, PG2, and PG3 are no qubits, down spin, up spin, or both up and down spin.

[0034] As described in Example 1 of FIGS. 4 to 6B, in Example 2, it is also preferable to control the electron potential directly below each gate other than the corresponding storage gate, barrier gate, and readout gate to increase, as shown in FIG. 6B. It goes without saying that the gate potential of storage gate PG1 may also be controlled to slightly deepen the electron potential of PG1. Example 3: FIG. 11 shows a wiring diagram of a multi-qubit array section of this example (Example 3) to which the quantum array group of Example 2 is applied. The quantum array section of FIG. 11 is composed of eight quantum array groups Row#0 to Row#7. Each array group has the same wiring structure and interconnection configuration as the quantum array group described in FIG. 7. It may also be similar to the quantum array group described in FIG. 2. That is, a multi-qubit array section may be configured by applying the quantum array group of Example 1. In the example of FIG. 11, the physical quantum bits are 64 bits, the logical quantum bits are 8 bits, and there are 64 charge meters SET. The optimal layout for the charge meter SET and quantum bit unit is to have the charge meter SET and readout DPG directly facing each other. The same barrier gate BG0 and storage gate PG1 in each quantum bit row are controlled to simultaneously apply voltage and current. To achieve this control, each quantum bit row is electrically connected using multilayer metal wiring. Figure 11 shows only a portion of the wiring layers to avoid clutter. These are the polysilicon wiring layer PO, the diffusion layer OD, the contact layer LCNT, and the metal wiring layers M0 to M3. In the example in Figure 11, the charge meter drain SD and charge meter source SS are routed from the right edge of the figure using M1 wiring, then descend to the lower layer using M0 wiring and distributed to the left and right within the chip row. Once distributed, the control voltage is shared between the source and drain of each charge meter via the diffusion layer wiring. The storage gate PG, barrier gate BG, and readout gate DPG are routed between quantum bit groups using M1 wiring and M2 wiring, and are electrically connected to the gate electrodes of the quantum bit units within each quantum bit group. The charge meter SET and charge meter barrier gate SEB are connected between quantum bit groups using M2 wiring and M3 wiring. By efficiently using multilayer wiring as in this example, it is possible to configure a NISQ quantum bit array with eight one-dimensional eight quantum bits in parallel.Since eight quantum bit arrays can be operated in parallel, the multiple output currents are simultaneously compared and detected. If the comparison and detection result is the majority, the information in the majority is determined as the desired spin information by majority logic. Example 4: Figure 12 illustrates an example of a method for determining the unique current readout pattern described in Figures 4, 5, 6A, and 6B. The left side of the figure illustrates the readout gate DPG, the barrier gate BG, and the opposing charge meter SET and charge meter barrier gate SEB, which are part of the quantum bit array of this embodiment. The unique readout current pattern Iin shown in Figure 6A (Figure 6B) is input to, for example, a transimpedance amplifier TIA via an input resistor Rin (several ohms). This TIA is an inverting amplifier circuit that converts current to voltage with a gain RG. It uses a reference voltage VREF as its input voltage and controls the potential on the input resistor Rin to VREF. This has the advantage that the drain-source potential of the charge meter SET can be set to the desired level by controlling the VREF potential. The readout current Iin is converted to the Vin potential by the TIA. Since the Vin voltage can be formulated as RG * Iin + VREF, the read current can be read as an analog value. This allows for current detection with the accuracy required for the calibration operation described in Figure 1. Even more advantageously, when the read current value is small (on the order of pA) and the gain resistor RG cannot be designed to be too large in the semiconductor process, the Vin voltage may have a small amplitude of a few millivolts. Therefore, voltage-to-voltage conversion can be performed using an operational amplifier (OTA) as shown in Figure 12. In this case, the gain can be designed by the ratio of the gain resistors RA and RB. For example, the input voltage to an ADC that converts analog voltages to digital levels can be amplified to a few tens of millivolts. Since amplification to a few tens of millivolts is sufficient as an input signal to the ADC, the read current value Iin can be digitized and detected by a downstream logic circuit. In other words, the unique read current pattern shown in Figure 6A (Figure 6B) can be detected, allowing the multiple spin states held in the multiple storage gates to be identified without omission. In the example of FIG. 12, an ADC circuit is not used, and a circuit for amplifying the logic circuit voltage to VDD / VSS is connected in the comparator circuit CMP.By appropriately setting the reference level VM, a binary value indicating whether or not an electron is present in the readout gate DPG can be read out. In the quantum bit array structure of this embodiment, it is also possible to process the spin quantum bits and convert them into the number of electrons, then move them one by one to the readout gate for readout. In this case, since it is only necessary to focus on the difference in the number of electrons, the aforementioned unique readout current pattern can be simplified and only two values, large and small, of the current, can be compared. Therefore, it is possible to read out the two values ​​using a comparator and transfer them to the downstream circuit without reading out an analog value. In this case, since a comparison circuit generally has fewer transistors than an ADC, high-speed operation can be expected. In other words, in the quantum system of Figure 1, if the circuit system of the comparison circuit of Figure 12 is used to quickly read out the results of the quantum operation, the results of the quantum operation can be quickly transferred to the user. Note that the readout circuit shown in Figure 12 can be located in an mK atmosphere near the quantum bit, or in a 4K atmosphere as described later in Figure 14. Placing the charge meter SET at mK shortens the physical distance between the charge meter SET and the transimpedance amplifier, which has the advantage of allowing the charge meter SET's output current to be converted to a stable voltage at high speed. On the other hand, if the readout circuit is placed at 4K, the allowable power capacity of the 4K atmosphere is large, on the order of watts, making it possible to increase the number of readout circuits that can be placed. In other words, since the number of readout circuits that can be activated simultaneously can be increased, there is the advantage that the quantum operation results can be transferred to a control device outside the dilution refrigerator.

[0035] 1 to 12, multiple storage quantum bits (Qbits) and readout bits (bits that do not intentionally store electrons) are alternately arranged, so that one charge meter SET can be logically arranged for one quantum bit, and therefore, even when three or more quantum dots are present, the spin states of all quantum bits can be read. In other words, when a large-capacity quantum semiconductor is operated quantumly, a quantum computer with high quantum fidelity can be provided.

[0036] Figure 13 shows the connection relationship between the quantum semiconductor QBA of the present invention, the analog chip CAC that inputs control signals to control the quantum semiconductor QBA, and the digital processing unit CDU that inputs control signals to control the analog chip CAC. The quantum computer QCAL is configured as an entire system by logically and electrically connecting these components. The quantum computer QCAL is sometimes referred to as a "quantum computer" or "quantum information processing unit." The analog chip CAC is preferably configured using a classical computer, i.e., an integrated LSI using the so-called CMOS process. Similarly, the digital processing unit CDU is preferably a processing unit that utilizes semiconductor chips using the CMOS process, just like the analog chip CAC. Simply put, the digital processing unit CDU can be a general-purpose personal computer (PC). It is also possible to incorporate a software module that generates the desired control signals into the PC.

[0037] Figure 14 shows an implementation method using a quantum semiconductor QBA, an analog chip CAC, a digital processing unit CDU, and a dilution refrigerator 10 according to the embodiment. The dilution refrigerator 10 is separated by a frame and a room temperature plate RT-PL to separate the external atmosphere from the internal vacuum atmosphere. The degree of vacuum inside the frame is controlled by using a pump device installed outside the refrigerator 10 to evacuate air through a vacuum tube VC. Temperature control inside the dilution refrigerator 10 is achieved by circulating diluted liquid helium through a pulse tube (PulseTube) shown in Figure 14. Figure 14 shows an example in which two pulse tubes are connected. The diluted liquid helium is obtained by liquefying two helium isotopes, 3He and 4He, and then injecting the 3He phase into the 4He phase to dilute it.

[0038] In the example of the dilution refrigerator 10 shown in Figure 14, multiple metal (mainly oxygen-free copper) plates (50K-PL (set to -223°C), 4K-PL (set to -269°C), PLA, PLB, and mKPL (set to approximately -273°C)) are installed and stored inside the Frame housing of the dilution refrigerator 10. The metal plates PLA and PLB are controlled at temperatures between 4K (-269°C) and mK (approximately -273°C). The temperature is controlled and maintained in thermal equilibrium using temperature control heaters (not shown) installed on each plate (50K-PL, 4K-PL, PLA, PLB, and mKPL) and a temperature controller (not shown) installed outside the dilution refrigerator 10 that controls the power input to the temperature control heaters. In the example shown in Figure 14, diluted liquid helium is circulated from the pulse tube (PulseTube) to the heat sink (Heatsink). This allows the metal plate 4K-PL and the metal plate mKPL, to which the heatsink Heatsink is connected, to be cryogenically cooled via the heatsink through which diluted liquid helium circulates. Therefore, the metal plate 4K-PL and the metal plate mKPL can be maintained at a cryogenic temperature of 10 mK to 100 mK. The heatsink Heatsink can be considered the first cryotube, and the pulse tube PulseTube can be considered the second cryotube. The metal plate mKPL can also be considered the first metal plate, and the metal plate 4K-PL can be considered the second metal plate. The quantum semiconductor QBA is mounted on the first cooling plate FGNDPLT of the quantum semiconductor QBA, which is located below the metal plate mKPL. The cooling plate FGNDPLT is thermally connected to the metal plate mKPL via cooling rods C0 to C3 (even-numbered C0 and C2 are not shown). In other words, the heatsink Heatsink is a cryotube that uses diluted liquid helium to cool the metal body, the cooling plate FGNDPLT. The cooling plate FGNDPLT, which is a metal body, is thermally connected to the metal plate mKPL via cooling rods C0 to C3. In this embodiment, the quantum semiconductor QBA is not mounted directly on the metal plate mKPL but is installed below the metal plate mKPL in order to perform quantum operation while applying a static magnetic field to the quantum semiconductor QBA.Due to space limitations for placing the magnet MAGNET, which generates the static magnetic field, at the bottom layer of the dilution refrigerator 10, the quantum semiconductor QBA is positioned as shown in Figure 14 in the dilution refrigerator 10 configuration example of this embodiment. The electrical signals required for quantum operation of the quantum semiconductor QBA are output from a control unit (CDU) installed outside the dilution refrigerator 10. The control signal among the electrical signals is output via coaxial wiring CXE and CXO, and the power supply voltage and power supply current among the electrical signals are output via DC twisted wiring TWE and TWO. The analog chip that generates the quantum bit control signal, and a portion of this chip, are electrically connected to the quantum semiconductor QBA. By implementing the above-described implementation, quantum operations and a quantum computer as described in Figures 1 to 13 can be realized. <<Modifications>> The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above-described embodiments and can, of course, be modified in various ways without departing from the spirit and scope of the invention.

[0039] The above-described embodiments (examples) have been described in detail to clearly explain the present invention, and are not necessarily limited to those including all of the described configurations. Furthermore, some of the configurations of the embodiments (examples) can be added, deleted, or replaced with other configurations. Furthermore, the above-described examples can be combined with each other without departing from the scope of the present invention.

[0040] The present invention can also have the following configuration: [1] A quantum bit array comprising: a first gate electrode, a second gate electrode, a first barrier gate electrode and a second barrier gate electrode adjacent to the second gate electrode, a third barrier gate electrode adjacent to the first gate electrode, a semiconductor layer, and a charge sensor that reads, as an output current, the number of electrons stored in the semiconductor layer below the second gate electrode, wherein the output current reflects the state of the electrons in the semiconductor layer below the second gate electrode when movement of electrons stored in the semiconductor layer below the first gate electrode and the second gate electrode is controlled between the first gate electrode and the second gate electrode, and the quantum bit array reads, based on the output current, the output current reflecting the state of the electrons in the semiconductor layer below the second gate electrode. [2] The quantum bit array according to [1], comprising: a first step of storing the electrons in the semiconductor layer below the first gate electrode; a second step of storing the electrons in the semiconductor layer below the second gate electrode; a third step of setting the electrons stored below the second gate electrode to a down spin state; a fourth step of applying, to the first barrier gate electrode and the second barrier gate electrode, a voltage that causes the electrons stored below the second gate electrode to tunnel into the semiconductor layer below the first gate electrode; a fifth step of applying, to the third barrier gate electrode and the first barrier gate electrode, a voltage that causes the electrons stored in the semiconductor layer below the first gate electrode to tunnel into the semiconductor layer below the second gate electrode; and a sixth step of reading the output current in the fourth step and the fifth step using the charge sensor to read the spin state of the electrons stored in the semiconductor layer of the first gate electrode.[3] The quantum bit array according to [2], comprising: a first unit composed of the third barrier gate electrode, the first gate electrode, and the first barrier gate electrode for storing and controlling the electrons in the semiconductor layer; and a second unit composed of a first charge sensor barrier gate, the charge sensor, and a second charge sensor barrier gate for reading the state of the electrons, the first charge sensor barrier gate and the second charge sensor barrier gate being arranged adjacent to the charge sensor; a first unit array is formed by connecting a plurality of the first units in series in a one-dimensional row direction; a second unit array is formed by connecting a plurality of the second units in series in a one-dimensional row direction; independent drain voltage supply wiring and source voltage supply wiring are connected to the plurality of second units; the charge sensor and the second gate electrode of the first unit are arranged opposite each other so as to directly face each other; and the first unit and the second unit are arranged opposite each other. [4] The quantum bit array according to [3], wherein a first dummy unit array and a second dummy unit array, each having the same transistor configuration as that of the first unit array and the second unit array, are arranged outside the first unit array and the second unit array, which are arranged opposite each other, and the quantum bit array has a quantum bit array group composed of the first unit array, the second unit array, the first dummy unit array, and the second dummy unit array. [5] The quantum bit array according to [4], wherein a plurality of the quantum bit array groups are arranged in a column direction, the gate electrodes having the same function in a plurality of first units that constitute a plurality of the quantum bit array groups are connected by control metal wiring, and the first step to the fourth step are performed simultaneously in a plurality of the first units and the second units that constitute a plurality of the quantum bit array groups.[6] The quantum bit array according to [4], further comprising a comparison circuit that receives the output current as an input, and a voltage conversion detection circuit, wherein in the fourth step, the comparison circuit compares the magnitude of the output current to determine the spin state, and the voltage conversion detection circuit detects whether the output current has a desired value as a result of quantum operation. [7] The quantum bit array according to [5], further comprising a comparison circuit that receives the output current as an input, and a voltage conversion detection circuit, wherein in the fourth step, the comparison circuit compares the magnitude of the output current to determine the spin state, the voltage conversion detection circuit detects whether the output current has a desired output current value as a result of a quantum operation, the comparison circuit and the voltage conversion detection circuit are connected to each second unit, and the same number of comparison circuits and voltage conversion detection circuits as the number of quantum bit array groups arranged in the column direction operate simultaneously, and the multiple output currents output from the second units in each quantum bit array group are compared and detected simultaneously, and when the result of the comparison and detection is the majority, the majority information is determined to be the desired spin information using majority logic. [8] The quantum bit array according to [2], further comprising a third gate electrode connected to the second barrier gate electrode, wherein when performing two-quantum operations using quantum bits stored in the first gate electrode and the third gate electrode, one of the two quantum bits is moved to the second gate electrode while maintaining its spin state, and a desired two-quantum operation operation is performed. Thereafter, the quantum bit that has been subjected to the quantum operation in the second gate electrode is moved to the third gate electrode while maintaining the result of the quantum operation, and then the second step to the fourth step are performed to determine spin information.[9] The quantum bit array according to [1], comprising: a first step of storing the electron in the semiconductor layer below the first gate electrode; a second step of applying, to the first barrier gate electrode and the second barrier gate electrode adjacent to the first gate electrode, a voltage that causes the electron to tunnel into the semiconductor layer below the first barrier gate electrode or the second gate electrode adjacent to the second barrier gate electrode when the electron is of up spin; a third step of applying, to the first barrier gate electrode and the second barrier gate electrode, a voltage that causes the electron to tunnel into the semiconductor layer below the second gate electrode when the electron is of down spin; and a fourth step of reading the output current in the second step and the third step with the charge sensor.

[10] A quantum information processing device comprising the quantum bit array according to any of [1] to [9].

[0041] BG0, BG1, BG3...barrier gates, DPG0, DPG1, DPG2, DPG3...readout gates, L1...qubit row, L2...charge meter row, L3...dummy transistor row, LCNT...contact layer, M0, M1, M2, M3...metal wiring layer, MP...contact layer, OD...diffusion layer, PG0, PG1, PG2, PG3...storage gate, PO...polysilicon wiring layer, Qbit...qubit, SET00, SET01, SET02, SET03, SET04...charge meter

Claims

1. A quantum bit array comprising: a first gate electrode; a second gate electrode; a semiconductor layer; and a charge sensor that reads the number of electrons stored in the semiconductor layer below the second gate electrode as an output current, wherein the output current reflects the state of the electrons in the semiconductor layer below the second gate electrode when movement of electrons stored in the semiconductor layer below the first gate electrode and the second gate electrode is controlled between the first gate electrode and the second gate electrode, and the quantum bit array reads the spin state of the electrons stored in the semiconductor layer below the first gate electrode based on the output current.

2. The quantum bit array according to claim 1, comprising: a first barrier gate electrode disposed between the first gate electrode and the second gate electrode; a second barrier gate electrode adjacent to the second gate electrode; and a third barrier gate electrode adjacent to the first gate electrode, the quantum bit array comprising: a first step of storing the electrons in the semiconductor layer below the first gate electrode; a second step of storing the electrons in the semiconductor layer below the second gate electrode; a third step of putting the electrons stored below the second gate electrode into a down spin state; a fourth step of applying a voltage to the first barrier gate electrode and the second barrier gate electrode to cause the electrons stored below the second gate electrode to tunnel into the semiconductor layer below the first gate electrode; and a fifth step of applying a voltage to the third barrier gate electrode and the first barrier gate electrode to cause the electrons stored in the semiconductor layer below the first gate electrode to tunnel into the semiconductor layer below the second gate electrode. and (6) reading the spin state of the electron stored in the semiconductor layer of the first gate electrode by reading the output current in the fourth step and the fifth step using the charge sensor.

3. A quantum bit array as defined in claim 2, comprising: a first unit composed of the third barrier gate electrode, the first gate electrode, and the first barrier gate electrode for storing and controlling the electrons in the semiconductor layer; and a second unit composed of a first charge sensor barrier gate, the charge sensor, and a second charge sensor barrier gate for reading the state of the electrons, the first charge sensor barrier gate and the second charge sensor barrier gate being arranged adjacent to the charge sensor; a first unit array is formed by connecting a plurality of the first units in series in a one-dimensional row direction; a second unit array is formed by connecting a plurality of the second units in series in a one-dimensional row direction; independent drain voltage supply wiring and source voltage supply wiring are connected to the plurality of second units; the charge sensor and the second gate electrode of the first unit are arranged opposite each other so as to face each other; and the first unit and the second unit are arranged opposite each other.

4. A quantum bit array as defined in claim 3, wherein a first dummy unit array and a second dummy unit array having the same transistor configuration as that constituting the first unit array and the second unit array are arranged outside the first unit array and the second unit array, which are arranged opposite each other, and the quantum bit array has a quantum bit array group composed of the first unit array, the second unit array, the first dummy unit array, and the second dummy unit array.

5. A quantum bit array according to claim 4, wherein a plurality of said quantum bit array groups are arranged in a column direction, and in a plurality of said first units constituting a plurality of said quantum bit array groups, said gate electrodes having the same function are connected by control metal wiring, and said first step to said fourth step are carried out simultaneously in a plurality of said first units and said second units constituting a plurality of said quantum bit array groups.

6. A quantum bit array according to claim 4, comprising a comparison circuit that receives the output current as an input, and a voltage conversion detection circuit, wherein in the fourth step, the comparison circuit compares the magnitude of the output current to determine the spin state, and the voltage conversion detection circuit detects whether the output current has a desired value as a result of quantum operations.

7. A quantum bit array as defined in claim 5, comprising a comparison circuit which receives the output current as an input, and a voltage conversion detection circuit, wherein in the fourth step, the comparison circuit compares the magnitude of the output current to determine the spin state, the voltage conversion detection circuit detects whether the output current has the desired output current value as a result of a quantum operation, the comparison circuit and the voltage conversion detection circuit are connected to each second unit, and the same number of comparison circuits and voltage conversion detection circuits as the number of quantum bit array groups arranged in the column direction operate simultaneously, and the multiple output currents output from the second units in each quantum bit array group are compared and detected simultaneously, and when the result of the comparison and detection is the majority, the majority information is determined to be the desired spin information using majority logic.

8. A quantum bit array as defined in claim 2, further comprising a third gate electrode connected to the second barrier gate electrode, wherein when performing two-quantum operations using quantum bits stored in the first gate electrode and the third gate electrode, one of the two quantum bits is moved to the second gate electrode while maintaining its spin state, and the desired two-quantum operation operation is performed, after which the quantum bit that has been subjected to the quantum operation in the second gate electrode is moved to the third gate electrode while maintaining the result of the quantum operation, and then the second step through the fourth step are performed to determine spin information.

9. A quantum bit array according to claim 1, comprising: a first barrier gate electrode disposed between the first gate electrode and the second gate electrode; a second barrier gate electrode adjacent to the second gate electrode; and a third barrier gate electrode adjacent to the first gate electrode, the quantum bit array performing the following steps: a first step of storing the electron in the semiconductor layer below the first gate electrode; a second step of applying, to the first barrier gate electrode and the second barrier gate electrode, a voltage that causes the electron to tunnel into the semiconductor layer below the second gate electrode when the electron is of up spin; a third step of applying, to the first barrier gate electrode and the second barrier gate electrode, a voltage that causes the electron to tunnel into the semiconductor layer below the second gate electrode when the electron is of down spin; and a fourth step of reading the output current in the second step and the third step using the charge sensor to read the spin state of the electron.

10. A quantum information processing device comprising a quantum bit array and a control device that controls the quantum bit array, wherein the quantum bit array comprises: a first gate electrode; a second gate electrode; a semiconductor layer; and a charge sensor that reads the number of electrons stored in the semiconductor layer below the second gate electrode as an output current, wherein the output current reflects the state of the electrons in the semiconductor layer below the second gate electrode when the movement of electrons stored in the semiconductor layer below the first gate electrode and the second gate electrode is controlled between the first gate electrode and the second gate electrode, and the quantum information processing device reads the spin state of the electrons stored in the semiconductor layer below the first gate electrode based on the output current.

11. A quantum information processing device according to claim 10, wherein the quantum bit array has a comparison circuit that receives the output current as an input, and a voltage conversion detection circuit, wherein the comparison circuit compares the magnitude of the output current to determine the spin state, and the voltage conversion detection circuit detects whether the output current has the desired value as a result of quantum operations.

12. A quantum information processing device as defined in claim 11, wherein the control device receives a quantum operation request specified by a user, executes a quantum operation or quantum operation using the quantum bit array, and returns the quantum operation result to the user; the control device executes the quantum operation or quantum operation for a predetermined period of time, and then performs a calibration process to confirm the fidelity of the quantum operation result; when obtaining the quantum operation or quantum operation result, the control device uses the comparison circuit to read out the spin state; and when performing the calibration process, the control device uses the voltage conversion detection circuit.

13. A quantum bit readout method using a quantum bit array comprising a first gate electrode, a second gate electrode, a semiconductor layer, and a charge sensor that reads the number of electrons stored in the semiconductor layer below the second gate electrode as an output current, the quantum bit readout method comprising: reading, by the charge sensor, the output current that reflects the state of the electrons in the semiconductor layer below the second gate electrode when the movement of electrons stored in the semiconductor layer below the first gate electrode and the second gate electrode is controlled between the first gate electrode and the second gate electrode; and reading, based on the output current, the spin state of the electrons stored in the semiconductor layer below the first gate electrode.

14. A quantum bit readout method according to claim 13, comprising the steps of: a first step of storing the electron in the semiconductor layer below the first gate electrode; a second step of storing the electron in the semiconductor layer below the second gate electrode; a third step of setting the electron stored below the second gate electrode to a down spin state; a fourth step of applying a voltage to a first barrier gate electrode disposed between the first gate electrode and the second gate electrode and to a second barrier gate electrode adjacent to the second gate electrode, such that the electron stored below the second gate electrode tunnels into the semiconductor layer below the first gate electrode; a fifth step of applying a voltage to a third barrier gate electrode adjacent to the first gate electrode and to the first barrier gate electrode, such that the electron stored in the semiconductor layer below the first gate electrode tunnels into the semiconductor layer below the second gate electrode; and a sixth step of reading the output current in the fourth step and the fifth step using the charge sensor to read the spin state of the electron stored in the semiconductor layer of the first gate electrode.

15. A quantum bit readout method according to claim 13, comprising the steps of: a first step of storing the electron in the semiconductor layer below the first gate electrode; a second step of applying, to a first barrier gate electrode disposed between the first gate electrode and the second gate electrode and a second barrier gate electrode adjacent to the second gate electrode, a voltage that causes the electron to tunnel into the semiconductor layer below the second gate electrode when the electron is of up spin; a third step of applying, to the first barrier gate electrode and the second barrier gate electrode, a voltage that causes the electron to tunnel into the semiconductor layer below the second gate electrode when the electron is of down spin; and a fourth step of reading the output current in the second step and the third step using the charge sensor to read the spin state of the electron.

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