Schottky barrier junction type high electron mobility transistor, semiconductor device, semiconductor module, and electronic apparatus

Abstract

This Schottky barrier junction type high electron mobility transistor includes: a compound semiconductor layer having a barrier layer; an insulator disposed on the compound semiconductor layer and having a gate through-hole; a gate electrode embedded in the gate through-hole; and a carrier capture region disposed at least at one end of the gate electrode in the gate length direction. A trap density of carriers captured at an interface between the carrier capture region and the compound semiconductor layer is higher than a trap density of carriers captured at an interface between the compound semiconductor layer and the insulator.

Description

Schottky barrier junction high electron mobility transistor, semiconductor device, semiconductor module and electronic device

[0001] The present disclosure relates to a high electron mobility transistor, a semiconductor device, a semiconductor module, and an electronic device. In particular, the high electron mobility transistor in this disclosure relates to a Schottky barrier junction high electron mobility transistor.

[0002] Non-Patent Document 1 below discloses a Schottky Barrier Junction type High Electron Mobility Transistor. Hereinafter, the Schottky barrier junction type high electron mobility transistor will be simply referred to as an "SBJ-HEMT." Also, the high electron mobility transistor will be simply referred to as a "HEMT." Unlike MIS gate type (Metal Insulator Semiconductor gate type) HEMTs, SBJ-HEMTs do not have a gate insulating film. Therefore, there are fewer carrier capture sources directly below the gate electrode, and SBJ-HEMTs are very advantageous in terms of threshold voltage (Vth) fluctuations.

[0003] JOURNAL OF THE ELECTRON DEVICES SOCIETY, VOLUME 9, 2021, pp.756-762. 'Analysis of Low Voltage RF Power Capability on AlGaN / GaN and InAlN / GaN HEMTs for Terminal Applications'. YUWEI ZHOU et.al.

[0004] When SBJ-HEMTs are subjected to a high temperature reverse bias (HTRB) test, a reliability test that applies extreme off-stress, the off-leakage current increases from the initial value. For this reason, there is a need to improve the off-state characteristics of SBJ-HEMTs.

[0005] The SBJ-HEMT according to the first embodiment of the present disclosure includes a compound semiconductor layer having a barrier layer, an insulator disposed in the compound semiconductor layer and having a gate through-hole, a gate electrode embedded in the gate through-hole, and a carrier capture region disposed at least at one end of the gate electrode in the gate length direction, in which the trap density of carriers captured at the interface with the compound semiconductor layer is higher than the trap density of carriers captured at the interface between the compound semiconductor layer and the insulator.

[0006] In the SBJ-HEMT according to the first embodiment, the carrier capture region includes a cavity surrounded by the compound semiconductor layer, the gate electrode, and the insulator.

[0007] In the SBJ-HEMT according to the second embodiment of the present disclosure, the carrier capture region in the SBJ-HEMT according to the first embodiment is disposed on the drain region side.

[0008] In the SBJ-HEMT according to the third embodiment of the present disclosure, the carrier capture regions in the SBJ-HEMT according to the first embodiment are disposed on both the source region side and the drain region side.

[0009] A semiconductor device according to a fourth embodiment of the present disclosure includes an SBJ-HEMT, which includes a compound semiconductor layer having a barrier layer, an insulator disposed in the compound semiconductor layer and having a gate through-hole, a gate electrode embedded in the gate through-hole, and a carrier capture region disposed at least at one end of the gate electrode in the gate length direction, the carrier capture region having a higher trap density of carriers captured at the interface with the compound semiconductor layer than the trap density of carriers captured at the interface between the compound semiconductor layer and the insulator.

[0010] A semiconductor module according to a fifth embodiment of the present disclosure includes a semiconductor device having an SBJ-HEMT, the SBJ-HEMT including a compound semiconductor layer having a barrier layer, an insulator disposed in the compound semiconductor layer and having a gate through-hole, a gate electrode embedded in the gate through-hole, and a carrier capture region disposed at least at one end of the gate electrode in the gate length direction, the carrier capture region having a higher trap density of carriers captured at the interface with the compound semiconductor layer than the trap density of carriers captured at the interface between the compound semiconductor layer and the insulator.

[0011] An electronic device according to a sixth embodiment of the present disclosure includes a semiconductor device having an SBJ-HEMT, the SBJ-HEMT including a compound semiconductor layer having a barrier layer, an insulator disposed in the compound semiconductor layer and having a gate through-hole, a gate electrode embedded in the gate through-hole, and a carrier capture region disposed at least at one end of the gate electrode in the gate length direction, the carrier capture region having a higher trap density of carriers captured at the interface with the compound semiconductor layer than the trap density of carriers captured at the interface between the compound semiconductor layer and the insulator.

[0012] FIG. 1 is a vertical cross-sectional view of an SBJ-HEMT mounted on a semiconductor device according to a first embodiment of the present disclosure during off-state operation. FIG. 2 is an enlarged vertical cross-sectional view of a main portion of the SBJ-HEMT shown in FIG. 1. FIG. 3 is an energy band structure diagram of the SBJ-HEMT shown in FIGS. 1 and 2 during off-state operation. (A) is an energy band structure diagram of the gate electrode of the SBJ-HEMT and the compound semiconductor layer immediately below it. (B) is an energy band structure diagram of the carrier capture region of the SBJ-HEMT. (C) is an energy band structure diagram of the insulator from the carrier capture region to the main electrode of the SBJ-HEMT and the compound semiconductor layer immediately below it. FIG. 4 is an enlarged vertical cross-sectional view of an SBJ-HEMT according to a comparative example, corresponding to FIG. 2. FIG. 5 is an enlarged vertical cross-sectional view of the SBJ-HEMT shown in FIG. 4 after carrier capture, corresponding to FIG. 2. FIG. 6 is a graph showing the relationship between charge density at the semiconductor interface and off-state leakage characteristics in an SBJ-HEMT. FIG. 7 is a graph showing the relationship between the type of GaN surface passivation film and the interface state density and energy. FIG. 8 is a schematic vertical cross-sectional view of an SBJ-HEMT at each operation, illustrating the mechanism by which drain-lag occurs. FIG. 9 is a graph illustrating the relationship between drain voltage and drain current. FIG. 10 is a schematic vertical cross-sectional view of an SBJ-HEMT at each operation, illustrating the mechanism by which high-frequency-high-temperature operating life occurs. FIG. 11 is a graph illustrating the relationship between high-frequency time and output. FIG. 12 is a graph illustrating the relationship between insulator thickness and carrier capture region width. FIG. 13 is a graph illustrating the relationship between insulator thickness and SBJ-HEMT breakdown voltage. FIG. 14 is a graph illustrating the relationship between insulator thickness and drain-lag characteristics. FIG. 15 is a graph illustrating the relationship between insulator thickness and high-frequency-high-temperature operating life characteristics. FIG. 16 is a cross-sectional view corresponding to FIG. 1 at a first step, illustrating each step of a method for manufacturing a semiconductor device according to the first embodiment. FIG. 17 is a cross-sectional view at a second step. FIG. 18 is a cross-sectional view at a third step. FIG. 19 is a cross-sectional view at a fourth step. Fig. 20 is a cross-sectional view at a fifth step. Fig. 21 is a cross-sectional view at a sixth step. Fig. 22 is a cross-sectional view at a seventh step. Fig. 23 is an enlarged vertical cross-sectional configuration view corresponding to Fig. 2 of a main part of an SBJ-HEMT mounted on a semiconductor device according to a second embodiment of the present disclosure in an off-operation state.24 is an enlarged longitudinal sectional configuration diagram corresponding to FIG. 2 of a main part of an SBJ-HEMT mounted on a semiconductor device according to a third embodiment of the present disclosure in off operation. FIG. 25 is an enlarged longitudinal sectional configuration diagram corresponding to FIG. 2 of a main part of an SBJ-HEMT mounted on a semiconductor device according to a fourth embodiment of the present disclosure in off operation. FIG. 26 is an enlarged longitudinal sectional configuration diagram corresponding to FIG. 2 of a main part of an SBJ-HEMT mounted on a semiconductor device according to a fifth embodiment of the present disclosure in off operation. FIG. 27 is a perspective view of a semiconductor module according to a sixth embodiment of the present disclosure. FIG. 28 is a block configuration diagram of an electronic device according to a seventh embodiment of the present disclosure.

[0013] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The description will be made in the following order. 1. First Embodiment The first embodiment is a first example in which the present technology is applied to a HEMT mounted on a semiconductor device. Here, the HEMT is an SBJ-HEMT. In the first embodiment, the longitudinal cross-sectional configuration, various characteristics, and manufacturing method of the SBJ-HEMT will be described. 2. Second Embodiment The second embodiment is a second example in which a specific process is performed on the Schottky barrier junction region in the SBJ-HEMT according to the first embodiment. 3. Third Embodiment The third embodiment is a third example in which the configuration of the carrier capture region is changed in the SBJ-HEMT according to the first or second embodiment. 4. Fourth Embodiment The fourth embodiment is a fourth example in which the configuration of the carrier capture region is changed in the SBJ-HEMT according to the first to third embodiments. 5. Fifth Embodiment The fifth embodiment is a fifth example in which the configuration of the carrier capture region is changed in the SBJ-HEMT according to the first to fourth embodiments. 6. Sixth Embodiment The sixth embodiment is a sixth example that explains a semiconductor module in which a semiconductor device including an SBJ-HEMT according to the first to fifth embodiments is mounted. 7. Seventh Embodiment The seventh embodiment is a seventh example that explains an electronic device in which a semiconductor device including an SBJ-HEMT according to the first to fifth embodiments is mounted. 8. Other Embodiments

[0014] 1 to 22 , a semiconductor device 1 and a manufacturing method thereof according to a first embodiment of the present disclosure will be described. Here, the arrow X direction shown as appropriate in the figures conveniently represents one planar direction of the semiconductor device 1 placed on a flat surface. The arrow Y direction represents another planar direction perpendicular to the arrow X direction. The arrow Z direction represents an upward direction perpendicular to the arrow X and arrow Y directions. In other words, the arrow X direction, arrow Y direction, and arrow Z direction exactly correspond to the X-axis direction, Y-axis direction, and Z-axis direction, respectively, of a three-dimensional coordinate system. Note that these directions are illustrated to facilitate understanding of the description and do not limit the directions of the present technology.

[0015] [Configuration of Semiconductor Device 1 and SBJ-HEMT 2] Fig. 1 shows an example of the cross-sectional configuration of a semiconductor device 1 according to the first embodiment and an SBJ-HEMT 2 mounted thereon. The cross-sectional configuration is a cross-sectional configuration as seen in the direction of arrow Y (hereinafter simply referred to as "side view"). Fig. 2 shows an example of the cross-sectional configuration in which a main part of the SBJ-HEMT 2 is enlarged.

[0016] (1) Schematic Overall Configuration of Semiconductor Device 1 and SBJ-HEMT 2 As shown in Fig. 1 and Fig. 2, the semiconductor device 1 is configured based on a substrate 3. The semiconductor device 1 includes an SBJ-HEMT 2 on the substrate 3.

[0017] In side view, the SBJ-HEMT 2 includes a substrate 3, a compound semiconductor layer 4, a pair of main electrodes 5 used as a source region and a drain region, and a gate electrode 8. For convenience, in FIG. 1, the left side is used as the main electrode 5 which is the source region (S), and the right side is used as the main electrode 5 which is the drain region (D). Each component of the SBJ-HEMT 2 will be described in detail below.

[0018] (2) Structure of the Substrate 3 In the first embodiment, the substrate 3 is made of a semiconductor material. Specifically, for example, Si, SiC, or a III-V group compound semiconductor is used as the substrate 3. Note that the lattice constant between the substrate 3 and the channel layer 42 can be controlled by using a buffer layer 41 that constitutes the compound semiconductor layer 4, which will be described later.

[0019] (3) Configuration of Compound Semiconductor Layer 4 The compound semiconductor layer 4 is formed by sequentially stacking a buffer layer 41, a channel layer 42, a barrier layer 44, and a cap layer 45 from the surface of the substrate 3 in the direction of the arrow Z. The detailed configuration of the compound semiconductor layer 4 is as follows:

[0020] (3-1) Configuration of Buffer Layer 41 The buffer layer 41 is formed on the substrate 3 using an epitaxial growth method. When the lattice constants of the substrate 3 and the channel layer 42 differ, the lattice constant can be controlled by the buffer layer 41. This improves the crystal quality of the channel layer 42. Furthermore, in the manufacturing process, warpage of the substrate 3 after the channel layer 42 is formed can be controlled. The warpage of the substrate 3 here corresponds to the warpage of a semiconductor wafer before the dicing step in the manufacturing process.

[0021] In the first embodiment, when the substrate 3 is made of single crystal Si and the channel layer 42 is made of GaN, the buffer layer 41 can be made of one or more compound semiconductor materials selected from AlN, AlGaN, and GaN. ４ ), Ga ２ O ３ Alternatively, the semiconductor layer 12 may be made of a compound semiconductor material such as AlN or diamond.

[0022] The buffer layer 41 may be formed as a single layer, or may be formed by laminating the above-mentioned multiple compound semiconductor materials. When the buffer layer 41 is formed from a ternary compound semiconductor material, the composition ratio may be gradually changed in the film formation direction. Furthermore, the buffer layer 41 may be doped with impurities such as C and Fe as appropriate. Doping with these impurities can reduce buffer leakage.

[0023] (3-2) Configuration of the Channel Layer 42 The channel layer 42 is made of, for example, a compound semiconductor material. The compound semiconductor material is formed on the buffer layer 41 by epitaxial growth. The channel layer 42 forms part of the current path between the pair of main electrodes 5. More specifically, a two-dimensional electron gas (2DEG) 43 is formed in the channel layer 42 due to the difference in polarization charge between the channel layer 42 and the barrier layer 44 disposed on the channel layer 42, and carriers are accumulated therein. Here, the carriers are, for example, electrons.

[0024] The channel layer 42 is formed of a compound semiconductor material, such as GaN. GaN may be formed of undoped GaN (u-GaN), which does not contain impurities. In this case, impurity scattering of carriers in the channel layer 42 can be suppressed, thereby improving carrier mobility. The channel layer 42 is formed to a thickness of, for example, 30 nm to 300 nm.

[0025] Here, a back barrier layer may be disposed between the channel layer 42 and the buffer layer 41. The back barrier layer may be, for example, an Al film formed by epitaxial growth. １－ｘ－ｙ Ga ｘ In ｙ N (0≦x<1, 0≦y<1), undoped Al １－ｘ－ｙ Ga ｘ In ｙ The back barrier layer does not have to be a single layer, and can be made of, for example, the above-mentioned Al １－ｘ－ｙ Ga ｘ In ｙThe layer may be laminated with varying N composition, or may have a composition that gradually changes in composition in the film-forming direction.

[0026] (3-3) Composition of Barrier Layer 44 The barrier layer 44 is made of a compound semiconductor material that accumulates carriers in the channel layer 42 due to polarization with the channel layer 42. The compound semiconductor material is formed on the barrier layer 44 by epitaxial growth. The barrier layer 44 is a nitride semiconductor material with a band gap larger than that of the channel layer 42. A detailed explanation will be given below. The barrier layer 44 is made of, for example, Al １－ｘ－ｙ Ga ｘ In ｙ N (0≦x<1, 0≦y<1), undoped Al １－ｘ－ｙ Ga ｘ In ｙ The semiconductor layer is made of a nitride semiconductor material such as N (0≦x<1, 0≦y<1).

[0027] The barrier layer 44 does not need to be a single layer. For example, １－ｘ－ｙ Ga ｘ In ｙ The barrier layer 44 may be stacked with varying N compositions, or may have a composition that gradually changes in the film-forming direction. The barrier layer 44 is formed to a thickness of, for example, 3 nm to 20 nm.

[0028] It should be noted that the "compound semiconductor layer having a barrier layer" according to the present disclosure corresponds to the "compound semiconductor layer 4 having the barrier layer 44."

[0029] (3-4) Composition of the Cap Layer 45 The cap layer 45 is formed by being laminated on the barrier layer 44. The cap layer 45 is formed, for example, of a single layer of GaN or SiN, or a composite layer in which SiN is laminated on GaN. The cap layer 45 may also be formed, for example, of a single layer, from a material whose composition element concentration changes in the thickness direction. The cap layer 45 may also be formed, for example, from Al １－ｚ－ｗ In ｚ Ga ｗThe cap layer 45 may be formed of a compound semiconductor material of N (0≦z≦1, 0≦w≦1, z+w≦1). In this case, the surface of the wafer on which the epitaxial layer is formed can be protected from handling and process history. The cap layer 45 is formed to a thickness of, for example, 0.5 nm to 5.0 nm.

[0030] It should be noted that the cap layer 45 is not necessarily required from the viewpoint of the final desired device characteristics, mass productivity, and the like.

[0031] (4) Configuration of the Main Electrode 5 One of the pair of main electrodes 5, which is used as a drain region, is disposed at one end on the right side of the two-dimensional electron gas 43 in the gate length direction of the SBJ-HEMT 2. The other of the pair of main electrodes 5, which is used as a source region, is disposed at the other end on the left side of the two-dimensional electron gas 43 in the gate length direction of the SBJ-HEMT 2. The main electrodes 5 and the two-dimensional electron gas 43 are electrically connected by low resistance.

[0032] Here, the main electrode 5 is formed by introducing n-type impurities at a high impurity density into the substrate 3. The n-type impurities are introduced by, for example, an ion implantation method.

[0033] Here, an isolation region serving as a non-active region is disposed around the outer periphery of the main electrode 5 and surrounding the active region where the SBJ-HEMT 2 is disposed. The isolation region is formed by injecting impurities using ion implantation. For example, B is used as the implanted impurity.

[0034] The main electrode 5 can also be formed using a selective regrowth method. In this case, the main electrode 5 is formed of, for example, n-type Ga １－ｘ In ｘ The main electrode 5 does not need to be a single layer, and may be formed of, for example, Ga １－ｘ In ｘThe layer may be formed by changing the composition of N (0≦x<1), or by gradually changing the composition in the film-forming direction. Si, Ge, etc. can be used as the n-type dopant. The impurity density is, for example, 1×10 １８ cm －３ That's all.

[0035] (5) Configuration of Electrode 9 The electrode 9 laminated on the surface of the main electrode 5 is electrically connected to the main electrode 5. The electrode 9 is an ohmic electrode, and is connected to the surface of the main electrode 5 with a low resistance value. Although detailed configuration is not shown, the electrode 9 is formed by sequentially laminating, for example, Ti, Al, Ni, and Au from the main electrode 5 side toward the arrow Z direction.

[0036] In the manufacturing process of the semiconductor device 1, the electrode 9 is subjected to an annealing treatment. When this annealing treatment is performed, the ohmic contact characteristics between the main electrode 5 and the electrode 9 can be improved.

[0037] The steps of forming the main electrode 5, the electrode 9, and the aforementioned element isolation region can be appropriately performed before or after the step of forming the gate electrode 8 in the manufacturing process of the semiconductor device 1.

[0038] (6) Structure of insulator 6 As shown in Figures 1 and 2, an insulator 6 serving as a passivation film is disposed on cap layer 45 of compound semiconductor layer 4, covering electrode 9. In the first embodiment, insulator 6 includes a first insulating film 61 and a second insulating film 62.

[0039] The first insulating film 61 is disposed on the cap layer 45 of the compound semiconductor layer 4. The first insulating film 61 is made of an insulating material that is insulating with respect to the barrier layer 44 and forms a good interface with the barrier layer 44, thereby improving the characteristics of the SBJ-HEMT 2. In addition, the first insulating film 61 is made of an insulating material that is wet-etchable and has high dry-etching resistance.

[0040] In the first embodiment, a film containing Al or a film containing an oxide is used for the first insulating film 61. Specifically, the first insulating film 61 is made of, for example, Al. ２ O ３ or HfO ２ The first insulating film 61 is formed by, for example, atomic layer deposition (ALD) and has a thickness of, for example, 1.5 nm to 5.0 nm.

[0041] The second insulating film 62 is disposed on the opposite side of the first insulating film 61 from the compound semiconductor layer 4. In other words, the second insulating film 62 is stacked on the first insulating film 61. The second insulating film 62 is made of an insulating material that is insulating with respect to the barrier layer 44 and the first insulating film 61 and can protect the surface of the compound semiconductor layer 4 from impurities such as ions. The second insulating film 62 is made of an insulating material that is suitable for dry etching and has high wet etching resistance. In other words, the second insulating film 62 is made of an insulating material that has a different etching selectivity ratio from the first insulating film 61.

[0042] In the first embodiment, a film containing nitride is used for the second insulating film 62. Specifically, for example, plasma SiN (P-SiN) is used for the second insulating film 62. The second insulating film 62 is formed by using, for example, a plasma chemical vapor deposition (CVD) method. The second insulating film 62 is formed to a thickness of, for example, 10 nm or more and 150 nm or less. More specifically, plasma SiN is a film containing SiH ４ and N.H. ３ and react with each other using plasma energy to form a silicon nitride film (SiN, Si ３ N ４ ) and hydrogen (H ２ ) is formed and deposited on the first insulating film 61. The second insulating film 62 is made of SiO 2 , which has a high wet etching selectivity with respect to the first insulating film 61. ２ is available.

[0043] (7) Configuration of Gate Electrode 8 The gate electrode 8 is in contact with the uppermost cap layer 45 of the compound semiconductor layer 4 at the center between the pair of main electrodes 5 through a gate through hole (or gate via hole) 6H formed in the insulator 6. That is, the gate electrode 8 is in contact with the compound semiconductor layer 4 by a Schottky barrier junction. The gate length of the gate electrode 8 is formed to be effectively the same as the opening width of the gate through hole 6H. The gate length of the gate electrode 8 is set to, for example, 0.1 μm or more and 1.0 μm or less.

[0044] In the first embodiment, the gate electrode 8 is formed by sequentially stacking Ni and Au layers from the compound semiconductor layer 4 in the direction of the arrow Z. The gate electrode 8 is formed, for example, by a mask deposition method. When viewed from the side, the gate electrode 8 is formed to have a T-shaped cross section (T-shaped gate electrode structure). An SBJ-HEMT 2 having a gate electrode 8 with such a structure can reduce gate impedance.

[0045] Furthermore, the gate electrode 8 may have a barrier metal such as Ti or Pd disposed between the Ni and Au. The provision of the barrier metal effectively suppresses or prevents metal diffusion of Ni and Au due to annealing treatment in the manufacturing process of the semiconductor device 1.

[0046] (8) Configuration of Carrier Capture Region 7 As shown in FIGS. 1 and 2, the SBJ-HEMT 2 according to the first embodiment includes a carrier trapping region 7. The carrier trapping region 7 is disposed at least at one end of the gate electrode 8 in the gate length direction. In the first embodiment, the carrier trapping region 7 is disposed at both one end of the gate electrode 8 on the drain region side and the other end of the gate electrode 8 on the source region side in the gate length direction.

[0047] The carrier capture region 7 is formed to include a cavity (or void) 71 surrounded by the compound semiconductor layer 4, the gate electrode 8, and the insulator 6. That is, the carrier capture region 7 is constructed at the interface between the cap layer 45 of the compound semiconductor layer 4 and the cavity 71. This will be explained in detail.

[0048] First, the cavity 71 is formed surrounded by the surface of the cap layer 45 of the compound semiconductor layer 4, the sidewall of the gate electrode 8, the side surface of the first insulating film 61 of the insulator 6, and the lower surface of the second insulating film 62 of the insulator 6. In the manufacturing process of the semiconductor device 1, in the step of forming the gate through-hole 6H, the cavity 71 can be formed by selectively side-etching the first insulating film 61 with respect to the compound semiconductor layer 4 and the second insulating film 62. The side etching is performed from the gate through-hole 6H toward the main electrode 5. The manufacturing process of the semiconductor device 1 will be described later as a manufacturing method of the semiconductor device 1.

[0049] In the carrier capture region 7, the trap density of carriers captured at the interface between the compound semiconductor layer 4 and the cavity 71 is higher than the trap density of carriers captured at the interface between the compound semiconductor layer 4 and the insulator 6. Explained in detail below, in the carrier capture region 7, the trap density of carriers captured at the interface between the cap layer 45 of the compound semiconductor layer 4 and the cavity 71 is higher than the trap density of carriers captured at the interface between the cap layer 45 of the compound semiconductor layer 4 and the first insulating film 61 of the insulator 6.

[0050] (8-1) Energy Band Structure of Carrier Capture Region 7 Figure 3 shows an example of the energy band structure of the SBJ-HEMT 2 during off-state operation (when an off-state voltage is applied). Figure 3(A) shows an example of the energy band structure of the gate electrode 8 of the SBJ-HEMT 2 and the compound semiconductor layer 4 directly below it. Figure 3(B) shows an example of the energy band structure of the carrier capture region 7 of the SBJ-HEMT 2. Figure 3(C) shows an example of the energy band structure of the insulator 6 from the carrier capture region 7 of the SBJ-HEMT 2 to the main electrode 5 used as the drain region (access portion) and the compound semiconductor layer 4 directly below it.

[0051] As shown in Figure 3A, in the SBJ-HEMT 2, the gate electrode 8 is in Schottky barrier junction with the compound semiconductor layer 4 directly below it. Here, CBM is the conduction band, VBM is the valence band, and E Ｆ is the Fermi energy, Eg is the band gap, and Vg is the gate voltage. The gate voltage Vg is, for example, −5 V.

[0052] 3C, in the SBJ-HEMT 2, at the access portion between the carrier capture region 7 or cavity 71 and the main electrode 5, the cap layer 45 of the compound semiconductor layer 4 contacts the first insulating film 61 of the insulator 6. During off-state operation, carriers that existed in the two-dimensional electron gas 43 during on-state operation of the SBJ-HEMT 2 are trapped at the interface between the cap layer 45 and the first insulating film 61. In the first embodiment, the carriers are electrons.

[0053] 3B, in the SBJ-HEMT 2, the carrier capture region 7 includes a cavity 71 and is formed at the interface between the cavity 71 and the cap layer 45 of the compound semiconductor layer 4. During off-state operation, carriers that existed in the two-dimensional electron gas 43 during on-state operation of the SBJ-HEMT 2 are captured at the interface between the cap layer 45 and the cavity 71. The trap density of carriers captured at the interface between the cap layer 45 and the cavity 71 is higher than the trap density of carriers captured at the interface between the cap layer 45 and the first insulating film 61. For example, the trap density of the carrier capture region 7 is 1.5 times or more the trap density of the access portion. Therefore, the energy band structure of the carrier capture region 7 is elevated toward the surface of the compound semiconductor layer 4 relative to the energy band structure of the access portion.

[0054] (8-2) Off-Leakage Characteristics of the SBJ-HEMT 20 According to the Comparative Example Fig. 4 shows an example of an enlarged vertical cross-sectional structure of the SBJ-HEMT 20 according to the comparative example. Fig. 5 shows an example of an enlarged vertical cross-sectional structure of the SBJ-HEMT 20 after carrier capture.

[0055] 4, in the off-state, in the SBJ-HEMT 20, the electric field intensity and current density increase due to electric field concentration at the end of the access part on the drain region side, which is closer to the gate electrode 8. As a result, carriers (here, electrons) are captured at the interface between the compound semiconductor layer 4 and the insulator 6 in the access part, increasing the carrier concentration (here, electron concentration Ns).

[0056] As shown in FIG. 5, after carrier capture, in the SBJ-HEMT 20, the carrier concentration becomes high at the interface between the compound semiconductor layer 4 and the insulator 6 in the access portion, and therefore the negative charge density becomes high.

[0057] FIG. 6 shows an example of the relationship between the charge density at the semiconductor interface and off-leakage characteristics. In FIG. 6, the horizontal axis represents the gate voltage Vg [V], and the vertical axis represents the drain current Id [A]. As shown in FIG. 6, the SBJ-HEMT 20 according to the comparative example has a high off-leakage current during off-state operation (see reference numeral 20).

[0058] (8-3) Off-Leakage Characteristics of the SBJ-HEMT 2 According to the First Embodiment Compared to the SBJ-HEMT 20 according to the comparative example shown in FIGS. 4 and 5, the SBJ-HEMT 2 shown in FIGS. 1 and 2 has a higher carrier (electron) trap density in the carrier capture region 7. The more carriers are trapped in the carrier capture region 7, the lower the carrier concentration (here, electron concentration Ns). In other words, the negative charge density in the carrier capture region 7 becomes higher. Therefore, in the SBJ-HEMT 2, the carrier capture region 7 makes it easier for the depletion layer to extend (spread), effectively mitigating the electric field strength.

[0059] As shown in FIG. 6, the off-leak current that flows during off-state operation in the SBJ-HEMT 2 according to the first embodiment is lower than the off-leak current of the SBJ-HEMT 20 according to the comparative example. In other words, the provision of the carrier capture region 7 effectively reduces the off-leak current of the SBJ-HEMT 2. Therefore, the SBJ-HEMT 2 can improve its high-temperature reverse bias (HTRB) characteristics.

[0060] (8-4) Improvement of SBJ-HEMT2 Characteristics by the Structure of the Insulator 6 In the SBJ-HEMT2 according to the first embodiment, it is important to optimize the insulator 6 when providing the carrier capture region 7. In other words, it is necessary to optimally set the configuration of the insulator 6 (semiconductor surface protection film) in contact with the surface of the compound semiconductor layer 4. FIG. 7 shows an example of the relationship between the type of GaN surface protection film and the interface state density and energy, as cited in the following reference: Reference: 16th Crystal Engineering Seminar, Crystal Engineering Subcommittee, Applied Physics Society, Hokkaido University, October 14, 2011.

[0061] In Fig. 7, the horizontal axis represents the energy [eV] from the bottom of the conduction band, and the vertical axis represents the interface state density [cm －２ eV －１ As shown in FIG. 7, the Al level at a level deeper than 0.2 eV from the conduction band Ec ２ O ３ The interface trap density of the SiN film is higher than that of the SiN film. Here, the interface trap density without surface protection is the highest.

[0062] (8-5) Other characteristic improvements of SBJ-HEMT2 As described above, the SBJ-HEMT2 can improve the high-temperature reverse bias characteristics by providing the carrier capture region 7. The SBJ-HEMT2 according to the first embodiment further improves the drain-lag characteristics and the radio frequency-high temperature operating life (RF-HTOL) characteristics.

[0063] 8 shows an example of an SBJ-HEMT for each operation, which explains the mechanism by which drain-lag occurs. Here, the mechanism by which drain-lag occurs is explained using the SBJ-HEMT 20 according to the comparative example shown in FIG. 4 or FIG. 5.

[0064] As shown in Figure 8, in the SBJ-HEMT 20, carriers are trapped at the interface between the compound semiconductor layer 4 and the insulator 6 in the access area during off-state operation. If these trapped carriers are not released during on-state operation, the electron density decreases, resulting in a deterioration in current capability. Interface traps release carriers with a certain time constant, resulting in a slow current response to voltage.

[0065] Figure 9 shows an example of the relationship between drain voltage and drain current. In Figure 9, the horizontal axis represents drain voltage Vd, and the vertical axis represents drain current Id. The drain current Id versus drain voltage Vd of SBJ-HEMT 20, indicated by the dashed line and labeled 20, is in an off-stress state. The longer the time constant, the lower the drain current Id, and the worse the drain-lag characteristics.

[0066] In contrast to the SBJ-HEMT 20 according to the comparative example, the SBJ-HEMT 2 according to the first embodiment has a carrier capture region 7 that captures carriers in an appropriate range over both the source region side and the drain region side. As a result, as shown by the reference numeral 2 in Figure 9, the source resistance is suppressed, and an increase in on-resistance (Ron) and a decrease in drain current (Id) can be suppressed, thereby improving the drain-lag characteristics.

[0067] 10 shows an example of an SBJ-HEMT for each operation, which explains the mechanism by which the high-frequency-high-temperature operating lifespan occurs. Here, the mechanism by which the high-frequency-high-temperature operating lifespan occurs is explained using the SBJ-HEMT 20 according to the comparative example shown in FIG. 4 or FIG. 5.

[0068] As shown in FIG. 10 , in the SBJ-HEMT 20, carriers are captured at the interface between the compound semiconductor layer 4 and the insulator 6 in the access portion during off operation (OFF1). If some of the captured carriers are not released during on operation (ON1), additional carriers will be captured at the interface between the compound semiconductor layer 4 and the insulator 6 in the access portion during the next off operation (OFF2), in addition to the carriers already captured. In other words, carriers are accumulated. During the next on operation (ON2), the output of the SBJ-HEMT 20 decreases due to the accumulated carriers. In particular, if carriers are captured over a wide area over the drain region side of the SBJ-HEMT 20 and accumulate without being sufficiently released, the output (Pout) decreases compared to the initial state.

[0069] Figure 11 shows an example of the relationship between high-frequency time and output. In Figure 11, the horizontal axis represents the high-frequency stress application time (RF-time). The vertical axis represents the output (Pout). As shown in Figure 11, the output of the SBJ-HEMT 20 decreases as the time constant increases, resulting in a deterioration in the high-frequency-high-temperature operating life characteristics.

[0070] Unlike the SBJ-HEMT 20 according to the comparative example, the SBJ-HEMT 2 according to the first embodiment has a carrier capture region 7 that captures carriers in an appropriate range over both the source region and the drain region. As a result, as shown in Figure 11, the decrease in output power during the transition to ON operation is effectively suppressed, and the high-frequency-high-temperature operating life characteristics are improved.

[0071] (8-6) Size of Carrier Capture Region 7 The carrier capture region 7 according to the first embodiment includes a cavity 71 , and the size of the cavity 71 is effectively determined by the thickness of the first insulating film 61 of the insulator 6 .

[0072] FIG. 12 shows an example of the relationship between the thickness of the insulator 6 and the width of the carrier capture region 7. In FIG. 12, the horizontal axis represents the thickness [nm] of the first insulating film 61 of the insulator 6. The vertical axis represents the width [nm] of the carrier capture region 7 in the gate length direction. FIG. 13 shows an example of the relationship between the thickness of the insulator 6 and the breakdown voltage of the SBJ-HEMT 2. In FIG. 13, the horizontal axis represents the thickness [nm] of the first insulating film 61 of the insulator 6. The vertical axis represents the breakdown voltage BVds [V] between the drain and source regions of the SBJ-HEMT 2. Here, the distance (Lgd) between the gate electrode and the drain region (main electrode 5) of the SBJ-HEMT 2 is set to 0.5 μm. As a result, the depletion layer does not extend any further, and the breakdown voltage appears to be saturated. FIG. 14 shows an example of the relationship between the thickness of the insulator 6 and the drain-lag characteristics. In FIG. 14, the horizontal axis represents the thickness [nm] of the first insulating film 61 of the insulator 6. The vertical axis represents the degradation rate [%] of the drain current Id of the SBJ-HEMT 2. Fig. 15 shows an example of the relationship between the thickness of the insulator 6 and the high-frequency-high-temperature operating life characteristics. In Fig. 15, the horizontal axis represents the thickness [nm] of the first insulating film 61 of the insulator 6. The vertical axis represents the rate of change [%] of the output when a high frequency is applied to the SBJ-HEMT 2 for 1000 minutes.

[0073] 12 , as the thickness of the first insulating film 61 increases, side etching of the first insulating film 61 is promoted. Therefore, the height of the carrier capture region 7 in the direction of arrow Z from the surface of the compound semiconductor layer 4 increases. Furthermore, in the carrier capture region 7, the width in the gate length direction from the end of the gate electrode 8 of the cavity 71 to the main electrode 5 used as the drain region increases. If the thickness of the first insulating film 61 is less than 1 nm, side etching becomes difficult, and therefore the cavity 71 is not formed, and as a result, the carrier capture region 7 is not formed. Furthermore, if the carrier capture region 7 is not formed, the depletion layer does not easily expand, and the off-leakage current increases during high-temperature reverse bias.

[0074] Furthermore, as shown in FIG. 13, if the thickness of the first insulating film 61 is less than 1 nm, the SBJ-HEMT 2 cannot obtain a sufficient breakdown voltage.

[0075] 12, when the thickness of the first insulating film 61 exceeds 2 nm, a cavity 71 is formed, resulting in the formation of a carrier capture region 7. The formation of the carrier capture region 7 facilitates the expansion of the depletion layer, thereby reducing the off-leak current during high-temperature reverse bias. Furthermore, as shown in FIG. 13, the SBJ-HEMT2 achieves a sufficient and stable breakdown voltage.

[0076] On the other hand, as shown in FIG. 12, when the thickness of the first insulating film 61 exceeds 10 nm, the width of the carrier capture region 7 becomes very large, at approximately 30 nm. In this case, as shown in FIG. 13, the amount of carriers captured by the carrier capture region 7 increases during off-state operation, and the degradation rate of the drain current Id increases. This deteriorates the drain-lag characteristics that allow for an instantaneous transition from off-state operation to on-state operation. Similarly, as shown in FIG. 14, the high-frequency-high-temperature operating life characteristics that allow for an instantaneous transition from off-state operation to on-state operation deteriorate.

[0077] Therefore, the thickness of the first insulating film 61 is set to 10 nm or less, i.e., the height of the cavity 71 from the surface of the compound semiconductor layer 4 is set to 10 nm or less, thereby constructing the carrier capture region 7. Here, in the manufacturing process of the semiconductor device 1, when the cavity 71 is formed, it is assumed that the second insulating film 62 is wet-etched from the first insulating film 61 side, and the height of the cavity 71 exceeds the thickness of the first insulating film 61. If the height of the cavity 71 is too high, the electric field relaxation effect due to the field plate effect of the gate electrode 8 will be weakened. For this reason as well, the height of the cavity 71 is set to 10 nm or less. The height of the cavity 71 that constructs the carrier capture region 7 is preferably set to 2 nm or more and 5 nm or less.

[0078] Furthermore, the width of the cavity 71, i.e., the width of the carrier capture region 7, is formed to a length of 1 nm to 15 nm in the gate length direction from at least one end of the gate electrode 8 (see FIG. 12 ). The gate electrode 8 side of the carrier capture region 7 is formed so as to be in contact with the gate electrode 8, with part of the gate electrode 8 exposed in the cavity 71. When the width of the carrier capture region 7 is preferably formed to a length of 2 nm to 12 nm, both off-operation characteristics and on-operation characteristics can be achieved.

[0079] Although not shown in the drawings, the carrier capture region 7 is formed to have substantially the same size in the gate width direction as the gate width dimension of the gate electrode 8. Furthermore, a plurality of carrier capture regions 7 may be arranged spaced apart from each other in the gate width direction.

[0080] 16 to 22 show an example of each process for explaining a method for manufacturing the semiconductor device 1 according to the first embodiment. The method for manufacturing the semiconductor device 1 is as follows.

[0081] First, a substrate 3 is prepared (see FIG. 16 ), and as shown in FIG. 16 , a compound semiconductor layer 4 is formed on the substrate 3. Single-crystal GaN is used for the substrate 3. The compound semiconductor layer 4 is formed by sequentially stacking a buffer layer 41, a channel layer 42, a barrier layer 44, and a cap layer 45. Each layer of the compound semiconductor layer 4 is formed by, for example, an epitaxial growth method.

[0082] 17 , a pair of main electrodes 5 are formed on the compound semiconductor layer 4. The main electrodes 5 are formed using an ion implantation method or a selective epitaxial growth method. Note that, in a step before or after the step of forming the main electrodes 5, an element isolation region (not shown) is formed.

[0083] As shown in FIG. 18, an electrode 9 is formed on the main electrode 5 to be in ohmic contact with the main electrode 5 .

[0084] 19, a first insulating film 61 is formed to cover the surface of the compound semiconductor layer 4 and the surface of the electrode 9. The first insulating film 61 is made of, for example, Al ２ O ３The thickness of the first insulating film 61 is, for example, 2 nm to 5 nm. The first insulating film 61 is formed by using, for example, the ALD method. ２ is available.

[0085] 20, a second insulating film 62 is formed on the first insulating film 61. The second insulating film 62 is made of, for example, plasma SiN. The thickness of the second insulating film 62 is, for example, 10 nm or more and 150 nm or less. The second insulating film 62 is formed by, for example, plasma CVD. The second insulating film 62 is made of, for example, SiO ２ When the second insulating film 62 is formed, the insulator 6 is formed in which the second insulating film 62 is stacked on the first insulating film 61 .

[0086] As shown in FIG. 21 , a through-hole 6H1, which is a part of the gate through-hole 6H, is formed in the second insulating film 62 of the insulator 6. The through-hole 6H1 is formed by dry etching using a mask formed by photolithography (not shown). For example, a carbon fluoride (CF)-based etching gas is used for the dry etching. The opening width of the through-hole 6H1 in the gate length direction corresponds to the gate length dimension of the SBJ-HEMT 2. Since the first insulating film 61 has an etching selectivity with respect to the second insulating film 62, the first insulating film 61 is used as an etching stopper in the process of forming the through-hole 6H1. This makes it possible to avoid damage to the surface of the compound semiconductor layer 4 that would otherwise be caused by dry etching.

[0087] 22 , a through-hole 6H2, which is the remaining portion of the gate through-hole 6H, is formed in the first insulating film 61 of the insulator 6. Using the through-hole 6H1 as a mask, the through-hole 6H2 is formed by wet etching until the surface of the compound semiconductor layer 4 is exposed. For example, a diluted tetramethylammonium hydroxide aqueous solution (TMAH) or a buffered hydrofluoric acid (BHF) solution is used for the wet etching. When the through-hole 6H2 is formed, the through-holes 6H1 and 6H2 communicate with each other, thereby forming the gate through-hole 6H.

[0088] Furthermore, when wet etching is used to form the through-hole 6H2, the second insulating film 62 is not substantially etched, and therefore a portion of the first insulating film 61 is removed by side etching using the through-hole 6H1 as a mask, thereby forming a cavity 71 (see FIG. 22 ). When the cavity 71 is formed, a carrier capture region 7 is substantially formed at the interface between the compound semiconductor layer 4 and the cavity 71.

[0089] 1 and 2, a gate electrode 8 is formed through the gate through-hole 6H to form a Schottky barrier junction with the surface of the compound semiconductor layer 4. When the gate electrode 8 is formed, the SBJ-HEMT 2 is substantially completed, and the method for manufacturing the semiconductor device 1 according to the first embodiment is completed.

[0090] [Operation and Effect] As described above, the semiconductor device 1 according to the first embodiment includes an SBJ-HEMT 2, as shown in FIGS. 1 and 2. The SBJ-HEMT 2 includes a compound semiconductor layer 4, an insulator 6, a gate electrode 8, and a carrier capture region 7. The compound semiconductor layer 4 includes a barrier layer. The insulator 6 is disposed in the compound semiconductor layer 4 and has a gate through-hole 6H. The gate electrode 8 is embedded in the gate through-hole 6H. The carrier capture region 7 is disposed at least at one end of the gate electrode 8 in the gate length direction. In the carrier capture region 7, the trap density of carriers captured at the interface with the compound semiconductor layer 4 is higher than the trap density of carriers captured at the interface between the compound semiconductor layer 4 and the insulator 6. The SBJ-HEMT 2 configured in this manner includes the carrier capture region 7, which facilitates the expansion of the depletion layer during off-state operation and realizes electric field relaxation. As a result, as shown in FIG. 6, high-temperature reverse bias characteristics are improved and off-state leakage is effectively suppressed.

[0091] In addition, in the SBJ-HEMT2, the distance Lgd between the gate electrode 8 and the main electrode 5, which is the drain region, can be increased to improve the breakdown voltage (see FIG. 13). In addition, the maximum value of the breakdown voltage can be significantly improved by the tolerance.

[0092] Furthermore, in the SBJ-HEMT2, the carrier capture region 7 on the source region side is formed to a minute size, so that deterioration of the on-resistance Ron on the on side and the drain current can be effectively suppressed (see FIG. 9).

[0093] Furthermore, in the SBJ-HEMT2, the carrier capture region 7 on the drain region side is formed to a minute size, which effectively suppresses the deterioration of the drain-lag characteristics when transitioning from off operation to on operation and the high-frequency-high-temperature operating life characteristics.

[0094] 21 and 22, in the method for manufacturing the semiconductor device 1, the gate through-hole 6H is formed by two-stage dry etching and wet etching. Wet etching can reduce damage to the surface of the compound semiconductor layer 4. As a result, the off-leakage characteristics and drain-lag characteristics can be improved.

[0095] 2. Second Embodiment A semiconductor device 1 according to a second embodiment of the present disclosure will be described with reference to Fig. 23. In the description of the second embodiment and subsequent embodiments, components that are the same as or substantially the same as components in the first embodiment are denoted by the same reference numerals, and duplicated descriptions will be omitted.

[0096] [Configuration of Semiconductor Device 1 and SBJ-HEMT 2] Figure 23 shows an example of an enlarged cross-sectional configuration of a main part of the semiconductor device 1 according to the second embodiment and the SBJ-HEMT 2 mounted thereon. As shown in Figure 23, in the SBJ-HEMT 2, a specific processing layer 46 is disposed on the surface of the compound semiconductor layer 4 within the gate through-hole 6H. This will be explained in detail.

[0097] The specific treatment layer 46 is, for example, hydrogen (H ２) plasma treatment. The hydrogen plasma treatment is performed, for example, for 0.3 minutes or more and 3.0 minutes or less. The specific treatment layer 46 can increase the negative fixed charge density. That is, since the negative charges increase directly below the gate electrode 8 and at the interface with the carrier capture region 7, the energy band is lifted, and the effect of lowering the carrier concentration (electron concentration Ns) of the two-dimensional electron gas 43 is enhanced. As a result, the depletion layer is more likely to extend during off-state operation, and the electric field relaxation effect is enhanced.

[0098] The specific processing layer 46 is also formed on the source region side, but is formed in a very small area, which effectively prevents an increase in on-resistance Ron and a decrease in drain current Id.

[0099] The specific processing layer 46 is formed after the gate through-hole 6H shown in FIG. 22 is formed in the method for manufacturing the semiconductor device 1 according to the first embodiment.

[0100] The specific treatment layer 46 may also be formed by a treatment that includes negative ions such as fluorine (F) or chlorine (Cl).

[0101] The other components are the same as or substantially the same as the components of the semiconductor device 1 and SBJ-HEMT 2 according to the first embodiment, and therefore will not be described here.

[0102] [Operational Effects] As described above, according to the semiconductor device 1 of the second embodiment, it is possible to obtain operational effects similar to those obtained by the semiconductor device 1 of the first embodiment.

[0103] 23, the semiconductor device 1 and the SBJ-HEMT 2 include a special processing layer 46. The special processing layer 46 can increase negative charges, thereby more effectively suppressing off-leakage.

[0104] 3. Third Embodiment A semiconductor device 1 according to a third embodiment of the present disclosure will be described with reference to FIG.

[0105] [Configuration of semiconductor device 1 and SBJ-HEMT 2] Figure 24 shows an example of an enlarged cross-sectional configuration of a main part of the semiconductor device 1 according to the third embodiment and the SBJ-HEMT 2 mounted thereon. As shown in Figure 24, in the SBJ-HEMT 2, a trap rich region 72 is disposed in a cavity 71, and a carrier capture region 7 is constructed including the interface between the compound semiconductor layer 4 and the trap rich region 72. This will be explained in detail.

[0106] The trap rich region 72 is formed of a material with many carrier traps (here, electron traps). The trap rich region 72 is formed of, for example, HfO ２ The trap rich region 72 may also be formed from a photosensitive resin material having a low dielectric constant (low-k).

[0107] In the SBJ-HEMT 2, a thin insulating film that does not impair the Schottky barrier junction may be formed between the gate electrode 8 and the compound semiconductor layer 4.

[0108] The other components are the same as or substantially the same as the components of the semiconductor device 1 and SBJ-HEMT 2 according to the first or second embodiment, and therefore a description thereof will be omitted here.

[0109] [Operational Effects] As described above, according to the semiconductor device 1 of the third embodiment, it is possible to obtain operational effects similar to those obtained by the semiconductor device 1 of the first embodiment.

[0110] 4. Fourth Embodiment A semiconductor device 1 according to a fourth embodiment of the present disclosure will be described with reference to FIG.

[0111] [Configuration of Semiconductor Device 1 and SBJ-HEMT 2] Figure 25 shows an example of an enlarged cross-sectional configuration of a main portion of the semiconductor device 1 according to the fourth embodiment and the SBJ-HEMT 2 mounted thereon. As shown in Figure 25, in the SBJ-HEMT 2, the carrier capture region 7 is disposed only on the drain region side. This makes it easier for the depletion layer to extend on the drain region side of the SBJ-HEMT 2. Furthermore, the SBJ-HEMT 2 effectively reduces the resistance on the source region side.

[0112] The other components are the same as or substantially the same as the components of the semiconductor device 1 and SBJ-HEMT 2 according to the first or second embodiment, and therefore a description thereof will be omitted here.

[0113] [Operational Effects] As described above, according to the semiconductor device 1 of the fourth embodiment, it is possible to obtain operational effects similar to those obtained by the semiconductor device 1 of the first embodiment.

[0114] Furthermore, in the SBJ-HEMT2, as shown in FIG. 25, the carrier capture region 7 is not disposed on the source region side, so that the resistance on the source region side can be effectively reduced.

[0115] 5. Fifth Embodiment A semiconductor device 1 according to a fifth embodiment of the present disclosure will be described with reference to FIG.

[0116] [Configurations of the Semiconductor Device 1 and the SBJ-HEMT 2] Figure 26 shows an example of an enlarged cross-sectional configuration of a main portion of the semiconductor device 1 according to the fifth embodiment and the SBJ-HEMT 2 mounted thereon. As shown in Figure 26, the SBJ-HEMT 2 includes a trap rich region 73 in a portion of the inner wall of the gate through-hole 6H on the compound semiconductor layer 4 side, and a carrier capture region 7 is constructed including the interface between the compound semiconductor layer 4 and the trap rich region 73. The trap rich region 73 is formed as a side spacer structure. Furthermore, the trap rich region 73 is formed, for example, from the same material as the trap rich region 72 according to the third embodiment described above.

[0117] The other components are the same as or substantially the same as the components of the semiconductor device 1 and SBJ-HEMT 2 according to the first or second embodiment, and therefore a description thereof will be omitted here.

[0118] [Operational Effects] As described above, according to the semiconductor device 1 of the fifth embodiment, it is possible to obtain operational effects similar to those obtained by the semiconductor device 1 of the first embodiment.

[0119] 6. Sixth Embodiment A semiconductor module 100 according to a sixth embodiment of the present disclosure will be described with reference to Fig. 27. Fig. 27 shows a schematic structure of the semiconductor module 100 according to the sixth embodiment.

[0120] [Configuration of Semiconductor Module 100] The semiconductor module 100 according to the sixth embodiment is an antenna-integrated module in which, for example, edge antennas 101 arranged in an array and front-end components are mounted as a single module on a substrate 110. The front-end components include a switch 102, a low-noise amplifier 103, a band-pass filter 104, and a power amplifier 105. The semiconductor module 100 can be used, for example, as a transceiver for communications.

[0121] The semiconductor module 100 includes the semiconductor device 1 according to any one of the first to fifth embodiments as transistors constituting, for example, a switch 102, a low-noise amplifier 103, or a power amplifier 105.

[0122] [Operation and Effect] The semiconductor module 100 according to the sixth embodiment includes the semiconductor device 1, and therefore can effectively suppress off-freak in wireless communication.

[0123] 7. Seventh Embodiment A wireless communication device (electronic device) 300 according to a seventh embodiment of the present disclosure will be described with reference to Fig. 28. Fig. 28 shows a schematic block configuration of the wireless communication device 300 according to the seventh embodiment.

[0124] [Configuration of Wireless Communication Device 300] The wireless communication device 300 according to the seventh embodiment includes an antenna ANT, an antenna switch circuit 301, a high-power amplifier HPA, a radio frequency integrated circuit RFIC (Radio Frequency Integrated Circuit), a baseband unit BB, an audio output unit MIC, a data output unit DT, and an interface unit I / F. The interface unit I / F includes, for example, a wireless local area network (W-LAN) and Bluetooth (registered trademark). The wireless communication device 300 is, for example, a mobile phone system having multiple functions such as voice and data communication and LAN connection.

[0125] The wireless communication device 300 includes a semiconductor device 1 according to any one of the first to fifth embodiments as transistors constituting an antenna switch circuit 301, a high power amplifier HPA, a radio frequency integrated circuit RFIC, or a baseband section BB.

[0126] [Operation and Effect] The wireless communication device 300 according to the seventh embodiment includes the semiconductor device 1, and therefore can effectively suppress off-leakage in wireless communication.

[0127] 8. Other Embodiments The present technology is not limited to the above-described embodiments and can be modified in various ways without departing from the spirit and scope of the present technology. For example, a semiconductor device may be constructed by combining two or more semiconductor devices according to any of the first to fifth embodiments. In the above-described embodiments, the semiconductor is formed of a GaN-based compound semiconductor material. In the present technology, the semiconductor may be formed of a GaAs-based compound semiconductor material.

[0128] As described above, the SBJ-HEMT according to the first embodiment of the present disclosure includes a compound semiconductor layer, an insulator, a gate electrode, and a carrier capture region. The compound semiconductor layer has a barrier layer. The insulator is disposed in the compound semiconductor layer and has a gate through-hole. The gate electrode is embedded in the gate through-hole. The carrier capture region is disposed at least at one end of the gate electrode in the gate length direction, and the trap density of carriers captured at the interface with the compound semiconductor layer is higher than the trap density of carriers captured at the interface between the compound semiconductor layer and the insulator. In an SBJ-HEMT configured in this manner, the carrier capture region 7 facilitates the expansion of the depletion layer during off-operation, thereby realizing electric field relaxation, thereby improving high-temperature reverse bias characteristics and effectively suppressing off-leakage.

[0129] In the SBJ-HEMT according to the first embodiment, the carrier capture region includes a cavity surrounded by the compound semiconductor layer, the gate electrode, and the insulator, which makes it possible to easily construct the carrier capture region.

[0130] In the SBJ-HEMT according to the second embodiment of the present disclosure, the carrier capture region is disposed on the drain region side in the SBJ-HEMT according to the first embodiment, which makes it possible to effectively suppress off-leakage on the drain region side of the SBJ-HEMT and effectively reduce on-resistance on the source region side.

[0131] In the SBJ-HEMT according to the third embodiment of the present disclosure, the carrier capture regions are disposed on both the source region side and the drain region side in the SBJ-HEMT according to the first embodiment. The SBJ-HEMT configured in this manner can achieve the same effects as those achieved by the SBJ-HEMT according to the first embodiment.

[0132] A semiconductor device according to a fourth embodiment of the present disclosure includes an SBJ-HEMT, the SBJ-HEMT including a compound semiconductor layer having a barrier layer, an insulator disposed in the compound semiconductor layer and having a gate through-hole, a gate electrode embedded in the gate through-hole, and a carrier capture region disposed at least at one end of the gate electrode in the gate length direction, the carrier capture region having a higher trap density at the interface with the compound semiconductor layer than the trap density at the interface between the compound semiconductor layer and the insulator. A semiconductor device configured in this manner can effectively suppress off-leakage of the SBJ-HEMT.

[0133] A semiconductor module according to a fifth embodiment of the present disclosure includes an SBJ-HEMT, the SBJ-HEMT including a compound semiconductor layer having a barrier layer, an insulator disposed in the compound semiconductor layer and having a gate through-hole, a gate electrode embedded in the gate through-hole, and a carrier capture region disposed at least at one end of the gate electrode in the gate length direction, the carrier capture region having a higher trap density at the interface with the compound semiconductor layer than the trap density at the interface between the compound semiconductor layer and the insulator. A semiconductor module configured in this manner can effectively suppress off-leakage of the SBJ-HEMT.

[0134] An electronic device according to a sixth embodiment of the present disclosure includes an SBJ-HEMT, the SBJ-HEMT including a compound semiconductor layer having a barrier layer, an insulator disposed in the compound semiconductor layer and having a gate through-hole, a gate electrode embedded in the gate through-hole, and a carrier capture region disposed at least at one end of the gate electrode in the gate length direction, the carrier capture region having a higher trap density at the interface with the compound semiconductor layer than the trap density at the interface between the compound semiconductor layer and the insulator. With this configuration, the off-leakage of the SBJ-HEMT can be effectively suppressed.

[0135] <Configuration of the Present Technology> The present technology has the following configuration: According to the present technology having the following configuration, it is possible to effectively suppress off-leakage in an SBJ-HEMT, a semiconductor device, a semiconductor module, and an electronic device.

[0136] (1) A Schottky barrier junction type high electron mobility transistor comprising: a compound semiconductor layer having a barrier layer; an insulator disposed on the compound semiconductor layer and having a gate through hole or a gate via hole; a gate electrode embedded in the gate through hole; and a carrier trapping region disposed on at least one end part of the gate electrode in a gate length direction, the carrier trapping region having a higher trap density of carriers trapped at an interface with the compound semiconductor layer than a trap density of carriers trapped at an interface between the compound semiconductor layer and the insulator. (2) The Schottky barrier junction type high electron mobility transistor according to (1), wherein the trap density of the carrier trapping region is 1.5 times or more the trap density at the interface between the compound semiconductor layer and the insulator. (3) The Schottky barrier junction high electron mobility transistor according to (1) or (2), wherein the carrier capture region is in contact with at least one end of the gate electrode and is formed to a length of 1.5 nm to 15.0 nm in the gate length direction. (4) The Schottky barrier junction high electron mobility transistor according to any one of (1) to (3), wherein the carrier capture region is formed to a height of 5 nm or less from the compound semiconductor layer.(5) The Schottky barrier junction high electron mobility transistor according to any one of (1) to (4), wherein the insulator comprises: a first insulating film formed in contact with the compound semiconductor layer; and a second insulating film formed on the opposite side of the first insulating film from the compound semiconductor layer and having an etching selectivity ratio different from that of the first insulating film. (6) The Schottky barrier junction high electron mobility transistor according to (5), wherein the first insulating film is formed to a thickness of 1.5 nm to 5.0 nm. (7) The Schottky barrier junction high electron mobility transistor according to (5) or (6), wherein the second insulating film is formed to a thickness of 10 nm to 150 nm. (8) The Schottky barrier junction high electron mobility transistor according to any one of (1) to (5), wherein the carrier capture region comprises a cavity or a void surrounded by the compound semiconductor layer, the gate electrode, and the insulator. (9) The Schottky barrier junction high electron mobility transistor according to any one of (5) to (8), wherein the carrier capture region is formed by selectively side-etching the first insulating film with respect to the compound semiconductor layer and the second insulating film. (10) The Schottky barrier junction high electron mobility transistor according to any one of (1) to (9), wherein the carrier capture region is disposed on the drain region side. (11) The Schottky barrier junction high electron mobility transistor according to any one of (1) to (9), wherein the carrier capture region is disposed on each of the source region side and the drain region side. (12) The Schottky barrier junction high electron mobility transistor according to any one of (1) to (11), wherein the compound semiconductor layer is a Group III nitride semiconductor layer containing one or more selected from Ga, In, and Al. (13) The Schottky barrier junction high electron mobility transistor according to any one of (5) to (7) or (9), wherein the first insulating film is a film containing Al or a film containing an oxide.(14) The first insulating film is made of Al. ２ O ３ or a film containing HfO ２(15) The Schottky barrier junction high electron mobility transistor according to any one of (5) to (7), (9), and (13), wherein the second insulating film is a film containing nitride. (16) The Schottky barrier junction high electron mobility transistor according to any one of (5) to (7), (9), and (13) to (15), wherein the second insulating film is a film containing SiN. (17) A semiconductor device comprising a Schottky barrier junction high electron mobility transistor, the Schottky barrier junction high electron mobility transistor comprising: a compound semiconductor layer having a barrier layer; an insulator disposed in the compound semiconductor layer and having a gate through-hole; a gate electrode embedded in the gate through-hole; and a carrier capture region disposed at least at one end of the gate electrode in a gate length direction, the carrier capture region having a higher trap density at an interface with the compound semiconductor layer than a trap density of carriers captured at an interface between the compound semiconductor layer and the insulator. (18) A semiconductor module comprising a semiconductor device having a Schottky barrier junction high electron mobility transistor, the Schottky barrier junction high electron mobility transistor comprising: a compound semiconductor layer having a barrier layer; an insulator disposed in the compound semiconductor layer and having a gate through-hole; a gate electrode embedded in the gate through-hole; and a carrier capture region disposed at least at one end of the gate electrode in a gate length direction, the carrier capture region having a higher trap density of carriers captured at an interface with the compound semiconductor layer than a trap density of carriers captured at an interface between the compound semiconductor layer and the insulator.(19) An electronic equipment comprising a semiconductor device having a Schottky barrier junction high electron mobility transistor, the Schottky barrier junction high electron mobility transistor comprising: a compound semiconductor layer having a barrier layer; an insulator disposed in the compound semiconductor layer and having a gate through-hole; a gate electrode embedded in the gate through-hole; and a carrier capture region disposed at least at one end of the gate electrode in a gate length direction, the carrier capture region having a higher trap density of carriers captured at an interface with the compound semiconductor layer than a trap density of carriers captured at an interface between the compound semiconductor layer and the insulator.

[0137] This application claims priority based on Japanese Patent Application No. 2024-153905, filed on September 6, 2024, in the Japan Patent Office, the entire contents of which are incorporated herein by reference.

[0138] Those skilled in the art will recognize that various modifications, combinations, subcombinations, and variations may occur depending on design requirements and other factors, and are intended to be within the scope of the appended claims and their equivalents.

Claims

1. A Schottky barrier junction high electron mobility transistor comprising: a compound semiconductor layer having a barrier layer; an insulator disposed on the compound semiconductor layer and having a gate through-hole; a gate electrode embedded in the gate through-hole; and a carrier capture region disposed at least at one end of the gate electrode in a gate length direction, the carrier capture region having a higher trap density at the interface with the compound semiconductor layer than the trap density of carriers captured at the interface between the compound semiconductor layer and the insulator.

2. A Schottky barrier junction high electron mobility transistor according to claim 1, wherein the trap density of said carrier capture region is 1.5 times or more the trap density at the interface between said compound semiconductor layer and said insulator.

3. A Schottky barrier junction high electron mobility transistor according to claim 1, wherein the carrier capture region is in contact with at least one end of the gate electrode and is formed to have a length of 1.5 nm to 15.0 nm in the gate length direction.

4. The Schottky barrier junction high electron mobility transistor according to claim 1, wherein the carrier capture region is formed at a height of 5 nm or less from the compound semiconductor layer.

5. The Schottky barrier junction high electron mobility transistor according to claim 1, wherein the insulator comprises a first insulating film formed in contact with the compound semiconductor layer, and a second insulating film formed on the opposite side of the first insulating film from the compound semiconductor layer and having an etching selectivity different from that of the first insulating film.

6. The Schottky barrier junction high electron mobility transistor according to claim 5, wherein the first insulating film is formed to a thickness of 1.5 nm or more and 5.0 nm or less.

7. The Schottky barrier junction high electron mobility transistor according to claim 5, wherein the second insulating film is formed to a thickness of 10 nm or more and 150 nm or less.

8. The Schottky barrier junction high electron mobility transistor according to claim 1, wherein the carrier capture region comprises a cavity surrounded by the compound semiconductor layer, the gate electrode, and the insulator.

9. A Schottky barrier junction high electron mobility transistor according to claim 5, wherein the carrier capture region is formed by selectively side-etching the first insulating film relative to the compound semiconductor layer and the second insulating film.

10. A Schottky barrier junction high electron mobility transistor according to claim 1, wherein said carrier capture region is disposed on the drain region side.

11. The Schottky barrier junction high electron mobility transistor according to claim 1, wherein the carrier capture region is disposed on each of the source region side and the drain region side.

12. The Schottky barrier junction high electron mobility transistor according to claim 1, wherein the compound semiconductor layer is a Group III nitride semiconductor layer containing one or more elements selected from the group consisting of Ga, In, and Al.

13. The Schottky barrier junction high electron mobility transistor according to claim 5, wherein the first insulating film is a film containing Al or a film containing an oxide.

14. The first insulating film is Al ２ O ３ or a film containing HfO ２ 6. The Schottky barrier junction high electron mobility transistor according to claim 5, wherein the film comprises:

15. The Schottky barrier junction high electron mobility transistor according to claim 5, wherein the second insulating film is a film containing nitride.

16. The Schottky barrier junction high electron mobility transistor according to claim 5, wherein the second insulating film is a film containing SiN.

17. A semiconductor device comprising a Schottky barrier junction high electron mobility transistor, the Schottky barrier junction high electron mobility transistor comprising: a compound semiconductor layer having a barrier layer; an insulator disposed on the compound semiconductor layer and having a gate through-hole; a gate electrode embedded in the gate through-hole; and a carrier capture region disposed at least at one end of the gate electrode in a gate length direction, the carrier capture region having a higher trap density of carriers captured at an interface with the compound semiconductor layer than a trap density of carriers captured at an interface between the compound semiconductor layer and the insulator.

18. A semiconductor module comprising a semiconductor device having a Schottky barrier junction high electron mobility transistor, the Schottky barrier junction high electron mobility transistor comprising: a compound semiconductor layer having a barrier layer; an insulator disposed in the compound semiconductor layer and having a gate through-hole; a gate electrode embedded in the gate through-hole; and a carrier capture region disposed at least at one end of the gate electrode in a gate length direction, the carrier capture region having a higher trap density at the interface with the compound semiconductor layer than the trap density of carriers captured at the interface between the compound semiconductor layer and the insulator.

19. An electronic device comprising a semiconductor device having a Schottky barrier junction high electron mobility transistor, the Schottky barrier junction high electron mobility transistor comprising: a compound semiconductor layer having a barrier layer; an insulator disposed in the compound semiconductor layer and having a gate through-hole; a gate electrode embedded in the gate through-hole; and a carrier capture region disposed at least at one end of the gate electrode in the gate length direction, the carrier capture region having a higher trap density at the interface with the compound semiconductor layer than the trap density of carriers captured at the interface between the compound semiconductor layer and the insulator.

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