Semiconductor device

Abstract

Provided is a semiconductor device comprising a first-conductivity-type high-concentration region that is provided in contact with a first gate trench part, is disposed between a base region and a drift region so as to be in contact with the drift region, and has a doping concentration higher than that of the drift region. The high-concentration region includes a decrease region in which the doping concentration monotonously decreases from a position where the doping concentration exhibits a maximum value toward the drift region in the depth direction of a semiconductor substrate. The decrease region includes a first position at which the doping concentration is 1 × 1016 / cm3. The distance in the depth direction between the first position and the lower end of the first gate trench part is 2.5 μm or less.

Description

Semiconductor Devices

[0001] The present invention relates to a semiconductor device.

[0002] Conventionally, a configuration in which a high-concentration n-type region is provided below a base region is known (see, for example, Patent Documents 1 to 4). Patent Document 1: International Publication No. 2023 / 042638 Patent Document 2: Japanese Patent Application Laid-Open No. 2019-186311 Patent Document 3: Japanese Patent Application Laid-Open No. 2023-081724 Patent Document 4: Japanese Patent Application Laid-Open No. 2023-120081 Problem to be solved

[0003] Displacement current in a gate trench portion of a semiconductor device is suppressed. General disclosure

[0004] In order to solve the above problem, one aspect of the present invention provides a semiconductor device provided on a semiconductor substrate having an upper surface. The semiconductor device may include a drift region of a first conductivity type provided inside the semiconductor substrate. Any of the semiconductor devices may include a first gate trench portion provided from the upper surface of the semiconductor substrate into the semiconductor substrate. Any of the semiconductor devices may include a base region of a second conductivity type provided in contact with the first gate trench portion. Any of the semiconductor devices may include a high concentration region of the first conductivity type provided in contact with the first gate trench portion, disposed between the base region and the drift region in contact with the drift region, and having a doping concentration higher than that of the drift region. In any of the semiconductor devices, the high concentration region may include a decrease region in which the doping concentration monotonically decreases from a position where the doping concentration has a maximum value toward the drift region in the depth direction of the semiconductor substrate. In any of the semiconductor devices, the decrease region may include a doping concentration of 1×10 １６ / cm ３ In any of the above semiconductor devices, a distance in the depth direction between the first position and a lower end of the first gate trench portion may be 2.5 μm or less.

[0005] In any of the above semiconductor devices, the maximum value of the doping concentration in the high concentration region is 1×10１６ / cm ３ That's it, 1 x 10 １７ / cm ３ It may be the following:

[0006] In any of the above semiconductor devices, the distance in the depth direction from a second position where the doping concentration in the high-concentration region has a maximum value to the drift region may be equal to or greater than the distance from the second position to the base region.

[0007] In any of the above semiconductor devices, the distance between the first position and a lower end of the first gate trench portion in the depth direction may be 1 μm or less.

[0008] In any of the above semiconductor devices, the distance in the depth direction between the first position and the lower end of the first gate trench portion may be 0.1% or more and 20% or less of the length of the first gate trench portion.

[0009] In any one of the semiconductor devices described above, the dose of the first conductivity type dopant in the high concentration region is 6×10 １２ / cm ２ That's it, 1.8 x 10 １３ / cm ２ It may be the following:

[0010] In any of the above semiconductor devices, a dose of the first conductivity type dopant in the high concentration region from the first position to a lower end of the high concentration region may be 0.1% or more and 10% or less of a dose of the first conductivity type dopant from an upper end to a lower end of the high concentration region.

[0011] In any of the above semiconductor devices, the first gate trench portion may be provided extending in a first direction on the upper surface of the semiconductor substrate. In any of the above semiconductor devices, a wall portion of the first gate trench portion in a cross section perpendicular to the first direction may include a curved lower portion that includes a lower end of the first gate trench portion. In any of the above semiconductor devices, the wall portion may include a linear upper portion that extends from the lower portion toward the upper surface of the semiconductor substrate. In any of the above semiconductor devices, the first position may be provided in a depth range facing the lower portion.

[0012] In any of the above semiconductor devices, the first position may be provided at the same depth as a lower end of the first gate trench portion.

[0013] Any of the above semiconductor devices may have a second conductivity type lower end region provided in contact with a lower end of the first gate trench portion.

[0014] In any of the above semiconductor devices, a lower end of the first gate trench portion may be in contact with a region of the first conductivity type.

[0015] In any of the above semiconductor devices, when a current of 0.1% to 10% of the rated current of the semiconductor device flows during turn-on, the potential of the high concentration region may be higher than a threshold voltage at which the semiconductor device turns on.

[0016] In any of the above semiconductor devices, the high concentration region may be in contact with the base region.

[0017] In any of the above semiconductor devices, an intermediate region of the first conductivity type having the same doping concentration as the drift region may be provided between the high concentration region and the base region.

[0018] Any of the above semiconductor devices may include a second gate trench portion provided from the top surface of the semiconductor substrate into the semiconductor substrate and arranged adjacent to the first gate trench portion. Any of the above semiconductor devices may include a first dummy trench portion provided from the top surface of the semiconductor substrate into the semiconductor substrate and arranged adjacent to the second gate trench portion on the opposite side to the first gate trench portion. Any of the above semiconductor devices may include a first mesa portion sandwiched between the first gate trench portion and the second gate trench portion within the semiconductor substrate. Any of the above semiconductor devices may include a second mesa portion sandwiched between the second gate trench portion and the first dummy trench portion within the semiconductor substrate. Any of the above semiconductor devices may include a top electrode arranged above the top surface of the semiconductor substrate. Any of the above semiconductor devices may include an interlayer insulating film provided between the semiconductor substrate and the top electrode and having a contact hole connecting the semiconductor substrate and the top electrode. In any of the above semiconductor devices, a first contact area where the semiconductor substrate and the upper surface electrode contact in the first mesa portion may be larger than a second contact area where the semiconductor substrate and the upper surface electrode contact in the second mesa portion.

[0019] Any of the above semiconductor devices may include a second dummy trench portion provided inside the semiconductor substrate from the top surface of the semiconductor substrate and arranged adjacent to the first dummy trench portion on the opposite side to the second gate trench portion. Any of the above semiconductor devices may include a third mesa portion sandwiched between the first dummy trench portion and the second dummy trench portion inside the semiconductor substrate. Any of the above semiconductor devices may include a third contact area at the third mesa portion where the semiconductor substrate and the top surface electrode contact each other, which is smaller than the first contact area.

[0020] In any of the above semiconductor devices, the second mesa may have the high concentration region. In the third mesa of any of the above semiconductor devices, the high concentration region may not be provided between the base region and the drift region, or the high concentration region may be smaller than that in the channel mesa.

[0021] In any of the above semiconductor devices, the third mesa portion may not be provided with the high concentration region.

[0022] In any of the above semiconductor devices, the second contact area may be equal to or less than half the first contact area, and the third contact area may be equal to or less than half the first contact area.

[0023] Any of the above semiconductor devices may include a third dummy trench portion provided inside the semiconductor substrate from the top surface of the semiconductor substrate and arranged adjacent to the second dummy trench portion on the opposite side to the first dummy trench portion. Any of the above semiconductor devices may include a fourth mesa portion sandwiched between the second dummy trench portion and the third dummy trench portion inside the semiconductor substrate. Any of the above semiconductor devices may include a fourth contact area where the semiconductor substrate and the top surface electrode contact at the fourth mesa portion, which is larger than both the second contact area and the third contact area.

[0024] Any of the above semiconductor devices may include a first dummy trench portion provided from the top surface of the semiconductor substrate into the semiconductor substrate and arranged adjacent to the gate trench portion. Any of the above semiconductor devices may include a second dummy trench portion provided from the top surface of the semiconductor substrate into the semiconductor substrate and arranged adjacent to the first dummy trench portion. Any of the above semiconductor devices may include a third mesa portion within the semiconductor substrate, sandwiched between the first dummy trench portion and the second dummy trench portion. Any of the above semiconductor devices may include a top electrode arranged above the top surface of the semiconductor substrate. Any of the above semiconductor devices may include an interlayer insulating film provided between the semiconductor substrate and the top electrode. In any of the above semiconductor devices, the interlayer insulating film may be provided with a first trench contact hole connecting the top electrode and the first dummy trench portion. In any of the above semiconductor devices, the interlayer insulating film may be provided with a second trench contact hole connecting the top electrode and the second dummy trench portion. In any of the above semiconductor devices, a mesa contact hole may be provided in the interlayer insulating film, connecting the top surface electrode and the third mesa portion. In any of the above semiconductor devices, the first dummy trench portion and the second dummy trench portion may be provided extending in a first direction on the top surface of the semiconductor substrate. In any of the above semiconductor devices, the mesa contact hole may not be arranged opposite either the first trench contact hole or the second trench contact hole in a second direction parallel to the top surface of the semiconductor substrate and perpendicular to the first direction.

[0025] In any of the above semiconductor devices, at least a portion of the first trench contact hole and at least a portion of the second trench contact hole may be disposed opposite each other in the second direction.

[0026] A second aspect of the present invention provides a semiconductor device provided on a semiconductor substrate having an upper surface. The semiconductor device may include an upper surface electrode provided above the upper surface of the semiconductor substrate. Any of the semiconductor devices may include a first conductivity type drift region provided inside the semiconductor substrate. Any of the semiconductor devices may include one or more gate trenches and a plurality of dummy trenches provided from the upper surface of the semiconductor substrate into the semiconductor substrate. Any of the semiconductor devices may include a channel mesa in contact with the gate trenches. Any of the semiconductor devices may include a dummy mesa sandwiched between two of the dummy trenches. In any of the semiconductor devices, the channel mesa and the dummy mesa may have a second conductivity type base region provided between the drift region and the upper surface of the semiconductor substrate. In any of the semiconductor devices, the channel mesa may include a first conductivity type emitter region provided between the base region and the upper surface of the semiconductor substrate and having a doping concentration higher than that of the drift region. In any of the above semiconductor devices, the channel mesa may have a high-concentration region of a first conductivity type provided between the base region and the drift region and having a doping concentration higher than that of the drift region. In the dummy mesa of any of the above semiconductor devices, the high-concentration region may not be provided between the base region and the drift region, or the high-concentration region may be smaller than that in the channel mesa. In any of the above semiconductor devices, the area of ​​a contact portion where the semiconductor substrate and the top electrode contact in the dummy mesa may be smaller than the area of ​​a contact portion where the semiconductor substrate and the top electrode contact in the channel mesa, or may be zero.

[0027] In any of the above semiconductor devices, a dummy mesa integral concentration obtained by integrating the doping concentration of the first conductivity type region from the depth position of the lower end of the base region to the depth position of the lower end of the dummy trench portion may be lower than a channel mesa integral concentration obtained by integrating the doping concentration of the first conductivity type region in the channel mesa portion from the depth position of the lower end of the base region to the depth position of the lower end of the gate trench portion.

[0028] In any of the above semiconductor devices, the drift region may be provided from the base region of the dummy mesa portion to a depth position of a lower end of the dummy trench portion.

[0029] In any of the above semiconductor devices, the base region of the dummy mesa portion may be provided deeper than the base region of the channel mesa portion.

[0030] In any of the above semiconductor devices, the area of ​​the high concentration region provided in one of the dummy mesa portions may be smaller than the area of ​​the high concentration region provided in one of the channel mesa portions when viewed from above.

[0031] In the dummy mesa portion of any of the above semiconductor devices, the high concentration region may be provided below the contact portion, and the high concentration region may not be provided in at least a part of the region that does not overlap with the contact portion.

[0032] The doping concentration of the second conductivity type region in contact with the upper surface electrode in the dummy mesa portion of any of the above semiconductor devices may be lower than the doping concentration of the second conductivity type region in contact with the upper surface electrode in the channel mesa portion.

[0033] In any of the above semiconductor devices, the channel mesa portion and the dummy mesa portion may be arranged side by side in a second direction. In any of the above semiconductor devices, the contact portion of the dummy mesa portion may be arranged facing the emitter region of the channel mesa portion in the second direction.

[0034] In any of the above semiconductor devices, the channel mesa portion and the dummy mesa portion may be arranged side by side in a second direction. In any of the above semiconductor devices, the contact portion of the dummy mesa portion may be arranged at a position not facing the emitter region of the channel mesa portion in the second direction.

[0035] Any of the above semiconductor devices may include a first dummy mesa portion and a second dummy mesa portion disposed farther from the channel mesa portion than the first dummy mesa portion, and an area of ​​the contact portion in the first dummy mesa portion may be smaller than an area of ​​the contact portion in the second dummy mesa portion.

[0036] In any of the above semiconductor devices, the channel mesa may be sandwiched between the gate trench and the dummy trench, and the dummy mesa may be a mesa adjacent to the channel mesa.

[0037] Any of the above semiconductor devices may include a first mesa portion sandwiched between two of the gate trench portions. A contact area between the semiconductor substrate and the upper surface electrode in the first mesa portion of any of the above semiconductor devices may be smaller than a contact area between the semiconductor substrate and the upper surface electrode in the channel mesa portion, or the first mesa portion may not be in contact with the upper surface electrode.

[0038] In any of the above semiconductor devices, the first mesa portion may have the base region and the high concentration region.

[0039] In any of the semiconductor devices described above, the first mesa portion may have the base region. In the first mesa portion of any of the semiconductor devices described above, the high concentration region may not be provided between the base region and the drift region, or the high concentration region may be smaller than that in the channel mesa portion.

[0040] In any of the above semiconductor devices, the dummy mesa portion may not be in contact with the upper surface electrode.

[0041] The above summary of the invention does not list all of the necessary features of the present invention. In addition, subcombinations of these features may also constitute inventions.

[0042] 10 is a cross-sectional view showing an example of a semiconductor device 100 according to an embodiment of the present invention. It is an example of a top view of the semiconductor device 100 shown in FIG. 1. It is an enlarged view of the vicinity of the gate trench portion 40. It is a diagram showing an example of a doping concentration distribution along the line A-A in FIG. 3. It is a diagram explaining an example of an operation at the time of turn-on of a semiconductor device according to a comparative example. It is a diagram explaining an example of an operation at the time of turn-on of a semiconductor device 100 according to an example. It is a diagram showing the relationship between the distance d1 (see FIG. 4) and the peak value of the rate of change dV / dt of voltage during reverse recovery of a diode mesa portion. It is a diagram showing another structural example of the mesa portion 61 and the mesa portion 62. It is a diagram showing an example of a doping concentration distribution along the line B-B in FIG. 8. It is a diagram showing another structural example of the mesa portion 61 and the mesa portion 62. It is a diagram showing an example of a doping concentration distribution along the line C-C in FIG. 10. It is a diagram showing another structural example of the mesa portion 61 and the mesa portion 62. It is a diagram showing an example of a doping concentration distribution along the line D-D in FIG. 12. It is a diagram showing another structural example of the mesa portion 61 and the mesa portion 62. 20 is a diagram showing an example of the distribution of doping concentrations along the line E-E of FIG. 14. FIG. 21 is a diagram showing another example of the structure of the mesa portion 61 and the mesa portion 62. FIG. 22 is a diagram showing an example of the distribution of doping concentrations along the line F-F of FIG. 16. FIG. 23 is a diagram showing another example of the structure of the mesa portion 61 and the mesa portion 62. FIG. 24 is a diagram showing an example of the distribution of doping concentrations along the line G-G of FIG. 18. FIG. 25 is a diagram showing another example of the structure of the mesa portion 61 and the mesa portion 62. FIG. 26 is a diagram showing an example of the distribution of doping concentrations along the line H-H of FIG. 20. FIG. 27 is a cross-sectional view showing another example of the semiconductor device 100. FIG. 28 is an example of a top view of the semiconductor device 100 described in FIG. 22. FIG. 29 is an example of a top view of the semiconductor device 100 described in FIG. 22. FIG. 29 is a diagram showing another example of the structure of the region shown in FIG. 24. FIG. 29 is a diagram showing the relationship between the collector-emitter voltage Vce(sat) in a saturated state and the turn-off loss Eoff according to the comparative example and the example. FIG. 29 is a diagram showing the relationship between dV / dt_peak and the gate resistance Rg according to the comparative example and the example. 29 is a diagram showing the relationship between dV / dt_peak and Eon+Err according to a comparative example and an example. FIG. 29 is a top view showing another example of the semiconductor device 100. FIG. 29 is a diagram showing an example of the II cross section of FIG. 29. FIG. 29 is a diagram showing an example of the JJ cross section of FIG. 29. FIG. 30 is a cross-sectional view showing another example of the semiconductor device 100.FIG. 33 is an example of a top view of the semiconductor device 100 described in FIG. 32. FIG. 34 is another example of a top view of the semiconductor device 100 described in FIG. 32. FIG. 35 is another example of a top view of the semiconductor device 100 described in FIG. 32. FIG. 36 is a cross-sectional view showing another example of the semiconductor device 100. FIG. 37 is a cross-sectional view showing another example of the semiconductor device 100. FIG. 38 is a cross-sectional view showing another example of the semiconductor device 100. FIG. 39 is a cross-sectional view showing another example of the semiconductor device 100. FIG. 40 is a top view showing another example of the second mesa portion 60-2 and the third mesa portion 60-3. FIG. 41 is a diagram showing an example of a reverse recovery waveform of a diode mesa portion during low current operation.

[0043] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention as claimed. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0044] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the directions when the semiconductor device is mounted.

[0045] In this specification, technical matters may be explained using orthogonal coordinate axes of the X-axis, Y-axis, and Z-axis. The orthogonal coordinate axes merely identify the relative positions of components and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is described without specifying positive or negative, it means a direction parallel to the +Z-axis and -Z-axis.

[0046] In this specification, orthogonal axes parallel to the upper and lower surfaces of the semiconductor substrate are referred to as the X-axis and Y-axis. Furthermore, an axis perpendicular to the upper and lower surfaces of the semiconductor substrate is referred to as the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. Furthermore, in this specification, the direction parallel to the upper and lower surfaces of the semiconductor substrate, including the X-axis and Y-axis, may be referred to as the horizontal direction.

[0047] The region from the center of the semiconductor substrate in the depth direction to the top surface of the semiconductor substrate may be referred to as the top surface side. Similarly, the region from the center of the semiconductor substrate in the depth direction to the bottom surface of the semiconductor substrate may be referred to as the bottom surface side.

[0048] In this specification, when we say "same" or "equal," it may also include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0049] In this specification, the conductivity type of a doped region doped with impurities is described as p-type or n-type. Sometimes, n-type conductivity is referred to as the first conductivity type and p-type conductivity is referred to as the second conductivity type, but the corresponding conductivity types may be reversed. In this specification, impurities may particularly refer to either n-type donors or p-type acceptors, and may be referred to as dopants. In this specification, doping refers to introducing donors or acceptors into a semiconductor substrate to form a semiconductor exhibiting n-type conductivity or a semiconductor exhibiting p-type conductivity.

[0050] In this specification, the doping concentration means the concentration of donors or acceptors in a thermal equilibrium state. In this specification, the net doping concentration means the net concentration obtained by adding together the donor concentration as the concentration of positive ions and the acceptor concentration as the concentration of negative ions, taking into account the polarity of the charge. As an example, the donor concentration is N Ｄ , acceptor concentration is N Ａ Then, the net doping concentration at any position is N Ｄ -N Ａ In this specification, the net doping concentration may be simply referred to as the doping concentration.

[0051] In this specification, when p+ type or n+ type is described, it means that the doping concentration is higher than that of p type or n type, and when p- type or n- type is described, it means that the doping concentration is lower than that of p type or n type. Furthermore, when p++ type or n++ type is described in this specification, it means that the doping concentration is higher than that of p+ type or n+ type. The unit system in this specification is the SI unit system unless otherwise specified. The unit of length may be expressed in cm, but various calculations may be performed after converting to meters (m).

[0052] FIG. 1 is a cross-sectional view showing an example of a semiconductor device 100 according to an embodiment of the present invention. The semiconductor device 100 includes an insulated gate bipolar transistor (IGBT). The semiconductor device 100 may also include a diode connected in anti-parallel to the IGBT. In FIG. 1, only some components of the semiconductor device 100 are shown, and some other components are omitted.

[0053] The semiconductor device 100 is provided on a semiconductor substrate 10. The semiconductor substrate 10 is a substrate formed of a semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate. The semiconductor substrate 10 may be a silicon carbide substrate, a gallium nitride substrate, or a substrate made of another semiconductor material. The semiconductor substrate 10 has an upper surface 21 and a lower surface. FIG. 1 shows the configuration of the upper surface 21 side of the semiconductor substrate 10, and does not illustrate the lower surface side. The semiconductor device 100 includes the semiconductor substrate 10, an interlayer insulating film 38, and an emitter electrode 52.

[0054] The interlayer insulating film 38 is provided between the upper surface 21 of the semiconductor substrate 10 and the emitter electrode 52. The interlayer insulating film 38 is a film including at least one layer of an insulating film such as silicate glass doped with impurities such as boron or phosphorus, a thermal oxide film, and other insulating films. In this example, a contact hole 54 is formed in the interlayer insulating film 38. The contact hole 54 is a through-hole provided to penetrate the interlayer insulating film 38.

[0055] The emitter electrode 52 is an example of an upper surface electrode provided above the upper surface 21 of the semiconductor substrate 10. The emitter electrode 52 in this example is provided above the interlayer insulating film 38. The emitter electrode 52 is connected to the upper surface 21 of the semiconductor substrate 10 via a contact hole 54. The emitter electrode 52 is, for example, an aluminum-silicon alloy. The emitter electrode 52 may have a multilayer structure of a barrier metal such as titanium or titanium nitride and an aluminum-silicon alloy. Furthermore, the contact hole 54 may have a plug formed by embedding tungsten, copper, or the like so as to contact the barrier metal and aluminum, or the like. Furthermore, the emitter electrode 52 may have nickel, gold, or the like laminated on top of a region formed of aluminum, or the like.

[0056] An n-type drift region 18 is provided inside the semiconductor substrate 10. The drift region 18 may be a region that remains without doping the semiconductor substrate 10. Although not shown, a collector region of a second conductivity type is provided on the lower surface side of the semiconductor substrate 10 in contact with the lower surface. A collector electrode is also provided in contact with the collector region. A field stop layer (FS layer) of a first conductivity type having a higher impurity concentration than the drift region 18 may be provided between the drift region 18 and the collector region. The drift region 18 may be a region having a constant doping concentration.

[0057] The semiconductor substrate 10 has a plurality of trenches extending from the upper surface 21 of the semiconductor substrate 10 toward the interior thereof. The trenches may reach the drift region 18 within the semiconductor substrate 10. The plurality of trenches may include one or more gate trenches 40 and one or more dummy trenches 30. The gate trenches 40 are trenches to which a gate voltage is applied. The dummy trenches 30 are connected to an emitter electrode 52 in another cross section. In FIG. 1 and subsequent figures, the gate trenches 40 are labeled G and the dummy trenches 30 are labeled E.

[0058] The trench portion in this example includes a plurality of gate trench portions 40 and a plurality of dummy trench portions 30. Each trench portion extends in a first direction (Y-axis direction). The plurality of trench portions are also aligned in a second direction (X-axis direction). In FIG. 1 , three gate trench portions 40 and four dummy trench portions 30 are alternately arranged. Each gate trench portion 40 in this example is an example of a first gate trench portion.

[0059] A mesa portion is provided between each trench portion in the X-axis direction. The mesa portion refers to a region inside the semiconductor substrate 10 that is sandwiched between two trench portions. As an example, the upper end of the mesa portion is the upper surface 21 of the semiconductor substrate 10. The depth position of the lower end of the mesa portion 60 is the same as the depth position of the lower end of the trench portion. In this example, the mesa portion is provided on the upper surface 21 of the semiconductor substrate 10, extending in the Y-axis direction along the trench portion.

[0060] The semiconductor device 100 of this example has one or more mesa portions 61 and one or more mesa portions 62. The mesa portion 61 is connected to the emitter electrode 52 via a contact hole 54. The mesa portion 62 is not connected to the emitter electrode 52 as shown in FIG. 1 , or has a smaller contact area with the emitter electrode 52 than the mesa portion 61.

[0061] The mesa portion 61 in this example is in contact with the gate trench portion 40. The mesa portion 61 may be sandwiched between the gate trench portion 40 and the dummy trench portion 30, or may be sandwiched between two gate trench portions 40. The mesa portion 62 in this example may be in contact with the dummy trench portion 30. The mesa portion 62 may be sandwiched between two dummy trench portions 30, or may be sandwiched between the dummy trench portion 30 and the gate trench portion 40. The mesa portion 62 may be sandwiched between two gate trench portions 40. In this example, the mesa portion sandwiched between the gate trench portion 40 and the dummy trench portion 30 is the mesa portion 61, and the other mesa portion is the mesa portion 62.

[0062] The mesa portion 61 has an n+ type emitter region 12 and a p-type base region 14 provided in contact with the gate trench portion 40. The emitter region 12 and the base region 14 are provided in this order from the upper surface 21 side of the semiconductor substrate 10. The emitter region 12 is in contact with the emitter electrode 52 via a contact hole 54. The emitter region 12 has a higher doping concentration than the drift region 18. The emitter region 12 and the base region 14 may be in contact with each other in the depth direction. The emitter region 12 and the base region 14 may be in contact with two trench portions that sandwich the mesa portion 61.

[0063] An n+-type high-concentration region 16 is disposed between the base region 14 and the drift region 18, in contact with the gate trench portion 40. The high-concentration region 16 has a higher doping concentration than the drift region 18. By providing the high-concentration region 16 between the drift region 18 and the base region 14, the carrier injection enhancement effect (IE effect) can be enhanced, and the collector-emitter saturation voltage Vce(sat) can be reduced. The high-concentration region 16 may be in contact with two trench portions that sandwich the mesa portion 61.

[0064] In this example, the high concentration region 16 is in contact with the drift region 18. The high concentration region 16 and the base region 14 may be in contact with each other in the depth direction, or may be separated from each other. In the example of FIG. 1 , an intermediate region 13 is provided between the high concentration region 16 and the base region 14. The intermediate region 13 has the same doping concentration as the drift region 18.

[0065] The mesa portion 62 may have the same structure as the mesa portion 61. However, the mesa portion 62 does not necessarily have to be provided with the emitter region 12. In the mesa portion 62, a base region 14 may be provided instead of the emitter region 12.

[0066] The semiconductor substrate 10 may be provided with a diode mesa portion that operates as a diode. The diode mesa portion has a structure similar to that of the mesa portion 62. However, the base region 14 of the diode mesa portion is connected to the emitter electrode 52 via a contact hole 54. A p-type collector region may be formed on the lower surface of the semiconductor substrate 10 below the mesa portions 61 and 62. An n-type cathode region may be formed on the lower surface of the semiconductor substrate 10 below the diode mesa portion.

[0067] The gate trench portion 40 has a gate trench provided on the upper surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is provided to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate trench and further inside than the gate insulating film 42. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0068] The gate trench portion 40 may be provided to be longer in the depth direction than the base region 14. The gate conductive portion 44 may be provided to be longer in the depth direction than the base region 14. The gate trench portion 40 in this cross section is covered with an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. When a predetermined gate voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the interface of the base region 14 that contacts the gate trench portion 40. As a result, a main current flows between the emitter electrode 52 and the collector electrode (not shown).

[0069] The dummy trench portion 30 may have a structure similar to that of the gate trench portion 40 in the cross section. That is, the dummy trench portion 30 includes a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 provided on the upper surface 21 of the semiconductor substrate 10. The dummy conductive portion 34 is electrically connected to the emitter electrode 52 in another cross section. The dummy insulating film 32 covers the inner wall of the dummy trench. The dummy conductive portion 34 is provided inside the dummy trench and is provided further inward than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 is formed of a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length in the depth direction as the gate conductive portion 44.

[0070] In this example, the gate trench 40 and the dummy trench 30 are covered with an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The bottoms of the dummy trench 30 and the gate trench 40 may have a downwardly convex curved shape (a curved shape in cross section). In this specification, the depth position of the lower end 46 of the gate trench 40 is designated Zt. The depth position of the lower end 46 of the gate trench 40 may be the same as the depth position of the lower end 36 of the dummy trench 30.

[0071] As described above, the mesa portion 62 does not have a contact hole 54 above it, or the length of the contact hole 54 above it in the Y-axis direction is shorter than the length of the contact hole 54 above the mesa portion 61. This prevents holes accumulated below the mesa portion 62 from being extracted, promoting the IE effect and reducing Vce(sat).

[0072] 2 is an example of a top view of the semiconductor device 100 shown in FIG. 2 shows only a portion of the active portion 120 of the semiconductor device 100. The active portion 120 may be a region in the semiconductor device 100 through which a main current flows, or may be a portion located inside the emitter region 12 provided at the outermost portion of the mesa portion 61 in the Y-axis direction. In FIG. 2, the structure exposed on the upper surface 21 of the semiconductor substrate 10 and the contact hole 54 are shown, and other structures are omitted.

[0073] The gate trench portion 40 and the dummy trench portion 30 extend in the Y-axis direction. In addition to the emitter region 12, the mesa portion 61 is provided with a contact region 15. The contact region 15 is a p+ type region with a higher doping concentration than the base region 14. In this example, the emitter region 12 and the contact region 15 are provided alternately in the Y-axis direction of the gate trench portion 40.

[0074] A contact hole 54 is provided above the mesa portion 61. In FIG. 2, the position where the contact hole 54 is provided is hatched. The contact hole 54 above the mesa portion 61 may be provided continuously from the emitter region 12 provided at one end in the Y-axis direction to the emitter region 12 provided at the other end. The base region 14 is exposed on the upper surface of the mesa portion 62. In this example, no contact hole 54 is provided above the mesa portion 62. The contact hole 54 may extend from the upper surface 21 of the semiconductor substrate 10 toward the lower surface and have a depth shallower than the bottom of the base region 14. The semiconductor device 100 may further include a trench contact portion in which a plug is formed inside the extended contact hole 54. The sidewalls of the trench contact portion may be in contact with the emitter region 12 and the contact region 15.

[0075] 3 is an enlarged view of the vicinity of the gate trench 40. In this example, the boundary portion of the gate trench 40 with the semiconductor substrate 10 is referred to as a wall 47. The wall 47 of the gate trench 40 in an XZ cross section perpendicular to the Y-axis direction includes a lower portion 48 and an upper portion 49. In this example, the lower portion 48 is a curved portion that includes the lower end 46 of the gate trench 40. The lower end 46 may be in contact with an n-type region such as the drift region 18. The upper portion 49 is a linear portion that extends from the lower portion 48 toward the upper surface 21 of the semiconductor substrate 10. Of the shape of the wall 47 in this cross section, a portion whose radius of curvature is greater than the length of the gate trench 40 in the Z-axis direction may be treated as a linear portion.

[0076] Each of the emitter region 12, the base region 14, and the intermediate region 13 may be in contact with the upper portion 49. At least a portion of the heavily doped region 16 may be in contact with the upper portion 49 and may be in contact with the lower portion 48. The heavily doped region 16 may be in contact with both the upper portion 49 and the lower portion 48. In the example of Figure 3, the upper end 19 of the heavily doped region 16 is in contact with the upper portion 49, and the lower end 17 is in contact with the lower portion 48.

[0077] 4 is a diagram showing an example of the distribution of doping concentrations along line A-A in FIG. 3. In this specification, the carrier concentration measured by spreading resistance (SR) measurement may be taken as the doping concentration. Line A-A is a straight line parallel to the Z axis, and passes from the emitter region 12 to the drift region 18 in the mesa portion 61.

[0078] The emitter region 12 and the base region 14 may each have a peak doping concentration. The pn junction between the emitter region 12 and the base region 14 may be defined as the boundary between the emitter region 12 and the base region 14.

[0079] The intermediate region 13 has the same doping concentration as the drift region 18. The pn junction between the intermediate region 13 and the base region 14 may be the boundary between the intermediate region 13 and the base region 14.

[0080] The high-concentration region 16 has a higher doping concentration than the drift region 18. The high-concentration region 16 may have a peak doping concentration. When the intermediate region 13 is provided, the position where the doping concentration is higher than the drift region 18 in the direction from the intermediate region 13 toward the high-concentration region 16 may be the upper end 19 of the high-concentration region 16. The position where the doping concentration is twice that of the drift region 18 may also be the upper end 19. When the intermediate region 13 is not provided, the pn junction portion formed by the high-concentration region 16 and the base region 14 may be the upper end 19 of the high-concentration region 16. The position where the doping concentration is higher than that of the drift region 18 in the direction from the drift region 18 toward the high-concentration region 16 may be the lower end 17 of the high-concentration region 16. The position where the doping concentration is twice that of the drift region 18 may also be the lower end 17.

[0081] The high concentration region 16 includes a second position 102 where the doping concentration exhibits a maximum value P1, and a decreasing region 103. The decreasing region 103 is a region where the doping concentration monotonically decreases from the second position 102 toward the drift region 18 in the depth direction of the semiconductor substrate 10. The region where the doping concentration monotonically decreases refers to a region where the doping concentration decreases or remains constant as the distance from the second position 102 increases, and there is no section where the doping concentration increases. In the example of FIG. 4 , the decreasing region 103 extends from the second position 102 to the bottom end 17. The doping concentration at the maximum value P1 is 1×10 １６ / cm ３ Greater than.

[0082] The reduced region 103 has a doping concentration of 1×10 １６ / cm ３ The first position 101 may coincide with the second position 102. That is, the doping concentration at the maximum value P1 is 1×10 １６ / cm ３ When there is a region where the first positions 101 are continuous in the Z-axis direction (i.e., when the doping concentration in the Z-axis direction is 1×10 １６ / cm ３If there is a region where the voltage does not change from the voltage Vcc, the position of the region that is closest to the drift region 18 may be set as the first position 101. The first position 101 may be located closer to the upper surface 21 than the lower end 46 of the gate trench portion 40.

[0083] In this example, the distance d1 between the first position 101 and the lower end 46 of the gate trench portion 40 in the depth direction (Z-axis direction) is 2.5 μm or less. As will be described later, reducing the distance d1 prevents holes from being excessively accumulated below the high-concentration region 16, thereby reducing turn-on loss. The distance d1 may be 1.5 μm or less, 1.0 μm or less, 0.8 μm or less, 0.5 μm or less, 0.2 μm or less, or even 0 μm.

[0084] 5 is a diagram illustrating an example of the operation of a semiconductor device according to a comparative example when it is turned on. In the semiconductor device according to the comparative example, the lower end 17 of the high-concentration region 16 is located away from the lower end 46 of the gate trench portion 40 in the depth direction, and the distance d1 described above is greater than 2.5 μm.

[0085] When a gate voltage equal to or greater than the threshold voltage is applied to the gate trench portion 40, the semiconductor device 100 turns on. Holes injected from a collector region provided on the underside of the semiconductor substrate 10 accumulate in a region 250 below the high-concentration region 16. When excess holes accumulate in the region 250, a displacement current flows from the region 250 to the gate conductive portion 44 via the gate insulating film 42 of the gate trench portion 40. When the displacement current flows to the gate conductive portion 44, an increase in the gate voltage is promoted, and the rate of increase dI / dt of the current at turn-on may become too high.

[0086] When a diode mesa portion is provided on the semiconductor substrate 10, an increase in the current increase rate dI / dt increases the voltage change rate dV / dt during reverse recovery of the diode mesa portion, which may result in a deviation from the required specifications of the semiconductor device. The current increase rate and voltage change rate can be suppressed by increasing the gate resistance connected to the gate trench portion 40, but increasing the gate resistance increases the turn-on loss Eon of the semiconductor device.

[0087] 6 is a diagram illustrating an example of the operation of the semiconductor device 100 according to the embodiment when it is turned on. In the semiconductor device 100, the first position 101 (see FIG. 4 ) of the high-concentration region 16 is located near the lower end 46 of the gate trench portion 40. Since the upper surface 21 of the semiconductor substrate 10 is at the emitter potential (e.g., 0 V) ​​and the lower surface is at the high collector potential, the potential in the mesa portion 61 decreases the farther away from the lower end 46 of the gate trench portion 40 and increases the closer to the lower end 46. Therefore, the closer the high-concentration region 16 is located to the lower end 46, the higher the potential of the high-concentration region 16.

[0088] By increasing the potential of the high-concentration region 16, the potential of the high-concentration region 16 at turn-on tends to be higher than the gate potential of the gate conductive portion 44. When the potential of the gate conductive portion 44 becomes lower than the potential of the high-concentration region 16, holes accumulated below the high-concentration region 16 gather at the interface between the high-concentration region 16 and the gate trench portion 40. As a result, the region of the high-concentration region 16 that contacts the gate trench portion 40 is inverted to a p-type region 210 by the holes. The holes accumulated below the high-concentration region 16 can pass through the region 210 to escape to the base region 14, so that excessive holes are not accumulated below the high-concentration region 16.

[0089] This can prevent a displacement current from flowing through the gate conductive portion 44. It can also prevent the current increase rate dI / dt and the voltage change rate dV / dt from increasing. This eliminates the need to increase the gate resistance, and can prevent an increase in switching loss.

[0090] The potential of the high-concentration region 16 at turn-on may be higher than the threshold voltage at which the semiconductor device 100 turns on. The potential of the high-concentration region 16 may be the potential at the lowest position of the portion in contact with the gate trench portion 40. This facilitates the formation of the region 210 and prevents excessive holes from accumulating below the high-concentration region 16. The potential of the high-concentration region 16 at turn-on, when a low current of 0.1% to 10% of the rated current of the semiconductor device 100 flows, may be higher than the threshold voltage. This prevents excessive holes from accumulating below the high-concentration region 16, particularly at low currents when holes are likely to accumulate. As an example, the threshold voltage of the semiconductor device 100 is 6 V to 8 V, and the potential of the high-concentration region 16 at turn-on is 10 V to 15 V. The term "turn-on" may refer to the timing when a channel is formed in the base region 14 and electron current begins to flow from the emitter region 12 toward the drift region 18.

[0091] 7 is a diagram showing the relationship between the distance d1 (see FIG. 4) and the peak value of the rate of change dV / dt of voltage during reverse recovery. The horizontal axis in FIG. 7 represents the distance d1. Position 0 on the horizontal axis indicates that the first position 101 coincides with position Zt. The distance d1 when the first position 101 is located closer to the upper surface 21 than position Zt is represented by a negative value on the horizontal axis, and the distance d1 when the first position 101 is located closer to the lower surface than position Zt is represented by a positive value on the horizontal axis.

[0092] As shown in FIG. 7 , the smaller the absolute value of the distance d1, the smaller the voltage change rate dV / dt. Furthermore, when the first position 101 is closer to the upper surface 21 than the position Zt, the voltage change rate dV / dt sharply decreases when the absolute value of the distance d1 is 2.5 μm or less. Furthermore, when the first position 101 is closer to the lower surface than the position Zt, the voltage change rate dV / dt sharply increases. For this reason, the distance d1 is set to 2.5 μm or less. A distance d1 of 2.5 μm or less refers to a range of −2.5 μm to 2.5 μm on the horizontal axis of FIG. 7 . As described above, the distance d1 may be 2.5 μm or less, 1.5 μm or less, 1 μm or less, 0.8 μm or less, 0.5 μm or less, 0.2 μm or less, or even 0 μm. Here, the first position 101 may be closer to the upper surface 21 than the position Zt. That is, the first position 101 may be shallower than the lower end 46 of the gate trench portion 40. In this way, it is possible to prevent a decrease in the breakdown voltage of the element.

[0093] 4 , the distance in the Z-axis direction between the lower end 17 of the high-concentration region 16 and the lower end 46 of the gate trench portion 40 is defined as d2. The distance d2 may be 0.5 μm or less, 0.3 μm or less, or 0.1 μm or less. This configuration can further suppress the displacement current to the gate conductive portion 44. The lower end 17 of the high-concentration region 16 may be located closer to the upper surface 21 of the semiconductor substrate 10 than the lower end 46 of the gate trench portion 40, or may be located closer to the lower surface of the semiconductor substrate 10.

[0094] 4 , the length of the gate trench portion 40 in the Z-axis direction is defined as L1. In the Z-axis direction, the distance d1 between the first position 101 and the lower end 46 of the gate trench portion 40 may be 0.1% or more and 20% or less of the length L1 of the gate trench portion 40. The distance d1 may be 10% or less, or may be 5% or less of the length L1. With this configuration, the displacement current to the gate conductive portion 44 can be further suppressed.

[0095] As shown in FIG. 4 , the first position 101 may be located at a position facing the lower portion 48 of the gate trench 40 in the X-axis direction. That is, the first position 101 may be located within the depth range in which the lower portion 48 is located in the depth direction. This configuration can further suppress the displacement current to the gate conductive portion 44. The first position 101 may be located at the same depth as the lower end 46 of the gate trench 40. This can further suppress the displacement current to the gate conductive portion 44. In this specification, the lower end 46 of the gate trench 40 is the lower end of the gate insulating film 42, but the lower end of the gate conductive portion 44 may also be treated as the lower end 46 of the gate trench 40. The same depth position may have an error of ±0.05 μm or less.

[0096] The maximum value P1 of the doping concentration in the high concentration region 16 (see FIG. 4) is 1×10 １６ / cm ３ That's it, 1 x 10 １７ / cm ３ The maximum value P1 may be 1×10 １７ / cm ３ If the maximum value P1 is greater than 1×10, the electric field in the high concentration region 16 becomes high, and the breakdown voltage may decrease. １６ / cm ３ The lower the value, the lower the IE effect. １６ / cm ３ or more, and may be 5×10 １６ / cm ３ It may be more than that.

[0097] The dose of the first conductivity type (n-type in this example) dopant in the high concentration region 16 is 6×10 １２ / cm ２ That's it, 1.8 x 10 １３ / cm ２ The doping concentration of the high concentration region 16 may be integrated from the upper end 19 to the lower end 17 of the high concentration region 16 and used as the dose amount in the high concentration region 16. The dose amount is 8×10 １２ / cm ２ or more, and may be 1×10 １３ / cm ２This makes it possible to suppress a decrease in breakdown voltage while achieving the IE effect.

[0098] 8 is a diagram showing another example of the structure of the mesa portion 61 and the mesa portion 62. The mesa portion 61 and the mesa portion 62 of this example differ from the example shown in FIG. 3 in that they do not have the intermediate region 13. The high concentration region 16 of this example is in contact with the base region 14. The other structures are similar to the example described in FIG. 3.

[0099] The high concentration region 16 may have a doping concentration distribution similar to that of the example in Figure 4. In this case, the gate trench portion 40 of this example may have a shorter length in the Z-axis direction compared to the example in Figure 3. In another example, the gate trench portion 40 of this example may have a length similar to that of the example in Figure 3. In this case, the high concentration region 16 may be formed longer in the Z-axis direction compared to the example in Figure 3.

[0100] 9 is a diagram showing an example of the distribution of doping concentrations along line B-B in FIG. 8. Line B-B is a straight line parallel to the Z axis, passing from the emitter region 12 to the drift region 18 in the mesa portion 61. The mesa portion 61 of this example differs from the example shown in FIG. 4 in that it does not have the intermediate region 13. A pn ​​junction is formed at the boundary between the high-concentration region 16 and the base region 14. In this example, the pn junction is the upper end 19 of the high-concentration region 16. The other structures are the same as those of the example shown in FIG. 4.

[0101] FIG. 10 is a diagram showing another structural example of the mesa portion 61 and the mesa portion 62. In the mesa portion 61 and the mesa portion 62 of this example, the high-concentration region 16 is provided below the lower end 46 of the gate trench portion 40. That is, the upper end 19 of the high-concentration region 16 is located above the lower end 46 of the gate trench portion 40, and the lower end 17 is located below the lower end 46 of the gate trench portion 40. However, the distance from the lower end 46 to the lower end 17 in the Z-axis direction may be shorter than the distance from the lower end 46 to the upper end 19. The distance from the lower end 46 to the lower end 17 may be less than half, or even less than one-quarter, of the distance from the lower end 46 to the upper end 19. The other structures are similar to those of the examples described in FIG. 3 or FIG. 8. In this example, the distance d2 between the lower end 17 of the high-concentration region 16 and the lower end 46 of the gate trench portion 40 may be 0.5 μm or less. In this example, the intermediate region 13 may or may not be provided.

[0102] 11 is a diagram showing an example of the distribution of doping concentrations along line CC in FIG. 10. Line CC is a straight line parallel to the Z axis, and passes from the emitter region 12 to the drift region 18 in the mesa portion 61. The mesa portion 61 of this example differs from the example shown in FIG. 9 in that the high-concentration region 16 is formed below the lower end 46 of the gate trench portion 40. The structure other than the high-concentration region 16 is the same as the example in FIG. 9.

[0103] In the present example, the high-concentration region 16 may have a longer length in the Z-axis direction of the reduced region 103 than the example shown in FIG. In the depth direction (Z-axis direction), the distance from the second position 102 where the doping concentration in the high-concentration region 16 reaches its maximum value P1 to the drift region 18 is defined as d3. The distance from the second position 102 to the base region 14 is defined as d4. The distance d3 may be greater than or equal to d4. Increasing the distance d3 allows the doping concentration in the reduced region 103 to change more gradually, thereby reducing electric field concentration near the lower end 17 of the high-concentration region 16. The distance d3 may be greater than the distance d4. For example, after implanting an n-type dopant at the second position 102, the semiconductor substrate 10 may be annealed for a relatively long time, thereby diffusing the n-type dopant downward and increasing the distance d3. The distance d3 may be at least two or even three times the distance d4. In each example described herein, the distance d3 may be equal to or greater than the distance d4, may be two or more times the distance d4, or may be three or more times the distance d4. In each example described herein, the distance d4 may be equal to or greater than the distance d3, may be two or more times the distance d3, or may be three or more times the distance d4. In any of these cases, the distance d1 may be set to 2.5 μm or less, or may be set to 1 μm or less.

[0104] The dose of n-type dopant in the high-concentration region 16 from the first position 101 to the lower end 17 of the high-concentration region 16 is designated DO1, and the dose of n-type dopant from the upper end 19 to the lower end 17 of the high-concentration region 16 is designated DO2. Furthermore, the dose of n-type dopant in the high-concentration region 16 from the lower end 46 of the gate trench portion 40 to the lower end 17 of the high-concentration region 16 is designated DO3. The dose of each region may be a value obtained by integrating the doping concentration of the region in the depth direction. The dose DO1 may be 0.1% or more and 10% or less of the dose DO2. The dose DO1 may be 5% or less of the dose DO2. By reducing the dose DO1, the reduced region 103 can be formed shorter, and the first position 101 can be controlled with precision. The dose DO3 may be 5% or less of the dose DO2. This prevents a decrease in the device breakdown voltage.

[0105] 12 is a diagram showing another example of the structure of the mesa portion 61 and the mesa portion 62. In the mesa portion 61 and the mesa portion 62 of this example, a high-concentration region 16 is provided instead of the intermediate region 13 in the example shown in FIG. 3. The other structures are the same as those of the example shown in FIG. 3. The high-concentration region 16 of this example is formed longer in the Z-axis direction than the high-concentration region 16 in FIG. 3. The high-concentration region 16 of this example may have a doping concentration distribution similar to that of the high-concentration region 16 of the example shown in FIG. 11, or may have a different doping concentration distribution.

[0106] Fig. 13 is a diagram showing an example of the distribution of the doping concentration along the line DD in Fig. 12. The line DD is a straight line parallel to the Z axis, and passes through the mesa portion 61 from the emitter region 12 to the drift region 18.

[0107] The high-concentration region 16 of this example differs from other examples described herein in that the doping concentration distribution in the depth direction includes a flat portion 104. Other structures are similar to those of any of the examples described herein. The flat portion 104 is a region in which the doping concentration in the depth direction is constant at a maximum value P1. The flat portion 104 may refer to a continuous region in which the doping concentration in the depth direction is 50% or more of the maximum value P1. The flat portion 104 may be formed continuously over 0.5 μm or more in the depth direction, or may be formed continuously over 1 μm or more, or may be formed continuously over 2 μm or more. The depth length of the flat portion 104 may be 30% or more, or may be 50% or more, of the depth length of the high-concentration region 16. The depth length of the flat portion 104 may be more than 1 time, or may be 1.5 times or more, or may be 2 times or more, the depth length of the reduced region 103.

[0108] For example, the flat portion 104 can be formed by implanting a constant dose of n-type dopant into multiple depth positions and annealing the semiconductor substrate 10. The smaller the distance between the depth positions, the more highly flat the flat portion 104 can be formed. When the flat portion 104 is provided, the center position of the flat portion 104 in the depth direction may be set as the second position 102. By providing the flat portion 104, the high concentration region 16 can be formed long in the Z-axis direction. Furthermore, since the high concentration region 16 can be made long while the reduced region 103 can be made short, the first position 101 can be controlled with precision.

[0109] FIG. 14 is a diagram showing another example structure of the mesa portion 61 and the mesa portion 62. The semiconductor device 100 of this example includes a p-type lower end region 204 provided in contact with the lower end 46 of the gate trench portion 40. The other structures are similar to any of the other examples described in this specification. FIG. 14 shows an example in which an intermediate region 13 is provided between the base region 14 and the high-concentration region 16. By providing the lower end region 204, it is possible to alleviate electric field concentration near the lower end 46 of the gate trench portion 40.

[0110] At least one lower end region 204 is not in contact with another trench portion arranged adjacent to the gate trench portion 40. Therefore, at least a portion of the lower ends 17 of the high concentration regions 16 in the mesa portion 61 and the mesa portion 62 is not covered by the lower end region 204 and is in contact with an n-type region such as the drift region 18. Not all lower end regions 204 need to be in contact with another trench portion arranged adjacent to them. In this case, the lower ends 17 of all the high concentration regions 16 are in contact with an n-type region. The lower end 17 of each high concentration region 16 may be in contact with an n-type region at the center of the mesa portion 61 in the X-axis direction.

[0111] Fig. 15 is a diagram showing an example of the distribution of the doping concentration along line E-E in Fig. 14. Line E-E is a straight line parallel to the Z axis, and passes through the position where bottom end region 204 is provided in mesa portion 61, from emitter region 12 to drift region 18.

[0112] A pn junction is provided at the boundary between the high concentration region 16 and the lower end region 204. At the position where the first position 101 contacts the gate trench portion 40, the first position 101 may be located above the pn junction.

[0113] FIG. 16 is a diagram showing another example of the structure of the mesa portion 61 and the mesa portion 62. The semiconductor device 100 of this example includes a p-type lower end region 204 provided in contact with the lower end 46 of the gate trench portion 40. The other structure is similar to any of the other examples described in this specification. FIG. 16 shows an example in which the base region 14 and the high concentration region 16 are in contact with each other. The other structure is similar to the example of FIG. 14.

[0114] Fig. 17 is a diagram showing an example of the distribution of doping concentrations along line F-F in Fig. 16. Line F-F is a straight line parallel to the Z axis, passing through the position where the lower end region 204 is provided in the mesa portion 61, from the emitter region 12 to the drift region 18. This example shows an example in which the base region 14 and the high concentration region 16 are in contact with each other. The other structures are similar to those of the example in Fig. 15.

[0115] 18 is a diagram showing another example of the structure of the mesa portion 61 and the mesa portion 62. The semiconductor device 100 of this example includes a p-type lower end region 204 provided in contact with the lower end 46 of the gate trench portion 40. The other structures are similar to the example described in FIG.

[0116] Fig. 19 is a diagram showing an example of the distribution of doping concentrations along line G-G in Fig. 18. Line G-G is a straight line parallel to the Z axis, and passes through the position where the lower end region 204 is provided in the mesa portion 61, from the emitter region 12 to the drift region 18. As shown in Figs. 18 and 19, the lower end region 204 may be provided inside the high-concentration region 16 in the Z-axis direction.

[0117] 20 is a diagram showing another example of the structure of the mesa portion 61 and the mesa portion 62. The semiconductor device 100 of this example includes a p-type lower end region 204 provided in contact with the lower end 46 of the gate trench portion 40. The other structures are similar to the example described in FIG.

[0118] Fig. 21 is a diagram showing an example of the distribution of doping concentrations along line HH in Fig. 20. Line HH is a straight line parallel to the Z axis, and passes through the position where the lower end region 204 is provided in the mesa portion 61, from the emitter region 12 to the drift region 18. As shown in Figs. 18 and 19, the lower end region 204 may be provided below the high concentration region 16 in the Z axis direction.

[0119] FIG. 22 is a cross-sectional view showing another example of the semiconductor device 100. The semiconductor device 100 of this example differs from the examples described in FIGS. 1 to 21 in the structure of each mesa portion. Other than the structure of the mesa portion, the semiconductor device 100 is the same as any of the examples described in FIGS. 1 to 21. For example, the structures of the gate trench portion 40 and the high-concentration region 16 may be the same as any of the examples described in FIGS. 1 to 21. The structures of the mesa portion and contact hole described in FIG. 22 and subsequent figures may be combined with the structures of the gate trench portion 40 and the high-concentration region 16 of any of the examples described in FIGS. 1 to 21.

[0120] In the semiconductor device 100 of this example, two or more gate trench portions 40 are arranged consecutively in the X-axis direction, and three or more dummy trench portions 30 are arranged consecutively. In Figure 22, three gate trench portions 40 and four dummy trench portions 30 are arranged alternately. In the example of Figure 22, one of the gate trench portions 40 is designated as a first gate trench portion 40-1, and the gate trench portion 40 arranged adjacent to the first gate trench portion 40-1 is designated as a second gate trench portion 40-2. Furthermore, the dummy trench portion 30 arranged adjacent to the second gate trench portion 40-2 on the opposite side from the first gate trench portion 40-1 is referred to as the first dummy trench portion 30-1, the dummy trench portion 30 arranged adjacent to the first dummy trench portion 30-1 on the opposite side from the second gate trench portion 40-2 is referred to as the second dummy trench portion 30-2, and the dummy trench portion 30 arranged adjacent to the second dummy trench portion 30-2 on the opposite side from the first dummy trench portion 30-1 is referred to as the third dummy trench portion 30-3.

[0121] Within the semiconductor substrate 10, the mesa portion 60 sandwiched between the first gate trench portion 40-1 and the second gate trench portion 40-2 is referred to as the first mesa portion 60-1, the mesa portion 60 sandwiched between the second gate trench portion 40-2 and the first dummy trench portion 30-1 is referred to as the second mesa portion 60-2, the mesa portion 60 sandwiched between the first dummy trench portion 30-1 and the second dummy trench portion 30-2 is referred to as the third mesa portion 60-3, and the mesa portion 60 sandwiched between the second dummy trench portion 30-2 and the third dummy trench portion 30-3 is referred to as the fourth mesa portion 60-4. In the example of Figure 22, the mesa portion 60 sandwiched between two gate trench portions 40 is referred to as the first mesa portion 60-1, the mesa portion 60 sandwiched between the gate trench portion 40 and the dummy trench portion 30 is referred to as the second mesa portion 60-2, the mesa portion 60 adjacent to the second mesa portion 60-2 on the opposite side of the first mesa portion 60-1 is referred to as the third mesa portion 60-3, and the mesa portion 60 sandwiched between the third mesa portions 60-3 is referred to as the fourth mesa portion 60-4.

[0122] Each mesa portion 60 is connected to the emitter electrode 52 via a contact hole 54 provided in the interlayer insulating film 38. The contact hole 54 may not be provided in some of the mesas 60.

[0123] The first mesa portion 60-1 has an emitter region 12, a base region 14, and a high-concentration region 16. The first mesa portion 60-1 may or may not have an intermediate region 13. The first mesa portion 60-1 is connected to the emitter electrode 52 by a first contact hole 54-1.

[0124] The second mesa portion 60-2 has a base region 14 and a high-concentration region 16. The second mesa portion 60-2 may or may not have an intermediate region 13. The second mesa portion 60-2 is connected to the emitter electrode 52 by a second contact hole 54-2.

[0125] The third mesa portion 60-3 has a base region 14 and a high-concentration region 16. The third mesa portion 60-3 may or may not have an intermediate region 13. The third mesa portion 60-3 is connected to the emitter electrode 52 by a second contact hole 54-2.

[0126] The fourth mesa portion 60-4 has a base region 14 and a high-concentration region 16. The fourth mesa portion 60-4 may or may not have an intermediate region 13. The fourth mesa portion 60-4 is connected to the emitter electrode 52 by a first contact hole 54-1.

[0127] The first contact hole 54-1 provided in one mesa portion 60 has a larger contact area between the semiconductor substrate 10 and the emitter electrode 52 than the second contact hole 54-2 provided in one mesa portion 60. For example, the first contact hole 54-1 may be formed longer in the Y-axis direction and wider in the X-axis direction than the second contact hole 54-2.

[0128] Fig. 23 is an example of a top view of the semiconductor device 100 described in Fig. 22. Fig. 23 shows the vicinity of one end of the trench portion in the Y-axis direction. The other end of the trench portion in the Y-axis direction may also have a structure similar to that shown in Fig. 23. Each trench portion may have a U-shape. The U-shape includes two linear extension portions extending in the Y-axis direction and a connection portion connecting the ends of the two extension portions.

[0129] The gate trench 40 of this example has two extensions 41 and a connection 43 that connects the ends of the two extensions 41. At least a portion of the connection 43 is provided in a curved shape on the upper surface of the semiconductor substrate 10. This reduces electric field concentration near the end of the gate trench 40. The gate trench 40 may be connected to a gate wiring provided above the interlayer insulating film 38 via a contact hole 55 provided in the interlayer insulating film 38. The contact hole 55 and the gate wiring may be arranged in a region that does not overlap with the emitter electrode 52.

[0130] The dummy trench portion 30 of this example has two extension portions 31 and a connection portion 33 that connects the ends of the two extension portions 31. At least a portion of the connection portion 33 is provided in a curved shape on the upper surface of the semiconductor substrate 10. This makes it possible to alleviate electric field concentration near the end of the dummy trench portion 30. The dummy trench portion 30 may be connected to an emitter electrode 52 provided above the interlayer insulating film 38 via a contact hole 56 provided in the interlayer insulating film 38.

[0131] 23, one U-shaped trench is arranged so as to be surrounded by other U-shaped trenches. For example, a U-shaped dummy trench 30 or a gate trench 40 is provided so as to surround a U-shaped dummy trench 30.

[0132] An emitter region 12 is provided on the upper surface of the first mesa portion 60-1. A p+ type contact region 15 having a doping concentration higher than that of the base region 14 may be provided on the upper surface of the first mesa portion 60-1. The emitter regions 12 and the contact regions 15 may be arranged alternately in the Y-axis direction or in the X-axis direction. Each of the emitter regions 12 and the contact regions 15 is in contact with the emitter electrode 52 via a first contact hole 54-1.

[0133] Base regions 14 are provided on the upper surfaces of the second mesa portion 60-2, the third mesa portion 60-3, and the fourth mesa portion 60-4. The base regions 14 of the second mesa portion 60-2 and the third mesa portion 60-3 are in contact with the emitter electrode 52 through a second contact hole 54-2. The base region 14 of the fourth mesa portion 60-4 is in contact with the emitter electrode 52 through a first contact hole 54-1.

[0134] A first contact area S1 where the semiconductor substrate 10 and the emitter electrode 52 contact in the first mesa portion 60-1 may be larger than a second contact area S2 where the semiconductor substrate 10 and the emitter electrode 52 contact in the second mesa portion 60-2. The second contact area S2 may be one-half or less, one-fourth or less, or one-tenth or less of the first contact area S1.

[0135] A third contact area S3 where the semiconductor substrate 10 and the emitter electrode 52 contact in the third mesa portion 60-3 may be smaller than the first contact area S1. The third contact area S23 may be equal to or smaller than half, one-quarter, or one-tenth of the first contact area S1. The second contact area S2 and the third contact area S3 may be the same or different.

[0136] A fourth contact area S4 where the semiconductor substrate 10 and the emitter electrode 52 contact each other in the fourth mesa portion 60-4 may be larger than both the second contact area S2 and the third contact area S3. The fourth contact area S4 may be at least two times, at least four times, or at least ten times the second contact area S2 and the third contact area S3. The fourth contact area S4 and the first contact area S1 may be the same or different.

[0137] The first contact area S1 corresponds to the total area of ​​the first contact holes 54-1 in one first mesa portion 60-1. The second contact area S2 corresponds to the total area of ​​the second contact holes 54-2 in one second mesa portion 60-2. The third contact area S3 corresponds to the total area of ​​the second contact holes 54-2 in one third mesa portion 60-3. The fourth contact area S4 corresponds to the total area of ​​the first contact holes 54-1 in one fourth mesa portion 60-4.

[0138] As described above, the first contact hole 54-1 may be formed longer in the Y-axis direction and wider in the X-axis direction than the second contact hole 54-2. The first contact hole 54-1 in this example may be formed continuously from one contact region 15 arranged at both ends in the Y-axis direction to the other contact region 15, or may be formed continuously from one emitter region 12 arranged at both ends in the Y-axis direction to the other emitter region 12. The second contact holes 54-2 may be arranged discretely in the Y-axis direction.

[0139] 24 is an example of a top view of the semiconductor device 100 described in FIG. 22. Fig. 24 shows a region near the center of the trench portion in the Y-axis direction. As described above, the first contact hole 54-1 is formed continuously from one contact region 15 arranged at both ends in the Y-axis direction to the other contact region 15. In addition, the second contact holes 54-2 are arranged discretely in the Y-axis direction.

[0140] This configuration suppresses hole extraction in the second mesa portion 60-2 and the third mesa portion 60-3, allowing carriers to accumulate below the second mesa portion 60-2 and the third mesa portion 60-3. This improves the trade-off between the collector-emitter voltage in the saturated state and the turn-off loss. Furthermore, by partially providing the second contact hole 54-2 in the second mesa portion 60-2 and the third mesa portion 60-3, excessive carrier accumulation can be prevented. Furthermore, as described with reference to FIGS. 1 to 21, excessive hole accumulation can be prevented by forming the high-concentration region 16 up to the vicinity of the bottom end 46 of the gate trench portion 40. However, the second mesa portion 60-2 and the third mesa portion 60-3 may be floating mesa portions without providing the second contact hole 54-2.

[0141] 25 is a diagram showing another example of the structure of the region shown in FIG. 24. In the semiconductor device 100 of this example, at least one contact hole 56 and at least one contact hole 54-2 are arranged opposite each other in the X-axis direction. A plurality of contact holes 56 and a plurality of second contact holes 54-2 may be arranged opposite each other in the X-axis direction. The contact holes of all of the second mesa portions 60-2, all of the third mesa portions 60-3, and all of the dummy trench portions 30 may be arranged in a line along the X-axis direction.

[0142] 26 is a diagram showing the relationship between collector-emitter saturation voltage Vce(sat) and turn-off loss Eoff for a comparative example and an example. The comparative example is an example in which first contact holes 54-1 are provided in all mesa portions, and the example is an example having the structure described with reference to FIGS. 22 to 25. As shown in FIG. 26, the example in which second contact holes 54-2 are provided has an improved Vce(sat)-Eoff trade-off compared to the comparative example in which second contact holes 54-2 are not provided.

[0143] 27 is a diagram showing the relationship between dV / dt_peak and gate resistance Rg in the comparative example and the example. dV / dt_peak is the peak value of the slope of the time waveform of the emitter-collector voltage when the semiconductor device 100 is turned on. In the example, the gate resistance Rg can be reduced when dV / dt_peak is set to the same level as in the comparative example. As a result, the semiconductor device 100 of the example has faster switching operation, reduced turn-on loss Eon, and reduced reverse recovery loss Err.

[0144] 28 is a diagram showing the relationship between dV / dt_peak and Eon+Err for the comparative example and the example. As described in FIG. 27, the semiconductor device 100 of the example can reduce the gate resistance Rg when dV / dt_peak is set to the same level as in the comparative example, and can reduce the turn-on loss Eon and the reverse recovery loss Err. As shown in FIG. 28, the semiconductor device 100 of the example can reduce Eon+Err by about 30% compared to the comparative example.

[0145] 29 is a top view showing another example of the semiconductor device 100. The semiconductor device 100 of this example differs from the examples described with reference to FIGS. 22 to 28 in the arrangement of the contact holes. The structure other than the contact holes is the same as any of the examples described with reference to FIGS. 22 to 28.

[0146] In this example, a contact hole 56-1 is provided in the first dummy trench portion 30-1 as an example of a first trench contact hole, and a contact hole 56-2 is provided in the second dummy trench portion 30-2 as an example of a second trench contact hole.

[0147] In the present example, a contact hole 54-1 is provided in the first mesa portion 60-1 as an example of a first mesa contact hole. In the present example, a contact hole 54-2 is provided in the second mesa portion 60-2 as an example of a second mesa contact hole. In the present example, a contact hole 54-3 is provided in the third mesa portion 60-3 as an example of a third mesa contact hole. In the present example, a contact hole 54-4 is provided in the fourth mesa portion 60-4 as an example of a fourth mesa contact hole.

[0148] As described with reference to FIG. 22 and other figures, contact holes 54-2, 54-3, 56-1, and 56-2 are each discretely arranged in the Y-axis direction. However, in this example, contact hole 54-3 is not arranged opposite either contact hole 56-1 or contact hole 56-2 in the X-axis direction. In other words, the range in the Y-axis direction in which contact hole 54-3 is provided does not overlap with the range in the Y-axis direction in which contact holes 56-1 and 56-2 are provided. At least a portion of contact hole 56-1 and at least a portion of contact hole 56-2 may be arranged opposite each other in the X-axis direction. In other words, the range in the Y-axis direction in which contact hole 56-1 is provided may overlap with the range in the Y-axis direction in which contact hole 56-2 is provided.

[0149] When the width of the mesa portion or the width of the trench portion is reduced, it becomes difficult to form each contact hole independently if the contact holes are arranged facing each other in the X-axis direction. In this example, since contact hole 54-3 does not face either contact hole 56-1 or contact hole 56-2, each contact hole can be easily formed even if the width of mesa portion 60 in the X-axis direction and the width of the trench portion in the X-axis direction are reduced.

[0150] In adjacent mesa and trench portions, the contact holes are preferably arranged so as not to face each other in the X-axis direction. In the gate trench portion 40, the contact hole 55 is not arranged in the area facing the contact hole 54-1. As in the example of FIG. 23 , the contact hole 55 may be arranged further outward in the Y-axis direction than the contact hole 54-1.

[0151] The contact hole 54-2 is not disposed opposite the contact hole 56-1 in the X-axis direction, but the contact holes 54-2 and 54-3 may be disposed opposite each other in the X-axis direction.

[0152] The contact holes 54-4 do not have to be formed in a range facing the contact hole 56-2. As shown in Fig. 29, the contact holes 54-4 may be provided discretely in the Y-axis direction in a range not facing the contact hole 56-2.

[0153] The contact hole 54-4 may be formed to be longer in the Y-axis direction than the contact holes 54-2 and 54-3, and shorter in the Y-axis direction than the contact hole 54-1.

[0154] Fig. 30 is a diagram showing an example of the II cross section of Fig. 29. The II cross section is an XZ cross section passing through contact holes 56-1 and 56-2. As shown in Fig. 30, no contact hole 54 is provided in the mesa portion adjacent to the trench portion in which the contact hole is provided.

[0155] Fig. 31 is a diagram showing an example of the J-J cross section of Fig. 29. The J-J cross section is an XZ cross section passing through contact holes 54-2 and 54-3. As shown in Fig. 31, no contact hole is provided in the trench portion adjacent to the mesa portion in which contact hole 54 is provided.

[0156] FIG. 32 is a cross-sectional view showing another example of the semiconductor device 100. The semiconductor device 100 of this example differs from the examples described in FIGS. 1 to 31 in the structure of each mesa portion. Other than the structure of the mesa portion, the semiconductor device 100 is similar to any of the examples described in FIGS. 1 to 31. For example, the structures of the gate trench portion 40 and the high-concentration region 16 may be similar to any of the examples described in FIGS. 1 to 21. However, the arrangement of the gate trench portion 40 and the high-concentration region 16 may be different from the examples described in FIGS. 1 to 21. The structures of the mesa portion and contact hole described in FIG. 32 and subsequent figures may be combined with the structures of the gate trench portion 40 and the high-concentration region 16 of any of the examples described in FIGS. 1 to 21.

[0157] The arrangement pattern of the gate trench portions 40 and the dummy trench portions 30 in the X-axis direction in the semiconductor device 100 of this example is similar to, but not limited to, the example in Fig. 22. In the example in Fig. 32, three gate trench portions 40 and four dummy trench portions 30 are arranged alternately. Furthermore, the arrangement pattern of the mesa portions 60 in the X-axis direction in the semiconductor device 100 of this example is similar to, but not limited to, the example in Fig. 22.

[0158] In this example, of the multiple mesa portions 60, the one that contacts the gate trench portion 40 and has the base region 14 and emitter region 12 provided therein is referred to as the channel mesa portion. A high-concentration region 16 may be provided in the channel mesa portion. In the example of FIG. 32 , the second mesa portion 60-2 sandwiched between the second gate trench portion 40-2 and the first dummy trench portion 30-1 is the channel mesa portion. An intermediate region 13 may or may not be provided in the channel mesa portion.

[0159] In this example, among the multiple mesa portions 60, the one sandwiched between two dummy trench portions 30 is referred to as a dummy mesa portion. A base region 14 is provided in the dummy mesa portion. The base region 14 of the dummy mesa portion is exposed on the upper surface 21 of the semiconductor substrate 10. The lower end of the base region 14 may be in contact with the drift region 18. The dummy mesa portion may be disposed next to the channel mesa portion. In the example of FIG. 32 , the third mesa portion 60-3 and the fourth mesa portion 60-4 are dummy mesa portions. The fourth mesa portion 60-4 may have the same structure as the third mesa portion 60-3 or a different structure. In this specification, the third mesa portion 60-3 and the fourth mesa portion 60-4 can each be interpreted as a dummy mesa portion, and the dummy mesa portion can be interpreted as the third mesa portion 60-3 or the fourth mesa portion 60-4. Furthermore, the second mesa portion 60-2 can be read as a channel mesa portion, and the channel mesa portion can be read as the second mesa portion 60-2.

[0160] In the dummy mesa portion (for example, the third mesa portion 60-3), the high-concentration region 16 is not provided between the base region 14 and the drift region 18, or the high-concentration region 16 is less than that in the channel mesa portion (for example, the second mesa portion 60-2). In the example of FIG. 32, the high-concentration region 16 is not provided in the third mesa portion 60-3.

[0161] In a dummy mesa portion (e.g., the third mesa portion 60-3), the integral of the doping concentration of the n-type region from the depth position of the lower end of the base region 14 to the depth position of the lower end of the dummy trench portion 30 is defined as the dummy mesa integral concentration. In a channel mesa portion (e.g., the second mesa portion 60-2), the integral of the doping concentration of the n-type region from the depth position of the lower end of the base region 14 to the depth position of the lower end of the gate trench portion 40 is defined as the channel mesa integral concentration. Each integral concentration may be measured at a position in contact with the trench portion, or at the center position of the mesa portion 60 in the X-axis direction. Having fewer high-concentration regions 16 in the dummy mesa portion than in the channel mesa portion may mean that the dummy mesa integral concentration is lower than the channel mesa integral concentration. In the example of FIG. 32, the dummy mesa integral concentration is the integral of the doping concentration of the drift region 18. On the other hand, the channel mesa integral concentration is higher than the dummy mesa integral concentration because of the presence of the high concentration region 16. The dummy mesa integral concentration may be half or less, one-quarter or less, or one-tenth or less of the channel mesa integral concentration.

[0162] In the dummy mesa portion of this example, the drift region 18 is provided from the base region 14 to the depth position of the lower end of the dummy trench portion 30. In other words, the high-concentration region 16 is not provided in the dummy mesa portion. In another example, the high-concentration region 16 may be provided in the dummy mesa portion. In this case, the high-concentration region 16 of the dummy mesa portion may have a lower doping concentration than the high-concentration region 16 of the channel mesa portion. The doping concentration of the high-concentration region 16 of the dummy mesa portion may be half or less, one-quarter or less, one-tenth or less, or one-hundredth or less of the doping concentration of the high-concentration region 16 of the channel mesa portion. However, the high-concentration region 16 of the dummy mesa portion has a higher concentration than the drift region 18.

[0163] The high-concentration region 16 of the dummy mesa portion may have a smaller width in the depth direction than the high-concentration region 16 of the channel mesa portion. The width in the depth direction of the high-concentration region 16 of the dummy mesa portion may be half or less, one-quarter or less, or one-tenth or less of the width in the depth direction of the high-concentration region 16 of the channel mesa portion. In this case, the doping concentrations of the high-concentration region 16 of the dummy mesa portion and the channel mesa portion may be the same.

[0164] In a top view, the area of ​​the high-concentration region 16 provided in one dummy mesa portion may be smaller than the area of ​​the high-concentration region 16 provided in one channel mesa portion. This is also an example of the number of high-concentration regions 16 in the dummy mesa portion being small. The top view refers to the projection of each component of the semiconductor device 100 onto a plane parallel to the top surface 21 of the semiconductor substrate 10.

[0165] The contact portion is the portion of the dummy mesa where the semiconductor substrate 10 and the emitter electrode 52 come into contact with each other. The contact portion is, for example, the opening of a contact hole 54 at the position of the upper surface 21 of the semiconductor substrate 10. In this specification, the opening of the contact hole 54 at the upper surface 21 of the semiconductor substrate 10 may be simply referred to as the contact hole 54. In this case, the contact hole 54 is an example of the contact portion.

[0166] The area of ​​the contact hole 54 in one dummy mesa may be smaller than the area of ​​the contact hole 54 in one channel mesa, or may be zero. In the example of Figure 32, a second contact hole 54-2 is provided in a dummy mesa (e.g., the third mesa 60-3), and a first contact hole 54-1 is provided in a channel mesa (e.g., the second mesa 60-2). As described above, the area of ​​the second contact hole 54-2 is smaller than the area of ​​the first contact hole 54-1.

[0167] According to this embodiment, the dummy mesa portion does not have a high-concentration region 16, or the high-concentration region 16 in the dummy mesa portion is relatively small. This makes it easier for holes injected from the lower surface when the semiconductor device 100 is turned on to flow into the dummy mesa portion. For example, some of the holes accumulated below the channel mesa portion tend to flow into the dummy mesa portion. This prevents excessive accumulation of holes near the gate trench portion 40 adjacent to the channel mesa portion.

[0168] By suppressing excessive accumulation of holes near the gate trench portion 40, it is possible to suppress the flow of displacement current through the gate trench portion 40. This makes it possible to suppress an increase in the rate of increase dI / dt of current and the rate of change dV / dt of voltage. This eliminates the need to increase the gate resistance, and makes it possible to suppress an increase in switching loss.

[0169] The second contact holes 54 provided in the dummy mesa portion allow holes to be discharged from the dummy mesa portion to the emitter electrode 52, thereby promoting the flow of holes into the dummy mesa portion. However, if the area of ​​the second contact holes 54 in the dummy mesa portion is increased, excessive hole discharge occurs, reducing the IE effect. In this example, by providing the second contact holes 54 with a small area in the dummy mesa portion, it is possible to suppress the displacement current to the gate trench portion 40 while maintaining the IE effect.

[0170] The semiconductor device 100 may be provided with mesa portions other than the channel mesa portion and the dummy mesa portion. In the example of FIG. 32 , in addition to the channel mesa portion and the dummy mesa portion, a first mesa portion 60-1 sandwiched between two gate trench portions 40 is provided. In this example, the first mesa portion 60-1 has a base region 14 in contact with the upper surface 21 of the semiconductor substrate 10. A high-concentration region 16 may or may not be provided below the base region 14. An intermediate region 13 may or may not be provided between the base region 14 and the high-concentration region 16. The contact area between the semiconductor substrate 10 and the emitter electrode 52 in the first mesa portion 60-1 is smaller than the contact area between the semiconductor substrate 10 and the emitter electrode 52 in the channel mesa portion (e.g., the second mesa portion 60-2), or the first mesa portion 60-1 does not contact the emitter electrode 52. The first mesa portion 60-1 shown in FIG. 32 is a floating mesa portion that is not connected to the emitter electrode 52, but is not limited to this.

[0171] Fig. 33 is an example of a top view of the semiconductor device 100 described in Fig. 32. Fig. 33 shows a region near the center of the trench portion in the Y-axis direction. As described above, the second mesa portion 60-2 is provided with a first contact hole 54-1, and the third mesa portion 60-3 and the fourth mesa portion 60-4 are provided with second contact holes 54-2. The first mesa portion 60-1 is not provided with a contact hole 54.

[0172] This configuration suppresses excessive discharge of holes from the second mesa 60-2 and the third mesa 60-3, making it easier to maintain the IE effect. It also makes it easier to accumulate holes below the first mesa 60-1, making it easier to maintain the IE effect. A second contact hole 54-2 may be provided in the first mesa 60-1.

[0173] The doping concentration of the p-type region in contact with the emitter electrode 52 in the dummy mesa may be lower than the doping concentration of the p-type region in contact with the emitter electrode 52 in the channel mesa. In this example, the base region 14 contacts the emitter electrode 52 in the dummy mesa (e.g., the third mesa 60-3), and the contact region 15 contacts the emitter electrode 52 in the channel mesa (e.g., the second mesa 60-2). This configuration increases the contact resistance between the emitter electrode 52 and the dummy mesa, allowing the amount of hole extraction to be adjusted. This makes it easier to maintain the IE effect. In another example, the emitter electrode 52 may also be in contact with the contact region 15 in the dummy mesa. In this case, holes are more easily discharged via the dummy mesa, making it easier to suppress the displacement current to the gate trench 40.

[0174] In this example, the channel mesa portion (e.g., the second mesa portion 60-2) and the dummy mesa portion (e.g., the third mesa portion 60-3) are arranged side by side in the X-axis direction. The second contact hole 54-2 of the dummy mesa portion may be arranged facing the emitter region 12 of the channel mesa portion in the X-axis direction. The second contact hole 54-2 may be provided over a wider area than the emitter region 12 in the Y-axis direction, or may be provided over the same area or a narrower area. By arranging the second contact hole 54-2 facing the emitter region 12, holes below the emitter region 12 are more likely to flow into the dummy mesa portion. This prevents displacement current from flowing through the gate trench portion 40 below the emitter region 12, thereby preventing the current increase rate dI / dt and the voltage change rate dV / dt from increasing.

[0175] The second contact holes 54-2 may be provided corresponding to at least some of the multiple emitter regions 12 in the channel mesa portion, or may be provided for all of the emitter regions 12. In other words, the number of second contact holes 54-2 provided discretely in the Y-axis direction in one dummy mesa portion may be less than or equal to the number of emitter regions 12 provided discretely in the Y-axis direction in one channel mesa portion.

[0176] Fig. 34 is another example of a top view of the semiconductor device 100 described in Fig. 32. In this example, the position of the second contact hole 54-2 differs from the example in Fig. 33. The other structures are similar to the example in Fig. 33.

[0177] In this example, the second contact hole 54-2 of the dummy mesa portion is disposed in a position that does not face the emitter region 12 of the channel mesa portion in the X-axis direction. The second contact hole 54-2 may be disposed in a position that faces the contact region 15 of the channel mesa portion in the X-axis direction. The second contact hole 54-2 may be provided in a range narrower than the contact region 15 in the Y-axis direction, or may be provided in the same range. In this example, holes below the emitter region 12 are more easily prevented from flowing into the dummy mesa portion, making it easier to maintain the IE effect and reducing the on-voltage.

[0178] The dummy mesa portion may include a second contact hole 54-2 facing the emitter region 12 and a second contact hole 54-2 facing the contact region 15. In this case, it is possible to adjust the balance between suppressing the displacement current and maintaining the IE effect. The second contact hole 54-2 in the dummy mesa portion may be disposed so as to face the boundary between the emitter region 12 and the contact region 15.

[0179] Fig. 35 is another example of a top view of the semiconductor device 100 described in Fig. 32. In this example, the second contact hole 54-2 is different from the example in Fig. 33. The other structures are similar to the example in Fig. 33.

[0180] In this example, the third mesa portion 60-3 is the first dummy mesa portion, and the fourth mesa portion 60-4 is the second dummy mesa portion. The second dummy mesa portion is located farther from the channel mesa portion than the first dummy mesa portion. The area of ​​the second contact hole 54-2 in the third mesa portion 60-3 is smaller than the area of ​​the second contact hole 54-2 in the fourth mesa portion 60-4. In other words, among the multiple dummy mesa portions, the area of ​​the second contact hole 54-2 in the dummy mesa portion closer to the channel mesa portion is smaller. This prevents holes below the channel mesa portion from flowing into adjacent dummy mesa portions. This makes it easier to maintain the IE effect. The area of ​​the second contact hole 54-2 in the third mesa portion 60-3 may be less than half, or even less than one-quarter, of the area of ​​the second contact hole 54-2 in the fourth mesa portion 60-4.

[0181] In another example, the area of ​​the second contact hole 54-2 in the third mesa portion 60-3 may be larger than the area of ​​the second contact hole 54-2 in the fourth mesa portion 60-4. In other words, among the multiple dummy mesa portions, the area of ​​the second contact hole 54-2 is larger in the dummy mesa portion closer to the channel mesa portion. This promotes the flow of holes below the channel mesa portion into the adjacent dummy mesa portion. This makes it easier to suppress the displacement current to the gate trench portion 40. The area of ​​the second contact hole 54-2 in the fourth mesa portion 60-4 may be less than half, or even less than one-quarter, of the area of ​​the second contact hole 54-2 in the third mesa portion 60-3.

[0182] 36 is a cross-sectional view showing another example of the semiconductor device 100. The semiconductor device 100 of this example differs from the examples described with reference to FIGS. 1 to 35 in the arrangement pattern of the gate trench portions 40 and the dummy trench portions 30. Other structures may be similar to those of the examples described with reference to FIGS. 1 to 35.

[0183] In this example, one gate trench portion 40 and two dummy trench portions 30 are alternately arranged along the X-axis direction. In other words, two dummy trench portions 30 are arranged between two gate trench portions 40.

[0184] In this example, the mesa portion 60 sandwiched between the gate trench portion 40 and the dummy trench portion 30 is referred to as the second mesa portion 60-2. The second mesa portion 60-2 is an example of a channel mesa portion. The mesa portion 60 sandwiched between two dummy trench portions 30 is referred to as the third mesa portion 60-3. The third mesa portion 60-3 is an example of a dummy mesa portion. The structures of the second mesa portion 60-2 and the third mesa portion 60-3 are similar to those in the example of FIG. 32 .

[0185] The second mesa 60-2 is provided with a first contact hole 54-1. The third mesa 60-3 is provided with a second contact hole 54-2. The third mesa 60-3 does not necessarily have to be provided with a contact hole 54.

[0186] In this example as well, the dummy mesa portion does not have a high-concentration region 16, or the high-concentration region 16 in the dummy mesa portion is relatively small. The area of ​​the contact hole 54 in one dummy mesa portion is either smaller than the area of ​​the contact hole 54 in one channel mesa portion, or is zero. In this example as well, the displacement current in the gate trench portion 40 can be suppressed while maintaining the IE effect.

[0187] Fig. 37 is a cross-sectional view showing another example of the semiconductor device 100. The semiconductor device 100 of this example differs from the example of Fig. 32 in the structure of the first mesa portion 60-1. The other structures may be similar to the example of Fig. 32.

[0188] In the first mesa portion 60-1 of this example, there is no high-concentration region 16 between the base region 14 and the drift region 18, or there are fewer high-concentration regions 16 than in the channel mesa portion (e.g., the second mesa portion 60-2). The number of high-concentration regions 16 in the first mesa portion 60-1 may be the same as that in the third mesa portion 60-3. In FIG. 37, there are no high-concentration regions 16 in the first mesa portion 60-1 and the third mesa portion 60-3.

[0189] According to this example, holes also flow more easily into the first mesa portion 60-1, which makes it possible to suppress the displacement current in the gate trench portion 40.

[0190] 38 is a cross-sectional view showing another example of the semiconductor device 100. The semiconductor device 100 of this example differs from the other examples described in this specification in that no contact hole 54 is provided for the dummy mesa portion. In other words, the dummy mesa portion of this example is not in contact with the emitter electrode 52. The structure other than the contact hole 54 is the same as any of the other examples described in this specification. This example also makes it possible to suppress the displacement current in the gate trench portion 40 and maintain the IE effect.

[0191] 39 is a cross-sectional view showing another example of the semiconductor device 100. The semiconductor device 100 of this example differs from the other examples described in this specification in the structure of the base region 14. The structure other than the base region 14 is the same as any of the other examples described in this specification.

[0192] In this example, the base regions 14 of the dummy mesa portions (e.g., the third mesa portion 60-3 and the fourth mesa portion 60-4) are formed deeper than the base region 14 of the channel mesa portion (e.g., the second mesa portion 60-2). This configuration makes it easier for holes to flow into the dummy mesa portions. This makes it easier to suppress the displacement current in the gate trench portion 40. The lower ends of the base regions 14 of the dummy mesa portions may be located closer to the upper surface 21 than the lower ends of the high-concentration regions 16, at the same depth, or further downward. The deeper the base regions 14 are formed, the easier it is for holes to flow into the dummy mesa portions.

[0193] Fig. 40 is a top view showing another example of the second mesa portion 60-2 and the third mesa portion 60-3. Fig. 40 shows the positions of the contact holes 54 and the high-concentration regions 16 when viewed from above. The drift region 18 shown in Fig. 40 is provided at the same depth as the high-concentration regions 16. In this example, a first contact hole 54-1 is provided in the second mesa portion 60-2, and a second contact hole 54-2 is provided in the third mesa portion 60-3.

[0194] In this example, when viewed from above, the area of ​​the high-concentration region 16 provided in one dummy mesa (the third mesa 60-3 in this example) is smaller than the area of ​​the high-concentration region 16 provided in one channel mesa (the second mesa 60-2 in this example). The area of ​​the high-concentration region 16 in the third mesa 60-3 may be less than half, or even less than one-quarter, of the area of ​​the high-concentration region 16 in the second mesa 60-2. Even with this configuration, the high-concentration region 16 in the dummy mesa can be smaller than the high-concentration region 16 in the channel mesa.

[0195] In the third mesa portion 60-3, a high-concentration region 16 may be provided below the contact portion (in this example, the second contact hole 54-2). In the third mesa portion 60-3, the high-concentration region 16 is not provided in at least a part of the region that does not overlap with the second contact hole 54-2. The entire second contact hole 54-2 may overlap with the high-concentration region 16, and the second contact hole 54-2 may be provided in a range wider than the high-concentration region 16 in the Y-axis direction.

[0196] 41 is a top view showing another example of the second mesa portion 60-2 and the third mesa portion 60-3. In this example, too, the area of ​​the high-concentration region 16 provided in one dummy mesa portion (the third mesa portion 60-3 in this example) is smaller than the area of ​​the high-concentration region 16 provided in one channel mesa portion (the second mesa portion 60-2 in this example). In this example, no high-concentration region 16 is provided below the contact portion (the second contact hole 54-2 in this example). A drift region 18 is provided below the second contact hole 54-2 at the same depth as the high-concentration region 16. The entire second contact hole 54-2 may overlap the drift region 18.

[0197] The number of high-concentration regions 16 provided in each dummy mesa portion may decrease the farther away from the channel mesa portion. For example, the number of high-concentration regions 16 in the fourth mesa portion 60-4 may be smaller than the number of high-concentration regions 16 in the third mesa portion 60-3. The area of ​​the high-concentration regions 16 in the fourth mesa portion 60-4 may be smaller in top view than the high-concentration regions 16 in the third mesa portion 60-3, and the integrated concentration in the depth direction may be smaller. The third mesa portion 60-3 may be provided with a high-concentration region 16, while the fourth mesa portion 60-4 may not be provided with a high-concentration region 16. The structure other than the high-concentration regions 16 is the same as any of the examples described in this specification.

[0198] In another example, the number of high-concentration regions 16 provided in each dummy mesa portion may increase the farther away from the channel mesa portion. For example, the number of high-concentration regions 16 in the fourth mesa portion 60-4 may be greater than the number of high-concentration regions 16 in the third mesa portion 60-3. The high-concentration regions 16 in the fourth mesa portion 60-4 may have a larger area in a top view and a larger integrated concentration in the depth direction than the high-concentration regions 16 in the third mesa portion 60-3. The third mesa portion 60-3 may not have a high-concentration region 16, and the fourth mesa portion 60-4 may have a high-concentration region 16. The structure other than the high-concentration regions 16 is the same as any of the examples described in this specification.

[0199] FIG. 42 shows an example of a reverse recovery waveform of a diode mesa during low-current operation. FIG. 42 shows the waveforms of the anode-cathode voltage Vak and the anode current Ia of the diode mesa. Also, in FIG. 42, the solid line shows the waveform of an example in which the high-concentration region 16 of the dummy mesa is reduced, as described in FIGS. 32 to 41, and the dashed line shows the waveform of a comparative example in which the high-concentration region 16 of the dummy mesa is not reduced. As shown in region 300 of FIG. 42, the example can reduce the slope dV / dt of Vak. This eliminates the need to increase the gate resistance in order to reduce dV / dt, thereby suppressing increases in switching loss.

[0200] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. For example, if the gate potential trench does not contact the emitter region 12, it can be considered a dummy trench portion 30. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0201] 10...semiconductor substrate, 12...emitter region, 13...intermediate region, 14...base region, 15...contact region, 16...high concentration region, 17...gate, 18...drift region, 19...upper end, 21...upper surface, 30...dummy trench portion, 31...extension portion, 32...dummy insulating film, 33...connection portion, 34...dummy conductive portion, 36...gate, 38...interlayer insulating film, 40...gate trench portion, 41...extension portion, 42...gate Gate insulating film, 43...connection portion, 44...gate conductive portion, 46...gate, 47...wall portion, 48...lower portion, 49...upper portion, 52...emitter electrode, 54, 55, 56...contact hole, 60, 61, 62...mesa portion, 100...semiconductor device, 101...first position, 102...second position, 103...decreased region, 104...flat portion, 120...active portion, 204...bottom end region, 210, 250...region, 300...region

Claims

A semiconductor device provided on a semiconductor substrate having an upper surface, a first conductivity type drift region provided inside the semiconductor substrate; a first gate trench portion provided from the upper surface of the semiconductor substrate to the interior of the semiconductor substrate; a second conductivity type base region provided in contact with the first gate trench portion; a first conductivity type high concentration region that is provided in contact with the first gate trench portion, is disposed between the base region and the drift region in contact with the drift region, and has a doping concentration higher than that of the drift region; Equipped with the high concentration region includes a decreasing region in which the doping concentration monotonically decreases from a position where the doping concentration has a maximum value toward the drift region in a depth direction of the semiconductor substrate, The doping concentration of the reduced region is 1×10 １６ / cm ３ and a first position where The distance between the first position and the lower end of the first gate trench portion in the depth direction is 2.5 μm or less. Semiconductor device. 　 The maximum value of the doping concentration in the high concentration region is 1×10 １６ / cm ３ That's it, 1 x 10 １７ / cm ３ is The semiconductor device according to claim 1 . 　 In the depth direction, the distance from a second position where the doping concentration in the high concentration region exhibits a maximum value to the drift region is equal to or greater than the distance from the second position to the base region. The semiconductor device according to claim 1 . 　 The distance between the first position and the lower end of the first gate trench portion in the depth direction is 1.0 μm or less. The semiconductor device according to claim 1 . 　 The first position is shallower than a bottom end of the first gate trench portion. The semiconductor device according to claim 1 . 　 In the depth direction, the distance between the first position and the lower end of the first gate trench portion is 0.1% or more and 20% or less of the length of the first gate trench portion. The semiconductor device according to claim 1 . 　 The dose of the first conductivity type dopant in the high concentration region is 6×10 １２ / cm ２ That's it, 1.8 x 10 １３ / cm ２ is The semiconductor device according to claim 1 . 　 a dose of the first conductivity type dopant in the high concentration region from the first position to a lower end of the high concentration region is 0.1% or more and 10% or less of a dose of the first conductivity type dopant from an upper end to a lower end of the high concentration region; The semiconductor device according to claim 1 . 　 the first gate trench portion is provided on the upper surface of the semiconductor substrate and extends in a first direction, The wall portion of the first gate trench portion in a cross section perpendicular to the first direction includes: a curved lower portion including a lower end of the first gate trench portion; a linear upper portion extending from the lower portion toward the upper surface of the semiconductor substrate; Including, The first position is provided in a depth range facing the lower portion. The semiconductor device according to claim 1 . 　 The first position is provided at the same depth as the bottom end of the first gate trench portion. The semiconductor device according to claim 1 . 　 a second conductivity type lower end region provided in contact with a lower end of the first gate trench portion; The semiconductor device according to claim 1 . 　 A lower end of the first gate trench portion is in contact with a region of the first conductivity type. The semiconductor device according to claim 1 . 　 When a current of 0.1% or more and 10% or less of the rated current of the semiconductor device flows during turn-on, the potential of the high concentration region is higher than the threshold voltage at which the semiconductor device is turned on. The semiconductor device according to claim 1 . 　 The high concentration region is in contact with the base region. The semiconductor device according to claim 1 . 　 Between the high concentration region and the base region, an intermediate region of the first conductivity type having the same doping concentration as the drift region is provided. The semiconductor device according to claim 1 . 　 a second gate trench portion provided from the upper surface of the semiconductor substrate to the interior of the semiconductor substrate and disposed adjacent to the first gate trench portion; a first dummy trench portion provided inside the semiconductor substrate from the upper surface of the semiconductor substrate and arranged adjacent to the second gate trench portion on the opposite side to the first gate trench portion; a first mesa portion sandwiched between the first gate trench portion and the second gate trench portion inside the semiconductor substrate; a second mesa portion sandwiched between the second gate trench portion and the first dummy trench portion within the semiconductor substrate; a top electrode disposed above the top surface of the semiconductor substrate; an interlayer insulating film provided between the semiconductor substrate and the upper surface electrode, the interlayer insulating film having a contact hole for connecting the semiconductor substrate and the upper surface electrode; Equipped with A first contact area where the semiconductor substrate and the upper surface electrode contact each other in the first mesa portion is larger than a second contact area where the semiconductor substrate and the upper surface electrode contact each other in the second mesa portion. 　 The semiconductor device according to claim 1 . 　 a second dummy trench portion provided inside the semiconductor substrate from the upper surface of the semiconductor substrate and arranged adjacent to the first dummy trench portion on the opposite side to the second gate trench portion; a third mesa portion sandwiched between the first dummy trench portion and the second dummy trench portion inside the semiconductor substrate; Equipped with A third contact area where the semiconductor substrate and the upper surface electrode contact each other in the third mesa portion is smaller than the first contact area. The semiconductor device according to claim 16. 　 the second mesa portion has the high concentration region, In the third mesa portion, the high concentration region is not provided between the base region and the drift region, or the high concentration region is less than that in the second mesa portion. The semiconductor device according to claim 17. 　 The third mesa portion is not provided with the high concentration region.

19. The semiconductor device according to claim 18. 　 The second contact area is less than half of the first contact area, and the third contact area is less than half of the first contact area.

20. The semiconductor device according to claim 19. 　 a third dummy trench portion provided inside the semiconductor substrate from the upper surface of the semiconductor substrate and disposed adjacent to the second dummy trench portion on the opposite side to the first dummy trench portion; a fourth mesa portion sandwiched between the second dummy trench portion and the third dummy trench portion inside the semiconductor substrate; Equipped with a fourth contact area where the semiconductor substrate and the upper surface electrode contact each other in the fourth mesa portion, the fourth contact area being larger than both the second contact area and the third contact area; 20. The semiconductor device according to claim 19. 　 a first dummy trench portion provided from the upper surface of the semiconductor substrate to the interior of the semiconductor substrate and disposed adjacent to the first gate trench portion; a second dummy trench portion provided from the upper surface of the semiconductor substrate to the interior of the semiconductor substrate and disposed adjacent to the first dummy trench portion; a third mesa portion sandwiched between the first dummy trench portion and the second dummy trench portion inside the semiconductor substrate; a top electrode disposed above the top surface of the semiconductor substrate; an interlayer insulating film provided between the semiconductor substrate and the upper electrode; Equipped with The interlayer insulating film has a first trench contact hole connecting the upper surface electrode and the first dummy trench portion; a second trench contact hole connecting the upper surface electrode and the second dummy trench portion; a mesa contact hole connecting the upper surface electrode and the third mesa portion; is established, the first dummy trench portion and the second dummy trench portion are provided on the upper surface of the semiconductor substrate so as to extend in a first direction; In a second direction parallel to the upper surface of the semiconductor substrate and perpendicular to the first direction, the mesa contact hole is not disposed opposite either the first trench contact hole or the second trench contact hole. The semiconductor device according to claim 1 . 　 At least a portion of the first trench contact hole and at least a portion of the second trench contact hole are disposed opposite each other in the second direction.

23. The semiconductor device according to claim 22. 　 A semiconductor device provided on a semiconductor substrate having an upper surface, an upper surface electrode provided above the upper surface of the semiconductor substrate; a first conductivity type drift region provided inside the semiconductor substrate; one or more gate trench portions and a plurality of dummy trench portions provided from the upper surface of the semiconductor substrate to the interior of the semiconductor substrate; a channel mesa portion in contact with the gate trench portion; a dummy mesa portion sandwiched between the two dummy trench portions; Equipped with the channel mesa portion and the dummy mesa portion each have a base region of a second conductivity type provided between the drift region and the upper surface of the semiconductor substrate; The channel mesa portion is an emitter region of a first conductivity type provided between the base region and the upper surface of the semiconductor substrate and having a doping concentration higher than that of the drift region; a first conductivity type high concentration region provided between the base region and the drift region, the high concentration region having a doping concentration higher than that of the drift region; and In the dummy mesa portion, the high concentration region is not provided between the base region and the drift region, or the high concentration region is less than that in the channel mesa portion, The area of ​​the contact portion where the semiconductor substrate and the upper surface electrode contact in the dummy mesa portion is smaller than the area of ​​the contact portion where the semiconductor substrate and the upper surface electrode contact in the channel mesa portion, or is zero. Semiconductor device. 　 A dummy mesa integral concentration obtained by integrating the doping concentration of a first conductivity type region from the depth position of the lower end of the base region to the depth position of the lower end of the dummy trench portion is lower than a channel mesa integral concentration obtained by integrating the doping concentration of a first conductivity type region from the depth position of the lower end of the base region to the depth position of the lower end of the gate trench portion in the channel mesa portion.

25. The semiconductor device according to claim 24. 　 The drift region is provided from the base region of the dummy mesa portion to a depth position of the lower end of the dummy trench portion.

26. The semiconductor device according to claim 25. 　 The base region of the dummy mesa portion is provided deeper than the base region of the channel mesa portion.

27. The semiconductor device according to claim 26. 　 In a top view, the area of ​​the high concentration region provided in one of the dummy mesa portions is smaller than the area of ​​the high concentration region provided in one of the channel mesa portions.

25. The semiconductor device according to claim 24. 　 In the dummy mesa portion, the high concentration region is provided below the contact portion, and the high concentration region is not provided in at least a part of the region that does not overlap with the contact portion.

29. The semiconductor device according to claim 28. 　 The doping concentration of the second conductivity type region in contact with the upper surface electrode in the dummy mesa portion is lower than the doping concentration of the second conductivity type region in contact with the upper surface electrode in the channel mesa portion.

25. The semiconductor device according to claim 24. 　 the channel mesa portion and the dummy mesa portion are arranged side by side in a second direction, The contact portion of the dummy mesa portion is disposed opposite the emitter region of the channel mesa portion in the second direction.

25. The semiconductor device according to claim 24. 　 the channel mesa portion and the dummy mesa portion are arranged side by side in a second direction, The contact portion of the dummy mesa portion is disposed at a position that does not face the emitter region of the channel mesa portion in the second direction.

25. The semiconductor device according to claim 24. 　 a first dummy mesa portion and a second dummy mesa portion disposed farther from the channel mesa portion than the first dummy mesa portion, The area of ​​the contact portion in the first dummy mesa portion is smaller than the area of ​​the contact portion in the second dummy mesa portion.

25. The semiconductor device according to claim 24. 　 the channel mesa portion is sandwiched between the gate trench portion and the dummy trench portion, The dummy mesa portion is a mesa portion adjacent to the channel mesa portion.

33. The semiconductor device according to any one of claims 24 to 32. 　 a first mesa portion sandwiched between the two gate trench portions; A contact area between the semiconductor substrate and the upper surface electrode in the first mesa portion is smaller than a contact area between the semiconductor substrate and the upper surface electrode in the channel mesa portion, or the first mesa portion is not in contact with the upper surface electrode.

35. The semiconductor device according to claim 34. 　 The first mesa portion has the base region and the high concentration region.

36. The semiconductor device according to claim 35. 　 the first mesa portion has the base region, In the first mesa portion, the high concentration region is not provided between the base region and the drift region, or the high concentration region is less than that in the channel mesa portion.

36. The semiconductor device according to claim 35. 　 The dummy mesa portion is not in contact with the upper surface electrode.

35. The semiconductor device according to claim 34.

Images