Improving system performance through hardware offload of best master clock algorithm

Abstract

The present disclosure describes a system, and a method to improve the system performance through hardware offload of a Best Master Clock Algorithm (BMCA). The system comprising at least one hardware entity integrated with a primary BMCA. The at least one hardware entity is configured to receive a plurality of Precision Time Protocol (PTP) masters from a plurality of PTP master clocks. Thereafter, the at least one hardware entity is configured to select a PTP master as a best PTP master from the plurality of PTP masters using the primary BMCA in the at least one hardware entity and transmit the best PTP master to a second entity for synchronizing a slave clock.

Description

[0001] IMPROVING SYSTEM PERFORMANCE THROUGH HARDWARE OFFLOAD OF BEST MASTER CLOCK ALGORITHM CROSS REFERENCE TO RELATED APPLICATION(S)

[0001] This application claims priority based on India Patent Application No.202441067013 filed September 4, 2024, the entire disclosure of which is incorporated by reference herein. TECHNICAL FIELD

[0002] The present disclosure relates to improving system performance through hardware offload of a Best Master Clock Algorithm (BMCA). BACKGROUND ART

[0003] In a conventional network, as shown in FIG.1, there may be multiple Grandmaster (GM) clocks 101, 103 connecting to a slave (or client) clock in an O-RAN-Distributed Unit (O-DU) 111 through a network consisting of Transparent Clocks (TCs) 105, 107, 109 such as routers or switches. The multiple Precision Time Protocol (PTP) masters from same or multiple GM clocks 101, 103 are transmitted to a Best Master Clock Algorithm (BMCA) 127 in the O-DU 111, wherein a PTP master carries Sync or Follow_up messages (which are 44 bytes) or Announce messages (which are 64 bytes). However, the slave (or client) clock in the O-DU 111 can select only one PTP master from the multiple PTP masters using the BMCA 127 for synchronization of the slave (or client) clock.

[0004] The information disclosed in this background of the disclosure section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person skilled in the art. SUMMARY

[0005] The present disclosure tries to address the aforesaid problem associated with working of existing BMCA.

[0006] In an embodiment, the present disclosure relates to a system. The system comprising at least one hardware entity integrated with a primary BMCA. The at least one hardware entity is configured to receive a plurality of PTP masters from a plurality of PTP master clocks. Thereafter, the at least one hardware entity is configured to select a PTP master as a best PTP master from the plurality of PTP masters using the primary BMCA in the at least one hardware entity. Lastly, the at least one hardware entity is configured to transmit the best PTP master to a second entity for synchronizing a slave clock.

[0007] In another embodiment, the present disclosure relates to a method. The method comprising receiving a plurality of PTP masters from a plurality of PTP master clocks. Thereafter, the method comprising selecting a PTP master as a best PTP master from the plurality of PTP masters using a primary BMCA in at least one hardware entity. Lastly, the method comprising transmitting the best PTP master to a second entity for synchronizing a slave clock.

[0008] In yet another embodiment, the present disclosure relates to a non-transitory computer readable medium. The non-transitory computer readable medium includes instructions stored thereon that when processed by at least one processor cause at least one hardware entity to perform operations comprising receiving a plurality of PTP masters from a plurality of PTP master clocks. Thereafter, the instructions cause the at least one processor to select a PTP master as a best PTP master from the plurality of PTP masters using a primary BMCA in the at least one hardware entity. Lastly, the instructions cause the at least one processor to transmit the best PTP master to a second entity for synchronizing a slave clock.

[0009] The foregoing summary is illustrative only and is not intended to be in any way limiting. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features will become apparent by reference to the drawings and the following detailed description. BRIEF DESCRIPTION OF THE ACCOMPANYING DRAWINGS

[0010] The accompanying drawings, which are incorporated in and constitute a part of this disclosure, illustrate embodiments and together with the description, serve to explain the disclosed principles. In the figures, the left-most digit(s) of a reference number identifies the figure in which the reference number first appears. The same numbers are used throughout the figures to reference like features and components. Some embodiments of system and methods in accordance with embodiments of the present subject matter are now described below, by way of example only, and with reference to the accompanying figures.

[0011] FIG.1 illustrates working of an existing BMCA in a conventional network.

[0012] FIG. 2 illustrates an environment for improving system performance through hardware offload of a BMCA in accordance with some embodiments of the present disclosure.

[0013] FIG.3 shows a detailed block diagram of a hardware entity of a system in accordance with some embodiments of the present disclosure.

[0014] FIGS. 4 and 5 illustrate flowcharts showing methods for improving system performance through hardware offload of a BMCA in accordance with some embodiments of the present disclosure.

[0015] It should be appreciated by those skilled in the art that any block diagrams herein represent conceptual views of illustrative systems embodying the principles of the present subject matter. Similarly, it will be appreciated that any flowcharts, flow diagrams, state transition diagrams, pseudo code, and the like represent various processes which may be substantially represented in computer readable medium and executed by a computer or processor, whether or not such computer or processor is explicitly shown. DETAILED DESCRIPTION

[0016] In the present document, the word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or implementation of the present subject matter described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

[0017] While the disclosure is susceptible to various modifications and alternative forms, specific embodiment thereof has been shown by way of example in the drawings and will be described in detail below. It should be understood, however that it is not intended to limit the disclosure to the particular forms disclosed, but on the contrary, the disclosure is to cover all modifications, equivalents, and alternatives falling within the scope of the disclosure.

[0018] The terms “comprises”, “comprising”, or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a setup, device or method that comprises a list of components or steps does not include only those components or steps but may include other components or steps not expressly listed or inherent to such setup or device or method. In other words, one or more elements in a system or apparatus proceeded by “comprises… a” does not, without more constraints, preclude the existence of other elements or additional elements in the system or method.

[0019] In the following detailed description of the embodiments of the disclosure, reference is made to the accompanying drawings that form a part hereof, and in which are shown by way of illustration specific embodiments in which the disclosure may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the disclosure, and it is to be understood that other embodiments may be utilized and that changes may be made without departing from the scope of the present disclosure. The following description is, therefore, not to be taken in a limiting sense.

[0020] Table 1 Abbreviation Description GM Grandmaster s CD Compact Disc FPGA Field-Programmable Gate Arrays

[0021] 127 in the conventional network shown in FIG.1 imposes a significant resource drain on the O-DU 111. This involves increased consumption of CPU processing time, generation of extra buffer duplicates, expanded memory needs, and handling traffic for numerous PTP masters. Additionally, the Network Interface Cards (NICs) 113, 115 are burdened with continuous time stamping of the PTP masters received from the same or multiple GM clocks. Among the PTP masters that are timestamped, all the PTP masters are forwarded by the NICs 113, 115 to the BMCA 127. However, only one PTP master is selected by the BMCA 127 for synchronization of the slave (or client) clock while other timestamped PTP masters are discarded by the BMCA 127. Consequently, this results in inefficient utilization of hardware or firmware resource in the NICs.

[0022] FIG. 2 illustrates an environment for improving system performance through hardware offload of a BMCA in accordance with some embodiments of the present disclosure. With reference to FIG.2, the environment 200 comprises a plurality of GM clocks 101, 103, a plurality of TCs 105, 107, 109, and an O-DU (also, referred as DU) 201. The GM clock 101 and the GM clock 103 of the plurality of GM clocks 101, 103, may, also, be referred as a PTP master clock. The GM clock 101 and the GM clock 103 are communicatively connected to the O-DU 201 through a TC network consisting of the plurality of TCs 105, 107, 109.

[0023] The O-DU 201 comprises a plurality of Hardware Entities (HEs) 203, 205, a plurality of NDDs 117, 119, a kernel 121, a transport layer 123, and a second entity 211. In FIG.2, only two hardware entities 203, 205 have been shown. However, in practice, there may be, without limitations, only one hardware entity or more than two hardware entities. In an embodiment, the plurality of hardware entities 203, 205, and the second entity 211 together form a system. The hardware entity 203 of the plurality of hardware entities 203, 205 is integrated with a primary BMCA 207 and the hardware entity 205 of the plurality of hardware entities 203, 205 is integrated with a primary BMCA 209. The at least one hardware entity 203, 205 is one of a NIC, network controller, or network adaptor. In an embodiment, the at least one hardware entity 203, 205 has hardware timestamp capability. Timestamping refers to generating ingress and egress timestamps for PTP masters. The at least one hardware entity 203, 205 with hardware timestamp capability have clocks in them that timestamp the best PTP master when it arrives. This approach helps in reducing the hardware overhead of timestamping the excess PTP masters belonging to all PTP masters. Further, this approach offloads software-based BMCA at the second entity 211 to hardware entities 203, 205, which perform hardware PTP timestamping and allow PTP master selected by the primary BMCA 207, 209 in the hardware entity 203, 205 further to upper layers (i.e., the NDDs 117, 119, the kernel 121, and the transport layer 123) within the O-DU 201. As a result, this approach of using the hardware entities 203, 205 (1) allows for better utilization of resources such as the hardware entities 203, 205 and the second entity 211 within the O-DU 201, (2) improves the system performance within the O-DU 201, (3) allows RAN vendors to offer better solution with limited hardware resources, and (4) improves overall return on investment per DU and reduces capital expenditure for operators.

[0024] NDDs 117, 119 perform the separation of the O-DU’s 201 hardware components i.e., the plurality of Hardware Entities (HEs) 203, 205 from its software elements i.e., the kernel 121. By decoupling hardware and software, the NDDs 117, 119 promotes flexibility, customization, and efficiency. The kernel 121 generally controls the operation of the O-DU 201. The transport layer 123 refers to a layer of protocols that provide end-to-end communication services for applications within the O-DU 201.

[0025] The second entity 211 comprises a PTP stack 125, a secondary BMCA 213, and a servo 129. In an embodiment, the second entity 211 may be a software entity. The second entity 211 may, also, be referred as a timing stack or a timing application. The servo 129 (also, referred as servo algorithm) is responsible for synchronizing a slave clock with a master clock by computing the phase or frequency or time offsets from PTP masters. The PTP stack 125 complies with IEEE standard 1588TMand enables clock synchronization over IP and Ethernet. In one embodiment, the primary BMCA and the secondary BMCA are same. In another embodiment, the primary BMCA and the secondary BMCA are different. The primary BMCA and the secondary BMCA may refer to the BMCA mentioned in the IEEE Standard 1588TMfor a Precision Clock Synchronization Protocol for Networked Measurement and Control Systems. Hence, the explanation including the operation of the primary BMCA and the secondary BMCA are omitted here. The secondary BMCA and the at least one hardware entity integrated with the primary BMCA are part of the O- DU 201 for synchronizing a slave clock of the O-DU 201.

[0026] The operation for improving system performance through hardware offload of a BMCA is explained with reference to FIG.2.

[0027] A plurality of PTP masters emanating from same or multiple PTP master clocks 101, 103 are transmitted to the O-DU 201 through the TC network. At least one hardware entity 203, 205 integrated with the primary BMCA 207, 209 receives the plurality of PTP masters from the plurality of PTP master clocks 101, 103. Thereafter, the primary BMCA 207, 209 in the at least one hardware entity 203, 205 selects a PTP master as a best PTP master from the plurality of PTP masters. The at least one hardware entity 203, 205 timestamps the best PTP master. The timestamp is a hardware timestamped. For instance, the primary BMCA 207 in the hardware entity 203 receives nine PTP masters from the plurality of PTP master clocks 101, 103 and selects one PTP master as the best PTP master from the nine PTP masters. The hardware entity 203 timestamps the best PTP master. Analogously, the primary BMCA 209 in the hardware entity 205 receives nine PTP masters from the plurality of PTP master clocks 101, 103 and selects one PTP master as the best PTP master from the nine PTP masters. The hardware entity 205 timestamps the best PTP master. The primary BMCA 207, 209 selects the best PTP master based on at least one of user- configurable designated priority attributes, a clock class attribute, a clock accuracy attribute, and a clock identity attribute. The user-configurable designated priority attribute is a user-configurable designation that a PTP instance belongs to an ordered set of PTP instances from which a master PTP instance is selected. The PTP instance refers to an instance of a PTP protocol, operating in a single device, within exactly one domain. The PTP instance implements those portions of the standard indicated as applicable to an ordinary clock, a boundary clock, or a transparent clock. The clock class attribute refers to an attribute defining an International Atomic Time (TAI) traceability, synchronization state, and expected performance of the time or frequency distributed by a boundary clock or ordinary clock. The boundary clock refers to a PTP instance that has multiple PTP ports in a domain and maintains the timescale used in the domain. Within a domain, the boundary clock may serve as the source of time to other PTP instances, that is, be a master clock. The boundary clock can in addition synchronize to another boundary clock or ordinary clock master. The ordinary clock can be configured either as an ordinary clock master or an ordinary clock slave. The ordinary clock refers to a PTP instance that has a single PTP Port in its domain and maintains the timescale used in the domain.. The clock accuracy attribute refers to an attribute defining the accuracy of the ordinary clock master of a PTP instance. The clock identity attribute refers to a tie-breaker based on unique identifiers for PTP Instances on different PTP nodes. The integration of the primary BMCA 207, 209 with the hardware entity 203, 205 to select a PTP master as a best PTP master from the plurality of PTP masters avoids handling and transmitting of unwanted PTP masters to the second entity 211. Consequently, this approach improves the O-DU 201 performance by efficiently utilizing the O-DU 201 resources by reducing additional utilization of CPU cycles, minimizing multiple buffer copies, reducing memory requirements, and avoiding multiple PTP masters traffic handling. As seen from FIG.2, the hardware entity 203 receives nine PTP masters and the hardware entity 205 receives nine PTP masters. One PTP master is selected from the nine PTP masters by the hardware entity 203 and sent to the second entity 211. One PTP master is selected from the nine PTP masters by the hardware entity 205 and sent to the second entity 211. Thus, the second entity 211 receives only two PTP masters (shown as dotted arrows in FIG.2), as against earlier 18 PTP masters (shown as solid arrows in FIG.1), which reduces the O- DU 201 and the hardware entity 203, 205 overhead significantly. For instance, with reference to FIG. 1, with total 18 PTP masters and with Sync or Follow_up message (which are 44 bytes) or Announce message (which are 64 bytes), assuming PTP packet rate of 16 packets per second (pps) for Sync or Follow_up message, 8pps for Announce message, the BMCA 127 receives 34 Kbytes per second of PTP master. With reference to FIG. 2, the secondary BMCA 213 receives just two PTP masters , thus, allowing the secondary BMCA 213 to select one PTP master out of the two PTP masters and resulting in reduction of traffic down to 3840 bytes (i.e., 3.8 Kbytes), which is approximately only 11% of PTP traffic encountered in the conventional network shown in FIG.1.

[0028] The hardware entity 203 transmits the selected best PTP master by the primary BMCA 207 to the secondary BMCA 213 of the second entity 211 through the NDD 117, the kernel, 121 and the transport layer 123. Analogously, the hardware entity 205 transmits the selected best PTP master by the primary BMCA 209 to the secondary BMCA 213 of the second entity 211 through the NDD 119, the kernel, 121 and the transport layer 123. The secondary BMCA 213 of the second entity 211 receives at least one best PTP master from the at least one hardware entity 203, 205. Thereafter, the secondary BMCA 213 of the second entity 211 selects a final best PTP master from the at least one best PTP master. For instance, the secondary BMCA 213 of the second entity 211 receives one best PTP master from the hardware entity 203 selected by the primary BMCA 207 and one best PTP master from the hardware entity 205 selected by the primary BMCA 209. The secondary BMCA 213 of the second entity 211 selects the final best PTP master from the two best PTP masters received from the hardware entity 203 and the hardware entity 205. The secondary BMCA 213 selects the final best PTP master based on at least one of user-configurable designated priority attributes, a clock class attribute, a clock accuracy attribute, and a clock identity attribute. Upon selection of the final best PTP master, the secondary BMCA 213 of the second entity 211 applies the final best PTP master for a slave clock synchronization in the O-DU 201.

[0029] The system and the method of the present disclosure for improving system performance through hardware offload of a BMCA is applicable to, but not limited to, LTE, 5G, and 6G wireless communication network.

[0030] FIG.3 shows a detailed block diagram of a hardware entity of a system in accordance with some embodiments of the present disclosure.

[0031] The hardware entity 203 may include, but not limited to, an I-O interface 301, a processor 303, data 307, and modules 313, which are described herein in detail.

[0032] The hardware entity 203 may communicate with the plurality of PTP master clocks 101 and 103 via the plurality of transparent clocks 105, 107, 109 and the I-O interface 301. The I-O interface 301 may employ communication protocols or methods such as, without limitation, Bluetooth, cellular e.g., CDMA, HSPA+, GSM, LTE, NR, WiMax, NG interface, or the like.

[0033] The processor 303 may include at least one data processor for improving system performance through hardware offload of a BMCA. The processor 303 may include specialized processing units such as, without limitation, integrated system (bus) controllers, memory management control units, floating point units, graphics processing units, digital signal processing units, etc.

[0034] In an embodiment, the data 307 may be stored within the memory 305. The memory 305 may be communicatively coupled to the processor 303 of the hardware entity 203. The memory 305 may, also, store processor instructions which may cause the processor 303 to execute the instructions for improving system performance through hardware offload of the BMCA. The memory 305 may include, without limitation, memory drives, etc. The memory drives may further include a drum, magnetic disc drive, magneto-optical drive, optical drive, RAID, solid-state memory devices, solid-state drives, etc.

[0035] The data 307 may include, for example, PTP data 309, and miscellaneous data 311. The PTP data 309 may store the plurality of PTP masters received from the plurality of PTP master clocks 101, 103. The miscellaneous data 311 may store data, including temporary data and temporary files, generated by modules 313 for performing the various functions of the hardware entity 203.

[0036] In an embodiment, the data 307 in the memory 305 are processed by the modules 313 present within the memory 305 of the hardware entity 203. The modules 313 may be implemented as dedicated hardware units. As used herein, the term module refers to at least one of an ASIC, an electronic circuit, a FPGA, a combinational logic circuit, and other suitable components that provide the described functionality. In some implementations, the modules 313 may be communicatively coupled to the processor 303 for performing one or more functions of the hardware entity 203. The modules 313 when configured with the functionality defined in the present disclosure will result in a novel hardware.

[0037] In one implementation, the modules 313 may include, but are not limited to, a transceiver 315, and a primary BMCA 207. The modules 313 may, also, include miscellaneous modules 317 to perform various miscellaneous functionalities of the hardware entity 203.

[0038] The transceiver 315 may receive the plurality of PTP masters from the plurality of PTP master clocks 101, 103.

[0039] When the primary BMCA 207 selects a PTP master as a best PTP master from the plurality of PTP masters, the transceiver 315 may transmit the best PTP master to the second entity 211 for synchronizing a slave clock.

[0040] The primary BMCA 207 may select a PTP master as a best PTP master from the plurality of PTP masters received from the transceiver 315. Further, the primary BMCA 207 may timestamp the best PTP master. The timestamp is a hardware timestamped. The primary BMCA may select the best PTP master based on at least one of user-configurable designated priority attributes, a clock class attribute, a clock accuracy attribute, and a clock identity attribute.

[0041] The detailed block diagram and operation of the hardware entity 205 of a system is same as the detailed block diagram and operation of the hardware entity 203 mentioned-above. Hence, the description of the detailed block diagram and operation of the hardware entity 205 is omitted.

[0042] FIG.4 illustrates a flowchart showing a method for improving system performance through hardware offload of a BMCA in accordance with some embodiments of the present disclosure.

[0043] As illustrated in FIG.4, the method 400 includes one or more blocks for improving system performance through hardware offload of a BMCA in accordance with some embodiments of the present disclosure. The method 400 may be described in the general context of computer executable instructions. Generally, computer executable instructions can include routines, programs, objects, components, data structures, procedures, modules, and functions, which perform particular functions or implement particular abstract data types.

[0044] The order in which the method 400 is described is not intended to be construed as a limitation, and any number of the described method blocks can be combined in any order to implement the method. Additionally, individual blocks may be deleted from the methods without departing from the scope of the subject matter described herein. Furthermore, the method can be implemented in any suitable hardware, software, firmware, or combination thereof.

[0045] At block 401, the transceiver 315 of the at least one hardware entity 203, 205 receives a plurality of PTP masters from a plurality of master clocks 101, 103. The at least one hardware entity 203, 205 is one of a NIC, network controller, or network adaptor.

[0046] At block 403, the primary BMCA 207 of the at least one hardware entity 203, 205 selects a PTP master as a best PTP master from the plurality of PTP masters. The primary BMCA 207 selects the best PTP master based on at least one of user-configurable designated priority attributes, a clock class attribute, a clock accuracy attribute, and a clock identity attribute.

[0047] At block 405, the transceiver 315 of the at least one hardware entity 203, 205 transmits the best PTP master to the second entity 211 for synchronizing a slave clock.

[0048] At block 407, the second entity 211 of the system receives at least one best PTP master from the at least one hardware entity 203, 205.

[0049] At block 409, the second entity 211 of the system selects a final best PTP master from the at least one best PTP master using the secondary BMCA 213. The secondary BMCA 213 selects the final best PTP master based on at least one of user-configurable designated priority attributes, a clock class attribute, a clock accuracy attribute, and a clock identity attribute.

[0050] At block 411, the second entity 211 of the system applies the final best PTP master for a slave clock synchronization in the DU 201.

[0051] FIG.5 illustrates a flowchart showing a method for improving system performance through hardware offload of a BMCA in accordance with some embodiments of the present disclosure.

[0052] As illustrated in FIG.5, the method 500 includes one or more blocks for improving system performance through hardware offload of a BMCA in accordance with some embodiments of the present disclosure. The method 500 may be described in the general context of computer executable instructions. Generally, computer executable instructions can include routines, programs, objects, components, data structures, procedures, modules, and functions, which perform particular functions or implement particular abstract data types.

[0053] The order in which the method 500 is described is not intended to be construed as a limitation, and any number of the described method blocks can be combined in any order to implement the method. Additionally, individual blocks may be deleted from the methods without departing from the scope of the subject matter described herein. Furthermore, the method can be implemented in any suitable hardware, software, firmware, or combination thereof.

[0054] At block 501, the transceiver 315 of the at least one hardware entity 203, 205 receives a plurality of PTP masters from a plurality of master clocks 101, 103. The at least one hardware entity 203, 205 is one of a NIC, network controller, or network adaptor.

[0055] At block 503, the primary BMCA 207 of the at least one hardware entity 203, 205 selects a PTP master as a best PTP master from the plurality of PTP masters. The primary BMCA 207 selects the best PTP master based on at least one of user-configurable designated priority attributes, a clock class attribute, a clock accuracy attribute, and a clock identity attribute.

[0056] At block 505, the transceiver 315 of the at least one hardware entity 203, 205 transmits the best PTP master to the second entity 211 for synchronizing a slave clock.

[0057] Some of the advantages of the present disclosure are listed below.

[0058] The present disclosure offloads software-based BMCA at a second entity to hardware entities, which perform hardware PTP timestamping and allow PTP master selected by a primary BMCA in a hardware entity further to upper layers (i.e., NDD, kernel, and transport layer) within a DU. As a result, the present disclosure (1) allows for better utilization of resources such as hardware entities and second entity within the DU, (2) improves the system performance within the DU, (3) allows RAN vendors to offer better solution with limited hardware resources, and (4) improves overall return on investment per DU and reduces capital expenditure for operators.

[0059] Some of the clauses are mentioned below.

[0060] [1]: A system, comprising at least one hardware entity integrated with a primary Best Master Clock Algorithm (BMCA). The at least one hardware entity is configured to receive a plurality of Precision Time Protocol (PTP) masters from a plurality of PTP master clocks. Thereafter, the at least one hardware entity is configured to select a PTP master as a best PTP master from the plurality of PTP masters using the primary BMCA in the at least one hardware entity and transmit the best PTP master to a second entity for synchronizing a slave clock.

[0061] [2]: The system described in [1], wherein the second entity comprises a secondary BMCA configured to receive at least one best PTP master from the at least one hardware entity. Thereafter, the second entity is configured to select a final best PTP master from the at least one best PTP master and apply the final best PTP master for a slave clock synchronization in a Distributed Unit (DU).

[0062] [3]: The system described in any one of [1] to [2], wherein the at least one hardware entity is configured to timestamp the best PTP master.

[0063] [4]: The system described in any one of [1] to [3], wherein the secondary BMCA and the at least one hardware entity integrated with the primary BMCA are part of a DU for synchronizing the slave clock.

[0064] [5]: The system described in any one of [1] to [4], wherein the primary BMCA and the secondary BMCA selects the best PTP master and the final best PTP master, respectively, based on at least one of user-configurable designated priority attributes, a clock class attribute, a clock accuracy attribute, and a clock identity attribute.

[0065] [6]: The system described in any one of [1] to [5], wherein the at least one hardware entity is one of a Network Interface Card (NIC), network controller, or network adaptor.

[0066] [7]: A method, comprising receiving a plurality of Precision Time Protocol (PTP) masters from a plurality of PTP master clocks. Thereafter, the method comprising selecting a PTP master as a best PTP master from the plurality of PTP masters using a primary Best Master Clock Algorithm (BMCA) in at least one hardware entity and transmitting the best PTP master to a second entity for synchronizing a slave clock.

[0067] [8]: The method described in [7], further comprising receiving at least one best PTP master from the at least one hardware entity, selecting a final best PTP master from the at least one best PTP master using a secondary BMCA, and applying the final best PTP master for a slave clock synchronization in a Distributed Unit (DU).

[0068] [9]: The method described in any one of [7] to [8], wherein selecting the PTP master as the best PTP master from the plurality of PTP masters using the primary BMCA further comprising timestamping the best PTP master.

[0069]

[0010] : The method described in any one of [7] to [9], wherein the secondary BMCA and the at least one hardware entity integrated with the primary BMCA are part of a DU for synchronizing the slave clock.

[0070]

[0011] : The method described in any one of [7] to

[0010] , wherein the primary BMCA and the secondary BMCA selects the best PTP master and the final best PTP master, respectively, based on at least one of user-configurable designated priority attributes, a clock class attribute, a clock accuracy attribute, and a clock identity attribute.

[0071]

[0012] : The method described in any one of [7] to

[0011] , wherein the at least one hardware entity is one of a Network Interface Card (NIC), network controller, or network adaptor.

[0072]

[0013] : A non-transitory computer readable medium including instructions stored thereon that when processed by at least one processor cause at least one hardware entity of a system to perform operations comprising receiving a plurality of Precision Time Protocol (PTP) masters from a plurality of PTP master clocks. Thereafter, the instructions cause the at least one hardware entity to perform operations comprising selecting a PTP master as a best PTP master from the plurality of PTP masters using a primary Best Master Clock Algorithm (BMCA) in the at least one hardware entity, and transmitting the best PTP master to a second entity for synchronizing a slave clock.

[0073]

[0014] : The computer readable medium described in

[0013] , wherein the instructions cause the second entity to perform operations comprising receiving at least one best PTP master from the at least one hardware entity, selecting a final best PTP master from the at least one best PTP master using a secondary BMCA, and applying the final best PTP master for a slave clock synchronization in a Distributed Unit (DU).

[0074]

[0015] : The computer readable medium described in any one of

[0013] to

[0014] , wherein selecting the PTP master as the best PTP master from the plurality of PTP masters using the primary BMCA in the hardware entity comprising timestamping the best PTP master.

[0075]

[0016] : The computer readable medium described in any one of

[0013] to

[0015] , wherein the secondary BMCA and the at least one hardware entity integrated with the primary BMCA are part of a DU for synchronizing the slave clock.

[0076]

[0017] : The computer readable medium described in any one of

[0013] to

[0016] , wherein the primary BMCA and the secondary BMCA selects the best PTP master and the final best PTP master, respectively, based on at least one of user-configurable designated priority attributes, a clock class attribute, a clock accuracy attribute, and a clock identity attribute.

[0077]

[0018] : The computer readable medium described in any one of

[0013] to

[0017] , wherein a hardware entity is one of a Network Interface Card (NIC), network controller, or network adaptor.

[0078] With respect to the use of substantially any plural and singular terms herein, those having skill in the art can translate from the plural to the singular and from the singular to the plural as is appropriate to the context or application. The various singular or plural permutations may be expressly set forth herein for sake of clarity.

[0079] One or more computer-readable storage media may be utilized in implementing embodiments consistent with the present disclosure. A computer-readable storage medium refers to any type of physical memory on which a software (program) readable by an information processing apparatus may be stored. The information processing apparatus includes a processor and a memory, and the processor executes a process of the software. Thus, a computer-readable storage medium may store instructions for execution by one or more processors, including instructions for causing the processor(s) to perform steps or stages consistent with the embodiments described herein. The term “computer-readable medium” should be understood to include tangible items and exclude carrier waves and transient signals, i.e., be non-transitory. Examples include RAM, ROM, volatile memory, non-volatile memory, hard drives, CD ROMs, DVDs, flash drives, disks, and any other known physical storage media.

[0080] The described operations may be implemented as a method, a system, or an article of manufacture using at least one of standard programming and engineering techniques to produce software, firmware, hardware, or any combination thereof. The described operations may be implemented as code maintained in a “non-transitory computer readable medium”, where a processor may read and execute the code from the computer readable medium. The processor is at least one of a microprocessor and a processor capable of processing and executing the queries. A non-transitory computer readable medium may include media such as magnetic storage medium (e.g., hard disk drives, floppy disks, tape, etc.), optical storage (CD-ROMs, DVDs, optical disks, etc.), volatile and non-volatile memory devices (e.g., EEPROMs, ROMs, PROMs, RAMs, DRAMs, SRAMs, Flash Memory, firmware, programmable logic, etc.), etc. Further, non-transitory computer-readable media include all computer-readable media except for a transitory. The code implementing the described operations may further be implemented in hardware logic (e.g., an integrated circuit chip, PGA, ASIC, etc.).

[0081] The terms “an embodiment”, “embodiment”, “embodiments”, “the embodiment”, “the embodiments”, “one or more embodiments”, “some embodiments”, and “one embodiment” mean “one or more (but not all) embodiments of the invention(s)” unless expressly specified otherwise.

[0082] The terms “including”, “comprising”, “having” and variations thereof mean “including but not limited to”, unless expressly specified otherwise.

[0083] The enumerated listing of items does not imply that any or all of the items are mutually exclusive, unless expressly specified otherwise.

[0084] The terms “a”, “an” and “the” mean “one or more”, unless expressly specified otherwise.

[0085] A description of an embodiment with several components in communication with each other does not imply that all such components are required. On the contrary, a variety of optional components are described to illustrate the wide variety of possible embodiments of the invention.

[0086] When a single device or article is described herein, it will be readily apparent that more than one device or article (whether or not they cooperate) may be used in place of a single device or article. Similarly, where more than one device or article is described herein (whether or not they cooperate), it will be readily apparent that a single device or article may be used in place of the more than one device, or article, or a different number of devices or articles may be used instead of the shown number of devices or programs. At least one of the functionalities and the features of a device may be alternatively embodied by one or more other devices which are not explicitly described as having such functionality or features. Thus, other embodiments of the invention need not include the device itself.

[0087] The illustrated operations of FIG. 4 show certain events occurring in a certain order. In alternative embodiments, certain operations may be performed in a different order, modified, or removed. Moreover, steps may be added to the above-described logic and still conform to the described embodiments. Further, operations described herein may occur sequentially or certain operations may be processed in parallel. Yet further, operations may be performed by a single processing unit or by distributed processing units.

[0088] Finally, the language used in the specification has been principally selected for readability and instructional purposes, and it may not have been selected to delineate or circumscribe the inventive subject matter. It is therefore intended that the scope of the invention be limited not by this detailed description, but rather by any claims that issue on an application based here on. Accordingly, the disclosure of the embodiments of the invention is intended to be illustrative, but not limiting, of the scope of the invention, which is set forth in the following claims.

[0089] While various aspects and embodiments have been disclosed herein, other aspects and embodiments will be apparent to those skilled in the art. The various aspects and embodiments disclosed herein are for purposes of illustration and are not intended to be limiting, with the true scope being indicated by the following claims.

[0002] REFERRAL NUMERALS: Reference number Description 101, 103 Grandmaster (GM) clock k

Claims

We Claim:

1. A system, comprising: at least one hardware entity integrated with a primary Best Master Clock Algorithm (BMCA) configured to: receive a plurality of Precision Time Protocol (PTP) masters from a plurality of PTP master clocks; select a PTP master as a best PTP master from the plurality of PTP masters using the primary BMCA in the at least one hardware entity; and transmit the best PTP master to a second entity for synchronizing a slave clock.

2. The system as claimed in claim 1, wherein the second entity comprises a secondary BMCA configured to: receive at least one best PTP master from the at least one hardware entity; select a final best PTP master from the at least one best PTP master; and apply the final best PTP master for a slave clock synchronization in a Distributed Unit (DU).

3. The system as claimed in claim 1, wherein the at least one hardware entity is configured to: timestamp the best PTP master.

4. The system as claimed in claim 2, wherein the secondary BMCA and the at least one hardware entity integrated with the primary BMCA are part of a DU for synchronizing the slave clock.

5. The system as claimed in claim 1, wherein the primary BMCA and the secondary BMCA selects the best PTP master and the final best PTP master, respectively, based on at least one of user-configurable designated priority attributes, a clock class attribute, a clock accuracy attribute, and a clock identity attribute.

6. The system as claimed in claim 1, wherein the at least one hardware entity is one of a Network Interface Card (NIC), network controller, or network adaptor.

7. A method comprising:receiving a plurality of Precision Time Protocol (PTP) masters from a plurality of PTP master clocks; selecting a PTP master as a best PTP master from the plurality of PTP masters using a primary Best Master Clock Algorithm (BMCA) in at least one hardware entity; and transmitting the best PTP master to a second entity for synchronizing a slave clock.

8. The method as claimed in claim 7, further comprising: receiving at least one best PTP master from the at least one hardware entity; selecting a final best PTP master from the at least one best PTP master using a secondary BMCA; and applying the final best PTP master for a slave clock synchronization in a Distributed Unit (DU).

9. The method as claimed in claim 7, wherein selecting the PTP master as the best PTP master from the plurality of PTP masters using the primary BMCA further comprising: timestamping the best PTP master.

10. The method as claimed in claim 8, wherein the secondary BMCA and the at least one hardware entity integrated with the primary BMCA are part of a DU for synchronizing the slave clock.

11. The method as claimed in claim 7, wherein the primary BMCA and the secondary BMCA selects the best PTP master and the final best PTP master, respectively, based on at least one of user-configurable designated priority attributes, a clock class attribute, a clock accuracy attribute, and a clock identity attribute.

12. The method as claimed in claim 7, wherein the at least one hardware entity is one of a Network Interface Card (NIC), network controller, or network adaptor.

13. A non-transitory computer readable medium including instructions stored thereon that when processed by at least one processor cause at least one hardware entity to perform operations comprising: receiving a plurality of Precision Time Protocol (PTP) masters from a plurality of PTP master clocks;selecting a PTP master as a best PTP master from the plurality of PTP masters using a primary Best Master Clock Algorithm (BMCA) in the at least one hardware entity; and transmitting the best PTP master to a second entity for synchronizing a slave clock.

14. The computer readable medium as claimed in claim 13, wherein the instructions cause the second entity to perform operations comprising: receiving at least one best PTP master from the at least one hardware entity; selecting a final best PTP master from the at least one best PTP master using a secondary BMCA; and applying the final best PTP master for a slave clock synchronization in a Distributed Unit (DU).

15. The computer readable medium as claimed in claim 13, wherein selecting the PTP master as the best PTP master from the plurality of PTP masters using the primary BMCA comprising: timestamping the best PTP master.

16. The computer readable medium as claimed in claim 14, wherein the secondary BMCA and the at least one hardware entity integrated with the primary BMCA are part of a DU for synchronizing the slave clock.

17. The computer readable medium as claimed in claim 13, wherein the primary BMCA and the secondary BMCA selects the best PTP master and the final best PTP master, respectively, based on at least one of user-configurable designated priority attributes, a clock class attribute, a clock accuracy attribute, and a clock identity attribute.

18. The computer readable medium as claimed in claim 13, wherein the at least one hardware entity is one of a Network Interface Card (NIC), network controller, or network adaptor.

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