Smart resolution graphics rendering based on graphics memory size

Abstract

Aspects presented herein relate to methods and devices for graphics processing including an apparatus, e.g., a graphics processor. The apparatus may obtain a first indication of at least one render target in a set of render targets for a frame, where the at least one render target includes an initial size of the at least one render target. The apparatus may also determine an updated size of the at least one render target for the frame. Further, the apparatus may output a second indication of the updated size of the at least one render target for the frame. The apparatus may also load the at least one render target including the updated size.

Description

Qualcomm Ref. No. 2404924WO 1SMART RESOLUTION GRAPHICS RENDERINGBASED ON GRAPHICS MEMORY SIZECROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims the benefit of India Patent Application Serial No. 202441067746, entitled “SMART RESOLUTION GRAPHICS RENDERING BASED ON GRAPHICS MEMORY SIZE” and filed on September 7, 2024, which is expressly incorporated by reference herein in its entirety.TECHNICAL FIELD

[0002] The present disclosure relates generally to processing systems and, more particularly, to one or more techniques for graphics processing.INTRODUCTION

[0003] Computing devices often perform graphics and / or display processing (e.g., utilizing a graphics processing unit (GPU), a central processing unit (CPU), a display processor, etc.) to render and display visual content. Such computing devices may include, for example, computer workstations, mobile phones such as smartphones, embedded systems, personal computers, tablet computers, and video game consoles. GPUs are configured to execute a graphics processing pipeline that includes one or more processing stages, which operate together to execute graphics processing commands and output a frame. A central processing unit (CPU) may control the operation of the GPU by issuing one or more graphics processing commands to the GPU. Modern day CPUs are typically capable of executing multiple applications concurrently, each of which may need to utilize the GPU during execution. A display processor is configured to convert digital information received from a CPU to analog values and may issue commands to a display panel for displaying the visual content. A device that provides content for visual presentation on a display may utilize a GPU and / or a display processor or display processing unit (DPU).

[0004] A graphics processor of a device may be configured to perform the processes in a graphics processing pipeline. Further, graphics processors may be utilized to perform graphics rendering. However, there has developed an increased need for improved rendering in graphics processing.129025-2387WO01Qualcomm Ref. No. 2404924WO 2BRIEF SUMMARY

[0005] The following presents a simplified summary of one or more aspects in order to provide a basic understanding of such aspects. This summary is not an extensive overview of all contemplated aspects, and is intended to neither identify key or critical elements of all aspects nor delineate the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed description that is presented later.

[0006] In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be a graphics processor, a graphics processing unit (GPU), a neural processing unit (NPU), a central processing unit (CPU), or any apparatus that may perform for graphics processing. The apparatus may obtain a first indication of at least one render target in a set of render targets for a frame, where the at least one render target includes an initial size of the at least one render target. The apparatus may also determine an updated size of the at least one render target for the frame. The apparatus may also output a second indication of the updated size of the at least one render target for the frame. Additionally, the apparatus may load the at least one render target including the updated size. The apparatus may also perform a render process for the at least one render target including the updated size. Moreover, the apparatus may store, based on the render process, the at least one render target including the updated size. The apparatus may also determine a size adjustment from the updated size of the at least one render target to the initial size of the at least one render target. The apparatus may also output a third indication of the size adjustment from the updated size of the at least one render target to the initial size of the at least one render target. Further, the apparatus may obtain a fourth indication of the at least one render target including the initial size.

[0007] The details of one or more examples of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the disclosure will be apparent from the description and drawings, and from the claims.BRIEF DESCRIPTION OF DRAWINGS

[0008] FIG. 1 is a block diagram that illustrates an example content generation system in accordance with one or more techniques of this disclosure.129025-2387WO01Qualcomm Ref. No. 2404924WO 3

[0009] FIG. 2 illustrates an example graphics processing unit (GPU) in accordance with one or more techniques of this disclosure.

[0010] FIG. 3 is a diagram illustrating example processing components in accordance with one or more techniques of this disclosure.

[0011] FIG. 4 is a diagram illustrating an example image or surface in accordance with one or more techniques of this disclosure.

[0012] FIG. 5 is a diagram illustrating an example geometry pipeline in accordance with one or more techniques of this disclosure.

[0013] FIG. 6 is a diagram illustrating an example GPU hardware in accordance with one or more techniques of this disclosure.

[0014] FIG. 7 is a diagram illustrating an example execution sequence in accordance with one or more techniques of this disclosure.

[0015] FIG. 8 is a diagram illustrating an example rendering sequence in accordance with one or more techniques of this disclosure.

[0016] FIG. 9 is a diagram illustrating example render targets in accordance with one or more techniques of this disclosure.

[0017] FIG. 10 is a diagram illustrating an example rendering sequence in accordance with one or more techniques of this disclosure.

[0018] FIG. 11 is a diagram illustrating an example upscale process in accordance with one or more techniques of this disclosure.

[0019] FIG. 12 is a communication flow diagram illustrating example communications between a GPU, a neural processing unit (NPU) / GPU, and a memory in accordance with one or more techniques of this disclosure.

[0020] FIG. 13 is a flowchart of an example method of graphics processing in accordance with one or more techniques of this disclosure.

[0021] FIG. 14 is a flowchart of an example method of graphics processing in accordance with one or more techniques of this disclosure.DETAILED DESCRIPTION

[0022] In some aspects, certain types of graphics applications, such as high-end applications or games in certain application program interfaces (APIs) (e.g., DirectX (DX)), may use a large render target (RT). That is, these applications may use a large render target view (RTV) or frame buffer objects that cannot be fully loaded to certain types of memory (e.g., graphics memory (GMEM)). A render target (RT) may be a target129025-2387WO01Qualcomm Ref. No. 2404924WO 4 block of pixels (e.g., a buffer) into which rendering may occur. In some aspects, a render target may refer to a buffer where the pixels are drawn (e.g., a video card draws pixels) for a scene that is being rendered in the background. In some instances, these graphics applications may currently divide the render target (RT) into multiple bins and proceed with rendering (e.g., visibility binning (vizbinning)). However, these multiple bins may increase the amount of overhead of many types of applications. That is, the use of multiple bins during rendering increases the time needed to perform all of the rendering for an image or frame, as the image is divided into multiple bins and each successive bin increases the time needed for rendering. In turn, this may increase the corresponding overhead associated with this type of rendering. Some types of GPUs may perform binning rendering, which renders a frame on a bin-by- bin basis. Another type of rendering is direct rendering, which does not use certain types of memory (e.g., GMEM) for render targets. As opposed to rendering a frame bin-by-bin (as in a binning rendering mode), a direct rendering mode may render an entire frame in one pass through a graphics pipeline. Also, many of these applications or games may perform better with a type of rendering that reduce the number of bins. For example, many applications or games may perform better with direct rendering (rather than bin rendering) due to the overhead of multiple bins that adds to a load and store time. In some aspects (e.g., direct 3D use cases), visibility binning (vizbinning) may have additional overhead due to a large number of bins. Additionally, certain binning modes (e.g., hardware binning mode) may have an increased number of bins, which results in a corresponding increase in rendering time. Further, the render time of certain types of rendering (e.g., direct rendering (DR)) may be lower than other types of binning rendering (e.g., visibility binning). Aspects of the present disclosure perform certain types of rendering (e.g., direct rendering) because of the decreased number of bins compared to other types of rendering (e.g., binning rendering), which may result in a reduced amount of overhead at a GPU.

[0023] Aspects of the present disclosure may include a number of benefits or advantages. For instance, aspects of the present disclosure may reduce the number of bins (e.g., the bins in hardware binning mode) in order to reduce the amount of time for rendering at a GPU. Aspects presented herein may also perform certain types of rendering (e.g., direct rendering) because of the decreased number of bins compared to other types of rendering (e.g., binning rendering), which may result in a reduced amount of overhead at a GPU. Also, aspects presented herein may reduce the129025-2387WO01Qualcomm Ref. No. 2404924WO 5 complexity of the image / frame for rendering. For example, aspects presented herein may reduce the render target (RT) size for rendering. That is, aspects presented herein may reduce the RT size, such that it fits in a memory (e.g., GMEM) as a single bin. By doing so, aspects presented herein may reduce the amount of time for rendering at a GPU. Further, aspects presented herein may reduce the load store time. Aspects presented herein may reduce the number of bins (e.g., the bins in hardware binning mode), in order to reduce the amount of time for rendering, reduce the complexity of the image for rendering, as well as reduce the load store time. Additionally, aspects presented herein may achieve a frames-per-second (FPS) improvement (e.g., a universal FPS improvement up to 20%) due to the faster render time and the reduced workload size.

[0024] Various aspects of systems, apparatuses, computer program products, and methods are described more fully hereinafter with reference to the accompanying drawings. This disclosure may, however, be embodied in many different forms and should not be construed as limited to any specific structure or function presented throughout this disclosure. Rather, these aspects are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art. Based on the teachings herein one skilled in the art should appreciate that the scope of this disclosure is intended to cover any aspect of the systems, apparatuses, computer program products, and methods disclosed herein, whether implemented independently of, or combined with, other aspects of the disclosure. For example, an apparatus may be implemented or a method may be practiced using any number of the aspects set forth herein. In addition, the scope of the disclosure is intended to cover such an apparatus or method which is practiced using other structure, functionality, or structure and functionality in addition to or other than the various aspects of the disclosure set forth herein. Any aspect disclosed herein may be embodied by one or more elements of a claim.

[0025] Although various aspects are described herein, many variations and permutations of these aspects fall within the scope of this disclosure. Although some potential benefits and advantages of aspects of this disclosure are mentioned, the scope of this disclosure is not intended to be limited to particular benefits, uses, or objectives. Rather, aspects of this disclosure are intended to be broadly applicable to different wireless technologies, system configurations, networks, and transmission protocols, some of which are illustrated by way of example in the figures and in the following129025-2387WO01Qualcomm Ref. No. 2404924WO 6 description. The detailed description and drawings are merely illustrative of this disclosure rather than limiting, the scope of this disclosure being defined by the appended claims and equivalents thereof.

[0026] Several aspects are presented with reference to various apparatus and methods. These apparatus and methods are described in the following detailed description and illustrated in the accompanying drawings by various blocks, components, circuits, processes, algorithms, and the like (collectively referred to as “elements”). These elements may be implemented using electronic hardware, computer software, or any combination thereof. Whether such elements are implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system.

[0027] By way of example, an element, or any portion of an element, or any combination of elements may be implemented as a “processing system” that includes one or more processors (which may also be referred to as processing units). Examples of processors include microprocessors, microcontrollers, graphics processing units (GPUs), general purpose GPUs (GPGPUs), central processing units (CPUs), application processors, digital signal processors (DSPs), reduced instruction set computing (RISC) processors, systems-on-chip (SOC), baseband processors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functionality described throughout this disclosure. One or more processors in the processing system may execute software. Software may be construed broadly to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software components, applications, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. The term application may refer to software. As described herein, one or more techniques may refer to an application, i.e., software, being configured to perform one or more functions. In such examples, the application may be stored on a memory, e.g., on-chip memory of a processor, system memory, or any other memory. Hardware described herein, such as a processor may be configured to execute the application. For example, the application may be described as including code that, when executed by the hardware,129025-2387WO01Qualcomm Ref. No. 2404924WO 7 causes the hardware to perform one or more techniques described herein. As an example, the hardware may access the code from a memory and execute the code accessed from the memory to perform one or more techniques described herein. In some examples, components are identified in this disclosure. In such examples, the components may be hardware, software, or a combination thereof. The components may be separate components or sub-components of a single component.

[0028] Accordingly, in one or more examples described herein, the functions described may be implemented in hardware, software, or any combination thereof. If implemented in software, the functions may be stored on or encoded as one or more instructions or code on a computer-readable medium. Computer-readable media includes computer storage media. Storage media may be any available media that may be accessed by a computer. By way of example, and not limitation, such computer-readable media may comprise a random access memory (RAM), a read-only memory (ROM), an electrically erasable programmable ROM (EEPROM), optical disk storage, magnetic disk storage, other magnetic storage devices, combinations of the aforementioned types of computer-readable media, or any other medium that may be used to store computer executable code in the form of instructions or data structures that may be accessed by a computer.

[0029] In general, this disclosure describes techniques for having a graphics processing pipeline in a single device or multiple devices, improving the rendering of graphical content, and / or reducing the load of a processing unit, i.e., any processing unit configured to perform one or more techniques described herein, such as a GPU. For example, this disclosure describes techniques for graphics processing in any device that utilizes graphics processing. Other example benefits are described throughout this disclosure.

[0030] As used herein, instances of the term “content” may refer to “graphical content,” “image,” and vice versa. This is true regardless of whether the terms are being used as an adjective, noun, or other parts of speech. In some examples, as used herein, the term “graphical content” may refer to a content produced by one or more processes of a graphics processing pipeline. In some examples, as used herein, the term “graphical content” may refer to a content produced by a processing unit configured to perform graphics processing. In some examples, as used herein, the term “graphical content” may refer to a content produced by a graphics processing unit.129025-2387WO01Qualcomm Ref. No. 2404924WO 8

[0031] In some examples, as used herein, the term “display content” may refer to content generated by a processing unit configured to perform displaying processing. In some examples, as used herein, the term “display content” may refer to content generated by a display processing unit. Graphical content may be processed to become display content. For example, a graphics processing unit may output graphical content, such as a frame, to a buffer (which may be referred to as a framebuffer). A display processing unit may read the graphical content, such as one or more frames from the buffer, and perform one or more display processing techniques thereon to generate display content. For example, a display processing unit may be configured to perform composition on one or more rendered layers to generate a frame. As another example, a display processing unit may be configured to compose, blend, or otherwise combine two or more layers together into a single frame. A display processing unit may be configured to perform scaling, e.g., upscaling or downscaling, on a frame. In some examples, a frame may refer to a layer. In other examples, a frame may refer to two or more layers that have already been blended together to form the frame, i.e., the frame includes two or more layers, and the frame that includes two or more layers may subsequently be blended. In some examples, as used herein, the term “graphics workload” may refer to any workload or order associated with graphics processing. In some examples, as used herein, the term “texture fetch” may refer to a memory request, which incurs transactions from a cache (e.g., a texture cache). Each time a warp executes a texture function to read from texture memory, this may be a single texture fetch. Also, texture memory may be read-only device memory, and may be accessed using the device functions described in a texture function. Reading a texture using one of these functions may be called a “texture fetch.” A “render target” may refer to a target block of pixels (buffer) into which rendering will occur. In some aspects, a render target may refer to a buffer where the pixels are drawn (e.g., a video card draws pixels) for a scene that is being rendered in the background. An intermediate render target may refer to a render target that is used in post-processing.

[0032] FIG. 1 is a block diagram that illustrates an example content generation system 100 configured to implement one or more techniques of this disclosure. The content generation system 100 includes a device 104. The device 104 may include one or more components or circuits for performing various functions described herein. In some examples, one or more components of the device 104 may be components of an SOC. The device 104 may include one or more components configured to perform129025-2387WO01Qualcomm Ref. No. 2404924WO 9 one or more techniques of this disclosure. In the example shown, the device 104 may include a processing unit 120, a content encoder / decoder 122, and a system memory 124. In some aspects, the device 104 may include a number of components, e.g., a communication interface 126, a transceiver 132, a receiver 128, a transmitter 130, a display processor 127, and one or more displays 131. Reference to the display 131 may refer to the one or more displays 131. For example, the display 131 may include a single display or multiple displays. The display 131 may include a first display and a second display. The first display may be a left-eye display and the second display may be a right-eye display. In some examples, the first and second display may receive different frames for presentment thereon. In other examples, the first and second display may receive the same frames for presentment thereon. In further examples, the results of the graphics processing may not be displayed on the device, e.g., the first and second display may not receive any frames for presentment thereon. Instead, the frames or graphics processing results may be transferred to another device. In some aspects, this may be referred to as split-rendering.

[0033] The processing unit 120 may include an internal memory 121. The processing unit 120 may be configured to perform graphics processing, such as in a graphics processing pipeline 107. The content encoder / decoder 122 may include an internal memory 123. In some examples, the device 104 may include a display processor, such as the display processor 127, to perform one or more display processing techniques on one or more frames generated by the processing unit 120 before presentment by the one or more displays 131. The display processor 127 may be configured to perform display processing. For example, the display processor 127 may be configured to perform one or more display processing techniques on one or more frames generated by the processing unit 120. The one or more displays 131 may be configured to display or otherwise present frames processed by the display processor 127. In some examples, the one or more displays 131 may include one or more of a liquid crystal display (LCD), a plasma display, an organic light emitting diode (OLED) display, a projection display device, an augmented reality display device, a virtual reality display device, a head-mounted display, or any other type of display device.

[0034] Memory external to the processing unit 120 and the content encoder / decoder 122, such as system memory 124, may be accessible to the processing unit 120 and the content encoder / decoder 122. For example, the processing unit 120 and the content129025-2387WO01Qualcomm Ref. No. 2404924WO 10 encoder / decoder 122 may be configured to read from and / or write to external memory, such as the system memory 124. The processing unit 120 and the content encoder / decoder 122 may be communicatively coupled to the system memory 124 over a bus. In some examples, the processing unit 120 and the content encoder / decoder 122 may be communicatively coupled to each other over the bus or a different connection.

[0035] The content encoder / decoder 122 may be configured to receive graphical content from any source, such as the system memory 124 and / or the communication interface 126. The system memory 124 may be configured to store received encoded or decoded graphical content. The content encoder / decoder 122 may be configured to receive encoded or decoded graphical content, e.g., from the system memory 124 and / or the communication interface 126, in the form of encoded pixel data. The content encoder / decoder 122 may be configured to encode or decode any graphical content.

[0036] The internal memory 121 or the system memory 124 may include one or more volatile or non-volatile memories or storage devices. In some examples, internal memory 121 or the system memory 124 may include RAM, SRAM, DRAM, erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, a magnetic data media or an optical storage media, or any other type of memory.

[0037] The internal memory 121 or the system memory 124 may be a non-transitory storage medium according to some examples. The term “non-transitory” may indicate that the storage medium is not embodied in a carrier wave or a propagated signal. However, the term “non-transitory” should not be interpreted to mean that internal memory 121 or the system memory 124 is non-movable or that its contents are static. As one example, the system memory 124 may be removed from the device 104 and moved to another device. As another example, the system memory 124 may not be removable from the device 104.

[0038] The processing unit 120 may be a central processing unit (CPU), a graphics processing unit (GPU), a general purpose GPU (GPGPU), or any other processing unit that may be configured to perform graphics processing. In some examples, the processing unit 120 may be integrated into a motherboard of the device 104. In some examples, the processing unit 120 may be present on a graphics card that is installed in a port in a motherboard of the device 104, or may be otherwise incorporated within a peripheral device configured to interoperate with the device 104. The processing129025-2387WO01Qualcomm Ref. No. 2404924WO 11 unit 120 may include one or more processors, such as one or more microprocessors, GPUs, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), arithmetic logic units (ALUs), digital signal processors (DSPs), discrete logic, software, hardware, firmware, other equivalent integrated or discrete logic circuitry, or any combinations thereof. If the techniques are implemented partially in software, the processing unit 120 may store instructions for the software in a suitable, non-transitory computer-readable storage medium, e.g., internal memory 121, and may execute the instructions in hardware using one or more processors to perform the techniques of this disclosure. Any of the foregoing, including hardware, software, a combination of hardware and software, etc., may be considered to be one or more processors.

[0039] The content encoder / decoder 122 may be any processing unit configured to perform content decoding. In some examples, the content encoder / decoder 122 may be integrated into a motherboard of the device 104. The content encoder / decoder 122 may include one or more processors, such as one or more microprocessors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), arithmetic logic units (ALUs), digital signal processors (DSPs), video processors, discrete logic, software, hardware, firmware, other equivalent integrated or discrete logic circuitry, or any combinations thereof. If the techniques are implemented partially in software, the content encoder / decoder 122 may store instructions for the software in a suitable, non-transitory computer-readable storage medium, e.g., internal memory 123, and may execute the instructions in hardware using one or more processors to perform the techniques of this disclosure. Any of the foregoing, including hardware, software, a combination of hardware and software, etc., may be considered to be one or more processors.

[0040] In some aspects, the content generation system 100 may include a communication interface 126. The communication interface 126 may include a receiver 128 and a transmitter 130. The receiver 128 may be configured to perform any receiving function described herein with respect to the device 104. Additionally, the receiver 128 may be configured to receive information, e.g., eye or head position information, rendering commands, or location information, from another device. The transmitter 130 may be configured to perform any transmitting function described herein with respect to the device 104. For example, the transmitter 130 may be configured to transmit information to another device, which may include a request for content. The129025-2387WO01Qualcomm Ref. No. 2404924WO 12 receiver 128 and the transmitter 130 may be combined into a transceiver 132. In such examples, the transceiver 132 may be configured to perform any receiving function and / or transmitting function described herein with respect to the device 104.

[0041] Referring again to FIG. 1, in certain aspects, the processing unit 120 may include a rendering component 198 configured to obtain a first indication of at least one render target in a set of render targets for a frame, where the at least one render target includes an initial size of the at least one render target. The rendering component 198 may also be configured to determine an updated size of the at least one render target for the frame. The rendering component 198 may also be configured to output a second indication of the updated size of the at least one render target for the frame. The rendering component 198 may also be configured to load the at least one render target including the updated size. The rendering component 198 may also be configured to perform a render process for the at least one render target including the updated size. The rendering component 198 may also be configured to store, based on the render process, the at least one render target including the updated size. The rendering component 198 may also be configured to determine a size adjustment from the updated size of the at least one render target to the initial size of the at least one render target. The rendering component 198 may also be configured to output a third indication of the size adjustment from the updated size of the at least one render target to the initial size of the at least one render target. The rendering component 198 may also be configured to obtain a fourth indication of the at least one render target including the initial size. Although the following description may be focused on display processing, the concepts described herein may be applicable to other similar processing techniques.

[0042] As described herein, a device, such as the device 104, may refer to any device, apparatus, or system configured to perform one or more techniques described herein. For example, a device may be a server, a base station, user equipment, a client device, a station, an access point, a computer, e.g., a personal computer, a desktop computer, a laptop computer, a tablet computer, a computer workstation, or a mainframe computer, an end product, an apparatus, a phone, a smart phone, a server, a video game platform or console, a handheld device, e.g., a portable video game device or a personal digital assistant (PDA), a wearable computing device, e.g., a smart watch, an augmented reality device, or a virtual reality device, a non-wearable device, a display or display device, a television, a television set-top box, an intermediate129025-2387WO01Qualcomm Ref. No. 2404924WO 13 network device, a digital media player, a video streaming device, a content streaming device, an in-car computer, any mobile device, any device configured to generate graphical content, or any device configured to perform one or more techniques described herein. Processes herein may be described as performed by a particular component (e.g., a GPU), but, in further embodiments, may be performed using other components (e.g., a CPU), consistent with disclosed embodiments.

[0043] GPUs may process multiple types of data or data packets in a GPU pipeline. For instance, in some aspects, a GPU may process two types of data or data packets, e.g., context register packets and draw call data. A context register packet may be a set of global state information, e.g., information regarding a global register, shading program, or constant data, which may regulate how a graphics context will be processed. For example, context register packets may include information regarding a color format. In some aspects of context register packets, there may be a bit that indicates which workload belongs to a context register. Also, there may be multiple functions or programming running at the same time and / or in parallel. For example, functions or programming may describe a certain operation, e.g., the color mode or color format. Accordingly, a context register may define multiple states of a GPU.

[0044] Context states may be utilized to determine how an individual processing unit functions, e.g., a vertex fetcher (VFD), a vertex shader (VS), a shader processor, or a geometry processor, and / or in what mode the processing unit functions. In order to do so, GPUs may use context registers and programming data. In some aspects, a GPU may generate a workload, e.g., a vertex or pixel workload, in the pipeline based on the context register definition of a mode or state. Certain processing units, e.g., a VFD, may use these states to determine certain functions, e.g., how a vertex is assembled. As these modes or states may change, GPUs may need to change the corresponding context. Additionally, the workload that corresponds to the mode or state may follow the changing mode or state.

[0045] FIG. 2 illustrates an example GPU 200 in accordance with one or more techniques of this disclosure. As shown in FIG. 2, GPU 200 includes command processor (CP) 210, draw call packets 212, VFD 220, VS 222, vertex cache (VPC) 224, triangle setup engine (TSE) 226, rasterizer (RAS) 228, Z process engine (ZPE) 230, pixel interpolator (PI) 232, fragment shader (FS) 234, render backend (RB) 236, level 1 (LI) cache (cluster cache (CCHE)) 237, level 2 (L2) cache (UCHE) 238, and system memory 240. Although FIG. 2 displays that GPU 200 includes processing units 220-129025-2387WO01Qualcomm Ref. No. 2404924WO 14238, GPU 200 may include a number of additional processing units. Additionally, processing units 220-238 are merely an example and any combination or order of processing units may be used by GPUs according to the present disclosure. GPU 200 also includes command buffer 250, context register packets 260, and context states 261.

[0046] As shown in FIG. 2, a GPU may utilize a CP, e.g., CP 210, or hardware accelerator to parse a command buffer into context register packets, e.g., context register packets 260, and / or draw call data packets, e.g., draw call packets 212. The CP 210 may then send the context register packets 260 or draw call packets 212 through separate paths to the processing units or blocks in the GPU. Further, the command buffer 250 may alternate different states of context registers and draw calls. For example, a command buffer may be structured in the following manner: context register of context N, draw call(s) of context N, context register of context N+l, and draw call(s) of context N+l .

[0047] GPUs may render images in a variety of different ways. In some instances, GPUs may render an image using rendering and / or tiled rendering. In tiled rendering GPUs, an image may be divided or separated into different sections or tiles. After the division of the image, each section or tile may be rendered separately. Tiled rendering GPUs may divide computer graphics images into a grid format, such that each portion of the grid, i.e., a tile, is separately rendered. In some aspects, during a binning pass, an image may be divided into different bins or tiles. In some aspects, during the binning pass, a visibility stream may be constructed where visible primitives or draw calls may be identified. In contrast to tiled rendering, direct rendering does not divide the frame into smaller bins or tiles. Rather, in direct rendering, the entire frame is rendered at a single time. Additionally, some types of GPUs may allow for both tiled rendering and direct rendering.

[0048] Instructions executed by a CPU (e.g., software instructions) or a display processor may cause the CPU or the display processor to search for and / or generate a composition strategy for composing a frame based on a dynamic priority and runtime statistics associated with one or more composition strategy groups. A frame to be displayed by a physical display device, such as a display panel, may include a plurality of layers. Also, composition of the frame may be based on combining the plurality of layers into the frame (e.g., based on a frame buffer). After the plurality of layers are combined into the frame, the frame may be provided to the display panel for display thereon. The process of combining each of the plurality of layers into the129025-2387WO01Qualcomm Ref. No. 2404924WO 15 frame may be referred to as composition, frame composition, a composition procedure, a composition process, or the like.

[0049] A frame composition procedure or composition strategy may correspond to a technique for composing different layers of the plurality of layers into a single frame. The plurality of layers may be stored in double data rate (DDR) memory. Each layer of the plurality of layers may further correspond to a separate buffer. A composer or hardware composer (HWC) associated with a block or function may determine an input of each layer / buffer and perform the frame composition procedure to generate an output indicative of a composed frame. That is, the input may be the layers and the output may be a frame composition procedure for composing the frame to be displayed on the display panel.

[0050] Some types of GPUs may include different types of pipelines, such as a graphics processing pipeline. Graphics processing pipelines may include one or more of a vertex shader stage, a hull shader stage, a domain shader stage, a geometry shader stage, and a pixel shader stage. These stages of the graphics processing pipeline may be considered shader stages. These shader stages may be implemented as one or more shader programs that execute on shader units at a GPU. Shader units may be configured as a programmable pipeline of processing components. In some examples, a shader unit may be referred to as “shader processors” or “unified shaders,” and may perform geometry, vertex, pixel, or other shading operations to render graphics. Shader units may include shader processors, each of which may include one or more components for fetching and decoding operations, one or more arithmetic logic units (ALUs) for carrying out arithmetic calculations, one or more memories, caches, and registers.

[0051] FIG. 3 is a diagram 300 that illustrates processing components, such as the processing unit 120 and the system memory 124, as may be identified in connection with the device 104 for processing data. In aspects, the processing unit 120 may include a CPU 302 and a GPU 312. The GPU 312 and the CPU 302 may be formed as an integrated circuit (e.g., a system-on-a-chip (SOC)) and / or the GPU 312 may be incorporated onto a motherboard with the CPU 302. Alternatively, the CPU 302 and the GPU 312 may be configured as distinct processing units that are communicatively coupled to each other. For example, the GPU 312 may be incorporated on a graphics card that is installed in a port of the motherboard that includes the CPU 302.129025-2387WO01Qualcomm Ref. No. 2404924WO 16

[0052] The CPU 302 may be configured to execute a software application that causes graphical content to be displayed (e.g., on the display(s) 131 of the device 104) based on one or more operations of the GPU 312. The software application may issue instructions to a graphics application program interface (API) 304, which may be a runtime program that translates instructions received from the software application into a format that is readable by a GPU driver 310. After receiving instructions from the software application via the graphics API 304, the GPU driver 310 may control an operation of the GPU 312 based on the instructions. For example, the GPU driver 310 may generate one or more command streams that are placed into the system memory 124, where the GPU 312 is instructed to execute the command streams (e.g., via one or more system calls). A command engine 314 included in the GPU 312 is configured to retrieve the one or more commands stored in the command streams. The command engine 314 may provide commands from the command stream for execution by the GPU 312. The command engine 314 may be hardware of the GPU 312, software / firmware executing on the GPU 312, or a combination thereof. While the GPU driver 310 is configured to implement the graphics API 304, the GPU driver 310 is not limited to being configured in accordance with any particular API. The system memory 124 may store the code for the GPU driver 310, which the CPU 302 may retrieve for execution. In examples, the GPU driver 310 may be configured to allow communication between the CPU 302 and the GPU 312, such as when the CPU 302 offloads graphics or non-graphics processing tasks to the GPU 312 via the GPU driver 310.

[0053] The system memory 124 may further store source code for one or more of an early preamble shader 324, a feedback shader 325, or a main shader 326. In such configurations, a shader compiler 308 executing on the CPU 302 may compile the source code of the shaders 324-326 to create object code or intermediate code executable by a shader core 316 of the GPU 312 during runtime (e.g., at the time when the shaders 324-326 are to be executed on the shader core 316). In some examples, the shader compiler 308 may pre-compile the shaders 324-326 and store the object code or intermediate code of the shader programs in the system memory 124. The shader compiler 308 (or in another example the GPU driver 310) executing on the CPU 302 may build a shader program with multiple components including the early preamble shader 324, the feedback shader 325, and the main shader 326. The main shader 326 may correspond to a portion or the entirety of the shader program that does129025-2387WO01Qualcomm Ref. No. 2404924WO 17 not include the early preamble shader 324 or the feedback shader 325. The shader compiler 308 may receive instructions to compile the shader(s) 324-326 from a program executing on the CPU 302. The shader compiler 308 may also identify constant load instructions and common operations in the shader program for including the common operations within the early preamble shader 324 (rather than the main shader 326). The shader compiler 308 may identify such common instructions, for example, based on (presently undetermined) constants 306 to be included in the common instructions. The constants 306 may be defined within the graphics API 304 to be constant across an entire draw call. The shader compiler 308 may utilize instructions such as a preamble shader start to indicate a beginning of the early preamble shader 324 and a preamble shader end to indicate an end of the early preamble shader 324. Similar instructions may be used for the feedback shader 325 and the main shader 326. The feedback shader 325 will be described in further detail below.

[0054] The shader core 316 included in the GPU 312 may include general purpose registers (GPRs) 318 and constant memory 320. The GPRs 318 may correspond to a single GPR, a GPR file, and / or a GPR bank. Each GPR in the GPRs 318 may store data accessible to a single thread. The software and / or firmware executing on GPU 312 may be a shader program 324-326, which may execute on the shader core 316 of GPU 312. The shader core 316 may be configured to execute many instances of the same instructions of the same shader program in parallel. For example, the shader core 316 may execute the main shader 326 for each pixel that defines a given shape. The shader core 316 may transmit and receive data from applications executing on the CPU 302. In examples, constants 306 used for execution of the shaders 324-326 may be stored in a constant memory 320 (e.g., a read / write constant RAM) or the GPRs 318. The shader core 316 may load the constants 306 into the constant memory 320. In further examples, execution of the early preamble shader 324 or the feedback shader 325 may cause a constant value or a set of constant values to be stored in on-chip memory such as the constant memory 320 (e.g., constant RAM), the GPU memory 322, or the system memory 124. The constant memory 320 may include memory accessible by all aspects of the shader core 316 rather than just a particular portion reserved for a particular thread such as values held in the GPRs 318.

[0055] GPUs can render images in a variety of different ways. In some instances, GPUs can render an image using rendering and / or tiled rendering. In tiled rendering GPUs, an129025-2387WO01Qualcomm Ref. No. 2404924WO 18 image can be divided or separated into different sections or tiles. After the division of the image, each section or tile can be rendered separately. Tiled rendering GPUs can divide computer graphics images into a grid format, such that each portion of the grid, i.e., a tile, is separately rendered. In some aspects, during a binning pass, an image can be divided into different bins or tiles. In some aspects, during the binning pass, a visibility stream can be constructed where visible primitives or draw calls can be identified. In contrast to tiled rendering, direct rendering does not divide the frame into smaller bins or tiles. Rather, in direct rendering, the entire frame is rendered at a single time. Additionally, some types of GPUs can allow for both tiled rendering and direct rendering.

[0056] In some aspects, GPUs can apply the drawing or rendering process to different bins or tiles. For instance, a GPU can render to one bin, and perform all the draws for the primitives or pixels in the bin. During the process of rendering to a bin, the render targets can be located in the GMEM. In some instances, after rendering to one bin, the content of the render targets can be moved to a system memory and the GMEM can be freed for rendering the next bin. Additionally, a GPU can render to another bin, and perform the draws for the primitives or pixels in that bin. Therefore, in some aspects, there might be a small number of bins, e.g., four bins, that cover all of the draws in one surface. Further, GPUs can cycle through all of the draws in one bin, but perform the draws for the draw calls that are visible, i.e., draw calls that include visible geometry. In some aspects, a visibility stream can be generated, e.g., in a binning pass, to determine the visibility information of each primitive in an image or scene. For instance, this visibility stream can identify whether a certain primitive is visible or not. In some aspects, this information can be used to remove primitives that are not visible, e.g., in the rendering pass. Also, at least some of the primitives that are identified as visible can be rendered in the rendering pass.

[0057] In some aspects of tiled rendering, there can be multiple processing phases or passes. For instance, the rendering can be performed in two passes, e.g., a visibility or binvisibility pass and a rendering or bin-rendering pass. During a visibility pass, a GPU can input a rendering workload, record the positions of the primitives or triangles, and then determine which primitives or triangles fall into which bin or area. In some aspects of a visibility pass, GPUs can also identify or mark the visibility of each primitive or triangle in a visibility stream. During a rendering pass, a GPU can input the visibility stream and process one bin or area at a time. In some aspects, the129025-2387WO01Qualcomm Ref. No. 2404924WO 19 visibility stream can be analyzed to determine which primitives, or vertices of primitives, are visible or not visible. As such, the primitives, or vertices of primitives, that are visible may be processed. By doing so, GPUs can reduce the unnecessary workload of processing or rendering primitives or triangles that are not visible.

[0058] In some aspects, during a visibility pass, certain types of primitive geometry, e.g., position-only geometry, may be processed. Additionally, depending on the position or location of the primitives or triangles, the primitives may be sorted into different bins or areas. In some instances, sorting primitives or triangles into different bins may be performed by determining visibility information for these primitives or triangles. For example, GPUs may determine or write visibility information of each primitive in each bin or area, e.g., in a system memory. This visibility information can be used to determine or generate a visibility stream. In a rendering pass, the primitives in each bin can be rendered separately. In these instances, the visibility stream can be fetched from memory used to drop primitives which are not visible for that bin.

[0059] Some aspects of GPUs or GPU architectures can provide a number of different options for rendering, e.g., software rendering and hardware rendering. In software rendering, a driver or CPU can replicate an entire frame geometry by processing each view one time. Additionally, some different states may be changed depending on the view. As such, in software rendering, the software can replicate the entire workload by changing some states that may be utilized to render for each viewpoint in an image. In certain aspects, as GPUs may be submitting the same workload multiple times for each viewpoint in an image, there may be an increased amount of overhead. In hardware rendering, the hardware or GPU may be responsible for replicating or processing the geometry for each viewpoint in an image. Accordingly, the hardware can manage the replication or processing of the primitives or triangles for each viewpoint in an image.

[0060] FIG. 4 illustrates image or surface 400, including multiple primitives divided into multiple bins. As shown in FIG. 4, image or surface 400 includes area 402, which includes primitives 421, 422, 423, and 424. The primitives 421, 422, 423, and 424 are divided or placed into different bins, e.g., bins 410, 411, 412, 413, 414, and 415. FIG. 4 illustrates an example of tiled rendering using multiple viewpoints for the primitives 421-424. For instance, primitives 421-424 are in first viewpoint 450 and second viewpoint 451. As such, the GPU processing or rendering the image or surface 400 including area 402 can utilize multiple viewpoints or multi-view rendering.129025-2387WO01Qualcomm Ref. No. 2404924WO 20

[0061] As indicated herein, GPUs or graphics processor units can use a tiled rendering architecture to reduce power consumption or save memory bandwidth. As further stated above, this rendering method can divide the scene into multiple bins, as well as include a visibility pass that identifies the triangles that are visible in each bin. Thus, in tiled rendering, a full screen can be divided into multiple bins or tiles. The scene can then be rendered multiple times, e.g., one or more times for each bin.

[0062] In aspects of graphics rendering, some graphics applications may render to a single target, i.e., a render target, one or more times. For instance, in graphics rendering, a frame buffer on a system memory may be updated multiple times. The frame buffer can be a portion of memory or random access memory (RAM), e.g., containing a bitmap or storage, to help store display data for a GPU. The frame buffer can also be a memory buffer containing a complete frame of data. Additionally, the frame buffer can be a logic buffer. In some aspects, updating the frame buffer can be performed in bin or tile rendering, where, as discussed above, a surface is divided into multiple bins or tiles and then each bin or tile can be separately rendered. Further, in tiled rendering, the frame buffer can be partitioned into multiple bins or tiles.

[0063] In some aspects of graphics processing, GPU hardware may be divided into multiple sections, e.g., hardware for geometry processing and hardware for pixel processing. Scalable GPU hardware may be desirable in order to meet different throughputs across various market segments. Also, in some aspects, scalable hardware for pixel processing may be designed in a variety of ways. For instance, a screen may be divided into different parts and multiple pixel processing hardware modules (i.e., slices) may work independently on different parts of the screen. By changing the number of pixel slices, a scalable throughput may be achieved for different tiers. However, designing scalable geometry processing hardware has an inherent challenge of evenly distributing the workload across independently working hardware modules (i.e., geometry slices).

[0064] There are a number of issues that may be encountered when designing scalable geometry processing hardware. For instance, the variable size of a drawcall (i.e., a work unit) and an adaptive workload expansion in the middle of the geometry pipeline are some issues that may occur when designing scalable geometry processing hardware. Workloads across different drawcalls may vary, so tying each drawcall to a geometry slice may create uneven data downstream. Apart from this, an application program interface (API) may specify that a geometry pipeline may support adaptive129025-2387WO01Qualcomm Ref. No. 2404924WO 21 workload expansion / reduction through different features, e.g., tessellation, geometry shading, and / or triangle culling.

[0065] FIG. 5 is a diagram 500 illustrating an example geometry pipeline in a GPU. As depicted in FIG. 5, diagram 500 includes a drawcall dispatch 510, an index fetch 512, a visibility handling step 514, a pre-vertex shader index cache 516, an attribute fetch of a cache missed index 518, a vertex shader 520, a hull shader 522, a tessellator 524, a pre-domain shader index cache 526, a domain shader 528, a primitive assembly 530, a geometry shader 532, and a triangle setup rasterization 534. As shown in FIG. 5, after an index fetch 512, each primitive may be expanded to create multiple primitives, where an amplification factor may be determined during run-time. As such, sending primitives to different modules without considering an amplification factor may create an unequal workload in a downstream pipeline. Accordingly, this may prevent the achievement of an optimal throughput.

[0066] Another issue that may be encountered when designing scalable geometry processing hardware is visibility handling (e.g., tiled rendering) across multiple geometry slices. As indicated above, in tile-based rendering, the screen is divided into multiple bins, and a binning pass is used to generate a per-bin visibility stream (i.e., primitives that may be identified as visible in a bin). Also, the visibility stream may be used in multiple bin-rendering passes (e.g., dropping invisible primitives from processing) to render the whole screen. Because of different visibilities of primitives, the workload pattern in each bin-rendering pass may vary significantly from a binning pass. A workload distribution scheme may need to ensure that an even workload (including amplification) is distributed to each geometry slice (even when accounting for the potential disparity in visibility).

[0067] In some aspects, different types of GPU hardware may support different types of workload execution. Additionally, different types of workloads may take a different amount of processing time in various stages of the GPU pipeline. Also, these types of workloads may introduce inefficiency in GPU hardware utilization. In some aspects, scheduling algorithms in order to time-share the GPU hardware may sequence the workload to achieve the best utilization of GPU hardware. This kind of workload pattern is common in certain types of binning (e.g., concurrent binning). For example, in concurrent binning, a tile sorting pass for a certain frame (e.g., frame ‘N+l’) may be run concurrently with a rendering pass of another frame (e.g., frame ‘N’).129025-2387WO01Qualcomm Ref. No. 2404924WO 22

[0068] FIG. 6 illustrates diagram 600 including one example of GPU hardware. More specifically, diagram 600 depicts a time-shared GPU hardware for concurrent binning. As shown in FIG. 6, diagram 600 includes GPU hardware 602 including index fetch component 610, workload selection component 630, memory 640, geometry processing pipe 650, vertex storage component 690, pixel processing pipe 692, and visibility generation component 694. As shown in FIG. 6, render commands 612 may be input to index fetch component 610, which may be output to workload selection component 630. The workload selection component 630 may have a render / sort selection capability, as well as a certain granularity (e.g., a granularity for a group of N primitives). Also, the workload selection component 630 may be referred to as a workload selection switch component, switch component, workload selection component, or selection component. The “switch” may refers to a switch in the selection of render / sorting workloads. The output of workload selection component 630 may be sent to geometry processing pipe 650, which may communicate with memory 640. The geometry processing pipe 650 may include fetch from memory component 652, return from memory component 654, decode and pack component 656, render output buffer 660, and shader processor 664. Also, the output of geometry processing pipe 650 may be sent to vertex storage component 690, which may be sent to pixel processing pipe 692 and visibility generation component 694.

[0069] As shown in FIG. 6, geometry pipe hardware (e.g., geometry processing pipe 650) may be time shared between tile sorting and tile render workloads. Also, a scheduling algorithm (e.g., workload selection component 630) may consider the availability of GPU hardware for tile sorting and tile render workload. The granularity of a workload may be selected such that there is limited workload switching overhead. Further, the granularity of a workload may be selected such that, at the same time, one workload does not block the other. As shown in FIG. 6, the workload selection component 630 may have a granularity of a group of N primitives. For instance, for concurrent binning, the workload distribution granularity may be a primitive batch (e.g., a set of N primitives).

[0070] Certain types of workloads (e.g., sorting workloads) may face higher memory access latencies compared to other types of workloads (e.g., render workloads). For example, render workloads may be of higher priority than sorting workloads, which may face higher memory access latencies. In some aspects, if these types of129025-2387WO01Qualcomm Ref. No. 2404924WO 23 workloads (e.g., sorting workloads) are executed in-order as per the scheduled workload sequence and granularity, there may be a reduction in hardware efficiency. For instance, if these types of workloads (e.g., sorting workloads) are executed inorder as per the scheduled workload sequence and granularity, a certain workload block (e.g., a head-of-line block) may occur, thus reducing the hardware efficiency. This type of scenario is shown in FIG. 7.

[0071] FIG. 7 illustrates diagram 700 including one example of a workload execution sequence. More specifically, diagram 700 depicts a workload execution sequence for a GPU (i.e., a scheduled execution order). As shown in FIG. 7, diagram 700 includes workload sequence 702 including workload 712, workload 714, workload 716, workload submission sequence 720, and execution sequence 730. FIG. 7 depicts a timeline of workload execution including workload submission sequence 720 and execution sequence 730. FIG. 7 illustrates that certain types of workloads (e.g., workload 712, workload 714, and workload 716) are executed in a certain order as per the scheduled workload sequence. As shown in FIG. 7, consider a workload submission sequence 720 (e.g., as determined by the workload selection component 630 in FIG. 6) to be workload 712, workload 714, and workload 716. Each of these workload may need to fetch data from memory (e.g., memory 640) and send it to shader processor (e.g., shader processor 664) for further processing. In some aspects, there may be a limit on how many requests can be made without processing the returned data (e.g., an OT limit). In some instances, some of the memory accesses for workload 714 may be granted before all accesses for workload 712, and some of the memory accesses for workload 716 may be granted before all accesses for workload 714.

[0072] In some aspects, certain types of graphics applications, such as high-end applications or games in certain application program interfaces (APIs) (e.g., DirectX (DX)), may use a large render target (RT). For example, these types of application may use a certain depth stencil view (DSV) size (e.g., up to 16K). That is, these applications may use a large render target view (RTV) or frame buffer objects that cannot be fully loaded to certain types of memory (e.g., graphics memory (GMEM)). A render target (RT) may be a target block of pixels (e.g., a buffer) into which rendering may occur. In some aspects, a render target may refer to a buffer where the pixels are drawn (e.g., a video card draws pixels) for a scene that is being rendered in the background. In some instances, these graphics applications may currently divide the render target129025-2387WO01Qualcomm Ref. No. 2404924WO 24(RT) into multiple bins and proceed with rendering (e.g., visibility binning (vizbinning)). However, these multiple bins may increase the amount of overhead of many types of applications. That is, the use of multiple bins during rendering increases the time needed to perform all of the rendering for an image or frame, as the image is divided into multiple bins and each successive bin increases the time needed for rendering. In turn, this may increase the corresponding overhead associated with this type of rendering.

[0073] FIG. 8 illustrates diagram 800 including one example of a rendering sequence. More specifically, diagram 800 depicts an example of a rendering sequence 802 that utilizes multiple bins at a GPU. As shown in FIG. 8, at 810, the GPU may obtain a render target (RT). At 820, the GPU may divide the image / frame into multiple bins or tiles, as well as perform a visibility pass. At 830, the GPU may determine whether the bin count is greater than a last bin. At 840, if the determination at 830 is no, the GPU may increase the bin count by 1 (e.g., bin++) and load the bin to a GMEM. At 850, the GPU may render the bin as per a visibility pass. At 860, the GPU may store the rendered bin to system memory. Again, the GPU may make a determination at 830. At 870, if the determination at 830 is yes, the GPU may end the operation. So the process of 830 to 870 may be repeated until the last bin is reached.

[0074] As shown in FIG. 8, some types of GPUs may perform binning rendering, which renders a frame on a bin-by-bin basis. Another type of rendering is direct rendering, which does not use certain types of memory (e.g., GMEM) for render targets. As opposed to rendering a frame bin-by-bin (as in a binning rendering mode), a direct rendering mode may render an entire frame in one pass through a graphics pipeline. Also, many of these applications or games may perform better with a type of rendering that reduce the number of bins. For example, many applications or games may perform better with direct rendering (rather than bin rendering) due to the overhead of multiple bins that adds to a load and store time. In some aspects (e.g., direct 3D use cases), visibility binning (vizbinning) may have additional overhead due to a large number of bins. Additionally, certain binning modes (e.g., hardware binning mode) may have an increased number of bins, which results in a corresponding increase in rendering time. Further, the render time of certain types of rendering (e.g., direct rendering (DR)) may be lower than other types of binning rendering (e.g., visibility binning).129025-2387WO01Qualcomm Ref. No. 2404924WO 25

[0075] Based on the above, it may be beneficial to perform certain types of rendering (e.g., direct rendering) because of the decreased number of bins compared to other types of rendering (e.g., binning rendering), which may result in a reduced amount of overhead at a GPU. That is, it may be beneficial to reduce the number of bins (e.g., the bins in hardware binning mode) in order to reduce the amount of time for rendering at GPUs. In turn, it may be beneficial to reduce the complexity of the image / frame for rendering, as well as reduce the load store time. Also, it may be beneficial to reduce the render target (RT) size for rendering. For instance, it may be beneficial to reduce the RT size, such that it fits in a memory (e.g., GMEM) as a single bin.

[0076] Aspects of the present disclosure may reduce the number of bins (e.g., the bins in hardware binning mode) in order to reduce the amount of time for rendering at a GPU. Aspects presented herein may also perform certain types of rendering (e.g., direct rendering) because of the decreased number of bins compared to other types of rendering (e.g., binning rendering), which may result in a reduced amount of overhead at a GPU. Further, aspects presented herein may reduce the complexity of the image / frame for rendering. For instance, aspects presented herein may reduce the render target (RT) size for rendering. Indeed, aspects presented herein may reduce the RT size, such that it fits in a memory (e.g., GMEM) as a single bin. By doing so, aspects presented herein may reduce the amount of time for rendering at a GPU. Additionally, aspects presented herein may reduce the load store time. Aspects presented herein may reduce the number of bins (e.g., the bins in hardware binning mode) in order to reduce the amount of time for rendering, reduce the complexity of the image for rendering, as well as reduce the load-store time (e.g., the load-store time at a GPU). Aspects presented herein may achieve a frames-per-second (FPS) improvement (e.g., a universal FPS improvement up to 20%) due to the faster render time and the reduced workload size.

[0077] Aspects presented herein may also downscale the render target (RT) size (e.g., depth stencil view (DSV) size) such that it fits into a certain memory size (e.g., GMEM). By doing so, aspects presented herein may render the scene in a single bin (e.g., an on-chip memory resident surface). Aspects presented herein may then perform the rendering and store / load it back at a later time. After the rendering process, aspects presented herein may upscale the surface back to its original size. Although there may be some loss in quality, this can be mitigated by downscaling and / or upscaling (e.g., artificial intelligence (Al) or machine learning (ML) (AIZML)-based129025-2387WO01Qualcomm Ref. No. 2404924WO 26 downscaling and / or upscaling). The scaling back to the original size may be performed using an AI / ML algorithm. A neural processing unit (NPU) may be utilized for running the AI / ML model. By doing so, this may introduce concurrency in the process, as the GPU renders the graphics workloads. So the AI / ML algorithm may be running concurrently on an NPU while the GPU continues to render the graphics workloads.

[0078] As indicated herein, aspects presented herein may utilize an AI / ML or neural network (NN) model to downscale and / or later upscale the RT to the original size. By downscaling and then upscaling back to the original size, aspects presented herein may not sacrifice too much in terms of image quality. Also, as mentioned herein, an NPU can be used for running an AI / ML model. By doing so, aspects presented herein may provide a significant improvement on GPU processing speed, as well as a reduced power consumption. This reduced power consumption may be due to a reduced workload size, which is universally applicable to all types of applications / games. Additionally, the RT that is targeted may be an intermediate RT (e.g., an off-screen RT or a RT that is used in post-processing), which may be used as a shader resource view (SRV) for later workloads. Thus, aspects presented herein may be using the RTs in a hybrid manner. For instance, in a frame, some RTs may be downscaled and some RTs may not be downscaled.

[0079] FIG. 9 illustrates diagram 900 and diagram 950 including examples of render targets. More specifically, diagram 900 depicts a render target of an initial size and a render target of a downscaled size. As shown in FIG. 9, diagram 900 depicts render target 910 that includes an initial size. Render target 910 also includes a plurality of bins (e.g., bins 912). Diagram 950 depicts render target 960 that includes a downscaled size. For instance, render target 960 has been downscaled in size compared to render target 910. Also, render target 960 includes a single bin (e.g., bin 962). Diagram 900 and diagram 950 depicts that by downscaling a render target (e.g., render target 960 that is downscaled compared to render target 910), it may include a fewer number of bins (e.g., bin 962 compared to multiple bins 912). By downscaling the size of render target 960 compared to render target 910, it may fit into a certain memory size (e.g., a GMEM size).

[0080] As shown in FIG. 9, aspects presented herein may downscale the size of render target 960 (e.g., depth stencil view (DSV) size) in order to fit into the size of a memory (e.g., a GMEM). By doing so, aspects presented herein may render the scene in a single129025-2387WO01Qualcomm Ref. No. 2404924WO 27 bin (e.g., bin 962) within render target 960. After downscaling render target 960, a GPU may perform the rendering and store / load it back at a later time. Additionally, after the rendering process, aspects presented herein may upscale the surface back to its original size (e.g., size of render target 910). In order to mitigate any potential loss in quality by downscaling render target 960 and the subsequent upscaling, aspects presented herein may utilize AI / ML-based downscaling and upscaling. That is, the upscaling back of render target 960 to the original size of render target 910 may be performed using an AI / ML algorithm. Also, in some aspects, a neural processing unit (NPU) may be utilized for running the AI / ML model in order to upscale back render target 960 to the original size of render target 910. By utilizing an NPU for the downscaling / upscaling, the GPU may concurrently render the graphics workloads. As such, the AI / ML algorithm may be running concurrently on an NPU while the GPU continues to render the graphics workloads, thus increasing the efficiency of the GPU by reducing the time spent processing, as well as the processing power utilized.

[0081] FIG. 10 illustrates diagram 1000 including one example of a rendering sequence.More specifically, diagram 1000 depicts an example of a rendering sequence 1002 that where the render target is downscaled to utilize a single bin. As shown in FIG. 10, at 1010, the GPU may obtain a render target (RT). For example, at 1010, the GPU may obtain an indication of a render target in a set of render targets for a frame, where the render target includes an initial size. At 1020, the GPU may determine an updated size of the render target for a frame. For example, at 1020, a GPU may instruct an NPU to utilize an AI / ML downscaler to determine a downscaled size of the render target. At 1030, the GPU may output an indication of the downscaled size of the render target for the frame. For example, an NPU may utilize an AI / ML algorithm to downscale the render target (e.g., downscale the render target to the size of a GMEM). At 1040, the GPU may load the full downscaled render target to a GMEM. For example, the GPU may load the render target including the downscaled size to a GMEM. This downscaled size of the render target may be the size of a reduced workload (e.g., a single bin).

[0082] As shown in FIG. 10, at 1050, the GPU may render the downscaled render target. For example, the GPU may perform a render process for the render target including the downscaled size (e.g., the size of a reduced workload or a single bin). At 1060, the GPU may store the bin to memory (e.g., system memory). For example, the GPU may store, based on the render process, the render target including the downscaled129025-2387WO01Qualcomm Ref. No. 2404924WO 28 size. At 1070, the GPU may determine a size adjustment from the downscaled size of the render target to the initial size of the target. That is, the GPU may determine an upscale size to return to the initial size of the render target. For example, a GPU may instruct an NPU to perform the inverse of the previous AI / ML model to perform the upscaling. Also, at 1070, the GPU may output (e.g., to an NPU) an indication of the size adjustment from the downscaled size of the render target to the initial size of the render target. At 1080, the GPU may obtain (e.g., from an NPU) an indication of the render target including the initial size. That is, at 1080, the GPU may receive, from an NPU, the upscaled render target that has been upscaled back to the initial size. At 1090, the GPU may end the process.

[0083] FIG. 11 illustrates diagram 1100 including one example of an upscale process. More specifically, diagram 1100 depicts an upscale process 1102 that can be performed using an AI / ML model at an NPU. As shown in FIG. 11, upscale process 1102 includes real image samples 1110, random seed 1120, generator, 1130, fake image 1140, discriminator 1150, and real / fake determination 1160. FIG. 11 depicts a high level overview of AI / ML-based upscaler at an NPU. As shown in FIG. 11 , the random seed 1120 may be a downscaled RT. At the generator 1130, the AI / ML algorithm or neural network (NN) may perform the upscaling or downscaling. The fake image 1140 may be the upscaled / downscaled render target from the neural network or AI / ML algorithm. The real image samples 1110 may be the render target that is rendered as per the original size configuration for the same graphics workload. Also, the discriminator 1150 may compare the real image samples 1110 and the fake image 1140. The discriminator 1150 may then issue real / fake determination 1160 after comparing the real image samples 1110 and the fake image 1140, and then adjust the weight of the AI / ML model based on the real / fake determination 1160.

[0084] As indicated herein, aspects presented herein may adjust or change the render target size. For example, aspects presented herein may adjust or change the render target size based on a size or configuration of a certain memory (e.g., a GMEM). Aspects presented herein may also utilize an AI / ML model for downscaling and upscaling the render target size. Also, aspects presented herein retrain the AI / ML model by providing the feedback of the same frames that were rendered as per the original size (e.g., the frames that have been downscaled and then upscaled). As such, in real time, aspects presented herein may utilize a smart resolution for some frames and then revalidate it with an updated AI / ML model after some heuristic threshold. Aspects129025-2387WO01Qualcomm Ref. No. 2404924WO 29 presented herein may also provide a significant FPS improvement (e.g., a universal improvement of up to 20%) due to faster render time an intelligently reduced workload size. Also, aspects presented herein may provide a significant improvement on power consumption at a GPU due to reduced workload size. Aspects presented herein may also utilize upscaling and / or downscaling that may be fed to another component (e.g., an NPU), thus improving the concurrency of processing at a GPU.

[0085] Aspects presented herein may utilize the aforementioned procedures for all types of graphics workloads (e.g., application, games, benchmarks, etc.) that may utilize a larger memory. For example, low tier, medium tier, or premium tier GPUs that have a smaller on-chip graphics memory may benefit from the aforementioned procedures. Additionally, as AI / ML-based graphics rendering is becoming more common, the aforementioned procedures will become more valuable for original equipment manufacturers (OEMs). Aspects presented herein may be implemented on all types of GPU chipsets. For instance, as the GMEM size is increasing, so is the render target size. Accordingly, downscaling the render target to the size of the GMEM may become increasingly useful. That is, reducing or downscaling the size of the render target RT according to a size of configuration of a memory (e.g., GMEM) may become increasingly useful.

[0086] Aspects of the present disclosure may include a number of benefits or advantages. For instance, aspects of the present disclosure may reduce the number of bins (e.g., the bins in hardware binning mode) in order to reduce the amount of time for rendering at a GPU. Aspects presented herein may also perform certain types of rendering (e.g., direct rendering) because of the decreased number of bins compared to other types of rendering (e.g., binning rendering), which may result in a reduced amount of overhead at a GPU. Also, aspects presented herein may reduce the complexity of the image / frame for rendering. For example, aspects presented herein may reduce the render target (RT) size for rendering. That is, aspects presented herein may reduce the RT size, such that it fits in a memory (e.g., GMEM) as a single bin. By doing so, aspects presented herein may reduce the amount of time for rendering at a GPU. Further, aspects presented herein may reduce the load store time. Aspects presented herein may reduce the number of bins (e.g., the bins in hardware binning mode), in order to reduce the amount of time for rendering, reduce the complexity of the image for rendering, as well as reduce the load store time. Additionally, aspects presented herein may achieve a frames-per-second (FPS) improvement (e.g., a129025-2387WO01Qualcomm Ref. No. 2404924WO 30 universal FPS improvement up to 20%) due to the faster render time and the reduced workload size.

[0087] FIG. 12 is a communication flow diagram 1200 of graphics processing in accordance with one or more techniques of this disclosure. As shown in FIG. 12, diagram 1200 includes example communications between GPU 1202 (e.g., a GPU, a GPU component, another graphics processor, an NPU, an NPU component, a CPU, a CPU component, or another central processor), NPU / GPU 1204 (e.g., a GPU, a GPU component, another graphics processor, an NPU, an NPU component, a CPU, a CPU component, or another central processor), and memory 1206 (e.g., a memory, a cache, a system memory, a graphics memory, a memory or cache at a CPU, or a memory or cache at a GPU), in accordance with one or more techniques of this disclosure.

[0088] At 1210, GPU 1202 may obtain a first indication of at least one render target in a set of render targets for a frame, where the at least one render target includes an initial size of the at least one render target. For example, GPU 1202 may obtain indication 1212 from NPU / GPU 1204. In some aspects, the at least one render target may be at least one intermediate render target and the set of render targets may be a set of intermediate render targets. Also, the initial size of the at least one render target may correspond to an application for the frame, and the at least one render target may correspond to a target area for rendering in the frame. In some aspects, a render target may refer to a buffer where the video card draws pixels for a scene that is being rendered in the background. An intermediate render target may refer to a render target that is used in post-processing.

[0089] At 1220, GPU 1202 may determine an updated size of the at least one render target for the frame. In some aspects, determining the updated size of the at least one render target may comprise: calculating an adjustment from the initial size of the at least one render target to the updated size of the at least one render target. Also, calculating the adjustment from the initial size of the at least one render target to the updated size of the at least one render target may comprise: calculating a downscale amount from the initial size of the at least one render target to the updated size of the at least one render target. In some aspects, determining the updated size of the at least one render target may comprise: obtaining, from a neural processing unit (NPU), a third indication of the at least one render target including the updated size. For example, GPU 1202 may obtain, from NPU / GPU 1204, a third indication of the at least one render target including the updated size.129025-2387WO01Qualcomm Ref. No. 2404924WO 31

[0090] At 1230, GPU 1202 may output a second indication of the updated size of the at least one render target for the frame. For example, GPU 1202 may output indication 1232 to NPU / GPU 1204. In some aspects, the updated size of the at least one render target may correspond to at least one of: a size of a graphics memory (GMEM) at a graphics processing unit (GPU), a size of an on-chip memory at the GPU, a size of one bin at the GPU, or a size of one tile at the GPU. Additionally, the updated size of the at least one render target may be less than the initial size of the at least one render target. In some aspects, outputting the second indication of the updated size of the at least one render target may comprise: transmitting, to a neural processing unit (NPU), the second indication of the updated size of the at least one render target; or storing, in a memory or a cache, the second indication of the updated size of the at least one render target.

[0091] At 1240, GPU 1202 may load the at least one render target including the updated size. For example, GPU 1202 may load render target 1242 to memory 1206. In some aspects, loading the at least one render target for the frame including the updated size may comprise: loading, to a graphics memory (GMEM) or an on-chip memory at a graphics processing unit (GPU), the at least one render target including the updated size.

[0092] At 1250, GPU 1202 may perform a render process for the at least one render target including the updated size.

[0093] At 1260, GPU 1202 may store, based on the render process, the at least one render target including the updated size. For example, GPU 1202 may load render target 1262 in memory 1206. In some aspects, storing the at least one render target may comprise storing the at least one render target to a system memory.

[0094] At 1270, GPU 1202 may determine a size adjustment from the updated size of the at least one render target to the initial size of the at least one render target.

[0095] At 1280, GPU 1202 may output a third indication of the size adjustment from the updated size of the at least one render target to the initial size of the at least one render target. For example, GPU 1202 may output indication 1282 to NPU / GPU 1204. In some aspects, outputting the third indication of the size adjustment may comprise: transmitting, to a neural processing unit (NPU), the third indication of the size adjustment; or storing the third indication of the size adjustment.

[0096] At 1290, GPU 1202 may obtain a fourth indication of the at least one render target including the initial size. For example, GPU 1202 may obtain indication 1292 from129025-2387WO01Qualcomm Ref. No. 2404924WO 32NPU / GPU 1204. In some aspects, obtaining the fourth indication of the at least one render target including the initial size may comprise: receiving, from a neural processing unit (NPU), the fourth indication of the at least one render target including the initial size.

[0097] FIG. 13 is a flowchart 1300 of an example method of graphics processing in accordance with one or more techniques of this disclosure. The method may be performed by a GPU (e.g., a GPU, a GPU component, another graphics processor, an NPU, an NPU component, a CPU, a CPU component, or another central processor), a CPU (e.g., a CPU, a cache at a CPU, a CPU component, another central processor, a GPU, a GPU component, or another graphics processor), a display driver integrated circuit (DDIC), an apparatus for data or graphics processing, a wireless communication device, and / or any apparatus that may perform data or graphics processing as used in connection with the examples of FIGs. 1-12.

[0098] At 1302, the GPU may obtain a first indication of at least one render target in a set of render targets for a frame, where the at least one render target includes an initial size of the at least one render target, as described in connection with the examples in FIGs. 1-12. For example, as described in 1210 of FIG. 12, GPU 1202 may obtain a first indication of at least one render target in a set of render targets for a frame, where the at least one render target includes an initial size of the at least one render target. Further, step 1302 may be performed by processing unit 120 in FIG. 1. In some aspects, the at least one render target may be at least one intermediate render target and the set of render targets may be a set of intermediate render targets. Also, the initial size of the at least one render target may correspond to an application for the frame, and the at least one render target may correspond to a target area for rendering in the frame. In some aspects, a render target may refer to a buffer where the video card draws pixels for a scene that is being rendered in the background. An intermediate render target may refer to a render target that is used in post-processing.

[0099] At 1304, the GPU may determine an updated size of the at least one render target for the frame, as described in connection with the examples in FIGs. 1-12. For example, as described in 1220 of FIG. 12, GPU 1202 may determine an updated size of the at least one render target for the frame. Further, step 1304 may be performed by processing unit 120 in FIG. 1. In some aspects, determining the updated size of the at least one render target may comprise: calculating an adjustment from the initial size of the at least one render target to the updated size of the at least one render target.129025-2387WO01Qualcomm Ref. No. 2404924WO 33Also, calculating the adjustment from the initial size of the at least one render target to the updated size of the at least one render target may comprise: calculating a downscale amount from the initial size of the at least one render target to the updated size of the at least one render target. In some aspects, determining the updated size of the at least one render target may comprise: obtaining, from a neural processing unit (NPU), a third indication of the at least one render target including the updated size. For example, GPU 1202 may obtain, from NPU / GPU 1204, a third indication of the at least one render target including the updated size.

[0100] At 1306, the GPU may output a second indication of the updated size of the at least one render target for the frame, as described in connection with the examples in FIGs. 1-12. For example, as described in 1230 of FIG. 12, GPU 1202 may output a second indication of the updated size of the at least one render target for the frame. Further, step 1306 may be performed by processing unit 120 in FIG. 1. In some aspects, the updated size of the at least one render target may correspond to at least one of: a size of a graphics memory (GMEM) at a graphics processing unit (GPU), a size of an on- chip memory at the GPU, a size of one bin at the GPU, or a size of one tile at the GPU. Additionally, the updated size of the at least one render target may be less than the initial size of the at least one render target. In some aspects, outputting the second indication of the updated size of the at least one render target may comprise: transmitting, to a neural processing unit (NPU), the second indication of the updated size of the at least one render target; or storing, in a memory or a cache, the second indication of the updated size of the at least one render target.

[0101] At 1308, the GPU may load the at least one render target including the updated size, as described in connection with the examples in FIGs. 1-12. For example, as described in 1240 of FIG. 12, GPU 1202 may load the at least one render target including the updated size. Further, step 1308 may be performed by processing unit 120 in FIG. 1. For example, GPU 1202 may load render target 1242 to memory 1206. In some aspects, loading the at least one render target for the frame including the updated size may comprise: loading, to a graphics memory (GMEM) or an on-chip memory at a graphics processing unit (GPU), the at least one render target including the updated size.

[0102] FIG. 14 is a flowchart 1400 of an example method of graphics processing in accordance with one or more techniques of this disclosure. The method may be performed by a GPU (e.g., a GPU, a GPU component, another graphics processor, an129025-2387WO01Qualcomm Ref. No. 2404924WO 34NPU, an NPU component, a CPU, a CPU component, or another central processor), a CPU (e.g., a CPU, a cache at a CPU, a CPU component, another central processor, a GPU, a GPU component, or another graphics processor), a display driver integrated circuit (DDIC), an apparatus for data or graphics processing, a wireless communication device, and / or any apparatus that may perform data or graphics processing as used in connection with the examples of FIGs. 1-12.

[0103] At 1402, the GPU may obtain a first indication of at least one render target in a set of render targets for a frame, where the at least one render target includes an initial size of the at least one render target, as described in connection with the examples in FIGs. 1-12. For example, as described in 1210 of FIG. 12, GPU 1202 may obtain a first indication of at least one render target in a set of render targets for a frame, where the at least one render target includes an initial size of the at least one render target. Further, step 1402 may be performed by processing unit 120 in FIG. 1. In some aspects, the at least one render target may be at least one intermediate render target and the set of render targets may be a set of intermediate render targets. Also, the initial size of the at least one render target may correspond to an application for the frame, and the at least one render target may correspond to a target area for rendering in the frame. In some aspects, a render target may refer to a buffer where the video card draws pixels for a scene that is being rendered in the background. An intermediate render target may refer to a render target that is used in post-processing.

[0104] At 1404, the GPU may determine an updated size of the at least one render target for the frame, as described in connection with the examples in FIGs. 1-12. For example, as described in 1220 of FIG. 12, GPU 1202 may determine an updated size of the at least one render target for the frame. Further, step 1404 may be performed by processing unit 120 in FIG. 1. In some aspects, determining the updated size of the at least one render target may comprise: calculating an adjustment from the initial size of the at least one render target to the updated size of the at least one render target. Also, calculating the adjustment from the initial size of the at least one render target to the updated size of the at least one render target may comprise: calculating a downscale amount from the initial size of the at least one render target to the updated size of the at least one render target. In some aspects, determining the updated size of the at least one render target may comprise: obtaining, from a neural processing unit (NPU), a third indication of the at least one render target including the updated129025-2387WO01Qualcomm Ref. No. 2404924WO 35 size. For example, GPU 1202 may obtain, from NPU / GPU 1204, a third indication of the at least one render target including the updated size.

[0105] At 1406, the GPU may output a second indication of the updated size of the at least one render target for the frame, as described in connection with the examples in FIGs. 1-12. For example, as described in 1230 of FIG. 12, GPU 1202 may output a second indication of the updated size of the at least one render target for the frame. Further, step 1406 may be performed by processing unit 120 in FIG. 1. In some aspects, the updated size of the at least one render target may correspond to at least one of: a size of a graphics memory (GMEM) at a graphics processing unit (GPU), a size of an on- chip memory at the GPU, a size of one bin at the GPU, or a size of one tile at the GPU. Additionally, the updated size of the at least one render target may be less than the initial size of the at least one render target. In some aspects, outputting the second indication of the updated size of the at least one render target may comprise: transmitting, to a neural processing unit (NPU), the second indication of the updated size of the at least one render target; or storing, in a memory or a cache, the second indication of the updated size of the at least one render target.

[0106] At 1408, the GPU may load the at least one render target including the updated size, as described in connection with the examples in FIGs. 1-12. For example, as described in 1240 of FIG. 12, GPU 1202 may load the at least one render target including the updated size. Further, step 1408 may be performed by processing unit 120 in FIG. 1. For example, GPU 1202 may load render target 1242 to memory 1206. In some aspects, loading the at least one render target for the frame including the updated size may comprise: loading, to a graphics memory (GMEM) or an on-chip memory at a graphics processing unit (GPU), the at least one render target including the updated size.

[0107] At 1410, the GPU may perform a render process for the at least one render target including the updated size, as described in connection with the examples in FIGs. 1- 12. For example, as described in 1250 of FIG. 12, GPU 1202 may perform a render process for the at least one render target including the updated size. Further, step 1410 may be performed by processing unit 120 in FIG. 1.

[0108] At 1412, the GPU may store, based on the render process, the at least one render target including the updated size, as described in connection with the examples in FIGs. 1- 12. For example, as described in 1260 of FIG. 12, GPU 1202 may store, based on the render process, the at least one render target including the updated size. Further, step129025-2387WO01Qualcomm Ref. No. 2404924WO 361412 may be performed by processing unit 120 in FIG. 1. In some aspects, storing the at least one render target may comprise storing the at least one render target to a system memory.

[0109] At 1414, the GPU may determine a size adjustment from the updated size of the at least one render target to the initial size of the at least one render target, as described in connection with the examples in FIGs. 1-12. For example, as described in 1270 of FIG. 12, GPU 1202 may determine a size adjustment from the updated size of the at least one render target to the initial size of the at least one render target. Further, step 1414 may be performed by processing unit 120 in FIG. 1.

[0110] At 1416, the GPU may output a third indication of the size adjustment from the updated size of the at least one render target to the initial size of the at least one render target, as described in connection with the examples in FIGs. 1-12. For example, as described in 1280 of FIG. 12, GPU 1202 may output a third indication of the size adjustment from the updated size of the at least one render target to the initial size of the at least one render target. Further, step 1416 may be performed by processing unit 120 in FIG. 1. For example, GPU 1202 may output indication 1282 to NPU / GPU 1204. In some aspects, outputting the third indication of the size adjustment may comprise: transmitting, to a neural processing unit (NPU), the third indication of the size adjustment; or storing the third indication of the size adjustment.[OHl] At 1418, the GPU may obtain a fourth indication of the at least one render target including the initial size, as described in connection with the examples in FIGs. 1-12. For example, as described in 1290 of FIG. 12, GPU 1202 may obtain a fourth indication of the at least one render target including the initial size. Further, step 1418 may be performed by processing unit 120 in FIG. 1. For example, GPU 1202 may obtain indication 1292 from NPU / GPU 1204. In some aspects, obtaining the fourth indication of the at least one render target including the initial size may comprise: receiving, from a neural processing unit (NPU), the fourth indication of the at least one render target including the initial size.

[0112] In configurations, a method or an apparatus for data or graphics processing is provided. The apparatus may be a GPU (or other graphics processor), an NPU, a CPU (or other central processor), a DDIC, an apparatus for graphics processing, and / or some other processor that may perform data or graphics processing. In aspects, the apparatus may be the processing unit 120 within the device 104, or may be some other hardware within the device 104 or another device. The apparatus, e.g., processing129025-2387WO01Qualcomm Ref. No. 2404924WO 37 unit 120, may include means for obtaining a first indication of at least one render target in a set of render targets for a frame, where the at least one render target includes an initial size of the at least one render target. The apparatus, e.g., processing unit 120, may also include means for determining an updated size of the at least one render target for the frame. The apparatus, e.g., processing unit 120, may also include means for outputting a second indication of the updated size of the at least one render target for the frame. The apparatus, e.g., processing unit 120, may also include means for loading the at least one render target including the updated size. The apparatus, e.g., processing unit 120, may also include means for determining a size adjustment from the updated size of the at least one render target to the initial size of the at least one render target. The apparatus, e.g., processing unit 120, may also include means for outputting a third indication of the size adjustment from the updated size of the at least one render target to the initial size of the at least one render target. The apparatus, e.g., processing unit 120, may also include means for obtaining a fourth indication of the at least one render target including the initial size. The apparatus, e.g., processing unit 120, may also include means for performing a render process for the at least one render target including the updated size. The apparatus, e.g., processing unit 120, may also include means for storing, based on the render process, the at least one render target including the updated size.

[0113] The subject matter described herein may be implemented to realize one or more benefits or advantages. For instance, the described graphics processing techniques may be used by a GPU, an NPU, a CPU, a central processor, or some other processor that may perform graphics processing to implement the graphics rendering techniques described herein. This may also be accomplished at a low cost compared to other graphics processing techniques. Moreover, the graphics processing techniques herein may improve or speed up graphics processing or execution. Further, the graphics processing techniques herein may improve resource or data utilization and / or resource efficiency. Additionally, aspects of the present disclosure may utilize graphics rendering techniques in order to improve memory bandwidth efficiency and / or increase processing speed at a GPU, an NPU, a CPU, or a DPU.

[0114] It is understood that the specific order or hierarchy of blocks in the processes / flowcharts disclosed is an illustration of example approaches. Based upon design preferences, it is understood that the specific order or hierarchy of blocks in the processes / flowcharts may be rearranged. Further, some blocks may be combined or129025-2387WO01Qualcomm Ref. No. 2404924WO 38 omitted. The accompanying method claims present elements of the various blocks in a sample order, and are not meant to be limited to the specific order or hierarchy presented.

[0115] The previous description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects. Thus, the claims are not intended to be limited to the aspects shown herein, but is to be accorded the full scope consistent with the language of the claims, wherein reference to an element in the singular is not intended to mean “one and only one” unless specifically so stated, but rather “one or more.” The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0116] Unless specifically stated otherwise, the term “some” refers to one or more and the term “or” may be interpreted as “and / or” where context does not dictate otherwise. Combinations such as “at least one of A, B, or C,” “one or more of A, B, or C,” “at least one of A, B, and C,” “one or more of A, B, and C,” and “A, B, C, or any combination thereof’ include any combination of A, B, and / or C, and may include multiples of A, multiples of B, or multiples of C. Specifically, combinations such as “at least one of A, B, or C,” “one or more of A, B, or C,” “at least one of A, B, and C,” “one or more of A, B, and C,” and “A, B, C, or any combination thereof’ may be A only, B only, C only, A and B, A and C, B and C, or A and B and C, where any such combinations may contain one or more member or members of A, B, or C. All structural and functional equivalents to the elements of the various aspects described throughout this disclosure that are known or later come to be known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the claims. Moreover, nothing disclosed herein is intended to be dedicated to the public regardless of whether such disclosure is explicitly recited in the claims. The words “module,” “mechanism,” “element,” “device,” and the like may not be a substitute for the word “means.” As such, no claim element is to be construed as a means plus function unless the element is expressly recited using the phrase “means for.”

[0117] In one or more examples, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. For example, although the129025-2387WO01Qualcomm Ref. No. 2404924WO 39 term “processing unit” has been used throughout this disclosure, such processing units may be implemented in hardware, software, firmware, or any combination thereof. If any function, processing unit, technique described herein, or other module is implemented in software, the function, processing unit, technique described herein, or other module may be stored on or transmitted over as one or more instructions or code on a computer-readable medium.

[0118] In accordance with this disclosure, the term “or” may be interpreted as “and / or” where context does not dictate otherwise. Additionally, while phrases such as “one or more” or “at least one” or the like may have been used for some features disclosed herein but not others, the features for which such language was not used may be interpreted to have such a meaning implied where context does not dictate otherwise.

[0119] In one or more examples, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. For example, although the term “processing unit” has been used throughout this disclosure, such processing units may be implemented in hardware, software, firmware, or any combination thereof. If any function, processing unit, technique described herein, or other module is implemented in software, the function, processing unit, technique described herein, or other module may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media may include computer data storage media or communication media including any medium that facilitates transfer of a computer program from one place to another. In this manner, computer-readable media generally may correspond to (1) tangible computer- readable storage media, which is non-transitory or (2) a communication medium such as a signal or carrier wave. Data storage media may be any available media that may be accessed by one or more computers or one or more processors to retrieve instructions, code and / or data structures for implementation of the techniques described in this disclosure. By way of example, and not limitation, such computer- readable media may comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices. Disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media. A computer program product may include a computer-readable medium.129025-2387WO01Qualcomm Ref. No. 2404924WO 40

[0120] The code may be executed by one or more processors, such as one or more digital signal processors (DSPs), general purpose microprocessors, application specific integrated circuits (ASICs), arithmetic logic units (ALUs), field programmable logic arrays (FPGAs), or other equivalent integrated or discrete logic circuitry. Accordingly, the term “processor,” as used herein may refer to any of the foregoing structure or any other structure suitable for implementation of the techniques described herein. Also, the techniques could be fully implemented in one or more circuits or logic elements.

[0121] The techniques of this disclosure may be implemented in a wide variety of devices or apparatuses, including a wireless handset, an integrated circuit (IC) or a set of ICs, e.g., a chip set. Various components, modules or units are described in this disclosure to emphasize functional aspects of devices configured to perform the disclosed techniques, but do not necessarily need realization by different hardware units. Rather, as described above, various units may be combined in any hardware unit or provided by a collection of inter-operative hardware units, including one or more processors as described above, in conjunction with suitable software and / or firmware. Accordingly, the term “processor,” as used herein may refer to any of the foregoing structure or any other structure suitable for implementation of the techniques described herein. Also, the techniques may be fully implemented in one or more circuits or logic elements.

[0122] The following aspects are illustrative only and may be combined with other aspects or teachings described herein, without limitation.

[0123] Aspect 1 is an apparatus for graphics processing, including at least one memory and at least one processor coupled to the at least one memory and, based at least in part on information stored in the at least one memory, the at least one processor, individually or in any combination, is configured to: obtain a first indication of at least one render target in a set of render targets for a frame, wherein the at least one render target includes an initial size of the at least one render target; determine an updated size of the at least one render target for the frame; output a second indication of the updated size of the at least one render target for the frame; and load the at least one render target including the updated size.

[0124] Aspect 2 is the apparatus of aspect 1, wherein to determine the updated size of the at least one render target, the at least one processor, individually or in any combination,129025-2387WO01Qualcomm Ref. No. 2404924WO 41 is configured to: calculate an adjustment from the initial size of the at least one render target to the updated size of the at least one render target.

[0125] Aspect 3 is the apparatus of aspect 2, wherein to calculate the adjustment from the initial size of the at least one render target to the updated size of the at least one render target, the at least one processor, individually or in any combination, is configured to: calculate a downscale amount from the initial size of the at least one render target to the updated size of the at least one render target.

[0126] Aspect 4 is the apparatus of any of aspects 2 to 3, wherein the at least one processor, individually or in any combination, is further configured to: determine a size adjustment from the updated size of the at least one render target to the initial size of the at least one render target.

[0127] Aspect 5 is the apparatus of aspect 4, wherein the at least one processor, individually or in any combination, is further configured to: output a third indication of the size adjustment from the updated size of the at least one render target to the initial size of the at least one render target.

[0128] Aspect 6 is the apparatus of aspect 5, wherein to output the third indication of the size adjustment, the at least one processor, individually or in any combination, is configured to: transmit, to a neural processing unit (NPU), the third indication of the size adjustment; or store the third indication of the size adjustment.

[0129] Aspect 7 is the apparatus of any of aspects 5 to 6, wherein the at least one processor, individually or in any combination, is further configured to: obtain a fourth indication of the at least one render target including the initial size.

[0130] Aspect 8 is the apparatus of aspect 7, wherein to obtain the fourth indication of the at least one render target including the initial size, the at least one processor, individually or in any combination, is configured to: receive, from a neural processing unit (NPU), the fourth indication of the at least one render target including the initial size.

[0131] Aspect 9 is the apparatus of any of aspects 1 to 8, wherein the at least one processor, individually or in any combination, is further configured to: perform a render process for the at least one render target including the updated size.

[0132] Aspect 10 is the apparatus of aspect 9, wherein the at least one processor, individually or in any combination, is further configured to: store, based on the render process, the at least one render target including the updated size.129025-2387WO01Qualcomm Ref. No. 2404924WO 42

[0133] Aspect 11 is the apparatus of aspect 10, wherein to store the at least one render target, the at least one processor, individually or in any combination, is configured to: store the at least one render target to a system memory.

[0134] Aspect 12 is the apparatus of any of aspects 1 to 11, wherein the updated size of the at least one render target corresponds to at least one of a size of a graphics memory (GMEM) at a graphics processing unit (GPU), a size of an on-chip memory at the GPU, a size of one bin at the GPU, or a size of one tile at the GPU.

[0135] Aspect 13 is the apparatus of any of aspects 1 to 12, wherein the updated size of the at least one render target is less than the initial size of the at least one render target.

[0136] Aspect 14 is the apparatus of any of aspects 1 to 13, wherein to determine the updated size of the at least one render target, the at least one processor, individually or in any combination, is configured to: obtain, from a neural processing unit (NPU), a third indication of the at least one render target including the updated size.

[0137] Aspect 15 is the apparatus of any of aspects 1 to 14, wherein to load the at least one render target for the frame including the updated size, the at least one processor, individually or in any combination, is configured to: load, to a graphics memory (GMEM) or an on-chip memory at a graphics processing unit (GPU), the at least one render target including the updated size.

[0138] Aspect 16 is the apparatus of any of aspects 1 to 15, wherein the at least one render target is at least one intermediate render target and the set of render targets is a set of intermediate render targets.

[0139] Aspect 17 is the apparatus of any of aspects 1 to 16, wherein the initial size of the at least one render target corresponds to an application for the frame, and wherein the at least one render target corresponds to a target area for rendering in the frame.

[0140] Aspect 18 is the apparatus of aspect 17, wherein to output the second indication of the updated size of the at least one render target, the at least one processor, individually or in any combination, is configured to: transmit, to a neural processing unit (NPU), the second indication of the updated size of the at least one render target; or store, in a memory or a cache, the second indication of the updated size of the at least one render target.

[0141] Aspect 19 is the apparatus of aspect 18, further including (i.e., comprising) at least one of an antenna or a transceiver coupled to the at least one processor, wherein to transmit the second indication, the at least one processor, individually or in any129025-2387WO01Qualcomm Ref. No. 2404924WO 43 combination, is configured to: transmit, via at least one of an antenna or a transceiver, the second indication.

[0142] Aspect 20 is the apparatus of any of aspects 1 to 19, wherein the apparatus is a wireless communication device.

[0143] Aspect 21 is a method of graphics processing for implementing any of aspects 1 to 20.

[0144] Aspect 22 is an apparatus for graphics processing including means for implementing any of aspects 1 to 20.

[0145] Aspect 23 is a computer-readable medium (e.g., a non-transitory computer-readable medium) storing computer executable code (e.g., code for graphics processing), the code when executed by at least one processor causes the at least one processor to implement any of aspects 1 to 20.129025-2387WO01

Claims

Qualcomm Ref. No. 2404924WO 44CLAIMSWHAT IS CLAIMED IS:

1. An apparatus for graphics processing, comprising: at least one memory; and at least one processor coupled to the at least one memory and, based at least in part on information stored in the at least one memory, the at least one processor, individually or in any combination, is configured to: obtain a first indication of at least one render target in a set of render targets for a frame, wherein the at least one render target includes an initial size of the at least one render target; determine an updated size of the at least one render target for the frame; output a second indication of the updated size of the at least one render target for the frame; and load the at least one render target including the updated size.

2. The apparatus of claim 1, wherein to determine the updated size of the at least one render target, the at least one processor, individually or in any combination, is configured to: calculate an adjustment from the initial size of the at least one render target to the updated size of the at least one render target.

3. The apparatus of claim 2, wherein to calculate the adjustment from the initial size of the at least one render target to the updated size of the at least one render target, the at least one processor, individually or in any combination, is configured to: calculate a downscale amount from the initial size of the at least one render target to the updated size of the at least one render target.

4. The apparatus of claim 1, wherein the at least one processor, individually or in any combination, is further configured to: determine a size adjustment from the updated size of the at least one render target to the initial size of the at least one render target.129025-2387WO01Qualcomm Ref. No. 2404924WO 455. The apparatus of claim 4, wherein the at least one processor, individually or in any combination, is further configured to: output a third indication of the size adjustment from the updated size of the at least one render target to the initial size of the at least one render target.

6. The apparatus of claim 5, wherein to output the third indication of the size adjustment, the at least one processor, individually or in any combination, is configured to: transmit, to a neural processing unit (NPU), the third indication of the size adjustment; or store the third indication of the size adjustment.

7. The apparatus of claim 5, wherein the at least one processor, individually or in any combination, is further configured to: obtain a fourth indication of the at least one render target including the initial size.

8. The apparatus of claim 7, wherein to obtain the fourth indication of the at least one render target including the initial size, the at least one processor, individually or in any combination, is configured to: receive, from a neural processing unit (NPU), the fourth indication of the at least one render target including the initial size.

9. The apparatus of claim 1, wherein the at least one processor, individually or in any combination, is further configured to: perform a render process for the at least one render target including the updated size.

10. The apparatus of claim 9, wherein the at least one processor, individually or in any combination, is further configured to: store, based on the render process, the at least one render target including the updated size.

11. The apparatus of claim 10, wherein to store the at least one render target, the at least one processor, individually or in any combination, is configured to: store the at least one render target to a system memory.129025-2387WO01Qualcomm Ref. No. 2404924WO 4612. The apparatus of claim 1, wherein the updated size of the at least one render target corresponds to at least one of: a size of a graphics memory (GMEM) at a graphics processing unit (GPU), a size of an on-chip memory at the GPU, a size of one bin at the GPU, or a size of one tile at the GPU.

13. The apparatus of claim 1, wherein the updated size of the at least one render target is less than the initial size of the at least one render target.

14. The apparatus of claim 1, wherein to determine the updated size of the at least one render target, the at least one processor, individually or in any combination, is configured to: obtain, from a neural processing unit (NPU), a third indication of the at least one render target including the updated size.

15. The apparatus of claim 1, wherein to load the at least one render target for the frame including the updated size, the at least one processor, individually or in any combination, is configured to: load, to a graphics memory (GMEM) or an on-chip memory at a graphics processing unit (GPU), the at least one render target including the updated size.

16. The apparatus of claim 1, wherein the at least one render target is at least one intermediate render target and the set of render targets is a set of intermediate render targets.

17. The apparatus of claim 1, wherein the initial size of the at least one render target corresponds to an application for the frame, and wherein the at least one render target corresponds to a target area for rendering in the frame.

18. The apparatus of claim 1, wherein to output the second indication of the updated size of the at least one render target, the at least one processor, individually or in any combination, is configured to: transmit, to a neural processing unit (NPU), the second indication of the updated size of the at least one render target; or129025-2387WO01Qualcomm Ref. No. 2404924WO 47 store, in a memory or a cache, the second indication of the updated size of the at least one render target.

19. A method of graphics processing, comprising: obtaining a first indication of at least one render target in a set of render targets for a frame, wherein the at least one render target includes an initial size of the at least one render target; determining an updated size of the at least one render target for the frame; outputting a second indication of the updated size of the at least one render target for the frame; and loading the at least one render target including the updated size.

20. A computer-readable medium storing computer executable code for graphics processing, the code when executed by at least one processor causes the at least one processor to: obtain a first indication of at least one render target in a set of render targets for a frame, wherein the at least one render target includes an initial size of the at least one render target; determine an updated size of the at least one render target for the frame; output a second indication of the updated size of the at least one render target for the frame; and load the at least one render target including the updated size.129025-2387WO01

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