Baseband processing system

Abstract

Disclosed is a baseband processing system. A first processor, a first acceleration device and a second acceleration device are used to constitute the baseband processing system and, on the basis of the first processor, the first acceleration device and the second acceleration device are configured to respectively execute baseband processing steps, such that a series of baseband processing steps for data can be executed jointly by the first acceleration device and the second acceleration device. In this way, allocating the multiple acceleration devices the series of baseband processing steps to be executed enables each acceleration device to only focus on executing specific and as few baseband processing steps as possible, thereby improving the specificity of the acceleration devices and achieving efficient collaboration between the different acceleration devices and thus reducing the overall energy consumption of the baseband processing system. In addition, providing in the baseband processing system the multiple acceleration devices that can be configured by the processor can flexibly configure or extend the acceleration devices on the basis of actual environments so as to improve the flexibility of the baseband processing system, helping to satisfy cloudification requirements of base stations.

Description

A baseband processing system

[0001] The present application claims priority from the Chinese patent application No. 202411295492.1 filed on September 13, 2024, and entitled "A baseband processing system", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the field of communication technology, and in particular to a baseband processing system. BACKGROUND

[0003] Mobile communication technology is constantly developing to meet people's growing demand for wireless communication. The 5th generation mobile communication technology (5th generation mobile networks or 5th generation wireless systems, 5G) is the latest generation of mobile communication technology that has been commercially used and is gradually popularizing.

[0004] As the most important component of the 5G network, the functions of the 5G base station can be divided into three parts: the centralized unit (CU), the distributed unit (DU), and the radio unit (RU). Currently, in the 5G network, one DU is usually connected to one or more RUs, thereby processing the uplink and downlink packets related to one or more RUs.

[0005] For the DU, since the DU needs to process a large number of uplink and downlink packets related to the RU, and a series of complex baseband processing steps need to be performed for each packet, the hardware in the current DU usually has strong speciality to ensure that the DU can quickly and efficiently complete the complex processing of the packet. In the cloud baseband scheme, since higher flexibility and resource sharing capabilities need to be supported, more general computing power needs to be introduced, which often leads to higher energy consumption of the DU in the cloud baseband scheme. SUMMARY

[0006] The present application provides a baseband processing system, which can reduce the overall energy consumption of the baseband processing system and improve the flexibility of the baseband processing system, thereby being beneficial to meet the cloudification needs of the base station.

[0007] In a first aspect, a baseband processing system is provided, comprising a first processor, a first acceleration device and a second acceleration device, the first acceleration device and the second acceleration device being connected by a communication link, the communication link being configured to support direct communication between the first acceleration device and the second acceleration device. That is, the communication link between the first acceleration device and the second acceleration device is actually a peer-to-peer communication bus, that is, the data transmission between the first acceleration device and the second acceleration device can directly complete communication based on the peer-to-peer communication bus, without the need to pass through a centralized control node (such as the first processor).

[0008] The first processor is configured to configure the first acceleration device to perform a first baseband processing step and configure the second acceleration device to perform a second baseband processing step. The first acceleration device is configured to perform the first baseband processing step on input first data and send the processed data to the second acceleration device. The second acceleration device is configured to perform the second baseband processing step on the data sent by the first acceleration device to obtain target data.

[0009] That is, the first acceleration device and the second acceleration device only perform part of a series of baseband processing steps of packet data, and the processing steps performed by the first acceleration device and the second acceleration device do not overlap. Moreover, after the first acceleration device completes the configured first baseband processing step on the input first data, the first acceleration device directly sends the processed data to the second acceleration device without the need for transit through other components (such as a processor or a host memory), thereby ensuring the efficiency of the joint completion of baseband processing by the first acceleration device and the second acceleration device.

[0010] In this scheme, the baseband processing system is composed of the first processor, the first acceleration device and the second acceleration device, and the baseband processing steps performed by the first acceleration device and the second acceleration device are configured based on the first processor, thereby enabling the joint completion of a series of baseband processing steps of data by the first acceleration device and the second acceleration device. Moreover, the first acceleration device and the second acceleration device are connected by a communication link supporting direct communication, thereby ensuring that the first acceleration device and the second acceleration device can directly interact with data. In this way, by distributing a series of baseband processing steps in a packet data processing flow to multiple acceleration devices for execution, the baseband processing steps that need to be performed can be distributed according to the computing power characteristics of each acceleration device, and the direct communication capability of the peer-to-peer communication bus is used to realize efficient cooperation between different acceleration devices, thereby reducing the overall energy consumption of the baseband processing system. Moreover, multiple acceleration devices that can be configured by the processor are provided in the baseband processing system, thereby enabling flexible configuration or expansion of the acceleration devices based on actual scenarios, improving the flexibility of the baseband processing system, and being conducive to meeting the cloudification needs of a base station.

[0011] In a possible implementation, the first accelerator is further configured to trigger the first baseband processing step on the first data according to the configuration of the first processor after obtaining the first task start signal; and the first accelerator is further configured to send the second task start signal to the second accelerator after sending the processed data to the second accelerator; and the second accelerator is further configured to trigger the second baseband processing step on the data sent by the first accelerator according to the configuration of the first processor after obtaining the second task start signal.

[0012] That is, the first processor configures the first accelerator to perform the first baseband processing step on the first data after obtaining the first task start signal, and configures the first accelerator to send the second task start signal to the second accelerator after sending the second data to the second accelerator. In addition, the first processor further configures the second accelerator to perform the second baseband processing step on the second data after receiving the second task start signal. In this way, based on the configuration of the first processor on the first accelerator and the second accelerator, the first accelerator and the second accelerator can be closely matched to implement the baseband processing of the data.

[0013] In a possible implementation, the first data is located in a memory used by the first processor, and the first accelerator is further configured to obtain the first data from the memory after obtaining the first task start signal. That is, the first accelerator is further connected with the memory used by the first processor through the peer-to-peer communication link. In this way, the first accelerator can directly read the data from the memory used by the first processor based on the peer-to-peer communication link.

[0014] In this scheme, by directly reading the input data from the memory used by the first processor by the first accelerator, the step of forwarding the input data by the first processor to the first accelerator can be omitted, the efficiency of data processing is improved, and the processing pressure of the first processor is reduced.

[0015] In a possible implementation, the baseband processing system further includes a second processor; the first processor and the first accelerator are located on a first device, and the second processor and the second accelerator are located on a second device; a data exchange device is connected between the first device and the second device, and the data exchange device supports a cross-device direct communication link; and the first accelerator sends the processed data to the second accelerator through the data exchange device.

[0016] In a possible implementation, the first processor is specifically configured to negotiate with the second processor to configure the second accelerator to perform the second baseband processing step.

[0017] That is, the first acceleration device and the second acceleration device are actually on different devices and managed by different processors. Therefore, in order to realize the joint execution of the baseband processing by the acceleration devices on different devices, the processors on the two devices can first negotiate to determine how the first acceleration device and the second acceleration device cooperatively execute the baseband processing.

[0018] In a possible implementation, the baseband processing system further includes a network card. The network card is configured to receive the fronthaul data and write first data including an in-phase quadrature (IQ) signal in the fronthaul data into a memory of the first acceleration device, so that the first acceleration device obtains the first data from the memory.

[0019] That is, the first processor can configure the network card to write the received data into the memory of the first acceleration device. For example, the first processor sends configuration information to the network card, where the configuration information is used to indicate that the storage address of the uplink data is the memory address in the first acceleration device.

[0020] In a possible implementation, the network card is separate from the first acceleration device, and the first processor is configured to configure the network card to write the fronthaul data including the IQ signal into the memory address of the first acceleration device through the direct communication link after receiving the fronthaul data including the IQ signal.

[0021] In a possible implementation, the network card is integrated on the first acceleration device. That is, the network card and the first acceleration device are combined, and it can also be understood that the first acceleration device also has the function of fronthaul data transmission and reception. The first acceleration device is configured to perform the first baseband processing step on the data including the IQ signal after the data including the IQ signal received through the network card meets the rule configured by the first processor.

[0022] That is, in the case where the network card and the first acceleration device are integrated, the first processor can configure the first acceleration device to start performing the first baseband processing step on the data including the IQ signal after the network card has received the data including the IQ signal of one symbol or one slot in the air interface, without the need for a task start signal to trigger the first acceleration device to perform the first baseband processing step.

[0023] In a possible implementation, the baseband processing system further includes a third acceleration device. The network card is further configured to write second data into a memory of the third acceleration device through the communication link according to the configuration of the first processor; and the third acceleration device is configured to perform a baseband processing step on the second data.

[0024] That is, the network card actually sends different data to different acceleration devices for processing according to the configuration of the first processor, which can not only achieve load balancing among the acceleration devices, but also select the matching acceleration device for different baseband data processing steps. In this way, by configuring the network card to send data to different acceleration devices, the multiple acceleration devices in the baseband processing system can be flexibly configured based on actual needs to process various data, improving the flexibility of the scheme.

[0025] In a possible implementation, the source address of the fronthaul data to which the first data belongs is a first address, the first address is a fronthaul link address of the first cell, the source address of the fronthaul data to which the second data belongs is a second address, and the second address is a fronthaul link address of the second cell; the first processor is further configured to configure the network card to send the fronthaul data with the source address of the first address to the first acceleration device and send the fronthaul data with the source address of the second address to the third acceleration device.

[0026] That is, by configuring the network card on the first processor to send data of different source addresses to different acceleration devices, the shunting processing of data of different source addresses can be achieved, so that the fronthaul data of different cells is shunted to different acceleration devices for processing, to meet the cloudification demand of baseband processing in actual application.

[0027] In a possible implementation, the fronthaul data to which the first data belongs is first type fronthaul data, and the fronthaul data to which the second data belongs is second type fronthaul data; the first processor is further configured to configure the network card to send the first data to the first acceleration device and send the second data to the third acceleration device.

[0028] That is, the first processor can configure the network card to process different types of fronthaul data to different acceleration devices, so that different types of fronthaul data can be shunted to different acceleration devices for processing.

[0029] In a possible implementation, the first type fronthaul data is used to transmit data of one air interface signal or air interface channel, and the second type fronthaul data is used to transmit data of another air interface signal or air interface channel. Since different air interface signals or channels may need different baseband processing procedures, shunting data of different air interface signals or channels to different acceleration devices for different baseband processing can help improve the energy efficiency of baseband processing.

[0030] In a possible implementation, the network card, the first acceleration device, and the second acceleration device are located on a first device, the third acceleration device is located on a second device, a data exchange device is connected between the first device and the second device, and the data exchange device supports a direct communication link across devices.

[0031] In the scheme, the different types of data are forwarded by the network card to the acceleration devices on different devices for processing, which can realize independent processing of different data, and the acceleration devices are independent of each other and will not affect each other, which is beneficial to realize flexible upgrade of the acceleration devices. For example, in the case of performing processing function upgrade for certain data (such as data of a certain type or data from a certain cell), the data can be distributed to new acceleration devices for processing to ensure that the original business data processing process is not affected.

[0032] In a possible implementation, the baseband processing system further includes a second processor; and the first processor is specifically configured to negotiate with the second processor to realize configuring the third acceleration device to perform the baseband processing step.

[0033] In a possible implementation, the first processor is specifically configured to configure the first acceleration device to perform the first baseband processing step and configure the second acceleration device to perform the second baseband processing step at a first time node; and the first processor is further configured to configure the first acceleration device to perform the third baseband processing step and configure the second acceleration device to perform the fourth baseband processing step at a second time node; wherein the third baseband processing step includes different processing steps from the first baseband processing step, and the fourth baseband processing step includes different processing steps from the second baseband processing step.

[0034] That is, the first processor can flexibly configure the baseband processing steps actually performed by each acceleration device, so that each acceleration device can perform different baseband processing steps at different time nodes to meet the actual application requirements.

[0035] In a possible implementation, the first acceleration device is further configured to perform the third baseband processing step on the input third data after obtaining a third task start signal, and the third task start signal is obtained after the second time node.

[0036] In a possible implementation, the amount of data to be processed by the first acceleration device at the first time node is different from the amount of data to be processed at the second time node.

[0037] In a possible implementation, the baseband processing system further includes a fourth acceleration device, which is added to the system after the first processor configures the first acceleration device to perform the first baseband processing step and configures the second acceleration device to perform the second baseband processing step; and the first processor is further configured to reconfigure the first acceleration device and / or the second acceleration device and the baseband processing step performed by the fourth acceleration device based on the capability of the fourth acceleration device.

[0038] In a possible implementation, the first processor is further configured to send a capability query request to the fourth acceleration device and receive a capability query response returned by the fourth acceleration device, so as to obtain the capability of the fourth acceleration device.

[0039] In a possible implementation, the first acceleration device and the second acceleration device are hardware of different structures; or, the first acceleration device and the second acceleration device are hardware of the same structure.

[0040] In a possible implementation, the first acceleration device and the second acceleration device are Field Programmable Gate Array (FPGA) chips, Application-Specific Integrated Circuit (ASIC) chips, Networking Processors (NP), CPUs, Graphics Processing Units (GPU), Neural-network Processing Units (NPU), or Tensor Processing Units (TPU). BRIEF DESCRIPTION OF DRAWINGS

[0041] FIG. 1 is a schematic diagram of an architecture of an access network device of a 5G network provided in the present application;

[0042] FIG. 2 is a schematic diagram of a structure of a baseband processing system provided in the present application;

[0043] FIG. 3 is a schematic diagram of a first acceleration device and a second acceleration device jointly completing a series of baseband processing steps provided in the present application;

[0044] FIG. 4 is a schematic diagram of a process in which a first acceleration device and a second acceleration device perform baseband processing based on a configuration of a first processor provided in the present application;

[0045] FIG. 5 is a schematic diagram of a structure of another baseband processing system provided in the present application;

[0046] FIG. 6 is a schematic diagram of a structure of another baseband processing system provided in the present application;

[0047] FIG. 7 is a schematic diagram of a process in which a first acceleration device and a second acceleration device perform baseband processing based on a configuration of a first processor provided in the present application, and the first acceleration device and the second acceleration device are located on different devices;

[0048] FIG. 8 is a schematic diagram of another baseband processing system provided in the present application;

[0049] Figure 9 is a schematic diagram of a network card, a first acceleration device and a second acceleration device jointly completing a series of baseband processing steps according to the present application;

[0050] Figure 10 is a schematic diagram of a network card, a first acceleration device and a second acceleration device completing baseband processing based on a configuration of a first processor according to the present application;

[0051] Figure 11 is a schematic diagram of another baseband processing system according to the present application;

[0052] Figure 12A is a schematic diagram of a network card forwarding first data and second data according to the present application;

[0053] Figure 12B is a schematic diagram of a network card forwarding first data and second data according to the present application;

[0054] Figure 12C is a schematic diagram of a network card forwarding first data and second data according to the present application;

[0055] Figure 12D is a schematic diagram of a format of a fronthaul eCPRI data packet according to the present application;

[0056] Figure 13 is a schematic diagram of another baseband processing system according to the present application;

[0057] Figure 14 is a schematic diagram of a baseband processing step performed by an acceleration device changing according to the present application;

[0058] Figure 15 is a schematic diagram of another baseband processing system according to the present application;

[0059] Figure 16 is a schematic diagram of a network device according to the present application. DETAILED DESCRIPTION

[0060] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all embodiments of the present application.

[0061] The terms "first", "second", "third", "fourth", and the like in the description and in the claims of the present application, and above-mentioned drawings (if there are) are used to distinguish similar objects, and do not have to be used to describe a particular order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "comprise" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device that includes a list of steps or units does not have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0062] In the current communication network, the communication between the access network device and the terminal device follows a certain protocol layer structure. The protocol layer can be divided into a control plane protocol layer and a user plane protocol layer. The control plane protocol layer can include at least one of the following: a radio resource control (RRC) layer, a packet data convergence protocol (PDCP) layer, a radio link control (RLC) layer, a media access control (MAC) layer, a physical (PHY) layer, etc. The user plane protocol layer can include at least one of the following: a service data adaptation protocol (SDAP) layer, a PDCP layer, an RLC layer, a MAC layer, a physical layer, etc.

[0063] Exemplarily, please refer to FIG. 1, which is an architecture schematic diagram of an access network device of a 5G network provided by the present application. As shown in FIG. 1, the access network device in the 5G network includes a CU, a DU and a RU. Among them, one CU is usually connected with one or more DUs, and one DU is usually connected with one or more RUs.

[0064] The CU and the DU implement different protocol layer functions of the wireless network: for example, the CU is configured to implement the functions of the PDCP layer and the protocol layers above (such as the RRC layer and / or the SDAP layer, etc.); the DU is configured to implement the functions of the protocol layers below the PDCP layer (such as the RLC layer, the MAC layer, and / or the PHY layer, etc.).

[0065] The RU is usually configured to be responsible for the transceiving of air interface radio electromagnetic waves, including antennas, radio frequencies and part of the PHY layer functions.

[0066] The DU and the RU can cooperate to jointly implement the functions of the PHY layer. One DU can be connected with one or more RUs. The functions of the DU and the RU can be configured in multiple ways according to design. For example, the DU is configured to implement baseband functions, and the RU is configured to implement radio frequency functions. For another example, the DU is configured to implement high-layer functions in the PHY layer, and the RU is configured to implement low-layer functions in the PHY layer or implement the low-layer functions and radio frequency functions. The high-layer functions in the PHY layer can include a part of functions of the PHY layer that are closer to the MAC layer, and the low-layer functions in the PHY layer can include another part of functions of the PHY layer that are closer to the radio frequency side.

[0067] The connection between the CU and the DU is referred to as backhaul. The connection between the DU and the RU is referred to as fronthaul. On the fronthaul, mainly in-phase quadrature (IQ) signals are transmitted, which requires low latency and high bandwidth. The one-way latency requirement is 100-250 us, and the bandwidth requirement is several times the air interface data rate. For example, when the evolved Common Public Radio Interface (eCPRI) protocol is used for the fronthaul, the bandwidth requirement of the fronthaul is about 4-5 times the air interface rate.

[0068] In recent years, with the increasing requirements of operators on the flexibility of wireless networks in construction, deployment, and operation and maintenance, cloud technology has been introduced into the field of Radio Access Network (RAN), and through the cloud deployment of CUs and DUs, i.e., Cloud RAN, the flexibility and deployment speed of the RAN are improved, more flexible resource scheduling and load balancing are achieved, and the deployment and operation and maintenance costs are reduced.

[0069] However, for the DU, since the DU needs to process a large number of uplink and downlink messages related to the RU, and each message needs to perform a series of complex baseband processing steps, currently, in the DU, a dedicated hardware is usually used to perform a series of baseband processing steps on the messages. The dedicated hardware is highly specialized and can efficiently complete all baseband processing steps corresponding to the uplink and downlink messages in time. However, if a single dedicated hardware is used to complete a series of baseband processing steps on the messages in the DU, it is often difficult to achieve flexible expansion, resulting in the difficulty of cloud deployment of the DU. On the other hand, if general hardware is used to complete the complex processing of the uplink and downlink messages in the cloud-deployed DU, the energy consumption of the DU will be high.

[0070] Therefore, the application provides a baseband processing system, which is configured by a first processor, a first accelerator and a second accelerator, and the baseband processing steps performed by the first accelerator and the second accelerator are configured based on the first processor, so that the first accelerator and the second accelerator jointly complete a series of baseband processing steps of data. In addition, the communication link supporting direct communication is provided between the first accelerator and the second accelerator, so as to ensure that the data interaction between the first accelerator and the second accelerator can be directly implemented. In this way, by distributing a series of baseband processing steps in the message data processing flow to a plurality of accelerators for execution, each accelerator can only focus on executing a specific baseband processing step, the specificity of the accelerator is improved, the data is transmitted between the accelerators through the communication link supporting peer-to-peer communication, so as to realize the efficient cooperation between different accelerators, thereby reducing the energy consumption of the baseband processing system as a whole. In addition, a plurality of accelerators configured by the processor are provided in the baseband processing system, so that the configuration or expansion of the accelerators can be flexibly performed based on the actual scene, the flexibility of the baseband processing system is improved, and the flexibility requirement of the cloud base station is met.

[0071] Referring to FIG. 2, FIG. 2 is a structural schematic diagram of a baseband processing system provided by the application. As shown in FIG. 2, the baseband processing system comprises a first processor, a first accelerator and a second accelerator. The first accelerator and the second accelerator have a communication link therebetween, which is used to support the direct communication between the first accelerator and the second accelerator. That is, the communication link between the first accelerator and the second accelerator is a peer-to-peer communication bus, that is, the data transmission between the first accelerator and the second accelerator can be directly completed based on the peer-to-peer communication bus, without the need to pass through a centralized control node (such as the first processor). For example, the communication link between the first accelerator and the second accelerator is, for example, a unified bus (UB), an ultra accelerator link (UALink) bus, an Nvlink bus or a compute express link (CXL) bus.

[0072] In addition, the first processor and the first accelerator have a communication link therebetween, and the first processor and the second accelerator have a communication link therebetween, so as to support the interaction between the first processor and the first accelerator and the second accelerator.

[0073] In the baseband processing system, the first processor is configured to configure the first accelerator to perform a first baseband processing step and configure the second accelerator to perform a second baseband processing step.

[0074] The first acceleration device is configured to perform a first baseband processing step on input first data and send the processed data to the second acceleration device. The second acceleration device is configured to perform a second baseband processing step on the data sent by the first acceleration device to obtain target data. The first baseband processing step can include one or more baseband processing steps, and the second baseband processing step can include another one or more baseband processing steps.

[0075] That is, by configuring the first acceleration device and the second acceleration device by the first processor, the first acceleration device and the second acceleration device can jointly complete a series of baseband processing steps of the packet data. The first acceleration device and the second acceleration device only complete part of the series of baseband processing steps of the packet data, and the processing steps performed by the first acceleration device and the second acceleration device do not overlap. After the first acceleration device completes the configured first baseband processing step on the input first data, the processed data is directly sent to the second acceleration device without the mediation of other components (such as a processor or a host memory), ensuring the efficiency of the joint baseband processing of the first acceleration device and the second acceleration device.

[0076] Exemplarily, referring to FIG. 3, FIG. 3 is a schematic diagram of the joint completion of a series of baseband processing steps by the first acceleration device and the second acceleration device. As shown in FIG. 3, taking the joint processing of the data of a physical uplink shared channel (PUSCH) by the first acceleration device and the second acceleration device as an example, the first baseband processing step performed by the first acceleration device on the input first data (i.e., the PUSCH data) includes RE demapping, channel estimation, and receiver equalization, and the second baseband processing performed by the second acceleration device on the data sent by the first acceleration device includes demodulation, descrambling, de-rate matching, LDPC decoding, and transport block (TB) generation.

[0077] It should be noted that FIG. 3 is an example of the joint processing of the PUSCH data by the first acceleration device and the second acceleration device to introduce the baseband processing steps performed by the first acceleration device and the second acceleration device. When the first acceleration device and the second acceleration device process other types of data, the baseband processing steps performed by the first acceleration device and the second acceleration device can be other types of steps, which are not limited herein. In general, the first processor can configure the baseband processing steps performed by the first acceleration device and the second acceleration device when processing various types of data.

[0078] In addition, the above describes that the first accelerator and the second accelerator jointly complete the baseband processing of data. In actual application, the first processor can be configured with two or more than two accelerators to jointly complete the baseband processing of data. That is, in addition to the first accelerator and the second accelerator, the baseband processing system can also include other accelerators. In this case, the target data obtained by the second accelerator performing the second baseband processing step can continue to be sent to other accelerators for processing.

[0079] The first processor can be a central processing unit (CPU). The first accelerator and the second accelerator can be FPGA chips, application-specific integrated circuit (ASIC) chips, networking processors (NP), CPUs, graphics processing units (GPU), neural-network processing units (NPU), or tensor processing units (TPU).

[0080] In addition, the first accelerator and the second accelerator can be different structures of hardware (for example, the first accelerator is a GPU, and the second accelerator is an ASIC chip). Alternatively, the first accelerator and the second accelerator are the same structure of hardware (for example, the first accelerator and the second accelerator are both ASIC chips).

[0081] Optionally, the first processor, the first accelerator, and the second accelerator can be deployed on the same device, such as a base station device or a server.

[0082] Optionally, in some scenarios, according to the difference between the processing steps, the first accelerator can have more general computing power, for example, the first accelerator is a GPU, and the second accelerator can have higher energy efficiency, for example, the second accelerator is a more specialized ASIC chip. Generally speaking, the more specialized the accelerator is, the fewer types of baseband tasks the accelerator can process, but the higher the energy efficiency of the accelerator is. In this way, by configuring the first accelerator with stronger general computing power and the second accelerator with stronger special line, the baseband processing can be jointly completed, which can ensure that the baseband processing system has strong general performance and energy efficiency at the same time, facilitating subsequent flexible configuration of the accelerator.

[0083] Exemplarily, refer to FIG. 4, which is a flowchart of a process in which a first accelerator and a second accelerator perform baseband processing based on a configuration of a first processor. As shown in FIG. 4, the process in which the first accelerator and the second accelerator perform baseband processing based on the configuration of the first processor includes the following steps 401-408.

[0084] In step 401, the first processor configures the first accelerator to perform a first baseband processing step, and configures the second accelerator to perform a second baseband processing step.

[0085] Specifically, the first processor can send configuration information to the first accelerator and the second accelerator respectively, to achieve the configuration of the first accelerator to perform the first baseband processing step, and the configuration of the second accelerator to perform the second baseband processing step. For example, the first baseband processing step performed by the first accelerator configured by the first processor includes three steps of RE demapping, channel estimation, and receiver equalization, and the second baseband processing step performed by the second accelerator configured by the first processor includes five steps of demodulation, descrambling, rate matching, LDPC decoding, and TB generation.

[0086] In addition, in order to ensure that the first accelerator and the second accelerator can successfully complete the baseband processing, the first processor can further configure the first accelerator and the second accelerator with the address of the input data of the respective processing process (including the description of PUSCH data and data format), the task start signal, the output address of the processed data, and the task end signal (including the receiving object and the signal value). Among them, the first processor configures the memory address of the second accelerator as the output address of the processed data of the first accelerator. In addition, the first processor configures the first task start signal as the start signal of the first accelerator, and configures the first accelerator to send the second task start signal to the second accelerator after completing the data output. Moreover, the first processor configures the second task start signal as the start signal of the second accelerator.

[0087] In step 402, the first accelerator receives the first task start signal.

[0088] After the baseband processing system obtains the data to be processed, the first accelerator can be triggered to process the data, so that the first accelerator receives the first task start signal. The first task start signal is, for example, a signal sent by the first processor or a clock interrupt signal.

[0089] In step 403, the first accelerator obtains the input data from the configured address and performs the first baseband processing step.

[0090] The first acceleration device receives the first task start signal, and obtains the input data (i.e., the first data) from the address configured by the first processor (e.g., a memory address in the first acceleration device, where the input data to be processed has been written into the memory space in the acceleration device), and performs the configured first baseband processing step.

[0091] Optionally, in some scenarios, the first data can be located on the memory used by the first processor, and the first acceleration device obtains the first data from the memory used by the first processor after receiving the first task start signal (i.e., the address of the input data configured by the first processor is the address of the memory used by the first processor). Please refer to FIG. 5, which is a structural schematic diagram of another baseband processing system provided by the present application. As shown in FIG. 5, in the baseband processing system, the first acceleration device and the second acceleration device are also connected to the memory used by the first processor through a communication link. In this way, the first acceleration device can directly read data from the memory used by the first processor through the communication link, and the second acceleration device can also directly write data into the memory used by the first processor based on the communication link.

[0092] In this solution, by directly reading the input data from the memory used by the first processor by the first acceleration device, the step of forwarding the input data by the first processor to the first acceleration device can be omitted, the efficiency of data processing is improved, and the processing pressure of the first processor is reduced.

[0093] Step 404: The first acceleration device sends the processed data to the second acceleration device.

[0094] After performing the first baseband processing step on the input data, the first acceleration device can obtain the data after performing the first baseband processing step (hereinafter referred to as processed data). Therefore, the first acceleration device sends the processed data to the second acceleration device according to the output address of the processed data configured by the first processor. Specifically, the output address of the processed data configured by the first processor for the first acceleration device can be the address of the memory of the second acceleration device. Therefore, the first acceleration device can write the processed data into the address of the memory of the second acceleration device through the peer-to-peer communication bus, so as to send the processed data to the second acceleration device.

[0095] Step 405: The first acceleration device sends a second task start signal to the second acceleration device.

[0096] After writing the processed data into the memory of the second acceleration device, the first acceleration device can send a second task start signal to the second acceleration device according to the configuration of the first processor.

[0097] At step 406, the second acceleration device obtains the processed data sent by the first acceleration device from the configured address, and performs the second baseband processing step.

[0098] For the second acceleration device, the second task start signal sent by the first acceleration device is the task start signal configured by the first processor for the second acceleration device. Therefore, after receiving the second task start signal, the second acceleration device triggers obtaining the processed data sent by the first acceleration device from the configured address, and performing the second baseband processing step.

[0099] At step 407, the second acceleration device outputs the target data obtained by performing the second baseband processing step.

[0100] After completing the second baseband processing step, the second acceleration device can output the obtained target data according to the configuration of the first processor, for example, send the target data to the first processor, so that the first processor continues to perform subsequent processing steps or forwards the target data to other components.

[0101] Alternatively, when the first processor configures the first acceleration device, the second acceleration device and other acceleration devices to jointly complete the baseband processing of the data, the second acceleration device can continue to send the obtained target data to other acceleration devices, so that other acceleration devices continue to complete the baseband processing.

[0102] At step 408, the second acceleration device sends a task completion signal.

[0103] After the second acceleration device outputs the target data, the second acceleration device can send a task completion signal to a specified object (for example, the first processor or other acceleration devices), to trigger further processing of the target data by the specified object.

[0104] Optionally, the baseband processing system further includes a second processor. The first processor and the first acceleration device are located on a first device, and the second processor and the second acceleration device are located on a second device. The first processor is specifically configured to negotiate with the second processor to configure the first acceleration device to perform the first baseband processing step and configure the second acceleration device to perform the second baseband processing step.

[0105] That is, the first acceleration device and the second acceleration device are actually located on different devices and are managed by different processors. Therefore, in order to realize the joint execution of the baseband processing by the acceleration devices on different devices, the processors on the two devices can first negotiate, so as to determine how the first acceleration device and the second acceleration device cooperatively perform the baseband processing.

[0106] Optionally, please refer to FIG. 6, which is a structural schematic diagram of another baseband processing system provided by the present application. As shown in FIG. 6, a data exchange device is connected between the first device and the second device, and the first acceleration device is configured to send the processed data to the second acceleration device through the data exchange device. The data exchange device is, for example, a switch, a router, or a hub. The data exchange device needs to support a cross-device direct communication link, for example, a peer-to-peer communication bus protocol, so that the first acceleration device can directly send the processed data to the second acceleration device through the data exchange device.

[0107] Exemplarily, please refer to FIG. 7, which is a flowchart of a process of performing baseband processing based on a configuration of a first processor by a first acceleration device and a second acceleration device located on different devices. As shown in FIG. 7, the process of performing baseband processing based on the configuration of the first processor by the first acceleration device and the second acceleration device includes the following steps 701-709.

[0108] In step 701, the first processor and the second processor negotiate to jointly perform baseband processing by the first acceleration device and the second acceleration device.

[0109] Specifically, the content negotiated by the first processor and the second processor can include, for example, a baseband processing step performed by the second acceleration device, an output address of the data processed by the first acceleration device (i.e., an address of the input data of the second acceleration device), a task completion signal of the first acceleration device (i.e., a task start signal of the second acceleration device), and the like.

[0110] In step 702, the first acceleration device is configured to perform a first baseband processing step, and the second acceleration device is configured to perform a second baseband processing step.

[0111] After the first processor and the second processor complete the negotiation, the configuration of the first acceleration device and the second acceleration device can be performed. Specifically, in this step, the first acceleration device can be configured by the first processor to perform the first baseband processing step, and the second acceleration device can be configured by the first processor to perform the second baseband processing step. In this step, the first acceleration device can also be configured by the first processor to perform the first baseband processing step, and the second acceleration device can be configured by the second processor to perform the second baseband processing step.

[0112] In step 703, the first acceleration device receives a first task start signal.

[0113] In step 704, the first acceleration device obtains input data from the configured address and performs the first baseband processing step.

[0114] The steps 703-704 are similar to the steps 402-403, and details are referred to the steps 402-403, and details are not described herein again.

[0115] In step 705, the first accelerator sends the processed data to the second accelerator through the data exchange device.

[0116] After obtaining the data sent by the first accelerator, since the second accelerator is on the second device, the first accelerator needs to send the output data to the second accelerator through the data exchange device, for example, directly writing the output data into the memory of the second accelerator through the switch.

[0117] In step 706, the first accelerator sends a second task start signal to the second accelerator.

[0118] In step 707, the second accelerator obtains the processed data sent by the first accelerator from the configured address, and performs a second baseband processing step.

[0119] In step 708, the second accelerator outputs the target data obtained by performing the second baseband processing step.

[0120] In step 709, the second accelerator sends a task completion signal.

[0121] The steps 706-709 are similar to the steps 405-408, and details are referred to the steps 405-408, and details are not described herein again.

[0122] Optionally, referring to FIG. 8, FIG. 8 is a schematic diagram of another baseband processing system provided by the application. As shown in FIG. 8, in addition to the first processor, the first accelerator and the second accelerator, the baseband processing system further includes a network card. The network card is configured to receive the front-haul data, and write the first data including the IQ signal in the front-haul data into the memory of the first accelerator, so that the first accelerator obtains the first data from the memory thereof.

[0123] That is, the first processor can configure the network card, so as to configure the network card to write the first data including the IQ signal in the received front-haul data into the memory of the first accelerator. For example, the first processor sends configuration information to the network card, and the configuration information is configured to indicate that the storage address of the first data is the memory address in the first accelerator.

[0124] In the case that the baseband processing system has the network card, the processing flow of the uplink data and the downlink data is as follows.

[0125] The uplink data processing flow is as follows: according to the configuration of the first processor, the network card receives the fronthaul data from the fronthaul interface, and after optional fronthaul decompression processing, the network card directly writes the first data (for example, the payload in the fronthaul data packet) including the IQ signal in the fronthaul data into the memory of the first acceleration device, and sequentially passes through the processing of the first acceleration device and the second acceleration device, to complete the baseband processing flow of the uplink data.

[0126] For example, referring to FIG. 9, FIG. 9 is a schematic diagram of a network card, a first acceleration device and a second acceleration device jointly completing a series of baseband processing steps provided by the present application. As shown in FIG. 9, for the fronthaul data of the uplink, after the network card receives the fronthaul data packet and performs optional fronthaul decompression processing, the network card sends the data including the IQ signal in the fronthaul data to the first acceleration device. Then, the first acceleration device sequentially performs RE demapping, channel estimation, receiver equalization on the data including the IQ signal, and the second acceleration device continues to perform demodulation, descrambling, rate matching, LDPC decoding and TB generation on the data processed by the first acceleration device.

[0127] The downlink data processing flow is the inverse process of the uplink data processing flow. The downlink TB data packet sequentially passes through the processing of the second acceleration device and the first acceleration device, and is directly sent to the network card. After optional fronthaul compression processing, the data is sent out through the fronthaul interface. As shown in FIG. 9, for the downlink data, the second acceleration device sequentially performs TB CRC addition, LDPC encoding, rate matching, scrambling and modulation on the downlink data, and the first acceleration device continues to perform layer mapping, precoding and RE mapping on the output data of the second acceleration device. Finally, the network card performs optional fronthaul compression processing on the output data of the first acceleration device, and sends the processed data out through the fronthaul interface.

[0128] For example, referring to FIG. 10, FIG. 10 is a flowchart of a network card, a first acceleration device and a second acceleration device completing baseband processing based on the configuration of a first processor provided by the present application. As shown in FIG. 10, the flow of the network card, the first acceleration device and the second acceleration device completing baseband processing based on the configuration of the first processor includes the following steps 1001-1010.

[0129] Step 1001, the first processor configures the network card.

[0130] Specifically, the first processor can send configuration information to the network card, and the configuration information is used to instruct the network card to write the fronthaul data including the IQ signal into the memory address of the first acceleration device through the communication link after receiving the fronthaul data including the IQ signal.

[0131] Step 1002, the first processor configures the first acceleration device to perform the first baseband processing step, and configures the second acceleration device to perform the second baseband processing step.

[0132] Step 1003, the network card writes the received fronthaul data including the IQ signal to the memory of the first acceleration device.

[0133] After the network card receives the fronthaul data through the fronthaul interface, the network card can write the received fronthaul data including the IQ signal to the memory of the first acceleration device according to the configuration of the first processor.

[0134] Step 1004, the first acceleration device receives the first task start signal.

[0135] After the network card completes the data writing, the first acceleration device can receive the first task start signal. The first task start signal may be, for example, from the first processor or the network card.

[0136] Specifically, if the network card does not have the function of processing the fronthaul protocol, the network card can send the header of the received fronthaul data packet to the first processor, and send the payload of the fronthaul data packet to the first acceleration device. The first processor determines that the uplink data of a symbol or a slot is received according to the received header, and then sends a task start signal to the first acceleration device.

[0137] If the network card has the function of processing the fronthaul protocol, the network card itself can determine whether the uplink data of a symbol or a slot has been received, so the network card can directly send the first task start signal to the first acceleration device.

[0138] Step 1005, the first acceleration device obtains input data from the configured address and performs the first baseband processing step.

[0139] The input data obtained by the first acceleration device from the configured address is actually the fronthaul data including the IQ signal sent by the network card.

[0140] Step 1006, the first acceleration device sends the processed data to the second acceleration device.

[0141] After obtaining the processed data, the first acceleration device directly sends the processed data to the second acceleration device through the peer-to-peer communication bus. If the second acceleration device is on the second device, the first acceleration device can send the processed data to the second acceleration device through the data exchange device, for example, directly write the processed data into the memory of the second acceleration device through the switch.

[0142] Step 1007, the first acceleration device sends a second task start signal to the second acceleration device.

[0143] Step 1008, the second acceleration device obtains the processed data sent by the first acceleration device from the configured address, and performs a second baseband processing step.

[0144] Step 1009, the second acceleration device outputs target data obtained by performing the second baseband processing step.

[0145] Step 1010, the second acceleration device sends a task completion signal.

[0146] Among them, steps 1005-1010 are similar to steps 403-408 described above, please refer to steps 403-408 described above for details, which will not be repeated here.

[0147] Optionally, as shown in FIG. 11, FIG. 11 is a structural schematic diagram of another baseband processing system provided by the application. In order to realize high integration of the device, the network card can be integrated on the first acceleration device. That is, the network card and the first acceleration device are combined, which can also be understood as the first acceleration device also has the function of transmitting and receiving front-end data.

[0148] In the case of integrating the network card on the first acceleration device, compared with the flow shown in FIG. 10, the interaction process between each component in the baseband processing system can have the following differences.

[0149] Difference 1: In the configuration obtained by the first acceleration device from the first processor, the address of the input data can be omitted, that is, the address of the input data is determined by the first acceleration device itself (that is, the first acceleration device determines where the front-end data received by the network card should be stored).

[0150] Difference 2: In the configuration obtained by the first acceleration device from the first processor, the first task start signal is optional. That is, the first acceleration device can determine the processing start time by itself according to the internal implementation, such as starting after the front-end data of one symbol or slot of the air interface is written into the memory, so that the first acceleration device does not need to be configured with the first task start signal.

[0151] Exemplarily, the first acceleration device is configured to perform a first baseband processing step on the data containing the IQ signal received by the network card after the data containing the IQ signal meets the rule configured by the first processor. Among them, the rule configured by the first processor is, for example, that the first acceleration device has received all the data containing the IQ signal of one symbol or slot through the network card.

[0152] Correspondingly, for downlink data, the address of the output data and the task completion signal in the configuration obtained by the first acceleration device from the first processor can also be optional. After the first acceleration device completes the baseband processing, the processed data is directly sent out through the integrated network card of the first acceleration device, and the first acceleration device does not need to send a task completion signal to other devices.

[0153] Referring to FIG. 12A, FIG. 12A is a schematic diagram of the network card forwarding the first data and the second data provided in the present application. As shown in FIG. 12A, the baseband processing system includes a first processor, a network card, a first acceleration device, a second acceleration device, and a third acceleration device. In addition to sending the received first data to the first acceleration device, the network card is also configured to receive second data and write the second data into the memory of the third acceleration device. The third acceleration device is configured to perform a baseband processing step on the second data.

[0154] That is, the network card actually sends different data to different acceleration devices for processing according to the configuration of the first processor, thereby achieving load sharing among the acceleration devices. In this way, by configuring the network card to send data to different acceleration devices, the multiple acceleration devices in the baseband processing system can be flexibly configured based on actual needs to process various data, thereby improving the flexibility of the scheme.

[0155] It should be noted that other acceleration devices can also be included in the baseband processing system, and the third acceleration device can be used in combination with other acceleration devices to implement the baseband processing of the second data.

[0156] Generally, an optical fiber (such as a 100 Gbps bandwidth optical fiber) used on a front-haul interface usually transmits front-haul data of multiple cells (such as each cell having a front-haul bandwidth requirement of 25 Gbps). One requirement of a cloud base station is to support flexible deployment and scaling of cell processing resources. Therefore, in one possible example, the network card includes programmable functions, and the network card can distribute front-haul data of different cells to different acceleration devices for processing according to the configuration.

[0157] In one possible example, the source address of the front-haul data packet to which the first data belongs is a first address, and the first address is the front-haul link address of a first cell. The source address of the front-haul data packet to which the second data belongs is a second address, and the second address is the front-haul link address of a second cell.

[0158] The first processor is further configured to configure the network card to send the first data to the first acceleration device and send the second data to the third acceleration device. In this way, when the network card receives the first data and the second data, the first data can be sent to the first acceleration device according to the source address of the first data, and the second data can be sent to the third acceleration device according to the source address of the second data. For example, refer to FIG. 12B, which is a schematic diagram of the network card forwarding the first data and the second data provided in the present application. As shown in FIG. 12B, for the first data belonging to the cell 1, the network card sends the first data to the first acceleration device according to the source address of the first data. For the second data belonging to the cell 2, the network card sends the second data to the third acceleration device according to the source address of the second data.

[0159] That is, by configuring the network card on the first processor to send the front-haul data of different source addresses to different acceleration devices, the shunting processing of the front-haul data of different addresses can be realized, so that the front-haul data of different cells can be shunted to different acceleration devices for processing, so as to meet the cloudification requirements of the base station in actual application.

[0160] In another possible example, the front-haul data to which the first data belongs is a first type of front-haul data, and the front-haul data to which the second data belongs is a second type of front-haul data; the first processor is further configured to configure the network card to send the first data to the first acceleration device and send the second data to the third acceleration device.

[0161] That is, the first processor can configure the network card to process different types of front-haul data to different acceleration devices, so that different types of front-haul data can be shunted to different acceleration devices for processing.

[0162] Generally, different types of front-haul data can be processed by different methods. Therefore, by shunting different types of front-haul data to different acceleration devices for processing, the acceleration device can be focused on processing a specific type of front-haul data, so as to use a more specialized acceleration device to perform the baseband processing step, thereby improving the energy efficiency of the baseband processing system as a whole.

[0163] Optionally, the first type of fronthaul data is used to transmit data of one air interface signal or air interface channel, and the second type of fronthaul data is used to transmit data of another air interface signal or air interface channel. For example, the air interface signal to which the data transmitted by the first type of fronthaul data belongs is a sounding reference signal (SRS) or a de-modulation reference signal (DMRS), or the air interface channel to which the data transmitted by the first type of fronthaul data belongs is a PUSCH, a physical uplink control channel (PUCCH), or a physical random access channel (PRACH). The air interface channel to which the data transmitted by the second type of fronthaul data belongs is a PUSCH, a PUCCH, or a PRACH, or the air interface signal to which the data transmitted by the second type of fronthaul data belongs is an SRS or a DMRS. Alternatively, the first type of fronthaul data is used to transmit air interface data of a first frequency band (e.g., a high frequency band), and the second type of fronthaul data is used to transmit air interface data of a second frequency band (e.g., a low frequency band).

[0164] Exemplarily, referring to FIG. 12C, FIG. 12C is a schematic diagram of a network card forwarding first data and second data according to another embodiment of the present application. As shown in FIG. 12C, for the first data belonging to the fronthaul data of a PUSCH, the network card sends the first data to the first accelerator according to the type of the fronthaul data to which the first data belongs. For the second data belonging to the fronthaul data of an SRS, the network card sends the second data to the third accelerator according to the type of the fronthaul data to which the second data belongs.

[0165] Referring to FIG. 12D, FIG. 12D is a schematic diagram of a format of a fronthaul eCPRI data packet according to an embodiment of the present application. As shown in FIG. 12D, the field PC_ID in the Payload of the fronthaul eCPRI data packet is used to identify a set of a series of IQ messages (such as a physical channel, a user, a stream, or an antenna port), and the field SEQ_ID is used to identify a specific message (such as an OFDM symbol or a subcarrier) in the set of IQ messages. Therefore, based on the values of the fields PC_ID and SEQ_ID in the Payload of the received fronthaul eCPRI data packet, the type of the fronthaul eCPRI data packet can be determined, and then the Payload in the fronthaul eCPRI data packet is sent to the corresponding accelerator for processing.

[0166] Optionally, referring to FIG. 13, FIG. 13 is a structural schematic diagram of another baseband processing system provided by the present application. As shown in FIG. 13, the network card, the first acceleration device and the second acceleration device are located on the first device, and the second processor and the third acceleration device are located on the second device. Moreover, the data exchange device is connected between the first device and the second device, and the data exchange device supports a direct communication link across devices, so that the network card can directly send data to the third acceleration device through the data exchange device. The first processor is further configured to negotiate with the second processor to configure the third acceleration device to perform the baseband processing step.

[0167] That is, the network card, the first acceleration device and the second acceleration device are located on the same device, and the third acceleration device is located on another device. The network card sends different data received to the acceleration devices on the same device and the acceleration device on the other device for processing.

[0168] In the present solution, by forwarding different types of data to the acceleration devices on different devices for processing by the network card, independent processing of different data can be achieved, and the acceleration devices are independent of each other and do not affect each other, which is conducive to flexible upgrading of the acceleration devices. For example, in the case of performing processing function upgrading for certain data (such as data of a certain type or data from a certain cell), the data can be shunted to a new acceleration device for processing to ensure that the original business data processing process is not affected.

[0169] Optionally, in order to adaptively adjust the steps processed by the acceleration devices according to the actual running situation in the application process, the first processor can configure different baseband processing steps for the acceleration devices at different time nodes to ensure that the process of the acceleration devices performing the baseband processing steps can meet the actual running requirements.

[0170] For example, the first processor is specifically configured to configure the first acceleration device to perform a first baseband processing step and configure the second acceleration device to perform a second baseband processing step at a first time node. Moreover, the first processor is further configured to configure the first acceleration device to perform a third baseband processing step and configure the second acceleration device to perform a fourth baseband processing step at a second time node.

[0171] Among them, the processing steps included in the third baseband processing step are different from the processing steps included in the first baseband processing step, and the processing steps included in the fourth baseband processing step are different from the processing steps included in the second baseband processing step.

[0172] That is, at the first time node, the first acceleration device is configured to perform the first baseband processing step; at the second time node, the first acceleration device is configured to perform the third baseband processing step. At the first time node, the second acceleration device is configured to perform the second baseband processing step; at the second time node, the second acceleration device is configured to perform the fourth baseband processing step. That is, the first processor can flexibly configure the baseband processing steps actually performed by each acceleration device, so that each acceleration device can perform different baseband processing steps at different time nodes to meet the actual application requirements.

[0173] Optionally, the first acceleration device is further configured to perform a third baseband processing step on the input third data after obtaining a third task start signal, the third task start signal being obtained after the second time node. That is, after the first processor reconfigures the first acceleration device to perform the third baseband processing step, the time node at which the reconfiguration information of the first processor takes effect is the time at which the first acceleration device receives the new task start signal (i.e., the third task start signal). That is, after receiving the new task start signal, the first acceleration device performs the third baseband processing step on the input third data according to the latest reconfiguration information of the first processor.

[0174] Generally, the computing power ratios (such as scalar, vector, tensor, and special computing power) of different acceleration devices are often different. Therefore, for the same baseband processing step, the energy consumption of different acceleration devices performing the baseband processing step is often different. Based on this, in actual applications, the first processor can comprehensively consider factors such as business load, energy consumption, and computing power demand to dynamically configure the acceleration devices to perform different baseband processing steps in different scenarios.

[0175] Exemplarily, the amount of traffic that the first acceleration device needs to process at the first time node is different from the amount of traffic that the first acceleration device needs to process at the second time node. That is, in the case that the amount of traffic of the data to be processed changes, the first processor can trigger adjustment of the baseband processing steps performed by the first acceleration device and the second acceleration device to meet the energy consumption demand or the throughput demand as much as possible.

[0176] Specifically, referring to FIG. 14, FIG. 14 is a schematic diagram of changes in baseband processing steps performed by an accelerator device provided by the present application. As shown in FIG. 14, in a low-load scenario, the amount of data to be processed is small, and thus the computing power required for baseband processing in the low-load scenario is also low. At this time, the first processor can configure the first accelerator device to complete the three baseband processing steps of RE demapping, channel estimation, and receiver equalization (i.e., the first baseband processing steps described above), and the second accelerator device to complete the five baseband processing steps of demodulation, descrambling, de-rate matching, LDPC decoding, and TB generation (i.e., the second baseband processing steps described above), for the purpose of reducing overall power consumption. Because the second accelerator device is more specialized and the first accelerator device is more general-purpose, the energy consumption of the second accelerator device in performing the two baseband processing steps of demodulation and descrambling will be lower than that of the first accelerator device, and thus the low-load scenario is to assign the latter five baseband processing steps to the second accelerator device for completion.

[0177] In a high-load scenario, as the amount of traffic increases, the computing power required for de-rate matching and LDPC decoding increases significantly. In this case, the computing power of the second accelerator device can be difficult to support the second accelerator device to process the five baseband processing steps, and thus the first processor can configure the second accelerator device to focus on completing the three baseband processing steps of de-rate matching, LDPC decoding, and TB generation (i.e., the fourth baseband processing steps described above), and configure the first accelerator device to perform the first five baseband processing steps (i.e., the third baseband processing steps described above), so as to meet the throughput requirements of baseband processing in priority.

[0178] Generally, the first processor can adjust the configuration of different accelerator devices, and the accelerator devices can enable the new configuration at the specified time according to the latest configuration received, so as to realize dynamic adjustment of the acceleration task chain.

[0179] In addition, unlike the traditional tightly coupled integrated cloud-based baseband solution, the baseband processing system provided by the present application can be a system that can be flexibly configured and adjusted, i.e., the accelerator devices in the baseband processing system can be flexibly plugged in and replaced.

[0180] Optionally, please refer to FIG. 15, which is a structural schematic diagram of another baseband processing system provided by the present application. As shown in FIG. 15, the baseband processing system comprises a first processor, a first acceleration device, a second acceleration device and a fourth acceleration device. The fourth acceleration device is added to the baseband processing system after the first processor configures the first acceleration device to perform the first baseband processing step and configures the second acceleration device to perform the second baseband processing step. For example, when the baseband processing algorithm changes or the specification of the baseband processing system needs to be adjusted, a fourth acceleration device can be added to the baseband processing system. For example, the fourth acceleration device is directly inserted into the peer-to-peer communication bus of the baseband processing system, so that the fourth acceleration device can perform peer-to-peer communication with the first processor, the first acceleration device and the second acceleration device.

[0181] After the fourth acceleration device is added to the baseband processing system, the first processor is further configured to reconfigure the first acceleration device and / or the second acceleration device and the baseband processing step performed by the fourth acceleration device based on the capability of the fourth acceleration device. The first processor reconfigures the baseband processing step performed by each acceleration device, which can be that the first acceleration device jointly completes the baseband processing of data with the second acceleration device and the fourth acceleration device, or that the fourth acceleration device replaces the first acceleration device or the second acceleration device to complete the baseband processing of data (i.e., the first acceleration device or the second acceleration device no longer performs the baseband processing of data).

[0182] For example, when the first baseband processing step configured by the first processor for the first acceleration device comprises RE demapping, channel estimation and receiver equalization, and the second baseband processing step configured by the first processor for the second acceleration device comprises demodulation, descrambling, de-rate matching, LDPC decoding and TB generation, if the processing algorithm of the baseband processing steps such as de-rate matching, LDPC decoding and TB generation changes, the first processor can configure the first acceleration device to complete RE demapping, channel estimation and receiver equalization, the second acceleration device to complete demodulation and descrambling, and the fourth acceleration device to complete de-rate matching, LDPC decoding and TB generation. In this way, when the processing algorithm of the baseband processing system is upgraded, the upgrade of the processing algorithm can be completed by flexibly introducing a new acceleration device, and the original acceleration device can still be used, improving the smooth upgradeability and compatibility of the baseband processing system.

[0183] Optionally, after the fourth acceleration device is added to the baseband processing system, the first processor is further configured to send a capability query request to the fourth acceleration device and receive a capability query response returned by the fourth acceleration device, so as to obtain the capability of the fourth acceleration device.

[0184] That is, when the first processor discovers a new accelerator device introduced on the peer-to-peer communication bus, the capability of the new accelerator device needs to be learned so as to arrange the baseband processing task chain. The first processor learns the capability of the new accelerator device through the accelerator device capability discovery process.

[0185] Specifically, when the first processor discovers a new fourth accelerator device introduced on the peer-to-peer communication bus, the first processor sends a capability query request to the fourth accelerator device to request the baseband processing capability of the fourth accelerator device. Then, the fourth accelerator device returns a capability query response to the first processor, and the capability query response includes one or more sets of acceleration capabilities (profiles) supported by the fourth accelerator device and the address of the input data corresponding to each acceleration profile. Wherein, an acceleration profile is a set of one or more baseband processing steps. The address of the input data corresponding to each acceleration profile can be a memory address in the accelerator device that can be accessed through the peer-to-peer communication bus. Taking the UB bus as an example, the address of the input data corresponding to the acceleration profile is the UB memory handle, which includes the UB entity ID representing the UB device and the memory address in the UB device.

[0186] The above introduces a baseband processing system provided by the present application. The following will introduce a network device for deploying the processors and accelerator devices in the above baseband processing system.

[0187] Please refer to FIG. 16, which is a structural schematic diagram of a network device provided by the present application. The network device 1600 can specifically be one device (for example, the first device or the second device described above) in the above baseband processing system, and the like, which is not limited here. Specifically, the network device 1600 includes a receiver 1601, a transmitter 1602, a processor 1603, a memory 1604 and an accelerator device 1605. Wherein, the number of the processor 1603 in the network device 1600 can be one or more, and one processor is taken as an example in FIG. 16; the number of the accelerator device 1605 in the network device 1600 can be one or more, and one accelerator device is taken as an example in FIG. 16. The processor 1603 can include an application processor 16031 and a communication processor 16032. In some embodiments of the present application, the receiver 1601, the transmitter 1602, the processor 1603, the memory 1604 and the accelerator device 1605 can be connected through a peer-to-peer communication bus.

[0188] The memory 1604 can include read-only memory and random access memory, and provide instructions and data to the processor 1603. A portion of the memory 1604 can also include non-volatile random access memory (NVRAM). The memory 1604 stores processor and operating instructions, executable modules, or data structures, or a subset thereof, or an extended set thereof, wherein the operating instructions can include various operating instructions for implementing various operations.

[0189] The processor 1603 controls the operation of the network device. In a specific application, various components of the network device are coupled together through a bus system, which can include a data bus, a power bus, a control bus, and a state signal bus, etc. However, for the sake of clarity, all the buses are referred to as a bus system in the figure.

[0190] The method disclosed in the above embodiments of the present application can be applied to or implemented by the processor 1603 and the acceleration device 1605. The processor 1603 can be an integrated circuit chip with signal processing capability. In the implementation process, each step of the above method can be completed by integrated logic circuits or instructions in software form in the processor 1603. The processor 1603 described above can be a general-purpose processor, a digital signal processor (DSP), a microprocessor, or a microcontroller, and can further include an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component. The processor 1603 can implement or execute the disclosed methods, steps, and logic block diagrams in the embodiments of the present application. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor. The steps of the method disclosed in conjunction with the embodiments of the present application can be directly embodied as a hardware code processor for execution, or a combination of hardware and software modules in the code processor for execution. The software module can be located in a random access memory, a flash memory, a read-only memory, a programmable read-only memory, or an electrically erasable programmable memory, a register, or other mature storage medium in the art. The storage medium is located in the memory 1604, and the processor 1603 reads the information in the memory 1604 and combines the hardware to complete the steps of the above method.

[0191] The receiver 1601 can be used to receive inputted digital or character information, and to generate signal input related to the relevant settings and function control of the network device. The transmitter 1602 can be used to output digital or character information through the first interface; the transmitter 1602 can also be used to send instructions to the disk group through the first interface to modify the data in the disk group; the transmitter 1602 can also include a display device such as a display screen.

Claims

1. A baseband processing system, characterized by, The system comprises: a first processor, a first acceleration device and a second acceleration device, the first acceleration device and the second acceleration device have a communication link therebetween, the communication link is used to support direct communication between the first acceleration device and the second acceleration device; the first processor is configured to configure the first acceleration device to perform a first baseband processing step and configure the second acceleration device to perform a second baseband processing step; the first acceleration device is configured to perform the first baseband processing step on input first data according to the configuration of the first processor, and send the processed data to the second acceleration device through the communication link; the second acceleration device is configured to perform the second baseband processing step on the data sent by the first acceleration device according to the configuration of the first processor, to obtain target data.

2. The system of claim 1, wherein, The first acceleration device is further configured to trigger the first baseband processing step on the first data according to the configuration of the first processor after obtaining a first task start signal; The first acceleration device is further configured to send a second task start signal to the second acceleration device after sending the processed data to the second acceleration device; The second acceleration device is further configured to trigger the second baseband processing step on the data sent by the first acceleration device according to the configuration of the first processor after obtaining the second task start signal.

3. The system of claim 1 or 2, wherein, The first data is located on a memory used by the first processor, and the first acceleration device is configured to obtain the first data from the memory after obtaining a first task start signal.

4. The system of any of claims 1-3, wherein, The system further comprises a second processor; The first processor and the first acceleration device are located on a first device, and the second processor and the second acceleration device are located on a second device; A data exchange device is connected between the first device and the second device, and the data exchange device supports a cross-device direct communication link; The first acceleration device sends the processed data to the second acceleration device through the data exchange device.

5. The system of claim 4, wherein, The first processor is specifically configured to negotiate with the second processor to achieve the configuration of the second acceleration device to perform the second baseband step.

6. The system of claim 1, wherein, The system further comprises a network card; The network card is configured to receive front-haul data, and write the first data including co-directional quadrature IQ signals in the front-haul data into a memory of the first acceleration device, so that the first acceleration device obtains the first data from the memory.

7. The system of claim 6, wherein, The first processor is configured to configure the network card to write the front-haul data including IQ signals into a memory address of the first acceleration device through the communication link after receiving the front-haul data including IQ signals.

8. The system of claim 6, wherein, The network card is integrated on the first acceleration device; The first acceleration device is configured to perform the first baseband processing step on the data including IQ signals received through the network card after the data including IQ signals meets the rules configured by the first processor.

9. The system of any of claims 6-8, wherein, The system further comprises a third acceleration device; The network card is further configured to write second data to the memory of the third acceleration device through the communication link according to the configuration of the first processor. The third acceleration device is configured to perform a baseband processing step on the second data.

10. The system of claim 9, wherein, The first data belongs to front-haul data with a first address as a source address, and the second data belongs to front-haul data with a second address as a source address. The first processor is further configured to configure the network card to send front-haul data with the first address as the source address to the first acceleration device and send front-haul data with the second address as the source address to the third acceleration device.

11. The system of claim 9 or 10, wherein, The first data belongs to first-type front-haul data, and the second data belongs to second-type front-haul data. The first processor is further configured to configure the network card to send the first data to the first acceleration device and send the second data to the third acceleration device.

12. The system of claim 11, wherein, The first-type front-haul data is used to transmit data of one air interface signal or air interface channel, and the second-type front-haul data is used to transmit data of another air interface signal or air interface channel.

13. The system of any of claims 9-12, wherein, The network card, the first acceleration device, and the second acceleration device are located on a first device, the third acceleration device is located on a second device, a data exchange device is connected between the first device and the second device, and the data exchange device supports a direct communication link across devices.

14. The system of claim 13, wherein, The system further includes a second processor, and the first processor is specifically configured to negotiate with the second processor to configure the third acceleration device to perform a baseband processing step.

15. The system of any of claims 1-14, wherein, The first processor is specifically configured to configure the first acceleration device to perform a first baseband processing step and configure the second acceleration device to perform a second baseband processing step at a first time node. The first processor is further configured to configure the first acceleration device to perform a third baseband processing step and configure the second acceleration device to perform a fourth baseband processing step at a second time node. The third baseband processing step includes different processing steps from the first baseband processing step, and the fourth baseband processing step includes different processing steps from the second baseband processing step.

16. The system of claim 15, wherein, The first acceleration device is further configured to perform the third baseband processing step on input third data after obtaining a third task start signal, and the third task start signal is obtained after the second time node.

17. The system of any of claims 15-16, wherein, The system further includes a fourth acceleration device, which is added to the system after the first processor configures the first acceleration device to perform a first baseband processing step and configures the second acceleration device to perform a second baseband processing step. The first processor is further configured to reconfigure the first acceleration device and / or the second acceleration device based on the capability of the fourth acceleration device and a baseband processing step performed by the fourth acceleration device.

18. The system of claim 17, wherein, The first processor is further configured to send a capability query request to the fourth acceleration device and receive a capability query response returned by the fourth acceleration device to obtain the capability of the fourth acceleration device.

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