Intermediate substrate for producing a substrate for a high-electron-mobility transistor

Abstract

The present invention relates to an intermediate substrate (100) for producing a high-electron-mobility transistor (HEMT), the intermediate substrate (100) comprising: o a carrier substrate (10) made of polycrystalline silicon carbide having an electrical resistivity of between 1 Ω.cm and 10 kΩ.cm; and o a seed layer (20) made of monocrystalline GaN, the intermediate substrate (100) further comprising a direct bonding interface (15) with or without the addition of material between the silicon carbide of the carrier substrate (10) and the seed layer (20).

Description

[0001] INTERMEDIATE SUBSTRATE FOR THE FABRICATION OF A SUBSTRATE FOR A HIGH ELECTRON MOBILITY TRANSISTOR

[0002] FIELD OF INVENTION

[0003] The present invention relates to an intermediate substrate for the fabrication of a high-electron-mobility transistor and a transistor fabricated from such an intermediate substrate. The invention also relates to a method for fabricating an intermediate substrate and a high-electron-mobility transistor.

[0004] STATE OF THE ART

[0005] High electron mobility transistors (HEMTs) are power transistors based on an III-V semiconductor, particularly gallium nitride (GaN). Since bulk gallium nitride substrates are unavailable, HEMTs are typically fabricated on a GaN layer deposited epitaxially onto a silicon substrate. A known HEMT is described, for example, in document EP2983195 A1.

[0006] Silicon exhibits different structural and mechanical properties than GaN, particularly in terms of its crystal lattice and coefficient of thermal expansion. This results in significant stress accumulation within the GaN, which increases as the GaN layer thickness increases. To compensate for these differences, intermediate layers are added between the silicon substrate and the GaN layers. These intermediate layers typically consist of aluminum nitride (AIN) and gallium aluminum nitride (AIGaN). However, these intermediate layers have high electrical and thermal conductivity, which negatively impacts the operation of the HEMT transistor.

[0007] Figure 1 schematically illustrates a known HEMT. The HEMT comprises, from its base to its surface, a silicon substrate 11 with a plurality of intermediate layers 21, a GaN buffer layer 31, a GaN channel 41, and an AIGaN barrier layer 51. The channel and barrier layer form a heterojunction, allowing the formation of a two-dimensional electron gas confined within the channel. The source electrode 61 and drain electrode 62 are formed on the channel 41. The gate electrode 63 is arranged on the barrier layer 51.

[0008] The blocking voltage of the HEMT depends on the total thickness of the layers arranged between the substrate 11 and the barrier layer 51, i.e., the sum of the thicknesses of the intermediate layers 21, the buffer layer 31, and the channel 41. To obtain a HEMT with a high blocking voltage, it would be necessary to deposit a very thick GaN buffer layer. For example, fabricating a HEMT with a known geometry and a blocking voltage greater than or equal to 1200 V would require a GaN layer approximately 8 pm thick in total, including a possible seed layer and / or intermediate layers 21 for thermomechanical adaptation. The thickness of the GaN layer is limited by the difference in coefficient of thermal expansion between silicon and GaN despite the intermediate layers, and depositing a GaN layer thicker than 8 pm would cause the substrate to break.

[0009] The blocking voltage also depends on the LGD distance between the gate electrode 63 and the drain electrode 62. Another solution to increase the blocking voltage would therefore be to significantly increase the LGD distance between the gate electrode 63 and the drain electrode 62. However, the distance between the gate electrode and the drain electrode is limited by the dimensions of the transistor.

[0010] It is not currently possible to obtain a HEMT exhibiting a blocking voltage of approximately 1200 V from such a structure.

[0011] DESCRIPTION OF THE INVENTION

[0012] One aim of the invention is to provide a substrate for the manufacture of a gallium nitride-based HEMT exhibiting a high blocking voltage, in particular greater than 1200 V.

[0013] To this end, the invention proposes an intermediate substrate for the fabrication of a high electron mobility transistor, comprising:

[0014] • a polycrystalline silicon carbide support substrate with an electrical resistivity between 1 G.cm and 10 kG.cm, and

[0015] • a seed layer in single-crystal GaN, said intermediate substrate comprising a direct bonding interface with or without material addition between the silicon carbide of the support substrate and the seed layer.

[0016] Preferably, the polycrystalline silicon carbide support substrate has an electrical resistivity between 1 G.cm and 5 kG.cm, preferably between 1 G.cm and 1000 G.cm, more preferably between 10 G.cm and 1000 G.cm and even more preferably between 100 G.cm and 1000 G.cm.

[0017] Silicon carbide has very good thermal conductivity, which helps to limit heating during transistor operation.

[0018] Furthermore, polycrystalline SiC has a coefficient of thermal expansion close to that of gallium nitride, allowing the deposition of a GaN layer up to 10 pm thick while minimizing the risk of substrate failure.

[0019] The band gap of polycrystalline SiC allows the fabrication of HEMTs with a particularly high blocking voltage relative to their dimensions. Specifically, a high blocking voltage can be fabricated using a polycrystalline SiC substrate with relatively low electrical resistivity.

[0020] Furthermore, it is possible to obtain a high blocking voltage with a buffer layer thickness that is lower than the thickness of buffer layers applied to silicon substrates.

[0021] Preferably, the support substrate has a thickness between 300 and 500 µm.

[0022] Advantageously, the germ layer has a thickness between 10 nm and 1 pm.

[0023] Advantageously, the direct bonding interface is a bonding layer arranged between the support substrate and the seed layer.

[0024] The invention also relates to a substrate for a high electron mobility transistor comprising an intermediate substrate as described above and a first epitaxial layer of single-crystal GaN or single-crystal AiGaN, the first epitaxial layer and the seed layer together forming a buffer layer.

[0025] Preferably, the buffer layer has a thickness between 3.5 and 5.5 pm.

[0026] The buffer layer can be made of carbon-doped GaN or unintentionally doped GaN.

[0027] Preferably, the substrate includes, on the buffer layer, a second unintentionally doped epitaxial layer of GaN configured to form a channel of the transistor.

[0028] The invention also relates to a high electron mobility transistor, comprising

[0029] • a substrate as described above,

[0030] • a GaN channel arranged on the buffer layer,

[0031] • a barrier layer forming a heterojunction with the channel, adapted to generate a two-dimensional electron gas in the channel,

[0032] • a source electrode and a drain electrode electrically connected to the channel,

[0033] • a grid electrode formed on the barrier layer so that the grid electrode is physically isolated from the channel.

[0034] The invention also relates to a substrate for a high electron mobility transistor, said substrate comprising, from its base to its surface:

[0035] • an intermediate substrate as described above,

[0036] • a first epitaxial layer of single-crystal GaN or single-crystal AIGaN, the first epitaxial layer and the seed layer together forming a buffer layer of single-crystal GaN or single-crystal AIGaN, a second epitaxial layer of unintentionally doped GaN configured to form a channel of the transistor.

[0037] Preferably, the buffer layer has a thickness between 3.5 and 5.5 pm.

[0038] The buffer layer can be made of carbon-doped GaN or unintentionally doped GaN.

[0039] The invention also relates to a high electron mobility transistor, comprising

[0040] • an intermediate substrate as described above,

[0041] • a first epitaxial layer of single-crystal GaN or single-crystal AIGaN, the first epitaxial layer and the germ layer together forming a buffer layer,

[0042] • a GaN channel arranged on the buffer layer,

[0043] • a barrier layer forming a heterojunction with the channel, adapted to generate a two-dimensional electron gas in the channel,

[0044] • a source electrode and a drain electrode electrically connected to the channel,

[0045] • a grid electrode formed on the barrier layer so that the grid electrode is physically isolated from the channel.

[0046] The barrier layer can be made of Alo.25Gao.75N.

[0047] The invention also relates to a method for manufacturing an intermediate substrate as described above, said method comprising the following steps:

[0048] • the formation of a weakening zone by the implantation of ionic species in a single-crystal GaN donor substrate,

[0049] • the bonding of said donor substrate onto a polycrystalline silicon carbide support substrate, so as to form a direct bonding interface between the support substrate and the donor substrate,

[0050] • the detachment of the donor substrate along the embrittlement zone so as to transfer a seed layer of single-crystal GaN onto the support substrate.

[0051] The gate-to-drain distance guarantees a blocking voltage of 1200 V, without having to increase the surface area of ​​the transistor.

[0052] In some embodiments, the bonding step includes the deposition of a bonding layer on the support substrate and / or on the donor substrate.

[0053] In other embodiments, the donor substrate is glued onto the support substrate without the addition of any material.

[0054] The invention also relates to a method for manufacturing a substrate for a high electron mobility transistor, comprising the fabrication of an intermediate substrate by a process as described above and the formation of a first epitaxial layer of single-crystal GaN or single-crystal AiGaN on the seed layer.

[0055] The invention also relates to a method for manufacturing a high electron mobility transistor as described above, said method comprising the following steps:

[0056] • the manufacture of an intermediate substrate by a process such as described above,

[0057] • the formation of a first epitaxial layer of single-crystal GaN or AIGaN on the germ layer,

[0058] • the formation, by epitaxy, of a transistor channel on the first epitaxial layer,

[0059] • the formation by epitaxy of a barrier layer forming a heterojunction with the canal,

[0060] • the formation of a cover layer on the barrier layer,

[0061] • the formation of a source electrode and a drain electrode electrically connected to the channel,

[0062] • the formation of a grid electrode on the cover layer.

[0063] DESCRIPTION OF THE FIGURES

[0064] Figure 1 is a cross-sectional view of a known high electron mobility transistor.

[0065] Figure 2 is a cross-sectional view of a high electron mobility transistor made from a substrate according to the invention.

[0066] Figure 3 illustrates the arrangement of the electrodes on the top face of the transistor.

[0067] Figure 4 illustrates a first embodiment of an intermediate substrate according to the invention.

[0068] Figure 5 illustrates a second embodiment of an intermediate substrate according to the invention.

[0069] Figure 6A illustrates a first step in the manufacture of an intermediate substrate according to the invention.

[0070] Figure 6B illustrates a second manufacturing step of an intermediate substrate according to the invention.

[0071] Figure 60 illustrates a third manufacturing step of an intermediate substrate according to the invention.

[0072] Figure 7 illustrates a substrate with a GaN buffer layer.

[0073] Figure 8 illustrates a substrate for a high electron mobility transistor.

[0074] Figure 9 compares the response curves of a HEMT transistor based on a known substrate and a HEMT according to the invention. DETAILED DESCRIPTION OF THE INVENTION

[0075] A HEMT transistor is shown in Figure 2. From its base to its surface, the transistor comprises a support substrate 10 made of polycrystalline silicon carbide (SiC), a buffer layer 35 made of single-crystal gallium nitride (GaN) or single-crystal gallium aluminum nitride (AIGaN), a channel 40 made of single-crystal GaN, and a barrier layer 50 made of Al₂₅Ga₇N overlying the channel and forming a heterojunction with the channel 40. A cover layer 70, typically a thin layer of gallium nitride or silicon nitride (SiN) with a thickness between one monolayer and 100 nm, can be arranged on the barrier layer. The cover layer acts as a passivation layer and also prevents oxidation of the barrier layer 50.

[0076] AIGaN refers to compounds with the stoichiometric formula Al x Cheerful. x N with 0 < x < 1. LAIo.25Gao.75N is a semiconductor alloy commonly used in electronics and optoelectronics. In this material, 25% of the cationic sites in the crystal lattice are occupied by aluminum atoms, and 75% by gallium atoms.

[0077] Source electrodes 61, drain electrode 62 and grid electrode 63 are arranged on the channel 40. The grid electrode 63 is arranged on the cover layer 70 between the source electrodes 61 and drain electrode 62. Typically, the LGD distance between the grid and the drain is greater than the LGS distance between the grid and the source.

[0078] Figure 3 illustrates the arrangement of the barrier layer 50 and the source electrode 61, drain electrode 62 and gate electrode 63 on the top face of the transistor. Each electrode typically has a rectangular or elongated shape extending along a transverse axis y perpendicular to the longitudinal axis x in a plane of the main surface of the substrate.

[0079] Due to the heterojunction, a two-dimensional electron gas forms at the interface between channel 40 and barrier layer 50. This two-dimensional electron gas serves as a conduction channel within the HEMT transistor. The buffer layer 35 helps to limit lateral and vertical leakage currents in the transistor and to better confine the two-dimensional electron gas of the heterojunction.

[0080] The transistor according to the invention has a blocking voltage greater than or equal to 1200 V, which is higher than the blocking voltage of known HEMTs. Blocking voltage is to be understood as the voltage with reference to ground. For example, a blocking voltage of 1200 V corresponds to 2 kV of floating voltage, that is, without electrical connection between the HEMT source and the circuit's ground plane.

[0081] In general, the blocking voltage of a HEMT transistor can be increased by increasing the gate-drain distance (LGD) and / or the gate length (LG), increasing the buffer layer thickness, and / or increasing the resistivity of the substrate. For a transistor of typical dimensions, the gate-drain distance (LGD) is limited to a value between 10 and 15 µm. The buffer layer thickness is limited due to the risk of breakage from thermal expansion. Therefore, the blocking voltage should be considered in relation to the gate-drain distance (LGD) and the resistivity of the substrate.

[0082] Regarding the support substrate, it should be noted that the band gap of SiC, which is greater than that of silicon, is closer to the band gap of the buffer layer material, namely GaN or AIGaN, than the band gap of silicon.

[0083] Surprisingly, in a HEMT on a SiC substrate with resistivities above a saturation value, the blocking voltage does not increase, or increases very little, with increasing resistivity. A saturation effect of the blocking voltage is thus observed as a function of substrate resistivity. This effect is unexpected and does not exist in current HEMTs based on silicon substrates, in which the blocking voltage increases continuously with increasing resistivity. Simulations in the context of the present invention have shown that the saturation value is typically between 0.36 and 3.6 G·cm. It is suggested that this effect is related to the proximity of the band gaps between the substrate and buffer materials.

[0084] Furthermore, the value of this resistivity is remarkably low for HEMTs exhibiting a high blocking voltage.

[0085] Beyond the saturation value, the impact of increasing electrical resistivity on the transistor blocking voltage is therefore negligible: an increase in substrate resistivity beyond the saturation value contributes almost nothing to increasing the transistor blocking voltage.

[0086] Table 1 shows the simulation results demonstrating the effect of electrical resistivity and the gate-to-drain LGD distance on the blocking voltage of a HEMT on a polycrystalline SiC substrate. In these simulations, substrate electrical resistivity values ​​between 0.072 G·cm and 3600 G·cm were used in combination with gate-to-drain LGD distances of 10, 15, 20, and 30 pm.

[0087] [Table 1]

[0088] A blocking voltage exceeding 1200 V can be achieved even with a gate-to-drain LGD distance of 10 pm when the substrate electrical resistivity is 36 Ω·cm or higher. For a gate-to-drain LGD distance of 15 pm, a substrate electrical resistivity of 0.26 Ω·cm is sufficient. In all configurations, saturation occurs above an electrical resistivity of approximately 3.6 V or 36 V.

[0089] In particular, for a resistivity beyond the saturation value and an LGD distance between the gate and the drain of 15 pm, a blocking voltage significantly greater than 1200V can be obtained, which is the desired blocking voltage for high-performance power electronic components.

[0090] To obtain high blocking voltages on a polycrystalline SiC substrate, it is therefore not necessary to use a substrate with very high electrical resistivity, as is the case with known HEMTs fabricated on a silicon substrate. It is sufficient to provide a resistivity greater than or equal to the saturation value, and typically close to the saturation value. Consequently, the substrate 10 has an electrical resistivity between 1 Ω·cm and 10 kΩ·cm, preferably between 1 Ω·cm and 5 kΩ·cm, more preferably between 1 Ω·cm and 1000 Ω·cm, even more preferably between 10 Ω·cm and 1000 Ω·cm, and even more preferably between 100 Ω·cm and 1000 Ω·cm, at room temperature, i.e., approximately 20°C. In the case of a polycrystalline SiC substrate, such electrical resistivity is sufficient to obtain the desired transistor blocking voltage.

[0091] The low constraints on electrical resistivity allow for the use of an easily fabricated SiC support substrate. For example, the support substrate can be made of unintentionally doped polycrystalline SiC. Using an unintentionally doped material eliminates the need for doping steps, thus reducing the cost and manufacturing constraints of the support substrate compared to a substrate doped for high resistivity, such as a vanadium-doped substrate.

[0092] Furthermore, polycrystalline SiC has a coefficient of thermal expansion close to that of GaN and AIGaN. Consequently, the risk of failure at the interface between the substrate support 10 and the buffer layer 35 is significantly reduced. It is therefore possible to deposit thick layers of GaN or AIGaN on a polycrystalline SiC substrate with a lower risk of failure than with a silicon substrate. Thus, the GaN or AIGaN layer on a polycrystalline SiC substrate can reach a thickness of up to 10 pm without increasing the risk of failure due to thermal expansion.

[0093] The use of a polycrystalline SiC support substrate therefore makes it possible simultaneously to lower the resistance of the support substrate required to obtain a transistor with a high blocking voltage, and to form relatively thick layers of GaN or AIGaN directly on the support substrate, making it possible to further increase the blocking voltage of the transistor without increasing the dimensions of the transistor.

[0094] Furthermore, the use of a polycrystalline SiC support substrate allows for a further reduction in the buffer layer thickness compared to known HEMTs. The buffer layer 35 of a HEMT according to the invention preferably has a thickness between 3.5 and 5.5 pm. Simulations have demonstrated that, in the case of a SiC support substrate, such a thickness is sufficient to guarantee a transistor blocking voltage of 1200 V for a HEMT with a gate-drain LGD between 10 pm and 15 pm.

[0095] At the same time, mechanical stresses in the substrate are minimized due to the relatively small thickness and the similarity of the thermal expansion coefficients of SiC, GaN, and AIGaN. A buffer layer thickness of between 3.5 and 5.5 pm therefore allows for a HEMT with typical dimensions and a blocking voltage of 1200V, while minimizing the risk of substrate failure due to thermal expansion.

[0096] The LGD between the gate and drain is between 10 pm and 15 pm, preferably 12 pm. For a polycrystalline SiC substrate and a buffer layer with a thickness between 3.5 and 5.5 pm, such an LGD allows for a transistor blocking voltage greater than or equal to 1200 V, while also optimizing the current density per cm². 2This results in a transistor with simultaneously optimized blocking voltage and current density, and a low risk of failure. The gate-source distance (LGS) is between 1 pm and 3 pm, preferably 2 pm. The gate length (LG) is also between 1 pm and 3 pm, preferably 2 pm.

[0097] The HEMT transistor is made from an intermediate substrate 100, shown in Figure 4. The intermediate substrate comprises the polycrystalline silicon carbide (SiC) support substrate and a single-crystal gallium nitride (GaN) seed layer 20.

[0098] The polycrystalline SiC substrate typically has a thickness of between 300 and 900 pm, preferably between 300 and 500 pm.

[0099] The seed layer 20 is a thin layer of single-crystal GaN, bonded via a direct bonding interface 15 to the upper face of the support substrate 10.

[0100] Direct bonding refers to a bonding interface with or without the addition of a material. Such direct bonding requires that both surfaces to be bonded be sufficiently smooth and free of particles or contamination. In this case, the attractive forces between the two surfaces become strong enough to cause molecular adhesion between them.

[0101] Referring to Figure 4, the seed layer can be bonded to the substrate without the addition of material, for example by vacuum bonding. Such bonding avoids the introduction of dopants that could alter the electrical properties of gallium nitride.

[0102] Alternatively, with reference to Figure 5, the direct bonding interface 15 can consist of a bonding layer 21 interposed between the support substrate 10 and the seed layer 20.

[0103] The bonding layer is made of a material whose electrical resistivity is equal to or greater than the electrical resistivity of the polycrystalline silicon carbide that constitutes the supporting substrate.

[0104] It is particularly useful to use a bonding layer with good thermal conductivity and a very thin thickness, for example less than 500 nm, especially less than 100 nm, and preferably less than 10 nm.

[0105] The maximum distance between the upper face of the support substrate and the lower face of the seed layer (i.e. the face facing the support substrate) is advantageously less than 500 nm, in particular less than 100 nm, and more advantageously less than 10 nm.

[0106] This results in thermal transparency, meaning that heat conduction from the heterojunction to the substrate is not affected by the adhesive layer during transistor operation. Silicon nitride (SiN) is particularly well-suited for use as an adhesive layer due to its bonding properties and high thermal conductivity. Another example of a suitable adhesive layer material is silicon dioxide (SiCh).

[0107] In some cases, the bonding layer material can bond with one of the materials present at the bonding interface. In other cases, the bonding layer can fracture into nodules between which the substrate and the seed layer are in direct contact.

[0108] The bonding layer can be produced using a low-pressure chemical vapor deposition (LPCVD) technique or a plasma-enhanced chemical vapor deposition (PECVD) technique.

[0109] Typically, the seed layer has a thickness between 10 nm and 1 pm. This thickness is easily transferred using the method described below and allows the growth of a uniform, single-crystal buffer layer on the substrate surface.

[0110] The level and nature of the seed layer doping are chosen according to the desired properties of the transistor to be manufactured. In some embodiments, the seed layer is made of unintentionally undoped GaN, for example, exhibiting a residual doping level of up to 5-10 15 or 10 16 at.crrr3 Embodiments in which the seed layer is made of GaN with p-type doping are also considered. An example of GaN seed layer doping is 2-10 carbon doping 19 cm -3 .

[0111] In a substrate for HEMT fabrication, a first epitaxial layer 30 of single-crystal GaN or single-crystal AiGaN is deposited on the seed layer 20 as illustrated in Figure 8. The first epitaxial layer 30 and the seed layer 20 together form the buffer layer 35 of the HEMT to be fabricated. Typically, the buffer layer 35 obtained by depositing the first epitaxial layer 30 onto the seed layer 20 has a thickness between 3.5 and 5.5 µm.

[0112] We will now describe the manufacturing steps of such a HEMT transistor.

[0113] The process begins by providing a donor substrate from which the single-crystal GaN seed layer will be formed. The donor substrate is typically a heterosubstrate, for example, a single-crystal GaN substrate on sapphire or a single-crystal GaN substrate on SiC. Such heterosubstrates are easier to fabricate than bulk substrates, especially for diameters greater than 4 inches (approximately 100 mm). Alternatively, a bulk single-crystal GaN substrate can be used.

[0114] In one particular embodiment, the donor substrate is fabricated by transferring a layer of GaN onto a temporary substrate, such as polycrystalline SiC. The transfer is performed, for example, using a SmartCut®-type process or by laser detachment. The resulting donor substrate can be used directly or after the GaN layer thickness has been increased by epitaxial growth.

[0115] Preferably, the free GaN face of the donor substrate is a [000-1] face, also called the nitrogen face because it contains nitrogen atoms in the outermost lattice of the crystal lattice. Thus, the top face of the transferred seed layer will be a gallium face (with gallium atoms in the outermost lattice) since the transfer involves an inversion of the transferred layer.

[0116] With reference to Figure 6A, as schematically represented by the arrows, an implantation of ionic species, such as hydrogen and / or helium, is implemented so as to form a weakening zone 21 in the donor substrate 200. Said weakening zone 21 defines a layer 20 of single-crystal GaN to be transferred.

[0117] Referring to Figure 6B, the weakened donor substrate 200 is bonded to a support substrate 10 via a bonding interface 15. The donor substrate can be bonded directly to the base substrate as illustrated in Figure 6B, or via a bonding layer as described above. The bonding layer can be applied to the donor substrate 200 and / or to the support substrate 10 before bonding (not shown).

[0118] With reference to Figure 6C, the donor substrate 200 is then detached along the embrittlement zone 21, which leads to the transfer of the seed layer 20 of single-crystal gallium nitride onto the support substrate 10, thus forming the intermediate substrate 100 as shown in Figure 4 or Figure 5. The remaining 201 of the donor substrate can be reused for the transfer of one or more other layers of single-crystal GaN onto other support substrates.

[0119] Subsequently, with reference to Figure 7, a first epitaxial layer is deposited on the seed layer 20. The first epitaxial layer is typically made of GaN. In some embodiments, the first epitaxial layer may be made of AIGaN. The first epitaxial layer 30 is intended to form, together with the seed layer 20, the buffer layer 35. The surface of the single-crystal seed layer 20 promotes the growth of a GaN layer 30 with a single-crystal structure. Epitaxial growth allows for the rapid and cost-effective production of a thick single-crystal GaN layer 30. After the GaN grows on the seed layer, the single-crystal structure of the seed layer 20 and the deposited layer is homogeneous and exhibits no boundary between the two layers. The germ layer 20 and the epitaxial layer 30 thus form a single homogeneous buffer layer 35 of single-crystal GaN or single-crystal AIGaN.

[0120] In a preferred embodiment, the epitaxial layer 30 is made of unintentionally doped single-crystal GaN or carbon-doped single-crystal GaN. Carbon doping increases the electrical resistivity of the buffer layer. For example, the carbon doping level can be between 10 17 and 5-10 19 atom' 3 Preferably, carbon doping is between 10 18 and 2 10 19 atom -3 It should be noted that the doping of the 30th layer of GaN deposited by epitaxy can be different from the doping of the 20th seed layer without impacting the crystal structure.

[0121] The thickness of the epitaxial layer 30 is approximately 3.5 to 5.5 pm to obtain a buffer layer 35 as described above.

[0122] After the formation of buffer layer 35, as shown in Figure 8, a second layer of single-crystal GaN is deposited epitaxially. Advantageously, this second deposition is carried out in the same epitaxial chamber to avoid additional process steps and prevent the risk of substrate contamination. The second GaN layer is intended to form channel 40 of the transistor. The second layer is unintentionally doped GaN, which may have a residual doping level of 5-10 or less. 15 or 10 16 at.crrr 3 During this second deposition, it is necessary to remove any added dopants to obtain an unintentionally doped GaN layer, possibly exhibiting low residual doping.

[0123] The thickness of the second epitaxial layer corresponds to the channel thickness and is advantageously approximately 300 nm. A barrier layer 50 is then deposited on the channel 40 as illustrated in Figure 3. Thanks to this barrier layer 50, which forms a heterojunction with the channel, a two-dimensional electron gas is generated at the interface between the barrier 50 and the channel 40, enabling electron conduction within the transistor. The barrier layer 50 extends only partially over the transistor surface and typically has an elongated rectangular shape along a longitudinal x-axis.

[0124] A cover layer (not shown) can then be deposited on the barrier layer 50. The cover layer is for example a p-doped GaN layer for a standard HEMT, or a thin layer of GaN and / or SiN for a HEMT for radio frequency applications.

[0125] In a manner known per se, the source electrodes 61 and drain electrodes 62 are deposited on the barrier layer 50 and the channel 40 or on either side of the barrier layer 50, for example by etching through a mask, and then are subjected to annealing to form an ohmic contact with said barrier layer 50. The grid electrode 63 is typically deposited on the cover layer on the upper face of the barrier layer 50.

[0126] Figure 9 illustrates the effect of the substrate material on the performance of the HEMT. Curve 9A represents the drain current as a function of the voltage applied to the gate of a HEMT based on a known silicon substrate, as illustrated in Figure 1. Curve 9B shows the response of a HEMT fabricated on a polycrystalline silicon carbide substrate, as described above, and exhibiting a resistivity of 100 G·cm. Both HEMTs have identical lateral dimensions, with a width LT of 140 mm, a gate length LG of 2 pm, a gate-to-drain distance LGD of 10 pm, and a gate-to-source distance LGS of 2 pm. The on-state resistance of the transistor according to the invention is increased by approximately 10% compared to the transistor on a silicon substrate.

[0127] Furthermore, the heat transfer efficiency of the polycrystalline SiC substrate transistor according to the invention is increased compared to the silicon substrate transistor. This allows for more efficient heat dissipation and consequently optimizes the performance of the HEMT.

[0128] The maximum on-state current performance of this transistor is 0.56 A / mm. The channel width is defined according to the desired current rating for the component. For example, a transistor width W=140 mm results in a maximum current of 78 A.

[0129] REFERENCES EP2983195 A1

Claims

DEMANDS 1. Intermediate substrate (100) for the fabrication of a high electron mobility transistor (HEMT), comprising: o a support substrate (10) of polycrystalline silicon carbide having an electrical resistivity between 1 G.cm and 10 kG.cm, and o a seed layer (20) of monocrystalline GaN, said intermediate substrate (100) comprising a direct bonding interface (15) with or without material addition between the silicon carbide of the support substrate (10) and the seed layer (20).

2. Intermediate substrate according to claim 1, wherein the polycrystalline silicon carbide support substrate has an electrical resistivity between 1 G.cm and 5 kG.cm, preferably between 1 G.cm and 1000 G.cm, more preferably between 10 G.cm and 1000 G.cm and even more preferably between 100 G.cm and 1000 G.cm.

3. Intermediate substrate according to claim 1 or claim 2, wherein the supporting substrate (10) has a thickness between 300 and 500 pm.

4. Intermediate substrate according to any one of the preceding claims, wherein the seed layer (20) has a thickness between 10 nm and 1 pm.

5. Intermediate substrate according to any one of the preceding claims, wherein the direct bonding interface (15) is a bonding layer (21) arranged between the support substrate (10) and the seed layer (20).

6. Substrate for high electron mobility transistor, comprising an intermediate substrate according to any one of the preceding claims and a first epitaxial layer (30) of single-crystal GaN or single-crystal AiGaN, the first epitaxial layer (30) and the seed layer (20) together forming a buffer layer (35).

7. Substrate according to claim 6, in which the buffer layer (35) has a thickness between 3.5 and 5.5 pm.

8. Substrate according to claim 6 or claim 7, wherein the buffer layer (35) is made of carbon-doped GaN or of unintentionally doped GaN.

9. Substrate according to any one of claims 6 to 8, comprising, on the buffer layer, a second unintentionally doped GaN epitaxial layer configured to form a channel (40) of the transistor.

10. High electron mobility transistor, comprising o a substrate according to any one of claims 6 to 8, o a GaN channel (40) arranged on the buffer layer (35), o a barrier layer (50) forming a heterojunction with the channel, adapted to generate a two-dimensional electron gas in the channel, o a source electrode (61) and a drain electrode (62) electrically connected to the channel (40), o a gate electrode (63) formed on the barrier layer (50) such that the gate electrode (63) is physically isolated from the channel (40).

11. Transistor according to claim 10, wherein the barrier layer (50) is made of Alo.25Gao.75N.

12. A method for manufacturing an intermediate substrate (100) according to any one of claims 1 to 5, said method comprising the following steps: o the formation of a embrittlement zone (21) by implanting ionic species in a donor substrate (200) of monocrystalline GaN, o the bonding of said donor substrate (200) onto a support substrate (10) of polycrystalline silicon carbide, so as to form a direct bonding interface (15) between the support substrate (10) and the donor substrate (200), o the detachment of the donor substrate (200) along the embrittlement zone (21) so as to transfer a seed layer (20) of monocrystalline GaN onto the support substrate (10).

13. Method of manufacturing an intermediate substrate (100) according to claim 12, wherein the bonding step comprises the deposition of a bonding layer (21) on the support substrate (10) and / or on the donor substrate (200).

14. Method of manufacturing an intermediate substrate (100) according to claim 12, wherein the donor substrate is bonded to the support substrate without the addition of material.

15. A method for manufacturing a substrate for a high electron mobility transistor, comprising manufacturing an intermediate substrate (100) by the method according to one of the claims 12 to 14 and the formation of a first epitaxial layer (30) of single-crystal GaN or single-crystal AIGaN on the seed layer (20).

16. A method for manufacturing a high electron mobility transistor according to claim 10 or claim 11, said method comprising the following steps: o manufacturing an intermediate substrate (100) by a method according to any one of claims 12 to 14, o forming a first epitaxial layer (30) of single-crystal GaN or single-crystal AIGaN on the seed layer (20), o forming by epitaxy a channel (40) of the transistor on the first epitaxial layer (30), o forming by epitaxy a barrier layer (50) forming a heterojunction with the channel (40), o forming a cover layer on the barrier layer (50), o forming a source electrode (61) and a drain electrode (62) electrically connected to the channel (40), o forming a gate electrode (63) on the cover layer.

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