Light-emitting element control circuit and light-emitting element drive system

Abstract

This light-emitting element control circuit comprises: a horizontal synchronization signal generation circuit configured to generate a horizontal synchronization signal; a first terminal configured to supply the horizontal synchronization signal to the outside of the light-emitting element control circuit; and a control unit configured to control one-dimensional drive of matrix drive for a plurality of light-emitting elements on the basis of the horizontal synchronization signal and a vertical synchronization signal. The vertical synchronization signal is supplied from the outside of the light-emitting element control circuit or is generated inside the light-emitting element control circuit.

Description

Light-emitting element control circuit and light-emitting element driving system

[0001] The present disclosure relates to a light-emitting element control circuit and a light-emitting element driving system.

[0002] In a liquid crystal display device, a backlight that irradiates light on the back surface of a liquid crystal display panel is often used. In recent years, in order to support HDR (High Dynamic Range), a backlight capable of local dimming has been demanded.

[0003] Local dimming is realized, for example, by matrix driving a plurality of light-emitting elements (see, for example, Patent Document 1).

[0004] Japanese Patent Application Laid-Open No. 2020-136249 (FIG. 11)

[0005] [Summary] In a backlight that matrix drives a plurality of light-emitting elements, it is desired to achieve both elimination of variations in horizontal synchronization signals between a plurality of circuits and facilitation of noise countermeasures.

[0006] The light-emitting element control circuit disclosed in this specification includes a horizontal synchronization signal generation circuit configured to generate a horizontal synchronization signal, a first terminal configured to supply the horizontal synchronization signal to the outside of the light-emitting element control circuit, and a control unit configured to control one-dimensional driving in matrix driving for a plurality of light-emitting elements based on the horizontal synchronization signal and a vertical synchronization signal. The vertical synchronization signal is supplied from the outside of the light-emitting element control circuit or generated inside the light-emitting element control circuit.

[0007] The light-emitting element driving system disclosed in this specification includes the light-emitting element control circuit having the above configuration and a light-emitting element driving circuit configured to receive the horizontal synchronization signal from the light-emitting element control circuit.

[0008] Figure 1 shows an LED (Light Emitting Diode) driving system according to the first comparative example. Figure 2 shows an LED driving system according to the second comparative example. Figure 3 shows an example of a signal waveform used in the LED driving system according to the second comparative example. Figure 4 shows an example of the brightness distribution of multiple LEDs connected to the LED driving system according to the second comparative example. Figure 5 shows an LED driving system according to the first embodiment. Figure 6 shows a schematic configuration of the LED driver. Figure 7 shows an LED driving system according to the second embodiment. Figure 8A shows a schematic configuration of the LED driver. Figure 8B shows a schematic configuration of the LED driver. Figure 9 shows an LED driving system according to the third embodiment. Figure 10 shows an LED driving system according to the fourth embodiment. Figure 11 shows an LED driving system according to the fifth embodiment. Figure 12 shows an LED driving system according to the sixth embodiment.

[0009] [Detailed Description] <First Comparative Example> Figure 1 shows an LED driving system according to the first comparative example. The LED driving system SYS1 includes LED drivers D1 to D3. Each of the LED drivers D1 to D3 drives multiple LEDs in a matrix based on the vertical synchronization signal VSYNC and the horizontal synchronization signal HSYNC supplied from the local dimming control device CNT1. Furthermore, each of the LED drivers D1 to D3 adjusts the brightness of each of the multiple LEDs according to the communication signal S1 supplied from the local dimming control device CNT1. For example, an SPI (Serial Peripheral Interface) signal is used as the communication signal S1.

[0010] The local dimming control device CNT1 and the LED driving system SYS1 are mounted on separate circuit boards. Therefore, inter-board wiring is required to transmit the horizontal synchronization signal HSYNC, which is a high-frequency clock signal of several MHz, creating a problem where noise countermeasures become more difficult.

[0011] <Second Comparative Example> Figure 2 shows an LED driving system according to the second comparative example. The LED driving system SYS2 includes LED drivers D4 to D6.

[0012] The LED driver D4 includes an oscillator OSC4 that generates a horizontal synchronization signal HSYNC. The LED driver D4 drives a matrix of multiple LEDs connected to itself based on the vertical synchronization signal VSYNC supplied from the local dimming control device CNT2 and the horizontal synchronization signal HSYNC output from the oscillator OSC4.

[0013] The LED driver D5 includes an oscillator OSC5 that generates a horizontal synchronization signal HSYNC. The LED driver D5 drives a plurality of LEDs connected to it in a matrix based on the vertical synchronization signal VSYNC supplied from the local dimming control device CNT2 and the horizontal synchronization signal HSYNC output from the oscillator OSC5.

[0014] The LED driver D6 includes an oscillator OSC6 that generates a horizontal synchronization signal HSYNC. The LED driver D6 matrix drives multiple LEDs connected to it based on the vertical synchronization signal VSYNC supplied from the local dimming control device CNT2 and the horizontal synchronization signal HSYNC output from the oscillator OSC6.

[0015] Furthermore, each of the LED drivers D4 to D6 adjusts the brightness of each of the multiple LEDs according to the communication signal S1 supplied from the local dimming control device CNT2. For example, an SPI signal can be used as the communication signal S1.

[0016] When the LED drive system SYS2 is used, inter-board wiring for transmitting the horizontal synchronization signal HSYNC becomes unnecessary, simplifying noise countermeasures.

[0017] However, when the LED drive system SYS2 is used, variations in the horizontal synchronization signal HSYNC between LED drivers D4 to D6 may cause variations in brightness.

[0018] In the following, LED drivers D4 to D6 will each drive 64 LEDs (8 rows x 8 columns) in a matrix.

[0019] Each of the LED drivers D4 to D6 updates the brightness data for each frame, which is reflected in the matrix drive, at the rising edge timing of the vertical synchronization signal VSYNC.

[0020] The LED driver D4 generates a matrix trigger signal MT1 based on the vertical synchronization signal VSYNC supplied from the local dimming control device CNT2 and the horizontal synchronization signal HSYNC output from the oscillator OSC4.

[0021] The LED driver D5 generates a matrix trigger signal MT2 based on the vertical sync signal VSYNC supplied from the local dimming control device CNT2 and the horizontal sync signal HSYNC output from the oscillator OSC5.

[0022] The LED driver D6 generates a matrix trigger signal MT3 based on the vertical synchronization signal VSYNC supplied from the local dimming control device CNT2 and the horizontal synchronization signal HSYNC output from the oscillator OSC6.

[0023] Figure 3 shows example waveforms of the vertical synchronization signal VSYNC and matrix trigger signals MT1 to MT3. In the example shown in Figure 3, the frequency of the horizontal synchronization signal HSYNC output from oscillator OSC4 is the ideal frequency, the frequency of the horizontal synchronization signal HSYNC output from oscillator OSC5 is higher than the ideal frequency, and the frequency of the horizontal synchronization signal HSYNC output from oscillator OSC6 is lower than the ideal frequency.

[0024] Each of the matrix trigger signals MT1 to MT3 has a pulse for the first period corresponding to the first column, synchronized with the pulse of the vertical synchronization signal VSYNC. For each of the matrix trigger signals MT1 to MT3, when 32768 periods of the horizontal synchronization signal HSYNC have elapsed from the rising edge timing of the pulse for the k period corresponding to the k column, the pulse for the (k+1) period corresponding to the (k+1) column rises. Here, k is a natural number greater than or equal to 1. In Figure 3, k=7, but there is no particular upper limit set for k. The period from the rising edge timing of the pulse for the k period corresponding to the k column to the rising edge timing of the pulse for the (k+1) period corresponding to the (k+1) column is the maximum drive (lighting) period of the LED in the k column. The period from the rising edge timing of the (k+1)th period pulse corresponding to the 8th column to the timing when 32768 periods of the horizontal synchronization signal HSYNC have elapsed or the rising edge timing of the vertical synchronization signal VSYNC, whichever comes first, is the maximum drive (illumination) period of the last column's LED.

[0025] In this comparative example, the period from the rising edge of one pulse to the rising edge of the next pulse in each of the matrix trigger signals MT1 to MT3 is set to 32768 cycles of the horizontal synchronization signal HSYNC, but this setting is for a dimming resolution of 15 bits. If a dimming resolution of X bits is required, the period from the rising edge of one pulse to the rising edge of the next pulse in each of the matrix trigger signals MT1 to MT3 should be set to 2 cycles of the horizontal synchronization signal HSYNC. Ｘ It is set to a period. For example, if a 16-bit dimming resolution is required, the period from the rising edge of one pulse to the rising edge of the next pulse in each of the matrix trigger signals MT1 to MT3 is set to 65536 (=2) of the horizontal synchronization signal HSYNC. １６ The period is set to ).

[0026] Furthermore, since the ON / OFF switching of MOSFETs (metal-oxide-semiconductor field-effect transistors) is required to perform matrix driving, in addition to the period of the dimming resolution mentioned above, the period for MOSFET switching time may also be counted. If the MOSFET switching period is Y, then the horizontal synchronization signal HSYNC (2 Ｘ The following period count is required: (+Y) where Y is a natural number greater than or equal to 1. For example, if X = 15 and Y = 32, then the 32,800 period count of the horizontal synchronization signal HSYNC is required.

[0027] For each of the matrix trigger signals MT1 to MT3, the period from the rising edge of one pulse to the rising edge of the next pulse corresponds to the duration the LED is lit. For example, if there are eight rows in the matrix drive, eight matrix trigger signals MT1, eight matrix trigger signals MT2, and eight matrix trigger signals MT3 are required, each corresponding to a row.

[0028] When local dimming control is performed to adjust all LEDs to a predetermined brightness (brightness 100), as shown in Figure 4, the LEDs connected to LED driver D4 will have the ideal brightness, the LEDs connected to LED driver D5 will be dimmer than ideal, the LEDs connected to LED driver D5 will be brighter than ideal in rows 1 to 7, and dimmer than ideal in row 8.

[0029] <First Embodiment> Figure 5 shows an LED driving system according to the first embodiment. The LED driving system SYS3 includes LED drivers D7 to D9.

[0030] The LED driving system SYS3 is used, for example, as part of the backlight of a liquid crystal display device that includes a SoC (System on Chip) 1, a liquid crystal display panel 2, and a local dimming control device CNT2.

[0031] The System on Chip (SoC) 1 outputs a vertical synchronization signal VSYNC and video signals such as LVDS (Low Voltage Differential Signal) to the local dimming control device CNT2. The local dimming control device CNT2 outputs the video signals to the liquid crystal display panel 2. The local dimming control device CNT2 outputs the vertical synchronization signal VSYNC and communication signals such as SPI signals S1 to LED drivers D7 to D9, respectively.

[0032] The LED driver D7 comprises terminals T71 to T73, an oscillator OSC7, and a register R7.

[0033] Terminal T71 is configured to receive the vertical synchronization signal VSYNC. Terminal T72 is configured to receive the communication signal S1. Terminal T73 is connected to the output terminal of the oscillator OSC7 inside the LED driver D7.

[0034] The oscillator OSC7 is configured to generate the horizontal synchronization signal HSYNC. However, in the sub-configurations described later, the oscillator OSC7 will stop operating.

[0035] Register R7 stores the register values ​​V0, V1, and V2.

[0036] If register value V0 is "0", it is the main setting; if register value V0 is "1", it is the sub setting. In the sub setting, both the horizontal sync signal HSYNC and the vertical sync signal VSYNC must be supplied externally. Register R7 stores "0" as the register value V0.

[0037] Register values ​​V1 and V2 are only valid when they are the main settings.

[0038] If register value V1 is "0", the system is set to use the internally generated horizontal synchronization signal HSYNC; if register value V1 is "1", the system is set to use the externally supplied horizontal synchronization signal HSYNC. Register R7 stores "0" as the register value V1.

[0039] When the register value V2 is "0", the internally generated horizontal synchronization signal HSYNC is set to be output externally. When the register value V2 is "1", the internally generated horizontal synchronization signal HSYNC is set not to be output externally. The register R7 stores "0" as the register value V2. Therefore, the terminal T73 is configured to supply the horizontal synchronization signal HSYNC externally.

[0040] The LED driver D8 includes terminals T81 to T83, an oscillator OSC8, and a register R8.

[0041] The terminal T81 is configured to receive the vertical synchronization signal VSYNC. The terminal T82 is configured to receive the communication signal S1. The terminal T83 is connected to the output terminal of the oscillator OSC8 inside the LED driver D8.

[0042] The oscillator OSC8 is configured to generate the horizontal synchronization signal HSYNC. However, in the case of the aforementioned sub - settings, the oscillator OSC8 stops operating.

[0043] The register R8 stores the register values V0, V1, and V2. The definitions of the register values V0, V1, and V2 are the same as those of the LED driver D7.

[0044] The register R8 stores "1" as the register value V0. Therefore, the terminal T83 is configured to receive the horizontal synchronization signal HSYNC.

[0045] The LED driver D9 includes terminals T91 to T93, an oscillator OSC9, and a register R9.

[0046] The terminal T91 is configured to receive the vertical synchronization signal VSYNC. The terminal T92 is configured to receive the communication signal S1. The terminal T93 is connected to the output terminal of the oscillator OSC9 inside the LED driver D9.

[0047] The oscillator OSC9 is configured to generate the horizontal synchronization signal HSYNC. However, in the case of the aforementioned sub - settings, the oscillator OSC9 stops operating.

[0048] Register R9 stores the register values ​​V0, V1, and V2. The definitions of the register values ​​V0, V1, and V2 are the same as those for LED drivers D7 and D8.

[0049] Register R9 stores the value "1" as register value V0. Therefore, terminal T93 becomes a terminal configured to receive the horizontal synchronization signal HSYNC.

[0050] LED drivers D7 to D9 have the same configuration, and their operating modes can be changed by changing the settings of register values ​​V0, V1, and V2. Alternatively, each of the LED drivers D7 to D9 may be fixed to a single operating mode. For example, the oscillators may be removed from LED drivers D8 and D9, and the operating modes of LED drivers D8 and D9 may be fixed to the operating mode corresponding to the sub-setting.

[0051] LED drivers D7 to D9 are mounted on the same circuit board 3.

[0052] Figure 6 shows a schematic configuration of the LED driver D7. The LED driver D7 comprises a matrix trigger signal generation circuit 70, a gate controller 71, and a current driver 72.

[0053] The matrix trigger signal generation circuit 70 generates matrix trigger signals in the same manner as the LED drivers D3 to D6 described above. More specifically, the matrix trigger signal generation circuit 70 generates matrix trigger signals MT_R1 to MT_R8 corresponding to rows 1 to 8. The gate controller 71 generates and outputs gate signals G1 to G8 corresponding to columns 1 to 8, whose LOW level periods are sequentially switched based on the matrix trigger signal MT_R1 corresponding to row 1. In other words, the gate controller 71 is a control unit configured to control the column drive of the 64 (8 rows x 8 columns) LEDs based on the horizontal synchronization signal HSYNC and the vertical synchronization signal. Note that the gate controller 71 may be supplied with any of the matrix trigger signals MT_R2 to MT_R8 corresponding to rows 2 to 8, respectively, instead of the matrix trigger signal MT_R1 corresponding to row 1. Each of the matrix trigger signals MT_R1 to MT_R8 is a signal that has eight pulses (corresponding to eight columns) in one period of the vertical synchronization signal VSYNC.

[0054] The current driver 72 generates pull currents I1 to I8 in response to the pulses of matrix trigger signals MT_R1 to MT_R8, which correspond to each of the 1st to 8th rows.

[0055] The LED drive system SYS3 can eliminate variations in the horizontal synchronization signal HSYNC between LED drivers D7 to D9, thus suppressing variations in brightness when, for example, local dimming control is performed to adjust all LEDs to a predetermined brightness.

[0056] Since the LED drive system SYS3 has LED drivers D7 to D9 mounted on the same board 3, inter-board wiring for transmitting the horizontal synchronization signal HSYNC is unnecessary, making noise countermeasures easier.

[0057] <Second Embodiment> Figure 7 shows an LED driving system according to the second embodiment. In Figure 7, the same parts as in Figure 5 are denoted by the same reference numerals, and detailed descriptions are omitted.

[0058] The LED driving system SYS4 comprises a gate controller GC1 and LED drivers D11 and D12.

[0059] The gate controller GC1 comprises terminals T101 to T103, an oscillator OSC10, and a register R10.

[0060] Terminal T101 is configured to receive the vertical synchronization signal VSYNC. Terminal T102 is configured to receive the communication signal S1. Terminal T103 is connected to the output terminal of the oscillator OSC10 inside the gate controller GC1.

[0061] The oscillator OSC10 is configured to generate the horizontal synchronization signal HSYNC. However, the oscillator OSC10 stops operating if both register values ​​V1 and V2, which will be described later, are "1".

[0062] Register R10 stores the register values ​​V1 and V2.

[0063] If register value V1 is "0", the internally generated horizontal synchronization signal HSYNC is used; if register value V1 is "1", the externally supplied horizontal synchronization signal HSYNC is used. Register R10 stores "0" as the register value V1.

[0064] When register value V2 is "0", the internally generated horizontal synchronization signal HSYNC is output externally. When register value V2 is "1", the internally generated horizontal synchronization signal HSYNC is not output externally. Register R10 stores "0" as register value V2. Therefore, terminal T103 is configured to supply the horizontal synchronization signal HSYNC externally.

[0065] The LED driver D11 includes terminals T111 to T113.

[0066] Terminal T111 is configured to receive the vertical synchronization signal VSYNC. Terminal T112 is configured to receive the communication signal S1. Terminal T113 is configured to receive the horizontal synchronization signal HSYNC.

[0067] The LED driver D12 includes terminals T121 to T123.

[0068] Terminal T121 is configured to receive the vertical synchronization signal VSYNC. Terminal T122 is configured to receive the communication signal S1. Terminal T123 is configured to receive the horizontal synchronization signal HSYNC.

[0069] LED driver D12 has the same configuration as LED driver D11.

[0070] The gate controller GC1 can change its operating mode by changing the settings of register values ​​V1 and V2. Alternatively, the gate controller GC1 may be fixed to a single operating mode.

[0071] The gate controller GC1 and the LED drivers D11 and D12 are mounted on the same circuit board 4.

[0072] Figure 8A shows the schematic configuration of LED drivers D11 and D12. LED driver D11 includes a current driver 111. LED driver D12 includes a current driver 121.

[0073] The gate controller GC1 generates a matrix trigger signal, similar to the LED drivers D3 to D6 described above, and generates and outputs gate signals G1 to G16 corresponding to the 1st to 16th columns, whose LOW level periods are sequentially switched based on the matrix trigger signal. In other words, the gate controller GC1 is a control unit configured to control the column drive of the matrix drive for 128 LEDs (8 rows x 16 columns) based on the horizontal synchronization signal HSYNC and the vertical synchronization signal. Note that, as shown in Figure 8B, a MOSFET may be used in common as an external component for LED drivers D11 and D12. In this case, the gate controller GC1 only needs to generate and output gate signals G1 to G8.

[0074] Current drivers 111 and 121 each generate pull currents I1 to I8 in accordance with the pulses of the matrix trigger signal corresponding to rows 1 to 8, respectively.

[0075] The LED drive system SYS4 can eliminate variations in the horizontal synchronization signal HSYNC between the gate controller GC1, LED driver D11, and LED driver D12. Therefore, it can suppress variations in brightness when local dimming control is performed to adjust all LEDs to a predetermined brightness.

[0076] Since the LED drive system SYS4 has a configuration in which the gate controller GC1, LED driver D11, and LED driver D12 are mounted on the same board 4, inter-board wiring for transmitting the horizontal synchronization signal HSYNC is unnecessary, making noise countermeasures easier.

[0077] <Third Embodiment> Figure 9 shows an LED driving system according to the third embodiment. LED driving system SYS3' is a modified example of LED driving system SYS3 shown in Figure 5.

[0078] The LED drive system SYS3' includes LED drivers D7' to D9'.

[0079] LED driver D7' differs from LED driver D7 shown in Figure 5 in that it includes counter C7 and terminal T74.

[0080] Terminal T74 is connected to the output terminal of counter C7 inside the LED driver D7'.

[0081] Counter C7 is configured to generate a vertical synchronization signal VSYNC based on the horizontal synchronization signal HSYNC output from oscillator OSC7. For example, counter C7 is configured to generate the vertical synchronization signal VSYNC by generating a pulse every 262144 (= 32768 × 8) cycles of the horizontal synchronization signal HSYNC. However, in sub-settings, counter C7 stops operating.

[0082] Register R7 stores register values ​​V3 and V4 in addition to register values ​​V0, V1, and V2.

[0083] Register values ​​V3 and V4, like register values ​​V1 and V2, are only effective when they are the main settings.

[0084] If register value V3 is "0", the system is set to use the internally generated vertical synchronization signal VSYNC; if register value V3 is "1", the system is set to use the externally supplied vertical synchronization signal VSYNC. Register R7 stores "0" as the register value V3.

[0085] When register value V4 is "0", the internally generated vertical synchronization signal VSYNC is output externally. When register value V4 is "1", the internally generated vertical synchronization signal VSYNC is not output externally. Register R7 stores "0" as register value V4. Therefore, terminal T74 is configured to supply the vertical signal VSYNC externally.

[0086] LED drivers D7' to D9' have the same configuration, and their operating modes can be changed by changing the settings of register values ​​V0 to V4. Alternatively, each of the LED drivers D7' to D9' may be fixed to a single operating mode. For example, the oscillator and counter may be removed from LED drivers D8' and D9', and the operating modes of LED drivers D8' and D9' may be fixed to the operating mode corresponding to the sub-setting.

[0087] LED drivers D7' to D9' are mounted on the same circuit board 3.

[0088] Since the LED drive system SYS3' generates the horizontal synchronization signal HSYNC and the vertical synchronization signal VSYNC from the same oscillation source, it is possible to establish an ideal relationship such as the vertical synchronization signal VSYNC and the matrix trigger signal MT1 shown in Figure 3.

[0089] <Fourth Embodiment> Figure 10 shows an LED driving system according to the fourth embodiment. LED driving system SYS4' is a modified example of LED driving system SYS4 shown in Figure 7.

[0090] The LED driving system SYS4' comprises a gate controller GC1' and LED drivers 11 and 12.

[0091] Gate controller GC1' differs from gate controller GC1 shown in Figure 7 in that it includes counter C10 and terminal T104.

[0092] Terminal T104 is connected to the output terminal of counter C10 inside the gate controller GC1'.

[0093] The counter C10 is configured to generate a vertical synchronization signal VSYNC based on the horizontal synchronization signal HSYNC output from the oscillator OSC10. For example, if the dimming resolution is 15 bits, the counter C10 is configured to generate a pulse every 262144 (= 32768 × 8) periods of the horizontal synchronization signal HSYNC. In addition to the dimming resolution period mentioned above, a period for MOSFET switching time may also be counted. In other words, the number of counts at which the counter C10 generates a pulse will change from the 262144 periods exemplified above when the dimming resolution changes or when MOSFET switching time is taken into consideration. However, if both register values ​​V3 and V4, which will be described later, are "1", the counter C10 will stop operating.

[0094] Register R10 stores register values ​​V3 and V4 in addition to register values ​​V0, V1, and V2.

[0095] If register value V3 is "0", the system is set to use the internally generated vertical synchronization signal VSYNC, and if register value V3 is "1", the system is set to use the externally supplied vertical synchronization signal VSYNC. Register R10 stores "0" as the register value V3.

[0096] When register value V4 is "0", the internally generated vertical synchronization signal VSYNC is output externally. When register value V4 is "1", the internally generated vertical synchronization signal VSYNC is not output externally. Register R10 stores "0" as register value V4. Therefore, terminal T104 is configured to supply the vertical signal VSYNC externally.

[0097] The gate controller GC1' can change its operating mode by changing the settings of register values ​​V1 to V4. Alternatively, the gate controller GC1' may be fixed to a single operating mode.

[0098] The gate controller GC1' and the LED drivers D11 and D12 are mounted on the same circuit board 4.

[0099] Since the LED drive system SYS4' generates the horizontal synchronization signal HSYNC and the vertical synchronization signal VSYNC from the same oscillation source, it is possible to establish an ideal relationship such as the vertical synchronization signal VSYNC and the matrix trigger signal MT1 shown in Figure 3.

[0100] <Fifth Embodiment> Figure 11 shows an LED driving system according to the fifth embodiment. The LED driving system SYS5 is another modification of the LED driving system SYS4 shown in Figure 7.

[0101] The LED drive system SYS5 incorporates a gate controller inside the local dimming control device CNT3. The local dimming control device CNT3, LED driver D11, and LED driver D12 are mounted on the same circuit board 4.

[0102] In the fifth embodiment, the gate controller is incorporated inside the local dimming control device, but it may also be incorporated inside a component other than the local dimming control device.

[0103] <Sixth Embodiment> Figure 12 shows an LED driving system according to the sixth embodiment. LED driving system SYS5' is a modified example of LED driving system SYS4' shown in Figure 10.

[0104] The LED drive system SYS5' incorporates a gate controller inside the local dimming control device CNT3'. The local dimming control device CNT3', LED driver D11, and LED driver D12 are mounted on the same circuit board 4.

[0105] In the sixth embodiment, the gate controller is incorporated inside the local dimming control device, but it may also be incorporated inside a component other than the local dimming control device.

[0106] <Other> The embodiments described above should be considered in all respects to be illustrative and not restrictive, and the technical scope of this disclosure is indicated by the claims rather than by the description of the embodiments, and should be understood to include all modifications that fall within the meaning and scope of equivalence to the claims.

[0107] For example, although an LED was used as the light-emitting element in the above configuration, other light-emitting elements may also be used.

[0108] For example, the specific number of LED drivers, the specific number of rows in the matrix drive, the specific number of columns in the matrix drive, etc., in the above embodiment are merely examples and are not limited to these specific numbers.

[0109] For example, in the LED driving system SYS3 shown in Figure 5, the sub-configured LED driver D8 may be equipped with a determination unit configured to determine whether or not the horizontal synchronization signal HSYNC is being properly supplied to terminal T83 from the main-configured LED driver D7. If the determination unit determines that the horizontal synchronization signal HSYNC is not being properly supplied to terminal T83, the LED driver D8 may rewrite the contents of register R8 to become the main-configured LED driver and output a command to instruct the LED driver D7 to change from the main-configured LED driver to the sub-configured LED driver. In this way, if the LED driver D7 is unable to output the horizontal synchronization signal HSYNC, the oscillator OSC8 generates the horizontal synchronization signal HSYNC, and the horizontal synchronization signal HSYNC generated by the oscillator OSC8 is supplied to the LED drivers D7 and D9, ensuring functional safety.

[0110] <Note> A note is provided for this disclosure in which specific configuration examples are shown in the embodiments described above.

[0111] The light-emitting element control circuit (D7, GC1, D7', GC1', CNT3, CNT3') of the present disclosure comprises a horizontal synchronization signal generation circuit (OSC7, OSC10) configured to generate a horizontal synchronization signal, a first terminal (T73, T103) configured to supply the horizontal synchronization signal to the outside of the light-emitting element control circuit, and a control unit (71) configured to control one-dimensional drive of a matrix drive for a plurality of light-emitting elements based on the horizontal synchronization signal and the vertical synchronization signal, wherein the vertical synchronization signal is supplied from the outside of the light-emitting element control circuit or generated inside the light-emitting element control circuit (first configuration).

[0112] The light-emitting element control circuit of the first configuration described above contributes to eliminating variations in horizontal synchronization signals between multiple circuits and facilitating noise countermeasures.

[0113] In the first configuration of the light-emitting element control circuit described above, there may also be a configuration (second configuration) that includes a current generation circuit (72) configured to generate a current for driving the plurality of light-emitting elements.

[0114] In the light-emitting element control circuit of the first or second configuration described above, a second terminal (T71, T101) is provided which is configured to receive the vertical synchronization signal from outside the light-emitting element control circuit, and the vertical synchronization signal may be supplied from outside the light-emitting element control circuit (third configuration).

[0115] In the first or second configuration of the light-emitting element control circuit described above, a vertical synchronization signal generation circuit (C7, C10) configured to generate the vertical synchronization signal based on the horizontal synchronization signal, and a third terminal (T74, T104) configured to supply the vertical synchronization signal to the outside of the light-emitting element control circuit, wherein the vertical synchronization signal is generated inside the light-emitting element control circuit (fourth configuration).

[0116] The light-emitting element driving system of the present disclosure (SYS3, SYS4, SYS3', SYS4', SYS5, SYS5') comprises a light-emitting element control circuit having any of the first to fourth configurations described above, and a light-emitting element driving circuit (D8, D9, D11, D12) configured to receive the horizontal synchronization signal from the light-emitting element control circuit (fifth configuration).

[0117] In the fifth configuration of the light-emitting element driving system described above, the light-emitting element control circuit and the light-emitting element driving circuit may be mounted on the same substrate (3, 4) (sixth configuration).

[0118] In the fifth or sixth configuration of the light-emitting element driving system described above, the light-emitting element driving circuit may include a light-emitting element driving circuit equipped with a backup horizontal signal synchronization circuit (OSC8, OSC9) configured to generate a backup horizontal synchronization signal, wherein when the light-emitting element control circuit is unable to output the horizontal synchronization signal, the backup horizontal signal synchronization circuit generates the backup horizontal synchronization signal, and the backup horizontal synchronization signal is supplied to the light-emitting element driving circuit (seventh configuration).

[0119] 1…SoC, 2…Liquid crystal display panel, 3, 4…Circuit board, 70…Matrix trigger signal generation circuit, 71, GC1…Gate controller, 72, 111, 121…Current driver, C7~C10…Counter, CNT1, CNT2, CNT3, CNT3'…Local dimming control device, D1~D9, D11, D12, D7'~D9'…LED driver, OSC3~OSC10…Oscillator, R7~R10…Register, SYS1~SYS5, SYS3'~SYS5'…LED driving system, T71~T74, T81~T84, T91~T94, T101~T104, T111~T114, T121~T124…Terminal

Claims

1. A light-emitting element control circuit comprising: a horizontal synchronization signal generation circuit configured to generate a horizontal synchronization signal; a first terminal configured to supply the horizontal synchronization signal to the outside of the light-emitting element control circuit; and a control unit configured to control one-dimensional drive of a matrix drive for a plurality of light-emitting elements based on the horizontal synchronization signal and the vertical synchronization signal, wherein the vertical synchronization signal is supplied from the outside of the light-emitting element control circuit or generated inside the light-emitting element control circuit.

2. The light-emitting element control circuit according to claim 1, further comprising a current generation circuit configured to generate a current for driving the plurality of light-emitting elements.

3. The light-emitting element control circuit according to claim 1 or claim 2, further comprising a second terminal configured to receive the vertical synchronization signal from outside the light-emitting element control circuit, wherein the vertical synchronization signal is supplied from outside the light-emitting element control circuit.

4. The light-emitting element control circuit according to claim 1 or 2, comprising: a vertical synchronization signal generation circuit configured to generate the vertical synchronization signal based on the horizontal synchronization signal; and a third terminal configured to supply the vertical synchronization signal to the outside of the light-emitting element control circuit, wherein the vertical synchronization signal is generated inside the light-emitting element control circuit.

5. A light-emitting element driving system comprising: a light-emitting element control circuit according to any one of claims 1 to 4; and a light-emitting element driving circuit configured to receive the horizontal synchronization signal from the light-emitting element control circuit.

6. The light-emitting element driving system according to claim 5, wherein the light-emitting element control circuit and the light-emitting element driving circuit are mounted on the same substrate.

7. The light-emitting element driving circuit includes a light-emitting element driving circuit equipped with a backup horizontal signal synchronization circuit configured to generate a backup horizontal synchronization signal, wherein when the light-emitting element control circuit is unable to output the horizontal synchronization signal, the backup horizontal signal synchronization circuit generates the backup horizontal synchronization signal and the backup horizontal synchronization signal is supplied to the light-emitting element driving circuit, the light-emitting element driving system according to claim 5 or 6.

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