Composite driving circuit, display panel and display device

Abstract

A composite driving circuit, comprising a pixel driving circuit (11) and a sensing driving circuit (12). The pixel driving circuit (11) is connected to a scanning end (GATE), a data line (DL), a plurality of reset control ends (SW-RESET), and at least one light-emitting element (EL). The sensing driving circuit (12) is connected to a sensing reset control end (SW-RST), a sensing output control end (SENSE), a sensing read line (SL), and at least one photoelectric sensing element (OPD). The composite driving circuit satisfies at least one of the following: the sensing output control end (SENSE) is configured to receive the same signal as the scanning end (GATE); and the sensing reset control end (SW-RST) is configured to receive the same signal as one of the plurality of reset control ends (SW-RESET).

Description

Composite driving circuit, display panel and display device TECHNICAL FIELD

[0001] The present document relates to, but is not limited to, the technical field of display, and in particular to a composite driving circuit, a display panel and a display device. BACKGROUND

[0002] Organic light emitting diode (OLED) and quantum dot light emitting diode (QLED) are active light emitting display devices, which have the advantages of self-emission, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, bendability and low cost.

[0003] SUMMARY

[0004] The following is a summary of the subject matter of the detailed description herein. This summary is not intended to limit the scope of the claims.

[0005] The embodiments of the present disclosure provide a composite driving circuit, a display panel and a display device.

[0006] In one aspect, the embodiments of the present disclosure provide a composite driving circuit, comprising: a pixel driving circuit and a sensing driving circuit. The pixel driving circuit comprises a plurality of pixel nodes; the pixel driving circuit is connected with a scan end, a data line, a plurality of reset control ends and at least one light emitting element, and is configured to reset at least one pixel node in the plurality of pixel nodes under the control of at least one reset control end in the plurality of reset control ends; write a data signal provided by the data line into one pixel node as a data writing node under the control of the scan end; and generate a driving signal for driving the at least one light emitting element to emit light according to the data signal. The sensing driving circuit comprises a first sensing node and a second sensing node, and the sensing driving circuit is connected with a sensing reset control end, a sensing output control end, a sensing reading line and at least one photoelectric sensing element, and is configured to reset the first sensing node under the control of the sensing reset control end; generate a sensing signal according to a photoelectric conversion signal written into the first sensing node by the at least one photoelectric sensing element; and provide the sensing signal written into the second sensing node to the sensing reading line under the control of the sensing output control end. The composite driving circuit satisfies at least one of the following: the sensing output control end is configured to receive the same signal as the scan end; and the sensing reset control end is configured to receive the same signal as one of the plurality of reset control ends.

[0007] In some example embodiments, the plurality of pixel nodes comprises a first pixel node, a second pixel node and a third pixel node. The pixel driving circuit comprises a driving sub-circuit, a data writing sub-circuit and a first compensation sub-circuit. The driving sub-circuit is connected with the first pixel node, the second pixel node and the third pixel node, and is configured to generate the driving signal under the control of the first pixel node; the data writing sub-circuit is connected with the scan end, the data line and one pixel node as a data writing node, and is configured to write a data signal to the data writing node under the control of the scan end; and the first compensation sub-circuit is connected with a first compensation control end, the first pixel node and the third pixel node, and is configured to turn on the first pixel node and the third pixel node under the control of the first compensation control end, so as to write a threshold voltage of the driving sub-circuit to the first pixel node. The pixel driving circuit is configured to perform writing the data signal to the data writing node and writing the threshold voltage of the driving sub-circuit to the first pixel node in steps. The data writing sub-circuit writes the data signal to the data writing node for a time period which is less than a time period for the first compensation sub-circuit to write the threshold voltage of the driving sub-circuit to the first pixel node.

[0008] In some example embodiments, a starting time for the data writing sub-circuit to write the data signal to the data writing node is later than an ending time for the first compensation sub-circuit to write the threshold voltage of the driving sub-circuit to the first pixel node.

[0009] In some example embodiments, the plurality of reset control terminals comprises a first reset control terminal, a second reset control terminal, and a third reset control terminal. The plurality of pixel nodes further comprises a fifth pixel node connected with a first light emitting electrode of the at least one light emitting element. The pixel driving circuit further comprises a first reset sub-circuit, a second reset sub-circuit, and a third reset sub-circuit. The first reset sub-circuit is connected with the first reset control terminal, a first initial signal line, and the first pixel node, and is configured to write a first initial signal provided by the first initial signal line to the first pixel node under the control of the first reset control terminal. The second reset sub-circuit is connected with the second reset control terminal, a second initial signal line, and the fifth pixel node, and is configured to write a second initial signal provided by the second initial signal line to the fifth pixel node under the control of the second reset control terminal. The third reset sub-circuit is connected with the third reset control terminal, a reference signal line, and the second pixel node, and is configured to write a reference signal provided by the reference signal line to the second pixel node under the control of the third reset control terminal, or is connected with the third reset control terminal, a third initial signal line, and the second pixel node, and is configured to write a third initial signal provided by the third initial signal line to the second pixel node under the control of the third reset control terminal.

[0010] In some example embodiments, the first compensation control terminal is configured to receive the same signal as the second reset control terminal, or the first compensation control terminal is configured to receive the same signal as the first reset control terminal.

[0011] In some example embodiments, the sensing reset control terminal is configured to receive the same signal as the first reset control terminal, or the sensing reset control terminal is configured to receive the same signal as the second reset control terminal.

[0012] In some example embodiments, the first reset sub-circuit comprises a first reset transistor, a gate of the first reset transistor is connected with the first reset control terminal, a first electrode of the first reset transistor is connected with the first initial signal line, and a second electrode of the first reset transistor is connected with the first pixel node. The second reset sub-circuit comprises a second reset transistor, a gate of the second reset transistor is connected with the second reset control terminal, a first electrode of the second reset transistor is connected with the second initial signal line, and a second electrode of the second reset transistor is connected with the fifth pixel node. The third reset sub-circuit comprises a third reset transistor, a gate of the third reset transistor is connected with the third reset control terminal, a first electrode of the third reset transistor is connected with the reference signal line or the third initial signal line, and a second electrode of the third reset transistor is connected with the second pixel node.

[0013] In some example embodiments, the plurality of pixel nodes further comprises a fourth pixel node; and the plurality of reset control terminals further comprises a fourth reset control terminal. The pixel driving circuit further comprises a first storage sub-circuit and a fourth reset sub-circuit. The first storage sub-circuit is connected with the first pixel node and the fourth pixel node, and is configured to store a voltage of the first pixel node; and the fourth reset sub-circuit is connected with the fourth reset control terminal, the fourth pixel node and a first power terminal, and is configured to turn on the fourth pixel node and the first power terminal under control of the fourth reset control terminal.

[0014] In some example embodiments, the fourth reset sub-circuit comprises a fourth reset transistor, a gate of the fourth reset transistor is connected with the fourth reset control terminal, a first pole of the fourth reset transistor is connected with the first power terminal, and a second pole of the fourth reset transistor is connected with the fourth pixel node. The first storage sub-circuit comprises a first capacitor, a first electrode of the first capacitor is connected with the first pixel node, and a second electrode of the first capacitor is connected with the fourth pixel node.

[0015] In some example embodiments, the plurality of reset control terminals further comprises a fifth reset control terminal. The plurality of pixel nodes further comprises a sixth pixel node, and the sixth pixel node is configured as the data write-in node. The pixel driving circuit further comprises a first storage sub-circuit and a fifth reset sub-circuit. The first storage sub-circuit is connected with the first pixel node and the sixth pixel node, and is configured to store a voltage of the first pixel node. The fifth reset sub-circuit is connected with the fifth reset control terminal, the second pixel node and the sixth pixel node, and is configured to turn on the second pixel node and the sixth pixel node under control of the fifth reset control terminal.

[0016] In some example embodiments, the sensing output control terminal is configured to receive a same signal as the scan terminal, and the sensing reset control terminal is configured to receive a same signal as any one of the plurality of reset control terminals; or the sensing reset control terminal is configured to receive a same signal as any one of the plurality of reset control terminals or the scan terminal.

[0017] In some example embodiments, the first sensing node is connected with the at least one photoelectric sensing element. The sensing driving circuit includes a sensing reset sub-circuit, a sensing sub-circuit, and a sensing output sub-circuit. The sensing reset sub-circuit is connected with a sensing reset signal line, the sensing reset control end, and the first sensing node, and is configured to write, under the control of the sensing reset control end, a sensing reset signal provided by the sensing reset signal line to the first sensing node to reset the first sensing node. The sensing sub-circuit is connected with the first sensing node, a second power supply end, and the second sensing node, and is configured to generate a sensing signal according to a photoelectric conversion signal written by the at least one photoelectric sensing element to the first sensing node. The sensing output sub-circuit is connected with the sensing output control end, the sensing read line, and the second sensing node, and is configured to provide the sensing signal to the sensing read line under the control of the sensing output control end.

[0018] In some example embodiments, the sensing driving circuit further includes a voltage stabilizing sub-circuit and a second compensation sub-circuit. The voltage stabilizing sub-circuit is connected with the first sensing node and a fourth power supply end. The second compensation sub-circuit is connected with a second compensation control end, the first sensing node, and the second sensing node, and is configured to turn on the first sensing node and the second sensing node under the control of the second compensation control end. The second compensation control end is configured to receive the same signal as the first compensation control end.

[0019] In some example embodiments, the sensing reset sub-circuit includes a sensing reset transistor, a gate of the sensing reset transistor is connected with the sensing reset control end, a first pole of the sensing reset transistor is connected with the sensing reset signal line, and a second pole of the sensing reset transistor is connected with the first sensing node. The sensing sub-circuit includes a sensing transistor, a gate of the sensing transistor is connected with the first sensing node, a first pole of the sensing transistor is connected with the second power supply end, and a second pole of the sensing transistor is connected with the second sensing node. The sensing output sub-circuit includes a sensing output transistor, a gate of the sensing output transistor is connected with the sensing output control end, a first pole of the sensing output transistor is connected with the second sensing node, and a second pole of the sensing output transistor is connected with the sensing read line. The voltage stabilizing sub-circuit includes a voltage stabilizing capacitor, a first electrode of the voltage stabilizing capacitor is connected with the first sensing node, and a second electrode of the voltage stabilizing capacitor is connected with the fourth power supply end. The second compensation sub-circuit includes a second compensation transistor, a gate of the second compensation transistor is connected with the second compensation control end, a first pole of the second compensation transistor is connected with the second sensing node, and a second pole of the second compensation transistor is connected with the first sensing node.

[0020] In another aspect, the embodiment provides a driving method of a composite driving circuit, applied to the composite driving circuit as described above, the driving method comprising: the pixel driving circuit performing reset on at least one pixel node in the plurality of pixel nodes under the control of at least one reset control terminal in the plurality of reset control terminals, writing a data signal provided by a data line into one of the pixel nodes as a data writing node under the control of a scan terminal, and generating a driving signal for driving the at least one light emitting element to emit light according to the data signal; the sensing driving circuit performing reset on a first sensing node under the control of a sensing reset control terminal, generating a sensing signal according to a photoelectric conversion signal of the at least one photoelectric sensing element written into the first sensing node, and providing the sensing signal written into a second sensing node to the sensing read line under the control of the sensing output control terminal. When the sensing reset control terminal is configured to receive the same signal as one of the plurality of reset control terminals, the composite driving circuit synchronously performs reset on the at least one pixel node and reset on the first sensing node. When the sensing output control terminal is configured to receive the same signal as the scan terminal, the composite driving circuit synchronously performs writing of the data signal into the data writing node and output of the sensing signal from the sensing read line.

[0021] In some example embodiments, the driving method further comprises: the pixel driving circuit writing a threshold voltage of a driving sub-circuit into the first pixel node under the control of a first compensation control terminal; and the sensing driving circuit writing a threshold voltage of a sensing sub-circuit into the first sensing node under the control of a second compensation control terminal. The first compensation control terminal and the second compensation control terminal are configured to receive the same signal as one of the plurality of reset control terminals.

[0022] In some example embodiments, the first compensation control terminal and the scan terminal are configured to receive different signals. The pixel driving circuit performs writing of the data signal into the data writing node and writing of the threshold voltage of the driving sub-circuit into the first pixel node in steps.

[0023] In some example embodiments, when the pixel driving circuit writes the threshold voltage of the driving sub-circuit into the first pixel node, the sensing driving circuit synchronously performs generation of the sensing signal according to the photoelectric conversion signal of the at least one photoelectric sensing element written into the first sensing node.

[0024] In some example embodiments, the driving cycle of the pixel driving circuit includes a refresh frame and a holding frame. In the refresh frame, the pixel driving circuit resets at least one of the plurality of pixel nodes under the control of at least one of the plurality of reset control terminals, and the sensing driving circuit resets the first sensing node; in the holding frame, the pixel driving circuit generates a driving signal for driving at least one light emitting element to emit light according to a data signal written in the refresh frame, and the sensing driving circuit outputs the sensing signal from the sensing read line; after the sensing driving circuit resets the first sensing node and before the sensing driving circuit outputs the sensing signal from the sensing read line, the sensing driving circuit generates a sensing signal according to a photoelectric conversion signal of the at least one photoelectric sensing element written in the first sensing node.

[0025] In some example embodiments, the driving cycle of the pixel driving circuit includes a refresh frame and a holding frame. In the holding frame, the pixel driving circuit resets at least one of the plurality of pixel nodes under the control of at least one of the plurality of reset control terminals, and the sensing driving circuit resets the first sensing node; in the refresh frame, the pixel driving circuit writes a data signal provided by the data line into one of the plurality of pixel nodes as a data writing node under the control of the scan terminal, and the sensing driving circuit outputs the sensing signal from the sensing read line; after the sensing driving circuit resets the first sensing node and before the sensing driving circuit outputs the sensing signal from the sensing read line, the sensing driving circuit generates a sensing signal according to a photoelectric conversion signal of the at least one photoelectric sensing element written in the first sensing node.

[0026] In another aspect, the embodiment provides a display panel, comprising: a substrate, a plurality of pixel driving circuits arranged on the substrate, a plurality of sensing driving circuits, a plurality of light emitting elements, and a plurality of photoelectric sensing elements. At least one pixel driving circuit of the plurality of pixel driving circuits comprises a plurality of pixel nodes, and is connected with a scan end, a data line, a plurality of reset control ends, and at least one light emitting element of the plurality of light emitting elements, and is configured to reset at least one pixel node of the plurality of pixel nodes under control of at least one reset control end of the plurality of reset control ends, write a data signal provided by the data line to one pixel node as a data writing node under control of the scan end, and generate a driving signal for driving the at least one light emitting element to emit light according to the data signal. At least one sensing driving circuit of the plurality of sensing driving circuits comprises a first sensing node and a second sensing node, and is connected with a sensing reset control end, a sensing output control end, a sensing reading line, and at least one photoelectric sensing element of the plurality of photoelectric sensing elements, and is configured to reset the first sensing node under control of the sensing reset control end, generate a sensing signal according to a photoelectric conversion signal written by the at least one photoelectric sensing element to the first sensing node, and provide the sensing signal written to the second sensing node to the sensing reading line under control of the sensing output control end. The display panel satisfies at least one of the following: the sensing output control end connected with the at least one sensing driving circuit is configured to receive the same signal as the scan end connected with the at least one pixel driving circuit; and the sensing reset control end connected with the at least one sensing driving circuit is configured to receive the same signal as one reset control end of the plurality of reset control ends connected with the at least one pixel driving circuit.

[0027] In some example embodiments, the plurality of pixel driving circuits and the plurality of sensing driving circuits are arranged in an array, n sensing driving circuits are arranged at intervals of m pixel driving circuits in a first direction; wherein m and n are both integers greater than 0, and m is greater than n.

[0028] In some example embodiments, the plurality of pixel driving circuits and the plurality of sensing driving circuits arranged in the first direction are configured to be connected with the same scan line; the plurality of pixel driving circuits arranged in a second direction are configured to be connected with the same data line, the plurality of sensing driving circuits arranged in the second direction are configured to be connected with the same sensing reading line, and the second direction intersects the first direction.

[0029] In some example embodiments, the plurality of light emitting elements are divided into a plurality of display units, the plurality of display units are arranged in a first direction and a second direction, the first direction intersects the second direction. Each display unit includes a light emitting element emitting a first color light, a light emitting element emitting a second color light, and a light emitting element emitting a third color light. Within the display unit, the light emitting element emitting the first color light and the light emitting element emitting the second color light are adjacent in the first direction, and the light emitting element emitting the third color light is on the same side of the light emitting element emitting the first color light and the light emitting element emitting the second color light in the second direction. A photoelectric sensing element is arranged between the light emitting elements emitting the third color light of two adjacent display units in the first direction.

[0030] In some example embodiments, the plurality of light emitting elements are divided into a plurality of display units, the plurality of display units are arranged in a first direction and a second direction, the first direction intersects the second direction. Each display unit includes a light emitting element emitting a first color light, a light emitting element emitting a second color light, and two light emitting elements emitting a third color light. At least one photoelectric sensing element is arranged between two light emitting elements emitting the third color light adjacent in the first direction or the second direction.

[0031] In some example embodiments, the at least one light emitting element includes a first light emitting electrode, a light emitting functional layer, and a second light emitting electrode arranged in a stack. The at least one photoelectric sensing element includes a first sensing electrode, a sensing functional layer, and a second sensing electrode arranged in a stack. The first light emitting electrode is connected to the pixel driving circuit, the first sensing electrode is connected to the sensing driving circuit, and the second light emitting electrode and the second sensing electrode are configured to receive the same signal; or the first light emitting electrode and the first sensing electrode are configured to receive the same signal, the second light emitting electrode is connected to the pixel driving circuit, and the second sensing electrode is connected to the sensing driving circuit.

[0032] In some example embodiments, the first light emitting electrode and the first sensing electrode are arranged in the same layer, and the second light emitting electrode and the second sensing electrode are arranged in the same layer.

[0033] In some example embodiments, the display panel further includes a first partition structure and a second partition structure, the first partition structure is located between adjacent light emitting elements, and the second partition structure is located between the at least one light emitting element and the adjacent photoelectric sensing element.

[0034] In some example embodiments, the first light emitting electrode is located on a side of the second light emitting electrode closer to the substrate, and the first sensing electrode is located on a side of the second sensing electrode farther from the substrate; or, the first light emitting electrode is located on a side of the second light emitting electrode farther from the substrate, and the first sensing electrode is located on a side of the second sensing electrode closer to the substrate.

[0035] In some example embodiments, the display panel further comprises: a first partition structure located between adjacent light emitting elements.

[0036] In some example embodiments, the display panel further comprises: a color filter layer and a first black matrix layer located on a side of the plurality of light emitting elements and the plurality of photoelectric sensing elements farther from the substrate. The color filter layer comprises: a plurality of first filter units and a plurality of second filter units; the first black matrix layer is located between different filter units; the first filter units at least partially overlap the light emitting regions of at least one light emitting element in the orthographic projection of the substrate, and the second filter units at least partially overlap the sensing regions of at least one photoelectric sensing element in the orthographic projection of the substrate.

[0037] In some example embodiments, the display panel further comprises: at least one touch control wiring layer located on a side of the color filter layer closer to the substrate; the touch control wiring layer in the orthographic projection of the substrate surrounds the light emitting region of a single light emitting element in the orthographic projection of the substrate; and the touch control wiring layer in the orthographic projection of the substrate surrounds or partially surrounds the sensing region of a single photoelectric sensing element in the orthographic projection of the substrate.

[0038] In some example embodiments, the display panel further comprises: at least one touch control wiring layer located on a side of the first black matrix layer farther from the substrate; and a second black matrix layer located on a side of the at least one touch control wiring layer farther from the substrate. The first black matrix layer and the second black matrix layer in the orthographic projection of the substrate cover the orthographic projection of the at least one touch control wiring layer in the substrate.

[0039] In another aspect, the embodiments provide a display device comprising the display panel as described above.

[0040] Other aspects can become apparent after reading and understanding the accompanying drawings and detailed description.

[0041] SUMMARY

[0042] The accompanying drawings are used to provide an understanding of the technical solutions of the present application, and constitute a part of the specification, and are used together with the embodiments of the present application to explain the technical solutions of the present application, and do not constitute a limitation on the technical solutions of the present application.

[0043] Fig. 1 is a structural schematic diagram of a composite driving circuit according to at least one embodiment of the present disclosure;

[0044] Fig. 2 is a structural schematic diagram of a pixel driving circuit according to at least one embodiment of the present disclosure;

[0045] Fig. 3 is an equivalent circuit diagram of a pixel driving circuit according to at least one embodiment of the present disclosure;

[0046] Fig. 4 is a structural schematic diagram of a sensing driving circuit according to at least one embodiment of the present disclosure;

[0047] Fig. 5 is an equivalent circuit diagram of a sensing driving circuit according to at least one embodiment of the present disclosure;

[0048] Fig. 6 is an equivalent circuit diagram of a composite driving circuit according to at least one embodiment of the present disclosure;

[0049] Fig. 7 is a working timing diagram of the composite driving circuit shown in Fig. 6;

[0050] Fig. 8 is another equivalent circuit diagram of a composite driving circuit according to at least one embodiment of the present disclosure;

[0051] Fig. 9 is a working timing diagram of the composite driving circuit shown in Fig. 8;

[0052] Fig. 10 is another equivalent circuit diagram of a composite driving circuit according to at least one embodiment of the present disclosure;

[0053] Fig. 11 is a working timing diagram of the composite driving circuit shown in Fig. 10;

[0054] Fig. 12 is another structural schematic diagram of a sensing driving circuit according to at least one embodiment of the present disclosure;

[0055] Fig. 13 is another equivalent circuit diagram of a sensing driving circuit according to at least one embodiment of the present disclosure;

[0056] Fig. 14 is another equivalent circuit diagram of a composite driving circuit according to at least one embodiment of the present disclosure;

[0057] Fig. 15 is a working timing diagram of the composite driving circuit shown in Fig. 14;

[0058] Fig. 16 is another equivalent circuit diagram of a composite driving circuit according to at least one embodiment of the present disclosure;

[0059] Fig. 17 is a working timing diagram of the composite driving circuit shown in Fig. 16;

[0060] FIG. 18 is another schematic diagram of a pixel driving circuit according to at least one embodiment of the present disclosure;

[0061] FIG. 19 is another equivalent circuit diagram of a pixel driving circuit according to at least one embodiment of the present disclosure;

[0062] FIG. 20 is another equivalent circuit diagram of a composite driving circuit according to at least one embodiment of the present disclosure;

[0063] FIG. 21 is a timing diagram of the composite driving circuit shown in FIG. 20 according to at least one embodiment of the present disclosure;

[0064] FIG. 22 is another equivalent circuit diagram of a composite driving circuit according to at least one embodiment of the present disclosure;

[0065] FIG. 23 is another equivalent circuit diagram of a composite driving circuit according to at least one embodiment of the present disclosure;

[0066] FIG. 24 is a timing diagram of the composite driving circuit shown in FIG. 23 according to at least one embodiment of the present disclosure;

[0067] FIG. 25 is another equivalent circuit diagram of a composite driving circuit according to at least one embodiment of the present disclosure;

[0068] FIG. 26 is a schematic diagram of a display panel according to at least one embodiment of the present disclosure;

[0069] FIG. 27 is a schematic diagram of an arrangement of light emitting elements and photoelectric sensing elements according to at least one embodiment of the present disclosure;

[0070] FIG. 28 is another schematic diagram of an arrangement of light emitting elements and photoelectric sensing elements according to at least one embodiment of the present disclosure;

[0071] FIG. 29 is a schematic diagram of an arrangement of pixel driving circuits and sensing driving circuits according to at least one embodiment of the present disclosure;

[0072] FIG. 30 is a schematic diagram of an arrangement of pixel driving circuits, sensing driving circuits, light emitting elements, and photoelectric sensing elements according to at least one embodiment of the present disclosure;

[0073] FIG. 31 is another schematic diagram of an arrangement of pixel driving circuits, sensing driving circuits, light emitting elements, and photoelectric sensing elements according to at least one embodiment of the present disclosure;

[0074] FIG. 32 is another schematic diagram of an arrangement of pixel driving circuits, sensing driving circuits, light emitting elements, and photoelectric sensing elements according to at least one embodiment of the present disclosure;

[0075] FIG. 33 is a schematic diagram of a wiring arrangement of pixel driving circuits and sensing driving circuits according to at least one embodiment of the present disclosure;

[0076] FIG. 34 is a partial cross-sectional schematic diagram of a display panel according to at least one embodiment of the present disclosure;

[0077] FIG. 35 is another partial cross-sectional view of a display panel according to an embodiment of the present disclosure;

[0078] FIG. 36 is a partial plan view of a display panel according to an embodiment of the present disclosure;

[0079] FIG. 37 is another partial cross-sectional view of a display panel according to an embodiment of the present disclosure;

[0080] FIG. 38 is another partial plan view of a display panel according to an embodiment of the present disclosure;

[0081] FIG. 39 is another partial cross-sectional view of a display panel according to an embodiment of the present disclosure;

[0082] FIG. 40 is another partial plan view of a display panel according to an embodiment of the present disclosure;

[0083] FIG. 41 is another partial plan view of a display panel according to an embodiment of the present disclosure;

[0084] FIG. 42 is another partial cross-sectional view of a display panel according to an embodiment of the present disclosure;

[0085] FIG. 43 is a schematic view of a display device according to an embodiment of the present disclosure.

[0086] Detailed Description

[0087] Embodiments of the present disclosure will be described below with reference to the accompanying drawings. The embodiments can be implemented in various forms. It is readily apparent to those skilled in the art that the embodiments and features thereof can be changed or replaced without departing from the gist of the present disclosure. Therefore, the disclosure should not be interpreted as being limited to the following embodiments. Embodiments in the present disclosure and features in the embodiments can be combined with each other as long as there is no contradiction.

[0088] In the drawings, the size, the thickness, or the region of one or more constituent elements, or layers, shown in the drawings, is sometimes exaggerated for the sake of explanation or clarification. Therefore, one embodiment of the present disclosure is not necessarily limited to such a size or the illustrated shape. The drawings are schematically shown for the sake of explanation and one embodiment of the present disclosure is not limited to the shape or the numerical value illustrated in the drawings.

[0089] The ordinal numbers "first", "second", "third", and the like in the present specification are used to avoid confusion among constituent elements and are not used to limit the numbers in the specification. "A plurality of" in the present disclosure means two or more.

[0090] In this specification, terms of "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicating the positional or directional relationship of the components are used to describe the positional relationship of the components with reference to the drawings for the convenience of explanation and simplification of the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be construed as limiting on the present disclosure. The positional relationship of the components is changed as appropriate according to the direction of the components described. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0091] In this specification, unless explicitly defined and limited otherwise, the terms "mount", "connected", "connected", "coupled" should be broadly understood. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or connected; it can be directly connected, or indirectly connected through an intermediate, or communication between two elements inside. For those skilled in the art, the meaning of the above terms in the present disclosure can be understood according to the situation.

[0092] In this specification, "connection" can include "electrical connection". "Electrical connection" includes the case where the components are connected together through an element having a certain electrical effect. The "element having a certain electrical effect" is not particularly limited as long as it can transmit electrical signals between the connected components. Examples of the "element having a certain electrical effect" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having multiple functions, and the like.

[0093] In this specification, a transistor refers to an element including at least three terminals of a gate, a drain, and a source. The transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. In this specification, the channel region refers to a region where current mainly flows.

[0094] In this specification, the first electrode can be a drain, and the second electrode can be a source, or the first electrode can be a source, and the second electrode can be a drain. In the case of using a transistor with opposite polarity or in the case of changing the direction of current in the circuit operation, the functions of "source" and "drain" are sometimes exchanged with each other. Therefore, in this specification, "source" and "drain" can be exchanged with each other. In addition, the gate can also be referred to as the control electrode.

[0095] In the present specification, “parallel” refers to a state in which the angle formed by two straight lines is -10° or more and 10° or less, and thus also includes a state in which the angle is -5° or more and 5° or less. In addition, “perpendicular” refers to a state in which the angle formed by two straight lines is 80° or more and 100° or less, and thus also includes a state in which the angle is 85° or more and 95° or less.

[0096] In the present specification, a circle, an ellipse, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, etc. are not strictly so, and can be an approximate circle, an approximate ellipse, an approximate triangle, an approximate rectangle, an approximate trapezoid, an approximate pentagon, or an approximate hexagon, etc. There can be some small deformations due to tolerances, such as a fillet, an arc edge, and a deformation, etc.

[0097] In the present disclosure, “about” or “approximately” means not strictly limited boundaries, and allows for a range of process and measurement errors. In the present disclosure, “about the same” means a difference of 10% or less in the exponent value.

[0098] In the present disclosure, “A and B are disposed in the same layer” means that A and B are formed at the same time by the same patterning process, or the surfaces of A and B close to the substrate are substantially the same distance from the substrate, or the surfaces of A and B close to the substrate are in direct contact with the same film layer.

[0099] In the present disclosure, an effective level signal or a signal for conducting includes a level signal for turning on a transistor, for example, a low level signal for turning on a P-type transistor, and a high level signal for turning on an N-type transistor.

[0100] An optical photodetector can realize in-screen sensing, for example, can replace an under-screen sensor, save space of the entire display device, and realize thinning of the display panel. In some implementations, the sensing driving circuit of the optical photodetector is disposed in the same layer (or multiple layers) as the pixel driving circuit of the OLED. Since the sensing and reading time of the optical photodetector occupies the display refresh time of the display panel, the adaptability of the optical photodetector to the display panel (for example, a high-frequency display panel) needs to be improved.

[0101] The embodiment provides a composite driving circuit, a display panel, and a display device, which can improve the refresh rate of a display panel provided with an optical photodetector and realize high-frequency display.

[0102] The embodiment provides a composite driving circuit, comprising: a pixel driving circuit and a sensing driving circuit. The pixel driving circuit comprises a plurality of pixel nodes; the pixel driving circuit is connected with a scanning end, a data line, a plurality of reset control ends and at least one light-emitting element, and is configured to reset at least one pixel node in the plurality of pixel nodes under the control of at least one reset control end in the plurality of reset control ends; write a data signal provided by the data line into one pixel node as a data writing node under the control of the scanning end; and generate a driving signal for driving the at least one light-emitting element to emit light according to the data signal. The sensing driving circuit comprises a first sensing node and a second sensing node; the sensing driving circuit is connected with a sensing reset control end, a sensing output control end, a sensing reading line and at least one photoelectric sensing element, and is configured to reset the first sensing node under the control of the sensing reset control end; generate a sensing signal according to a photoelectric conversion signal written into the first sensing node by the at least one photoelectric sensing element; and provide the sensing signal written into the second sensing node to the sensing reading line under the control of the sensing output control end. The composite driving circuit satisfies at least one of the following conditions: the sensing output control end is configured to receive the same signal as the scanning end; and the sensing reset control end is configured to receive the same signal as one reset control end in the plurality of reset control ends.

[0103] In the composite driving circuit provided by the embodiment, the pixel driving circuit and the sensing driving circuit can multiplex part of signals, the occupation of the display refresh time of the display panel by the sensing and data reading time length of the photoelectric sensing element can be reduced, and thus the refresh rate of the display panel is improved.

[0104] In some example embodiments, the plurality of pixel nodes can include a first pixel node, a second pixel node, and a third pixel node. The pixel driving circuit can include a driving sub-circuit, a data writing sub-circuit, and a first compensation sub-circuit. The driving sub-circuit is connected with the first pixel node, the second pixel node, and the third pixel node, and is configured to generate a driving signal under the control of the first pixel node. The data writing sub-circuit is connected with a scan terminal, a data line, and one pixel node as a data writing node, and is configured to write a data signal to the data writing node under the control of the scan terminal. The first compensation sub-circuit is connected with a first compensation control terminal, the first pixel node, and the third pixel node, and is configured to turn on the first pixel node and the third pixel node under the control of the first compensation control terminal, so as to write a threshold voltage of the driving sub-circuit to the first pixel node. In some examples, the pixel driving circuit can be configured to perform the writing of the data signal to the data writing node and the writing of the threshold voltage of the driving sub-circuit to the first pixel node in steps. The time length for the data writing sub-circuit to write the data signal to the data writing node can be less than the time length for the first compensation sub-circuit to write the threshold voltage of the driving sub-circuit to the first pixel node. For example, the starting time for the data writing sub-circuit to write the data signal to the data writing node can be later than the ending time for the first compensation sub-circuit to write the threshold voltage of the driving sub-circuit to the first pixel node. The pixel driving circuit of the present example separates the data writing process and the threshold voltage compensation process, which can achieve sufficient compensation of the threshold voltage, thereby facilitating the realization of a high refresh rate, for example, the refresh rate can be greater than 120 Hz, for example, the refresh rate can be 240 Hz.

[0105] The scheme of the present embodiment is exemplified below through some examples.

[0106] FIG. 1 is a structural schematic diagram of a composite driving circuit according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 1, the composite driving circuit 10 can include a pixel driving circuit 11 and a sensing driving circuit 12. The pixel driving circuit 11 is connected with at least one light emitting element EL, and is configured to provide a driving signal to the connected at least one light emitting element EL. The sensing driving circuit 12 is connected with at least one optoelectric sensing element OPD, and is configured to generate a sensing signal according to the sensing result of the connected at least one optoelectric sensing element OPD. The pixel driving circuit 11 can drive the light emitting element EL to realize picture display, and the sensing driving circuit 12 can drive the optoelectric sensing element OPD to realize optical sensing, and further realize functions such as fingerprint recognition, touch, ambient light detection, heart rate monitoring, etc. by using the sensing result.

[0107] In some examples, the pixel driving circuit 11 can include a plurality of pixel nodes, one of which can serve as a data writing node. The pixel driving circuit 11 can be connected with a scan terminal GATE, a data line DL, a set of reset control terminals SW-RESET (e.g., including a plurality of reset control terminals), and a first power terminal VDD1. The pixel driving circuit 11 can be configured to reset at least one pixel node under the control of at least one reset control terminal, write a data signal provided by the data line DL to the data writing node under the control of the scan terminal GATE, and generate a driving signal for driving the light emitting element EL to emit light according to the data signal. The driving signal can be, for example, a driving current.

[0108] In some examples, the sensing driving circuit 12 can include a first sensing node and a second sensing node. The sensing driving circuit 12 can be connected with a sensing reset control terminal SW-RST, a sensing output control terminal SENSE, a sensing read line SL, and a second power terminal VDD2, and configured to reset the first sensing node under the control of the sensing reset control terminal SW-RST, write a photoelectric conversion signal from the optoelectronic sensing element OPD to the first sensing node, and generate a sensing signal, and provide the sensing signal written to the second sensing node to the sensing read line SL under the control of the sensing output control terminal SENSE.

[0109] In some examples, the light emitting element EL can include a first light emitting electrode, a light emitting functional layer, and a second light emitting electrode stacked. The first light emitting electrode of the light emitting element EL can be connected with the pixel driving circuit 11, and the second light emitting electrode of the light emitting element EL1 can be connected with a third power terminal VSS1. The optoelectronic sensing element OPD can include a first sensing electrode, a sensing functional layer, and a second sensing electrode stacked. The first sensing electrode of the optoelectronic sensing element OPD can be connected with the sensing driving circuit 12, and the second sensing electrode of the optoelectronic sensing element 12 can be connected with a fourth power terminal VSS2.

[0110] In some examples, the first power terminal VDD1 and the second power terminal VDD2 can be configured to receive the same signal, e.g., configured to receive a first power signal. The third power terminal VSS1 and the fourth power terminal VSS2 can be configured to receive the same signal, e.g., configured to receive a second power signal. The first power signal can be greater than the second power signal. For example, the first power signal can be a positive voltage signal, and the second power signal can be a negative voltage signal.

[0111] In some examples, the sensing output control terminal SENSE can be configured to receive the same signal as the scan terminal GATE. For example, the scan terminal GATE connected to the at least one pixel driving circuit 11 and the sensing output control terminal SENSE connected to the at least one sensing driving circuit 12 can be connected to the same scan line. In this way, the process of the pixel driving circuit 11 writing a data signal to the data writing node can be synchronized with the process of the sensing driving circuit 12 providing a sensing signal to the sensing reading line SL.

[0112] In some examples, the sensing reset control terminal SW-RST can be configured to receive the same signal as one of the reset control terminals in the group of reset control terminals. For example, the sensing reset control terminal SW-RST connected to the at least one sensing driving circuit 12 and one of the reset control terminals connected to the at least one pixel driving circuit 11 can be connected to the same reset control line. In this way, the process of the pixel driving circuit 11 resetting one of the pixel nodes can be synchronized with the process of the sensing driving circuit 12 resetting the first sensing node.

[0113] In some examples, the sensing output control terminal SENSE can be configured to receive the same signal as the scan terminal GATE; and the sensing reset control terminal SW-RST can be configured to receive the same signal as one of the reset control terminals in the group of reset control terminals. In this way, the process of the pixel driving circuit 11 writing a data signal to the data writing node can be synchronized with the process of the sensing driving circuit 12 providing a sensing signal to the sensing reading line SL; and the process of the pixel driving circuit 11 resetting one of the pixel nodes can be synchronized with the process of the sensing driving circuit 12 resetting the first sensing node.

[0114] FIG. 2 is a schematic diagram of a structure of a pixel driving circuit according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 2, the pixel driving circuit can include a driving sub-circuit 111, a data writing sub-circuit 112, a compensation sub-circuit 113, a first storage sub-circuit 114, a second storage sub-circuit 115, a first reset sub-circuit 101, a second reset sub-circuit 102, a third reset sub-circuit 103, a fourth reset sub-circuit 104, a first light emitting control sub-circuit 106, and a second light emitting control sub-circuit 107.

[0115] In some examples, the first reset sub-circuit 101 can be connected with a first reset control terminal SW-RESET1, a first initial signal line INIT1 and a first pixel node PN1, and be configured to write, under control of the first reset control terminal SW-RESET1, a first initial signal provided by the first initial signal line INIT1 to the first pixel node PN1 to reset the first pixel node PN1. The second reset sub-circuit 102 can be connected with a second reset control terminal SW-RESET2, a second initial signal line INIT2 and a fifth pixel node PN5, and be configured to write, under control of the second reset control terminal SW-RESET2, a second initial signal provided by the second initial signal line INIT2 to the fifth pixel node PN5 to reset the fifth pixel node PN5. The third reset sub-circuit 103 can be connected with a third reset control terminal SW-RESET3, a reference signal line REF and a second pixel node PN2, and be configured to write, under control of the third reset control terminal SW-RESET3, a reference signal provided by the reference signal line REF to the second pixel node PN2. The fourth reset sub-circuit 104 can be connected with a fourth reset control terminal SW-RESET4, a fourth pixel node PN4 and a first power supply terminal VDD1, and be configured to turn on the fourth pixel node PN4 and the first power supply terminal VDD1 under control of the fourth reset control terminal SW-RESET4.

[0116] In some examples, the driving sub-circuit 111 can be connected with the first pixel node PN1, the second pixel node PN2 and the third pixel node PN3, and be configured to generate, under control of the first pixel node PN1, a driving signal for driving the light emitting element EL to emit light. The data writing sub-circuit 112 can be connected with a data line DL, the second pixel node PN2 and a scan terminal GATE, and be configured to write, under control of the scan terminal GATE, a data signal provided by the data line DL to the second pixel node PN2. The first compensation transistor 113 can be connected with the first pixel node PN1, the third pixel node PN3 and a first compensation control terminal CMP1, and be configured to turn on the first pixel node PN1 and the third pixel node PN3 under control of the first compensation control terminal CMP1 to write a threshold voltage of the driving sub-circuit 111 to the first pixel node PN1.

[0117] In some examples, the first storage sub-circuit 114 can be connected with the first pixel node PN1 and the fourth pixel node PN4, and be configured to store a potential of the first pixel node PN1. The second storage sub-circuit 115 can be connected with the fourth pixel node PN4 and the second pixel node PN2, and be configured to store a potential of the second pixel node PN2.

[0118] In some examples, the first light emitting control sub-circuit 106 can be connected with the second pixel node PN2, the light emitting control end EM and the first power supply end VDD1, and configured to turn on the second pixel node PN2 and the first power supply end VDD1 under the control of the light emitting control end EM. The second light emitting control sub-circuit 107 can be connected with the third pixel node PN3, the fourth pixel node PN4 and the light emitting control end, and configured to turn on the third pixel node PN3 and the fifth pixel node PN5 under the control of the light emitting control end EM.

[0119] In some examples, the first light emitting electrode of the light emitting element EL can be connected with the fifth pixel node PN5, and the second light emitting electrode can be connected with the third power supply end VSS1. For example, the first light emitting electrode can be an anode of the light emitting element EL, and the second light emitting electrode can be a cathode of the light emitting element EL.

[0120] FIG. 3 is an equivalent circuit diagram of a pixel driving circuit according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 3, the pixel driving circuit of the present example can be a 9T2C structure, including nine transistors and two capacitors. Among them, the driving sub-circuit 111 can include a driving transistor PT3; the data writing sub-circuit 112 can include a data writing transistor PT4; the first compensation sub-circuit 113 can include a first compensation transistor PT2; the first reset sub-circuit 101 can include a first reset transistor PT1; the second reset sub-circuit 102 can include a second reset transistor PT7; the third reset sub-circuit 103 can include a third reset transistor PT8; the fourth reset sub-circuit 104 can include a fourth reset transistor PT9; the first light emitting control sub-circuit 106 can include a first light emitting control transistor PT5; the second light emitting control sub-circuit 107 can include a second light emitting control transistor PT6; the first storage sub-circuit 114 can include a first capacitor C1; and the second storage sub-circuit 115 can include a second capacitor C2.

[0121] In some examples, the gate of the driving transistor PT3 is connected with the first pixel node PN1, the first pole of the driving transistor PT3 is connected with the second pixel node PN2, and the second pole of the driving transistor PT3 is connected with the third pixel node PN3. The driving transistor PT3 can determine the size of the driving signal according to the voltage difference between its gate and first pole.

[0122] In some examples, a gate of the data write transistor PT4 is connected with the scan terminal GATE, a first electrode of the data write transistor PT4 is connected with the data line DL, and a second electrode of the data write transistor PT4 is connected with the second pixel node PN2. When a conductive signal is applied to the scan terminal GATE, the data write transistor PT4 writes a data signal provided by the data line DL to the second pixel node PN2. In the present example, the second pixel node PN2 is a data write node.

[0123] In some examples, a gate of the first compensation transistor PT2 is connected with the first compensation control terminal CMP1, a first electrode of the first compensation transistor PT2 is connected with the third pixel node PN3, and a second electrode of the first compensation transistor PT2 is connected with the first pixel node PN1. When a conductive signal is applied to the first compensation control terminal CMP1, the first compensation transistor PT2 turns on the first pixel node PN1 and the third pixel node PN3.

[0124] In some examples, a first electrode of the first capacitor C1 is connected with the first pixel node PN1, and a second electrode of the first capacitor C1 is connected with the fourth pixel node PN4. A first electrode of the second capacitor C2 is connected with the second pixel node PN2, and a second electrode of the second capacitor C2 is connected with the fourth pixel node PN4.

[0125] In some examples, a gate of the first reset transistor PT1 is connected with the first reset control terminal SW-RESET1, a first electrode of the first reset transistor PT1 is connected with the first initial signal line INIT1, and a second electrode of the first reset transistor PT1 is connected with the first pixel node PN1. When a conductive signal is applied to the first reset control terminal SW-RESET1, the first reset transistor PT1 writes a first initial signal transmitted by the first initial signal line INIT1 to the first pixel node PN1 to reset the first pixel node PN1.

[0126] In some examples, a gate of the second reset transistor PT7 is connected with the second reset control terminal SW-RESET2, a first electrode of the second reset transistor PT7 is connected with the second initial signal line INIT2, and a second electrode of the second reset transistor PT7 is connected with the fifth pixel node PN5. When a conductive signal is applied to the second reset control terminal SW-RESET2, the second reset transistor PT7 writes a second initial signal transmitted by the second initial signal line INIT2 to the fifth pixel node PN5 to reset the fifth pixel node PN5.

[0127] In some examples, a gate of the third reset transistor PT8 is connected with the third reset control end SW-RESET3, a first electrode of the third reset transistor PT8 is connected with the reference signal line REF, and a second electrode of the third reset transistor PT8 is connected with the second pixel node PN2. When a conductive signal is applied to the third reset control end SW-RESET3, the third reset transistor PT8 writes the reference signal transmitted by the reference signal line REF to the second pixel node PN2.

[0128] In some examples, a gate of the fourth reset transistor PT9 is connected with the fourth reset control end SW-RESET4, a first electrode of the fourth reset transistor PT9 is connected with the first power supply end VDD1, and a second electrode of the fourth reset transistor PT9 is connected with the fourth pixel node PN4. When a conductive signal is applied to the fourth reset control end SW-RESET4, the fourth reset transistor PT9 can connect the fourth pixel node PN4 and the first power supply end VDD1.

[0129] In some examples, the plurality of pixel nodes of the pixel driving circuit can include a first pixel node PN1, a second pixel node PN2, a third pixel node PN3, a fourth pixel node PN4, and a fifth pixel node PN5. The second pixel node PN2 can be a data writing node, and the fifth pixel node PN5 can be a light emitting element reset node.

[0130] In some examples, the first pixel node PN1 can be a connection point of a second electrode of the first reset transistor PT1, a second electrode of the first compensation transistor PT2, a gate of the driving transistor PT3, and a first electrode of the first capacitor C1. The second pixel node PN2 can be a connection point of a second electrode of the data writing transistor PT4, a first electrode of the driving transistor PT3, a first electrode of the second capacitor C2, and a second electrode of the first light emitting control transistor PT5. The third pixel node PN3 can be a connection point of a second electrode of the driving transistor PT3, a first electrode of the first compensation transistor PT2, and a first electrode of the second light emitting control transistor PT6. The fourth pixel node PN4 can be a connection point of a second electrode of the first capacitor C1, a second electrode of the second capacitor C2, and a second electrode of the fourth reset transistor PT9. The fifth pixel node PN5 can be a connection point of a second electrode of the second light emitting control transistor PT6, a second electrode of the second reset transistor PT7, and a first light emitting electrode of the light emitting element EL.

[0131] FIG. 3 shows an exemplary structure of the driving sub-circuit 111, the first compensation sub-circuit 113, the data writing sub-circuit 112, the first storage sub-circuit 114, the second storage sub-circuit 115, the first light-emitting control sub-circuit 106, the second light-emitting control sub-circuit 107, the first reset sub-circuit 101, the second reset sub-circuit 102, the third reset sub-circuit 103, and the fourth reset sub-circuit 104. It is easy for those skilled in the art to understand that the implementation of the above sub-circuits is not limited thereto as long as the functions thereof can be achieved.

[0132] FIG. 4 is a schematic diagram of a structure of a sensing driving circuit according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 4, the sensing driving circuit can include a sensing reset sub-circuit 122, a sensing sub-circuit 121, a sensing output sub-circuit 123, and a voltage stabilizing sub-circuit 124.

[0133] In some examples, the sensing reset sub-circuit 122 can be connected with a sensing reset signal terminal RST, a sensing reset control terminal SW-RST, and a first sensing node SN1, and configured to turn on the sensing reset signal terminal RST and the first sensing node SN1 under the control of the sensing reset control terminal SW-RST to reset the first sensing node SN1. The sensing sub-circuit 121 can be connected with the first sensing node SN1, a second sensing node SN2, and a second power supply terminal VDD2, and configured to generate a sensing signal under the control of the first sensing node SN1. The sensing output sub-circuit 123 can be connected with the second sensing node SN2, a sensing output control terminal SENSE, and a sensing read line SL, and configured to provide the sensing signal to the sensing read line SL under the control of the sensing output control terminal SENSE. The voltage stabilizing sub-circuit 124 can be connected with the first sensing node SN1 and a fourth power supply terminal VSS2, and configured to maintain the potential of the first sensing node SN1. A first sensing electrode of the photoelectric sensing element OPD can be connected with the first sensing node SN1, and a second sensing electrode of the photoelectric sensing element OPD can be connected with the fourth power supply terminal VSS2. For example, the first sensing electrode can be an anode of the photoelectric sensing element OPD, and the second sensing electrode can be a cathode of the photoelectric sensing element OPD.

[0134] FIG. 5 is an equivalent circuit diagram of a sensing driving circuit according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 5, the sensing driving circuit of the present example can be a 3T1C structure including three transistors and one capacitor. Among them, the sensing reset sub-circuit 122 can include a sensing reset transistor ST2; the sensing sub-circuit 121 can include a sensing transistor ST1; the sensing output sub-circuit 123 can include a sensing output transistor ST3; and the voltage stabilizing sub-circuit 124 can include a voltage stabilizing capacitor C jOPD .

[0135] In some examples, a gate of the sensing reset transistor ST2 is connected with the sensing reset control terminal SW-RST, a first electrode of the sensing reset transistor ST2 is connected with the sensing reset signal terminal RST, and a second electrode of the sensing reset transistor ST2 is connected with the first sensing node SN1. When a conductive signal is applied to the sensing reset control terminal SW-RST, the sensing reset transistor ST2 turns on the sensing reset signal terminal RST and the first sensing node SN1 to reset the first sensing node SN1.

[0136] In some examples, a gate of the sensing transistor ST1 is connected with the first sensing node SN1, a first electrode of the sensing transistor ST1 is connected with the second power terminal VDD2, and a second electrode of the sensing transistor ST1 is connected with the second sensing node SN2. When a photoelectric conversion signal generated by the photoelectric sensing element OPD is applied to the first sensing node SN1, the sensing transistor ST1 can generate a sensing signal by using a signal of the second power terminal VDD2.

[0137] In some examples, a gate of the sensing output transistor ST3 is connected with the sensing output control terminal SENSE, a first electrode of the sensing output transistor ST3 is connected with the second sensing node SN2, and a second electrode of the sensing output transistor ST3 is connected with the sensing read line SL. When a conductive signal is applied to the sensing output control terminal SENSE, the sensing output transistor ST3 provides the sensing signal written in the second sensing node SN2 to the sensing read line SL.

[0138] In some examples, a first electrode of the voltage stabilizing capacitor C jOPD is connected with the first sensing node SN1, and a second electrode of the voltage stabilizing capacitor C jOPD is connected with the fourth power terminal VSS2.

[0139] In some examples, the sensing driving circuit can include a first sensing node SN1 and a second sensing node SN2. The first sensing node SN1 can be a connection point of a first sensing electrode of the photoelectric sensing element OPD, a first electrode of the voltage stabilizing capacitor C jOPD , a second electrode of the sensing reset transistor ST1, and a gate of the sensing transistor ST1. The second sensing node SN2 can be a connection point of the second electrode of the sensing transistor ST1 and a first electrode of the sensing output transistor ST3.

[0140] FIG. 5 shows an exemplary structure of the sensing reset sub-circuit 122, the sensing sub-circuit 121, the sensing output sub-circuit 123, and the voltage stabilizing sub-circuit 124. It is easy for those skilled in the art to understand that the implementation of the above sub-circuits is not limited thereto as long as the functions thereof can be achieved.

[0141] FIG. 6 is an equivalent circuit diagram of a composite driving circuit according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 6, the composite driving circuit can include a pixel driving circuit 11 and a sensing driving circuit 12. The pixel driving circuit 11 can include a driving transistor PT3, a data writing transistor PT4, a first compensation transistor PT2, a first reset transistor PT1, a second reset transistor PT2, a third reset transistor PT8, a fourth reset transistor PT9, a first light emitting control transistor PT5, a second light emitting control transistor PT6, a first capacitor C1, and a second capacitor C2. The sensing driving circuit 12 can include a sensing transistor ST1, a sensing reset transistor ST2, a sensing output transistor ST3, and a voltage stabilizing capacitor C jOPD .

[0142] In some examples, a gate of the data writing transistor PT4 and a gate of the sensing output transistor ST3 are connected with a scan line GL. In other words, the scan terminal and the sensing output control terminal are both connected with the scan line GL and configured to receive the same scan signal.

[0143] In some examples, a gate of the first compensation transistor PT2, a gate of the second reset transistor PT7, and a gate of the third reset transistor PT8 are connected with a second reset control line RESET2. In other words, the first compensation control terminal, the second reset control terminal, and the third reset control terminal are all connected with the second reset control line RESET2 and configured to receive the same signal.

[0144] In some examples, a gate of the first reset transistor PT1 and a gate of the sensing reset transistor ST2 are connected with a first reset control line RESET1. In other words, the first reset control terminal and the sensing reset control terminal are both connected with the first reset control line RESET1 and configured to receive the same signal.

[0145] In some examples, a gate of the fourth reset transistor PT9 is connected with a third reset control line RESET3. In other words, the fourth reset control terminal is connected with the third reset control line RESET3. A gate of the first light emitting control transistor PT5 and a gate of the second light emitting control transistor PT6 are connected with a light emitting control line EML. In other words, the light emitting control terminals are connected with the light emitting control line EML.

[0146] In some examples, a first electrode of the first light emitting control transistor PT5 and a first electrode of the fourth reset transistor PT9 are both connected with a first power line VDDL. A first electrode of the sensing transistor ST1 is connected with the first power line VDDL. In other words, the first power terminal and the second power terminal are both connected with the first power line VDDL and configured to receive the same first power signal.

[0147] In some examples, the second light emitting electrode of the light emitting element EL is connected with the second power supply line VSSL. The second sensing electrode of the opto-sensing element OPD is connected with the second power supply line VSSL. In other words, the third power terminal and the fourth power terminal are both connected with the second power supply line VSSL, configured to receive the same second power signal.

[0148] The remaining description of the composite driving circuit of the present example can refer to the description of the equivalent circuit diagrams of the pixel driving circuit and the sensing driving circuit in the foregoing embodiments, and thus will not be repeated here.

[0149] In some examples, the first initial signal line INIT1 can be configured to provide a first initial signal; the second initial signal line INIT2 can be configured to provide a second initial signal. The first initial signal and the second initial signal can be the same or different. The reference signal line REF can be configured to provide a reference signal. The reference signal can be different from the first initial signal and the second initial signal. For example, the reference signal can be greater than the first initial signal and the second initial signal. The sensing reset signal line RSTL can be configured to provide a sensing reset signal. For example, the sensing reset signal can be the same as the first initial signal or the second initial signal.

[0150] In some examples, the first power supply line VDDL can be configured to provide a first power signal, which can be a constant high level signal; the second power supply line VSSL can be configured to provide a second power signal, which can be a constant low level signal. The first power signal is greater than the second power signal.

[0151] In some examples, the scan line GL can be configured to provide a scan signal. The scan signal can be configured to control the data writing transistor PT4 to write the data signal provided by the data line DL to the second pixel node PN2, and simultaneously control the sensing output transistor ST3 to provide the sensing signal to the sensing read line SL.

[0152] In some examples, the first reset control line RESET1 can be configured to provide a first reset control signal. The first reset control signal can be configured to control the first reset transistor T1 to write the first initial signal provided by the first initial signal line INIT1 to the first pixel node PN1, and simultaneously control the sensing reset transistor ST2 to write the sensing reset signal provided by the sensing reset signal line RSTL to the first sensing node SN1.

[0153] In some examples, the second reset control line RESET2 can be configured to provide a second reset control signal. The second reset control signal can be configured to control the first compensation transistor PT2 to turn on the first pixel node PN1 and the third pixel node PN3, and simultaneously control the second reset transistor PT7 to reset the fifth pixel node PN5 with a second initial signal provided by the second initial signal line INIT2, and control the third reset transistor PT8 to write a reference signal provided by the reference signal line REF into the second pixel node PN2.

[0154] In some examples, the third reset control line RESET3 can be configured to provide a third reset control signal. The third reset control signal can be configured to control the fourth reset transistor PT9 to write a first power signal provided by the first power supply line VDDL into the fourth pixel node PN4.

[0155] In some examples, the light emission control line EML can be configured to provide a light emission control signal. The light emission control signal can be configured to control the first light emission control transistor PT5 to write a first power signal provided by the first power supply line VDDL into the second pixel node PN2, and control the second light emission control transistor PT6 to turn on the third pixel node PN3 and the fifth pixel node PN5.

[0156] FIG. 7 is a timing diagram of the operation of the composite driving circuit shown in FIG. 6. In some examples, as shown in FIG. 6, the composite driving circuit can include 12 transistors (i.e., transistors PT1 to PT9, transistors ST1 to ST3) and 3 capacitor units (i.e., a first capacitor C1, a second capacitor C2, and a voltage stabilizing capacitor C jOPD ). The types of the 12 transistors of the composite driving circuit can be the same, for example, can all be P-type transistors, and can be low-temperature polysilicon thin film transistors. However, the present embodiment is not limited thereto.

[0157] In some examples, as shown in FIG. 6, the composite driving circuit can be connected with 10 input terminals (i.e., a data line DL, a scan line GL, a first reset control line RESET1, a second reset control line RESET2, a third reset control line RESET3, a first initial signal line INIT1, a second initial signal line INIT2, a reference signal line REF, a light emission control line EML, a sensing reset signal line RSTL), 1 power terminal (i.e., a first power supply line VDDL), and 1 output terminal (i.e., a sensing read line SL). The light emitting element EL and the optoelectric sensing element OPD can both be connected with a second power supply line VSSL.

[0158] In some examples, in a high refresh stage (e.g., a refresh rate of 120 Hz or 240 Hz), the pixel driving circuit writes the data signal in each frame, and in a low refresh rate stage (e.g., a refresh rate of 60 Hz), the driving period of the pixel driving circuit can include a refresh frame and a holding frame, the data signal is written in the refresh frame, and the data signal is not written in the holding frame. The data signal writing manner in the refresh frame is similar to the data signal writing manner in the high refresh stage.

[0159] The working timing of the composite driving circuit in the refresh frame and the holding frame of the present example is exemplified below with reference to FIG. 7.

[0160] In some examples, as shown in FIG. 7, the pixel driving circuit in the refresh frame can include a refresh reset stage A1, a threshold compensation stage A2, a data writing stage A3, and a refresh light emitting stage A4; and the sensing driving circuit in the refresh frame can include a sensing reset stage S1, a sensing stage S2, and a sensing output stage S3. The refresh reset stage A1 can be synchronized with the sensing reset stage S1, the sensing stage S2 can be synchronized with the threshold compensation stage A2, and the sensing output stage S3 can be synchronized with the data writing stage A3.

[0161] In the refresh reset stage A1 and the sensing reset stage S1, the first reset control line RESET1 provides a low-level first reset control signal, the second reset control line RESET2 provides a low-level second reset control signal, and the third reset control line RESET3 provides a low-level third reset control signal; the scan line GL provides a high-level scan signal, and the light emitting control line EML provides a high-level light emitting control signal.

[0162] The first reset control signal provided by the first reset control line RESET1 is low, and the first reset transistor PT1 and the sensing reset transistor ST2 are both turned on. The first initial signal transmitted by the first initial signal line INIT1 is provided to the first pixel node PN1 through the turned-on first reset transistor PT1, and the first pixel node PN1 is initialized (i.e., reset); the sensing reset signal transmitted by the sensing reset signal line RSTL is provided to the first sensing node SN1 through the turned-on sensing reset transistor ST2, and the first sensing node SN1 is initialized.

[0163] The second reset control signal provided by the second reset control line RESET2 is low, and the second reset transistor PT7, the third reset transistor PT8 and the first compensation transistor PT2 are all turned on. The first pixel node PN1 is connected with the third pixel node PN3 through the first compensation transistor PT2, and the third pixel node PN3 is initialized by the first initial signal. The second initial signal provided by the second initial signal line INIT2 is provided to the fifth pixel node PN5 through the turned-on second reset transistor PT7, and the fifth pixel node PN5 is initialized. The reference signal provided by the reference signal line REF is provided to the second pixel node PN2 through the turned-on third reset transistor PT8, so that the second pixel node PN2 is written with the reference signal.

[0164] The third reset control signal provided by the third reset control line RESET3 is low, and the fourth reset transistor PT9 is turned on. The first power signal provided by the first power supply line VDDL is written to the fourth pixel node PN4 through the turned-on fourth reset transistor PT9.

[0165] The light emission control signal provided by the light emission control line EML is high, and the first light emission control transistor PT5 and the second light emission control transistor PT6 are both turned off. The scanning signal provided by the scanning line GL is high, and the data writing transistor PT4 and the sensing output transistor ST3 are both turned off.

[0166] In the threshold compensation stage A2 and the sensing stage S2, the second reset control line RESET2 provides a low second reset control signal, and the third reset control line RESET3 provides a low third reset control signal; the first reset control line RESET1 provides a high first reset control signal, the light emission control line EML provides a high light emission control signal, and the scanning line GL provides a high scanning signal.

[0167] The first reset control signal provided by the first reset control line RST1 is high, and the first reset transistor PT1 and the sensing reset transistor ST2 are both turned off. The light emission control signal provided by the light emission control line EML is high, and the first light emission control transistor PT5 and the second light emission control transistor PT6 are both turned off. The scanning signal provided by the scanning line GL is high, and the data writing transistor PT4 and the sensing output transistor ST3 are both turned off.

[0168] The second reset control signal provided by the second reset control line RST2 is low, and the first compensation transistor PT2, the second reset transistor PT7 and the third reset transistor PT8 remain in the open state. In the threshold compensation stage A2, since the first reset transistor PT1 is closed and the second pixel node PN2 is written with the reference signal, the driving transistor PT3 is opened, and the threshold voltage of the driving transistor PT3 is written into the first pixel node PN1 through the open first compensation transistor PT2.

[0169] The third reset control signal provided by the third reset control line RST3 is low, and the fourth reset transistor PT9 remains in the open state, and the fourth pixel node PN4 can be maintained at the potential of the first power supply signal, so that the first capacitor C1 can maintain the potential of the first pixel node PN1 after writing the threshold voltage.

[0170] In the sensing stage S2, the photoelectric sensing element OPD can write the photoelectric conversion signal generated by sensing into the first sensing node SN1, and the voltage stabilizing capacitor C jOPD The photoelectric conversion signal written into the first sensing node SN1 can be stored. In response to the change of the potential of the first sensing node SN1, the sensing transistor ST1 is opened, and a corresponding sensing signal can be generated based on the size of the photoelectric conversion signal, and the sensing signal can be written into the second sensing node SN2.

[0171] In the data writing stage A3 and the sensing output stage S3, the scan line GL provides a low-level scan signal, the third reset control line RESET3 provides a low-level third reset control signal; the first reset control line RESET1 provides a high-level first reset control signal, the second reset control line RESET2 provides a high-level second reset control signal, and the light-emitting control line EML provides a high-level light-emitting control signal.

[0172] The first reset control signal provided by the first reset control line RST1 is high, and the first reset transistor PT1 and the sensing reset transistor ST2 are both closed. The light-emitting control signal provided by the light-emitting control line EML is high, and the first light-emitting control transistor PT5 and the second light-emitting control transistor PT6 are both closed. The second reset control signal provided by the second reset control line RESET2 is high, and the first compensation transistor PT2, the second reset transistor PT7 and the third reset transistor PT8 are all closed.

[0173] The scan signal provided by the scan line GL is low, and the data writing transistor PT4 and the sensing output transistor ST3 are both opened. The data signal provided by the data line DL is written into the second pixel node PN2 through the open data writing transistor PT4. In the sensing output stage S3, the sensing signal generated by the sensing transistor ST2 can be provided to the sensing reading line SL through the open sensing output transistor ST3.

[0174] The third reset control signal provided by the third reset control line RST3 is low, and the fourth reset transistor PT9 keeps open. The potential of the first pixel node PN1 can be maintained by the first capacitor C1, and the potential of the second pixel node PN2 can be maintained by the second capacitor C2. The first pixel node PN1 writes the threshold voltage of the driving transistor, and the second pixel node PN2 writes the data signal.

[0175] In the refresh emission phase A4, the emission control line EML provides a low-level emission control signal; the scan line GL provides a high-level scan signal, the first reset control line RESET1 provides a high-level first reset control signal, the second reset control line RESET2 provides a high-level second reset control signal, and the third reset control line RESET3 provides a high-level third reset control signal.

[0176] The scan signal provided by the scan line GL is high, and the data write transistor PT4 and the sensing output transistor ST3 are both closed. The first reset control signal provided by the first reset control line RST1 is high, and the first reset transistor PT1 and the sensing reset transistor ST2 are both closed. The second reset control signal provided by the second reset control line RESET2 is high, and the first compensation transistor PT2, the second reset transistor PT7 and the third reset transistor PT8 are all closed. The third reset control signal provided by the third reset control line RESET3 is high, and the fourth reset transistor PT9 is closed. In the refresh emission phase A4, the fourth reset transistor PT9 is closed, and the data signal written into the second pixel node PN2 can be coupled to write into the first pixel node PN1 through the first capacitor C1 and the second capacitor C2.

[0177] The emission control signal provided by the emission control line EML is low, and the first emission control transistor PT5 and the second emission control transistor PT6 are both open. In the refresh emission phase A4, the driving transistor T3 is open, and the first pixel node PN1 can record the data voltage and the threshold voltage at the same time. The first power supply signal provided by the first power supply line VDDL can be provided to the emission element EL through the first emission control transistor PT5, the driving transistor PT3 and the second emission control transistor PT6 to drive the emission element EL to emit light. In the refresh emission phase A4, the sensing driving circuit 12 can not work.

[0178] In the present example, the threshold compensation stage A2 of the pixel driving circuit 11 is prior to the data writing stage A3, and the threshold compensation duration (i.e. the duration of the threshold compensation stage A2) can be greater than the duration of the data writing stage A3 (i.e. the data writing duration 1H of a single row of pixel circuits in a frame), so as to ensure that the threshold voltage is sufficiently compensated, thereby ensuring the display effect. Moreover, the threshold voltage compensation stage A2 can be synchronized with the sensing stage S2 of the sensing driving circuit 12, so as to ensure the sensing duration of the photoelectric sensing element OPD.

[0179] In some examples, the pixel driving circuit 11 in the holding frame can include a holding reset stage B1 and a holding light-emitting stage B2. The sensing driving circuit 12 in the holding frame can not work.

[0180] In the holding reset stage B1, the second reset control line RESET2 provides a low-level second reset control signal; the scan line GL provides a high-level scan signal, the first reset control line RESET1 provides a high-level first reset control signal, the third reset control line RESET3 provides a high-level third reset control signal, and the light-emitting control line EML provides a high-level light-emitting control signal.

[0181] The scan signal provided by the scan line GL is high level, and the data writing transistor PT4 and the sensing output transistor ST3 are both closed. The first reset control signal provided by the first reset control line RST1 is high level, and the first reset transistor PT1 and the sensing reset transistor ST2 are both closed. The light-emitting control signal provided by the light-emitting control line EML is high level, and the first light-emitting control transistor PT5 and the second light-emitting control transistor PT6 are both closed. The third reset control signal provided by the third reset control line RESET3 is high level, and the fourth reset transistor PT9 is closed.

[0182] The second reset control signal provided by the second reset control line RESET2 is low level, and the first compensation transistor PT2, the second reset transistor PT7 and the third reset transistor PT8 are all turned on. In the holding reset stage B1, the potential of the first pixel node PN1 can be maintained by using the first capacitor C1 and the second capacitor C2, so that the voltage of the first pixel node PN1 is maintained to be the same as that in the refresh light-emitting stage A4 of the refresh frame, i.e. the first pixel node PN1 can record the data voltage and the threshold voltage at the same time.

[0183] In the holding light-emitting stage B2, the light-emitting control line EML provides a low-level light-emitting control signal; the scan line GL provides a high-level scan signal, the first reset control line RESET1 provides a high-level first reset control signal, the second reset control line RESET2 provides a high-level second reset control signal, and the third reset control line RESET3 provides a high-level third reset control signal.

[0184] When the scan signal provided by the scan line GL is high, the data write transistor PT4 and the sensing output transistor ST3 are both closed. When the first reset control signal provided by the first reset control line RST1 is high, the first reset transistor PT1 and the sensing reset transistor ST2 are both closed. When the second reset control signal provided by the second reset control line RESET2 is high, the first compensation transistor PT2, the second reset transistor PT7 and the third reset transistor PT8 are all closed. When the third reset control signal provided by the third reset control line RESET3 is high, the fourth reset transistor PT9 is closed.

[0185] When the light emitting control signal provided by the light emitting control line EML is low, the first light emitting control transistor PT5 and the second light emitting control transistor PT6 are both open. In the light emitting stage B2, the potential of the first pixel node PT1 is maintained, the threshold voltage and the data voltage written in the refresh frame are recorded, and the driving transistor PT3 is open. Under the control of the first pixel node PT1, the driving signal is provided to the light emitting element EL by using the first power signal to drive the light emitting element EL to emit light.

[0186] The pixel driving circuit 11 and the sensing driving circuit 12 in the example can share the scan line GL and the first reset control line RESET1, so that the threshold compensation stage of the pixel driving circuit 11 can be synchronized with the sensing stage of the sensing driving circuit 12, and the data write stage of the pixel driving circuit 11 can be synchronized with the sensing output stage of the sensing driving circuit 12. The display refresh time occupied by the sensing driving circuit 12 can be reduced, and the refresh rate of the display panel can be improved.

[0187] FIG. 8 is another equivalent circuit diagram of the composite driving circuit according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 8, the gate of the data write transistor PT4 of the pixel driving circuit 11 is connected with the scan line GL, and the gate of the sensing output transistor ST3 of the sensing driving circuit 12 is connected with the scan line GL. In other words, the scan end and the sensing output control end are both connected with the scan line GL and configured to receive the same scan signal.

[0188] In some examples, the gate of the first compensation transistor PT2, the gate of the second reset transistor PT7, the gate of the third reset transistor PT8 of the pixel driving circuit 11, and the gate of the sensing output transistor ST3 of the sensing driving circuit 12 are all connected with the second reset control line RESET2. In other words, the first compensation control end, the second reset control end, the third reset control end and the sensing reset end are all connected with the second reset control line RESET2 and configured to receive the same signal.

[0189] The remaining circuit of the composite driving circuit in the example can be referred to the description of the foregoing embodiments, and thus will not be described here again.

[0190] FIG. 9 is a timing diagram of the composite driving circuit shown in FIG. 8. In some examples, the composite driving circuit can include 12 transistors (i.e., transistors PT1 to PT9, and transistors ST1 to ST3) and 3 capacitor units (i.e., a first capacitor C1, a second capacitor C2, and a voltage stabilizing capacitor C jOPD ). The 12 transistors of the composite driving circuit can be of the same type, e.g., all P-type transistors. However, the present embodiments are not limited thereto.

[0191] In some examples, as shown in FIG. 8, the composite driving circuit can be connected with 10 input terminals (i.e., a data line DL, a scan line GL, a first reset control line RESET1, a second reset control line RESET2, a third reset control line RESET3, a first initial signal line INIT1, a second initial signal line INIT2, a reference signal line REF, an emission control line EML, and a sensing reset signal line RSTL), 1 power terminal (i.e., a first power line VDDL), and 1 output terminal (i.e., a sensing read line SL). The light emitting element EL and the optoelectric sensing element OPD can both be connected with a second power line VSSL.

[0192] In some examples, as shown in FIG. 9, the pixel driving circuit 11 in a refresh frame can include a refresh reset phase A1, a threshold compensation phase A2, a data write phase A3, and a refresh emission phase A4. The threshold compensation phase A2 can include a first sub-phase A21 and a second sub-phase A22. The pixel driving circuit 11 in a hold frame can include a hold reset phase B1 and a hold emission phase B2. The timing of the pixel driving circuit 11 in the refresh frame and the hold frame can be referred to the description of the foregoing embodiments, and thus will not be repeated here.

[0193] In some examples, as shown in FIG. 9, the sensing driving circuit 12 in a refresh frame can include a sensing reset phase S1, a sensing phase S2, and a sensing output phase S3. The sensing output phase S3 can be synchronized with the data write phase A3, the sensing reset phase S1 can be synchronized with the refresh reset phase A1 and the first sub-phase A21 of the threshold compensation phase A2, and the sensing phase S2 can be synchronized with the second sub-phase A22 of the threshold compensation phase A2.

[0194] In the sensing reset phase S1, the second reset control signal provided by the second reset control line RESET2 is at a low level, and the sensing reset transistor ST2 is turned on. The sensing reset signal transmitted by the sensing reset signal line RSTL is provided to the first sensing node SN1 through the turned-on sensing reset transistor ST2, and the first sensing node SN1 is initialized. The scan signal provided by the scan line GL is at a high level, and the sensing output transistor ST3 is turned off.

[0195] In the sensing phase S2, the second reset control signal provided by the second reset control line RESET2 is high, and the sensing reset transistor ST2 is off; the scan signal provided by the scan line GL is high, and the sensing output transistor ST3 is off.

[0196] In the sensing phase S2, the photoelectric sensing element OPD can write the photoelectric conversion signal generated by sensing into the first sensing node SN1, and the voltage stabilizing capacitor C jOPD The photoelectric conversion signal written into the first sensing node SN1 can be stored. In response to the change of the potential of the first sensing node SN1, the sensing transistor ST1 is turned on, and a corresponding sensing signal can be generated based on the size of the photoelectric conversion signal, which can be written into the second sensing node SN2.

[0197] In the sensing output phase S3, the second reset control signal provided by the second reset control line RESET2 is high, and the sensing reset transistor ST2 is off. The scan signal provided by the scan line GL is low, and the sensing output transistor ST3 is on. The sensing signal generated by the sensing transistor ST2 can be provided to the sensing read line SL through the turned-on sensing output transistor ST3.

[0198] The pixel driving circuit 11 and the sensing driving circuit 12 of the present example can share the scan line GL, so that the data writing phase of the pixel driving circuit 11 can be synchronized with the sensing output phase of the sensing driving circuit 12. Moreover, the pixel driving circuit 11 and the sensing driving circuit 12 can share the second reset control line RESET2, so that the initialization phase of the first sensing node SN1 can be synchronized with the initialization phase of the fifth pixel node PN5, thereby prolonging the time length of the sensing reset phase of the sensing driving circuit 12, i.e., prolonging the initialization time length of the first sensing node SN1. Compared with the embodiment of the composite driving circuit shown in FIG. 6, the present embodiment shortens the time length of the sensing phase of the sensing driving circuit of the composite driving circuit.

[0199] FIG. 10 is another equivalent circuit diagram of the composite driving circuit according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 10, the gate of the data writing transistor PT4 of the pixel driving circuit 11 is connected with the scan line GL, and the gate of the sensing output transistor ST3 of the sensing driving circuit 12 is connected with the scan line GL. In other words, the scan end and the sensing output control end are both connected with the scan line GL and configured to receive the same scan signal.

[0200] In some examples, the gate of the sensing reset transistor ST2 of the sensing driving circuit 12 is connected with a sensing reset control line OPDRST. In other words, the sensing reset control terminal is connected with the sensing reset control line OPDRST. The sensing reset control line OPDRST can be configured to transmit different signals from the first reset control line RESET1, the second reset control line RESET2, and the third reset control line RESET3.

[0201] The remaining circuit descriptions of the composite driving circuit of the present example can refer to the descriptions of the foregoing embodiments, and thus will not be described herein again.

[0202] FIG. 11 is a working timing diagram of the composite driving circuit shown in FIG. 10. In some examples, the composite driving circuit can include 12 transistors (i.e., the transistors PT1 to PT9 and the transistors ST1 to ST3) and 3 capacitor units (i.e., the first capacitor C1, the second capacitor C2, and the voltage stabilizing capacitor C jOPD ). The types of the 12 transistors of the composite driving circuit can be the same, for example, all P-type transistors. However, the present embodiment is not limited thereto.

[0203] In some examples, as shown in FIG. 10, the composite driving circuit can be connected with 11 input terminals (i.e., the data line DL, the scan line GL, the first reset control line RESET1, the second reset control line RESET2, the third reset control line RESET3, the first initial signal line INIT1, the second initial signal line INIT2, the reference signal line REF, the light emitting control line EML, the sensing reset signal line RSTL, the sensing reset control line OPDRST), 1 power terminal (i.e., the first power line VDDL), and 1 output terminal (i.e., the sensing reading line SL). The light emitting element EL and the photoelectric sensing element OPD can be both connected with the second power line VSSL.

[0204] In some examples, as shown in FIG. 11, the pixel driving circuit 11 in a refresh frame can include a refresh reset phase A1, a threshold compensation phase A2, a data writing phase A3, and a refresh light emitting phase A4. The pixel driving circuit 11 in a holding frame can include a holding reset phase B1 and a holding light emitting phase B2. The working timing of the pixel driving circuit 11 in the refresh frame and the holding frame can refer to the descriptions of the foregoing embodiments, and thus will not be described herein again.

[0205] In some examples, as shown in FIG. 11, the sensing reset phase S1 of the sensing driving circuit 12 can be located in the hold frame. For example, the sensing reset phase S1 can be performed synchronously with the hold reset phase B1 of the pixel driving circuit 11. The sensing phase can include a first sensing phase S21, which can be located before the sensing output phase S3, and a second sensing phase S22, which can be located after the sensing reset phase S1. For example, the second sensing phase S22 can be synchronous with the hold light emitting phase B2 of the pixel driving circuit 11 in the hold frame; the first sensing phase S21 can be synchronous with the refresh reset phase A1 and the threshold compensation phase A2 of the pixel driving circuit 11 in the refresh frame.

[0206] In the sensing reset phase S1, the sensing reset control signal provided by the sensing reset control line OPDRST is low, and the sensing reset transistor ST2 is turned on. The sensing reset signal transmitted by the sensing reset signal line RSTL is provided to the first sensing node SN1 through the turned-on sensing reset transistor ST2, and the first sensing node SN1 is initialized. The scan signal provided by the scan line GL is high, and the sensing output transistor ST3 is turned off.

[0207] In the first sensing phase S21 and the second sensing phase S22, the sensing reset control signal provided by the sensing reset control line OPDRST is high, and the sensing reset transistor ST2 is turned off. The scan signal provided by the scan line GL is high, and the sensing output transistor ST3 is turned off. The photoelectric sensing element OPD can write the photoelectric conversion signal generated by sensing into the first sensing node SN1, and the voltage stabilizing capacitor C jOPD The photoelectric conversion signal written into the first sensing node SN1 can be stored. In response to the change of the potential of the first sensing node SN1, the sensing transistor ST1 is turned on, and a corresponding sensing signal can be generated based on the size of the photoelectric conversion signal, which can be written into the second sensing node SN2.

[0208] In the sensing output phase S3, the sensing reset control signal provided by the sensing reset control line OPDRST is high, and the sensing reset transistor ST2 is turned off. The scan signal provided by the scan line GL is low, and the sensing output transistor ST3 is turned on. The sensing signal generated by the sensing transistor ST2 can be provided to the sensing read line SL through the turned-on sensing output transistor ST3.

[0209] The pixel driving circuit 11 and the sensing driving circuit 12 of the present example can share the scan line GL, so that the data writing phase of the pixel driving circuit 11 and the sensing output phase of the sensing driving circuit 12 can be synchronized. Moreover, the sensing driving circuit 12 can maintain the sensing phase in the hold frame, and compared with the foregoing embodiments, the present example can increase the time length of the sensing phase of the sensing driving circuit.

[0210] FIG. 12 is another schematic diagram of a sensing driving circuit according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 12, the sensing driving circuit can include a sensing reset sub-circuit 122, a sensing sub-circuit 121, a sensing output sub-circuit 123, a voltage stabilizing sub-circuit 124, and a second compensation sub-circuit 125.

[0211] In some examples, the second compensation sub-circuit 125 can be connected with the first sensing node SN1, the second sensing node SN2, and the second compensation control terminal CMP2, and configured to turn on the first sensing node SN1 and the second sensing node SN2 under the control of the second compensation control terminal CMP2, so as to compensate the threshold voltage of the sensing sub-circuit 121 to the first sensing node SN1. The remaining structures of the sensing driving circuit can refer to the description of the embodiment shown in FIG. 4, and thus will not be repeated here.

[0212] FIG. 13 is another equivalent circuit diagram of a sensing driving circuit according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 13, the sensing driving circuit of the present example can be a 4T1C structure including four transistors and one capacitor. Among them, the sensing reset sub-circuit 122 can include a sensing reset transistor ST2; the sensing sub-circuit 121 can include a sensing transistor ST1; the sensing output sub-circuit 123 can include a sensing output transistor ST3; the voltage stabilizing sub-circuit 124 can include a voltage stabilizing capacitor C jOPD ; and the second compensation sub-circuit 125 can include a second compensation transistor ST4.

[0213] In some examples, the gate of the second compensation transistor ST4 is connected with the second compensation control terminal CMP2, the first pole of the second compensation transistor ST4 is connected with the second sensing node SN2, and the second pole of the second compensation transistor ST4 is connected with the first sensing node SN1.

[0214] FIG. 13 shows an exemplary structure of the second compensation sub-circuit 125, and those skilled in the art can easily understand that the implementation of the above-mentioned sub-circuit is not limited thereto, as long as it can realize its function. The remaining structures of the sensing driving circuit of the present example can refer to the description of the foregoing embodiments, and thus will not be repeated here.

[0215] FIG. 14 is another equivalent circuit diagram of the composite driving circuit according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 14, the pixel driving circuit 11 can include a driving transistor PT3, a data writing transistor PT4, a first compensation transistor PT2, a first reset transistor PT1, a second reset transistor PT7, a third reset transistor PT8, a fourth reset transistor PT9, a first light emitting control transistor PT5, a second light emitting control transistor PT6, a first capacitor C1, and a second capacitor C2. The sensing driving circuit 12 can include a sensing transistor ST1, a sensing reset transistor ST2, a sensing output transistor ST3, a second compensation transistor ST4, and a voltage stabilizing capacitor C jOPD .

[0216] In some examples, the gate of the data writing transistor PT4 of the pixel driving circuit 11 is connected with the scan line GL, and the gate of the sensing output transistor ST3 of the sensing driving circuit 12 is connected with the scan line GL. In other words, the scan end and the sensing output control end are both connected with the scan line GL, and are configured to receive the same scan signal.

[0217] In some examples, the gate of the first compensation transistor PT2, the gate of the second reset transistor PT7, and the gate of the third reset transistor PT8 of the pixel driving circuit 11, and the gate of the second compensation transistor ST4 of the sensing driving circuit 12 are all connected with the second reset control line RESET2. In other words, the second compensation control end, the first compensation control end, the second reset control end, and the third reset control end are all connected with the second reset control line RESET2, and are configured to receive the same signal.

[0218] In some examples, the gate of the first reset transistor PT1 of the pixel driving circuit 11 is connected with the first reset control line RESET1, and the gate of the sensing reset transistor ST2 of the sensing driving circuit 12 is connected with the first reset control line RESET1. In other words, the first reset control end and the sensing reset control end are both connected with the first reset control line RESET1, and are configured to receive the same signal.

[0219] The remaining circuit description of the composite driving circuit of the present example can refer to the description of the foregoing embodiments, and thus will not be described here again.

[0220] FIG. 15 is a working timing diagram of the composite driving circuit shown in FIG. 14. In some examples, the composite driving circuit can include 13 transistors (i.e., the transistors PT1 to PT9, and the transistors ST1 to ST4) and 3 capacitor units (i.e., the first capacitor C1, the second capacitor C2, and the voltage stabilizing capacitor C jOPD ). The types of the 13 transistors of the composite driving circuit can be the same, for example, all P-type transistors. However, the present embodiment is not limited thereto.

[0221] In some examples, as shown in FIG. 14, the composite driving circuit can be connected with 10 input terminals (i.e., data lines DL, scan lines GL, a first reset control line RESET1, a second reset control line RESET2, a third reset control line RESET3, a first initial signal line INIT1, a second initial signal line INIT2, a reference signal line REF, a light-emitting control line EML, and a sensing reset signal line RSTL), 1 power supply terminal (i.e., a first power supply line VDDL), and 1 output terminal (i.e., a sensing read line SL). The light-emitting element EL and the optoelectric sensing element OPD can both be connected with the second power supply line VSSL.

[0222] In some examples, as shown in FIG. 15, the pixel driving circuit 11 in a refresh frame can include a refresh reset phase A1, a threshold compensation phase A2, a data writing phase A3, and a refresh light-emitting phase A4. The pixel driving circuit 11 in a holding frame can include a holding reset phase B1 and a holding light-emitting phase B2. The working timing of the pixel driving circuit 11 in the refresh frame and the holding frame can refer to the description of the foregoing embodiments, which will not be repeated here.

[0223] In some examples, the sensing driving circuit 12 in a refresh frame can include a sensing reset phase S1, a sensing phase S2, and a sensing output phase S3. The sensing output phase S3 can be synchronized with the data writing phase A3, the sensing reset phase S1 can be synchronized with the refresh reset phase A1, and the sensing phase S2 can be synchronized with the threshold compensation phase A2.

[0224] In some examples, when the second reset control signal provided by the second reset control line RESET2 is at a low level, the second compensation transistor ST4 is turned on, the first sensing node SN1 and the second sensing node SN2 can be turned on, and the threshold voltage of the sensing transistor ST1 can be written to the first sensing node SN1. For example, the threshold voltage compensation process of the first sensing node SN1 can be synchronized with the threshold voltage compensation process of the first pixel node PN1. The remaining description of the working timing of the sensing driving circuit 12 can refer to the description of the foregoing embodiments, which will not be repeated here.

[0225] The pixel driving circuit 11 and the sensing driving circuit 12 of the present example can share the scan line GL and the first reset control line RESET1, so that the threshold compensation phase of the pixel driving circuit 11 can be synchronized with the sensing phase of the sensing driving circuit 12, and the data writing phase of the pixel driving circuit 11 can be synchronized with the sensing output phase of the sensing driving circuit 12, which can reduce the display refresh time occupied by the sensing driving circuit 12 and is conducive to improving the refresh rate of the display panel. Moreover, the sensing driving circuit of the present example can perform threshold compensation on the first sensing node SN1 by setting the second compensation transistor, which can be conducive to improving the sensing effect.

[0226] FIG. 16 is another equivalent circuit diagram of the composite driving circuit according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 16, the gate of the data writing transistor PT4 of the pixel driving circuit 11 is connected with the scan line GL, and the gate of the sensing output transistor ST3 of the sensing driving circuit 12 is connected with the scan line GL. In other words, the scan end and the sensing output control end are both connected with the scan line GL, and are configured to receive the same scan signal.

[0227] In some examples, the gate of the sensing reset transistor ST2 of the sensing driving circuit 12 is connected with the sensing reset control line OPDRST. In other words, the sensing reset control end is connected with the sensing reset control line OPDRST. The sensing reset control line OPDRST, the first reset control line RESET1, the second reset control line RESET2, and the third reset control line RESET3 can be configured to transmit different signals.

[0228] In some examples, the gate of the first compensation transistor PT2, the gate of the second reset transistor PT7, and the gate of the third reset transistor PT8 of the pixel driving circuit, and the gate of the second compensation transistor ST4 of the sensing driving circuit are all connected with the second reset control line RESET2. In other words, the second compensation control end, the first compensation control end, the second reset control end, and the third reset control end are all connected with the second reset control line RESET2, and are configured to receive the same signal.

[0229] The remaining circuit description of the composite driving circuit of the present example can refer to the description of the foregoing embodiments, and thus will not be described here again.

[0230] FIG. 17 is a working timing diagram of the composite driving circuit shown in FIG. 16. In some examples, the composite driving circuit can include 13 transistors (i.e., the transistors PT1 to PT9, and the transistors ST1 to ST4) and 3 capacitor units (i.e., the first capacitor C1, the second capacitor C2, and the voltage stabilizing capacitor C jOPD ). The types of the 13 transistors of the composite driving circuit can be the same, for example, all P-type transistors. However, the present embodiment is not limited thereto.

[0231] In some examples, as shown in FIG. 16, the composite driving circuit can be connected with 11 input terminals (i.e., data lines DL, scan lines GL, a first reset control line RESET1, a second reset control line RESET2, a third reset control line RESET3, a first initial signal line INIT1, a second initial signal line INIT2, a reference signal line REF, a light-emitting control line EML, a sensing reset signal line RSTL, a sensing reset control line OPDRST), 1 power supply terminal (i.e., a first power supply line VDDL), and 1 output terminal (i.e., a sensing read line SL). The light-emitting element EL and the photoelectric sensing element OPD can be connected with the second power supply line VSSL.

[0232] In some examples, as shown in FIG. 17, the pixel driving circuit 11 in a refresh frame can include a refresh reset phase A1, a pixel threshold compensation phase A2, a data writing phase A3, and a refresh light-emitting phase. The pixel driving circuit 11 in a holding frame can include a holding reset phase B1 and a holding light-emitting phase B2. The working timing of the pixel driving circuit 11 in the refresh frame and the holding frame can refer to the description of the foregoing embodiments, and will not be described here again.

[0233] In some examples, as shown in FIG. 17, the sensing reset phase S1 of the sensing driving circuit 12 can be located in the holding frame. For example, the sensing reset phase S1 can be performed synchronously with the holding reset phase B1 of the pixel driving circuit 11. The sensing phase can include a first sensing phase S21 and a second sensing phase S22, the first sensing phase S21 can be located before the sensing output phase S3, and the second sensing phase S22 can be located after the sensing reset phase S1. For example, the second sensing phase S22 can be synchronous with the holding light-emitting phase B2 of the pixel driving circuit 11 in the holding frame; the first sensing phase S21 can be synchronous with the refresh reset phase A1 and the threshold compensation phase A2 of the pixel driving circuit 11 in the refresh frame. The working timing of the sensing driving circuit can refer to the description of the foregoing embodiment shown in FIG. 11, and will not be described here again.

[0234] The pixel driving circuit 11 and the sensing driving circuit 12 of the present example can share the scan line GL, so that the data writing phase of the pixel driving circuit 11 and the sensing output phase of the sensing driving circuit 12 can be synchronous. The sensing driving circuit of the present example can perform threshold compensation on the first sensing node SN1 by setting the second compensation transistor, which can be beneficial to improve the sensing effect. Moreover, the sensing driving circuit 12 can keep the sensing phase in the holding frame, compared with the foregoing embodiments, the present example can increase the time length of the sensing phase of the sensing driving circuit.

[0235] In some examples, the types of all the transistors in the composite driving circuit in the foregoing embodiments can be the same, for example, all can be N-type transistors. In this case, the active level signal of the N-type transistor is high level; the active level signals of the first reset control signal, the second reset control signal, the third reset control signal, the scanning signal and the light-emitting control signal are all adjusted to high level.

[0236] In some examples, the types of some of the transistors in the composite driving transistor in the foregoing embodiments can be the same, for example, the first compensation transistor PT2, the first reset transistor PT1 and the sensing reset transistor ST2 can all be N-type transistors, and can be oxide thin film transistors, and the remaining transistors can be P-type transistors, wherein the first compensation control end can be configured to receive different signals from the second reset control end and the third reset control end. The active layer of the low temperature poly-silicon thin film transistor can be low temperature poly-silicon (LTPS, Low Temperature Poly-Silicon), and the active layer of the oxide thin film transistor can be oxide semiconductor (Oxide). The low temperature poly-silicon thin film transistor has the advantages of high mobility and fast charging, and the oxide thin film transistor has the advantage of low leakage current. Integrating the low temperature poly-silicon thin film transistor and the oxide thin film transistor on one display panel forms a low temperature polycrystalline oxide (LTPO, Low Temperature Polycrystalline Oxide) display panel, which can take advantage of both and reduce power consumption and improve display quality.

[0237] FIG. 18 is another structural schematic diagram of a pixel driving circuit according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 18, the pixel driving circuit can include a driving sub-circuit 111, a data writing sub-circuit 112, a compensation sub-circuit 113, a first storage sub-circuit 114, a third storage sub-circuit 116, a first reset sub-circuit 101, a second reset sub-circuit 102, a third reset sub-circuit 103, a fifth reset sub-circuit 105, a first light-emitting control sub-circuit 106 and a second light-emitting control sub-circuit 107.

[0238] In some examples, the first reset sub-circuit 101 can be connected with a first reset control terminal SW-RESET1, a first initial signal line INIT1 and a first pixel node PN1, and be configured to write, under control of the first reset control terminal SW-RESET1, a first initial signal provided by the first initial signal line INIT1 to the first pixel node PN1 to reset the first pixel node PN1. The second reset sub-circuit 102 can be connected with a second reset control terminal SW-RESET2, a second initial signal line INIT2 and a fifth pixel node PN5, and be configured to write, under control of the second reset control terminal SW-RESET2, a second initial signal provided by the second initial signal line INIT2 to the fifth pixel node PN5 to reset the fifth pixel node PN5. The third reset sub-circuit 103 can be connected with a third reset control terminal SW-RESET3, a third initial signal line INIT3 and a second pixel node PN2, and be configured to write, under control of the third reset control terminal SW-RESET3, a third initial signal provided by the third initial signal line INIT3 to the second pixel node PN2 to initialize the second pixel node PN2. The fifth reset sub-circuit 105 can be connected with a fifth reset control terminal SW-RESET5, the second pixel node PN2 and a fourth pixel node PN4, and be configured to conduct, under control of the fifth reset control terminal SW-RESET5, the second pixel node PN2 and the fourth pixel node PN4.

[0239] In some examples, the driving sub-circuit 111 can be connected with the first pixel node PN1, the second pixel node PN2 and a third pixel node PN3, and be configured to generate, under control of the first pixel node PN1, a driving signal for driving the light emitting element EL to emit light. The data writing sub-circuit 112 can be connected with a data line DL, a sixth pixel node PN6 and a scan terminal GATE, and be configured to write, under control of the scan terminal GATE, a data signal provided by the data line DL to the sixth pixel node PN6. The first compensation transistor 113 can be connected with the first pixel node PN1, the third pixel node PN3 and a first compensation control terminal CMP1, and be configured to conduct, under control of the first compensation control terminal CMP1, the first pixel node PN1 and the third pixel node PN3 to write a threshold voltage of the driving sub-circuit 111 to the first pixel node PN1.

[0240] In some examples, the first storage sub-circuit 114 can be connected with the first pixel node PN1 and the sixth pixel node PN6, and be configured to store a potential of the first pixel node PN1. The third storage sub-circuit 116 can be connected with the sixth pixel node PN6 and a first power terminal VDD1, and be configured to maintain a potential of the sixth pixel node PN6.

[0241] In some examples, the first light emitting control sub-circuit 106 can be connected with the second pixel node PN2, the light emitting control end EM, and the first power supply end VDD1, and configured to turn on the second pixel node PN2 and the first power supply end VDD1 under the control of the light emitting control end EM. The second light emitting control sub-circuit 107 can be connected with the third pixel node PN3, the fourth pixel node PN4, and the light emitting control end, and configured to turn on the third pixel node PN3 and the fifth pixel node PN5 under the control of the light emitting control end EM.

[0242] FIG. 19 is another equivalent circuit diagram of a pixel driving circuit according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 19, the pixel driving circuit of the present example can be a 9T2C structure, including nine transistors and two capacitors. Among them, the driving sub-circuit 111 can include a driving transistor PT3; the data writing sub-circuit 112 can include a data writing transistor PT4; the first compensation sub-circuit 113 can include a first compensation transistor PT2; the first reset sub-circuit 101 can include a first reset transistor PT1; the second reset sub-circuit 102 can include a second reset transistor PT7; the third reset sub-circuit 103 can include a third reset transistor PT8; the fifth reset sub-circuit 105 can include a fifth reset transistor PT10; the first light emitting control sub-circuit 106 can include a first light emitting control transistor PT5; the second light emitting control sub-circuit 107 can include a second light emitting control transistor PT6; the first storage sub-circuit 114 can include a first capacitor C1; and the third storage sub-circuit 116 can include a third capacitor C3.

[0243] In some examples, the gate of the driving transistor PT3 is connected with the first pixel node PN1, the first pole of the driving transistor PT3 is connected with the second pixel node PN2, and the second pole of the driving transistor PT3 is connected with the third pixel node PN3. The driving transistor PT3 can determine the size of the driving signal according to the voltage difference between its gate and first pole.

[0244] In some examples, the gate of the data writing transistor PT4 is connected with the scanning end GATE, the first pole of the data writing transistor PT4 is connected with the data line DL, and the second pole of the data writing transistor PT4 is connected with the sixth pixel node PN6. When the data writing transistor PT4 is turned on by the driving signal applied to the scanning end GATE, the data writing transistor PT4 writes the data signal provided by the data line DL to the sixth pixel node PN6. In the present example, the sixth pixel node PN6 is a data writing node.

[0245] In some examples, a gate of the first compensation transistor PT2 is connected with the first compensation control end CMP1, a first electrode of the first compensation transistor PT2 is connected with the third pixel node PN3, and a second electrode of the first compensation transistor PT2 is connected with the first pixel node PN1. When a conduction signal is applied to the first compensation control end CMP1, the first compensation transistor PT2 turns on the first pixel node PN1 and the third pixel node PN3.

[0246] In some examples, a first electrode of the first capacitor C1 is connected with the first pixel node PN1, and a second electrode of the first capacitor C1 is connected with the sixth pixel node PN6. A first electrode of the third capacitor C3 is connected with the first power supply end VDD1, and a second electrode of the third capacitor C3 is connected with the sixth pixel node PN6.

[0247] In some examples, a gate of the first reset transistor PT1 is connected with the first reset control end SW-RESET1, a first electrode of the first reset transistor PT1 is connected with the first initial signal line INIT1, and a second electrode of the first reset transistor PT1 is connected with the first pixel node PN1. When a conduction signal is applied to the first reset control end SW-RESET1, the first reset transistor PT1 writes a first initial signal transmitted by the first initial signal line INIT1 into the first pixel node PN1 to realize initialization of the first pixel node PN1.

[0248] In some examples, a gate of the second reset transistor PT7 is connected with the second reset control end SW-RESET2, a first electrode of the second reset transistor PT7 is connected with the second initial signal line INIT2, and a second electrode of the second reset transistor PT7 is connected with the fifth pixel node PN5. When a conduction signal is applied to the second reset control end SW-RESET2, the second reset transistor PT7 writes a second initial signal transmitted by the second initial signal line INIT2 into the fifth pixel node PN5 to realize initialization of the fifth pixel node PN5.

[0249] In some examples, a gate of the third reset transistor PT8 is connected with the third reset control end SW-RESET3, a first electrode of the third reset transistor PT8 is connected with the third initial signal line INIT3, and a second electrode of the third reset transistor PT8 is connected with the second pixel node PN2. When a conduction signal is applied to the third reset control end SW-RESET3, the third reset transistor PT8 writes a third initial signal transmitted by the third initial signal line INIT3 into the second pixel node PN2 to realize initialization of the second pixel node PN2.

[0250] In some examples, the gate of the fifth reset transistor PT10 is connected with the fifth reset control terminal SW-RESET5, the first electrode of the fifth reset transistor PT10 is connected with the second pixel node PN2, and the second electrode of the fifth reset transistor PT10 is connected with the sixth pixel node PN6. When a conductive signal is applied to the fifth reset control terminal SW-RESET5, the fifth reset transistor PT10 can conduct the second pixel node PN2 and the sixth pixel node PN6.

[0251] In some examples, the plurality of pixel nodes of the pixel driving circuit can include a first pixel node PN1, a second pixel node PN2, a third pixel node PN3, a fifth pixel node PN5, and a sixth pixel node PN6. The sixth pixel node PN6 can serve as a data writing node, and the fifth pixel node PN5 can serve as a light emitting element reset node.

[0252] In some examples, the first pixel node PN1 can be a connection point of the second electrode of the first reset transistor PT1, the second electrode of the first compensation transistor PT2, the gate of the driving transistor PT3, and the first electrode of the first capacitor C1. The second pixel node PN2 can be a connection point of the second electrode of the data writing transistor PT4, the first electrode of the driving transistor PT3, the first electrode of the fifth reset transistor PT10, and the second electrode of the first light emitting control transistor PT5. The third pixel node PN3 can be a connection point of the second electrode of the driving transistor PT3, the first electrode of the first compensation transistor PT2, and the first electrode of the second light emitting control transistor PT6. The fifth pixel node PN5 can be a connection point of the second electrode of the second light emitting control transistor PT6, the second electrode of the second reset transistor PT7, and the first light emitting electrode of the light emitting element EL. The sixth pixel node PN6 can be a connection point of the second electrode of the first capacitor C1, the second electrode of the data writing transistor PT4, the second electrode of the fifth reset transistor PT10, and the second electrode of the third capacitor C3.

[0253] FIG. 19 shows an exemplary structure of the driving sub-circuit 111, the first compensation sub-circuit 113, the data writing sub-circuit 112, the first storage sub-circuit 114, the third storage sub-circuit 116, the first light emitting control sub-circuit 106, the second light emitting control sub-circuit 107, the first reset sub-circuit 101, the second reset sub-circuit 102, the third reset sub-circuit 103, and the fifth reset sub-circuit 105. It is easy for those skilled in the art to understand that the implementation of the above-mentioned sub-circuits is not limited thereto as long as the functions thereof can be realized.

[0254] FIG. 20 is another equivalent circuit diagram of the composite driving circuit according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 20, the composite driving circuit can include a pixel driving circuit 11 and a sensing driving circuit 12. The pixel driving circuit 11 can include a driving transistor PT3, a data writing transistor PT4, a first compensation transistor PT2, a first reset transistor PT1, a second reset transistor PT2, a third reset transistor PT8, a fifth reset transistor PT10, a first light emitting control transistor PT5, a second light emitting control transistor PT6, a first capacitor C1, and a third capacitor C3. The sensing driving circuit 12 can include a sensing transistor ST1, a sensing reset transistor ST2, a sensing output transistor ST3, and a voltage stabilizing capacitor C jOPD .

[0255] In some examples, the gate of the data writing transistor PT4 is connected with the scan line GL, and the gate of the sensing output transistor ST3 is connected with the scan line GL. In other words, the scan end and the sensing output control end are both connected with the scan line GL, and are configured to receive the same scan signal.

[0256] In some examples, the gate of the first compensation transistor PT2 and the gate of the first reset transistor PT1 are both connected with the second reset control line RESET2. In other words, the first compensation control end and the first reset control end are both connected with the second reset control line RESET2, and are configured to receive the same signal.

[0257] In some examples, the gate of the third reset transistor PT8 is connected with the fifth reset control line RESET5, the gate of the second reset transistor PT7 is connected with the fourth reset control line RESET4, and the gate of the fifth reset transistor PT10 is connected with the sixth reset control line RESET6. In other words, the third reset control end can be connected with the fifth reset control line RESET5, the second reset control end can be connected with the fourth reset control line RESET4, and the fifth reset control end can be connected with the sixth reset control line RESET6. The gate of the sensing reset transistor ST2 can be connected with the sensing reset control end SW-RST. For example, the sensing reset control end SW-RST can be connected with the fifth reset control line RESET5. However, the present embodiment is not limited thereto. In other examples, the sensing reset control end SW-RST can be connected with the second reset control line RESET2, the fourth reset control line RESET4, or the sixth reset control line RESET6.

[0258] The remaining circuit description of the composite driving circuit of the present example can refer to the description of the foregoing embodiments, and thus will not be described here again.

[0259] FIG. 21 is a timing diagram of the operation of the composite driving circuit shown in FIG. 20. This example is described with the sensing reset control terminal SW-RST connected to the fifth reset control line RESET5. In some examples, the composite driving circuit can include 12 transistors (i.e., transistors PT1-PT9 and transistors ST1-ST3) and 3 capacitor units (i.e., the first capacitor C1, the second capacitor C2, and the voltage stabilizing capacitor C jOPD ). The 12 transistors of the composite driving circuit can be of the same type, e.g., all P-type transistors. However, the present embodiments are not limited thereto.

[0260] In some examples, as shown in FIG. 20, the composite driving circuit can be connected to 11 input terminals (i.e., the data line DL, the scan line GL, the second reset control line RESET2, the fourth reset control line RESET4, the fifth reset control line RESET5, the sixth reset control line RESET6, the first initial signal line INIT1, the second initial signal line INIT2, the third signal line INIT3, the emission control line EML, and the sensing reset signal line RSTL), 1 power supply terminal (i.e., the first power supply line VDDL), and 1 output terminal (i.e., the sensing read line SL). The light emitting element EL and the photoelectric sensing element OPD can both be connected to the second power supply line VSSL.

[0261] In some examples, as shown in FIG. 21, the pixel driving circuit 11 in a refresh frame can include a refresh reset phase A1, a threshold compensation phase A2, a data write phase A3, and a refresh emission phase A4. The pixel driving circuit 11 in a hold frame can include a hold reset phase B1 and a hold emission phase B2. The sensing driving circuit 12 in a refresh frame can include a sensing reset phase S1, a sensing phase S2, and a sensing output phase S3. In this example, the sensing driving circuit 12 can maintain the sensing phase after initializing the first sensing node in a hold frame.

[0262] In the refresh reset phase A1, the fifth reset control line RESET5 provides a low-level fifth reset control signal, and the sixth reset control line RESET6 provides a low-level sixth reset control signal; the scan line GL provides a high-level scan signal, the emission control line EML provides a high-level emission control signal, the second reset control line RESET2 provides a high-level second reset control signal, and the fourth reset control line RESET2 provides a high-level fourth reset control signal.

[0263] The fifth reset control signal provided by the fifth reset control line RESET5 is low, and the third reset transistor PT8 and the sensing reset transistor ST2 are both turned on. The third reset transistor PT8 is turned on, and the third initial signal provided by the third initial signal line INIT3 is written into the second pixel node N2, and the second pixel node PN2 is initialized. The sensing reset signal transmitted by the sensing reset signal line RSTL is provided to the first sensing node SN1 through the turned-on sensing reset transistor ST2, and the first sensing node SN1 is initialized. The sensing reset stage S1 of the sensing driving circuit is synchronized with the refresh reset stage S1.

[0264] The sixth reset control signal provided by the sixth reset control line RESET6 is low, and the fifth reset transistor PT10 is turned on to turn on the second pixel node PN2 and the sixth pixel node PN6, and the third initial signal is used to initialize the sixth pixel node PN6.

[0265] The second reset control signal provided by the second reset control line RESET2 is high, and the first reset transistor PT1 and the first compensation transistor PT2 are both turned off. The fourth reset control signal provided by the fourth reset control line RESET4 is high, and the second reset transistor PT7 is turned off. The scan signal provided by the scan line GL is high, and the data write transistor PT4 and the sensing output transistor ST3 are both turned off. The emission control signal provided by the emission control line EML is high, and the first emission control transistor PT5 and the second emission control transistor PT6 are both turned off.

[0266] In the threshold compensation stage A2, the sixth reset control signal provided by the sixth reset control line RESET6 is low, the second reset control signal provided by the second reset control line RESET2 is low, and the fourth reset control signal provided by the fourth reset control line RESET4 is low; the fifth reset control signal provided by the fifth reset control line RESET5 is high, the scan signal provided by the scan line GL is high, and the emission control signal EML is high.

[0267] The sixth reset control signal provided by the sixth reset control line RESET6 is low, and the fifth reset transistor PT10 is turned on to turn on the second pixel node PN2 and the sixth pixel node PN6, and is used to maintain the potential of the second pixel node PN2.

[0268] The second reset control signal provided by the second reset control line RESET2 is low, and the first compensation transistor PT2 and the first reset transistor PT1 are both turned on. The first reset transistor PT1 is turned on, and the first initial signal provided by the first initial signal line INIT1 is written into the first pixel node N1, and the first pixel node PN1 is initialized. The first compensation transistor PT2 is turned on, and the first pixel node PN1 and the third pixel node PN3 can be turned on, and the threshold voltage of the driving transistor PT3 is written into the first pixel node PN1. The fourth reset control signal provided by the fourth reset control line RESET4 is low, and the second reset transistor PT7 is turned on, and the second initial signal provided by the second initial signal line INIT2 is written into the fifth pixel node N5, and the fifth pixel node PN5 is initialized.

[0269] The fifth reset control signal provided by the fifth reset control line RESET5 is high, and the third reset transistor PT8 and the sensing reset transistor ST2 are both turned off. The scan signal provided by the scan line GL is high, and the data writing transistor PT4 and the sensing output transistor ST3 are both turned off. The emission control signal provided by the emission control signal EML is high, and the first emission control transistor PT5 and the second emission control transistor PT6 can be turned off.

[0270] In the data writing stage A3, the scan signal provided by the scan line GL is low; the second reset control signal provided by the second reset control line RESET2 is high, the fourth reset control signal provided by the fourth reset control line RESET4 is high, the fifth reset control signal provided by the fifth reset control line RESET5 is high, and the sixth reset control signal provided by the sixth reset control line RESET6 is high.

[0271] The scan signal provided by the scan line GL is low, and the data writing transistor PT4 and the sensing output transistor ST3 are both turned on. The data writing transistor PT4 is turned on, and the data signal transmitted by the data line DL is written into the sixth pixel node PN6. The sensing output transistor ST3 is turned on, and the sensing signal generated by the sensing transistor ST2 can be provided to the sensing reading line SL through the turned-on sensing output transistor ST3. The data writing process of the pixel driving circuit in the present example can be synchronized with the sensing signal output process of the sensing driving circuit.

[0272] The stage after the sensing reset transistor ST1 is turned off and before the sensing output transistor ST3 is turned on is the sensing stage S2. In the sensing stage S2, the photoelectric sensing element OPD can write the photoelectric conversion signal generated by the sensing into the first sensing node SN1, and the voltage stabilizing capacitor C jOPDThe photoelectric conversion signal written to the first sensing node SN1 can be stored. In response to a change in the potential of the first sensing node SN1, the sensing transistor ST1 is turned on, and a corresponding sensing signal can be generated based on the size of the photoelectric conversion signal, which can be written to the second sensing node SN2.

[0273] In the refresh light emitting phase A4, the light emitting control line EML provides a low-level light emitting control signal; the scan line GL provides a high-level scan signal, the second reset control line RESET2 provides a high-level second reset control signal, the fourth reset control line RESET4 provides a high-level fourth reset control signal, the fifth reset control line RESET5 provides a high-level fifth reset control signal, and the sixth reset control line RESET6 provides a high-level sixth reset control signal.

[0274] The light emitting control signal provided by the light emitting control line EML is low, and the first light emitting control transistor PT5 and the second light emitting control transistor PT6 are both turned on. In the refresh light emitting phase A4, under the action of the first capacitor C1 and the third capacitor C3, the data signal can be written to the first pixel node PN1, and the first pixel node PN1 can record the data voltage and the threshold voltage at the same time. The driving transistor T3 is turned on, and the first power supply signal provided by the first power supply line VDDL can be provided to the light emitting element EL through the conductive first light emitting control transistor PT5, the driving transistor PT3 and the second light emitting control transistor PT6 to drive the light emitting element EL to emit light. In the refresh light emitting phase A4, the sensing driving circuit 12 can not work.

[0275] In some examples, in the holding reset phase B1 of the holding frame, the fifth reset control signal provided by the fifth reset control line RESET5 is low, the third reset transistor PT8 is turned on, and the second pixel node PN2 is initialized; the fourth reset control signal provided by the fourth reset control line RESET4 is low, the second reset transistor PT7 is turned on, and the fifth pixel node PN5 is initialized. In the holding reset phase B1, the potential of the first pixel node PN1 can be maintained by the first capacitor C1 and the third capacitor C3, so that the voltage of the first pixel node PN1 remains the same as that in the refresh light emitting phase A4 of the refresh frame, that is, the first pixel node PN1 can record the data voltage and the threshold voltage at the same time.

[0276] In the light emitting stage B2, the light emitting control signal provided by the light emitting control line EML is at a low level, and the first light emitting control transistor PT5 and the second light emitting control transistor PT6 are both turned on. In the light emitting stage B2, the potential of the first pixel node PN1 is maintained, and the threshold voltage and the data voltage written in the refresh frame are recorded at the same time. The driving transistor PT3 can be turned on to provide a driving signal to the light emitting element EL under the control of the first pixel node PT1, so as to drive the light emitting element EL to emit light.

[0277] The pixel driving circuit 11 and the sensing driving circuit 12 in the example can share the scan line GL and the fifth reset control line RESET5, so that the initialization process of the second pixel node PN2 by the pixel driving circuit 11 can be synchronized with the initialization process of the first sensing node SN1 by the sensing driving circuit 12, and the process of the pixel driving circuit 11 writing the data signal to the sixth pixel node PN6 can be synchronized with the process of the sensing driving circuit 12 reading the sensing signal from the sensing reading line SL, so as to reduce the display refresh time occupied by the sensing driving circuit 12 and improve the refresh rate of the display panel.

[0278] In other examples, the sensing reset control end SW-RST can be connected to the second reset control line RESET2, so that the threshold compensation process of the pixel driving circuit 11 can be synchronized with the initialization process of the first sensing node SN1 by the sensing driving circuit 12. The example can shorten the sensing stage time of the sensing driving circuit.

[0279] In other examples, the sensing reset control end SW-RST can be connected to the fourth reset control line RESET4, so that the initialization process of the fifth pixel node PN5 by the pixel driving circuit 11 can be synchronized with the initialization process of the first sensing node SN1 by the sensing driving circuit 12. In the holding frame stage, the sensing driving circuit 12 can initialize the first sensing node SN1 and then maintain the sensing stage, thereby increasing the sensing time.

[0280] In other examples, the sensing reset control end SW-RST can be connected to the sixth reset control line RESET6, so that the process of turning on the second pixel node PN2 and the sixth pixel node PN6 by the pixel driving circuit 11 can be synchronized with the initialization process of the first sensing node SN1 by the sensing driving circuit 12. The example can shorten the sensing time of the sensing driving circuit.

[0281] FIG. 22 is another equivalent circuit diagram of the composite driving circuit according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 22, the composite driving circuit can include a pixel driving circuit 11 and a sensing driving circuit 12. The pixel driving circuit 11 can include a driving transistor PT3, a data writing transistor PT4, a first compensation transistor PT2, a first reset transistor PT1, a second reset transistor PT2, a third reset transistor PT8, a fifth reset transistor PT10, a first light emitting control transistor PT5, a second light emitting control transistor PT6, a first capacitor C1, and a third capacitor C3. The sensing driving circuit 12 can include a sensing transistor ST1, a sensing reset transistor ST2, a sensing output transistor ST3, a second compensation transistor ST4, and a voltage stabilizing capacitor C jOPD .

[0282] In some examples, the gate of the first compensation transistor PT2, the gate of the first reset transistor PT1, and the gate of the second compensation transistor ST4 are all connected with the second reset control line RESET2. In other words, the first compensation control terminal, the first reset control terminal, and the second compensation control terminal are all connected with the second reset control line RESET2 and are configured to receive the same signal.

[0283] In some examples, the gate of the third reset transistor PT8 and the gate of the sensing reset transistor ST2 are both connected with the fifth reset control line RESET5. In other words, the third reset control terminal and the sensing reset control terminal can both be connected with the fifth reset control line RESET5 and configured to receive the same signal.

[0284] The pixel driving circuit 11 and the sensing driving circuit 12 of the present example can share the scan line GL and the fifth reset control line RESET5, so that the initialization process of the pixel driving circuit 11 to the second pixel node PN2 can be synchronized with the initialization process of the sensing driving circuit 12 to the first sensing node SN1, and the process of the pixel driving circuit 11 to write the data signal to the sixth pixel node PN6 can be synchronized with the process of the sensing driving circuit 12 to read the sensing signal from the sensing read line SL, which can reduce the display refresh time occupied by the sensing driving circuit 12 and is conducive to improving the refresh rate of the display panel. Moreover, the sensing driving circuit of the present example can perform threshold compensation on the first sensing node SN1 by setting the second compensation transistor, which can be conducive to improving the sensing effect. The remaining circuit description and working timing of the composite driving circuit of the present example can refer to the description of the foregoing embodiments, and thus will not be described here again.

[0285] FIG. 23 is another equivalent circuit diagram of the composite driving circuit according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 23, the composite driving circuit can include a pixel driving circuit 11 and a sensing driving circuit 12. The pixel driving circuit 11 can include a driving transistor PT3, a data writing transistor PT4, a first compensation transistor PT2, a first reset transistor PT1, a second reset transistor PT2, a third reset transistor PT8, a fifth reset transistor PT10, a first light emitting control transistor PT5, a second light emitting control transistor PT6, a first capacitor C1, and a third capacitor C3. The sensing driving circuit 12 can include a sensing transistor ST1, a sensing reset transistor ST2, a sensing output transistor ST3, and a voltage stabilizing capacitor C jOPD .

[0286] In some examples, the gate of the data writing transistor PT4 is connected with a scan line GL, and the gate of the sensing output transistor ST3 is connected with a sensing output control terminal SENSE. The scan line GL and the sensing output control terminal SENSE can be configured to receive different signals.

[0287] In some examples, the gate of the first compensation transistor PT2, the gate of the first reset transistor PT1, and the gate of the second compensation transistor ST4 are all connected with a second reset control line RESET2. In other words, the first compensation control terminal, the first reset control terminal, and the second compensation control terminal are all connected with the second reset control line RESET2 and configured to receive the same signal.

[0288] In some examples, the gate of the third reset transistor PT8 and the gate of the sensing reset transistor ST2 are both connected with a fifth reset control line RESET5. In other words, the third reset control terminal and the sensing reset control terminal can both be connected with the fifth reset control line RESET5 and configured to receive the same signal. However, the present embodiment is not limited thereto. In other examples, the gate of the sensing reset transistor ST2 can be connected with the second reset control line RESET2, the fourth reset control line RESET4, the sixth reset control line RESET5, the scan line GL, or the light emitting control line EML.

[0289] The remaining circuit descriptions of the composite driving circuit of the present example can refer to the descriptions of the foregoing embodiments, and thus will not be described again here.

[0290] FIG. 24 is a timing diagram of the composite driving circuit shown in FIG. 23. In some examples, the composite driving circuit can include 13 transistors (i.e., transistors PT1 to PT9 and transistors ST1 to ST4) and 3 capacitor units (i.e., the first capacitor C1, the second capacitor C2, and the voltage stabilizing capacitor C jOPD). The types of the 13 transistors of the composite driving circuit can be the same, for example, all P-type transistors. However, the present embodiment is not limited thereto.

[0291] In some examples, as shown in FIG. 23, the composite driving circuit can be connected with 11 input terminals (i.e., data lines DL, scan lines GL, a second reset control line RESET2, a fourth reset control line RESET4, a fifth reset control line RESET5, a sixth reset control line RESET6, a first initial signal line INIT1, a second initial signal line INIT2, a third signal line INIT3, an emission control line EML, and a sensing reset signal line RSTL), 1 power terminal (i.e., a first power line VDDL), and 1 output terminal (i.e., a sensing read line SL). The light emitting element EL and the optoelectric sensing element OPD can both be connected with the second power line VSSL.

[0292] In some examples, as shown in FIG. 24, the pixel driving circuit 11 in a refresh frame can include a refresh reset phase A1, a threshold compensation phase A2, a data write phase A3, and a refresh emission phase A4. The pixel driving circuit 11 in a holding frame can include a holding reset phase B1 and a holding emission phase B2. The sensing driving circuit 12 can include a sensing reset phase S1, a sensing phase S2, and a sensing output phase S3. The sensing reset phase S1 of the sensing driving circuit 12 can be synchronized with the refresh reset phase A1 of the pixel driving circuit 11, and the sensing output phase S3 can be located in the holding emission phase B2 of the holding frame. The time duration between the sensing reset phase S1 and the sensing output phase S3 is the sensing phase S2, thereby increasing the sensing time duration. The remaining working timing descriptions of the composite driving circuit of the present example can refer to the descriptions of the foregoing embodiments, which will not be repeated here.

[0293] The sensing output control terminals of the sensing driving circuit of the present example can be controlled individually, and the sensing signal reading is performed by using the holding frame, which is conducive to increasing the sensing time duration and improving the light sensing amount.

[0294] In other examples, the types of all the transistors included in the composite driving circuit of the foregoing embodiments can be the same, for example, all N-type transistors. Alternatively, the types of some of the transistors included in the composite driving circuit of the foregoing embodiments can be the same. For example, the first compensation transistor PT2, the first reset transistor PT1, and the second compensation transistor ST4 can all be N-type transistors, and the remaining transistors can be P-type transistors; or the first compensation transistor PT2, the first reset transistor PT1, the second compensation transistor ST4, the sensing reset transistor ST2, and the third reset transistor PT3 can all be N-type transistors, and the remaining transistors can all be P-type transistors.

[0295] In some examples, the threshold compensation stage and the data writing stage of the pixel driving circuit can be separated. The reset process of the first sensing node by the sensing driving circuit can be synchronized with the reset process of the second pixel node, the first pixel node, or the fifth pixel node by the pixel driving circuit, the threshold compensation process of the first sensing node by the sensing driving circuit can be synchronized with the threshold compensation process of the first pixel node by the pixel driving circuit, and the process of reading the sensing signal by the sensing driving circuit can be synchronized with the process of writing the data signal by the pixel driving circuit. The present embodiment is not limited to the combination of the foregoing embodiments.

[0296] FIG. 25 is another equivalent circuit diagram of the composite driving circuit according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 25, the composite driving circuit can include a pixel driving circuit 11 and a sensing driving circuit 12. The pixel driving circuit 11 can include a driving transistor PT3, a data writing transistor PT4, a first compensation transistor PT2, a first reset transistor PT1, a second reset transistor PT2, a third reset transistor PT8, a fourth reset transistor PT9, a first light emitting control transistor PT5, a second light emitting control transistor PT6, a first capacitor C1, and a second capacitor C2. The sensing driving circuit 12 can include a sensing transistor ST1, a sensing reset transistor ST2, a sensing output transistor ST3, and a voltage stabilizing capacitor C jOPD .

[0297] In some examples, the first light emitting electrode of the light emitting element EL can be connected with the first power supply line VDDL, and the second light emitting electrode can be connected with the fifth pixel node PN5. The gate of the first light emitting control transistor PT5 can be connected with the light emitting control line EML, the first electrode can be connected with the second pixel node PN2, and the second electrode can be connected with the fifth pixel node PN5. The gate of the second light emitting control transistor PT6 can be connected with the light emitting control line EML, the first electrode can be connected with the second power supply line VSSL, and the second electrode can be connected with the third pixel node PN3. The driving transistor PT3 of the present example can be configured to provide a driving signal to the second light emitting electrode of the light emitting element EL.

[0298] In some examples, the sensing reset control terminal SW-RST can be connected with the first reset control line RESET1 or the second reset control line RESET2, or can be separately provided. The sensing output control terminal SENSE can be connected with the scan line GL, or can be separately provided.

[0299] In some examples, the first sensing electrode of the optoelectric sensing element OPD can be connected with the first sensing node SN1, and the second sensing electrode can be connected with the second power supply line VSSL. The present embodiment is not limited thereto. In other examples, the first sensing electrode of the optoelectric sensing element OPD can be connected with the first power supply line VDDL, and the second sensing electrode can be connected with the first sensing node SN1.

[0300] The remaining circuit description and working timing of the composite driving circuit of the present example can refer to the description of the foregoing embodiments, and thus will not be described here again.

[0301] The present embodiment also provides a driving method of a composite driving circuit, which is applied to the composite driving circuit as described above. The driving method can include: the pixel driving circuit performing reset on at least one pixel node in the plurality of pixel nodes under the control of at least one reset control terminal in the plurality of reset control terminals, writing a data signal provided by a data line into one of the pixel nodes as a data writing node under the control of the scan terminal, and generating a driving signal for driving the at least one light emitting element to emit light according to the data signal; and the sensing driving circuit performing reset on the first sensing node under the control of the sensing reset control terminal, generating a sensing signal according to the photoelectric conversion signal written into the first sensing node by the at least one photoelectric sensing element, and providing the sensing signal written into the second sensing node to the sensing read line under the control of the sensing output control terminal. When the sensing reset control terminal is configured to receive the same signal as one of the plurality of reset control terminals, the composite driving circuit synchronously performs reset on the at least one pixel node and the first sensing node. When the sensing output control terminal is configured to receive the same signal as the scan terminal, the composite driving circuit synchronously writes the data signal into the data writing node and outputs the sensing signal from the sensing read line.

[0302] In the present embodiment, the pixel driving circuit and the sensing driving circuit can multiplex part of the signals, so as to reduce the occupation of the display refresh time of the display panel by the sensing and data readout time length of the photoelectric sensing element, thereby improving the refresh rate of the display panel.

[0303] In some example embodiments, the driving method can further include: the pixel driving circuit writing the threshold voltage of the driving sub-circuit into the first pixel node under the control of the first compensation control terminal; and the sensing driving circuit writing the threshold voltage of the sensing sub-circuit into the first sensing node under the control of the second compensation control terminal. The first compensation control terminal and the second compensation control terminal are configured to receive the same signal as one of the plurality of reset control terminals.

[0304] In some example embodiments, the first compensation control terminal and the scan terminal are configured to receive different signals. The pixel driving circuit performs writing of the data signal into the data writing node and writing of the threshold voltage of the driving sub-circuit into the first pixel node in steps. The present example separates the data writing process and the threshold voltage compensation process of the pixel driving circuit, so as to achieve sufficient compensation of the threshold voltage, thereby facilitating the realization of a higher refresh rate.

[0305] In some example embodiments, when the pixel driving circuit writes the threshold voltage of the driving sub-circuit to the first pixel node, the sensing driving circuit synchronously performs writing the photoelectric conversion signal according to the at least one photoelectric sensing element to the first sensing node to generate the sensing signal. In this example, the sensing driving circuit can generate the sensing signal synchronously during the threshold voltage writing process of the driving sub-circuit, which is beneficial to increase the sensing time.

[0306] In some example embodiments, the driving period of the pixel driving circuit includes a refresh frame and a holding frame. In the refresh frame, the pixel driving circuit resets at least one of the plurality of pixel nodes under the control of at least one of the plurality of reset control terminals, and the sensing driving circuit resets the first sensing node; in the holding frame, the pixel driving circuit generates a driving signal for driving at least one light emitting element to emit light according to the data signal written in the refresh frame, and the sensing driving circuit outputs the sensing signal from the sensing read line; after the sensing driving circuit resets the first sensing node and before the sensing driving circuit outputs the sensing signal from the sensing read line, the sensing driving circuit generates the sensing signal according to the photoelectric conversion signal written by the at least one photoelectric sensing element to the first sensing node. For example, this example can refer to the description of the above-described embodiment shown in FIG. 24.

[0307] In some example embodiments, the driving period of the pixel driving circuit includes a refresh frame and a holding frame. In the holding frame, the pixel driving circuit resets at least one of the plurality of pixel nodes under the control of at least one of the plurality of reset control terminals, and the sensing driving circuit resets the first sensing node; in the refresh frame, the pixel driving circuit writes the data signal provided by the data line to one of the pixel nodes as a data writing node under the control of the scan terminal, and the sensing driving circuit outputs the sensing signal from the sensing read line; after the sensing driving circuit resets the first sensing node and before the sensing driving circuit outputs the sensing signal from the sensing read line, the sensing driving circuit generates the sensing signal according to the photoelectric conversion signal written by the at least one photoelectric sensing element to the first sensing node. For example, this example can refer to the description of the above-described embodiment shown in FIG. 17.

[0308] The detailed description of the driving method of the composite driving circuit provided in this example can refer to the description of the above-described embodiments, and thus will not be described here again.

[0309] The embodiment also provides a display panel, comprising: a substrate, a plurality of pixel driving circuits arranged on the substrate, a plurality of sensing driving circuits, a plurality of light-emitting elements, and a plurality of photoelectric sensing elements. At least one pixel driving circuit of the plurality of pixel driving circuits comprises a plurality of pixel nodes, and is connected with a scan end, a data line, a plurality of reset control ends, and at least one light-emitting element of the plurality of light-emitting elements, and is configured to reset at least one pixel node of the plurality of pixel nodes under control of at least one reset control end of the plurality of reset control ends; write a data signal provided by the data line into one pixel node serving as a data writing node under control of the scan end; and generate a driving signal for driving the at least one light-emitting element to emit light according to the data signal. At least one sensing driving circuit of the plurality of sensing driving circuits comprises a first sensing node and a second sensing node, and is connected with a sensing reset control end, a sensing output control end, a sensing reading line, and at least one photoelectric sensing element of the plurality of photoelectric sensing elements, and is configured to reset the first sensing node under control of the sensing reset control end; generate a sensing signal according to a photoelectric conversion signal written into the first sensing node by the at least one photoelectric sensing element; and provide the sensing signal written into the second sensing node to the sensing reading line under control of the sensing output control end. The display panel satisfies at least one of the following conditions: the sensing output control end connected with the at least one sensing driving circuit is configured to receive the same signal as the scan end connected with the at least one pixel driving circuit; and the sensing reset control end connected with the at least one sensing driving circuit is configured to receive the same signal as one reset control end of the plurality of reset control ends connected with the at least one pixel driving circuit.

[0310] The display panel of the embodiment can integrate display and optical sensing functions, and the pixel driving circuit and the sensing driving circuit can multiplex part of signals, so that the display refresh time of the display panel occupied by the sensing and data reading time of the photoelectric sensing element is reduced, and the refresh rate of the display panel is improved.

[0311] The display panel of the embodiment is described below by way of examples.

[0312] FIG. 26 is a schematic diagram of a display panel according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 26, the display panel can include an active area AA and a bezel area BB surrounding the active area AA. The active area AA can be rectangular, such as a rounded rectangular. The active area AA can include a first area A1, a second area A2, a third area A3, and a fourth area A4. In other examples, the active area AA can be circular, elliptical, polygonal, or other shapes. In other examples, the active area AA can include a portion of the first area A1, the second area A2, the third area A3, and the fourth area A4.

[0313] In some examples, the first area A1 can be a camera under display area. For example, a camera in a front projection of the display panel can at least partially overlap the first area A1. The first area A1 can be located in a top middle region of the active area AA. The first area A1 can be circular or rectangular. The first area A1 can be a light-transmissive area so that a camera under the display panel receives light. In other examples, the first area A1 can be located in a middle region of the active area AA or can be located in a top left corner or a top right corner of the active area AA, or other regions.

[0314] In some examples, the second area A2 can be an infrared sensor area. The second area A2 can be located on a side of the first area A1 along a first direction D1. For example, an infrared sensor, such as an ambient light sensor, in a front projection of the display panel can be located at least in the second area A2. In other examples, the second area A2 can be located on a side of the first area A1 along a second direction D2.

[0315] In some examples, the third area A3 can be a fingerprint sensing area. The third area A3 can be located in a lower middle region of the active area AA. The third area A3 can be substantially rectangular, such as a rounded rectangular. In other examples, the third area A3 can be located in a middle region of the active area AA or can be located in a lower left corner or a lower right corner of the active area AA, or other regions.

[0316] In some examples, the fourth area A4 can be a touch sensing area. The fourth area A4 can include all areas in the active area AA except the first area A1, the second area A2, and the third area A3.

[0317] In some examples, the light emitting elements can be distributed across the entire active area AA, such that the active area AA implements a display function. The optoelectronic sensing elements can be distributed across a partial area of the active area AA, and optical sensing can be performed in the partial area where the optoelectronic sensing elements are distributed. For example, the optoelectronic sensing elements can be arranged in the second area A2, such as to replace an under-display sensing sensor, for implementing a sensing function; or the optoelectronic sensing elements can be arranged in the third area A3, for performing fingerprint recognition. In other examples, the optoelectronic sensing elements can be distributed across the entire active area AA, and optical sensing can be performed across the entire active area AA, such as to implement full-screen fingerprint recognition or to implement a touch function.

[0318] In some examples, the display panel integrating display and optoelectronic sensing functions can implement full-screen fingerprint recognition, and can be applied to smart home devices (such as smart door locks) or vehicle-mounted devices, etc. Alternatively, the display panel can implement blood information, blood oxygen, etc. signal acquisition and analysis by integrating optoelectronic sensing functions, and can be applied to portable devices (such as wristbands, tablets, etc.) in the field of smart medical treatment. Alternatively, the display panel can implement ambient light (such as infrared, near-infrared band) photosensing by integrating optoelectronic sensing functions, and can be used for dynamic dimming by extracting information.

[0319] FIG. 27 is a schematic diagram of an arrangement of light emitting elements and optoelectronic sensing elements according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 27, the plurality of light emitting elements of the display panel can be divided into a plurality of display units PX. The plurality of display units PX can be arranged in an array along a first direction D1 and a second direction D2. The first direction D1 intersects the second direction D2, for example, the first direction D1 can be perpendicular to the second direction D2.

[0320] In some examples, each display unit PX can include one light emitting element EL1 emitting first color light, one light emitting element EL2 emitting second color light, and one light emitting element EL3 emitting third color light. Within the display unit PX, the light emitting element EL1 emitting first color light and the light emitting element EL2 emitting second color light can be arranged in sequence along the first direction D1, and the light emitting element EL3 emitting third color light can be located on the same side of the light emitting elements EL1 and EL2 along the second direction D2, and can be arranged in a staggered manner with the light emitting elements EL1 and EL2 along the second direction D2. For example, the first color light is red light, the second color light is blue light, and the third color light is green light. The light emitting element EL1 is a red light emitting element, the light emitting element EL2 is a blue light emitting element, and the light emitting element EL3 is a green light emitting element.

[0321] In some examples, the optoelectric sensing element OPD can be located between the light emitting elements EL3 emitting the third color light of adjacent display units PX along the first direction D1. Along the second direction D2, the plurality of optoelectric sensing elements OPD can be arranged in alignment. For example, along the first direction D1, the plurality of light emitting elements EL1 emitting the first color light and the plurality of light emitting elements EL2 emitting the second color light can be arranged in one-to-one spacing, and the plurality of light emitting elements EL3 emitting the third color light and the plurality of optoelectric sensing elements OPD can be arranged in one-to-one spacing; along the second direction D2, the plurality of light emitting elements EL1 emitting the first color light and the plurality of light emitting elements EL2 emitting the second color light can be arranged in one-to-one spacing, and the plurality of light emitting elements EL3 emitting the third color light can be arranged in alignment in sequence, and the plurality of optoelectric sensing elements OPD can be arranged in alignment in sequence.

[0322] In some examples, the size of the light emitting region of the light emitting element EL3 can be smaller than the size of the light emitting region of the light emitting elements EL1 and EL2. The size of the sensing region of the optoelectric sensing element OPD can be substantially the same as the size of the light emitting region of the light emitting element EL3. The light emitting region of the light emitting element can refer to the overlapping and contacting region of the first light emitting electrode, the light emitting functional layer and the second light emitting electrode of the light emitting element, and the size of the light emitting region can be determined by the size of the pixel opening of the corresponding light emitting element opened by the pixel defining layer. The sensing region of the optoelectric sensing element OPD can refer to the overlapping and contacting region of the first sensing electrode, the sensing functional layer and the second sensing electrode of the optoelectric sensing element, and the size of the sensing region can be determined by the size of the sensing opening of the corresponding optoelectric sensing element opened by the pixel defining layer.

[0323] In the present example, the size of A refers to the size of the orthographic projection of A on the substrate. When the orthographic projection of A on the substrate is rectangular, the size of A can include at least one of the following: the length of the orthographic projection of A on the substrate along the first direction, the length of the orthographic projection of A on the substrate along the second direction, the area of the orthographic projection of A on the substrate; wherein the first direction can be perpendicular to the second direction. When the orthographic projection of A on the substrate is circular or elliptical, the size of A can include at least one of the following: the radius of the orthographic projection of A on the substrate, the diameter of the orthographic projection of A on the substrate, the area of the orthographic projection of A on the substrate.

[0324] FIG. 28 is a schematic view of another arrangement of light emitting elements and photoelectric sensing elements according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 28, each display unit PX can include one light emitting element EL1 emitting light of a first color, one light emitting element EL2 emitting light of a second color, and two light emitting elements EL3a and EL3b emitting light of a third color. Within the display unit PX, the light emitting element EL1 emitting light of the first color and the light emitting element EL2 emitting light of the second color can be arranged in sequence along a first direction D1, the two light emitting elements EL3a and EL3b emitting light of the third color can be arranged in sequence along the first direction D1, and the two light emitting elements EL3a and EL3b emitting light of the third color can be located on the same side of the light emitting elements EL1 and EL2 along a second direction D2 and arranged staggered with the light emitting elements EL1 and EL2 along the second direction D2.

[0325] In some examples, a photoelectric sensing element OPD can be located between two adjacent light emitting elements EL3 emitting light of the third color. For example, a photoelectric sensing element OPD can be arranged between the two adjacent light emitting elements EL3a and EL3b along the first direction D1. Along the second direction D2, the photoelectric sensing elements OPD can be arranged spaced apart between the adjacent light emitting elements EL1 and EL2.

[0326] In some examples, the light emitting region of the light emitting element EL3 can have a size smaller than the light emitting regions of the light emitting elements EL1 and EL2. The sensing region of the photoelectric sensing element OPD can have a size smaller than the light emitting region of the light emitting element EL3. The arrangement of the present example can ensure RGBG

[0327] The arrangement of the light emitting elements and the photoelectric sensing elements of the present example can make full use of the arrangement space.

[0328] FIG. 29 is a schematic view of an arrangement of pixel driving circuits and sensing driving circuits according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 29, a plurality of pixel driving circuits 11 and a plurality of sensing driving circuits 12 can be arranged in an array along a first direction D1 and a second direction D2. The plurality of circuits arranged in alignment along the first direction D1 can be referred to as a row of circuits, and the plurality of circuits arranged in alignment along the second direction D2 can be referred to as a column of circuits. Among them, the plurality of pixel driving circuits 11 arranged in alignment along the second direction D2 can be referred to as a column of pixel driving circuits, and the plurality of sensing driving circuits 12 arranged in alignment along the second direction D2 can be referred to as a column of sensing driving circuits.

[0329] In some examples, along the first direction D1, the plurality of pixel driving circuits 11 and the plurality of sensing driving circuits 12 can be arranged in an interval manner. For example, m pixel driving circuits 11 can be arranged in an interval manner between n sensing driving circuits, where m and n are integers greater than 0, and m is greater than n. In this example, m can be 3, and n can be 1. Along the first direction D1, three columns of pixel driving circuits 11 can be arranged in an interval manner between one column of sensing driving circuits 12.

[0330] FIG. 30 is a schematic view of an arrangement of a pixel driving circuit, a sensing driving circuit, a light emitting element, and a photoelectric sensing element according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 30, the plurality of pixel driving circuits 11 can be connected to the plurality of light emitting elements one by one. The plurality of sensing driving circuits 12 can be connected to the plurality of photoelectric sensing elements OPD one by one. The arrangement of the plurality of light emitting elements and the plurality of photoelectric sensing elements can refer to the description of the arrangement of the light emitting elements and the photoelectric sensing elements according to the example shown in FIG. 27.

[0331] In some examples, as shown in FIG. 30, three pixel driving circuits 11 arranged in an interval manner along the first direction D1 can be connected to a light emitting element EL1 emitting a first color light, a light emitting element EL3 emitting a third color light, and a light emitting element EL2 emitting a second color light one by one. The light emitting elements and the connected pixel driving circuits 11 can at least partially overlap in the orthographic projection of the substrate. A photoelectric sensing element OPD arranged between adjacent display units along the first direction D1 can be connected to a sensing driving circuit 12 interpolated in the pixel driving circuits connected to the adjacent display units. The photoelectric sensing element OPD and the connected sensing driving circuit 12 can at least partially overlap in the orthographic projection of the substrate.

[0332] FIG. 31 is another schematic view of an arrangement of a pixel driving circuit, a sensing driving circuit, a light emitting element, and a photoelectric sensing element according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 31, the arrangement of the plurality of light emitting elements and the plurality of photoelectric sensing elements OPD can refer to the description of the arrangement of the light emitting elements and the photoelectric sensing elements according to the example shown in FIG. 27. The plurality of pixel driving circuits 11 can be connected to the plurality of light emitting elements one by one. At least one sensing driving circuit 12 can be connected to at least two photoelectric sensing elements OPD. For example, one sensing driving circuit 12 can be connected to two photoelectric sensing elements OPD adjacent along the first direction D1.

[0333] In this example, two photoelectric sensing elements share one sensing driving circuit, which can be beneficial to improve the arrangement density of the light emitting elements, and can be beneficial to improve the accumulation of the sensing signal and reduce the signal-to-noise ratio.

[0334] FIG. 32 is a schematic diagram of another arrangement of pixel driving circuits, sensing driving circuits, light emitting elements, and optoelectric sensing elements according to at least one embodiment of the present disclosure. In some examples, the arrangement of the plurality of light emitting elements and the plurality of optoelectric sensing elements OPD can refer to the description of the embodiment shown in FIG. 27. As shown in FIG. 32, the plurality of pixel driving circuits 11 can be connected to the plurality of light emitting elements one-to-one. At least one sensing driving circuit 12 can be connected to at least two optoelectric sensing elements OPD. For example, one sensing driving circuit 12 can be connected to four adjacent optoelectric sensing elements OPD. The four adjacent optoelectric sensing elements can include four optoelectric sensing elements OPD arranged as two rows and two columns. Since the plurality of optoelectric sensing elements share one sensing driving circuit, the number of sensing driving circuits inserted in the pixel driving circuit can be reduced. For example, the sensing driving circuits can be arranged alternately in rows.

[0335] The plurality of optoelectric sensing elements (such as four) sharing one sensing driving circuit in the present example can be beneficial to improve the arrangement density of the light emitting elements, and can be beneficial to improve the sensing signal accumulation amount and reduce the signal-to-noise ratio.

[0336] FIG. 33 is a schematic diagram of the wiring arrangement of pixel driving circuits and sensing driving circuits according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 33, the arrangement of the plurality of light emitting elements (including light emitting elements EL1, EL2, and EL3) and the plurality of optoelectric sensing elements OPD can refer to the description of the embodiment shown in FIG. 27. The plurality of pixel driving circuits 11 can be connected to the plurality of light emitting elements one-to-one. At least one sensing driving circuit 12 can be connected to at least two optoelectric sensing elements OPD. For example, one sensing driving circuit 12 can be connected to two optoelectric sensing elements OPD adjacent in the first direction D1.

[0337] In some examples, the plurality of pixel driving circuits 11 and the sensing driving circuits 12 in the same row can be connected to the same scan line (for example, scan lines GL(i), GL(i+1), i is an integer greater than 0). The plurality of pixel driving circuits 11 in the same column can be connected to the same data line (for example, data lines DL(j), DL(j+1), DL(j+2), DL(j+3), DL(j+4), DL(j+5), j is an integer greater than 0). The plurality of sensing driving circuits 12 in the same column can be connected to the same sensing read line (for example, sensing read line SL(k), k is an integer greater than 0). The plurality of optoelectric sensing elements OPD connected to the same sensing read line can serve as an effective sensing unit, and the effective sensing unit can output a sensing signal through the sensing read line. The arrangement of the present example can be beneficial to improve the sensing signal accumulation amount and reduce the signal-to-noise ratio, and can effectively utilize the arrangement space.

[0338] FIG. 34 is a schematic diagram of a partial cross-sectional view of a display panel according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 34, in a direction perpendicular to the display panel (e.g., a third direction D3), the display panel can include a substrate 200, a circuit structure layer 21, a functional structure layer 22, an encapsulation structure layer 23, and a color filter layer 24 disposed on the substrate 200 in sequence. The circuit structure layer 21 can include at least a plurality of pixel driving circuits and a plurality of sensing driving circuits, each of which can include a plurality of transistors and at least one capacitor. The functional structure layer 22 can include at least a plurality of light emitting elements EL and a plurality of optoelectric sensing elements OPD. The third direction D3 can be perpendicular to a plane in which the first direction D1 and the second direction D2 lie, and the first direction D1 and the second direction D2 can be parallel to a plane in which the substrate 200 lies.

[0339] In some examples, as shown in FIG. 34, the circuit structure layer 21 can include a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer, and a second source-drain metal layer disposed on the substrate 200. A first gate insulating layer 201 can be disposed between the semiconductor layer and the first gate metal layer, a second gate insulating layer 202 can be disposed between the first gate metal layer and the second gate metal layer, an interlayer insulating layer 203 can be disposed between the second gate metal layer and the first source-drain metal layer, a first planarization layer 204 can be disposed between the first source-drain metal layer and the second source-drain metal layer, and a second planarization layer 205 can be disposed on a side of the second source-drain metal layer away from the substrate 200. The first gate insulating layer 201, the second gate insulating layer 202, and the interlayer insulating layer 203 can be inorganic insulating layers, and the first planarization layer 204 and the second planarization layer 205 can be organic insulating layers. However, the present embodiments are not limited thereto. In other examples, a buffer layer can be disposed on a side of the semiconductor layer close to the substrate, which can prevent harmful substances in the substrate from invading the inside of the display panel and can increase the adhesion of the film layers in the display panel to the substrate. In other examples, a bottom shielding metal (BSM) layer can be disposed on a side of the buffer layer close to the substrate, which can be configured to at least partially cover the active layer of the thin film transistor of the driving circuit to avoid the influence of external light on the performance of the thin film transistor. In other examples, a passivation layer can be disposed between the first source-drain metal layer and the second source-drain metal layer, and the first planarization layer can be disposed on a side of the passivation layer close to the substrate 200.

[0340] The film layer structure of the circuit structure layer 21 is described below by taking one transistor PT and one capacitor PC of the pixel driving circuit and one transistor ST and one capacitor SC of the sensing driving circuit as examples. For example, the transistor PT can be the second reset transistor or the second light emitting control transistor in the pixel driving circuit, and the transistor ST can be the sensing reset transistor in the sensing driving circuit.

[0341] In some examples, the semiconductor layer can at least include: an active layer PT0 of the transistor PT and an active layer ST0 of the transistor ST. The active layer of each transistor can include: a first region, a second region, and a channel region between the first region and the second region. The first gate metal layer can at least include: a gate electrode PT03 of the transistor PT, a gate electrode ST03 of the transistor ST, a first electrode of the capacitor PC, and a first electrode of the capacitor SC. The gate electrode PT03 of the transistor PT can cover the channel region of the active layer PT0 in the orthographic projection of the substrate 200; the gate electrode ST03 of the transistor ST can cover the channel region of the active layer ST0 in the orthographic projection of the substrate 200. The second gate metal layer can at least include: a second electrode of the capacitor PC and a second electrode of the capacitor SC. The second electrode and the first electrode of the capacitor PC can at least partially overlap in the orthographic projection of the substrate 200, for example, the two can coincide. The second electrode and the first electrode of the capacitor SC can at least partially overlap in the orthographic projection of the substrate 200, for example, the two can coincide.

[0342] In some examples, the first source-drain metal layer can at least include: a first electrode PT01 and a second electrode PT02 of the transistor PT, and a first electrode ST01 and a second electrode ST02 of the transistor ST. The first electrode PT01 of the transistor 21 can be electrically connected with the first region of the active layer PT0, and the second electrode PT02 can be electrically connected with the second region of the active layer PT0. The first electrode ST01 of the transistor ST can be electrically connected with the first region of the active layer ST0 of the transistor ST, and the second electrode ST02 can be electrically connected with the second region of the active layer ST0.

[0343] In some examples, the second source-drain metal layer can at least include: a first transfer electrode 211 and a second transfer electrode 212. The first transfer electrode 211 can be electrically connected with the second electrode PT02 of the transistor PT of the pixel driving circuit through the via hole of the first planar layer 204. The second transfer electrode 21 can be electrically connected with the second electrode ST02 of the transistor ST of the sensing driving circuit through the via hole of the first planar layer 204.

[0344] In some examples, the functional structure layer 22 can include a pixel definition layer 221, a spacer column layer 222, a plurality of light emitting elements EL, and a plurality of optoelectric sensing elements OPD. The light emitting element EL can include a first light emitting electrode 311, a light emitting functional layer 312, and a second light emitting electrode 313 which are sequentially stacked. For example, the first light emitting electrode 311 of the light emitting element EL can be an anode, and the first light emitting electrode 311 can be disposed on the second planar layer 205 and electrically connected to the first transfer electrode 211 through a via hole formed in the second planar layer 205 to achieve electrical connection with the pixel driving circuit. The optoelectric sensing element OPD can include a first sensing electrode 321, a sensing functional layer 322, and a second sensing electrode 323 which are sequentially stacked. The first sensing electrode 321 can be disposed on the second planar layer 205 and electrically connected to the second transfer electrode 212 through a via hole formed in the second planar layer 205 to achieve electrical connection with the sensing driving circuit.

[0345] In some examples, the pixel definition layer 221 can be disposed on a side of the first light emitting electrode 311 and the first sensing electrode 321 away from the substrate 200. The pixel definition layer 221 can be formed with a plurality of pixel openings and a plurality of sensing openings, one pixel opening can expose at least part of the surface of a corresponding first light emitting electrode 311, and one sensing opening can expose at least part of the surface of a corresponding first sensing electrode 321.

[0346] In some examples, at least part of the light emitting functional layer 312 can be disposed in one pixel opening and connected to the corresponding first light emitting electrode 311. The second light emitting electrode 313 can be disposed on the light emitting functional layer 312 and connected to the light emitting functional layer 312. The light emitting functional layer 312 can emit light of a corresponding color under the drive of the first light emitting electrode 311 and the second light emitting electrode 313.

[0347] In some examples, at least part of the sensing functional layer 322 can be disposed in one sensing opening and connected to the corresponding first sensing electrode 321. The second sensing electrode 323 can be disposed on the sensing functional layer 322 and connected to the sensing functional layer 322. The sensing functional layer 322 can generate a corresponding optoelectric conversion signal under the drive of the first sensing electrode 321 and the second sensing electrode 323.

[0348] In some examples, the first light emitting electrode 311 and the first sensing electrode 321 can be disposed in the same layer, and the second light emitting electrode 313 and the second sensing electrode 323 can be disposed in the same layer. The second light emitting electrode 313 and the second sensing electrode 323 can be connected to the second power line and configured to receive the same signal. The second light emitting electrode 313 and the second sensing electrode 323 can be an integral structure.

[0349] In some examples, the isolation column layer 222 can be located on the side of the pixel definition layer 221 away from the substrate 200, for example, the isolation column layer can include a plurality of isolation columns (PS).

[0350] In some examples, the light emitting functional layer 312 of the light emitting element EL can include an emitting layer (EML), and one or more film layers including a hole injection layer (HIL), a hole transport layer (HTL), a hole block layer (HBL), an electron block layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Under the voltage driving of the first light emitting electrode 311 and the second light emitting electrode 313, the light emitting characteristic of the organic material can be utilized to emit light according to the required gray scale. In other examples, the light emitting element can adopt a tandem structure design, the light emitting functional layer of the light emitting element can include at least two emitting layers, and the adjacent two emitting layers are connected in series by utilizing a charge generation layer as a hetero layer, so that the light emitting current of the light emitting element can be greatly reduced under the same light emitting intensity, the power consumption and the service life of the display product can be improved, and the brightness requirement of the user can be met.

[0351] In some examples, the emitting layers of the light emitting elements of different colors can be different. For example, the red light emitting element includes a red emitting layer, the green light emitting element includes a green emitting layer, and the blue light emitting element includes a blue emitting layer. In order to reduce the process difficulty and improve the yield, the hole injection layer and the hole transport layer located on one side of the emitting layer can adopt a common layer, and the electron injection layer and the electron transport layer located on the other side of the emitting layer can adopt a common layer. In some examples, any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer can be made by one process (one-time evaporation process or one-time inkjet printing process), and isolation can be achieved by forming a film layer surface step difference or by surface treatment. For example, any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer corresponding to adjacent sub-pixels can be isolated. In some examples, the organic light emitting layer can be prepared by evaporation using a fine metal mask (FMM) or an open mask, or by using an inkjet process.

[0352] In some examples, the sensing functional layer 322 of the optoelectric sensing element OPD can include a photosensitive layer, and one or more film layers including a hole transport layer, an electron blocking layer, a hole blocking layer, and an electron transport layer. The photosensitive layer can include an organic molecular material. When a photon irradiates to the photosensitive layer, the photon will excite an electron in the photosensitive molecule to transition into a conductive band, forming an electron-hole pair, thereby generating a sensing current. In other examples, the optoelectric sensing element can adopt a tandem structure design, and the sensing functional layer of the optoelectric sensing element can include at least two photosensitive layers. By connecting the adjacent two photosensitive layers in series, the cumulative amount of sensing signal can be improved.

[0353] In some examples, as shown in FIG. 34, the encapsulation structure layer 23 can include a first encapsulation layer 231, a second encapsulation layer 232, and a third encapsulation layer 233 stacked in sequence. Among them, the first encapsulation layer 231 and the third encapsulation layer 233 can adopt inorganic materials, and the second encapsulation layer 232 can adopt organic materials. The second encapsulation layer 232 can be arranged between the first encapsulation layer 231 and the third encapsulation layer 233 to prevent external water vapor from entering the light emitting element EL and the optoelectric sensing element OPD. However, the present embodiment is not limited thereto. For example, the encapsulation structure layer can adopt a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0354] In some examples, as shown in FIG. 34, the color filter layer 24 and the first black matrix layer 25 can be located on the side of the encapsulation structure layer 23 away from the substrate substrate 200. The color filter layer 24 can include a plurality of first filter units (such as first filter units 241) and a plurality of second filter units 242. The first black matrix layer 25 can be located between different filter units. The first filter unit 241 can at least partially overlap the light emitting area of at least one light emitting element EL in the projection of the substrate substrate 200; for example, the projection of one first filter unit 241 on the substrate substrate 200 can cover the projection of the light emitting area of one light emitting element EL on the substrate substrate 200. The second filter unit 242 can at least partially overlap the sensing area of at least one optoelectric sensing element OPD in the projection of the substrate substrate 200; for example, the projection of the second filter unit 242 on the substrate substrate 200 can cover the projection of the sensing area of one optoelectric sensing element OPD on the substrate substrate 200.

[0355] In some examples, the plurality of first filter units of the color filter layer 24 can include a plurality of red filter units, a plurality of green filter units, and a plurality of blue filter units. The first filter units of different colors can correspond to the light emitting elements of different colors of the functional structure layer 21. For example, the blue filter units can correspond to the blue light emitting elements, and the projection of the blue filter units on the substrate can at least partially overlap with the projection of the light emitting area of the blue light emitting elements on the substrate, such as the projection of the blue filter units on the substrate can cover the projection of the light emitting area of the blue light emitting elements on the substrate. In the present example, the filter units can pass light of a single color and absorb light of other colors. For example, the blue filter units can pass blue light and absorb light of other colors.

[0356] In some examples, the plurality of second filter units 242 can correspond to the plurality of photoelectric sensing elements OPD of the functional structure layer 21. For example, the plurality of second filter units 242 can include a plurality of green filter units. By shielding the photoelectric sensing elements with the second filter units (such as green filter units), the stray light noise can be reduced.

[0357] FIG. 35 is another partial cross-sectional view of a display panel according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 35, the light emitting element can include a second light emitting electrode 313, a light emitting functional layer 312a, and a first light emitting electrode 311 stacked in a direction away from the substrate 200. The second light emitting electrode 313 can be connected to the pixel driving circuit, and the first light emitting electrode 311 can be connected to the first power line. The connection relationship between the pixel driving circuit and the light emitting element in the present example can be as described in the embodiment shown in FIG. 25. In some examples, the light emitting functional layer 312a of the present example can include the same film layers as the light emitting functional layer 312 of the embodiment shown in FIG. 34, and the order of the film layers in the light emitting functional layer 312a in the direction away from the substrate 200 can be opposite to the order of the film layers in the light emitting functional layer 312 of the embodiment shown in FIG. 34.

[0358] In some examples, the photoelectric sensing element can include a second sensing electrode 323, a sensing functional layer 322a, and a first sensing electrode 321 stacked in a direction away from the substrate 200. The second sensing electrode 323 can be connected to the sensing driving circuit, and the first sensing electrode 321 can be connected to the first power line. In some examples, the sensing functional layer 322a of the present example can include the same film layers as the sensing functional layer 322 of the embodiment shown in FIG. 34, and the order of the film layers in the sensing functional layer 322a in the direction away from the substrate 200 can be opposite to the order of the film layers in the sensing functional layer 322 of the embodiment shown in FIG. 34.

[0359] In some examples, the second light emitting electrode 313 and the second sensing electrode 323 can be arranged in the same layer; the first sensing electrode 321 and the first light emitting electrode 311 can be arranged in the same layer, for example, can be an integrated structure.

[0360] Compared with the embodiment shown in FIG. 34, the photoelectric sensing element and the light emitting element of the present example can adopt an inverted structure. By synchronously inverting the light emitting element and the photoelectric sensing element, the second light emitting electrode and the second sensing electrode can transmit the first power signal, and the voltage drop (IR drop) of the first power signal can be reduced.

[0361] FIG. 36 is a partial plan view of a display panel according to at least one embodiment of the present disclosure. The arrangement of the light emitting elements (including light emitting elements EL1, EL2, and EL3), the photoelectric sensing element OPD, the pixel driving circuit 11, and the sensing driving circuit 12 of the present example can refer to the description of the embodiments, and will not be described here. The film layers of the light emitting elements and the photoelectric sensing element of the display panel of the present example can refer to the description of the embodiments shown in FIG. 34 or FIG. 35.

[0362] In some examples, as shown in FIG. 36, the display panel can include a first partition structure 41 and a second partition structure 42. The first partition structure 41 and the second partition structure 42 can be located on the side of the pixel definition layer away from the substrate. The first partition structure 41 can include a first partition strip 411 extending along the second direction D2 and a second partition strip 412 extending along the first direction D1. The second partition strip 412 can be located in the spacing region between adjacent rows of light emitting elements, and the first partition strip 411 can be located in the spacing region between adjacent light emitting elements in the same row of light emitting elements. The length of the second partition strip 412 along the first direction D1 is greater than the length of the first partition strip 411 along the second direction D2.

[0363] In some examples, the second partition structure 42 can include a partition strip extending along the second direction D2, and the second partition structure 42 can be located between the photoelectric sensing element OPD and the light emitting element adjacent along the first direction D1. In other examples, the first partition structure and the second partition structure can be connected to form a mesh structure, and each mesh can surround one light emitting element or one photoelectric sensing element.

[0364] By arranging the first partition structure and the second partition structure, the present example can reduce the crosstalk between adjacent light emitting elements and between the light emitting element and the photoelectric sensing element, and can improve the signal-to-noise ratio of the photoelectric sensing element.

[0365] FIG. 37 is another partial cross-sectional schematic view of a display panel according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 37, the light emitting element can include the second light emitting electrode 313, the light emitting functional layer 312a, and the first light emitting electrode 311 stacked in a direction away from the substrate base plate 200. The second light emitting electrode 313 is connected with the pixel driving circuit, and the first light emitting electrode 311 can be connected with the first power supply line. The connection relationship between the light emitting element and the pixel driving circuit can refer to the description of the embodiment shown in FIG. 25.

[0366] In some examples, the optoelectric sensing element can include the first sensing electrode 321, the light emitting functional layer 322, and the second sensing electrode 323 stacked in a direction away from the substrate base plate 200. The first sensing electrode 321 is connected with the sensing driving circuit, and the second sensing electrode 323 can be connected with the second power supply line.

[0367] In some examples, the second light emitting electrode 313 is located on the side of the first light emitting electrode 311 close to the substrate base plate 200, and the first sensing electrode 321 is located on the side of the second sensing electrode 323 close to the substrate base plate 200. The light emitting element of the present example can adopt an inverted structure, and the optoelectric sensing element does not adopt an inverted structure, which can improve the parasitic capacitance caused by the electrode integrated arrangement of the light emitting element and the optoelectric sensing element. In other examples, the light emitting element can not adopt an inverted structure, and the optoelectric sensing element can adopt an inverted structure. The remaining description of the present embodiment can refer to the description of the foregoing embodiments, which will not be repeated here.

[0368] FIG. 38 is another partial plan view of a display panel according to at least one embodiment of the present disclosure. The arrangement of the light emitting elements (including the light emitting elements EL1, EL2, and EL3), the optoelectric sensing element OPD, the pixel driving circuit 11, and the sensing driving circuit 12 of the present example can refer to the description of the foregoing embodiments, which will not be repeated here. The film layers of the light emitting element and the optoelectric sensing element of the display panel of the present example can refer to the description of the embodiment shown in FIG. 37.

[0369] In some examples, as shown in FIG. 38, the display panel can include a first partition structure 41. The first partition structure 41 can be located on the side of the pixel definition layer away from the substrate base plate. The first partition structure 41 can include the first partition strip 411 extending along the second direction D2 and the second partition strip 412 extending along the first direction D1. The second partition strip 412 can be located in the spacing region between adjacent rows of light emitting elements, and the first partition strip 411 can be located in the spacing region between adjacent light emitting elements in the same row of light emitting elements. The length of the second partition strip 412 along the first direction D1 is greater than the length of the first partition strip 411 along the second direction D2.

[0370] The first partition structure can reduce the crosstalk between adjacent light emitting elements. In addition, the light emitting element is inverted, and a second partition structure between the light emitting element and the photoelectric sensing element is not required, which is beneficial to improve the size of the sensing area of the photoelectric sensing element.

[0371] FIG. 39 is another partial cross-sectional view of a display panel according to at least one embodiment of the present disclosure. FIG. 40 is another partial plan view of a display panel according to at least one embodiment of the present disclosure. In some examples, as shown in FIGS. 39 and 40, the display panel can further include a touch structure layer 26, which can be located on a side of the color filter layer 24 and the first black matrix layer 25 close to the encapsulation structure layer 23. The touch structure layer 26 can include at least one touch trace layer.

[0372] In some examples, the display panel can adopt a Touch on TFE structure, which mainly includes a flexible multi-layer on cell (FMLOC) structure and a flexible single-layer on cell (FSLOC) structure. The FMLOC structure is based on the working principle of mutual capacitance detection, generally uses two layers of metal to form a driving (Tx) electrode and a sensing (Rx) electrode, and an integrated circuit (IC) detects the mutual capacitance between the driving electrode and the sensing electrode to realize touch action. The FSLOC structure is based on the working principle of self-capacitance (or voltage) detection, generally uses a single layer of metal to form a touch electrode, and an integrated circuit detects the self-capacitance (or voltage) of the touch electrode to realize touch action. The present example takes the FMLOC structure as an example for illustration. The touch structure layer 26 can include two touch trace layers (e.g., including a touch trace layer 261).

[0373] In some examples, as shown in FIG. 40, the orthographic projection of the touch trace layer 261 on the substrate can surround the orthographic projection of a single light emitting element (e.g., light emitting elements EL1, EL2, and EL3) on the substrate, and can surround the orthographic projection of a single photoelectric sensing element OPD on the substrate. For example, the touch trace layer 261 can be arranged in a mesh manner, and a single mesh can surround one light emitting element or one photoelectric sensing element OPD.

[0374] FIG. 41 is another partial plan view of a display panel according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 41, the footprint of the touch wiring layer 261 on the substrate can surround the footprint of a single light emitting element (e.g., light emitting elements EL1, EL2, and EL3) on the substrate and partially surround the footprint of a single optoelectric sensing element OPD on the substrate. For example, the touch wiring layer 261 can be arranged in a mesh pattern, and a single mesh can surround one light emitting element or surround one light emitting element and one optoelectric sensing element OPD.

[0375] This example can reduce reflection and improve the signal-to-noise ratio of the sensing signal by reducing the wiring of the touch wiring layer near the optoelectric sensing element. The remaining description of this example can refer to the description of the previous embodiments, and thus will not be repeated here.

[0376] FIG. 42 is another partial cross-sectional view of a display panel according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 42, the display panel can include a touch structure layer 26 (e.g., including a touch wiring layer 261) on a side of the first black matrix layer 25 and the color filter layer 24 away from the substrate 200, and a second black matrix layer 27 on a side of the touch structure layer away from the substrate 200. The footprints of the first black matrix layer 25 and the second black matrix layer 27 on the substrate 200 cover the footprint of the touch wiring layer 261 on the substrate 200. The footprints of the first black matrix layer 25 and the second black matrix layer 27 on the substrate 200 can not overlap with the light emitting regions of the light emitting elements EL and the sensing regions of the optoelectric sensing elements OPD on the substrate 200.

[0377] This example can reduce reflection and improve the signal-to-noise ratio of the optoelectric sensing element by providing a first black matrix layer and a second black matrix layer and disposing the touch wiring layer between the two black matrix layers. The remaining structure of the display panel of this example can refer to the description of the previous embodiments, and thus will not be repeated here.

[0378] In other examples, the material of the pixel definition layer of the display structure layer can be black, and the display panel can further include a touch structure layer, which can be on a side of the color filter layer and the first black matrix layer close to the encapsulation structure layer. The touch structure layer can include at least one touch wiring layer, and the footprint of the touch wiring layer on the substrate can be within the footprint of the pixel definition layer on the substrate. In some examples, the material of the isolation column layer can be black. The remaining structure of the display panel of this example can refer to the description of the previous embodiments, and thus will not be repeated here.

[0379] In some examples, the material of the pixel definition layer of the display structure layer can be black, and the display panel can further include a touch structure layer located on the first black matrix layer and the color filter layer away from the substrate substrate, and a second black matrix layer located on the touch structure layer away from the substrate substrate. The touch structure layer can include at least one touch trace layer. The first black matrix layer and the second black matrix layer can cover the projection of the touch trace layer on the substrate substrate. The remaining structures of the display panel according to the present example can be referred to the description of the foregoing embodiments, and thus will not be repeated here.

[0380] FIG. 43 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. As shown in FIG. 43, the present embodiment provides a display device 91 including a display panel 910. In some examples, the display panel 910 can integrate photoelectric sensing and display functions, for example, the display panel 910 can be an OLED display panel, a QLED display panel, a Micro-LED display panel, or a Mini-LED display panel. The display device 91 can be a product having an image (including a static image or a dynamic image, where the dynamic image can be a video) display function. For example, the display device can be any one of a display, a television, a billboard, a digital photo frame, a laser printer with display function, a telephone, a mobile phone, a picture screen, a personal digital assistant (PDA), a digital camera, a camcorder, a viewfinder, a navigator, a vehicle, a large-area wall, an information query device (such as a business query device of an electronic government, a bank, a hospital, a power department, etc.), a monitor, and the like. For another example, the display device can also be a micro display, any one of a VR device or an AR device containing a micro display, and the like.

[0381] The drawings in the present disclosure only involve the structures involved in the present disclosure, and other structures can be referred to the general design. The embodiments of the present disclosure, i.e., the features in the embodiments, can be combined with each other to obtain new embodiments without conflict. It should be noted that the above examples or embodiments are only exemplary and not restrictive. Therefore, the present disclosure is not limited to the details shown and described herein. Various modifications, replacements or omissions can be made to the forms and details without departing from the scope of the present disclosure.

Claims

1. A composite drive circuit comprising: A pixel driving circuit and a sensing driving circuit; The pixel driving circuit comprises a plurality of pixel nodes; The pixel driving circuit is connected with a scan end, a data line, a plurality of reset control ends and at least one light emitting element, and is configured to reset at least one pixel node in the plurality of pixel nodes under the control of at least one reset control end in the plurality of reset control ends; write a data signal provided by the data line into one pixel node as a data writing node under the control of the scan end; and generate a driving signal for driving the at least one light emitting element to emit light according to the data signal; The sensing driving circuit comprises a first sensing node and a second sensing node, and the sensing driving circuit is connected with a sensing reset control end, a sensing output control end, a sensing reading line and at least one photoelectric sensing element, and is configured to reset the first sensing node under the control of the sensing reset control end; generate a sensing signal according to a photoelectric conversion signal written into the first sensing node by the at least one photoelectric sensing element; and provide the sensing signal written into the second sensing node to the sensing reading line under the control of the sensing output control end; The composite driving circuit satisfies at least one of the following conditions: The sensing output control end is configured to receive the same signal as the scan end; The sensing reset control end is configured to receive the same signal as one of the plurality of reset control ends.

2. The composite drive circuit of claim 1, wherein, The plurality of pixel nodes comprises a first pixel node, a second pixel node and a third pixel node; The pixel driving circuit comprises: a driving sub-circuit connected with the first pixel node, the second pixel node and the third pixel node, and configured to generate the driving signal under the control of the first pixel node; a data writing sub-circuit connected with the scan end, the data line and one pixel node as a data writing node, and configured to write a data signal into the data writing node under the control of the scan end; a first compensation sub-circuit connected with a first compensation control end, the first pixel node and the third pixel node, and configured to turn on the first pixel node and the third pixel node under the control of the first compensation control end, so as to write a threshold voltage of the driving sub-circuit into the first pixel node; wherein the pixel driving circuit is configured to perform writing the data signal into the data writing node and writing the threshold voltage of the driving sub-circuit into the first pixel node in steps; The duration for which the data writing sub-circuit writes the data signal into the data writing node is shorter than the duration for which the first compensation sub-circuit writes the threshold voltage of the driving sub-circuit into the first pixel node.

3. The composite drive circuit of claim 2, wherein, The starting time for which the data writing sub-circuit writes the data signal into the data writing node is later than the ending time for which the first compensation sub-circuit writes the threshold voltage of the driving sub-circuit into the first pixel node.

4. The composite drive circuit of claim 2 or 3, wherein, The plurality of reset control ends comprises a first reset control end, a second reset control end and a third reset control end; The plurality of pixel nodes further include a fifth pixel node connected with a first light emitting electrode of the at least one light emitting element; The pixel driving circuit further includes: A first reset sub-circuit connected with the first reset control terminal, a first initial signal line and the first pixel node, configured to write a first initial signal provided by the first initial signal line to the first pixel node under the control of the first reset control terminal; A second reset sub-circuit connected with the second reset control terminal, a second initial signal line and the fifth pixel node, configured to write a second initial signal provided by the second initial signal line to the fifth pixel node under the control of the second reset control terminal; A third reset sub-circuit connected with the third reset control terminal, a reference signal line and the second pixel node, configured to write a reference signal provided by the reference signal line to the second pixel node under the control of the third reset control terminal, or connected with the third reset control terminal, a third initial signal line and the second pixel node, configured to write a third initial signal provided by the third initial signal line to the second pixel node under the control of the third reset control terminal.

5. The composite drive circuit of claim 4, wherein, The first compensation control terminal and the second reset control terminal are configured to receive the same signal, or the first compensation control terminal and the first reset control terminal are configured to receive the same signal.

6. The composite drive circuit of claim 4, wherein, The sensing reset control terminal is configured to receive the same signal as the first reset control terminal, or the sensing reset control terminal is configured to receive the same signal as the second reset control terminal.

7. The composite drive circuit of claim 4, wherein, The first reset sub-circuit includes a first reset transistor, a gate of the first reset transistor is connected with the first reset control terminal, a first electrode of the first reset transistor is connected with the first initial signal line, and a second electrode of the first reset transistor is connected with the first pixel node; The second reset sub-circuit includes a second reset transistor, a gate of the second reset transistor is connected with the second reset control terminal, a first electrode of the second reset transistor is connected with the second initial signal line, and a second electrode of the second reset transistor is connected with the fifth pixel node; The third reset sub-circuit includes a third reset transistor, a gate of the third reset transistor is connected with the third reset control terminal, a first electrode of the third reset transistor is connected with the reference signal line or the third initial signal line, and a second electrode of the third reset transistor is connected with the second pixel node.

8. The composite drive circuit of claim 2 or 3, wherein, The plurality of pixel nodes further include a fourth pixel node, and the plurality of reset control terminals further include a fourth reset control terminal. The pixel driving circuit further includes: A first storage sub-circuit connected with the first pixel node and the fourth pixel node, configured to store a voltage of the first pixel node; A fourth reset sub-circuit connected with the fourth reset control terminal, the fourth pixel node and a first power supply terminal, configured to turn on the fourth pixel node and the first power supply terminal under the control of the fourth reset control terminal.

9. The composite drive circuit of claim 8, wherein, The fourth reset sub-circuit comprises a fourth reset transistor, a gate of the fourth reset transistor is connected with the fourth reset control end, a first pole of the fourth reset transistor is connected with the first power supply end, and a second pole of the fourth reset transistor is connected with the fourth pixel node. The first storage sub-circuit comprises a first capacitor, a first electrode of the first capacitor is connected with the first pixel node, and a second electrode of the first capacitor is connected with the fourth pixel node.

10. The composite drive circuit of claim 2 or 3, wherein, The plurality of reset control ends comprises a fifth reset control end. The plurality of pixel nodes further comprises a sixth pixel node, and the sixth pixel node serves as the data write-in node. The pixel driving circuit further comprises: A first storage sub-circuit connected with the first pixel node and the sixth pixel node, configured to store the voltage of the first pixel node; A fifth reset sub-circuit connected with the fifth reset control end, the second pixel node and the sixth pixel node, configured to turn on the second pixel node and the sixth pixel node under the control of the fifth reset control end.

11. The composite drive circuit of claim 10, wherein, The sensing output control end is configured to receive the same signal as the scanning end, and the sensing reset control end is configured to receive the same signal as any one of the plurality of reset control ends or the scanning end. The sensing reset control end is configured to receive the same signal as any one of the plurality of reset control ends or the scanning end.

12. The composite drive circuit of any one of claims 2 to 11, wherein, The first sensing node is connected with the at least one photoelectric sensing element. The sensing driving circuit comprises: A sensing reset sub-circuit connected with a sensing reset signal line, the sensing reset control end and the first sensing node, configured to reset the first sensing node by writing the sensing reset signal provided by the sensing reset signal line into the first sensing node under the control of the sensing reset control end; A sensing sub-circuit connected with the first sensing node, a second power supply end and the second sensing node, configured to generate a sensing signal according to the photoelectric conversion signal written into the first sensing node by the at least one photoelectric sensing element; A sensing output sub-circuit connected with the sensing output control end, a sensing read line and the second sensing node, configured to provide the sensing signal to the sensing read line under the control of the sensing output control end.

13. The composite drive circuit of claim 12, wherein, The sensing driving circuit further comprises: A voltage stabilizing sub-circuit connected with the first sensing node and a fourth power supply end; A second compensation sub-circuit connected with a second compensation control end, the first sensing node and the second sensing node, configured to turn on the first sensing node and the second sensing node under the control of the second compensation control end; The second compensation control end is configured to receive the same signal as the first compensation control end.

14. The composite drive circuit of claim 13, wherein, The sensing reset sub-circuit comprises a sensing reset transistor, a gate of the sensing reset transistor is connected with the sensing reset control end, a first pole of the sensing reset transistor is connected with the sensing reset signal line, and a second pole of the sensing reset transistor is connected with the first sensing node. The sensing sub-circuit comprises a sensing transistor, a gate of the sensing transistor is connected with the first sensing node, a first pole of the sensing transistor is connected with the second power supply end, and a second pole of the sensing transistor is connected with the second sensing node; The sensing output sub-circuit comprises a sensing output transistor, a gate of the sensing output transistor is connected with the sensing output control end, a first pole of the sensing output transistor is connected with the second sensing node, and a second pole of the sensing output transistor is connected with the sensing reading line; The voltage stabilizing sub-circuit comprises a voltage stabilizing capacitor, a first electrode of the voltage stabilizing capacitor is connected with the first sensing node, and a second electrode of the voltage stabilizing capacitor is connected with the fourth power supply end; The second compensation sub-circuit comprises a second compensation transistor, a gate of the second compensation transistor is connected with the second compensation control end, a first pole of the second compensation transistor is connected with the second sensing node, and a second pole of the second compensation transistor is connected with the first sensing node.

15. A driving method of a composite driving circuit, applied to the composite driving circuit in any one of claims 1 to 14, the driving method comprising: resetting at least one pixel node in a plurality of pixel nodes under the control of at least one reset control end in a plurality of reset control ends by a pixel driving circuit; writing a data signal provided by a data line into one of the pixel nodes as a data writing node under the control of a scanning end, and generating a driving signal for driving at least one light emitting element to emit light according to the data signal; resetting a first sensing node under the control of a sensing reset control end by a sensing driving circuit; generating a sensing signal according to a photoelectric conversion signal written into the first sensing node by the at least one photoelectric sensing element; and providing the sensing signal written into a second sensing node to the sensing reading line under the control of the sensing output control end; wherein, when the sensing reset control end is configured to receive the same signal as one of the plurality of reset control ends, the composite driving circuit synchronously performs the resetting of the at least one pixel node and the resetting of the first sensing node; when the sensing output control end is configured to receive the same signal as the scanning end, the composite driving circuit synchronously performs the writing of the data signal into the data writing node and the output of the sensing signal from the sensing reading line.

16. The driving method of claim 15, further comprising: writing a threshold voltage of a driving sub-circuit into a first pixel node under the control of a first compensation control end by the pixel driving circuit; writing a threshold voltage of a sensing sub-circuit into the first sensing node under the control of a second compensation control end by the sensing driving circuit; the first compensation control end and the second compensation control end are configured to receive the same signal as one of the plurality of reset control ends. ​ 17. The driving method according to claim 16, wherein The first compensation control end and the scanning end are configured to receive different signals; the pixel driving circuit step-by-step writes the data signal to the data writing node and writes the threshold voltage of the driving sub-circuit to the first pixel node.

18. The driving method according to claim 16 or 17, wherein When the pixel driving circuit writes the threshold voltage of the driving sub-circuit to the first pixel node, the sensing driving circuit synchronously writes the photoelectric conversion signal of the at least one photoelectric sensing element to the first sensing node to generate the sensing signal.

19. The driving method according to claim 15, wherein The driving cycle of the pixel driving circuit includes a refresh frame and a holding frame; In the refresh frame, the pixel driving circuit resets at least one of the pixel nodes under the control of at least one of the reset control ends, and the sensing driving circuit resets the first sensing node; In the holding frame, the pixel driving circuit generates a driving signal for driving at least one light emitting element to emit light according to the data signal written in the refresh frame, and the sensing driving circuit outputs the sensing signal from the sensing reading line; After the sensing driving circuit resets the first sensing node, and before the sensing signal is output from the sensing reading line, the sensing driving circuit generates the sensing signal according to the photoelectric conversion signal of the at least one photoelectric sensing element written to the first sensing node.

20. The driving method according to claim 15, wherein The driving cycle of the pixel driving circuit includes a refresh frame and a holding frame; In the holding frame, the pixel driving circuit resets at least one of the pixel nodes under the control of at least one of the reset control ends, and the sensing driving circuit resets the first sensing node; In the refresh frame, the pixel driving circuit writes the data signal provided by the data line to one of the pixel nodes as a data writing node under the control of the scanning end, and the sensing driving circuit outputs the sensing signal from the sensing reading line; After the sensing driving circuit resets the first sensing node, and before the sensing signal is output from the sensing reading line, the sensing driving circuit generates the sensing signal according to the photoelectric conversion signal of the at least one photoelectric sensing element written to the first sensing node.

21. A display panel comprising: A substrate, a plurality of pixel driving circuits arranged on the substrate, a plurality of sensing driving circuits, a plurality of light emitting elements, and a plurality of photoelectric sensing elements; At least one of the pixel driving circuits includes a plurality of pixel nodes, and is connected with a scanning end, a data line, a plurality of reset control ends, and at least one of the light emitting elements, and is configured to reset at least one of the pixel nodes under the control of at least one of the reset control ends, write the data signal provided by the data line to one of the pixel nodes as a data writing node under the control of the scanning end, and generate a driving signal for driving the at least one light emitting element to emit light according to the data signal; At least one of the plurality of sensing driving circuits comprises a first sensing node and a second sensing node, and is connected with a sensing reset control end, a sensing output control end, a sensing reading line and at least one of the plurality of photoelectric sensing elements, and is configured to reset the first sensing node under the control of the sensing reset control end; A photoelectric conversion signal of the at least one photoelectric sensing element is written into the first sensing node to generate a sensing signal; and the sensing signal written into the second sensing node is provided to the sensing reading line under the control of the sensing output control end; The display panel satisfies at least one of the following conditions: The sensing output control end connected with the at least one sensing driving circuit is configured to receive the same signal as the scanning end connected with the at least one pixel driving circuit; The sensing reset control end connected with the at least one sensing driving circuit is configured to receive the same signal as one of the plurality of reset control ends connected with the at least one pixel driving circuit.

22. The display panel of claim 21, wherein, The plurality of pixel driving circuits and the plurality of sensing driving circuits are arranged in an array, and n sensing driving circuits are arranged at intervals of m pixel driving circuits in a first direction; wherein m and n are both integers greater than 0, and m is greater than n.

23. The display panel of claim 22, wherein, The plurality of pixel driving circuits and the plurality of sensing driving circuits arranged in the first direction are configured to be connected with the same scanning line; The plurality of pixel driving circuits arranged in a second direction are configured to be connected with the same data line, the plurality of sensing driving circuits arranged in the second direction are configured to be connected with the same sensing reading line, and the second direction intersects the first direction.

24. The display panel of claim 21, wherein, The plurality of light emitting elements are divided into a plurality of display units, and the plurality of display units are arranged in an array along a first direction and a second direction, and the first direction intersects the second direction; Each display unit comprises a light emitting element emitting light of a first color, a light emitting element emitting light of a second color, and a light emitting element emitting light of a third color; In the display unit, the light emitting element emitting light of the first color and the light emitting element emitting light of the second color are adjacent in the first direction, and the light emitting element emitting light of the third color is located on the same side of the light emitting element emitting light of the first color and the light emitting element emitting light of the second color in the second direction; A photoelectric sensing element is arranged between the light emitting elements emitting light of the third color of two adjacent display units in the first direction. The plurality of light emitting elements are divided into a plurality of display units, and the plurality of display units are arranged in an array along a first direction and a second direction, and the first direction intersects the second direction; 25. The display panel of claim 21, wherein, Each display unit comprises a light emitting element emitting light of a first color, a light emitting element emitting light of a second color, and two light emitting elements emitting light of a third color; At least one photoelectric sensing element is arranged between two light emitting elements emitting light of the third color adjacent in the first direction or the second direction. The at least one light emitting element comprises a first light emitting electrode, a light emitting functional layer and a second light emitting electrode arranged in a stack.

26. The display panel of claim 21, wherein, ​ The at least one optoelectric sensing element comprises: a first sensing electrode, a sensing functional layer and a second sensing electrode which are stacked; The first light-emitting electrode is connected with the pixel driving circuit, the first sensing electrode is connected with the sensing driving circuit, and the second light-emitting electrode and the second sensing electrode are configured to receive the same signal. Alternatively, the first light-emitting electrode and the first sensing electrode are configured to receive the same signal, the second light-emitting electrode is connected with the pixel driving circuit, and the second sensing electrode is connected with the sensing driving circuit.

27. The display panel of claim 26, wherein, The first light-emitting electrode and the first sensing electrode are arranged in the same layer, and the second light-emitting electrode and the second sensing electrode are arranged in the same layer.

28. The display panel of claim 27, further comprising: The first partition structure is located between adjacent light-emitting elements, and the second partition structure is located between at least one light-emitting element and an adjacent optoelectric sensing element.

29. The display panel of claim 26, wherein, The first light-emitting electrode is located on the side of the second light-emitting electrode close to the substrate, and the first sensing electrode is located on the side of the second sensing electrode away from the substrate; or the first light-emitting electrode is located on the side of the second light-emitting electrode away from the substrate, and the first sensing electrode is located on the side of the second sensing electrode close to the substrate.

30. The display panel of claim 29, further comprising: The first partition structure is located between adjacent light-emitting elements.

31. The display panel of any of claims 21-30, further comprising: The color filter layer and the first black matrix layer are located on the side of the plurality of light-emitting elements and the plurality of optoelectric sensing elements away from the substrate. The color filter layer comprises: a plurality of first filter units and a plurality of second filter units; and the first black matrix layer is located between different filter units. The first filter unit at least partially overlaps the light-emitting area of at least one light-emitting element in the orthographic projection of the substrate, and the second filter unit at least partially overlaps the sensing area of at least one optoelectric sensing element in the orthographic projection of the substrate.

32. The display panel of claim 31, further comprising: At least one touch wiring layer is located on the side of the color filter layer close to the substrate. The orthographic projection of the touch wiring layer on the substrate surrounds the light-emitting area of a single light-emitting element in the orthographic projection of the substrate. The orthographic projection of the touch wiring layer on the substrate surrounds or partially surrounds the sensing area of a single optoelectric sensing element in the orthographic projection of the substrate.

33. The display panel of claim 31, further comprising: At least one touch wiring layer is located on the side of the first black matrix layer away from the substrate; A second black matrix layer is located on the side of the at least one touch wiring layer away from the substrate; The orthographic projection of the first black matrix layer and the second black matrix layer on the substrate covers the orthographic projection of the at least one touch wiring layer on the substrate.

34. A display device comprising the display panel of any one of claims 21 to 33.

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