Thin-film transistor and manufacturing method therefor, display panel, and display device

Abstract

The present disclosure belongs to the field of display technology. Provided are a thin-film transistor and a manufacturing method therefor, a display panel, and a display device. The thin-film transistor comprises: a substrate; a first insulating layer located on the substrate, the first insulating layer comprising a via hole; and a gate and an active layer located in the via hole, the orthographic projections of the gate and the active layer on a first plane perpendicular to the substrate having an overlapping region. The technical solution of the present disclosure can reduce the planar size of the thin-film transistor.

Description

Thin film transistor, manufacturing method thereof, display panel and display device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and particularly refers to a thin film transistor, a manufacturing method thereof, a display panel and a display device. BACKGROUND

[0002] Thin film transistor (TFT) is a very important component in the field of display technology, and plays a very important role in liquid crystal display (LCD) and organic light emitting diode display (OLED).

[0003] SUMMARY

[0004] The technical problem to be solved by the present disclosure is to provide a thin film transistor, a manufacturing method thereof, a display panel and a display device, which can reduce the planar size of the thin film transistor.

[0005] To solve the above technical problem, the technical scheme provided by the embodiments of the present disclosure is as follows:

[0006] In one aspect, a thin film transistor is provided, comprising:

[0007] a substrate;

[0008] a first insulating layer on the substrate, the first insulating layer comprising a via hole;

[0009] a gate and an active layer in the via hole, the gate and the active layer having an overlapping area in the orthogonal projection on a first plane perpendicular to the substrate.

[0010] In some embodiments, the gate covers at least part of the sidewall of the via hole, and the gate in the via hole forms a first trench;

[0011] a gate insulating layer covering the gate and located at least in the first trench, the gate insulating layer in the first trench forming a second trench;

[0012] an active layer covering the gate insulating layer and located at least in the second trench, the active layer in the second trench forming a third trench.

[0013] In some embodiments, the thin film transistor further comprises:

[0014] a second insulating layer filling the third trench.

[0015] In some embodiments, the thin film transistor further comprises:

[0016] a second insulating layer covering the active layer and located at least in the third trench, the second insulating layer located in the third trench forming a fourth trench;

[0017] an additional gate located in the fourth trench, the additional gate and the active layer having an overlapping region in a normal projection on a first plane perpendicular to the substrate.

[0018] In some embodiments, the active layer covers at least a portion of a sidewall of the via, the active layer located in the via forming a fifth trench;

[0019] a gate insulating layer covering the active layer and located at least in the fifth trench, the gate insulating layer located in the fifth trench forming a sixth trench;

[0020] the gate located in the sixth trench.

[0021] In some embodiments, the active layer includes a first portion located in the via and a second portion extending from the via to a surface of the first insulating layer away from the substrate, and the thin film transistor further includes:

[0022] a source and a drain located on a side of the second portion away from the substrate.

[0023] In some embodiments, an aperture of the via is 2-5 microns.

[0024] In some embodiments, a sidewall of the via is perpendicular to the substrate.

[0025] Embodiments of the present disclosure further provide a display panel including the thin film transistor as described above.

[0026] Embodiments of the present disclosure further provide a display device including the thin film transistor as described above.

[0027] Embodiments of the present disclosure further provide a method for manufacturing a thin film transistor, including:

[0028] providing a substrate;

[0029] forming a first insulating layer on the substrate, etching the first insulating layer to form a via;

[0030] forming a gate and an active layer in the via, the gate and the active layer having an overlapping region in a normal projection on a first plane perpendicular to the substrate.

[0031] In some embodiments, the forming a gate and an active layer in the via includes:

[0032] forming a gate covering at least part of the sidewall of the via, the gate in the via forming a first trench;

[0033] forming a gate insulating layer covering at least the gate in the first trench, the gate insulating layer in the first trench forming a second trench;

[0034] forming an active layer covering at least the gate insulating layer in the second trench, the active layer in the second trench forming a third trench.

[0035] In some embodiments, the method further comprises:

[0036] forming a second insulating layer filling the third trench.

[0037] In some embodiments, the method further comprises:

[0038] forming a second insulating layer covering at least the active layer in the third trench, the second insulating layer in the third trench forming a fourth trench;

[0039] forming an additional gate in the fourth trench, the additional gate and the active layer having an overlapping region in a normal projection on a first plane perpendicular to the substrate.

[0040] In some embodiments, the forming a gate and an active layer in the via comprises:

[0041] forming an active layer covering at least part of the sidewall of the via, the active layer in the via forming a fifth trench;

[0042] forming a gate insulating layer covering at least the active layer in the fifth trench, the gate insulating layer in the fifth trench forming a sixth trench;

[0043] forming the gate in the sixth trench.

[0044] In some embodiments, the active layer comprises a first portion in the via and a second portion extending from the via to a side surface of the first insulating layer away from the substrate; the method further comprises:

[0045] forming a source and a drain on the side of the second portion away from the substrate. BRIEF DESCRIPTION OF DRAWINGS

[0046] FIGS. 1-9 are schematic diagrams of fabricating a thin film transistor according to an embodiment of the present disclosure;

[0047] FIGS. 10 and 11 are schematic diagrams of fabricating a thin film transistor according to another embodiment of the present disclosure;

[0048] FIGS. 12-14 are schematic diagrams of structures for fabricating a thin film transistor according to another embodiment of the present disclosure.

[0049] Reference signs

[0050] 01 substrate

[0051] 02 first insulating layer

[0052] 03 gate metal layer

[0053] 031 gate

[0054] 04 gate insulating layer

[0055] 05 active layer

[0056] 06 second insulating layer

[0057] 07 source-drain metal layer

[0058] 071 source

[0059] 072 drain

[0060] 08 additional gate

[0061] GK via hole

[0062] GC1 first trench

[0063] GC2 second trench

[0064] GC3 third trench

[0065] GC4 fourth trench

[0066] GC5 fifth trench

[0067] GC6 sixth trench DETAILED DESCRIPTION

[0068] To make the technical problems, technical solutions and advantages of the embodiments of the present disclosure clearer, the following will be described in detail with reference to the drawings and specific embodiments.

[0069] The embodiments of the present disclosure provide a thin film transistor and a manufacturing method thereof, a display panel and a display device, which can reduce the planar size of the thin film transistor.

[0070] The embodiments of the present disclosure provide a thin film transistor, comprising:

[0071] a substrate;

[0072] a first insulating layer on the substrate, the first insulating layer comprising a via hole;

[0073] A gate electrode and an active layer located in the via, the gate electrode and the active layer having an overlapping region in a normal projection on a first plane perpendicular to the substrate.

[0074] In the embodiment, the first insulating layer includes a via, the gate electrode and the active layer of the thin film transistor are located in the via, and the gate electrode and the active layer have an overlapping region in a normal projection on a first plane perpendicular to the substrate. In this way, the channel length of the thin film transistor is controlled by the depth of the via. When the channel length of the thin film transistor needs to be increased, the planar size of the thin film transistor does not need to be increased, and only the depth of the via needs to be increased. Thus, the planar size of the thin film transistor can be reduced, and the footprint of the thin film transistor can be reduced. In addition, the vertical channel structure of the thin film transistor is beneficial to improving the bending stress resistance of the thin film transistor and reducing the working voltage of the thin film transistor.

[0075] In the embodiment, the channel length of the thin film transistor is determined by the size of the normal part of the gate electrode and the active layer. When the aperture of the via is fixed, the channel length of the thin film transistor can be increased by increasing the depth of the via. The longer the length of the normal part in the first direction, the longer the channel length. The first direction is perpendicular to the substrate.

[0076] In a specific embodiment, as shown in FIGS. 1-9, the thin film transistor includes a substrate 01 and a first insulating layer 02 located on the substrate 01. The substrate 01 can include a substrate, a barrier layer, a buffer layer, etc. The substrate can be a glass substrate or a polyimide substrate. The first insulating layer 02 can be polyimide, silicon oxide, or silicon nitride, etc. As shown in FIG. 2, the first insulating layer 02 forms a via GK. The aperture of the via GK can be 2-5 microns. Preferably, the sidewall of the via GK is perpendicular to the substrate 01. In this way, the planar size of the thin film transistor can be reduced. As shown in FIG. 4, a gate electrode 031 is formed in the via GK. The gate electrode 031 can be at least one of Ti, Al, Mo, Ta, Cr, Zr, Hf, Nb, Ag, Au, Cu, Sb, V, Ru, Pt, Zn, and Mg. The thickness of the gate electrode 031 can be 200-500 nm. The gate electrode 031 can cover the bottom and the sidewall of the via GK. The gate electrode 031 located in the via can form a first trench GC1. As shown in FIG. 5, a gate insulating layer 04 is formed in the first trench GC1. The gate insulating layer 04 can be SiO2, Al2O3, HfO2, ZrO2, TiO2, MgO, ZnO, or MgF2. The thickness of the gate insulating layer 04 can be 50-200 nm. As shown in FIG. 6, an active layer 05 is formed on the gate insulating layer 04. The active layer 05 can be amorphous silicon, microcrystalline silicon, polycrystalline silicon, or monocrystalline silicon. The thickness of the active layer 05 can be 50-200 nm. As shown in FIG. 7, a source electrode 032 is formed on the active layer 05. The source electrode 032 can be at least one of Ti, Al, Mo, Ta, Cr, Zr, Hf, Nb, Ag, Au, Cu, Sb, V, Ru, Pt, Zn, and Mg. The thickness of the source electrode 032 can be 200-500 nm. The source electrode 032 can cover the active layer 05. The source electrode 032 located in the via can form a second trench GC2. As shown in FIG. 8, a drain electrode 033 is formed on the active layer 05. The drain electrode 033 can be at least one of Ti, Al, Mo, Ta, Cr, Zr, Hf, Nb, Ag, Au, Cu, Sb, V, Ru, Pt, Zn, and Mg. The thickness of the drain electrode 033 can be 200-500 nm. The drain electrode 033 can cover the active layer 05. The drain electrode 033 located in the via can form a third trench GC3. As shown in FIG. 9, a passivation layer 06 is formed on the source electrode 032 and the drain electrode 033. The passivation layer 06 can be polyimide, silicon oxide, or silicon nitride, etc. The thickness of the passivation layer 06 can be 50-200 nm. xThe thickness of the gate insulating layer 04 can be 200-500 nm, the gate insulating layer 04 can be located only in the first trench, and can also extend from the first trench to the side of the first insulating layer 02 away from the substrate 01, and the gate insulating layer 04 located in the first trench forms a second trench GC2. As shown in FIG. 6, the active layer 05 is arranged in the second trench, the active layer 05 can be a metal oxide semiconductor, and can be an oxide of at least one of In, Zn, Sn, Ga and Hf. The thickness of the active layer 05 can be 200-500 nm. The active layer 05 is not only located in the second trench, but also extends from the second trench to the side of the first insulating layer 02 away from the substrate 01, and the active layer 05 located in the second trench forms a third trench GC3.

[0077] As shown in FIG. 7, the thin film transistor further comprises a second insulating layer 06 filling the third trench. The second insulating layer 06 can be an organic resin, silicon oxide or silicon nitride. The thickness of the second insulating layer 06 can be 200-500 nm, and the second insulating layer 06 can provide a flat surface for subsequent formation of the source electrode and the drain electrode. As shown in FIG. 9, the thin film transistor further comprises a source electrode 071 and a drain electrode 072. The source electrode 071 and the drain electrode 072 can be at least one of Ti, Al, Mo, Ta, Cr, Zr, Hf, Nb, Ag, Au, Cu, Sb, V, Ru, Pt, Zn and Mg. The thickness of the source electrode 071 and the drain electrode 072 can be 200-500 nm. The active layer 05 comprises a first part located in the via and a second part extending from the via to the side surface of the first insulating layer 02 away from the substrate 01. The source electrode 071 and the drain electrode 072 are located on the side of the second part away from the substrate 01.

[0078] In the embodiment, the source electrode 071 and the drain electrode 072 are located on the same horizontal plane, and the orthographic projections of the source electrode 071 and the drain electrode 072 on the substrate 01 do not overlap. This can avoid the generation of parasitic capacitance between the source electrode 071 and the drain electrode 072, improve the subthreshold swing of the thin film transistor, and reduce the leakage current of the thin film transistor.

[0079] In the embodiment, the channel length of the thin film transistor is determined by the length of the part of the active layer and the gate electrode facing each other. As shown in FIG. 6, the channel length of the thin film transistor is equal to d1+d2+d3. In the case that the aperture of the via is unchanged, the channel length of the thin film transistor can be controlled by the depth of the via. When it is necessary to increase the channel length of the thin film transistor, the planar size of the thin film transistor does not need to be increased, and only the depth of the via needs to be increased. Therefore, the planar size of the thin film transistor can be reduced, and the footprint of the thin film transistor can be reduced.

[0080] In another embodiment, as shown in Fig. 1, the thin film transistor comprises a substrate 01 and a first insulating layer 02 on the substrate 01, wherein the substrate 01 can comprise a substrate, a barrier layer and a buffer layer, etc., the substrate can be a glass substrate or a polyimide substrate, and the first insulating layer 02 can be polyimide, silicon oxide or silicon nitride, etc. As shown in Fig. 2, the first insulating layer 02 is formed with a via hole GK, the aperture of the via hole GK can be 2-5 microns, and preferably, the sidewall of the via hole GK is perpendicular to the substrate 01, which can be beneficial to reduce the planar size of the thin film transistor; as shown in Fig. 4, a gate 031 is formed in the via hole GK, the gate 031 can be at least one of Ti, Al, Mo, Ta, Cr, Zr, Hf, Nb, Ag, Au, Cu, Sb, V, Ru, Pt, Zn and Mg, and the thickness of the gate 031 can be 200-500 nm, the gate 031 can cover the bottom and sidewall of the via hole GK, the gate 031 can cover part of the sidewall of the via hole GK, or the gate 031 can cover the entire sidewall of the via hole GK, and the gate 031 in the via hole forms a first groove GC1; as shown in Fig. 5, a gate insulating layer 04 is arranged in the first groove, the gate insulating layer 04 can be at least one of SiO2, Al2O3, HfO2, etc., the thickness of the gate insulating layer 04 can be 200-500 nm, the gate insulating layer 04 can be located only in the first groove, or the gate insulating layer 04 can extend from the first groove to the side of the first insulating layer 02 away from the substrate 01, and the gate insulating layer 04 in the first groove forms a second groove GC2; as shown in Fig. 6, an active layer 05 is arranged in the second groove, the active layer 05 can be a metal oxide semiconductor, which can be an oxide of at least one of In, Zn, Sn, Ga and Hf, and the thickness of the active layer 05 can be 200-500 nm, the active layer 05 is not only located in the second groove, but also extends from the second groove to the side of the first insulating layer 02 away from the substrate 01, and the active layer 05 in the second groove forms a third groove GC3. x

[0081] As shown in Fig. 10, the thin film transistor further comprises a second insulating layer 06 filling the third groove, the second insulating layer 06 can be an organic resin, silicon oxide or silicon nitride, and the thickness of the second insulating layer 06 can be 200-500 nm, and the second insulating layer 06 in the third groove forms a fourth groove GC4.

[0082] As shown in Fig. 11, the thin film transistor further comprises an additional gate 08 in the fourth groove GC4, and the additional gate 08 and the active layer 05 have an overlapping area in the orthogonal projection on a first plane perpendicular to the substrate 01. The additional gate 08 can realize a double-gate thin film transistor, and increase the mobility of the thin film transistor.

[0083] ​As shown in Fig. 11, the thin film transistor further comprises a source electrode 071 and a drain electrode 072, the source electrode 071 and the drain electrode 072 can be made of at least one of Ti, Al, Mo, Ta, Cr, Zr, Hf, Nb, Ag, Au, Cu, Sb, V, Ru, Pt, Zn and Mg, the thickness of the source electrode 071 and the drain electrode 072 can be 200-500 nm, the active layer 05 comprises a first part located in the via and a second part extending from the via to the side surface of the first insulating layer 02 away from the substrate 01; the source electrode 071 and the drain electrode 072 are located on the side of the second part away from the substrate 01.

[0084] In the embodiment, the source electrode 071 and the drain electrode 072 are located on the same horizontal plane, and the orthographic projections of the source electrode 071 and the drain electrode 072 on the substrate 01 do not overlap, which can avoid the generation of parasitic capacitance between the source electrode 071 and the drain electrode 072, improve the subthreshold swing of the thin film transistor, and reduce the leakage current of the thin film transistor.

[0085] In the embodiment, the channel length of the thin film transistor is determined by the length of the part of the active layer and the gate in direct opposition, as shown in Fig. 6, the channel length of the thin film transistor is equal to d1+d2+d3, and in the case that the aperture of the via is unchanged, the channel length of the thin film transistor can be controlled by the depth of the via, and when it is necessary to increase the channel length of the thin film transistor, the planar size of the thin film transistor does not need to be increased, and only the depth of the via needs to be increased, thereby the planar size of the thin film transistor can be reduced, and the footprint of the thin film transistor can be reduced.

[0086] In another embodiment, as shown in Fig. 1, the thin film transistor comprises a substrate 01 and a first insulating layer 02 located on the substrate 01, wherein the substrate 01 can comprise a substrate, a barrier layer and a buffer layer, etc., the substrate can be made of a glass substrate or a polyimide substrate, and the first insulating layer 02 can be made of polyimide, silicon oxide or silicon nitride, etc. As shown in Fig. 2, the first insulating layer 02 is formed with a via GK, the aperture of the via GK can be 2-5 microns, and preferably, the sidewall of the via GK is perpendicular to the substrate 01, which can be beneficial to reduce the planar size of the thin film transistor; as shown in Fig. 12, the active layer 05 is arranged in the via GK, the active layer 05 can be made of a metal oxide semiconductor, which can be an oxide of at least one of In, Zn, Sn, Ga and Hf, the thickness of the active layer 05 can be 200-500 nm, and the active layer 05 not only is located in the via, but also extends from the via to the side of the first insulating layer 02 away from the substrate 01, and the active layer 05 located in the via forms a fifth groove GC5; as shown in Fig. 13, the gate insulating layer 04 is arranged in the fifth groove GC5, the gate insulating layer 04 can be made of SiO2, Al2O3, HfO2, ZrO2, TiO2, MgO, CaO, SrO, BaO, La2O3, Y2O3, CeO2, Nd2O3, Gd2O3, Sm2O3, Eu2O3, Tb2O3, Dy2O3, Ho2O3, Er2O3, Tm2O3, Yb2O3, Lu2O3, etc., and the thickness of the gate insulating layer 04 can be 10-100 nm; as shown in Fig. 14, the gate electrode 03 is arranged on the gate insulating layer 04, the gate electrode 03 can be made of at least one of Ti, Al, Mo, Ta, Cr, Zr, Hf, Nb, Ag, Au, Cu, Sb, V, Ru, Pt, Zn and Mg, and the thickness of the gate electrode 03 can be 200-500 nm; as shown in Fig. 15, the source electrode 071 and the drain electrode 072 are arranged on the side of the active layer 05 away from the substrate 01, the source electrode 071 and the drain electrode 072 can be made of at least one of Ti, Al, Mo, Ta, Cr, Zr, Hf, Nb, Ag, Au, Cu, Sb, V, Ru, Pt, Zn and Mg, and the thickness of the source electrode 071 and the drain electrode 072 can be 200-500 nm. xThe gate insulating layer 04 can be 200-500 nm thick, can be located only in the fifth trench, and can extend from the fifth trench to the side of the first insulating layer 02 away from the substrate 01. The gate insulating layer 04 located in the fifth trench forms a sixth trench GC6. As shown in FIG. 14, the sixth trench is provided with a gate electrode 031. The gate electrode 031 can be made of at least one of Ti, Al, Mo, Ta, Cr, Zr, Hf, Nb, Ag, Au, Cu, Sb, V, Ru, Pt, Zn, and Mg. The thickness of the gate electrode 031 can be 200-500 nm.

[0087] As shown in FIG. 14, the thin film transistor further includes a source electrode 071 and a drain electrode 072. The source electrode 071 and the drain electrode 072 can be made of at least one of Ti, Al, Mo, Ta, Cr, Zr, Hf, Nb, Ag, Au, Cu, Sb, V, Ru, Pt, Zn, and Mg. The thickness of the source electrode 071 and the drain electrode 072 can be 200-500 nm. The active layer 05 includes a first part located in the via and a second part extending from the via to the side surface of the first insulating layer 02 away from the substrate 01. The source electrode 071 and the drain electrode 072 are located on the side of the second part away from the substrate 01.

[0088] In this embodiment, the source electrode 071 and the drain electrode 072 are located on the same horizontal plane, and the orthogonal projections of the source electrode 071 and the drain electrode 072 on the substrate 01 do not overlap. This can avoid the generation of parasitic capacitance between the source electrode 071 and the drain electrode 072, improve the subthreshold swing of the thin film transistor, and reduce the leakage current of the thin film transistor.

[0089] In this embodiment, the channel length of the thin film transistor is determined by the length of the part of the active layer and the gate electrode facing each other. As shown in FIG. 14, the channel length of the thin film transistor is equal to d4. In the case where the aperture of the via is unchanged, the channel length of the thin film transistor can be controlled by the depth of the via. When it is necessary to increase the channel length of the thin film transistor, the planar size of the thin film transistor does not need to be increased, and only the depth of the via needs to be increased. Therefore, the planar size of the thin film transistor can be reduced, and the footprint of the thin film transistor can be reduced.

[0090] Embodiments of the present disclosure also provide a display panel including the thin film transistor described above.

[0091] Embodiments of the present disclosure also provide a display device including the thin film transistor described above.

[0092] The display device includes, but is not limited to, a radio frequency unit, a network module, an audio output unit, an input unit, a sensor, a display unit, a user input unit, an interface unit, a memory, a processor, and a power supply, and the like. Those skilled in the art can understand that the structure of the display device does not constitute a limitation on the display device, and the display device can include more or less components described above, or combine certain components, or different component arrangements. In the embodiments of the present disclosure, the display device includes, but is not limited to, a display, a mobile phone, a tablet computer, a television, a wearable electronic device, a navigation display device, and the like.

[0093] The display device can be a television, a liquid crystal display, a digital photo frame, a mobile phone, a tablet computer, or any product or component with a display function, wherein the display device further includes a flexible circuit board, a printed circuit board, and a back plate.

[0094] Embodiments of the present disclosure also provide a manufacturing method of a thin film transistor, comprising:

[0095] providing a substrate;

[0096] forming a first insulating layer on the substrate, etching the first insulating layer to form a via hole;

[0097] forming a gate and an active layer in the via hole, the gate and the active layer have an overlapping area in a normal projection on a first plane perpendicular to the substrate.

[0098] In the embodiment, the first insulating layer includes the via hole, the gate and the active layer of the thin film transistor are located in the via hole, and the gate and the active layer have an overlapping area in a normal projection on a first plane perpendicular to the substrate. In this way, the channel length of the thin film transistor can be controlled by the depth of the via hole. When it is necessary to increase the channel length of the thin film transistor, the planar size of the thin film transistor does not need to be increased, and only the depth of the via hole needs to be increased. Therefore, the planar size of the thin film transistor can be reduced, and the footprint of the thin film transistor can be reduced. In addition, the vertical channel structure of the thin film transistor is beneficial to improve the bending stress resistance of the thin film transistor and is conducive to reducing the working voltage of the thin film transistor.

[0099] In a specific embodiment, as shown in FIGS. 1-9, the manufacturing method of the thin film transistor includes the following steps:

[0100] Step a1, as shown in FIG. 1, a substrate 01 is provided, and a first insulating layer 02 is formed on the substrate 01;

[0101] The substrate 01 can include a substrate, a barrier layer, a buffer layer, and the like. The substrate can adopt a glass substrate or a polyimide substrate. The first insulating layer 02 can adopt polyimide, silicon oxide, or silicon nitride, and the like.

[0102] Step a2, as shown in Fig. 2, etching the first insulating layer 02 to form a via hole GK, the aperture of the via hole GK can be 2-5 microns, preferably, the sidewall of the via hole GK is perpendicular to the substrate 01, which can be beneficial to reduce the planar size of the thin film transistor;

[0103] Step a3, as shown in Fig. 3, forming a gate metal layer 03, the gate metal layer 03 can adopt at least one of Ti, Al, Mo, Ta, Cr, Zr, Hf, Nb, Ag, Au, Cu, Sb, V, Ru, Pt, Zn and Mg, the thickness of the gate metal layer 03 can be 200-500 nm;

[0104] Step a4, as shown in Fig. 4, etching the gate metal layer 03 to form a gate electrode 031, the gate electrode 031 can cover the bottom and sidewall of the via hole GK, the gate electrode 031 can cover part of the sidewall of the via hole GK, or can cover the whole sidewall of the via hole GK, the gate electrode 031 located in the via hole forms a first groove GC1;

[0105] Step a5, as shown in Fig. 5, forming a gate insulating layer 04 in the first groove GC1, the gate insulating layer 04 can adopt at least one of SiO2, Al2O3, HfO x , the thickness of the gate insulating layer 04 can be 200-500 nm, the gate insulating layer 04 can be located only in the first groove GC1, or can extend from the first groove GC1 to the side of the first insulating layer 02 away from the substrate 01, the gate insulating layer 04 located in the first groove GC1 forms a second groove GC2;

[0106] Step a6, as shown in Fig. 6, forming an active layer 05 in the second groove GC2, the active layer 05 can adopt metal oxide semiconductor, which can be at least one of In, Zn, Sn, Ga and Hf oxide, the thickness of the active layer 05 can be 200-500 nm, the active layer 05 is not only located in the second groove GC2, but also extends from the second groove GC2 to the side of the first insulating layer 02 away from the substrate 01, the active layer 05 located in the second groove GC2 forms a third groove GC3.

[0107] Step a7, as shown in Fig. 7, forming a second insulating layer 06 filling the third groove GC3, the second insulating layer 06 can adopt organic resin, silicon oxide or silicon nitride, the thickness of the second insulating layer 06 can be 200-500 nm, the second insulating layer 06 can provide a flat surface for the subsequent formation of source and drain electrodes.

[0108] Step a8, as shown in FIG. 8, a source-drain metal layer 07 is formed, the source-drain metal layer 07 can adopt at least one of Ti, Al, Mo, Ta, Cr, Zr, Hf, Nb, Ag, Au, Cu, Sb, V, Ru, Pt, Zn and Mg, and the thickness of the source-drain metal layer 07 can be 200-500 nm;

[0109] Step a9, as shown in FIG. 9, the source-drain metal layer 07 is etched to form a source electrode 071 and a drain electrode 072. The active layer 05 includes a first part located in the via and a second part extending from the via to the surface of the first insulating layer away from the substrate; the source electrode 071 and the drain electrode 072 are located on the side of the second part away from the substrate.

[0110] In this embodiment, the source electrode 071 and the drain electrode 072 are located on the same horizontal plane, and the orthogonal projection of the source electrode 071 and the drain electrode 072 on the substrate 01 does not overlap, which can avoid the generation of parasitic capacitance between the source electrode 071 and the drain electrode 072, improve the subthreshold swing of the thin film transistor, and reduce the leakage current of the thin film transistor.

[0111] In this embodiment, the channel length of the thin film transistor is determined by the length of the part of the active layer and the gate in direct opposition, as shown in FIG. 6, the channel length of the thin film transistor is equal to d1+d2+d3, and in the case of a constant aperture of the via, the channel length of the thin film transistor can be controlled by the depth of the via. When it is necessary to increase the channel length of the thin film transistor, the planar size of the thin film transistor does not need to be increased, and only the depth of the via needs to be increased, thereby reducing the planar size of the thin film transistor and reducing the footprint of the thin film transistor.

[0112] In another embodiment, the method for manufacturing a thin film transistor includes the following steps:

[0113] Step b1, as shown in FIG. 1, a substrate 01 is provided, and a first insulating layer 02 is formed on the substrate 01;

[0114] The substrate 01 can include a substrate, a barrier layer, a buffer layer and the like, the substrate can adopt a glass substrate or a polyimide substrate, and the first insulating layer 02 can adopt polyimide, silicon oxide or silicon nitride and the like.

[0115] Step b2, as shown in FIG. 2, the first insulating layer 02 is etched to form a via GK, the aperture of the via GK can be 2-5 microns, and preferably, the sidewall of the via GK is perpendicular to the substrate 01, which can be beneficial to reduce the planar size of the thin film transistor;

[0116] Step b3, as shown in FIG. 3, a gate metal layer 03 is formed, the gate metal layer 03 can adopt at least one of Ti, Al, Mo, Ta, Cr, Zr, Hf, Nb, Ag, Au, Cu, Sb, V, Ru, Pt, Zn and Mg, and the thickness of the gate metal layer 03 can be 200-500nm;

[0117] Step b4, as shown in FIG. 4, the gate metal layer 03 is etched to form a gate electrode 031, the gate electrode 031 can cover the bottom and sidewall of the via hole GK, the gate electrode 031 can cover part of the sidewall of the via hole GK, or can cover the entire sidewall of the via hole GK, and the gate electrode 031 located in the via hole forms a first groove GC1;

[0118] Step b5, as shown in FIG. 5, a gate insulating layer 04 is formed in the first groove, the gate insulating layer 04 can adopt at least one of SiO2, Al2O3, HfO x , and the thickness of the gate insulating layer 04 can be 200-500nm, the gate insulating layer 04 can be located only in the first groove GC1, and can also extend from the first groove GC1 to the side of the first insulating layer 02 away from the substrate 01, and the gate insulating layer 04 located in the first groove GC1 forms a second groove GC2;

[0119] Step b6, as shown in FIG. 6, an active layer 05 is formed in the second groove GC2, the active layer 05 can adopt a metal oxide semiconductor, which can be an oxide of at least one of In, Zn, Sn, Ga and Hf, and the thickness of the active layer 05 can be 200-500nm, the active layer 05 is not only located in the second groove GC2, but also extends from the second groove GC2 to the side of the first insulating layer 02 away from the substrate 01, and the active layer 05 located in the second groove GC2 forms a third groove GC3.

[0120] Step b7, as shown in FIG. 10, a second insulating layer 06 is formed to fill the third groove GC3, the second insulating layer 06 can adopt organic resin, silicon oxide or silicon nitride, and the thickness of the second insulating layer 06 can be 200-500nm, and the second insulating layer 06 located in the third groove GC3 forms a fourth groove GC4.

[0121] Step b8, as shown in FIG. 11, an additional gate electrode 08 is formed in the fourth groove GC4, and the additional gate electrode 08 and the active layer 05 have an overlapping area in the orthogonal projection on the first plane perpendicular to the substrate. The additional gate electrode 08 can realize a double-gate thin film transistor, and increase the mobility of the thin film transistor.

[0122] Step b9, as shown in FIG. 11, source electrode 071 and drain electrode 072 are formed, source electrode 071 and drain electrode 072 can adopt at least one of Ti, Al, Mo, Ta, Cr, Zr, Hf, Nb, Ag, Au, Cu, Sb, V, Ru, Pt, Zn and Mg, the thickness of source electrode 071 and drain electrode 072 can be 200-500 nm, the active layer 05 includes a first part located in the via and a second part extending from the via to the first insulating layer away from the substrate side surface; source electrode 071 and drain electrode 072 are located away from the substrate side of the second part.

[0123] In this embodiment, source electrode 071 and drain electrode 072 are located in the same horizontal plane, and the orthogonal projection of source electrode 071 and drain electrode 072 on the substrate 01 does not overlap, which can avoid the generation of parasitic capacitance between source electrode 071 and drain electrode 072, improve the subthreshold swing of the thin film transistor, and reduce the leakage current of the thin film transistor.

[0124] In this embodiment, the channel length of the thin film transistor is determined by the length of the active layer and the gate opposite part. As shown in FIG. 6, the channel length of the thin film transistor is equal to d1+d2+d3. In the case of constant aperture of the via, the channel length of the thin film transistor can be controlled by the depth of the via. When it is necessary to increase the channel length of the thin film transistor, the planar size of the thin film transistor does not need to be increased, and only the depth of the via needs to be increased, thereby reducing the planar size of the thin film transistor and reducing the footprint of the thin film transistor.

[0125] In another embodiment, the method for manufacturing a thin film transistor comprises the following steps:

[0126] Step c1, as shown in FIG. 1, a substrate 01 is provided, and a first insulating layer 02 is formed on the substrate 01;

[0127] The substrate 01 can include a substrate, a barrier layer, a buffer layer and the like, the substrate can adopt a glass substrate or a polyimide substrate, and the first insulating layer 02 can adopt polyimide, silicon oxide or silicon nitride, etc.

[0128] Step c2, as shown in FIG. 2, the first insulating layer 02 is etched to form a via GK, the aperture of the via GK can be 2-5 microns, preferably, the side wall of the via GK is perpendicular to the substrate 01, which can be beneficial to reduce the planar size of the thin film transistor;

[0129] Step c3, as shown in FIG. 12, the active layer 05 is formed in the via hole GK, the active layer 05 can adopt metal oxide semiconductor, can be at least one of In, Zn, Sn, Ga and Hf oxide, the thickness of the active layer 05 can be 200-500nm, the active layer 05 not only in the via hole GK, also extends from the via hole GK to the side of the first insulating layer 02 away from the base 01, the active layer 05 in the via hole GK forms the fifth groove GC5;

[0130] Step c4, as shown in FIG. 13, the gate insulating layer 04 is formed in the fifth groove GC5, the gate insulating layer 04 can adopt at least one of SiO2, Al2O3, HfO x The thickness of the gate insulating layer 04 can be 200-500nm, the gate insulating layer 04 can be located in the fifth groove GC5, also can extend from the fifth groove GC5 to the side of the first insulating layer 02 away from the base 01, the gate insulating layer 04 in the fifth groove GC5 forms the sixth groove GC6;

[0131] Step c5, as shown in FIG. 14, the gate 031 is formed in the sixth groove GC6, the gate 031 can adopt at least one of Ti, Al, Mo, Ta, Cr, Zr, Hf, Nb, Ag, Au, Cu, Sb, V, Ru, Pt, Zn and Mg, the thickness of the gate 031 can be 200-500nm.

[0132] Step c6, as shown in FIG. 14, the source 071 and the drain 072 are formed, the source 071 and the drain 072 can adopt at least one of Ti, Al, Mo, Ta, Cr, Zr, Hf, Nb, Ag, Au, Cu, Sb, V, Ru, Pt, Zn and Mg, the thickness of the source 071 and the drain 072 can be 200-500nm, the active layer 05 includes a first part located in the via hole and a second part extending from the via hole to the side surface of the first insulating layer away from the base; The source 071 and the drain 072 are located on the side of the second part away from the base.

[0133] In the embodiment, the source 071 and the drain 072 are located in the same horizontal plane, the orthogonal projection of the source 071 and the drain 072 on the base 01 does not overlap, which can avoid the generation of parasitic capacitance between the source 071 and the drain 072, improve the subthreshold swing of the thin film transistor, and reduce the leakage current of the thin film transistor.

[0134] In the embodiment, the channel length of the thin film transistor is determined by the length of the active layer and the part of the gate electrode in direct contact, as shown in FIG. 14, the channel length of the thin film transistor is equal to d4, and in the case of a constant aperture of the via hole, the channel length of the thin film transistor can be controlled by the depth of the via hole, and when it is necessary to increase the channel length of the thin film transistor, the planar size of the thin film transistor does not need to be increased, and only the depth of the via hole needs to be increased, thereby being capable of reducing the planar size of the thin film transistor and reducing the footprint of the thin film transistor.

[0135] In the method embodiments of the present disclosure, the serial numbers of the steps cannot be used to limit the sequence of the steps, and for those skilled in the art, the sequence of the steps can be changed without creative effort, and the changed sequence is within the protection scope of the present disclosure.

[0136] It should be noted that each of the embodiments in the present specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment mainly describes the differences from other embodiments. In particular, for the embodiments, since they are basically similar to the product embodiments, the description is relatively simple, and the related parts can be referred to the part of the description of the product embodiments.

[0137] Unless otherwise defined, technical terms or scientific terms used in the present disclosure should be understood as the common meaning thereof to those skilled in the art. The terms "first", "second", and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are used to distinguish different components. The terms "include", "contain", and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms "connect" or "connected" and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms "upper", "lower", "left", "right", and the like are used to represent relative positional relationships, and when the absolute positions of the described objects change, the relative positional relationships may also change accordingly.

[0138] It can be understood that when an element such as a layer, a film, a region, or a substrate is referred to as being "on" or "under" another element, it can be "directly" on or under the other element, or there can be an intermediate element.

[0139] In the description of the above-described embodiments, specific features, structures, materials, or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0140] The above merely provides the specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto, any person skilled in the art can easily think of the changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A thin film transistor, characterized by comprising: Comprising: a substrate; a first insulating layer on the substrate, the first insulating layer comprising a via; a gate and an active layer in the via, the gate and the active layer having an overlapping region in a projection on a first plane perpendicular to the substrate.

2. The thin film transistor of claim 1, wherein: the gate covers at least part of a sidewall of the via, the gate in the via forming a first trench; a gate insulating layer covering the gate is formed in at least the first trench, the gate insulating layer in the first trench forming a second trench; an active layer covering the gate insulating layer is formed in at least the second trench, the active layer in the second trench forming a third trench.

3. The thin film transistor according to claim 2, wherein The thin film transistor further comprises: a second insulating layer filling the third trench.

4. The thin film transistor according to claim 2, wherein The thin film transistor further comprises: a second insulating layer covering the active layer is formed in at least the third trench, the second insulating layer in the third trench forming a fourth trench; an additional gate in the fourth trench, the additional gate and the active layer having an overlapping region in a projection on a first plane perpendicular to the substrate.

5. The thin film transistor of claim 1, wherein: the active layer covers at least part of a sidewall of the via, the active layer in the via forming a fifth trench; a gate insulating layer covering the active layer is formed in at least the fifth trench, the gate insulating layer in the fifth trench forming a sixth trench; the gate in the sixth trench.

6. The thin film transistor according to any one of claims 1 to 5, wherein The active layer comprises a first portion in the via and a second portion extending from the via to a surface of the first insulating layer away from the substrate; the thin film transistor further comprises: a source and a drain on a side of the second portion away from the substrate.

7. The thin film transistor according to claim 1, wherein An aperture of the via is 2-5 microns.

8. The thin film transistor according to claim 1, wherein A sidewall of the via is perpendicular to the substrate.

9. A display panel, characterized by, A device comprising the thin film transistor of any one of claims 1-8.

10. A display device, characterized by comprising: A device comprising the thin film transistor of any one of claims 1-8.

11. A method of fabricating a thin film transistor, comprising: Comprising: providing a substrate; forming a first insulating layer on the substrate, etching the first insulating layer to form a via; forming a gate and an active layer in the via, the gate and the active layer having an overlapping region in a projection on a first plane perpendicular to the substrate.

12. The method of fabricating a thin film transistor according to claim 11, wherein The forming a gate and an active layer in the via comprises: forming the gate covering at least part of a sidewall of the via, the gate in the via forming a first trench; forming a gate insulating layer covering the gate is formed in at least the first trench, the gate insulating layer in the first trench forming a second trench; forming an active layer covering the gate insulating layer is formed in at least the second trench, the active layer in the second trench forming a third trench.

13. The method of fabricating a thin film transistor according to claim 12, wherein The method further comprises: forming a second insulating layer filling the third trench.

14. The method of fabricating a thin film transistor according to claim 12, wherein The method further comprises: forming a second insulating layer covering the active layer is formed in at least the third trench, the second insulating layer in the third trench forming a fourth trench; An additional gate is formed in the fourth trench, and the additional gate and the active layer have an overlapping region in a normal projection on a first plane perpendicular to the substrate.

15. The method for fabricating a thin-film transistor according to claim 11, characterized in that, The forming the gate and the active layer in the via includes: An active layer is formed to cover at least part of the sidewall of the via, and the active layer in the via forms a fifth trench; A gate insulating layer is formed to cover at least the active layer in the fifth trench, and the gate insulating layer in the fifth trench forms a sixth trench; The gate is formed in the sixth trench.

16. The method of fabricating a thin film transistor according to any one of claims 11 to 15, wherein The active layer includes a first part in the via and a second part extending from the via to a side surface of the first insulating layer away from the substrate; The manufacturing method further includes: A source and a drain are formed on the side of the second part away from the substrate.

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