Display substrate and preparation method therefor, and display device

Abstract

A display substrate and a preparation method therefor, and a display device. The display substrate comprises: a base substrate (101); first electrodes disposed on the base substrate (101); a pixel defining layer (40) disposed on the side of the first electrodes away from the base substrate (101), wherein the pixel defining layer (40) defines pixel openings (100), and each pixel opening (100) exposes at least part of one first electrode; isolation columns (50) disposed on the side of the pixel defining layer (40) away from the base substrate (101); a light-emitting functional layer which is at least partially located in the pixel openings (100) and disposed on the side of the first electrodes away from the base substrate (101), wherein the light-emitting functional layer comprises at least one charge production layer (31), and the charge production layer (31) is separated from the isolation columns (50) at the pixel defining layer (40); and second electrodes disposed on the side of the light-emitting functional layer away from the base substrate (101) and connected to the isolation columns (50).

Description

Display substrate, preparation method thereof and display device TECHNICAL FIELD

[0001] The present disclosure relates to, but is not limited to, the technical field of display, in particular to a display substrate, a preparation method thereof and a display device. BACKGROUND

[0002] An organic light emitting diode (OLED) is an active light emitting display device, which has the advantages of self-emission, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility and low cost. With the continuous development of display technology, a display device with an OLED as a light emitting device and a thin film transistor (TFT) for signal control has become the mainstream product in the current display field.

[0003] SUMMARY

[0004] The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of protection of the claims.

[0005] The display substrate provided by the embodiments of the present disclosure comprises:

[0006] a substrate substrate;

[0007] a first electrode disposed on the substrate substrate;

[0008] a pixel definition layer disposed on a side of the first electrode away from the substrate substrate, the pixel definition layer defining a pixel opening, the pixel opening exposing at least part of the first electrode;

[0009] an isolation column disposed on a side of the pixel definition layer away from the substrate substrate;

[0010] a light emitting functional layer at least partially located in the pixel opening, disposed on a side of the first electrode away from the substrate substrate, the light emitting functional layer comprising at least one charge production layer, the charge production layer being cut off by the isolation column at the pixel definition layer; and

[0011] a second electrode disposed on a side of the light emitting functional layer away from the substrate substrate and connected with the isolation column.

[0012] In some embodiments of the display substrate, the side of the pixel definition layer away from the substrate substrate has a blocking portion, the blocking portion being close to the pixel opening.

[0013] In some embodiments of the display substrate, the side of the pixel definition layer away from the substrate substrate is provided with a groove.

[0014] The trench is located between the barrier portions;

[0015] A projection of the trench on the substrate substrate is located within a projection of the pixel defining layer on the substrate substrate.

[0016] In some embodiments of the display substrate, the trench has a first width on a side away from the substrate substrate, and a second width on a side close to the substrate substrate, the first width being greater than the second width.

[0017] In some embodiments of the display substrate, a groove depth of the trench is to

[0018] A thickness of the pixel defining layer is to

[0019] In some embodiments of the display substrate, the isolation column includes a first conductive layer and a second conductive layer, the first conductive layer being disposed between the second conductive layer and the substrate substrate;

[0020] The first conductive layer is disposed at a groove bottom of the trench, and a projection of the first conductive layer on the substrate substrate is located within a projection of the trench on the substrate substrate.

[0021] The second conductive layer and the pixel defining layer are spaced apart along a direction perpendicular to the substrate substrate.

[0022] In some embodiments of the display substrate, a spacing between the isolation column and the barrier portion is to

[0023] In some embodiments of the display substrate, materials of the first conductive layer and the second conductive layer are different.

[0024] In some embodiments of the display substrate, the barrier portion includes a first side surface and a second side surface;

[0025] The first side surface defines the trench, and the second side surface defines the pixel opening together with the pixel defining layer.

[0026] In some embodiments of the display substrate, the first side surface is inclined toward a side away from the trench, and a first included angle between the first side surface and the substrate substrate can be formed.

[0027] The second side surface is inclined toward a side away from the pixel opening, and a second included angle between the second side surface and the substrate substrate can be formed.

[0028] wherein the first angle is not equal to the second angle.

[0029] In some embodiments of the display substrate, the first angle is 30° to 60°.

[0030] The second angle is 60° to 90°.

[0031] In some embodiments of the display substrate, the first side is inclined to one side of the trench and can form a third angle with the substrate substrate;

[0032] The second side is inclined to one side of the pixel opening and can form a fourth angle with the substrate substrate.

[0033] wherein the third angle is not equal to the fourth angle.

[0034] In some embodiments of the display substrate, the third angle is 90° to 130°.

[0035] The fourth angle is 90° to 130°.

[0036] In some embodiments of the display substrate, the material of the pixel defining layer is an inorganic material.

[0037] In some embodiments of the display substrate, the material of the pixel defining layer is the same as that of the blocking portion.

[0038] In some embodiments of the display substrate, the material of the pixel defining layer is different from that of the blocking portion.

[0039] In some embodiments of the display substrate, the material of the blocking portion is an organic material.

[0040] In some embodiments of the display substrate, the second electrode has a projection on the substrate substrate that overlaps with the first electrode, the light-emitting functional layer, the pixel defining layer, the first conductive layer, and the second conductive layer.

[0041] In some embodiments of the display substrate, the second electrode has a projection on the substrate substrate that overlaps with the first conductive layer, the first side, the second side, and the charge production layer.

[0042] In some embodiments of the display substrate, the second electrode covers the first side and the second side.

[0043] The display device provided by the embodiments of the present disclosure also includes the display substrate as described above.

[0044] The embodiment of the present disclosure provides a preparation method of a display substrate, comprising:

[0045] forming a first electrode on a substrate;

[0046] forming a pixel definition layer on a side of the first electrode away from the substrate, the pixel definition layer defining a pixel opening, the pixel opening exposing at least part of the first electrode;

[0047] forming an isolation column on a side of the pixel definition layer away from the substrate;

[0048] forming a light-emitting functional layer on a side of the first electrode away from the substrate, the light-emitting functional layer being located in the pixel opening, the light-emitting functional layer comprising at least one charge production layer, the charge production layer being separated from the isolation column at the pixel definition layer; and

[0049] forming a second electrode on a side of the light-emitting functional layer away from the substrate,

[0050] the second electrode being connected with the isolation column.

[0051] Other aspects can become apparent after reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0052] The accompanying drawings are included to provide a further understanding of the present disclosure and constitute a part of the specification, which together with the detailed description, serve to explain the technical solutions of the present disclosure, but do not constitute a limitation on the technical solutions of the present disclosure.

[0053] FIG. 1 is a structural schematic diagram of a display device;

[0054] FIG. 2 is a planar structural schematic diagram of a display substrate;

[0055] FIG. 3a is a planar structural schematic diagram of a display substrate according to an embodiment of the present disclosure;

[0056] FIG. 3b is a cross-sectional structural schematic diagram of A-A in FIG. 3a;

[0057] FIG. 4a is a schematic diagram of a display substrate according to an embodiment of the present disclosure after forming a driving circuit layer, a first electrode and a pixel definition film in a preparation process;

[0058] FIG. 4b is a schematic diagram of a display substrate according to an embodiment of the present disclosure after forming a photoresist film and performing an exposure process;

[0059] FIG. 4c is a schematic diagram of a display substrate according to an embodiment of the present disclosure after forming a first photoresist pattern;

[0060] FIG. 4d is a schematic view showing a process of preparing a display substrate according to an embodiment of the present disclosure, in which a pixel defining layer is formed and excess photoresist film is covered;

[0061] FIG. 4e is a schematic view showing a process of preparing a display substrate according to an embodiment of the present disclosure, in which a pixel defining layer is formed and excess photoresist film is removed;

[0062] FIG. 4f is a schematic view showing a process of preparing a display substrate according to an embodiment of the present disclosure, in which a second conductive film and a third conductive film are formed;

[0063] FIG. 4g is a schematic view showing a process of preparing a display substrate according to an embodiment of the present disclosure, in which a second photoresist pattern is formed;

[0064] FIG. 4h is a schematic view showing a process of preparing a display substrate according to an embodiment of the present disclosure, in which a first transition conductive layer and a second transition conductive layer are formed;

[0065] FIG. 4i is a schematic view showing a process of preparing a display substrate according to an embodiment of the present disclosure, in which a spacer is formed;

[0066] FIG. 4j is a schematic view showing a process of preparing a display substrate according to an embodiment of the present disclosure, in which a light emitting functional layer and a second electrode are formed;

[0067] FIG. 4k is a schematic view showing a process of preparing a display substrate according to an embodiment of the present disclosure, in which a pixel defining layer is formed;

[0068] FIG. 5 is a schematic view showing a process of preparing a display substrate according to another embodiment of the present disclosure, in which a pixel defining layer is formed;

[0069] FIG. 6a is a schematic view showing a planar structure of another display substrate according to an embodiment of the present disclosure;

[0070] FIG. 6b is a schematic view showing a cross-sectional structure along B-B of FIG. 6a;

[0071] FIG. 7a is a schematic view showing a process of preparing a display substrate according to an embodiment of the present disclosure, in which a driving circuit layer, a first electrode, and a pixel defining film are formed;

[0072] FIG. 7b is a schematic view showing a process of preparing a display substrate according to an embodiment of the present disclosure, in which a first defining layer is formed;

[0073] FIG. 7c is a schematic view showing a process of preparing a display substrate according to an embodiment of the present disclosure, in which a second conductive film and a third conductive film are formed;

[0074] FIG. 7d is a schematic view showing a process of preparing a display substrate according to an embodiment of the present disclosure, in which a second photoresist pattern is formed;

[0075] FIG. 7e is a schematic view showing a process of preparing a display substrate according to an embodiment of the present disclosure, in which a first transition conductive layer and a second transition conductive layer are formed;

[0076] FIG. 7f is a schematic view showing a process of preparing a display substrate according to an embodiment of the present disclosure, in which a spacer is formed;

[0077] FIG. 7g is a schematic view of a preparation process of a substrate after forming a boundary layer according to an embodiment of the present disclosure;

[0078] FIG. 7h is a schematic view of a preparation process of a substrate after forming a light-emitting functional layer and a second electrode according to an embodiment of the present disclosure;

[0079] FIG. 7i is a partial enlarged view of FIG. 7g;

[0080] FIG. 8 is a schematic view of a preparation process of a substrate after forming a boundary layer according to another embodiment of the present disclosure;

[0081] FIGS. 9a-9e are schematic views of a pixel arrangement and a position relationship of a partition structure in a substrate according to an embodiment of the present disclosure;

[0082] Legend of reference numerals: 101, substrate; 102, driving circuit layer; 103, pixel boundary film; 104, photoresist film; 1041, low-cured area; 1042, high-cured area; 1043, uncured area; 105, first photoresist pattern; 106, second conductive film; 107, third conductive film; 108, first transition conductive layer; 109, second transition conductive layer; 110, second photoresist pattern; 111, first boundary film; 11, first color anode; 12, second color anode; 13, third color anode; 21, first color cathode; 22, second color cathode; 23, third color cathode; 31, charge production layer; 32, first light-emitting layer; 33, second light-emitting layer; 40, pixel boundary layer; 41, first top surface; 42, first bottom surface; 43, first side surface; 44, second side surface; 45, blocking portion; 461, second top surface; 462, second bottom surface; 463, second side surface; 47, boundary layer; 48, first side surface; 49, third bottom surface; 50, isolation column; 51, first conductive layer; 511, first surface; 512, second surface; 513, first sidewall; 514, first recess; 52, second conductive layer; 521, third surface; 522, fourth surface; 523, second recess; 60, encapsulation layer; 100, pixel opening; 200, trench. DETAILED DESCRIPTION

[0083] In order to make the objects, technical solutions and advantages of the present disclosure clearer, the following will be used to specifically explain the embodiments of the present disclosure with reference to the drawings. It should be noted that the embodiments can be implemented in a variety of different forms. Those skilled in the art can easily understand that the modes and contents can be changed into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. The embodiments in the present disclosure and the features in the embodiments can be combined with each other arbitrarily without conflict.

[0084] The proportions of the drawings in the present disclosure can be used as a reference in the actual process, but are not limited thereto. For example, the width-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are also not limited to the number shown in the drawings. The drawings described in the present disclosure are only schematic structural diagrams, and one embodiment of the present disclosure is not limited to the shapes or values shown in the drawings.

[0085] In the present specification, ordinal numbers such as "first", "second", "third", and the like are provided to avoid confusion of constituent elements, and are not intended to be limited in terms of numbers.

[0086] In the present specification, for the convenience of explanation, words indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to explain the positional relationship of the constituent elements with reference to the drawings, and are only for the convenience of describing the present specification and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction of describing each constituent element. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0087] In the present specification, unless specifically defined and limited otherwise, the terms "mount", "connected", "connection" should be interpreted broadly. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate piece, or the communication inside two elements. Those skilled in the art can understand the specific meaning of the above terms in the present disclosure according to the specific circumstances.

[0088] In this specification, a transistor means an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (a drain electrode terminal, a drain region, or a drain electrode) and the source electrode (a source electrode terminal, a source region, or a source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that, in this specification, the channel region means a region where current flows mainly.

[0089] In this specification, the first terminal can be a drain electrode and the second terminal can be a source electrode, or the first terminal can be a source electrode and the second terminal can be a drain electrode. The functions of the "source electrode" and the "drain electrode" are sometimes interchanged with each other in the case of using a transistor whose polarity is reversed or in the case where the direction of current flowing in a circuit is changed, and the like. Therefore, in this specification, the "source electrode" and the "drain electrode" can be interchanged with each other, and the "source terminal" and the "drain terminal" can be interchanged with each other.

[0090] In this specification, "electrically connected" includes the case where components are connected through an element having some function of electricity. The element having some function of electricity is not particularly limited as long as electric signals can be transmitted and received between components to be connected. Examples of the element having some function of electricity include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, and another element having some function.

[0091] In this specification, "parallel" means a state where an angle formed between two straight lines is greater than or equal to -10° and less than or equal to 10°, and thus includes a state where the angle is greater than or equal to -5° and less than or equal to 5°. In addition, "perpendicular" means a state where an angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°, and thus includes a state where the angle is greater than or equal to 85° and less than or equal to 95°.

[0092] In this specification, a "film" and a "layer" can be interchanged with each other. For example, a "conductive layer" can be replaced with a "conductive film". Similarly, an "insulating film" can be replaced with an "insulating layer".

[0093] In this specification, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, and the like are not strictly limited to these shapes, and can be approximately a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, and can have some small deformation due to a tolerance, can have a rounded corner, a curved side, and deformation, and the like.

[0094] In this specification, "about" means not strictly limited to the limit, and allows a range of values within a process and measurement error.

[0095] OLED evaporation process uses multiple high-precision metal mask plates (Fine Metal Mask, hereinafter referred to as: FMM), which greatly increases the production cost of OLED. Now many technologies consider how to use FMM-free pixel patterning, such as inkjet printing, isolation column and photolithography process to realize pixel patterning (Advanced Patterning, hereinafter referred to as: AP) technology. The AP technology evaporates organic light-emitting materials on the substrate, and the pixel is patterned through the isolation column and the photolithography process, in which the isolation column plays the role of cutting off and lapping with the cathode (CTD) conductive. The OLED produced by the AP technology has the advantages of large pixel aperture ratio, low power consumption, high brightness realization, pixel-level packaging, etc.

[0096] The present inventors have found that for a tandem OLED light-emitting device, the charge generation layer (CGL) in the tandem OLED light-emitting device is prone to short circuit (Short) with the existing isolation column, resulting in abnormal display of the product. Fluctuations in organic light-emitting materials, evaporation processes, etc. can also cause the charge generation layer (CGL) to short circuit (Short) with the existing isolation column.

[0097] FIG. 1 is a structural schematic diagram of a display device. As shown in FIG. 1, the display device can include a timing controller, a data signal driver, a scan signal driver, and a pixel array, which can include a plurality of scan signal lines (S1 to Sm), a plurality of data signal lines (D1 to Dn), and a plurality of sub-pixels Pxij.

[0098] In an exemplary embodiment, the timing controller can provide a grayscale value and a control signal suitable for the specification of the data signal driver to the data signal driver, can provide a clock signal, a scan start signal, and the like suitable for the specification of the scan signal driver to the scan signal driver. The data signal driver can generate a data voltage to be provided to the data signal lines D1, D2, D3, …, and Dn using the grayscale value and the control signal received from the timing controller. For example, the data signal driver can sample the grayscale value using the clock signal, and apply a data voltage corresponding to the grayscale value to the data signal lines D1 to Dn in units of sub-pixel behavior, n can be a natural number. The scan signal driver can generate a scan signal to be provided to the scan signal lines S1, S2, S3, …, and Sm by receiving the clock signal, the scan start signal, and the like from the timing controller. For example, the scan signal driver can sequentially provide a scan signal having an on-level pulse to the scan signal lines S1 to Sm. For example, the scan signal driver can be configured in the form of a shift register, and can generate a scan signal in a manner of sequentially transferring a scan start signal provided in the form of an on-level pulse to a next stage circuit under the control of a clock signal, m can be a natural number. The sub-pixel array can include a plurality of pixel sub-PXij. Each pixel sub-PXij can be connected to a corresponding data signal line and a corresponding scan signal line, i and j can be natural numbers. The sub-pixel PXij can refer to a sub-pixel in which a transistor is connected to an i-th scan signal line and connected to a j-th data signal line.

[0099] FIG. 2 is a schematic diagram of a planar structure of a display device. As shown in FIG. 2, the display area of the display device can include a plurality of pixel units P arranged in a matrix manner along a first direction D1 and a second direction D2, at least one of the plurality of pixel units P can include a first sub-pixel P1 emitting first color light, a second sub-pixel P2 emitting second color light, and a third sub-pixel P3 emitting third color light, the first sub-pixel P1 can include a pixel driving circuit and a first color light emitting device. The second sub-pixel P2 can include a pixel driving circuit and a second color light emitting device. The third sub-pixel P3 can include a pixel driving circuit and a third color light emitting device. The pixel driving circuits in the sub-pixels are respectively connected to scan signal lines and data signal lines, and are configured to receive data voltages transmitted by the data signal lines under the control of the scan signal lines, and output corresponding currents to the light emitting devices. The light emitting devices in the sub-pixels are respectively connected to the pixel driving circuits in the sub-pixels where the light emitting devices are located, and are configured to emit light with corresponding brightness in response to the currents output by the pixel driving circuits in the sub-pixels where the light emitting devices are located. Wherein, the first direction D1 and the second direction D2 are both parallel to the substrate 101, the first direction D1 and the second direction D2 intersect, for example, the first direction D1 and the second direction D2 are perpendicular to each other.

[0100] In an example embodiment, the first sub-pixel P1 can be a red sub-pixel emitting red (R) light, the second sub-pixel P2 can be a blue sub-pixel emitting blue (B) light, and the third sub-pixel P3 can be a green sub-pixel emitting green (G) light. In an example embodiment, the shape of the light emitting device of the sub-pixel can be any one or more of a triangle, a square, a rectangle, a diamond, a trapezoid, a parallelogram, a pentagon, a hexagon, and other polygons, and the plurality of sub-pixels in one pixel unit can be arranged in a horizontal side-by-side manner, a vertical side-by-side manner, an X shape, a cross shape, a pin shape, a square shape, a diamond shape, a Delta, a Real RGB, or a PenTile, without limitation in the present disclosure.

[0101] In an example embodiment, the pixel unit can include four sub-pixels, without limitation in the present disclosure.

[0102] The present disclosure provides a display substrate, which can include:

[0103] a substrate 101;

[0104] a first electrode disposed on the substrate 101;

[0105] a pixel defining layer 40 disposed on a side of the first electrode away from the substrate 101, the pixel defining layer 40 defining a pixel opening 100 exposing at least part of the first electrode;

[0106] an isolation column 50 disposed on a side of the pixel defining layer 40 away from the substrate 101;

[0107] a light emitting functional layer at least partially located in the pixel opening 100, disposed on a side of the first electrode away from the substrate 101, the light emitting functional layer including at least one charge production layer 31, the charge production layer 31 being blocked by the isolation column 50 at the pixel defining layer 40; and

[0108] a second electrode disposed on a side of the light emitting functional layer away from the substrate 101 and connected with the isolation column 50.

[0109] The display substrate of the present disclosure is illustrated below by some example embodiments.

[0110] FIG. 3a is a schematic diagram of a planar structure of a display substrate according to an embodiment of the present disclosure. FIG. 3b is a schematic diagram of a cross-sectional structure along A-A direction in FIG. 3a. As shown in FIG. 3a, the pixel defining layer 40 of the display substrate defines a plurality of pixel openings 100 arranged in a matrix along a first direction D1 and a second direction D2, and each pixel opening 100 is provided with a light emitting device of a sub-pixel. Each light emitting device of a sub-pixel can include at least a first electrode (anode), a light emitting functional layer, and a second electrode (cathode). The first electrode can be connected with a pixel driving circuit, the light emitting functional layer is connected with the first electrode, and the second electrode is connected with the light emitting functional layer. The second electrode is connected with a second power supply line (VSS) through an isolation column 50, and the light emitting functional layer emits light under the driving of the first electrode and the second electrode. The light emitting functional layer can include at least one charge generation layer 31 (CGL) and a plurality of sub-light emitting functional layers, and one charge generation layer 31 (CGL) is sandwiched between two sub-light emitting functional layers. Wherein, the plurality of indicates a number of two or more. The sub-light emitting functional layer can include a light emitting layer (EML) and any one or more of a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). The light emitting layer can be red, blue, or green.

[0111] The charge generation layer 31 (CGL) in each light emitting device of a sub-pixel is blocked by the isolation column 50 at the pixel defining layer 40. The display substrate further includes the isolation column 50. The isolation column 50 is disposed on a side of the pixel defining layer 40 away from the substrate 101. The charge generation layer 31 (CGL) in each light emitting device of a sub-pixel is blocked by the isolation column 50 at the pixel defining layer 40, so that the charge generation layer 31 (CGL) is not in contact with the isolation column 50, avoiding short circuit. The second electrode of each light emitting device of a sub-pixel can be electrically connected with the isolation column 50. As shown in FIG. 3b, in a direction perpendicular to the display substrate (for example, a third direction D3), the display substrate can include a substrate 101, a driving circuit layer 102 disposed on the substrate 101, a light emitting structure layer disposed on a side of the driving circuit layer 102 away from the substrate 101, and an encapsulation layer 60 disposed on a side of the light emitting structure layer away from the substrate 101. In some possible implementation manners, the display device can include other film layers, for example, a color film structure layer and a touch structure layer disposed on a side of the encapsulation layer 60 away from the substrate 101, which are not limited herein.

[0112] In an example embodiment, the substrate 101 can be a silicon substrate 101, a glass substrate 101 or a flexible substrate 101. The driving circuit layer 102 can include pixel driving circuits and traces, etc., which can include gate lines, initial signal lines, reference signal lines, data lines, first power lines (VDD), second power lines (VSS), etc. The pixel driving circuits can include transistors.

[0113] In an example embodiment, the light emitting structure layer can include a plurality of light emitting devices, which can include at least a first electrode (anode), a light emitting functional layer and a second electrode (cathode), the first electrode can be connected with the pixel driving circuit, the light emitting functional layer is connected with the first electrode, the second electrode is connected with the light emitting functional layer, the second electrode is connected with the second power line (VSS) through the isolation column 50, and the light emitting functional layer emits light under the driving of the first electrode and the second electrode.

[0114] In an example embodiment, the light emitting functional layer is located in the pixel opening 100 and is arranged on the side of the first electrode away from the substrate 101. The light emitting functional layer includes at least one charge production layer 31 (CGL), and the charge production layer 31 is blocked at the pixel defining layer 40 from the isolation column 50, so as to avoid the charge production layer 31 (CGL) from contacting the isolation column 50 and causing short circuit.

[0115] In an example embodiment, the plurality of first electrodes can include a first color anode 11, a second color anode 12 and a third color anode 13. The plurality of second electrodes can include a first color cathode 21, a second color cathode 22 and a third color cathode 23. The plurality of light emitting functional layers can include a first light emitting functional layer, a second light emitting functional layer and a third light emitting functional layer. The first color anode 11, the first light emitting functional layer and the first color cathode 21 form a first color light emitting device of a first sub-pixel P1. The second color anode 12, the second light emitting functional layer and the second color cathode 22 form a second color light emitting device of a second sub-pixel P2. The third color anode 13, the third light emitting functional layer and the third color cathode 23 form a third color light emitting device of a third sub-pixel P3.

[0116] In an example embodiment, the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 can be arranged in a triangular shape, a diamond shape, Delta, Dimond, Real RGB or PenTile, etc., which is not limited in the present disclosure. The pixel defining layer 40 is arranged in a non-light emitting area between pixels, which can ensure that the pixel aperture ratio is not reduced, and different pixel arrangement designs have corresponding pixel defining layer 40 design schemes, as shown in FIGS. 9a-9e.

[0117] In an exemplary embodiment, the plurality of pixel openings 100 can include a first color pixel opening 100, a second color pixel opening 100, and a third color pixel opening 100.

[0118] The first color pixel opening 100 exposes the first color anode 11, and a first light emitting functional layer is located within the first color pixel opening 100 and covers a side of the first color anode 11 away from the substrate 101. A first color cathode 21 is located on a side of the first light emitting functional layer away from the substrate 101.

[0119] The second color pixel opening 100 exposes the second color anode 12, and a second light emitting functional layer is located within the second color pixel opening 100 and covers a side of the second color anode 12 away from the substrate 101. A second color cathode 22 is located on a side of the second light emitting functional layer away from the substrate 101.

[0120] The third color pixel opening 100 exposes the third color anode 13, and a third light emitting functional layer is located within the third color pixel opening 100 and covers a side of the third color anode 13 away from the substrate 101. A third color cathode 23 is located on a side of the third light emitting functional layer away from the substrate 101.

[0121] In an exemplary embodiment, the first electrode can be a stacked structure of indium tin oxide (ITO) / silver (Ag) / indium tin oxide (ITO).

[0122] In an exemplary embodiment, the first light emitting functional layer can include two sub light emitting functional layers and a charge generation layer 31 (CGL) located between the two sub light emitting functional layers, and the sub light emitting functional layers can include one light emitting layer (EML) and any one or more of a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). The light emitting layer can be red, blue, or green.

[0123] In an exemplary embodiment, the second light emitting functional layer can include two sub light emitting functional layers and a charge generation layer 31 (CGL) located between the two sub light emitting functional layers, and the sub light emitting functional layers can include one light emitting layer (EML) and any one or more of a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). The light emitting layer can be red, blue, or green.

[0124] In an exemplary embodiment, the third light-emitting functional layer can include two sub light-emitting functional layers and a charge generation layer 31 (CGL) located between the two sub light-emitting functional layers, and the sub light-emitting functional layer can include one light-emitting layer (EML) and any one or more of a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). The light-emitting layer can be red, blue, or green.

[0125] In an exemplary embodiment, the pixel opening 100 exposes at least part of a first electrode. By using the pixel defining layer 40 between the sub-pixels, the color mixing problem between the sub-pixels and the crosstalk problem between the sub-pixels when driving at low brightness can be fundamentally solved, and the display clarity, color performance (color gamut), uniformity, and other image quality performance are further improved. The isolation column 50 is arranged on the side of the pixel defining layer 40 away from the substrate 101 and is connected with the second electrode.

[0126] In an exemplary embodiment, please refer to FIGS. 3b, 4i, 4j, 6b, 7f, 7g, 7h, and 8, the isolation column 50 can include a first conductive layer 51 and a second conductive layer 52, and the first conductive layer 51 is arranged between the second conductive layer 52 and the substrate 101.

[0127] The orthogonal projection width of the first conductive layer 51 on the substrate 101 is smaller than the orthogonal projection width of the second conductive layer 52 on the substrate 101, and the orthogonal projection of the first conductive layer 51 on the substrate 101 is located within the orthogonal projection of the second conductive layer 52 on the substrate 101. The orthogonal projection width of the first conductive layer 51 on the substrate 101 refers to the size of the orthogonal projection of the first conductive layer 51 on the substrate along the first direction D1, and the orthogonal projection width of the second conductive layer 52 on the substrate 101 refers to the size of the orthogonal projection of the second conductive layer 52 on the substrate 101 along the first direction D1. In this way, in the process of forming the light-emitting functional layer, the second conductive layer 52 can shield the light-emitting functional layer material, avoiding the light-emitting functional layer material from contacting the first conductive layer 51, and the light-emitting functional layer material is more likely to be deposited in the pixel opening 100 to form the light-emitting functional layer. In the process of forming the second electrode, the second conductive layer 52 can shield the second electrode material, and the second electrode material is deposited on the side of the light-emitting functional layer away from the substrate 101. As the second electrode material is deposited, the second electrode material can overflow from the pixel opening 100 to contact the first conductive layer 51, so that the first conductive layer 51 can be connected with the second power supply line (VSS).

[0128] In an exemplary embodiment, please refer to FIG. 4i, FIG. 4j, FIG. 7f, FIG. 7g, FIG. 7h and FIG. 8, the first conductive layer 51 has a first surface 511 away from the substrate 101, a second surface 512 close to the substrate 101, and a first sidewall 513 connecting the first surface 511 and the second surface 512. The second surface 512 on the substrate 101 covers the first surface 511 on the substrate 101. In this way, the first conductive layer 51 has a narrow-top-wide-bottom structure.

[0129] At least part of the second electrode covers the first sidewall 513.

[0130] In an exemplary embodiment, please refer to FIG. 4i, FIG. 4j, FIG. 7f, FIG. 7g, FIG. 7h and FIG. 8, the first sidewall 513 is recessed to the inner side of the first conductive layer 51, which can reduce the risk of the second electrode breaking, increase the area of the connecting surface between the first conductive layer 51 and the second electrode, and improve the stability of the connection between the first conductive layer 51 and the second electrode.

[0131] In an exemplary embodiment, please refer to FIG. 4i, FIG. 4j, FIG. 7f, FIG. 7g, FIG. 7h and FIG. 8, the second conductive layer 52 has a third surface 521 away from the substrate 101 and a fourth surface 522 close to the substrate 101, and the fourth surface 522 on the substrate 101 covers the third surface 521 on the substrate 101. In this way, the second conductive layer 52 has a narrow-top-wide-bottom structure.

[0132] In an exemplary embodiment, the materials of the first conductive layer 51 and the second conductive layer 52 can be different. In this way, in the process of forming the first conductive layer 51 and the second conductive layer 52 by wet etching, the wet etching solution can use a wet etching solution with a high selectivity ratio of the first conductive layer 51, which is conducive to forming the morphology of the isolation column 50, i.e., the second conductive layer 52 with a narrow-top-wide-bottom structure and the first conductive layer 51 with a narrow-top-wide-bottom structure and the first sidewall 513 recessed to the inner side of the first conductive layer 51. In addition, the wet etching solution also needs to consider the etching effect on the upper layer material of the first electrode, and use a wet etching solution that satisfies the high selectivity ratio of the first conductive layer 51 and has a small etching effect on the upper layer material of the first electrode.

[0133] In an exemplary embodiment, please refer to FIG. 4e, FIG. 4i, FIG. 4j, FIG. 7g, FIG. 7h and FIG. 8, the side of the pixel definition layer 40 away from the substrate 101 has a blocking part 45 close to the pixel opening 100, which is configured to separate the charge generation layer 31 (CGL) from the isolation column 50. The side of the pixel definition layer 40 away from the substrate 101 is provided with a groove 200. The groove 200 is located between the blocking parts 45.

[0134] The trench 200 extends toward the substrate substrate 101 to form the barrier portion 45 on both sides of the trench 200 on the side of the pixel defining layer 40 away from the substrate substrate 101. The orthogonal projection of the trench 200 on the substrate substrate 101 is within the orthogonal projection of the pixel defining layer 40 on the substrate substrate 101.

[0135] The first conductive layer 51 is disposed on the bottom of the trench 200, and the orthogonal projection of the first conductive layer 51 on the substrate substrate 101 is within the orthogonal projection of the trench 200 on the substrate substrate 101. The second conductive layer 52 and the pixel defining layer 40 are spaced apart in a direction perpendicular to the substrate substrate 101. In this way, by adjusting the depth of the trench 200, the position of the first conductive layer 51 relative to the substrate substrate 101 in a direction perpendicular to the substrate substrate 101 can be adjusted, thereby adjusting the distance between the second conductive layer 52 and the pixel defining layer 40 in a direction perpendicular to the substrate substrate 101. In the process of forming the light-emitting functional layer and the second electrode, in addition to the shielding effect of the second conductive layer 52 on the light-emitting functional layer material and the second electrode material, the distance can also be adjusted, the evaporation and deposition position of the light-emitting functional layer material on the isolation column 50 can be adjusted, the light-emitting functional layer material can be prevented from contacting the first conductive layer 51, and after the second electrode material overflows from the pixel opening 100, the second electrode material can enter the trench 200 through the distance, thereby increasing the contact area between the second electrode and the first conductive layer 51.

[0136] In an example embodiment, as shown in FIGS. 3a and 6a, the axis L1 of the orthogonal projection of the first conductive layer 51 on the substrate substrate 101 coincides with the axis L2 of the orthogonal projection of the trench 200 on the substrate substrate 101. It can be understood that in other embodiments, the axis L1 of the orthogonal projection of the first conductive layer 51 on the substrate substrate 101 does not coincide with the axis L2 of the orthogonal projection of the trench 200 on the substrate substrate 101, and is offset to one side of the orthogonal projection of one of the two barrier portions 45 on the substrate substrate 101.

[0137] In an example embodiment, please refer to FIGS. 4i, 4j, 7g, 7h and 8, the orthogonal projection of the second conductive layer 52 on the substrate substrate 101 covers the orthogonal projection of the trench 200 on the substrate substrate 101. In this way, the second conductive layer 52 can prevent the light-emitting functional layer material from falling into the trench 200 and affecting the subsequent contact between the second electrode and the first conductive layer 51.

[0138] In an example embodiment, please refer to FIGS. 4e, 4h, 4i and 4j together, the pixel defining layer 40 includes a first top surface 41 away from the substrate substrate 101 and a first bottom surface 42 close to the substrate substrate 101.

[0139] The barrier portion 45 includes a first side surface 43 and a second side surface 44.

[0140] The first top surface 41 is located on the side of the barrier portion 45 away from the substrate 101. The first side surface 43 defines the trench 200, and the second side surface 44 and the pixel defining layer 40 together define the pixel opening 100.

[0141] In an example embodiment, as shown in FIG. 4i, the distance between the isolation column 50 and the barrier portion 45 is to wherein the distance refers to the distance between the side of the isolation column 50 facing the barrier portion 45 and the side of the barrier portion 45 facing the isolation column 50.

[0142] In an example embodiment, the first conductive layer 51 and the second conductive layer 52 are made of different materials.

[0143] In an example embodiment, the trench 200 has a first width W1 on the side away from the substrate 101, and a second width W2 on the side close to the substrate 101. The first width W1 refers to the dimension of the trench 200 along the first direction D1 on the side away from the substrate 101. The second width W2 refers to the dimension of the trench 200 along the first direction D1 on the side close to the substrate 101. The first width W1 is greater than the second width W2, as shown in FIG. 4e. In this way, the width of the two ends of the trench 200 along the direction perpendicular to the substrate 101 (the third direction D3) is different, i.e., the width of the side of the trench 200 away from the substrate 101 is greater than the width of the side of the trench 200 close to the substrate 101, and the trench 200 has an inverted trapezoidal shape with a wide top and a narrow bottom, which facilitates the second electrode material overflowing from the pixel opening 100 to enter the trench 200.

[0144] In an example embodiment, the groove depth of the trench 200 can be about to The thickness of the pixel defining layer 40 is to In this way, the trench 200 does not penetrate the pixel defining layer 40, causing damage to the layer structure between the pixel defining layer 40 and the substrate 101, for example, the driving circuit layer 102. In the embodiment of the present disclosure, the thickness of the pixel defining layer 40 between the bottom of the trench 200 and the driving circuit layer 102 can be about to

[0145] In an example embodiment, as shown in FIG. 4e and FIG. 4k, the first side surface 43 is inclined to the side away from the trench 200, and can form a first included angle a1 with the substrate 101.

[0146] The second side 44 is inclined to a side away from the pixel opening 100, and can form a second included angle a2 with the substrate 101. By adjusting the size of the first included angle a1 and the second included angle a2, the distance between the isolation column 50 and the first side 43 and the size of the pixel opening 100 can be adjusted, so that the charge generation layer 31 (CGL) is blocked by the isolation column 50 at the blocking part 45, so that the charge generation layer 31 (CGL) does not contact the isolation column 50, avoids short circuit, and facilitates the second electrode material to enter the groove 200, thereby increasing the contact area between the second electrode and the isolation column 50.

[0147] The first included angle a1 and the second included angle a2 are not equal. For example, the first included angle a1 can be smaller than the second included angle a2. The smaller the first included angle a1, the flatter the slope of the first side 43, which is more conducive to improving the second electrode film forming effect and reducing the second electrode load. The larger the second included angle a2, the steeper the slope of the second side 44, which is more conducive to preventing the charge generation layer 31 (CGL) from contacting the isolation column 50 over the blocking part 45. It can be understood that in other embodiments, the first included angle a1 and the second included angle a2 can also be equal.

[0148] In an exemplary embodiment, the first included angle a1 is 30° to 60°. The second included angle a2 is 60° to 90°.

[0149] In an exemplary embodiment, please refer to Figures 7g and 7i, the first side 43 is inclined to a side of the groove 200, and can form a third included angle a3 with the substrate 101.

[0150] The second side 44 is inclined to a side of the pixel opening 100, and can form a fourth included angle a4 with the substrate 101. By adjusting the size of the third included angle a3 and the fourth included angle a4, the distance between the isolation column 50 and the first side 43 and the size of the pixel opening 100 can be adjusted, so that the charge generation layer 31 (CGL) is blocked by the isolation column 50 at the blocking part 45, so that the charge generation layer 31 (CGL) does not contact the isolation column 50, avoids short circuit.

[0151] The third included angle a3 and the fourth included angle a4 are not equal. It can be understood that in other embodiments, the third included angle a3 and the fourth included angle a4 can also be equal.

[0152] In an exemplary embodiment, the third included angle a3 is 90° to 130°. The fourth included angle a4 is 90° to 130°.

[0153] In an exemplary embodiment, the material of the pixel defining layer 40 is inorganic material. The pixel defining layer 40 made of inorganic material can effectively block water vapor, especially during the subsequent wet etching process of the isolation column 50, so as to avoid water vapor entering the light emitting device. If the pixel defining layer 40 is made of organic material, the water absorption of the organic material will affect the reliability of the light emitting device, and during the subsequent wet etching process of the isolation column 50, the etching liquid will also corrode the organic material.

[0154] In an exemplary embodiment, the material of the pixel defining layer 40 is the same as that of the blocking portion 45.

[0155] In an exemplary embodiment, the material of the pixel defining layer 40 is different from that of the blocking portion 45.

[0156] In an exemplary embodiment, the material of the blocking portion 45 is organic material.

[0157] In an exemplary embodiment, please refer to FIG. 3b and FIG. 4j together, the orthogonal projection of the second electrode on the substrate 101 overlaps with the orthogonal projection of the first electrode, the light emitting functional layer, the pixel defining layer 40, the first conductive layer 51 and the second conductive layer 52 on the substrate 101, respectively. For example, the orthogonal projection of the second electrode on the substrate 101 covers the orthogonal projection of the first electrode, the light emitting functional layer, the first side surface 43, the first top surface 41 and the second side surface 44 on the substrate 101.

[0158] In an exemplary embodiment, the orthogonal projection of the second electrode on the substrate 101 overlaps with the orthogonal projection of the first conductive layer 51, the first side surface 43, the second side surface 44 and the charge generation layer 31 (CGL) on the substrate 101, respectively. For example, the orthogonal projection of the second electrode on the substrate 101 covers the orthogonal projection of the first side surface 43, the second side surface 44 and the charge generation layer 31 (CGL) on the substrate 101. The orthogonal projection of the second electrode on the substrate 101 covers part of the first conductive layer 51.

[0159] In an exemplary embodiment, please refer to FIG. 3b and FIG. 4j, the second electrode covers the first side surface 43, the first top surface 41 and the second side surface 44. In this way, the second electrode can wrap the side of the blocking portion 45 away from the substrate 101, increase the connection area between the second electrode and the blocking portion 45, improve the connection stability between the second electrode and the blocking portion 45, and ensure the electrical connection stability between the second electrode and the first conductive layer 51.

[0160] The preparation process of the display substrate is exemplarily illustrated below. The "patterning process" in the present disclosure includes coating photoresist, mask exposure, development, etching, stripping photoresist and the like for metal material, inorganic material or transparent conductive material, and includes coating organic material, mask exposure and development and the like for organic material. The deposition can adopt any one or more of sputtering, evaporation, chemical vapor deposition, the coating can adopt any one or more of spraying, spin coating and inkjet printing, and the etching can adopt any one or more of dry etching and wet etching, which are not limited in the present disclosure. The "thin film" refers to a thin film of a certain material on the substrate 101 prepared by deposition, coating or other processes. If the "thin film" does not need to be patterned during the entire preparation process, the "thin film" can also be referred to as a "layer". If the "thin film" needs to be patterned during the entire preparation process, it is referred to as a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" in the present disclosure means that A and B are formed at the same time by the same patterning process. The "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps the boundary of the orthographic projection of B.

[0161] In the exemplary embodiments, the preparation process of the display substrate can include the following operations.

[0162] 1.1, forming the driving circuit layer 102, the first electrode and the pixel defining film 103.

[0163] In the exemplary embodiments, forming the driving circuit layer 102, the first electrode and the pixel defining film 103 can include: first forming the driving circuit layer 102 on the substrate 101; then, depositing a layer of first conductive film on the side of the driving circuit layer 102 away from the substrate 101, and patterning the first conductive film by photolithography to form the first electrode arranged on the side of the driving circuit layer 102 away from the substrate 101; then, depositing a layer of pixel defining film 103 covering the first electrode on the side of the driving circuit layer 102 away from the substrate 101. The plurality of first electrodes can include a first color anode 11, a second color anode 12 and a third color anode 13, as shown in FIG. 4a.

[0164] In the exemplary embodiments, the first color anode 11, the second color anode 12 and the third color anode 13 can be a stacked structure of indium tin oxide (ITO) / silver (Ag) / indium tin oxide (ITO).

[0165] In the example embodiment, the driving circuit layer 102 can include a gate driving circuit, an electrostatic protection circuit, an initialization circuit, a pixel internal compensation circuit, a pixel driving circuit, and a wire, etc. The wire can include a gate line, an initial signal line, a reference signal line, a data line, a first power line (VDD), a second power line (VSS), etc. The pixel driving circuit, the gate driving circuit, the electrostatic protection circuit, the pixel internal compensation circuit, and the pixel driving circuit can each include a transistor, which can include a control electrode G, a first electrode S, and a second electrode D. The control electrode G, the first electrode S, and the second electrode D can be connected to respective connection electrodes through tungsten metal filled vias (i.e., tungsten vias, W-vias), and can be connected to other electrical structures (e.g., wires, etc.) through the connection electrodes.

[0166] In the example embodiment, the pixel defining film 103 can be formed by a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process.

[0167] In the example embodiment, the pixel defining film 103 can be made of an inorganic material, such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiOxNy). The pixel defining film 103 made of an inorganic material can effectively block water vapor, especially during a subsequent isolation column 50 wet etching process, to prevent water vapor from entering the light emitting device. If the pixel defining film 103 is made of an organic material, the water absorption of the organic material can affect the reliability of the light emitting device, and the etching liquid can also corrode the organic material during the subsequent isolation column 50 wet etching process.

[0168] 1.2, Forming a photoresist film 104.

[0169] In the example embodiment, forming the photoresist film 104 can include: coating a photoresist film 104 on the substrate 101 on which the pattern is formed, and forming a low solidification area 1041, a high solidification area 1042, and an un-solidified area 1043 on the photoresist film 104 by exposure, wherein the orthographic projection of the low solidification area 1041 and the orthographic projection of the high solidification area 1042 on the substrate 101 do not overlap with the orthographic projection of the first electrode on the substrate 101, and the orthographic projection of the un-solidified area 1043 on the substrate 101 covers the orthographic projection of the first electrode on the substrate 101. The orthographic projection of the low solidification area 1041 on the substrate 101 does not overlap with the orthographic projection of the high solidification area 1042 on the substrate 101. The orthographic projection of the low solidification area 1041 on the substrate 101 is located between the orthographic projection of the high solidification area 1042 on the substrate 101 and the orthographic projection of the first electrode on the substrate 101, as shown in FIG. 4b.

[0170] In an exemplary embodiment, the mask 70 used in the exposure is a halftone mask.

[0171] 1.3, forming the first photoresist pattern 105.

[0172] In an exemplary embodiment, forming the first photoresist pattern 105 can include: on the substrate 101 on which the aforementioned pattern is formed, developing the photoresist film 104, the photoresist film 104 of the low-cured area 1041 and the high-cured area 1042 is at least partially reserved, the photoresist film 104 of the uncured area 1043 is removed, forming the first photoresist pattern 105, the first photoresist pattern 105 covers the pixel defining layer 40 area formed subsequently by the pixel defining film 103, wherein the thickness of the photoresist film 104 reserved in the low-cured area 1041 is less than the thickness of the photoresist film 104 reserved in the high-cured area 1042, as shown in FIG. 4c.

[0173] 1.4, forming the pixel defining layer 40.

[0174] In an exemplary embodiment, forming the pixel defining layer 40 can include: on the substrate 101 on which the aforementioned pattern is formed, using a dry etching process to pattern the pixel defining film 103, etching to remove the area of the pixel defining film 103 not covered by the first photoresist pattern 105, exposing the first electrode, reserving the area of the pixel defining film 103 covered by the first photoresist pattern 105, forming the pixel defining layer 40. Due to the different thicknesses of the first photoresist pattern 105 covering the pixel defining film 103 (the thickness of the photoresist film 104 reserved in the low-cured area 1041 is less than the thickness of the photoresist film 104 reserved in the high-cured area 1042), the dry etching process can form a groove 200 on the side of the pixel defining layer 40 away from the substrate 101, the orthographic projection of the groove 200 on the substrate 101 is within the orthographic projection of the pixel defining layer 40 on the substrate 101, as shown in FIG. 4d. On the substrate 101 on which the aforementioned pattern is formed, the excess photoresist film 104 is removed, obtaining the display substrate after the pixel defining layer 40 is formed, as shown in FIG. 4e.

[0175] In an exemplary embodiment, the pixel defining layer 40 and the groove 200 can be formed simultaneously by the same dry etching process; or the pixel defining layer 40 and the groove 200 can be formed respectively by two etching processes.

[0176] In an exemplary embodiment, the orthographic projection of the pixel defining layer 40 on the substrate 101 does not overlap with the orthographic projection of the first electrode on the substrate 101, as shown in FIG. 4e. In another embodiment, the orthographic projection of the pixel defining layer 40 on the substrate 101 partially overlaps with the orthographic projection of the first electrode on the substrate 101, as shown in FIG. 5.

[0177] In an example embodiment, the pixel defining layer 40 includes a first top surface 41 and a first bottom surface 42. The first top surface 41 is a surface of the pixel defining layer 40 away from the substrate 101. The first bottom surface 42 is a surface of the pixel defining layer 40 close to the substrate 101. The trench 200 can form a barrier portion 45 on the pixel defining layer 40 on both sides of the trench 200, and the first top surface 41 is on a side of the barrier portion 45 away from the substrate 101. The barrier portion 45 includes a first side surface 43 and a second side surface 44. The first side surface 43 defines the trench 200. The second side surface 44 and the pixel defining layer 40 together define the pixel opening 100.

[0178] In an example embodiment, the pixel defining layer 40 can further include a first side surface 48. The first side surface 48 is between the second side surface 44 and the substrate 101. The first side surface 48 is perpendicular to the substrate 101, and the second side surface 44 is connected to the first side surface 48 on a side away from the substrate 101 and inclined away from the pixel opening 100 from the first side surface 48. In another embodiment, the second side surface 44 is inclined away from the pixel opening 100 from the first electrode, as shown in FIG. 5.

[0179] In an example embodiment, the pixel defining layer 40 can be made of an inorganic material, such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiOxNy).

[0180] In an example embodiment, the pixel defining layer 40 can be a single-layer structure or a multi-layer structure.

[0181] In an example embodiment, the thickness of the pixel defining layer 40 can be about to For example, the thickness of the pixel defining layer 40 can be about or so.

[0182] In an example embodiment, the trench 200 has a first width W1 on a side away from the substrate 101, and a second width W2 on a side close to the substrate 101. The first width W1 refers to the size of the trench 200 on a side away from the substrate 101 along the first direction D1. The second width W2 refers to the size of the trench 200 on a side close to the substrate 101 along the first direction D1. The first width W1 is greater than the second width W2, as shown in FIG. 4e. In this way, the width of the two ends of the trench 200 in the direction perpendicular to the substrate 101 (the third direction D3) is different, i.e. the width of the side of the trench 200 away from the substrate 101 is greater than the width of the side of the trench 200 close to the substrate 101, and the trench 200 is an inverted trapezoid with the top wide and the bottom narrow.

[0183] In an example embodiment, please refer to FIG. 4e and FIG. 4k together, the first side surface 43 is inclined to the side away from the groove 200, and a first included angle a1 can be formed between the first side surface 43 and the substrate 101.

[0184] In an example embodiment, please refer to FIG. 4e and FIG. 4k together, the second side surface 44 is inclined to the side away from the pixel opening 100, and a second included angle a2 can be formed between the second side surface 44 and the substrate 101.

[0185] In an example embodiment, please refer to FIG. 4e and FIG. 4k together, the first included angle a1 is not equal to the second included angle a2.

[0186] In an example embodiment, please refer to FIG. 4e and FIG. 4k together, the first included angle a1 can be about 30° to 60°. For example, the first included angle a1 can be about 45°.

[0187] In an example embodiment, please refer to FIG. 4e and FIG. 4k together, the second included angle a2 can be about 60° to 90°. For example, the second included angle a2 can be about 75°.

[0188] In an example embodiment, the material of the pixel defining layer 40 is the same as that of the barrier portion 45.

[0189] 1.5, forming the second conductive thin film 106 and the third conductive thin film 107.

[0190] In an example embodiment, forming the second conductive thin film 106 and the third conductive thin film 107 can include: sequentially depositing a layer of the second conductive thin film 106 and a layer of the third conductive thin film 107 on the substrate 101 with the aforementioned pattern, the second conductive thin film 106 covering the pixel defining layer 40, the first electrode, and the inner wall of the groove 200, and the third conductive thin film 107 being disposed on the side of the second conductive thin film 106 away from the substrate 101, as shown in FIG. 4f.

[0191] In an example embodiment, the second conductive thin film 106 and the third conductive thin film 107 can be formed by magnetron sputtering.

[0192] In an example embodiment, the second conductive thin film 106 and the third conductive thin film 107 can be made of conductive materials, such as one or more of titanium (Ti), aluminum (Al), molybdenum (Mo), copper (Cu), aluminum-neodymium alloy (AlNd), indium tin oxide (ITO), and indium gallium zinc oxide (IGZO).

[0193] In the example embodiment, the second conductive thin film 106 and the third conductive thin film 107 are made of different materials. In the embodiment of the present disclosure, the second conductive thin film 106 can be made of aluminum (Al). The third conductive thin film 107 can be made of titanium (Ti). The second conductive thin film 106 and the third conductive thin film 107 can be a single-layer structure or a multi-layer structure, and the materials of each layer can be the same or different.

[0194] In the example embodiment, the thickness of the second conductive thin film 106 is greater than the thickness of the third conductive thin film 107.

[0195] 1.6, forming the first transition conductive layer 108 and the second transition conductive layer 109.

[0196] In the example embodiment, forming the first transition conductive layer 108 and the second transition conductive layer 109 can include: coating a photoresist thin film 104 on the substrate 101 on which the aforementioned pattern is formed, forming a second photoresist pattern 110 by exposure and development, the orthographic projection of the second photoresist pattern 110 on the substrate 101 covering the orthographic projection of the trench 200 on the substrate 101, and the orthographic projection of the second photoresist pattern 110 on the substrate 101 being within the range of the orthographic projection of the pixel defining layer 40 on the substrate 101, as shown in FIG. 4g.

[0197] Subsequently, on the substrate 101 on which the aforementioned pattern is formed, the second conductive thin film 106 and the third conductive thin film 107 are patterned by a dry etching process, the regions of the second conductive thin film 106 and the third conductive thin film 107 not covered by the second photoresist pattern 110 are etched and removed, exposing the first electrode, and the regions of the second conductive thin film 106 and the third conductive thin film 107 covered by the second photoresist pattern 110 are retained, so that the third conductive thin film 107 forms the second transition conductive layer 109, the second conductive thin film 106 forms the first transition conductive layer 108, and the second transition conductive layer 109 is disposed on the side of the first transition conductive layer 108 away from the substrate 101. The orthographic projection of the second transition conductive layer 109 on the substrate 101 covers the orthographic projection of the first transition conductive layer 108 and the trench 200 on the substrate 101, as shown in FIG. 4h.

[0198] In the example embodiment, the first transition conductive layer 108 covers the bottom and the first side 43 of the trench 200.

[0199] In the example embodiment, the orthographic projection of the first transition conductive layer 108 on the substrate 101 overlaps the orthographic projection of the trench 200 on the substrate 101.

[0200] In an example embodiment, the orthogonal projection of the second transition conductive layer 109 on the substrate 101 is within the range of the orthogonal projection of the pixel defining layer 40 on the substrate 101.

[0201] 1.7, forming the isolation column 50.

[0202] In an example embodiment, forming the isolation column 50 can include: on the substrate 101 on which the aforementioned pattern is formed, first patterning the first transition conductive layer 108 and the second transition conductive layer 109 by a wet etching process, using the isotropic characteristics of wet etching to form the second conductive layer 52 from the second transition conductive layer 109 and the first conductive layer 51 from the first transition conductive layer 108, wherein the first conductive layer 51 and the second conductive layer 52 form the isolation column 50, as shown in FIG. 4i.

[0203] In an example embodiment, the orthogonal projection width of the first conductive layer 51 on the substrate 101 is less than the orthogonal projection width of the second conductive layer 52 on the substrate 101, and the orthogonal projection of the first conductive layer 51 on the substrate 101 is within the range of the orthogonal projection of the second conductive layer 52 on the substrate 101. The orthogonal projection width of the first conductive layer 51 on the substrate 101 refers to the size of the orthogonal projection of the first conductive layer 51 on the substrate along the first direction D1, and the orthogonal projection width of the second conductive layer 52 on the substrate 101 refers to the size of the orthogonal projection of the second conductive layer 52 on the substrate 101 along the first direction D1.

[0204] In an example embodiment, the first conductive layer 51 is disposed at the bottom of the trench 200, and the orthogonal projection of the first conductive layer 51 on the substrate 101 is within the range of the orthogonal projection of the trench 200 on the substrate 101.

[0205] In an example embodiment, the distance between the isolation column 50 and the blocking portion 45 can be about to For example, the distance between the isolation column 50 and the blocking portion 45 can be about ±

[0206] In an example embodiment, the first conductive layer 51 has a first surface 511 distal from the substrate 101, a second surface 512 proximal to the substrate 101, and a first sidewall 513 connecting between the first surface 511 and the second surface 512. A width of a projection of the first surface 511 on the substrate 101 is less than a width of a projection of the second surface 512 on the substrate 101. The width of the projection of the first surface 511 on the substrate 101 refers to a dimension of a projection of the first surface 511 on the substrate 101 along the first direction D1, and the width of the projection of the second surface 512 on the substrate 101 refers to a dimension of a projection of the second surface 512 on the substrate 101 along the first direction D1.

[0207] In an example embodiment, a projection of the second surface 512 on the substrate 101 covers a projection of the first surface 511 on the substrate 101.

[0208] In an example embodiment, a projection of a groove bottom of the trench 200 on the substrate 101 covers a projection of the second surface 512 on the substrate 101.

[0209] In an example embodiment, a thickness of the first conductive layer 51 is greater than a groove depth of the trench 200.

[0210] In an example embodiment, the thickness of the first conductive layer 51 can be about to For example, the thickness of the first conductive layer 51 can be about to

[0211] In an example embodiment, a groove depth of the trench 200 can be about to For example, the groove depth of the trench 200 can be about to

[0212] In an example embodiment, the first sidewall 513 is recessed toward an inner side of the first conductive layer 51.

[0213] In an example embodiment, the first conductive layer 51 is formed with a first recess 514 at a position of the trench 200, the first recess 514 is recessed toward a side proximal to the substrate 101, and a projection of the first recess 514 on the substrate 101 is within a range of a projection of the trench 200 on the substrate 101.

[0214] In an example embodiment, a projection of the second conductive layer 52 on the substrate 101 covers a projection of the trench 200 on the substrate 101.

[0215] In the example embodiment, the second conductive layer 52 has a third surface 521 away from the substrate 101 and a fourth surface 522 close to the substrate 101, and the third surface 521 has a smaller width in orthographic projection on the substrate 101 than the fourth surface 522.

[0216] In this way, the cross section of the second conductive layer 52 in the direction perpendicular to the substrate 101 can include a trapezoid.

[0217] In the example embodiment, the fourth surface 522 in orthographic projection on the substrate 101 covers the third surface 521 in orthographic projection on the substrate 101.

[0218] In the example embodiment, the third surface 521 in orthographic projection on the substrate 101 covers the trench 200 in orthographic projection on the substrate 101.

[0219] In the example embodiment, the second conductive layer 52 is formed with a second recess 523 at the position of the first recess 514, the second recess 523 is recessed toward the side close to the substrate 101, and the second recess 523 in orthographic projection on the substrate 101 is within the range of the first recess 514 in orthographic projection on the substrate 101.

[0220] In the example embodiment, the first conductive layer 51 and the second conductive layer 52 can be made of conductive materials, such as one or more of titanium (Ti), aluminum (Al), molybdenum (Mo), copper (Cu), aluminum-neodymium alloy (AlNd), indium tin oxide (ITO), and indium gallium zinc oxide (IGZO).

[0221] In the example embodiment, the materials of the first conductive layer 51 and the second conductive layer 52 are different. The wet etching solution is selected to have a high selectivity to the first conductive layer 51 and a small etching effect on the upper layer material of the first electrode.

[0222] In the example embodiment, the material of the first conductive layer 51 can be aluminum (Al). The material of the second conductive layer 52 can be titanium (Ti). When the upper layer material of the first electrode is indium tin oxide (ITO), the wet etching solution is aluminum wet etching solution (such as phosphoric acid, nitric acid, acetic acid, and additives (such as potassium chloride)).

[0223] In the example embodiment, the first conductive layer 51 and the second conductive layer 52 can be a single-layer structure or a multi-layer structure, and the materials of each layer can be the same or different.

[0224] In an example embodiment, the first conductive layer 51 has a thickness greater than the thickness of the second conductive layer 52.

[0225] In an example embodiment, the second conductive layer 52 has a thickness of about to For example, the second conductive layer 52 has a thickness of about to

[0226] 1.8, forming a light-emitting functional layer and a second electrode.

[0227] In an example embodiment, forming a light-emitting functional layer and a second electrode can include: on the substrate 101 on which the aforementioned pattern is formed, by a plating process, such as a thermal evaporation plating process, magnetron sputtering, sequentially depositing a light-emitting functional layer material and a second electrode material, at least part of the light-emitting functional layer material is disposed on the surface of the first electrode away from the substrate 101, forming a light-emitting functional layer, the second electrode material is disposed on the surface of the light-emitting functional layer away from the substrate 101, in contact with the light-emitting functional layer, at least part of the second electrode material covers the first side wall 513 of the first conductive layer 51, and is electrically connected to the first conductive layer 51, forming a second electrode, as shown in FIG. 4j. Wherein the plurality of light-emitting functional layers can include a first light-emitting functional layer, a second light-emitting functional layer and a third light-emitting functional layer. The plurality of second electrodes can include a first color cathode 21, a second color cathode 22 and a third color cathode 23.

[0228] In an example embodiment, the light-emitting functional layer and the first electrode have an overlap in orthographic projection on the substrate 101, for example, the orthographic projection of the light-emitting functional layer on the substrate 101 covers the orthographic projection of the first electrode on the substrate 101, and the light-emitting functional layer is in direct contact with the first electrode.

[0229] In an example embodiment, the light-emitting functional layer can include two sub-light-emitting functional layers and a charge generation layer 31 (CGL) located between the two sub-light-emitting functional layers, and the sub-light-emitting functional layer can include a light-emitting layer (EML) and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL).

[0230] In the embodiments of the present disclosure, the light-emitting functional layer can include a first sub-light-emitting functional layer disposed close to the substrate 101, a second sub-light-emitting functional layer disposed away from the substrate 101, and a charge generation layer 31 located between the first sub-light-emitting functional layer and the second sub-light-emitting functional layer, so that the first electrode, the light-emitting functional layer, and the second electrode can form a Tandem OLED light-emitting device. The first sub-light-emitting functional layer can include a first light-emitting layer 32. The second sub-light-emitting functional layer can include a second light-emitting layer 33.

[0231] In the example embodiments, the preparation process of the light-emitting functional layer and the second electrode formed by the thermal evaporation coating process can include: sequentially spraying, by an evaporation source, the light-emitting functional layer material and the second electrode material to the substrate 101 with the aforementioned pattern, the light-emitting functional layer material being blocked by the isolation column 50 at the pixel defining layer 40, and the light-emitting functional layer material disposed on the first electrode forming the light-emitting functional layer; the second electrode material being continuous at the pixel defining layer 40 to achieve electrical connection with the first electrode layer.

[0232] In the example embodiments, the light-emitting functional layer material is blocked by the pixel defining layer 40 from the isolation column 50, avoiding the charge generation layer 31 (CGL) in the light-emitting functional layer from contacting the isolation column 50 and causing short circuit.

[0233] In the example embodiments, the orthographic projection of the second electrode on the substrate 101 respectively overlaps with the orthographic projection of the first electrode, the light-emitting functional layer, the pixel defining layer 40, and the first and second conductive layers 51 and 52 on the substrate 101.

[0234] In the example embodiments, the orthographic projection of the second electrode on the substrate 101 respectively overlaps with the orthographic projection of the first conductive layer 51, the first side surface 43, the second side surface 44, and the charge generation layer 31 (CGL) on the substrate 101.

[0235] In the example embodiments, the preparation method of the display substrate of the present disclosure can simultaneously form the light-emitting functional layer and the second electrode of multiple sub-pixels emitting the same color through the same preparation process. For example, the preparation method of the display substrate of the present disclosure can first simultaneously form the light-emitting functional layer and the second electrode of multiple first sub-pixels P1 through a first thermal evaporation coating process; then, simultaneously form the light-emitting functional layer and the second electrode of multiple second sub-pixels P2 through a second thermal evaporation coating process; and finally, simultaneously form the light-emitting functional layer and the second electrode of multiple third sub-pixels P3 through a third thermal evaporation coating process.

[0236] In an exemplary embodiment, the light emitting device of the sub-pixel can include a first electrode, a second electrode, and a light emitting functional layer disposed between the first electrode and the second electrode, and the light emitting functional layer can include a hole injection layer disposed on the first electrode, a first hole transport layer disposed on the hole injection layer, a first light emitting layer 32 disposed on the first hole transport layer, a first electron transport layer disposed on the first light emitting layer 32, a charge production layer 31 disposed on the first electron transport layer, a second hole transport layer disposed on the charge production layer 31, a second light emitting layer 33 disposed on the second hole transport layer, a second electron transport layer disposed on the second light emitting layer 33, and an electron injection layer disposed on the second electron transport layer.

[0237] In an exemplary embodiment, the second electrode covers the first side surface 43, the first top surface 41, and the second side surface 44.

[0238] In an exemplary embodiment, the orthographic projection of the second electrode on the substrate 101 covers the orthographic projection of the first electrode, the light emitting functional layer, the first side surface 43, the first top surface 41, and the second side surface 44 on the substrate 101.

[0239] In an exemplary embodiment, the first electrode, the light emitting functional layer, and the second electrode form a light emitting device of the sub-pixel.

[0240] In an exemplary embodiment, the preparation method of the display substrate of the present disclosure can simultaneously form the light emitting functional layer and the second electrode of the plurality of sub-pixels of the same color through the same preparation process. For example, the preparation method of the display substrate of the present disclosure can first simultaneously form the first light emitting functional layer and the first color cathode 21 of the plurality of first sub-pixels P1 through a first thermal evaporation film plating process; then, the second light emitting functional layer and the second color cathode 22 of the plurality of second sub-pixels P2 are formed through a second thermal evaporation film plating process; finally, the third light emitting functional layer and the third color cathode 23 of the plurality of third sub-pixels P3 are formed through a third thermal evaporation film plating process. The first color electrode, the first light emitting functional layer, and the first color cathode 21 form a light emitting device of the first sub-pixel P1. The second color electrode, the second light emitting functional layer, and the second color cathode 22 form a light emitting device of the second sub-pixel P2. The third color electrode, the third light emitting functional layer, and the third color cathode 23 form a light emitting device of the third sub-pixel P3.

[0241] In an exemplary embodiment, the light emitting device of the sub-pixel can include a first color anode 11, a first color cathode 21, and a first light emitting functional layer disposed between the first color anode 11 and the first color cathode 21, the first light emitting functional layer can include a hole injection layer disposed on the first color anode 11, a first hole transport layer disposed on the hole injection layer, a first light emitting layer 32 disposed on the first hole transport layer, a first electron transport layer disposed on the first light emitting layer 32, a charge generation layer 31 disposed on the first electron transport layer, a second hole transport layer disposed on the charge generation layer 31, a second light emitting layer 33 disposed on the second hole transport layer, a second electron transport layer disposed on the second light emitting layer 33, and an electron injection layer disposed on the second electron transport layer.

[0242] 1.9, forming an encapsulation layer 60.

[0243] In an exemplary embodiment, forming the encapsulation layer 60 can include: covering an encapsulation film on the substrate 101 on which the aforementioned pattern is formed, and forming the encapsulation layer 60 covering the second electrode, as shown in FIGS. 3a and 3b.

[0244] In an exemplary embodiment, the encapsulation film can be formed by a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process.

[0245] The display substrate of the embodiments of the present disclosure can avoid the short circuit of the charge generation layer 31 (CGL) and the isolation column 50 by adopting the pixel definition layer 40 to separate the charge generation layer 31 (CGL) from the isolation column 50, thereby avoiding the risk of product abnormal display. The second electrode can directly contact the isolation column 50, ensuring that the second electrode can effectively overlap the isolation column 50, and further ensuring the stability of the electrical connection between the light emitting device and the isolation column 50.

[0246] FIG. 6a is a schematic diagram of a cross-sectional structure of another display substrate according to an embodiment of the present disclosure. FIG. 6b is a schematic diagram of a cross-sectional structure in the direction of B-B in FIG. 6a. In an exemplary embodiment, in the direction perpendicular to the display substrate, the structure of the display substrate according to the embodiment of the present disclosure is basically the same as that shown in FIGS. 3a and 3b, except that the display substrate according to the embodiment of the present disclosure further includes a boundary layer 47, the pixel definition layer 40 is disposed between the boundary layer 47 and the substrate 101, and the orthographic projection of the boundary layer 47 on the substrate 101 is located within the orthographic projection of the pixel definition layer 40 on the substrate 101. The boundary layer 47 is separated at the isolation column 50 to form two blocking portions 45 located on both sides of the isolation column 50, and the trench 200 is formed between the two blocking portions 45.

[0247] In an exemplary embodiment, as shown in FIG. 7g, the pixel defining layer 40 includes a second top surface 461 away from the substrate 101, a second bottom surface 462 close to the substrate 101, and a second side surface 463 connecting between the second top surface 461 and the second bottom surface 462.

[0248] The barrier portion 45 includes the first side surface 43, the second side surface 44, and a third bottom surface 49 close to the substrate 101.

[0249] The first top surface 41 is located on a side of the barrier portion 45 away from the substrate 101. The first side surface 43 defines the trench 200, and the second side surface 44 and the second side surface 463 jointly define the pixel opening 100.

[0250] In an exemplary embodiment, as shown in FIG. 7g and FIG. 7h, the distance between the isolation column 50 and the barrier portion 45 is to wherein the distance refers to the distance between the side of the isolation column 50 facing the barrier portion 45 and the side of the barrier portion 45 facing the isolation column 50.

[0251] In an exemplary embodiment, as shown in FIG. 7g, FIG. 7h, and FIG. 7i, the orthographic projection width of the first top surface 41 on the substrate 101 is greater than the orthographic projection width of the third bottom surface 49 on the substrate 101, and the orthographic projection of the first top surface 41 on the substrate 101 covers the orthographic projection of the third bottom surface 49 on the substrate 101. The orthographic projection width of the first top surface 41 on the substrate 101 refers to the size of the orthographic projection of the first top surface 41 on the substrate along the first direction D1, and the orthographic projection width of the third bottom surface 49 on the substrate 101 refers to the size of the orthographic projection of the third bottom surface 49 on the substrate 101 along the first direction D1. In this way, the width of the barrier portion 45 at both ends in the direction perpendicular to the substrate 101 (the third direction D3) is different, forming an inverted trapezoid with a wide top and a narrow bottom, which can further prevent the light-emitting functional layer material from falling into the trench 200 and affecting the subsequent contact between the second electrode and the first conductive layer 51.

[0252] In an exemplary embodiment, as shown in FIG. 7g and FIG. 7h, the orthographic projection of the first top surface 41 on the substrate 101 is located within the orthographic projection of the pixel defining layer 40 on the substrate 101. In this way, the setting of the barrier layer 47 does not affect the area of the pixel opening 100.

[0253] In an example embodiment, the material of the pixel defining layer 40 is inorganic material. The pixel defining layer 40 made of inorganic material can effectively block water vapor, especially during the subsequent wet etching process of the isolation column 50, so as to avoid water vapor entering the light emitting device. If the pixel defining layer 40 is made of organic material, the water absorption of the organic material will affect the reliability of the light emitting device, and the etching liquid will also corrode the organic material during the subsequent wet etching process of the isolation column 50.

[0254] In an example embodiment, the material of the boundary layer 47 is organic material. The boundary layer 47 can be formed after the formation of the isolation column 50, so as to avoid being corroded by the etching liquid.

[0255] In an example embodiment, please refer to FIG. 6b and FIG. 7h together, the orthogonal projection of the second electrode on the substrate 101 overlaps with the orthogonal projection of the first electrode, the light emitting functional layer, the pixel defining layer 40, the boundary layer 47, the first conductive layer 51 and the second conductive layer 52 on the substrate 101. For example, the orthogonal projection of the second electrode on the substrate 101 covers the orthogonal projection of the first electrode, the light emitting functional layer, the second side surface 463, the first top surface 41, the first side surface 43 and the second side surface 44 on the substrate 101.

[0256] In an example embodiment, please refer to FIG. 6b and FIG. 7h together, the second electrode covers the first top surface 41 and the first side surface 43 and the second side surface 44 located on both sides of the first top surface 41. In this way, the second electrode can wrap the side of the blocking part 45 away from the substrate 101, increase the connection area between the second electrode and the blocking part 45, improve the connection stability between the second electrode and the blocking part 45, and ensure the electrical connection stability between the second electrode and the first conductive layer 51.

[0257] In an example embodiment, the preparation process of the substrate can include the following operations.

[0258] 2.1, forming the driving circuit layer 102, the first electrode and the first boundary film 111.

[0259] In an example embodiment, forming the driving circuit layer 102, the first electrode and the first boundary film 111 can include: first forming the driving circuit layer 102 on the substrate 101; then, depositing a layer of first conductive film on the side of the driving circuit layer 102 away from the substrate 101, patterning the first conductive film by photolithography process, so that the first conductive film forms the first electrode arranged on the side of the driving circuit layer 102 away from the substrate 101; then, depositing a layer of first boundary film 111 covering the first electrode on the side of the driving circuit layer 102 away from the substrate 101. The plurality of first electrodes can include the first color anode 11, the second color anode 12 and the third color anode 13, as shown in FIG. 7a.

[0260] In an exemplary embodiment, the first color anode 11, the second color anode 12 and the third color anode 13 can be a stack structure of indium tin oxide (ITO) / silver (Ag) / indium tin oxide (ITO).

[0261] In an exemplary embodiment, the driving circuit layer 102 can include a gate driving circuit, an electrostatic protection circuit, an initialization circuit, a pixel internal compensation circuit, a pixel driving circuit, and a wire, etc. The wire can include a gate line, an initial signal line, a reference signal line, a data line, a first power supply line (VDD), a second power supply line (VSS), etc. The pixel driving circuit, the gate driving circuit, the electrostatic protection circuit, the pixel internal compensation circuit and the pixel driving circuit can each include a transistor, which can include a control electrode G, a first electrode S and a second electrode D. The control electrode G, the first electrode S and the second electrode D can be connected to respective connection electrodes through tungsten metal filled vias (i.e., tungsten vias, W-vias) and can be connected to other electrical structures (such as wires, etc.) through the connection electrodes.

[0262] In an exemplary embodiment, the first defining thin film 111 can be formed by a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process.

[0263] In an exemplary embodiment, the first defining thin film 111 can be made of inorganic material, such as silicon nitride (SiNx), silicon oxide (SiOx) or silicon oxynitride (SiOxNy). The first defining thin film 111 made of inorganic material can effectively block water vapor, especially during a subsequent isolation column 50 wet etching process, to prevent water vapor from entering the light emitting device. If the first defining thin film 111 is made of organic material, the water absorption of the organic material will affect the reliability of the light emitting device, and the etching liquid will also corrode the organic material during the subsequent isolation column 50 wet etching process.

[0264] 2.2, forming the pixel defining layer 40.

[0265] In an exemplary embodiment, forming the pixel defining layer 40 can include: on the substrate 101 on which the aforementioned pattern is formed, using an etching process to pattern the first defining thin film 111 to expose the first electrode, thereby forming the pixel defining layer 40, as shown in FIG. 7b.

[0266] In an exemplary embodiment, the orthogonal projection of the pixel defining layer 40 on the substrate 101 does not overlap with the orthogonal projection of the first electrode on the substrate 101, as shown in FIG. 7b. In another embodiment, the orthogonal projection of the pixel defining layer 40 on the substrate 101 partially overlaps with the orthogonal projection of the first electrode on the substrate 101, as shown in FIG. 8.

[0267] In an example embodiment, the pixel defining layer 40 includes a second top surface 461, a second bottom surface 462, and a second side surface 463 connected between the second top surface 461 and the second bottom surface 462, the second top surface 461 being a surface of the pixel defining layer 40 away from the substrate 101. The second bottom surface 462 is a surface of the pixel defining layer 40 close to the substrate 101.

[0268] In an example embodiment, the pixel defining layer 40 can be made of an inorganic material, such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiOxNy).

[0269] In an example embodiment, the pixel defining layer 40 can be a single-layer structure or a multi-layer structure.

[0270] In an example embodiment, the thickness of the pixel defining layer 40 can be about to about For example, the thickness of the pixel defining layer 40 can be about .

[0271] 2.3, forming the second conductive thin film 106 and the third conductive thin film 107.

[0272] In an example embodiment, forming the second conductive thin film 106 and the third conductive thin film 107 can include sequentially depositing a layer of the second conductive thin film 106 and a layer of the third conductive thin film 107 on the substrate 101 with the aforementioned pattern, the second conductive thin film 106 covering the pixel defining layer 40 and the first electrode, and the third conductive thin film 107 being disposed away from the substrate 101, as shown in FIG. 7c.

[0273] In an example embodiment, the second conductive thin film 106 and the third conductive thin film 107 can be formed by magnetron sputtering.

[0274] In an example embodiment, the second conductive thin film 106 and the third conductive thin film 107 can be made of a conductive material, such as one or more of titanium (Ti), aluminum (Al), molybdenum (Mo), copper (Cu), aluminum-neodymium alloy (AlNd), indium tin oxide (ITO), and indium gallium zinc oxide (IGZO).

[0275] In an example embodiment, the second conductive thin film 106 and the third conductive thin film 107 are made of different materials. In an embodiment of the present disclosure, the material of the second conductive thin film 106 can be aluminum (Al). The material of the third conductive thin film 107 can be titanium (Ti). The second conductive thin film 106 and the third conductive thin film 107 can be a single-layer structure or a multi-layer structure, and the material of each layer can be the same or different.

[0276] In the exemplary embodiment, the thickness of the second conductive film 106 is greater than the thickness of the third conductive film 107.

[0277] 2.4, forming the first transition conductive layer 108 and the second transition conductive layer 109.

[0278] In the exemplary embodiment, forming the first transition conductive layer 108 and the second transition conductive layer 109 can include: on the substrate 101 with the aforementioned pattern, coating a layer of photoresist film 104, forming a second photoresist pattern 110 by exposure and development, the orthographic projection of the second photoresist pattern 110 on the substrate 101 is within the orthographic projection of the pixel defining layer 40 on the substrate 101, as shown in Figure 7d.

[0279] Subsequently, on the substrate 101 with the aforementioned pattern, the second conductive film 106 and the third conductive film 107 are patterned by dry etching process, the areas of the second conductive film 106 and the third conductive film 107 not covered by the second photoresist pattern 110 are etched and removed, exposing the first electrode, the areas of the second conductive film 106 and the third conductive film 107 covered by the second photoresist pattern 110 are retained, so that the third conductive film 107 forms the second transition conductive layer 109, and the second conductive film 106 forms the first transition conductive layer 108, the second transition conductive layer 109 is arranged on the side of the first transition conductive layer 108 away from the substrate 101. The orthographic projection of the second transition conductive layer 109 on the substrate 101 covers the orthographic projection of the first transition conductive layer 108 on the substrate 101, and the orthographic projection of the second transition conductive layer 109 on the substrate 101 is within the orthographic projection of the pixel defining layer 40 on the substrate 101, as shown in Figure 7e.

[0280] 2.5, forming the isolation column 50.

[0281] In the exemplary embodiment, forming the isolation column 50 can include: on the substrate 101 with the aforementioned pattern, first pattern the first transition conductive layer 108 and the second transition conductive layer 109 by wet etching process, use the isotropic characteristics of wet etching to form the second conductive layer 52 from the second transition conductive layer 109 and the first conductive layer 51 from the first transition conductive layer 108, wherein the first conductive layer 51 and the second conductive layer 52 form the isolation column 50, as shown in Figure 7f.

[0282] In the exemplary embodiment, the orthographic projection of the first conductive layer 51 on the substrate 101 is within the orthographic projection of the second conductive layer 52 on the substrate 101.

[0283] In an example embodiment, the first conductive layer 51 has a first surface 511 distal from the substrate 101, a second surface 512 proximal to the substrate 101, and a first sidewall 513 connecting between the first surface 511 and the second surface 512. The first surface 511 has a first surface projection width on the substrate 101, and the second surface 512 has a second surface projection width on the substrate 101. The first surface projection width on the substrate 101 refers to a dimension of a projection of the first surface 511 on the substrate 101 along the first direction D1, and the second surface projection width on the substrate 101 refers to a dimension of a projection of the second surface 512 on the substrate 101 along the first direction D1.

[0284] In an example embodiment, the second surface 512 has a second surface projection on the substrate 101 covering a first surface projection of the first surface 511 on the substrate 101.

[0285] In an example embodiment, the first conductive layer 51 has a thickness of about to about For example, the first conductive layer 51 has a thickness of about to about

[0286] In an example embodiment, the first sidewall 513 is recessed toward an inner side of the first conductive layer 51.

[0287] In an example embodiment, the second conductive layer 52 has a third surface 521 distal from the substrate 101 and a fourth surface 522 proximal to the substrate 101, and the third surface 521 has a third surface projection width on the substrate 101, and the fourth surface 522 has a fourth surface projection width on the substrate 101. The third surface projection width on the substrate 101 refers to a dimension of a projection of the third surface 521 on the substrate 101 along the first direction D1, and the fourth surface projection width on the substrate 101 refers to a dimension of a projection of the fourth surface 522 on the substrate 101 along the first direction D1. In this way, a cross section of the second conductive layer 52 in a direction perpendicular to the substrate 101 can include a trapezoid.

[0288] In an example embodiment, the fourth surface 522 has a fourth surface projection on the substrate 101 covering a third surface projection of the third surface 521 on the substrate 101.

[0289] In an example embodiment, the first conductive layer 51 and the second conductive layer 52 can be made of a conductive material, such as one or more of titanium (Ti), aluminum (Al), molybdenum (Mo), copper (Cu), aluminum-neodymium alloy (AlNd), indium tin oxide (ITO), and indium gallium zinc oxide (IGZO).

[0290] In an example embodiment, the first conductive layer 51 and the second conductive layer 52 are made of different materials. The wet etching solution is selected based on the first conductive layer 51 and has a small etching effect on the upper layer material of the first electrode.

[0291] In an example embodiment, the first conductive layer 51 is made of aluminum (Al), and the second conductive layer 52 is made of titanium (Ti). When the upper layer material of the first electrode is indium tin oxide (ITO), the wet etching solution is an aluminum wet etching solution (e.g., phosphoric acid, nitric acid, acetic acid, and an additive such as potassium chloride).

[0292] In an example embodiment, the first conductive layer 51 and the second conductive layer 52 can be a single-layer structure or a multi-layer structure, and the materials of each layer can be the same or different.

[0293] In an example embodiment, the thickness of the first conductive layer 51 is greater than the thickness of the second conductive layer 52.

[0294] In an example embodiment, the thickness of the second conductive layer 52 is about to For example, the thickness of the second conductive layer 52 is about .

[0295] 2.6, forming a boundary layer 47.

[0296] In an example embodiment, forming the boundary layer 47 can include: coating a second boundary film on the substrate 101 on which the pattern is formed, and patterning the second boundary film by an etching process to expose the first electrode, thereby forming the boundary layer 47. The boundary layer 47 is disposed on the side of the pixel boundary layer 40 away from the substrate, and the orthographic projection of the boundary layer 47 on the substrate 101 is within the orthographic projection of the pixel boundary layer 40 on the substrate 101. The boundary layer 47 is interrupted at the isolation column 50 to form two blocking portions 45 on both sides of the isolation column 50, and a groove 200 is formed between the two blocking portions 45, and the orthographic projection of the groove 200 on the substrate 101 is within the orthographic projection of the pixel boundary layer 40 and the boundary layer 47 on the substrate 101, as shown in FIG. 7g.

[0297] In an example embodiment, the orthographic projection of the boundary layer 47 on the substrate 101 does not overlap the orthographic projection of the first electrode on the substrate 101, as shown in FIG. 7g. In another embodiment, the orthographic projection of the boundary layer 47 on the substrate 101 partially overlaps the orthographic projection of the first electrode on the substrate 101, as shown in FIG. 8.

[0298] In an example embodiment, the barrier portion 45 includes a first top surface 41, a third bottom surface 49, and a first side surface 43 and a second side surface 44 connected between the first top surface 41 and the third bottom surface 49, the first top surface 41 being a surface of the barrier portion 45 on a side away from the substrate 101. The third bottom surface 49 is a surface of the barrier portion 45 on a side close to the substrate 101. The first side surface 43 and the second side surface 44 are located on opposite sides of the first top surface 41, and the first side surface 43 defines the trench 200. The second side surface 463 and the second side surface 44 define the pixel opening 100.

[0299] In an example embodiment, a width of a projection of the first top surface 41 on the substrate 101 is greater than a width of a projection of the third bottom surface 49 on the substrate 101. The width of the projection of the first top surface 41 on the substrate 101 refers to a dimension of a projection of the first top surface 41 on the substrate along the first direction D1, and the width of the projection of the third bottom surface 49 on the substrate 101 refers to a dimension of a projection of the third bottom surface 49 on the substrate 101 along the first direction D1.

[0300] In an example embodiment, a projection of the first top surface 41 on the substrate 101 covers a projection of the third bottom surface 49 on the substrate 101.

[0301] In an example embodiment, a projection of the first top surface 41 on the substrate 101 is within a range of a projection of the pixel defining layer 40 on the substrate 101.

[0302] In an example embodiment, the pixel defining layer 40 is not made of the same material as the barrier portion 45.

[0303] In an example embodiment, the defining layer 47 can be made of an organic material, for example, a negative resist.

[0304] In an example embodiment, the defining layer 47 can be a single-layer structure or a multi-layer structure.

[0305] In an example embodiment, the defining layer 47 can have a thickness of about to about For example, the defining layer 47 can have a thickness of about .

[0306] In an exemplary embodiment, the trench 200 has a first width W1 on the side away from the substrate 101 and a second width W2 on the side closer to the substrate 101. The first width W1 refers to the dimension of the trench 200 along a first direction D1 on the side away from the substrate 101. The second width W2 refers to the dimension of the trench 200 along the first direction D1 on the side closer to the substrate 101. The first width W1 is smaller than the second width W2, as shown in FIG. 7g. This results in different widths at both ends of the trench 200 along a direction perpendicular to the substrate 101 (third direction D3), i.e., the width of the trench 200 on the side away from the substrate 101 is smaller than the width of the trench 200 on the side closer to the substrate 101, giving the trench 200 a trapezoidal shape that is narrower at the top and wider at the bottom.

[0307] In an exemplary embodiment, referring to Figures 7g and 7i together, the first side surface 43 is inclined toward the trench 200 and can form a third included angle α3 with the substrate 101.

[0308] In an exemplary embodiment, referring together to Figures 7g and 7i, the second side 44 is inclined toward the pixel opening 100 and can form a fourth included angle α4 with the substrate 101.

[0309] In the exemplary embodiment, referring to Figures 7g and 7i together, the third included angle α3 and the fourth included angle α4 are not equal.

[0310] In an exemplary embodiment, the third included angle α3 can be approximately 90° to 130°. The third included angle α3 can be approximately 110°.

[0311] In an exemplary embodiment, the fourth included angle α4 can be approximately 90° to 130°. The fourth included angle α4 can be approximately 110°.

[0312] In an exemplary embodiment, the orthographic projection of the first conductive layer 51 on the substrate 101 is within the range of the orthographic projection of the trench 200 on the substrate 101.

[0313] In an exemplary embodiment, the distance between the isolation post 50 and the blocking portion 45 can be approximately to For example, the distance between the isolation post 50 and the blocking part 45 can be approximately about.

[0314] In an exemplary embodiment, the orthographic projection of the bottom of the trench 200 onto the substrate 101 covers the orthographic projection of the second surface 512 onto the substrate 101.

[0315] In an exemplary embodiment, the thickness of the first conductive layer 51 is greater than the trench depth of the trench 200.

[0316] In an example embodiment, the groove depth of the trench 200 can be about For example, the groove depth of the trench 200 can be about or about

[0317] In an example embodiment, the orthographic projection of the second conductive layer 52 on the substrate 101 covers the orthographic projection of the trench 200 on the substrate 101.

[0318] In an example embodiment, the orthographic projection of the third surface 521 on the substrate 101 covers the orthographic projection of the trench 200 on the substrate 101.

[0319] 2.7, forming a light-emitting functional layer and a second electrode.

[0320] In an example embodiment, forming a light-emitting functional layer and a second electrode can include: on the substrate 101 on which the pattern is formed, by a plating process, such as a thermal evaporation plating process, a magnetron sputtering, sequentially depositing a light-emitting functional layer material and a second electrode material, at least part of the light-emitting functional layer material is disposed on the surface of the first electrode away from the substrate 101, forming a light-emitting functional layer, the second electrode material is disposed on the surface of the light-emitting functional layer away from the substrate 101, and contacts the light-emitting functional layer, at least part of the second electrode material covers the side of the boundary layer 47 away from the substrate 101, at least part of the second electrode material covers the first side wall 513 of the first conductive layer 51, and is electrically connected with the first conductive layer 51, forming a second electrode, as shown in FIG. 7h. Wherein, the plurality of light-emitting functional layers can include a first light-emitting functional layer, a second light-emitting functional layer and a third light-emitting functional layer. The plurality of second electrodes can include a first color cathode 21, a second color cathode 22 and a third color cathode 23.

[0321] In an example embodiment, the orthographic projection of the light-emitting functional layer on the substrate 101 overlaps with the orthographic projection of the first electrode on the substrate 101, for example, the orthographic projection of the light-emitting functional layer on the substrate 101 covers the orthographic projection of the first electrode on the substrate 101, and the light-emitting functional layer directly contacts the first electrode.

[0322] In an example embodiment, the light-emitting functional layer can include two sub-light-emitting functional layers and a charge generation layer 31 (CGL) located between the two sub-light-emitting functional layers, and the sub-light-emitting functional layer can include a light-emitting layer (EML) and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL) and an electron injection layer (EIL).

[0323] ​In the embodiments of the present disclosure, the light-emitting functional layer can include a first sub-light-emitting functional layer disposed close to the substrate 101 and a second sub-light-emitting functional layer disposed away from the substrate 101, and a charge generation layer 31 located between the first sub-light-emitting functional layer and the second sub-light-emitting functional layer, so that the first electrode, the light-emitting functional layer and the second electrode can form a tandem OLED light-emitting device. The first sub-light-emitting functional layer can include a first light-emitting layer 32. The second sub-light-emitting functional layer can include a second light-emitting layer 33.

[0324] In the example embodiments, the preparation process of the light-emitting functional layer and the second electrode formed by the thermal evaporation coating process can include: sequentially spraying, by an evaporation source, the light-emitting functional layer material and the second electrode material to the substrate 101 with the aforementioned pattern, the light-emitting functional layer material being blocked by the isolation column 50 at the pixel defining layer 40, and the light-emitting functional layer material disposed on the first electrode forming the light-emitting functional layer; the second electrode material being continuous at the pixel defining layer 40 to achieve electrical connection with the first electrode layer.

[0325] In the example embodiments, the light-emitting functional layer material is blocked by the pixel defining layer 40 and the isolation column 50, avoiding the charge generation layer 31 (CGL) in the light-emitting functional layer from contacting the isolation column 50 and causing short circuit.

[0326] In the example embodiments, the orthogonal projection of the second electrode on the substrate 101 overlaps with the orthogonal projection of the first electrode, the light-emitting functional layer, the pixel defining layer 40, the defining layer 47, the first conductive layer 51 and the second conductive layer 52 on the substrate 101, respectively.

[0327] In the example embodiments, the orthogonal projection of the second electrode on the substrate 101 covers the orthogonal projection of the defining layer 47 on the substrate 101.

[0328] In the example embodiments, the orthogonal projection of the second electrode on the substrate 101 overlaps with the orthogonal projection of the first conductive layer 51, the first side surface 43, the second side surface 44 and the charge generation layer 31 (CGL) on the substrate 101, respectively.

[0329] In the example embodiments, the preparation method of the display substrate can simultaneously form the light-emitting functional layer and the second electrode of multiple sub-pixels emitting the same color through the same preparation process. For example, the preparation method of the display substrate can first simultaneously form the light-emitting functional layer and the second electrode of multiple first sub-pixels P1 through a first thermal evaporation coating process; then, simultaneously form the light-emitting functional layer and the second electrode of multiple second sub-pixels P2 through a second thermal evaporation coating process; and finally, simultaneously form the light-emitting functional layer and the second electrode of multiple third sub-pixels P3 through a third thermal evaporation coating process.

[0330] In an exemplary embodiment, the light emitting device of the sub-pixel can include a first electrode, a second electrode, and a light emitting functional layer disposed between the first electrode and the second electrode, and the light emitting functional layer can include a hole injection layer disposed on the first electrode, a first hole transport layer disposed on the hole injection layer, a first light emitting layer 32 disposed on the first hole transport layer, a first electron transport layer disposed on the first light emitting layer 32, a charge production layer 31 disposed on the first electron transport layer, a second hole transport layer disposed on the charge production layer 31, a second light emitting layer 33 disposed on the second hole transport layer, a second electron transport layer disposed on the second light emitting layer 33, and an electron injection layer disposed on the second electron transport layer.

[0331] In an exemplary embodiment, the second electrode covers the first top surface 41 and the second side surface 43 and the second side surface 44 on both sides of the first top surface 41.

[0332] In an exemplary embodiment, the second electrode covers the first top surface 41 and the second side surface 43 and the second side surface 44 on both sides of the first top surface 41.

[0333] In an exemplary embodiment, the first electrode, the light emitting functional layer, and the second electrode form a light emitting device of the sub-pixel.

[0334] In an exemplary embodiment, the preparation method of the display substrate of the present disclosure can simultaneously form the light emitting functional layer and the second electrode of the plurality of sub-pixels of the same color through the same preparation process. For example, the preparation method of the display substrate of the present disclosure can first simultaneously form the first light emitting functional layer and the first color cathode 21 of the plurality of first sub-pixels P1 through a first thermal evaporation film plating process; then, the second light emitting functional layer and the second color cathode 22 of the plurality of second sub-pixels P2 are formed through a second thermal evaporation film plating process; and finally, the third light emitting functional layer and the third color cathode 23 of the plurality of third sub-pixels P3 are formed through a third thermal evaporation film plating process. The first color electrode, the first light emitting functional layer, and the first color cathode 21 form a light emitting device of the first sub-pixel P1. The second color electrode, the second light emitting functional layer, and the second color cathode 22 form a light emitting device of the second sub-pixel P2. The third color electrode, the third light emitting functional layer, and the third color cathode 23 form a light emitting device of the third sub-pixel P3.

[0335] In an exemplary embodiment, the light emitting device of the sub-pixel can include a first color anode 11, a first color cathode 21, and a first light emitting functional layer disposed between the first color anode 11 and the first color cathode 21, the first light emitting functional layer can include a hole injection layer disposed on the first color anode 11, a first hole transport layer disposed on the hole injection layer, a first light emitting layer 32 disposed on the first hole transport layer, a first electron transport layer disposed on the first light emitting layer 32, a charge generation layer 31 disposed on the first electron transport layer, a second hole transport layer disposed on the charge generation layer 31, a second light emitting layer 33 disposed on the second hole transport layer, a second electron transport layer disposed on the second light emitting layer 33, and an electron injection layer disposed on the second electron transport layer.

[0336] 2.8, forming an encapsulation layer 60.

[0337] In an exemplary embodiment, forming the encapsulation layer 60 can include: covering an encapsulation thin film on the substrate 101 on which the aforementioned pattern is formed, and forming the encapsulation layer 60 covering the second electrode, as shown in FIGS. 6a and 6b.

[0338] In an exemplary embodiment, the encapsulation thin film can be formed by a chemical vapor deposition (CVD) process, or an atomic layer deposition (ALD) process.

[0339] On the other hand, the present disclosure also provides a manufacturing method of a display substrate, which can include:

[0340] forming a first electrode on a substrate 101;

[0341] forming a pixel definition layer 40 on a side of the first electrode away from the substrate 101, the pixel definition layer 40 defining a pixel opening 100 exposing at least part of the first electrode;

[0342] forming an isolation column 50 on a side of the pixel definition layer 40 away from the substrate 101;

[0343] forming a light emitting functional layer on a side of the first electrode away from the substrate 101, the light emitting functional layer being located within the pixel opening 100, the light emitting functional layer including at least one charge generation layer 31, the charge generation layer 31 being blocked by the isolation column 50 at the pixel definition layer 40; and

[0344] forming a second electrode on a side of the light emitting functional layer away from the substrate 101,

[0345] the second electrode being connected to the isolation column 50.

[0346] The display device can be any product or component with a display function, such as a mobile phone, a wearable device, an AR or VR display device, a vehicle-mounted display device, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, or the like, and the embodiments of the present application are not limited thereto.

[0347] Although the embodiments of the present disclosure are disclosed as above, the content described is only the embodiments adopted for the convenience of understanding the present disclosure, and is not intended to limit the present application. Any person skilled in the art can make any modification and change in the form and details without departing from the spirit and scope of the present disclosure, and the patent protection scope of the present application shall be subject to the scope defined by the appended claims.

Claims

1. A display substrate, comprising: a substrate substrate; a first electrode disposed on the substrate substrate; a pixel defining layer disposed on a side of the first electrode distal to the substrate substrate, the pixel defining layer defining a pixel opening exposing at least a portion of the first electrode; an isolation column disposed on a side of the pixel defining layer distal to the substrate substrate; a light emitting functional layer at least partially within the pixel opening, disposed on a side of the first electrode distal to the substrate substrate, the light emitting functional layer comprising at least one charge production layer, the charge production layer being separated from the isolation column at the pixel defining layer; and a second electrode disposed on a side of the light emitting functional layer distal to the substrate substrate and connected to the isolation column. A side of the pixel defining layer distal to the substrate substrate has a barrier portion proximate to the pixel opening. A side of the pixel defining layer distal to the substrate substrate is provided with a trench; the trench is located between the barrier portions; a projection of the trench on the substrate substrate is within a projection of the pixel defining layer on the substrate substrate. The trench has a first width on a side distal to the substrate substrate and a second width on a side proximate to the substrate substrate, the first width being greater than the second width. The isolation column comprises a first conductive layer and a second conductive layer, the first conductive layer being disposed between the second conductive layer and the substrate substrate; the first conductive layer is disposed on a bottom of the trench, a projection of the first conductive layer on the substrate substrate is within a projection of the trench on the substrate substrate; the second conductive layer and the pixel defining layer are spaced apart in a direction perpendicular to the substrate substrate. The first conductive layer and the second conductive layer are of different materials. The barrier portion comprises a first side and a second side; the first side defines the trench, and the second side defines the pixel opening together with the pixel defining layer. The first side is inclined away from the trench and forms a first included angle with the substrate substrate; the second side is inclined away from the pixel opening and forms a second included angle with the substrate substrate; wherein the first included angle is not equal to the second included angle. The first included angle is 30° to 60°; the second included angle is 60° to 90°. The first side is inclined toward the trench and forms a third included angle with the substrate substrate; the second side is inclined toward the pixel opening and forms a fourth included angle with the substrate substrate; wherein the third included angle is not equal to the fourth included angle. The third included angle is 90° to 130°; the fourth included angle is 90° to 130°. The pixel defining layer is of an inorganic material. The pixel defining layer and the barrier portion are of the same material. The pixel defining layer and the barrier portion are of different materials. The barrier portion is of an organic material. ​ ​ ​ ​ ​ ​ ​ 2.The display substrate of claim 1, wherein, ​ 3.The display substrate of claim 2, wherein, ​ ​ ​ 4.The display substrate of claim 3, wherein, ​ 5.The display substrate of claim 3, wherein, The groove has a groove depth of From The thickness of the pixel defining layer is To 6.The display substrate of claim 3, wherein, ​ ​ ​ ​ 7.The display substrate of claim 6, wherein, The spacing between the isolation column and the blocking portion is From 8.The display substrate of claim 6, wherein, ​ 9.The display substrate of claim 6, wherein, ​ ​ 10.The display substrate of claim 9, wherein, ​ ​ ​ 11.The display substrate of claim 10, wherein, ​ ​ 12.The display substrate of claim 9, wherein, ​ ​ ​ 13.The display substrate of claim 12, wherein, ​ ​ 14. The display substrate according to any one of claims 9 to 13, wherein, ​ 15.The display substrate of claim 14, wherein, ​ 16.The display substrate of claim 14, wherein, ​ 17.The display substrate of claim 16, wherein, ​ 18.The display substrate of claim 6, wherein, A normal projection of the second electrode on the substrate substrate overlaps with normal projections of the first electrode, the light emitting functional layer, the pixel defining layer, the first conductive layer and the second conductive layer on the substrate substrate respectively.

19. The display substrate of claim 9, wherein, A normal projection of the second electrode on the substrate substrate overlaps with normal projections of the first conductive layer, the first side, the second side and the charge production layer on the substrate substrate respectively. 20.The display substrate of claim 19, wherein, The second electrode covers the first side and the second side.

21. A display device comprising the display substrate according to any one of claims 1 to 20.

22. A method of manufacturing a display substrate, comprising: forming a first electrode on a substrate substrate; forming a pixel defining layer on a side of the first electrode distal to the substrate substrate, the pixel defining layer defining a pixel opening, the pixel opening exposing at least part of the one first electrode; forming an isolation column on a side of the pixel defining layer distal to the substrate substrate; forming a light emitting functional layer on a side of the first electrode distal to the substrate substrate, the light emitting functional layer being within the pixel opening, the light emitting functional layer comprising at least one charge production layer, the charge production layer being isolated from the isolation column at the pixel defining layer; and forming a second electrode on a side of the light emitting functional layer distal to the substrate substrate, the second electrode being connected to the isolation column. ​

Images